//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for Intel Silvermont to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// def SLMModel : SchedMachineModel { // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 // instructions per cycle. let IssueWidth = 2; let MicroOpBufferSize = 32; // Based on the reorder buffer. let LoadLatency = 3; let MispredictPenalty = 10; let PostRAScheduler = 1; // For small loops, expand by a small factor to hide the backedge cost. let LoopMicroOpBufferSize = 10; // FIXME: SSE4 is unimplemented. This flag is set to allow // the scheduler to assign a default model to unrecognized opcodes. let CompleteModel = 0; } let SchedModel = SLMModel in { // Silvermont has 5 reservation stations for micro-ops def IEC_RSV0 : ProcResource<1>; def IEC_RSV1 : ProcResource<1>; def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } def MEC_RSV : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. def IEC_RSV01 : ProcResGroup<[IEC_RSV0, IEC_RSV1]>; def FPC_RSV01 : ProcResGroup<[FPC_RSV0, FPC_RSV1]>; def SMDivider : ProcResource<1>; def SMFPMultiplier : ProcResource<1>; def SMFPDivider : ProcResource<1>; // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 // cycles after the memory operand. def : ReadAdvance; // Many SchedWrites are defined in pairs with and without a folded load. // Instructions with folded loads are usually micro-fused, so they only appear // as two micro-ops when queued in the reservation station. // This multiclass defines the resource usage for variants with and without // folded loads. multiclass SMWriteResPair { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; } // Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the // latency. def : WriteRes { let Latency = !add(Lat, 3); } } // A folded store needs a cycle on MEC_RSV for the store data, but it does not // need an extra port cycle to recompute the address. def : WriteRes; def : WriteRes; def : WriteRes { let Latency = 3; } def : WriteRes; def : WriteRes; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. def : WriteRes; // This is quite rough, latency depends on the dividend. def : WriteRes { let Latency = 25; let ResourceCycles = [1, 25]; } def : WriteRes { let Latency = 29; let ResourceCycles = [1, 1, 25]; } // Scalar and vector floating point. defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; // This is quite rough, latency depends on precision def : WriteRes { let Latency = 5; let ResourceCycles = [1, 2]; } def : WriteRes { let Latency = 8; let ResourceCycles = [1, 1, 2]; } def : WriteRes { let Latency = 34; let ResourceCycles = [1, 34]; } def : WriteRes { let Latency = 37; let ResourceCycles = [1, 1, 34]; } // Vector integer operations. defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; // String instructions. // Packed Compare Implicit Length Strings, Return Mask def : WriteRes { let Latency = 13; let ResourceCycles = [13]; } def : WriteRes { let Latency = 13; let ResourceCycles = [13, 1]; } // Packed Compare Explicit Length Strings, Return Mask def : WriteRes { let Latency = 17; let ResourceCycles = [17]; } def : WriteRes { let Latency = 17; let ResourceCycles = [17, 1]; } // Packed Compare Implicit Length Strings, Return Index def : WriteRes { let Latency = 17; let ResourceCycles = [17]; } def : WriteRes { let Latency = 17; let ResourceCycles = [17, 1]; } // Packed Compare Explicit Length Strings, Return Index def : WriteRes { let Latency = 21; let ResourceCycles = [21]; } def : WriteRes { let Latency = 21; let ResourceCycles = [21, 1]; } // AES Instructions. def : WriteRes { let Latency = 8; let ResourceCycles = [5]; } def : WriteRes { let Latency = 8; let ResourceCycles = [5, 1]; } def : WriteRes { let Latency = 8; let ResourceCycles = [5]; } def : WriteRes { let Latency = 8; let ResourceCycles = [5, 1]; } def : WriteRes { let Latency = 8; let ResourceCycles = [5]; } def : WriteRes { let Latency = 8; let ResourceCycles = [5, 1]; } // Carry-less multiplication instructions. def : WriteRes { let Latency = 10; let ResourceCycles = [10]; } def : WriteRes { let Latency = 10; let ResourceCycles = [10, 1]; } def : WriteRes { let Latency = 100; } def : WriteRes { let Latency = 100; } def : WriteRes; def : WriteRes; // AVX is not supported on that architecture, but we should define the basic // scheduling resources anyway. def : WriteRes; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; defm : SMWriteResPair; } // SchedModel