//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for AMD btver2 (Jaguar) to support // instruction scheduling and other instruction cost heuristics. Based off AMD Software // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix. // //===----------------------------------------------------------------------===// def BtVer2Model : SchedMachineModel { // All x86 instructions are modeled as a single micro-op, and btver2 can // decode 2 instructions per cycle. let IssueWidth = 2; let MicroOpBufferSize = 64; // Retire Control Unit let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency) let HighLatency = 25; let MispredictPenalty = 14; // Minimum branch misdirection penalty let PostRAScheduler = 1; // FIXME: SSE4/AVX is unimplemented. This flag is set to allow // the scheduler to assign a default model to unrecognized opcodes. let CompleteModel = 0; } let SchedModel = BtVer2Model in { // Jaguar can issue up to 6 micro-ops in one cycle def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam) def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA) def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM // Any pipe - FIXME we need this until we can discriminate between int/fpu load/store/moves properly def JAny : ProcResGroup<[JALU0, JALU1, JLAGU, JSAGU, JFPU0, JFPU1]>; // Integer Pipe Scheduler def JALU01 : ProcResGroup<[JALU0, JALU1]> { let BufferSize=20; } // AGU Pipe Scheduler def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> { let BufferSize=12; } // Fpu Pipe Scheduler def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> { let BufferSize=18; } def JDiv : ProcResource<1>; // integer division def JMul : ProcResource<1>; // integer multiplication def JVALU0 : ProcResource<1>; // vector integer def JVALU1 : ProcResource<1>; // vector integer def JVIMUL : ProcResource<1>; // vector integer multiplication def JSTC : ProcResource<1>; // vector store/convert def JFPM : ProcResource<1>; // FP multiplication def JFPA : ProcResource<1>; // FP addition // Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 // cycles after the memory operand. def : ReadAdvance; // Many SchedWrites are defined in pairs with and without a folded load. // Instructions with folded loads are usually micro-fused, so they only appear // as two micro-ops when dispatched by the schedulers. // This multiclass defines the resource usage for variants with and without // folded loads. multiclass JWriteResIntPair { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; } // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the // latency. def : WriteRes { let Latency = !add(Lat, 3); } } multiclass JWriteResFpuPair { // Register variant is using a single cycle on ExePort. def : WriteRes { let Latency = Lat; } // Memory variant also uses a cycle on JLAGU and adds 5 cycles to the // latency. def : WriteRes { let Latency = !add(Lat, 5); } } // A folded store needs a cycle on the SAGU for the store data. def : WriteRes; //////////////////////////////////////////////////////////////////////////////// // Arithmetic. //////////////////////////////////////////////////////////////////////////////// defm : JWriteResIntPair; defm : JWriteResIntPair; def : WriteRes { let Latency = 6; let ResourceCycles = [4]; } // FIXME 8/16 bit divisions def : WriteRes { let Latency = 25; let ResourceCycles = [1, 25]; } def : WriteRes { let Latency = 41; let ResourceCycles = [1, 1, 25]; } // This is for simple LEAs with one or two input operands. // FIXME: SAGU 3-operand LEA def : WriteRes; //////////////////////////////////////////////////////////////////////////////// // Integer shifts and rotates. //////////////////////////////////////////////////////////////////////////////// defm : JWriteResIntPair; //////////////////////////////////////////////////////////////////////////////// // Loads, stores, and moves, not folded with other operations. // FIXME: Split x86 and SSE load/store/moves //////////////////////////////////////////////////////////////////////////////// def : WriteRes { let Latency = 5; } def : WriteRes; def : WriteRes; //////////////////////////////////////////////////////////////////////////////// // Idioms that clear a register, like xorps %xmm0, %xmm0. // These can often bypass execution ports completely. //////////////////////////////////////////////////////////////////////////////// def : WriteRes; //////////////////////////////////////////////////////////////////////////////// // Branches don't produce values, so they have no latency, but they still // consume resources. Indirect branches can fold loads. //////////////////////////////////////////////////////////////////////////////// defm : JWriteResIntPair; //////////////////////////////////////////////////////////////////////////////// // Floating point. This covers both scalar and vector operations. // FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions? // FIXME: Double precision latencies // FIXME: SS vs PS latencies // FIXME: ymm latencies //////////////////////////////////////////////////////////////////////////////// defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; def : WriteRes { let Latency = 21; let ResourceCycles = [1, 1, 21]; } def : WriteRes { let Latency = 26; let ResourceCycles = [1, 1, 21]; } def : WriteRes { let Latency = 19; let ResourceCycles = [1, 1, 19]; } def : WriteRes { let Latency = 24; let ResourceCycles = [1, 1, 19]; } // FIXME: integer pipes defm : JWriteResFpuPair; // Float -> Integer. defm : JWriteResFpuPair; // Integer -> Float. defm : JWriteResFpuPair; // Float -> Float size conversion. def : WriteRes { let Latency = 2; let ResourceCycles = [2]; } def : WriteRes { let Latency = 7; let ResourceCycles = [1, 2]; } // Vector integer operations. defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; defm : JWriteResFpuPair; def : WriteRes { let Latency = 2; let ResourceCycles = [2]; } def : WriteRes { let Latency = 7; let ResourceCycles = [1, 2]; } // FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2? def : WriteRes { let Latency = 1; let ResourceCycles = [1]; } def : WriteRes { let Latency = 6; let ResourceCycles = [1, 1]; } def : WriteRes { let Latency = 3; let ResourceCycles = [2]; } def : WriteRes { let Latency = 8; let ResourceCycles = [1, 2]; } //////////////////////////////////////////////////////////////////////////////// // String instructions. // Packed Compare Implicit Length Strings, Return Mask // FIXME: approximate latencies + pipe dependencies //////////////////////////////////////////////////////////////////////////////// def : WriteRes { let Latency = 7; let ResourceCycles = [2]; } def : WriteRes { let Latency = 12; let ResourceCycles = [1, 2]; } // Packed Compare Explicit Length Strings, Return Mask def : WriteRes { let Latency = 13; let ResourceCycles = [5]; } def : WriteRes { let Latency = 18; let ResourceCycles = [1, 5]; } // Packed Compare Implicit Length Strings, Return Index def : WriteRes { let Latency = 6; let ResourceCycles = [2]; } def : WriteRes { let Latency = 11; let ResourceCycles = [1, 2]; } // Packed Compare Explicit Length Strings, Return Index def : WriteRes { let Latency = 13; let ResourceCycles = [5]; } def : WriteRes { let Latency = 18; let ResourceCycles = [1, 5]; } //////////////////////////////////////////////////////////////////////////////// // AES Instructions. //////////////////////////////////////////////////////////////////////////////// def : WriteRes { let Latency = 3; let ResourceCycles = [1, 1]; } def : WriteRes { let Latency = 8; let ResourceCycles = [1, 1, 1]; } def : WriteRes { let Latency = 2; let ResourceCycles = [1]; } def : WriteRes { let Latency = 7; let ResourceCycles = [1, 1]; } def : WriteRes { let Latency = 2; let ResourceCycles = [1]; } def : WriteRes { let Latency = 7; let ResourceCycles = [1, 1]; } //////////////////////////////////////////////////////////////////////////////// // Carry-less multiplication instructions. //////////////////////////////////////////////////////////////////////////////// def : WriteRes { let Latency = 2; let ResourceCycles = [1]; } def : WriteRes { let Latency = 7; let ResourceCycles = [1, 1]; } // FIXME: pipe for system/microcode? def : WriteRes { let Latency = 100; } def : WriteRes { let Latency = 100; } def : WriteRes; def : WriteRes; } // SchedModel