//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains instruction aliases for Sparc. //===----------------------------------------------------------------------===// // Instruction aliases for conditional moves. // mov rs2, rd multiclass cond_mov_alias { // mov (%icc|%xcc|%fcc0), rs2, rd def : InstAlias; // mov (%icc|%xcc|%fcc0), simm11, rd def : InstAlias; // fmovs (%icc|%xcc|%fcc0), $rs2, $rd def : InstAlias; // fmovd (%icc|%xcc|%fcc0), $rs2, $rd def : InstAlias; } // Instruction aliases for integer conditional branches and moves. multiclass int_cond_alias { // b $imm def : InstAlias; // b %xcc, $imm def : InstAlias, Requires<[Is64Bit]>; defm : cond_mov_alias, Requires<[HasV9]>; defm : cond_mov_alias, Requires<[Is64Bit]>; // fmovq (%icc|%xcc), $rs2, $rd def : InstAlias, Requires<[HasV9, HasHardQuad]>; def : InstAlias, Requires<[Is64Bit, HasHardQuad]>; } // Instruction aliases for floating point conditional branches and moves. multiclass fp_cond_alias { // fb $imm def : InstAlias; defm : cond_mov_alias, Requires<[HasV9]>; // fmovq %fcc0, $rs2, $rd def : InstAlias, Requires<[HasV9, HasHardQuad]>; } defm : int_cond_alias<"a", 0b1000>; defm : int_cond_alias<"n", 0b0000>; defm : int_cond_alias<"ne", 0b1001>; defm : int_cond_alias<"e", 0b0001>; defm : int_cond_alias<"g", 0b1010>; defm : int_cond_alias<"le", 0b0010>; defm : int_cond_alias<"ge", 0b1011>; defm : int_cond_alias<"l", 0b0011>; defm : int_cond_alias<"gu", 0b1100>; defm : int_cond_alias<"leu", 0b0100>; defm : int_cond_alias<"cc", 0b1101>; defm : int_cond_alias<"cs", 0b0101>; defm : int_cond_alias<"pos", 0b1110>; defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; defm : fp_cond_alias<"u", 0b0111>; defm : fp_cond_alias<"g", 0b0110>; defm : fp_cond_alias<"ug", 0b0101>; defm : fp_cond_alias<"l", 0b0100>; defm : fp_cond_alias<"ul", 0b0011>; defm : fp_cond_alias<"lg", 0b0010>; defm : fp_cond_alias<"ne", 0b0001>; defm : fp_cond_alias<"e", 0b1001>; defm : fp_cond_alias<"ue", 0b1010>; defm : fp_cond_alias<"ge", 0b1011>; defm : fp_cond_alias<"uge", 0b1100>; defm : fp_cond_alias<"le", 0b1101>; defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; // Instruction aliases for JMPL. // jmp addr -> jmpl addr, %g0 def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>; def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>; // call addr -> jmpl addr, %o7 def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>; def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>; // retl -> RETL 8 def : InstAlias<"retl", (RETL 8)>; // ret -> RET 8 def : InstAlias<"ret", (RET 8)>; // mov reg, rd -> or %g0, reg, rd def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; // mov simm13, rd -> or %g0, simm13, rd def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; // restore -> restore %g0, %g0, %g0 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>; def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>; def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>; def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;