1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_XD) ||
45 inheritsFrom(child, IC_XS));
47 return(inheritsFrom(child, IC_64BIT_REXW) ||
48 inheritsFrom(child, IC_64BIT_OPSIZE) ||
49 inheritsFrom(child, IC_64BIT_XD) ||
50 inheritsFrom(child, IC_64BIT_XS));
52 return inheritsFrom(child, IC_64BIT_OPSIZE);
54 return inheritsFrom(child, IC_64BIT_XD);
56 return inheritsFrom(child, IC_64BIT_XS);
58 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
60 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
62 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
63 inheritsFrom(child, IC_64BIT_REXW_XD) ||
64 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
66 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
68 return(inheritsFrom(child, IC_64BIT_REXW_XD));
70 return(inheritsFrom(child, IC_64BIT_REXW_XS));
71 case IC_64BIT_XD_OPSIZE:
72 case IC_64BIT_XS_OPSIZE:
74 case IC_64BIT_REXW_XD:
75 case IC_64BIT_REXW_XS:
76 case IC_64BIT_REXW_OPSIZE:
79 return inheritsFrom(child, IC_VEX_W) ||
80 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
82 return inheritsFrom(child, IC_VEX_W_XS) ||
83 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
85 return inheritsFrom(child, IC_VEX_W_XD) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
88 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
101 case IC_VEX_L_W_OPSIZE:
104 llvm_unreachable("Unknown instruction class");
108 /// outranks - Indicates whether, if an instruction has two different applicable
109 /// classes, which class should be preferred when performing decode. This
110 /// imposes a total ordering (ties are resolved toward "lower")
112 /// @param upper - The class that may be preferable
113 /// @param lower - The class that may be less preferable
114 /// @return - True if upper is to be preferred, false otherwise.
115 static inline bool outranks(InstructionContext upper,
116 InstructionContext lower) {
117 assert(upper < IC_max);
118 assert(lower < IC_max);
120 #define ENUM_ENTRY(n, r, d) r,
121 static int ranks[IC_max] = {
126 return (ranks[upper] > ranks[lower]);
129 /// stringForContext - Returns a string containing the name of a particular
130 /// InstructionContext, usually for diagnostic purposes.
132 /// @param insnContext - The instruction class to transform to a string.
133 /// @return - A statically-allocated string constant that contains the
134 /// name of the instruction class.
135 static inline const char* stringForContext(InstructionContext insnContext) {
136 switch (insnContext) {
138 llvm_unreachable("Unhandled instruction class");
139 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
145 /// stringForOperandType - Like stringForContext, but for OperandTypes.
146 static inline const char* stringForOperandType(OperandType type) {
149 llvm_unreachable("Unhandled type");
150 #define ENUM_ENTRY(i, d) case i: return #i;
156 /// stringForOperandEncoding - like stringForContext, but for
157 /// OperandEncodings.
158 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
161 llvm_unreachable("Unhandled encoding");
162 #define ENUM_ENTRY(i, d) case i: return #i;
168 void DisassemblerTables::emitOneID(raw_ostream &o,
171 bool addComma) const {
173 o.indent(i * 2) << format("0x%hx", id);
175 o.indent(i * 2) << 0;
183 o << InstructionSpecifiers[id].name;
189 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
190 /// all ModR/M decisions for instructions that are invalid for all possible
191 /// ModR/M byte values.
193 /// @param o - The output stream on which to emit the table.
194 /// @param i - The indentation level for that output stream.
195 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
197 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
200 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
201 /// be compacted by eliminating redundant information.
203 /// @param decision - The decision to be compacted.
204 /// @return - The compactest available representation for the decision.
205 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
207 bool satisfiesOneEntry = true;
208 bool satisfiesSplitRM = true;
209 bool satisfiesSplitReg = true;
213 for (index = 0; index < 256; ++index) {
214 if (decision.instructionIDs[index] != decision.instructionIDs[0])
215 satisfiesOneEntry = false;
217 if (((index & 0xc0) == 0xc0) &&
218 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
219 satisfiesSplitRM = false;
221 if (((index & 0xc0) != 0xc0) &&
222 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
223 satisfiesSplitRM = false;
225 if (((index & 0xc0) == 0xc0) &&
226 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
227 satisfiesSplitReg = false;
229 if (((index & 0xc0) != 0xc0) &&
230 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
231 satisfiesSplitReg = false;
234 if (satisfiesOneEntry)
235 return MODRM_ONEENTRY;
237 if (satisfiesSplitRM)
238 return MODRM_SPLITRM;
240 if (satisfiesSplitReg)
241 return MODRM_SPLITREG;
246 /// stringForDecisionType - Returns a statically-allocated string corresponding
247 /// to a particular decision type.
249 /// @param dt - The decision type.
250 /// @return - A pointer to the statically-allocated string (e.g.,
251 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
252 static const char* stringForDecisionType(ModRMDecisionType dt)
254 #define ENUM_ENTRY(n) case n: return #n;
257 llvm_unreachable("Unknown decision type");
263 /// stringForModifierType - Returns a statically-allocated string corresponding
264 /// to an opcode modifier type.
266 /// @param mt - The modifier type.
267 /// @return - A pointer to the statically-allocated string (e.g.,
268 /// "MODIFIER_NONE" for MODIFIER_NONE).
269 static const char* stringForModifierType(ModifierType mt)
271 #define ENUM_ENTRY(n) case n: return #n;
274 llvm_unreachable("Unknown modifier type");
280 DisassemblerTables::DisassemblerTables() {
283 for (i = 0; i < array_lengthof(Tables); i++) {
284 Tables[i] = new ContextDecision;
285 memset(Tables[i], 0, sizeof(ContextDecision));
288 HasConflicts = false;
291 DisassemblerTables::~DisassemblerTables() {
294 for (i = 0; i < array_lengthof(Tables); i++)
298 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
302 ModRMDecision &decision)
304 static uint64_t sTableNumber = 0;
305 static uint64_t sEntryNumber = 1;
306 ModRMDecisionType dt = getDecisionType(decision);
309 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
311 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
314 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
315 o2.indent(i2) << 0 << " /* EmptyTable */\n";
318 o2.indent(i2) << "}";
322 o1 << "/* Table" << sTableNumber << " */\n";
327 llvm_unreachable("Unknown decision type");
329 emitOneID(o1, i1, decision.instructionIDs[0], true);
332 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
333 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
336 for (index = 0; index < 64; index += 8)
337 emitOneID(o1, i1, decision.instructionIDs[index], true);
338 for (index = 0xc0; index < 256; index += 8)
339 emitOneID(o1, i1, decision.instructionIDs[index], true);
342 for (index = 0; index < 256; ++index)
343 emitOneID(o1, i1, decision.instructionIDs[index], true);
349 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
352 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
353 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
356 o2.indent(i2) << "}";
360 llvm_unreachable("Unknown decision type");
378 void DisassemblerTables::emitOpcodeDecision(
383 OpcodeDecision &decision) const {
386 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
388 o2.indent(i2) << "{" << "\n";
391 for (index = 0; index < 256; ++index) {
394 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
396 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
405 o2.indent(i2) << "}" << "\n";
407 o2.indent(i2) << "}" << "\n";
410 void DisassemblerTables::emitContextDecision(
415 ContextDecision &decision,
416 const char* name) const {
417 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
419 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
424 for (index = 0; index < IC_max; ++index) {
425 o2.indent(i2) << "/* ";
426 o2 << stringForContext((InstructionContext)index);
430 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
432 if (index + 1 < IC_max)
437 o2.indent(i2) << "}" << "\n";
439 o2.indent(i2) << "};" << "\n";
442 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
444 o.indent(i * 2) << "static const struct InstructionSpecifier ";
445 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
449 uint16_t numInstructions = InstructionSpecifiers.size();
450 uint16_t index, operandIndex;
452 for (index = 0; index < numInstructions; ++index) {
453 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
457 stringForModifierType(InstructionSpecifiers[index].modifierType);
460 o.indent(i * 2) << "0x";
461 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
464 o.indent(i * 2) << "{" << "\n";
467 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
468 o.indent(i * 2) << "{ ";
469 o << stringForOperandEncoding(InstructionSpecifiers[index]
470 .operands[operandIndex]
473 o << stringForOperandType(InstructionSpecifiers[index]
474 .operands[operandIndex]
478 if (operandIndex < X86_MAX_OPERANDS - 1)
485 o.indent(i * 2) << "}," << "\n";
487 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
491 o.indent(i * 2) << "}";
493 if (index + 1 < numInstructions)
500 o.indent(i * 2) << "};" << "\n";
503 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
506 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
510 for (index = 0; index < 256; ++index) {
513 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
514 o << "IC_VEX_L_W_OPSIZE";
515 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
516 o << "IC_VEX_L_OPSIZE";
517 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
519 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
521 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
522 o << "IC_VEX_W_OPSIZE";
523 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
525 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
527 else if (index & ATTR_VEXL)
529 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
531 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
532 o << "IC_VEX_OPSIZE";
533 else if ((index & ATTR_VEX) && (index & ATTR_XD))
535 else if ((index & ATTR_VEX) && (index & ATTR_XS))
537 else if (index & ATTR_VEX)
539 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
540 o << "IC_64BIT_REXW_XS";
541 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
542 o << "IC_64BIT_REXW_XD";
543 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
544 (index & ATTR_OPSIZE))
545 o << "IC_64BIT_REXW_OPSIZE";
546 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
547 o << "IC_64BIT_XD_OPSIZE";
548 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
549 o << "IC_64BIT_XS_OPSIZE";
550 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
552 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
554 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
555 o << "IC_64BIT_OPSIZE";
556 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
557 o << "IC_64BIT_REXW";
558 else if ((index & ATTR_64BIT))
560 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
562 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
564 else if (index & ATTR_XS)
566 else if (index & ATTR_XD)
568 else if (index & ATTR_OPSIZE)
578 o << " /* " << index << " */";
584 o.indent(i * 2) << "};" << "\n";
587 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
592 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
593 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
594 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
595 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
596 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
597 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
600 void DisassemblerTables::emit(raw_ostream &o) const {
607 raw_string_ostream o1(s1);
608 raw_string_ostream o2(s2);
610 emitInstructionInfo(o, i2);
613 emitContextTable(o, i2);
616 o << "static const InstrUID modRMTable[] = {\n";
618 emitEmptyTable(o1, i1);
620 emitContextDecisions(o1, o2, i1, i2);
631 void DisassemblerTables::setTableFields(ModRMDecision &decision,
632 const ModRMFilter &filter,
637 for (index = 0; index < 256; ++index) {
638 if (filter.accepts(index)) {
639 if (decision.instructionIDs[index] == uid)
642 if (decision.instructionIDs[index] != 0) {
643 InstructionSpecifier &newInfo =
644 InstructionSpecifiers[uid];
645 InstructionSpecifier &previousInfo =
646 InstructionSpecifiers[decision.instructionIDs[index]];
649 continue; // filtered instructions get lowest priority
651 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
652 newInfo.name == "XCHG32ar" ||
653 newInfo.name == "XCHG32ar64" ||
654 newInfo.name == "XCHG64ar"))
655 continue; // special case for XCHG*ar and NOOP
657 if (outranks(previousInfo.insnContext, newInfo.insnContext))
660 if (previousInfo.insnContext == newInfo.insnContext &&
661 !previousInfo.filtered) {
662 errs() << "Error: Primary decode conflict: ";
663 errs() << newInfo.name << " would overwrite " << previousInfo.name;
665 errs() << "ModRM " << index << "\n";
666 errs() << "Opcode " << (uint16_t)opcode << "\n";
667 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
672 decision.instructionIDs[index] = uid;
677 void DisassemblerTables::setTableFields(OpcodeType type,
678 InstructionContext insnContext,
680 const ModRMFilter &filter,
686 ContextDecision &decision = *Tables[type];
688 for (index = 0; index < IC_max; ++index) {
689 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
692 if (inheritsFrom((InstructionContext)index,
693 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
694 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],