1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o,
57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::vector<CodeGenRegister*> &Regs,
61 void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
63 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
64 const std::string &ClassName);
65 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
66 const std::string &ClassName);
68 } // End anonymous namespace
70 // runEnums - Print out enum values for all of the registers.
71 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
72 CodeGenTarget &Target, CodeGenRegBank &Bank) {
73 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
75 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
78 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
80 emitSourceFileHeader("Target Register Enum Values", OS);
82 OS << "\n#ifdef GET_REGINFO_ENUM\n";
83 OS << "#undef GET_REGINFO_ENUM\n";
85 OS << "namespace llvm {\n\n";
87 OS << "class MCRegisterClass;\n"
88 << "extern const MCRegisterClass " << Namespace
89 << "MCRegisterClasses[];\n\n";
91 if (!Namespace.empty())
92 OS << "namespace " << Namespace << " {\n";
93 OS << "enum {\n NoRegister,\n";
95 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
96 OS << " " << Registers[i]->getName() << " = " <<
97 Registers[i]->EnumValue << ",\n";
98 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
99 "Register enum value mismatch!");
100 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
102 if (!Namespace.empty())
105 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
106 if (!RegisterClasses.empty()) {
108 // RegisterClass enums are stored as uint16_t in the tables.
109 assert(RegisterClasses.size() <= 0xffff &&
110 "Too many register classes to fit in tables");
112 OS << "\n// Register classes\n";
113 if (!Namespace.empty())
114 OS << "namespace " << Namespace << " {\n";
116 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
118 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
122 if (!Namespace.empty())
126 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
127 // If the only definition is the default NoRegAltName, we don't need to
129 if (RegAltNameIndices.size() > 1) {
130 OS << "\n// Register alternate name indices\n";
131 if (!Namespace.empty())
132 OS << "namespace " << Namespace << " {\n";
134 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
135 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
136 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
138 if (!Namespace.empty())
142 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
143 if (!SubRegIndices.empty()) {
144 OS << "\n// Subregister indices\n";
145 std::string Namespace =
146 SubRegIndices[0]->getNamespace();
147 if (!Namespace.empty())
148 OS << "namespace " << Namespace << " {\n";
149 OS << "enum {\n NoSubRegister,\n";
150 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
151 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
152 OS << " NUM_TARGET_SUBREGS\n};\n";
153 if (!Namespace.empty())
157 OS << "} // End llvm namespace \n";
158 OS << "#endif // GET_REGINFO_ENUM\n\n";
161 void RegisterInfoEmitter::
162 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
163 const std::string &ClassName) {
164 unsigned NumRCs = RegBank.getRegClasses().size();
165 unsigned NumSets = RegBank.getNumRegPressureSets();
167 OS << "/// Get the weight in units of pressure for this register class.\n"
168 << "const RegClassWeight &" << ClassName << "::\n"
169 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
170 << " static const RegClassWeight RCWeightTable[] = {\n";
171 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
173 const CodeGenRegister::Set &Regs = RC.getMembers();
177 std::vector<unsigned> RegUnits;
178 RC.buildRegUnitSet(RegUnits);
179 OS << " {" << (*Regs.begin())->getWeight(RegBank)
180 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
182 OS << "}, \t// " << RC.getName() << "\n";
185 << " return RCWeightTable[RC->getID()];\n"
188 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
189 // bother generating a table.
190 bool RegUnitsHaveUnitWeight = true;
191 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
192 UnitIdx < UnitEnd; ++UnitIdx) {
193 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
194 RegUnitsHaveUnitWeight = false;
196 OS << "/// Get the weight in units of pressure for this register unit.\n"
197 << "unsigned " << ClassName << "::\n"
198 << "getRegUnitWeight(unsigned RegUnit) const {\n"
199 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
200 << " && \"invalid register unit\");\n";
201 if (!RegUnitsHaveUnitWeight) {
202 OS << " static const uint8_t RUWeightTable[] = {\n ";
203 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
204 UnitIdx < UnitEnd; ++UnitIdx) {
205 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
206 assert(RU.Weight < 256 && "RegUnit too heavy");
207 OS << RU.Weight << ", ";
210 << " return RUWeightTable[RegUnit];\n";
213 OS << " // All register units have unit weight.\n"
219 << "// Get the number of dimensions of register pressure.\n"
220 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
221 << " return " << NumSets << ";\n}\n\n";
223 OS << "// Get the name of this register unit pressure set.\n"
224 << "const char *" << ClassName << "::\n"
225 << "getRegPressureSetName(unsigned Idx) const {\n"
226 << " static const char *PressureNameTable[] = {\n";
227 for (unsigned i = 0; i < NumSets; ++i ) {
228 OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
231 << " return PressureNameTable[Idx];\n"
234 OS << "// Get the register unit pressure limit for this dimension.\n"
235 << "// This limit must be adjusted dynamically for reserved registers.\n"
236 << "unsigned " << ClassName << "::\n"
237 << "getRegPressureSetLimit(unsigned Idx) const {\n"
238 << " static const unsigned PressureLimitTable[] = {\n";
239 for (unsigned i = 0; i < NumSets; ++i ) {
240 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
241 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
242 << ", \t// " << i << ": " << RegUnits.Name << "\n";
245 << " return PressureLimitTable[Idx];\n"
248 // This table may be larger than NumRCs if some register units needed a list
249 // of unit sets that did not correspond to a register class.
250 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
251 OS << "/// Table of pressure sets per register class or unit.\n"
252 << "static const int RCSetsTable[] = {\n ";
253 std::vector<unsigned> RCSetStarts(NumRCUnitSets);
254 for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) {
255 RCSetStarts[i] = StartIdx;
256 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
257 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
258 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
259 OS << *PSetI << ", ";
262 OS << "-1, \t// #" << RCSetStarts[i] << " ";
264 OS << RegBank.getRegClasses()[i]->getName();
267 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
268 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
269 OS << "~" << RegBank.getRegPressureSet(*PSetI).Name;
277 OS << "/// Get the dimensions of register pressure impacted by this "
278 << "register class.\n"
279 << "/// Returns a -1 terminated array of pressure set IDs\n"
280 << "const int* " << ClassName << "::\n"
281 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
282 OS << " static const unsigned RCSetStartTable[] = {\n ";
283 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
284 OS << RCSetStarts[i] << ",";
287 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
288 << " return &RCSetsTable[SetListStart];\n"
291 OS << "/// Get the dimensions of register pressure impacted by this "
292 << "register unit.\n"
293 << "/// Returns a -1 terminated array of pressure set IDs\n"
294 << "const int* " << ClassName << "::\n"
295 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
296 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
297 << " && \"invalid register unit\");\n";
298 OS << " static const unsigned RUSetStartTable[] = {\n ";
299 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
300 UnitIdx < UnitEnd; ++UnitIdx) {
301 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ",";
304 << " unsigned SetListStart = RUSetStartTable[RegUnit];\n"
305 << " return &RCSetsTable[SetListStart];\n"
310 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
311 const std::vector<CodeGenRegister*> &Regs,
313 // Collect all information about dwarf register numbers
314 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
315 DwarfRegNumsMapTy DwarfRegNums;
317 // First, just pull all provided information to the map
318 unsigned maxLength = 0;
319 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
320 Record *Reg = Regs[i]->TheDef;
321 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
322 maxLength = std::max((size_t)maxLength, RegNums.size());
323 if (DwarfRegNums.count(Reg))
324 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
325 getQualifiedName(Reg) + "specified multiple times");
326 DwarfRegNums[Reg] = RegNums;
332 // Now we know maximal length of number list. Append -1's, where needed
333 for (DwarfRegNumsMapTy::iterator
334 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
335 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
336 I->second.push_back(-1);
338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
340 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
342 // Emit reverse information about the dwarf register numbers.
343 for (unsigned j = 0; j < 2; ++j) {
344 for (unsigned i = 0, e = maxLength; i != e; ++i) {
345 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
346 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
347 OS << i << "Dwarf2L[]";
352 // Store the mapping sorted by the LLVM reg num so lookup can be done
353 // with a binary search.
354 std::map<uint64_t, Record*> Dwarf2LMap;
355 for (DwarfRegNumsMapTy::iterator
356 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
357 int DwarfRegNo = I->second[i];
360 Dwarf2LMap[DwarfRegNo] = I->first;
363 for (std::map<uint64_t, Record*>::iterator
364 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
365 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
373 // We have to store the size in a const global, it's used in multiple
375 OS << "extern const unsigned " << Namespace
376 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
378 OS << " = sizeof(" << Namespace
379 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
380 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
386 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
387 Record *Reg = Regs[i]->TheDef;
388 const RecordVal *V = Reg->getValue("DwarfAlias");
389 if (!V || !V->getValue())
392 DefInit *DI = cast<DefInit>(V->getValue());
393 Record *Alias = DI->getDef();
394 DwarfRegNums[Reg] = DwarfRegNums[Alias];
397 // Emit information about the dwarf register numbers.
398 for (unsigned j = 0; j < 2; ++j) {
399 for (unsigned i = 0, e = maxLength; i != e; ++i) {
400 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
401 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
402 OS << i << "L2Dwarf[]";
405 // Store the mapping sorted by the Dwarf reg num so lookup can be done
406 // with a binary search.
407 for (DwarfRegNumsMapTy::iterator
408 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
409 int RegNo = I->second[i];
410 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
413 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
421 // We have to store the size in a const global, it's used in multiple
423 OS << "extern const unsigned " << Namespace
424 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
426 OS << " = sizeof(" << Namespace
427 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
428 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
436 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
437 const std::vector<CodeGenRegister*> &Regs,
439 // Emit the initializer so the tables from EmitRegMappingTables get wired up
440 // to the MCRegisterInfo object.
441 unsigned maxLength = 0;
442 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
443 Record *Reg = Regs[i]->TheDef;
444 maxLength = std::max((size_t)maxLength,
445 Reg->getValueAsListOfInts("DwarfNumbers").size());
451 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
453 // Emit reverse information about the dwarf register numbers.
454 for (unsigned j = 0; j < 2; ++j) {
457 OS << "DwarfFlavour";
462 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
464 for (unsigned i = 0, e = maxLength; i != e; ++i) {
465 OS << " case " << i << ":\n";
470 raw_string_ostream(Tmp) << Namespace
471 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
473 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
484 // Emit information about the dwarf register numbers.
485 for (unsigned j = 0; j < 2; ++j) {
488 OS << "DwarfFlavour";
493 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
495 for (unsigned i = 0, e = maxLength; i != e; ++i) {
496 OS << " case " << i << ":\n";
501 raw_string_ostream(Tmp) << Namespace
502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
504 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
516 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
517 // Width is the number of bits per hex number.
518 static void printBitVectorAsHex(raw_ostream &OS,
519 const BitVector &Bits,
521 assert(Width <= 32 && "Width too large");
522 unsigned Digits = (Width + 3) / 4;
523 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
525 for (unsigned j = 0; j != Width && i + j != e; ++j)
526 Value |= Bits.test(i + j) << j;
527 OS << format("0x%0*x, ", Digits, Value);
531 // Helper to emit a set of bits into a constant byte array.
532 class BitVectorEmitter {
535 void add(unsigned v) {
536 if (v >= Values.size())
537 Values.resize(((v/8)+1)*8); // Round up to the next byte.
541 void print(raw_ostream &OS) {
542 printBitVectorAsHex(OS, Values, 8);
546 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
547 OS << getEnumName(VT);
550 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
551 OS << Idx->EnumValue;
554 // Differentially encoded register and regunit lists allow for better
555 // compression on regular register banks. The sequence is computed from the
556 // differential list as:
559 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
561 // The initial value depends on the specific list. The list is terminated by a
562 // 0 differential which means we can't encode repeated elements.
564 typedef SmallVector<uint16_t, 4> DiffVec;
566 // Differentially encode a sequence of numbers into V. The starting value and
567 // terminating 0 are not added to V, so it will have the same size as List.
569 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
570 assert(V.empty() && "Clear DiffVec before diffEncode.");
571 uint16_t Val = uint16_t(InitVal);
572 for (unsigned i = 0; i != List.size(); ++i) {
573 uint16_t Cur = List[i];
574 V.push_back(Cur - Val);
580 template<typename Iter>
582 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
583 assert(V.empty() && "Clear DiffVec before diffEncode.");
584 uint16_t Val = uint16_t(InitVal);
585 for (Iter I = Begin; I != End; ++I) {
586 uint16_t Cur = (*I)->EnumValue;
587 V.push_back(Cur - Val);
593 static void printDiff16(raw_ostream &OS, uint16_t Val) {
597 // Try to combine Idx's compose map into Vec if it is compatible.
598 // Return false if it's not possible.
599 static bool combine(const CodeGenSubRegIndex *Idx,
600 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
601 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
602 for (CodeGenSubRegIndex::CompMap::const_iterator
603 I = Map.begin(), E = Map.end(); I != E; ++I) {
604 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
605 if (Entry && Entry != I->second)
609 // All entries are compatible. Make it so.
610 for (CodeGenSubRegIndex::CompMap::const_iterator
611 I = Map.begin(), E = Map.end(); I != E; ++I)
612 Vec[I->first->EnumValue - 1] = I->second;
616 static const char *getMinimalTypeForRange(uint64_t Range) {
617 assert(Range < 0xFFFFFFFFULL && "Enum too large");
626 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
627 CodeGenRegBank &RegBank,
628 const std::string &ClName) {
629 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
630 OS << "unsigned " << ClName
631 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
633 // Many sub-register indexes are composition-compatible, meaning that
635 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
637 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
638 // The illegal entries can be use as wildcards to compress the table further.
640 // Map each Sub-register index to a compatible table row.
641 SmallVector<unsigned, 4> RowMap;
642 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
644 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
645 unsigned Found = ~0u;
646 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
647 if (combine(SubRegIndices[i], Rows[r])) {
654 Rows.resize(Found + 1);
655 Rows.back().resize(SubRegIndices.size());
656 combine(SubRegIndices[i], Rows.back());
658 RowMap.push_back(Found);
661 // Output the row map if there is multiple rows.
662 if (Rows.size() > 1) {
663 OS << " static const " << getMinimalTypeForRange(Rows.size())
664 << " RowMap[" << SubRegIndices.size() << "] = {\n ";
665 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
666 OS << RowMap[i] << ", ";
671 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1)
672 << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n";
673 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
675 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
677 OS << Rows[r][i]->EnumValue << ", ";
684 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n"
685 << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n";
687 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
689 OS << " return Rows[0][IdxB];\n";
694 // runMCDesc - Print out MC register descriptions.
697 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
698 CodeGenRegBank &RegBank) {
699 emitSourceFileHeader("MC Register Information", OS);
701 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
702 OS << "#undef GET_REGINFO_MC_DESC\n";
704 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
706 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
707 // The lists of sub-registers and super-registers go in the same array. That
708 // allows us to share suffixes.
709 typedef std::vector<const CodeGenRegister*> RegVec;
711 // Differentially encoded lists.
712 SequenceToOffsetTable<DiffVec> DiffSeqs;
713 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
714 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
715 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
716 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
718 // Keep track of sub-register names as well. These are not differentially
720 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
721 SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs;
722 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
724 SequenceToOffsetTable<std::string> RegStrings;
726 // Precompute register lists for the SequenceToOffsetTable.
727 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
728 const CodeGenRegister *Reg = Regs[i];
730 RegStrings.add(Reg->getName());
732 // Compute the ordered sub-register list.
733 SetVector<const CodeGenRegister*> SR;
734 Reg->addSubRegsPreOrder(SR, RegBank);
735 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
736 DiffSeqs.add(SubRegLists[i]);
738 // Compute the corresponding sub-register indexes.
739 SubRegIdxVec &SRIs = SubRegIdxLists[i];
740 for (unsigned j = 0, je = SR.size(); j != je; ++j)
741 SRIs.push_back(Reg->getSubRegIndex(SR[j]));
742 SubRegIdxSeqs.add(SRIs);
744 // Super-registers are already computed.
745 const RegVec &SuperRegList = Reg->getSuperRegs();
746 diffEncode(SuperRegLists[i], Reg->EnumValue,
747 SuperRegList.begin(), SuperRegList.end());
748 DiffSeqs.add(SuperRegLists[i]);
750 // Differentially encode the register unit list, seeded by register number.
751 // First compute a scale factor that allows more diff-lists to be reused:
756 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
757 // value for the differential decoder is the register number multiplied by
760 // Check the neighboring registers for arithmetic progressions.
761 unsigned ScaleA = ~0u, ScaleB = ~0u;
762 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
763 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
764 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
765 if (i+1 != Regs.size() &&
766 Regs[i+1]->getNativeRegUnits().size() == RUs.size())
767 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
768 unsigned Scale = std::min(ScaleB, ScaleA);
769 // Default the scale to 0 if it can't be encoded in 4 bits.
772 RegUnitInitScale[i] = Scale;
773 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
776 // Compute the final layout of the sequence table.
778 SubRegIdxSeqs.layout();
780 OS << "namespace llvm {\n\n";
782 const std::string &TargetName = Target.getName();
784 // Emit the shared table of differential lists.
785 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
786 DiffSeqs.emit(OS, printDiff16);
789 // Emit the table of sub-register indexes.
790 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
791 SubRegIdxSeqs.emit(OS, printSubRegIndex);
794 // Emit the table of sub-register index sizes.
795 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
796 << TargetName << "SubRegIdxRanges[] = {\n";
797 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
798 for (ArrayRef<CodeGenSubRegIndex*>::const_iterator
799 SRI = SubRegIndices.begin(), SRE = SubRegIndices.end();
801 OS << " { " << (*SRI)->getOffset() << ", "
803 << " },\t// " << (*SRI)->getName() << "\n";
807 // Emit the string table.
809 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
810 RegStrings.emit(OS, printChar);
813 OS << "extern const MCRegisterDesc " << TargetName
814 << "RegDesc[] = { // Descriptors\n";
815 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
817 // Emit the register descriptors now.
818 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
819 const CodeGenRegister *Reg = Regs[i];
820 OS << " { " << RegStrings.get(Reg->getName()) << ", "
821 << DiffSeqs.get(SubRegLists[i]) << ", "
822 << DiffSeqs.get(SuperRegLists[i]) << ", "
823 << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
824 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
826 OS << "};\n\n"; // End of register descriptors...
828 // Emit the table of register unit roots. Each regunit has one or two root
830 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
831 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
832 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
833 assert(!Roots.empty() && "All regunits must have a root register.");
834 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
835 OS << " { " << getQualifiedName(Roots.front()->TheDef);
836 for (unsigned r = 1; r != Roots.size(); ++r)
837 OS << ", " << getQualifiedName(Roots[r]->TheDef);
842 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
844 // Loop over all of the register classes... emitting each one.
845 OS << "namespace { // Register classes...\n";
847 // Emit the register enum value arrays for each RegisterClass
848 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
849 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
850 ArrayRef<Record*> Order = RC.getOrder();
852 // Give the register class a legal C name if it's anonymous.
853 std::string Name = RC.getName();
855 // Emit the register list now.
856 OS << " // " << Name << " Register Class...\n"
857 << " const uint16_t " << Name
859 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
860 Record *Reg = Order[i];
861 OS << getQualifiedName(Reg) << ", ";
865 OS << " // " << Name << " Bit set.\n"
866 << " const uint8_t " << Name
868 BitVectorEmitter BVE;
869 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
870 Record *Reg = Order[i];
871 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
879 OS << "extern const MCRegisterClass " << TargetName
880 << "MCRegisterClasses[] = {\n";
882 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
883 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
885 // Asserts to make sure values will fit in table assuming types from
887 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
888 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
889 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
891 OS << " { " << '\"' << RC.getName() << "\", "
892 << RC.getName() << ", " << RC.getName() << "Bits, "
893 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
894 << RC.getQualifiedName() + "RegClassID" << ", "
895 << RC.SpillSize/8 << ", "
896 << RC.SpillAlignment/8 << ", "
897 << RC.CopyCost << ", "
898 << RC.Allocatable << " },\n";
903 EmitRegMappingTables(OS, Regs, false);
905 // Emit Reg encoding table
906 OS << "extern const uint16_t " << TargetName;
907 OS << "RegEncodingTable[] = {\n";
908 // Add entry for NoRegister
910 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
911 Record *Reg = Regs[i]->TheDef;
912 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
914 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
915 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
916 Value |= (uint64_t)B->getValue() << b;
918 OS << " " << Value << ",\n";
920 OS << "};\n"; // End of HW encoding table
922 // MCRegisterInfo initialization routine.
923 OS << "static inline void Init" << TargetName
924 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
925 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n"
926 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
927 << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
928 << RegisterClasses.size() << ", "
929 << TargetName << "RegUnitRoots, "
930 << RegBank.getNumNativeRegUnits() << ", "
931 << TargetName << "RegDiffLists, "
932 << TargetName << "RegStrings, "
933 << TargetName << "SubRegIdxLists, "
934 << (SubRegIndices.size() + 1) << ",\n"
935 << TargetName << "SubRegIdxRanges, "
936 << " " << TargetName << "RegEncodingTable);\n\n";
938 EmitRegMapping(OS, Regs, false);
942 OS << "} // End llvm namespace \n";
943 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
947 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
948 CodeGenRegBank &RegBank) {
949 emitSourceFileHeader("Register Information Header Fragment", OS);
951 OS << "\n#ifdef GET_REGINFO_HEADER\n";
952 OS << "#undef GET_REGINFO_HEADER\n";
954 const std::string &TargetName = Target.getName();
955 std::string ClassName = TargetName + "GenRegisterInfo";
957 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
959 OS << "namespace llvm {\n\n";
961 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
962 << " explicit " << ClassName
963 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
964 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
965 << " { return false; }\n";
966 if (!RegBank.getSubRegIndices().empty()) {
967 OS << " virtual unsigned composeSubRegIndicesImpl"
968 << "(unsigned, unsigned) const;\n"
969 << " virtual const TargetRegisterClass *"
970 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
972 OS << " virtual const RegClassWeight &getRegClassWeight("
973 << "const TargetRegisterClass *RC) const;\n"
974 << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n"
975 << " virtual unsigned getNumRegPressureSets() const;\n"
976 << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n"
977 << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
978 << " virtual const int *getRegClassPressureSets("
979 << "const TargetRegisterClass *RC) const;\n"
980 << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n"
983 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
985 if (!RegisterClasses.empty()) {
986 OS << "namespace " << RegisterClasses[0]->Namespace
987 << " { // Register classes\n";
989 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
990 const CodeGenRegisterClass &RC = *RegisterClasses[i];
991 const std::string &Name = RC.getName();
993 // Output the extern for the instance.
994 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
996 OS << "} // end of namespace " << TargetName << "\n\n";
998 OS << "} // End llvm namespace \n";
999 OS << "#endif // GET_REGINFO_HEADER\n\n";
1003 // runTargetDesc - Output the target register and register file descriptions.
1006 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1007 CodeGenRegBank &RegBank){
1008 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1010 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1011 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1013 OS << "namespace llvm {\n\n";
1015 // Get access to MCRegisterClass data.
1016 OS << "extern const MCRegisterClass " << Target.getName()
1017 << "MCRegisterClasses[];\n";
1019 // Start out by emitting each of the register classes.
1020 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1021 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
1023 // Collect all registers belonging to any allocatable class.
1024 std::set<Record*> AllocatableRegs;
1026 // Collect allocatable registers.
1027 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1028 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1029 ArrayRef<Record*> Order = RC.getOrder();
1032 AllocatableRegs.insert(Order.begin(), Order.end());
1035 // Build a shared array of value types.
1036 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1037 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
1038 VTSeqs.add(RegisterClasses[rc]->VTs);
1040 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1041 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1044 // Emit SubRegIndex names, skipping 0.
1045 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1046 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1047 OS << SubRegIndices[i]->getName();
1053 // Emit SubRegIndex lane masks, including 0.
1054 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1055 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1056 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask)
1057 << SubRegIndices[i]->getName() << '\n';
1063 // Now that all of the structs have been emitted, emit the instances.
1064 if (!RegisterClasses.empty()) {
1065 OS << "\nstatic const TargetRegisterClass *const "
1066 << "NullRegClasses[] = { NULL };\n\n";
1068 // Emit register class bit mask tables. The first bit mask emitted for a
1069 // register class, RC, is the set of sub-classes, including RC itself.
1071 // If RC has super-registers, also create a list of subreg indices and bit
1072 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1073 // SuperRC, that satisfies:
1075 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1077 // The 0-terminated list of subreg indices starts at:
1079 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1081 // The corresponding bitmasks follow the sub-class mask in memory. Each
1082 // mask has RCMaskWords uint32_t entries.
1084 // Every bit mask present in the list has at least one bit set.
1086 // Compress the sub-reg index lists.
1087 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1088 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1089 SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
1090 BitVector MaskBV(RegisterClasses.size());
1092 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1093 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1094 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1095 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1097 // Emit super-reg class masks for any relevant SubRegIndices that can
1099 IdxList &SRIList = SuperRegIdxLists[rc];
1100 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1101 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1103 RC.getSuperRegClasses(Idx, MaskBV);
1106 SRIList.push_back(Idx);
1108 printBitVectorAsHex(OS, MaskBV, 32);
1109 OS << "// " << Idx->getName();
1111 SuperRegIdxSeqs.add(SRIList);
1115 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1116 SuperRegIdxSeqs.layout();
1117 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1120 // Emit NULL terminated super-class lists.
1121 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
1122 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
1123 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1125 // Skip classes without supers. We can reuse NullRegClasses.
1129 OS << "static const TargetRegisterClass *const "
1130 << RC.getName() << "Superclasses[] = {\n";
1131 for (unsigned i = 0; i != Supers.size(); ++i)
1132 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1133 OS << " NULL\n};\n\n";
1137 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1138 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1139 if (!RC.AltOrderSelect.empty()) {
1140 OS << "\nstatic inline unsigned " << RC.getName()
1141 << "AltOrderSelect(const MachineFunction &MF) {"
1142 << RC.AltOrderSelect << "}\n\n"
1143 << "static ArrayRef<MCPhysReg> " << RC.getName()
1144 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1145 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1146 ArrayRef<Record*> Elems = RC.getOrder(oi);
1147 if (!Elems.empty()) {
1148 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1149 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1150 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1154 OS << " const MCRegisterClass &MCR = " << Target.getName()
1155 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1156 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1157 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1158 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1159 if (RC.getOrder(oi).empty())
1160 OS << "),\n ArrayRef<MCPhysReg>(";
1162 OS << "),\n makeArrayRef(AltOrder" << oi;
1163 OS << ")\n };\n const unsigned Select = " << RC.getName()
1164 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1165 << ");\n return Order[Select];\n}\n";
1169 // Now emit the actual value-initialized register class instances.
1170 OS << "namespace " << RegisterClasses[0]->Namespace
1171 << " { // Register class instances\n";
1173 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
1174 const CodeGenRegisterClass &RC = *RegisterClasses[i];
1175 OS << " extern const TargetRegisterClass "
1176 << RegisterClasses[i]->getName() << "RegClass = {\n "
1177 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
1178 << "RegClassID],\n "
1179 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
1180 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
1181 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
1182 if (RC.getSuperClasses().empty())
1183 OS << "NullRegClasses,\n ";
1185 OS << RC.getName() << "Superclasses,\n ";
1186 if (RC.AltOrderSelect.empty())
1189 OS << RC.getName() << "GetRawAllocationOrder\n";
1196 OS << "\nnamespace {\n";
1197 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1198 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1199 OS << " &" << RegisterClasses[i]->getQualifiedName()
1202 OS << "}\n"; // End of anonymous namespace...
1204 // Emit extra information about registers.
1205 const std::string &TargetName = Target.getName();
1206 OS << "\nstatic const TargetRegisterInfoDesc "
1207 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1208 OS << " { 0, 0 },\n";
1210 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1211 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1212 const CodeGenRegister &Reg = *Regs[i];
1214 OS << Reg.CostPerUse << ", "
1215 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1217 OS << "};\n"; // End of register descriptors...
1220 std::string ClassName = Target.getName() + "GenRegisterInfo";
1222 if (!SubRegIndices.empty())
1223 emitComposeSubRegIndices(OS, RegBank, ClassName);
1225 // Emit getSubClassWithSubReg.
1226 if (!SubRegIndices.empty()) {
1227 OS << "const TargetRegisterClass *" << ClassName
1228 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1230 // Use the smallest type that can hold a regclass ID with room for a
1232 if (RegisterClasses.size() < UINT8_MAX)
1233 OS << " static const uint8_t Table[";
1234 else if (RegisterClasses.size() < UINT16_MAX)
1235 OS << " static const uint16_t Table[";
1237 PrintFatalError("Too many register classes.");
1238 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1239 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1240 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1241 OS << " {\t// " << RC.getName() << "\n";
1242 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1243 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1244 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1245 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1246 << " -> " << SRC->getName() << "\n";
1248 OS << " 0,\t// " << Idx->getName() << "\n";
1252 OS << " };\n assert(RC && \"Missing regclass\");\n"
1253 << " if (!Idx) return RC;\n --Idx;\n"
1254 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1255 << " unsigned TV = Table[RC->getID()][Idx];\n"
1256 << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
1259 EmitRegUnitPressure(OS, RegBank, ClassName);
1261 // Emit the constructor of the class...
1262 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1263 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1264 OS << "extern const char " << TargetName << "RegStrings[];\n";
1265 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
1266 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1267 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1268 << TargetName << "SubRegIdxRanges[];\n";
1269 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1271 EmitRegMappingTables(OS, Regs, true);
1273 OS << ClassName << "::\n" << ClassName
1274 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1275 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1276 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1277 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1278 OS.write_hex(RegBank.CoveringLanes);
1280 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1281 << Regs.size()+1 << ", RA, PC,\n " << TargetName
1282 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1283 << " " << TargetName << "RegUnitRoots,\n"
1284 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1285 << " " << TargetName << "RegDiffLists,\n"
1286 << " " << TargetName << "RegStrings,\n"
1287 << " " << TargetName << "SubRegIdxLists,\n"
1288 << " " << SubRegIndices.size() + 1 << ",\n"
1289 << " " << TargetName << "SubRegIdxRanges,\n"
1290 << " " << TargetName << "RegEncodingTable);\n\n";
1292 EmitRegMapping(OS, Regs, true);
1297 // Emit CalleeSavedRegs information.
1298 std::vector<Record*> CSRSets =
1299 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1300 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1301 Record *CSRSet = CSRSets[i];
1302 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1303 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1305 // Emit the *_SaveList list of callee-saved registers.
1306 OS << "static const MCPhysReg " << CSRSet->getName()
1307 << "_SaveList[] = { ";
1308 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1309 OS << getQualifiedName((*Regs)[r]) << ", ";
1312 // Emit the *_RegMask bit mask of call-preserved registers.
1313 OS << "static const uint32_t " << CSRSet->getName()
1314 << "_RegMask[] = { ";
1315 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1320 OS << "} // End llvm namespace \n";
1321 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1324 void RegisterInfoEmitter::run(raw_ostream &OS) {
1325 CodeGenTarget Target(Records);
1326 CodeGenRegBank &RegBank = Target.getRegBank();
1327 RegBank.computeDerivedInfo();
1329 runEnums(OS, Target, RegBank);
1330 runMCDesc(OS, Target, RegBank);
1331 runTargetHeader(OS, Target, RegBank);
1332 runTargetDesc(OS, Target, RegBank);
1337 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1338 RegisterInfoEmitter(RK).run(OS);
1341 } // End llvm namespace