1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
33 class RegisterInfoEmitter {
34 RecordKeeper &Records;
36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
38 // runEnums - Print out enum values for all of the registers.
39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 // runMCDesc - Print out MC register descriptions.
42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
44 // runTargetHeader - Emit a header fragment for the register info emitter.
45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
46 CodeGenRegBank &Bank);
48 // runTargetDesc - Output the target register and register file descriptions.
49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
50 CodeGenRegBank &Bank);
52 // run - Output the register file description.
53 void run(raw_ostream &o);
56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
58 void EmitRegMappingTables(raw_ostream &o,
59 const std::deque<CodeGenRegister> &Regs,
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
62 const std::string &ClassName);
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
64 const std::string &ClassName);
66 } // End anonymous namespace
68 // runEnums - Print out enum values for all of the registers.
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
70 CodeGenTarget &Target, CodeGenRegBank &Bank) {
71 const auto &Registers = Bank.getRegisters();
73 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace =
77 Registers.front().TheDef->getValueAsString("Namespace");
79 emitSourceFileHeader("Target Register Enum Values", OS);
81 OS << "\n#ifdef GET_REGINFO_ENUM\n";
82 OS << "#undef GET_REGINFO_ENUM\n";
84 OS << "namespace llvm {\n\n";
86 OS << "class MCRegisterClass;\n"
87 << "extern const MCRegisterClass " << Namespace
88 << "MCRegisterClasses[];\n\n";
90 if (!Namespace.empty())
91 OS << "namespace " << Namespace << " {\n";
92 OS << "enum {\n NoRegister,\n";
94 for (const auto &Reg : Registers)
95 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
96 assert(Registers.size() == Registers.back().EnumValue &&
97 "Register enum value mismatch!");
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
100 if (!Namespace.empty())
103 const auto &RegisterClasses = Bank.getRegClasses();
104 if (!RegisterClasses.empty()) {
106 // RegisterClass enums are stored as uint16_t in the tables.
107 assert(RegisterClasses.size() <= 0xffff &&
108 "Too many register classes to fit in tables");
110 OS << "\n// Register classes\n";
111 if (!Namespace.empty())
112 OS << "namespace " << Namespace << " {\n";
114 for (const auto *RC : RegisterClasses)
115 OS << " " << RC->getName() << "RegClassID"
116 << " = " << RC->EnumValue << ",\n";
118 if (!Namespace.empty())
122 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
123 // If the only definition is the default NoRegAltName, we don't need to
125 if (RegAltNameIndices.size() > 1) {
126 OS << "\n// Register alternate name indices\n";
127 if (!Namespace.empty())
128 OS << "namespace " << Namespace << " {\n";
130 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
131 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
132 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
134 if (!Namespace.empty())
138 auto &SubRegIndices = Bank.getSubRegIndices();
139 if (!SubRegIndices.empty()) {
140 OS << "\n// Subregister indices\n";
141 std::string Namespace = SubRegIndices.front().getNamespace();
142 if (!Namespace.empty())
143 OS << "namespace " << Namespace << " {\n";
144 OS << "enum {\n NoSubRegister,\n";
146 for (const auto &Idx : SubRegIndices)
147 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
148 OS << " NUM_TARGET_SUBREGS\n};\n";
149 if (!Namespace.empty())
153 OS << "} // End llvm namespace\n";
154 OS << "#endif // GET_REGINFO_ENUM\n\n";
157 static void printInt(raw_ostream &OS, int Val) {
161 static const char *getMinimalTypeForRange(uint64_t Range) {
162 assert(Range < 0xFFFFFFFFULL && "Enum too large");
170 void RegisterInfoEmitter::
171 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
172 const std::string &ClassName) {
173 unsigned NumRCs = RegBank.getRegClasses().size();
174 unsigned NumSets = RegBank.getNumRegPressureSets();
176 OS << "/// Get the weight in units of pressure for this register class.\n"
177 << "const RegClassWeight &" << ClassName << "::\n"
178 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
179 << " static const RegClassWeight RCWeightTable[] = {\n";
180 for (const auto *RCP : RegBank.getRegClasses()) {
181 const CodeGenRegisterClass &RC = *RCP;
182 const CodeGenRegister::Set &Regs = RC.getMembers();
186 std::vector<unsigned> RegUnits;
187 RC.buildRegUnitSet(RegUnits);
188 OS << " {" << (*Regs.begin())->getWeight(RegBank)
189 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
191 OS << "}, \t// " << RC.getName() << "\n";
194 << " return RCWeightTable[RC->getID()];\n"
197 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
198 // bother generating a table.
199 bool RegUnitsHaveUnitWeight = true;
200 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
201 UnitIdx < UnitEnd; ++UnitIdx) {
202 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
203 RegUnitsHaveUnitWeight = false;
205 OS << "/// Get the weight in units of pressure for this register unit.\n"
206 << "unsigned " << ClassName << "::\n"
207 << "getRegUnitWeight(unsigned RegUnit) const {\n"
208 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
209 << " && \"invalid register unit\");\n";
210 if (!RegUnitsHaveUnitWeight) {
211 OS << " static const uint8_t RUWeightTable[] = {\n ";
212 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
213 UnitIdx < UnitEnd; ++UnitIdx) {
214 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
215 assert(RU.Weight < 256 && "RegUnit too heavy");
216 OS << RU.Weight << ", ";
219 << " return RUWeightTable[RegUnit];\n";
222 OS << " // All register units have unit weight.\n"
228 << "// Get the number of dimensions of register pressure.\n"
229 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
230 << " return " << NumSets << ";\n}\n\n";
232 OS << "// Get the name of this register unit pressure set.\n"
233 << "const char *" << ClassName << "::\n"
234 << "getRegPressureSetName(unsigned Idx) const {\n"
235 << " static const char *PressureNameTable[] = {\n";
236 unsigned MaxRegUnitWeight = 0;
237 for (unsigned i = 0; i < NumSets; ++i ) {
238 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
239 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
240 OS << " \"" << RegUnits.Name << "\",\n";
242 OS << " nullptr };\n"
243 << " return PressureNameTable[Idx];\n"
246 OS << "// Get the register unit pressure limit for this dimension.\n"
247 << "// This limit must be adjusted dynamically for reserved registers.\n"
248 << "unsigned " << ClassName << "::\n"
249 << "getRegPressureSetLimit(unsigned Idx) const {\n"
250 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
251 << " PressureLimitTable[] = {\n";
252 for (unsigned i = 0; i < NumSets; ++i ) {
253 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
254 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
255 << RegUnits.Name << "\n";
258 << " return PressureLimitTable[Idx];\n"
261 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
263 // This table may be larger than NumRCs if some register units needed a list
264 // of unit sets that did not correspond to a register class.
265 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
266 std::vector<std::vector<int>> PSets(NumRCUnitSets);
268 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
269 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
270 PSets[i].reserve(PSetIDs.size());
271 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
272 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
273 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
275 std::sort(PSets[i].begin(), PSets[i].end());
276 PSetsSeqs.add(PSets[i]);
281 OS << "/// Table of pressure sets per register class or unit.\n"
282 << "static const int RCSetsTable[] = {\n";
283 PSetsSeqs.emit(OS, printInt, "-1");
286 OS << "/// Get the dimensions of register pressure impacted by this "
287 << "register class.\n"
288 << "/// Returns a -1 terminated array of pressure set IDs\n"
289 << "const int* " << ClassName << "::\n"
290 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
291 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
292 << " RCSetStartTable[] = {\n ";
293 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
294 OS << PSetsSeqs.get(PSets[i]) << ",";
297 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
300 OS << "/// Get the dimensions of register pressure impacted by this "
301 << "register unit.\n"
302 << "/// Returns a -1 terminated array of pressure set IDs\n"
303 << "const int* " << ClassName << "::\n"
304 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
305 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
306 << " && \"invalid register unit\");\n";
307 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
308 << " RUSetStartTable[] = {\n ";
309 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
310 UnitIdx < UnitEnd; ++UnitIdx) {
311 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
315 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
319 void RegisterInfoEmitter::EmitRegMappingTables(
320 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
321 // Collect all information about dwarf register numbers
322 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
323 DwarfRegNumsMapTy DwarfRegNums;
325 // First, just pull all provided information to the map
326 unsigned maxLength = 0;
327 for (auto &RE : Regs) {
328 Record *Reg = RE.TheDef;
329 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
330 maxLength = std::max((size_t)maxLength, RegNums.size());
331 if (DwarfRegNums.count(Reg))
332 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
333 getQualifiedName(Reg) + "specified multiple times");
334 DwarfRegNums[Reg] = RegNums;
340 // Now we know maximal length of number list. Append -1's, where needed
341 for (DwarfRegNumsMapTy::iterator
342 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
343 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
344 I->second.push_back(-1);
346 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
348 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
350 // Emit reverse information about the dwarf register numbers.
351 for (unsigned j = 0; j < 2; ++j) {
352 for (unsigned i = 0, e = maxLength; i != e; ++i) {
353 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
354 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
355 OS << i << "Dwarf2L[]";
360 // Store the mapping sorted by the LLVM reg num so lookup can be done
361 // with a binary search.
362 std::map<uint64_t, Record*> Dwarf2LMap;
363 for (DwarfRegNumsMapTy::iterator
364 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
365 int DwarfRegNo = I->second[i];
368 Dwarf2LMap[DwarfRegNo] = I->first;
371 for (std::map<uint64_t, Record*>::iterator
372 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
373 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
381 // We have to store the size in a const global, it's used in multiple
383 OS << "extern const unsigned " << Namespace
384 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
386 OS << " = array_lengthof(" << Namespace
387 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
394 for (auto &RE : Regs) {
395 Record *Reg = RE.TheDef;
396 const RecordVal *V = Reg->getValue("DwarfAlias");
397 if (!V || !V->getValue())
400 DefInit *DI = cast<DefInit>(V->getValue());
401 Record *Alias = DI->getDef();
402 DwarfRegNums[Reg] = DwarfRegNums[Alias];
405 // Emit information about the dwarf register numbers.
406 for (unsigned j = 0; j < 2; ++j) {
407 for (unsigned i = 0, e = maxLength; i != e; ++i) {
408 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
409 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
410 OS << i << "L2Dwarf[]";
413 // Store the mapping sorted by the Dwarf reg num so lookup can be done
414 // with a binary search.
415 for (DwarfRegNumsMapTy::iterator
416 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
417 int RegNo = I->second[i];
418 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
421 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
429 // We have to store the size in a const global, it's used in multiple
431 OS << "extern const unsigned " << Namespace
432 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
434 OS << " = array_lengthof(" << Namespace
435 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
442 void RegisterInfoEmitter::EmitRegMapping(
443 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
444 // Emit the initializer so the tables from EmitRegMappingTables get wired up
445 // to the MCRegisterInfo object.
446 unsigned maxLength = 0;
447 for (auto &RE : Regs) {
448 Record *Reg = RE.TheDef;
449 maxLength = std::max((size_t)maxLength,
450 Reg->getValueAsListOfInts("DwarfNumbers").size());
456 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
458 // Emit reverse information about the dwarf register numbers.
459 for (unsigned j = 0; j < 2; ++j) {
462 OS << "DwarfFlavour";
467 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
469 for (unsigned i = 0, e = maxLength; i != e; ++i) {
470 OS << " case " << i << ":\n";
475 raw_string_ostream(Tmp) << Namespace
476 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
478 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
489 // Emit information about the dwarf register numbers.
490 for (unsigned j = 0; j < 2; ++j) {
493 OS << "DwarfFlavour";
498 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
500 for (unsigned i = 0, e = maxLength; i != e; ++i) {
501 OS << " case " << i << ":\n";
506 raw_string_ostream(Tmp) << Namespace
507 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
509 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
521 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
522 // Width is the number of bits per hex number.
523 static void printBitVectorAsHex(raw_ostream &OS,
524 const BitVector &Bits,
526 assert(Width <= 32 && "Width too large");
527 unsigned Digits = (Width + 3) / 4;
528 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
530 for (unsigned j = 0; j != Width && i + j != e; ++j)
531 Value |= Bits.test(i + j) << j;
532 OS << format("0x%0*x, ", Digits, Value);
536 // Helper to emit a set of bits into a constant byte array.
537 class BitVectorEmitter {
540 void add(unsigned v) {
541 if (v >= Values.size())
542 Values.resize(((v/8)+1)*8); // Round up to the next byte.
546 void print(raw_ostream &OS) {
547 printBitVectorAsHex(OS, Values, 8);
551 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
552 OS << getEnumName(VT);
555 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
556 OS << Idx->EnumValue;
559 // Differentially encoded register and regunit lists allow for better
560 // compression on regular register banks. The sequence is computed from the
561 // differential list as:
564 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
566 // The initial value depends on the specific list. The list is terminated by a
567 // 0 differential which means we can't encode repeated elements.
569 typedef SmallVector<uint16_t, 4> DiffVec;
571 // Differentially encode a sequence of numbers into V. The starting value and
572 // terminating 0 are not added to V, so it will have the same size as List.
574 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
575 assert(V.empty() && "Clear DiffVec before diffEncode.");
576 uint16_t Val = uint16_t(InitVal);
577 for (unsigned i = 0; i != List.size(); ++i) {
578 uint16_t Cur = List[i];
579 V.push_back(Cur - Val);
585 template<typename Iter>
587 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
588 assert(V.empty() && "Clear DiffVec before diffEncode.");
589 uint16_t Val = uint16_t(InitVal);
590 for (Iter I = Begin; I != End; ++I) {
591 uint16_t Cur = (*I)->EnumValue;
592 V.push_back(Cur - Val);
598 static void printDiff16(raw_ostream &OS, uint16_t Val) {
602 // Try to combine Idx's compose map into Vec if it is compatible.
603 // Return false if it's not possible.
604 static bool combine(const CodeGenSubRegIndex *Idx,
605 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
606 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
607 for (CodeGenSubRegIndex::CompMap::const_iterator
608 I = Map.begin(), E = Map.end(); I != E; ++I) {
609 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1];
610 if (Entry && Entry != I->second)
614 // All entries are compatible. Make it so.
615 for (CodeGenSubRegIndex::CompMap::const_iterator
616 I = Map.begin(), E = Map.end(); I != E; ++I)
617 Vec[I->first->EnumValue - 1] = I->second;
622 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
623 CodeGenRegBank &RegBank,
624 const std::string &ClName) {
625 const auto &SubRegIndices = RegBank.getSubRegIndices();
626 OS << "unsigned " << ClName
627 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
629 // Many sub-register indexes are composition-compatible, meaning that
631 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
633 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
634 // The illegal entries can be use as wildcards to compress the table further.
636 // Map each Sub-register index to a compatible table row.
637 SmallVector<unsigned, 4> RowMap;
638 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
640 auto SubRegIndicesSize =
641 std::distance(SubRegIndices.begin(), SubRegIndices.end());
642 for (const auto &Idx : SubRegIndices) {
643 unsigned Found = ~0u;
644 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
645 if (combine(&Idx, Rows[r])) {
652 Rows.resize(Found + 1);
653 Rows.back().resize(SubRegIndicesSize);
654 combine(&Idx, Rows.back());
656 RowMap.push_back(Found);
659 // Output the row map if there is multiple rows.
660 if (Rows.size() > 1) {
661 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
662 << SubRegIndicesSize << "] = {\n ";
663 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
664 OS << RowMap[i] << ", ";
669 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
670 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
671 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
673 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
675 OS << Rows[r][i]->EnumValue << ", ";
682 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
683 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
685 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
687 OS << " return Rows[0][IdxB];\n";
692 // runMCDesc - Print out MC register descriptions.
695 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
696 CodeGenRegBank &RegBank) {
697 emitSourceFileHeader("MC Register Information", OS);
699 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
700 OS << "#undef GET_REGINFO_MC_DESC\n";
702 const auto &Regs = RegBank.getRegisters();
704 auto &SubRegIndices = RegBank.getSubRegIndices();
705 // The lists of sub-registers and super-registers go in the same array. That
706 // allows us to share suffixes.
707 typedef std::vector<const CodeGenRegister*> RegVec;
709 // Differentially encoded lists.
710 SequenceToOffsetTable<DiffVec> DiffSeqs;
711 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
712 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
713 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
714 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
716 // Keep track of sub-register names as well. These are not differentially
718 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
719 SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
720 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
722 SequenceToOffsetTable<std::string> RegStrings;
724 // Precompute register lists for the SequenceToOffsetTable.
726 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
727 const auto &Reg = *I;
728 RegStrings.add(Reg.getName());
730 // Compute the ordered sub-register list.
731 SetVector<const CodeGenRegister*> SR;
732 Reg.addSubRegsPreOrder(SR, RegBank);
733 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
734 DiffSeqs.add(SubRegLists[i]);
736 // Compute the corresponding sub-register indexes.
737 SubRegIdxVec &SRIs = SubRegIdxLists[i];
738 for (unsigned j = 0, je = SR.size(); j != je; ++j)
739 SRIs.push_back(Reg.getSubRegIndex(SR[j]));
740 SubRegIdxSeqs.add(SRIs);
742 // Super-registers are already computed.
743 const RegVec &SuperRegList = Reg.getSuperRegs();
744 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
746 DiffSeqs.add(SuperRegLists[i]);
748 // Differentially encode the register unit list, seeded by register number.
749 // First compute a scale factor that allows more diff-lists to be reused:
754 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
755 // value for the differential decoder is the register number multiplied by
758 // Check the neighboring registers for arithmetic progressions.
759 unsigned ScaleA = ~0u, ScaleB = ~0u;
760 ArrayRef<unsigned> RUs = Reg.getNativeRegUnits();
761 if (I != Regs.begin() &&
762 std::prev(I)->getNativeRegUnits().size() == RUs.size())
763 ScaleB = RUs.front() - std::prev(I)->getNativeRegUnits().front();
764 if (std::next(I) != Regs.end() &&
765 std::next(I)->getNativeRegUnits().size() == RUs.size())
766 ScaleA = std::next(I)->getNativeRegUnits().front() - RUs.front();
767 unsigned Scale = std::min(ScaleB, ScaleA);
768 // Default the scale to 0 if it can't be encoded in 4 bits.
771 RegUnitInitScale[i] = Scale;
772 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
776 // Compute the final layout of the sequence table.
778 SubRegIdxSeqs.layout();
780 OS << "namespace llvm {\n\n";
782 const std::string &TargetName = Target.getName();
784 // Emit the shared table of differential lists.
785 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
786 DiffSeqs.emit(OS, printDiff16);
789 // Emit the table of sub-register indexes.
790 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
791 SubRegIdxSeqs.emit(OS, printSubRegIndex);
794 // Emit the table of sub-register index sizes.
795 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
796 << TargetName << "SubRegIdxRanges[] = {\n";
797 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
798 for (const auto &Idx : SubRegIndices) {
799 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
800 << Idx.getName() << "\n";
804 // Emit the string table.
806 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
807 RegStrings.emit(OS, printChar);
810 OS << "extern const MCRegisterDesc " << TargetName
811 << "RegDesc[] = { // Descriptors\n";
812 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
814 // Emit the register descriptors now.
816 for (const auto &Reg : Regs) {
817 OS << " { " << RegStrings.get(Reg.getName()) << ", "
818 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
819 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
820 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << " },\n";
823 OS << "};\n\n"; // End of register descriptors...
825 // Emit the table of register unit roots. Each regunit has one or two root
827 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
828 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
829 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
830 assert(!Roots.empty() && "All regunits must have a root register.");
831 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
832 OS << " { " << getQualifiedName(Roots.front()->TheDef);
833 for (unsigned r = 1; r != Roots.size(); ++r)
834 OS << ", " << getQualifiedName(Roots[r]->TheDef);
839 const auto &RegisterClasses = RegBank.getRegClasses();
841 // Loop over all of the register classes... emitting each one.
842 OS << "namespace { // Register classes...\n";
844 SequenceToOffsetTable<std::string> RegClassStrings;
846 // Emit the register enum value arrays for each RegisterClass
847 for (const auto *RCP : RegisterClasses) {
848 const CodeGenRegisterClass &RC = *RCP;
849 ArrayRef<Record*> Order = RC.getOrder();
851 // Give the register class a legal C name if it's anonymous.
852 std::string Name = RC.getName();
854 RegClassStrings.add(Name);
856 // Emit the register list now.
857 OS << " // " << Name << " Register Class...\n"
858 << " const MCPhysReg " << Name
860 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
861 Record *Reg = Order[i];
862 OS << getQualifiedName(Reg) << ", ";
866 OS << " // " << Name << " Bit set.\n"
867 << " const uint8_t " << Name
869 BitVectorEmitter BVE;
870 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
871 Record *Reg = Order[i];
872 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
880 RegClassStrings.layout();
881 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
882 RegClassStrings.emit(OS, printChar);
885 OS << "extern const MCRegisterClass " << TargetName
886 << "MCRegisterClasses[] = {\n";
888 for (const auto *RCP : RegisterClasses) {
889 const CodeGenRegisterClass &RC = *RCP;
891 // Asserts to make sure values will fit in table assuming types from
893 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
894 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
895 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
897 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
898 << RegClassStrings.get(RC.getName()) << ", "
899 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
900 << RC.getQualifiedName() + "RegClassID" << ", "
901 << RC.SpillSize/8 << ", "
902 << RC.SpillAlignment/8 << ", "
903 << RC.CopyCost << ", "
904 << RC.Allocatable << " },\n";
909 EmitRegMappingTables(OS, Regs, false);
911 // Emit Reg encoding table
912 OS << "extern const uint16_t " << TargetName;
913 OS << "RegEncodingTable[] = {\n";
914 // Add entry for NoRegister
916 for (const auto &RE : Regs) {
917 Record *Reg = RE.TheDef;
918 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
920 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
921 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
922 Value |= (uint64_t)B->getValue() << b;
924 OS << " " << Value << ",\n";
926 OS << "};\n"; // End of HW encoding table
928 // MCRegisterInfo initialization routine.
929 OS << "static inline void Init" << TargetName
930 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
931 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
933 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
934 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
935 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
936 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
937 << TargetName << "RegStrings, " << TargetName << "RegClassStrings, "
938 << TargetName << "SubRegIdxLists, "
939 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
940 << TargetName << "SubRegIdxRanges, " << TargetName
941 << "RegEncodingTable);\n\n";
943 EmitRegMapping(OS, Regs, false);
947 OS << "} // End llvm namespace\n";
948 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
952 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
953 CodeGenRegBank &RegBank) {
954 emitSourceFileHeader("Register Information Header Fragment", OS);
956 OS << "\n#ifdef GET_REGINFO_HEADER\n";
957 OS << "#undef GET_REGINFO_HEADER\n";
959 const std::string &TargetName = Target.getName();
960 std::string ClassName = TargetName + "GenRegisterInfo";
962 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
964 OS << "namespace llvm {\n\n";
966 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
967 << " explicit " << ClassName
968 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
969 << " bool needsStackRealignment(const MachineFunction &) const override\n"
970 << " { return false; }\n";
971 if (!RegBank.getSubRegIndices().empty()) {
972 OS << " unsigned composeSubRegIndicesImpl"
973 << "(unsigned, unsigned) const override;\n"
974 << " const TargetRegisterClass *getSubClassWithSubReg"
975 << "(const TargetRegisterClass*, unsigned) const override;\n";
977 OS << " const RegClassWeight &getRegClassWeight("
978 << "const TargetRegisterClass *RC) const override;\n"
979 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
980 << " unsigned getNumRegPressureSets() const override;\n"
981 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
982 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
983 << " const int *getRegClassPressureSets("
984 << "const TargetRegisterClass *RC) const override;\n"
985 << " const int *getRegUnitPressureSets("
986 << "unsigned RegUnit) const override;\n"
989 const auto &RegisterClasses = RegBank.getRegClasses();
991 if (!RegisterClasses.empty()) {
992 OS << "namespace " << RegisterClasses.front()->Namespace
993 << " { // Register classes\n";
995 for (const auto *RCP : RegisterClasses) {
996 const CodeGenRegisterClass &RC = *RCP;
997 const std::string &Name = RC.getName();
999 // Output the extern for the instance.
1000 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1002 OS << "} // end of namespace " << TargetName << "\n\n";
1004 OS << "} // End llvm namespace\n";
1005 OS << "#endif // GET_REGINFO_HEADER\n\n";
1009 // runTargetDesc - Output the target register and register file descriptions.
1012 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1013 CodeGenRegBank &RegBank){
1014 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1016 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1017 OS << "#undef GET_REGINFO_TARGET_DESC\n";
1019 OS << "namespace llvm {\n\n";
1021 // Get access to MCRegisterClass data.
1022 OS << "extern const MCRegisterClass " << Target.getName()
1023 << "MCRegisterClasses[];\n";
1025 // Start out by emitting each of the register classes.
1026 const auto &RegisterClasses = RegBank.getRegClasses();
1027 const auto &SubRegIndices = RegBank.getSubRegIndices();
1029 // Collect all registers belonging to any allocatable class.
1030 std::set<Record*> AllocatableRegs;
1032 // Collect allocatable registers.
1033 for (const auto *RCP : RegisterClasses) {
1034 const CodeGenRegisterClass &RC = *RCP;
1035 ArrayRef<Record*> Order = RC.getOrder();
1038 AllocatableRegs.insert(Order.begin(), Order.end());
1041 // Build a shared array of value types.
1042 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1043 for (const auto *RC : RegisterClasses)
1044 VTSeqs.add(RC->VTs);
1046 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1047 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1050 // Emit SubRegIndex names, skipping 0.
1051 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1053 for (const auto &Idx : SubRegIndices) {
1054 OS << Idx.getName();
1059 // Emit SubRegIndex lane masks, including 0.
1060 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1061 for (const auto &Idx : SubRegIndices) {
1062 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
1068 // Now that all of the structs have been emitted, emit the instances.
1069 if (!RegisterClasses.empty()) {
1070 OS << "\nstatic const TargetRegisterClass *const "
1071 << "NullRegClasses[] = { nullptr };\n\n";
1073 // Emit register class bit mask tables. The first bit mask emitted for a
1074 // register class, RC, is the set of sub-classes, including RC itself.
1076 // If RC has super-registers, also create a list of subreg indices and bit
1077 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1078 // SuperRC, that satisfies:
1080 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1082 // The 0-terminated list of subreg indices starts at:
1084 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1086 // The corresponding bitmasks follow the sub-class mask in memory. Each
1087 // mask has RCMaskWords uint32_t entries.
1089 // Every bit mask present in the list has at least one bit set.
1091 // Compress the sub-reg index lists.
1092 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1093 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1094 SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
1095 BitVector MaskBV(RegisterClasses.size());
1097 for (const auto *RCP : RegisterClasses) {
1098 const CodeGenRegisterClass &RC = *RCP;
1099 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1100 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1102 // Emit super-reg class masks for any relevant SubRegIndices that can
1104 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1105 for (auto &Idx : SubRegIndices) {
1107 RC.getSuperRegClasses(&Idx, MaskBV);
1110 SRIList.push_back(&Idx);
1112 printBitVectorAsHex(OS, MaskBV, 32);
1113 OS << "// " << Idx.getName();
1115 SuperRegIdxSeqs.add(SRIList);
1119 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1120 SuperRegIdxSeqs.layout();
1121 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1124 // Emit NULL terminated super-class lists.
1125 for (const auto *RCP : RegisterClasses) {
1126 const CodeGenRegisterClass &RC = *RCP;
1127 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1129 // Skip classes without supers. We can reuse NullRegClasses.
1133 OS << "static const TargetRegisterClass *const "
1134 << RC.getName() << "Superclasses[] = {\n";
1135 for (const auto *Super : Supers)
1136 OS << " &" << Super->getQualifiedName() << "RegClass,\n";
1137 OS << " nullptr\n};\n\n";
1141 for (const auto *RCP : RegisterClasses) {
1142 const CodeGenRegisterClass &RC = *RCP;
1143 if (!RC.AltOrderSelect.empty()) {
1144 OS << "\nstatic inline unsigned " << RC.getName()
1145 << "AltOrderSelect(const MachineFunction &MF) {"
1146 << RC.AltOrderSelect << "}\n\n"
1147 << "static ArrayRef<MCPhysReg> " << RC.getName()
1148 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1149 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1150 ArrayRef<Record*> Elems = RC.getOrder(oi);
1151 if (!Elems.empty()) {
1152 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1153 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1154 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1158 OS << " const MCRegisterClass &MCR = " << Target.getName()
1159 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1160 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1161 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1162 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1163 if (RC.getOrder(oi).empty())
1164 OS << "),\n ArrayRef<MCPhysReg>(";
1166 OS << "),\n makeArrayRef(AltOrder" << oi;
1167 OS << ")\n };\n const unsigned Select = " << RC.getName()
1168 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1169 << ");\n return Order[Select];\n}\n";
1173 // Now emit the actual value-initialized register class instances.
1174 OS << "\nnamespace " << RegisterClasses.front()->Namespace
1175 << " { // Register class instances\n";
1177 for (const auto *RCP : RegisterClasses) {
1178 const CodeGenRegisterClass &RC = *RCP;
1179 OS << " extern const TargetRegisterClass " << RC.getName()
1180 << "RegClass = {\n " << '&' << Target.getName()
1181 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1182 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
1183 << "SubClassMask,\n SuperRegIdxSeqs + "
1184 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";
1185 if (RC.getSuperClasses().empty())
1186 OS << "NullRegClasses,\n ";
1188 OS << RC.getName() << "Superclasses,\n ";
1189 if (RC.AltOrderSelect.empty())
1192 OS << RC.getName() << "GetRawAllocationOrder\n";
1199 OS << "\nnamespace {\n";
1200 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1201 for (const auto *RC : RegisterClasses)
1202 OS << " &" << RC->getQualifiedName() << "RegClass,\n";
1204 OS << "}\n"; // End of anonymous namespace...
1206 // Emit extra information about registers.
1207 const std::string &TargetName = Target.getName();
1208 OS << "\nstatic const TargetRegisterInfoDesc "
1209 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1210 OS << " { 0, 0 },\n";
1212 const auto &Regs = RegBank.getRegisters();
1213 for (const auto &Reg : Regs) {
1215 OS << Reg.CostPerUse << ", "
1216 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1218 OS << "};\n"; // End of register descriptors...
1221 std::string ClassName = Target.getName() + "GenRegisterInfo";
1223 auto SubRegIndicesSize =
1224 std::distance(SubRegIndices.begin(), SubRegIndices.end());
1226 if (!SubRegIndices.empty())
1227 emitComposeSubRegIndices(OS, RegBank, ClassName);
1229 // Emit getSubClassWithSubReg.
1230 if (!SubRegIndices.empty()) {
1231 OS << "const TargetRegisterClass *" << ClassName
1232 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1234 // Use the smallest type that can hold a regclass ID with room for a
1236 if (RegisterClasses.size() < UINT8_MAX)
1237 OS << " static const uint8_t Table[";
1238 else if (RegisterClasses.size() < UINT16_MAX)
1239 OS << " static const uint16_t Table[";
1241 PrintFatalError("Too many register classes.");
1242 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1243 for (const auto *RCP : RegisterClasses) {
1244 const CodeGenRegisterClass &RC = *RCP;
1245 OS << " {\t// " << RC.getName() << "\n";
1246 for (auto &Idx : SubRegIndices) {
1247 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1248 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1249 << " -> " << SRC->getName() << "\n";
1251 OS << " 0,\t// " << Idx.getName() << "\n";
1255 OS << " };\n assert(RC && \"Missing regclass\");\n"
1256 << " if (!Idx) return RC;\n --Idx;\n"
1257 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1258 << " unsigned TV = Table[RC->getID()][Idx];\n"
1259 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1262 EmitRegUnitPressure(OS, RegBank, ClassName);
1264 // Emit the constructor of the class...
1265 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1266 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1267 OS << "extern const char " << TargetName << "RegStrings[];\n";
1268 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1269 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1270 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1271 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1272 << TargetName << "SubRegIdxRanges[];\n";
1273 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1275 EmitRegMappingTables(OS, Regs, true);
1277 OS << ClassName << "::\n" << ClassName
1278 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1279 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1280 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1281 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1282 OS.write_hex(RegBank.CoveringLanes);
1284 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1285 << ", RA, PC,\n " << TargetName
1286 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1287 << " " << TargetName << "RegUnitRoots,\n"
1288 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1289 << " " << TargetName << "RegDiffLists,\n"
1290 << " " << TargetName << "RegStrings,\n"
1291 << " " << TargetName << "RegClassStrings,\n"
1292 << " " << TargetName << "SubRegIdxLists,\n"
1293 << " " << SubRegIndicesSize + 1 << ",\n"
1294 << " " << TargetName << "SubRegIdxRanges,\n"
1295 << " " << TargetName << "RegEncodingTable);\n\n";
1297 EmitRegMapping(OS, Regs, true);
1302 // Emit CalleeSavedRegs information.
1303 std::vector<Record*> CSRSets =
1304 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1305 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1306 Record *CSRSet = CSRSets[i];
1307 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1308 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1310 // Emit the *_SaveList list of callee-saved registers.
1311 OS << "static const MCPhysReg " << CSRSet->getName()
1312 << "_SaveList[] = { ";
1313 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1314 OS << getQualifiedName((*Regs)[r]) << ", ";
1317 // Emit the *_RegMask bit mask of call-preserved registers.
1318 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1320 // Check for an optional OtherPreserved set.
1321 // Add those registers to RegMask, but not to SaveList.
1322 if (DagInit *OPDag =
1323 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1324 SetTheory::RecSet OPSet;
1325 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1326 Covered |= RegBank.computeCoveredRegisters(
1327 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1330 OS << "static const uint32_t " << CSRSet->getName()
1331 << "_RegMask[] = { ";
1332 printBitVectorAsHex(OS, Covered, 32);
1337 OS << "} // End llvm namespace\n";
1338 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1341 void RegisterInfoEmitter::run(raw_ostream &OS) {
1342 CodeGenTarget Target(Records);
1343 CodeGenRegBank &RegBank = Target.getRegBank();
1344 RegBank.computeDerivedInfo();
1346 runEnums(OS, Target, RegBank);
1347 runMCDesc(OS, Target, RegBank);
1348 runTargetHeader(OS, Target, RegBank);
1349 runTargetDesc(OS, Target, RegBank);
1354 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1355 RegisterInfoEmitter(RK).run(OS);
1358 } // End llvm namespace