1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "dfa-emitter"
20 #include "CodeGenTarget.h"
21 #include "llvm/ADT/DenseSet.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/CodeGen/DFAPacketizerDefs.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include "llvm/Support/Debug.h"
35 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
37 // dbgsInsnClass - When debugging, print instruction class stages.
39 void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
41 // dbgsStateInfo - When debugging, print the set of state info.
43 void dbgsStateInfo(const std::set<unsigned> &stateInfo);
45 // dbgsIndent - When debugging, indent by the specified amount.
47 void dbgsIndent(unsigned indent);
51 // class DFAPacketizerEmitter: class that generates and prints out the DFA
52 // for resource tracking.
55 class DFAPacketizerEmitter {
57 std::string TargetName;
59 // allInsnClasses is the set of all possible resources consumed by an
62 std::vector<std::vector<unsigned>> allInsnClasses;
63 RecordKeeper &Records;
66 DFAPacketizerEmitter(RecordKeeper &R);
69 // collectAllFuncUnits - Construct a map of function unit names to bits.
71 int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
72 std::map<std::string, unsigned> &FUNameToBitsMap,
77 // collectAllComboFuncs - Construct a map from a combo function unit bit to
78 // the bits of all included functional units.
80 int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
81 std::map<std::string, unsigned> &FUNameToBitsMap,
82 std::map<unsigned, unsigned> &ComboBitToBitsMap,
86 // collectOneInsnClass - Populate allInsnClasses with one instruction class.
88 int collectOneInsnClass(const std::string &ProcName,
89 std::vector<Record*> &ProcItinList,
90 std::map<std::string, unsigned> &FUNameToBitsMap,
95 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
96 // used in each stage.
98 int collectAllInsnClasses(const std::string &ProcName,
99 std::vector<Record*> &ProcItinList,
100 std::map<std::string, unsigned> &FUNameToBitsMap,
101 std::vector<Record*> &ItinDataList,
105 void run(raw_ostream &OS);
107 } // End anonymous namespace.
111 // State represents the usage of machine resources if the packet contains
112 // a set of instruction classes.
114 // Specifically, currentState is a set of bit-masks.
115 // The nth bit in a bit-mask indicates whether the nth resource is being used
116 // by this state. The set of bit-masks in a state represent the different
117 // possible outcomes of transitioning to this state.
118 // For example: consider a two resource architecture: resource L and resource M
119 // with three instruction classes: L, M, and L_or_M.
120 // From the initial state (currentState = 0x00), if we add instruction class
121 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
122 // represents the possible resource states that can result from adding a L_or_M
125 // Another way of thinking about this transition is we are mapping a NDFA with
126 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
128 // A State instance also contains a collection of transitions from that state:
129 // a map from inputs to new states.
134 static int currentStateNum;
135 // stateNum is the only member used for equality/ordering, all other members
136 // can be mutated even in const State objects.
138 mutable bool isInitial;
139 mutable std::set<unsigned> stateInfo;
140 typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
141 mutable TransitionMap Transitions;
145 bool operator<(const State &s) const {
146 return stateNum < s.stateNum;
150 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
151 // may be a valid transition from this state i.e., can an instruction of type
152 // InsnClass be added to the packet represented by this state.
154 // Note that for multiple stages, this quick check does not take into account
155 // any possible resource competition between the stages themselves. That is
156 // enforced in AddInsnClassStages which checks the cross product of all
157 // stages for resource availability (which is a more involved check).
159 bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
160 std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
162 // AddInsnClass - Return all combinations of resource reservation
163 // which are possible from this state (PossibleStates).
165 // PossibleStates is the set of valid resource states that ensue from valid
168 void AddInsnClass(std::vector<unsigned> &InsnClass,
169 std::map<unsigned, unsigned> &ComboBitToBitsMap,
170 std::set<unsigned> &PossibleStates) const;
172 // AddInsnClassStages - Return all combinations of resource reservation
173 // resulting from the cross product of all stages for this InsnClass
174 // which are possible from this state (PossibleStates).
176 void AddInsnClassStages(std::vector<unsigned> &InsnClass,
177 std::map<unsigned, unsigned> &ComboBitToBitsMap,
178 unsigned chkstage, unsigned numstages,
179 unsigned prevState, unsigned origState,
180 DenseSet<unsigned> &VisitedResourceStates,
181 std::set<unsigned> &PossibleStates) const;
183 // addTransition - Add a transition from this state given the input InsnClass
185 void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
187 // hasTransition - Returns true if there is a transition from this state
188 // given the input InsnClass
190 bool hasTransition(std::vector<unsigned> InsnClass) const;
192 } // End anonymous namespace.
195 // class DFA: deterministic finite automaton for processor resource tracking.
202 // Set of states. Need to keep this sorted to emit the transition table.
203 typedef std::set<State> StateSet;
211 const State &newState();
214 // writeTable: Print out a table representing the DFA.
216 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
217 int numInsnClasses = 0,
218 int maxResources = 0, int numCombos = 0, int maxStages = 0);
220 } // End anonymous namespace.
223 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
225 // dbgsInsnClass - When debugging, print instruction class stages.
227 void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
228 DEBUG(dbgs() << "InsnClass: ");
229 for (unsigned i = 0; i < InsnClass.size(); ++i) {
231 DEBUG(dbgs() << ", ");
233 DEBUG(dbgs() << "0x" << utohexstr(InsnClass[i]));
235 DFAInput InsnInput = getDFAInsnInput(InsnClass);
236 DEBUG(dbgs() << " (input: 0x" << utohexstr(InsnInput) << ")");
240 // dbgsStateInfo - When debugging, print the set of state info.
242 void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
243 DEBUG(dbgs() << "StateInfo: ");
245 for (std::set<unsigned>::iterator SI = stateInfo.begin();
246 SI != stateInfo.end(); ++SI, ++i) {
247 unsigned thisState = *SI;
249 DEBUG(dbgs() << ", ");
251 DEBUG(dbgs() << "0x" << utohexstr(thisState));
256 // dbgsIndent - When debugging, indent by the specified amount.
258 void dbgsIndent(unsigned indent) {
259 for (unsigned i = 0; i < indent; ++i) {
260 DEBUG(dbgs() << " ");
266 // Constructors and destructors for State and DFA
269 stateNum(currentStateNum++), isInitial(false) {}
271 DFA::DFA(): currentState(nullptr) {}
274 // addTransition - Add a transition from this state given the input InsnClass
276 void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
278 assert(!Transitions.count(InsnClass) &&
279 "Cannot have multiple transitions for the same input");
280 Transitions[InsnClass] = To;
284 // hasTransition - Returns true if there is a transition from this state
285 // given the input InsnClass
287 bool State::hasTransition(std::vector<unsigned> InsnClass) const {
288 return Transitions.count(InsnClass) > 0;
292 // AddInsnClass - Return all combinations of resource reservation
293 // which are possible from this state (PossibleStates).
295 // PossibleStates is the set of valid resource states that ensue from valid
298 void State::AddInsnClass(std::vector<unsigned> &InsnClass,
299 std::map<unsigned, unsigned> &ComboBitToBitsMap,
300 std::set<unsigned> &PossibleStates) const {
302 // Iterate over all resource states in currentState.
304 unsigned numstages = InsnClass.size();
305 assert((numstages > 0) && "InsnClass has no stages");
307 for (std::set<unsigned>::iterator SI = stateInfo.begin();
308 SI != stateInfo.end(); ++SI) {
309 unsigned thisState = *SI;
311 DenseSet<unsigned> VisitedResourceStates;
313 DEBUG(dbgs() << " thisState: 0x" << utohexstr(thisState) << "\n");
314 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
315 numstages - 1, numstages,
316 thisState, thisState,
317 VisitedResourceStates, PossibleStates);
321 void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
322 std::map<unsigned, unsigned> &ComboBitToBitsMap,
323 unsigned chkstage, unsigned numstages,
324 unsigned prevState, unsigned origState,
325 DenseSet<unsigned> &VisitedResourceStates,
326 std::set<unsigned> &PossibleStates) const {
328 assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
329 unsigned thisStage = InsnClass[chkstage];
332 dbgsIndent((1 + numstages - chkstage) << 1);
333 dbgs() << "AddInsnClassStages " << chkstage << " (0x"
334 << utohexstr(thisStage) << ") from ";
335 dbgsInsnClass(InsnClass);
340 // Iterate over all possible resources used in thisStage.
341 // For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
343 for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
344 unsigned resourceMask = (0x1 << j);
345 if (resourceMask & thisStage) {
346 unsigned combo = ComboBitToBitsMap[resourceMask];
347 if (combo && ((~prevState & combo) != combo)) {
348 DEBUG(dbgs() << "\tSkipped Add 0x" << utohexstr(prevState)
349 << " - combo op 0x" << utohexstr(resourceMask)
350 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
354 // For each possible resource used in thisStage, generate the
355 // resource state if that resource was used.
357 unsigned ResultingResourceState = prevState | resourceMask | combo;
359 dbgsIndent((2 + numstages - chkstage) << 1);
360 dbgs() << "0x" << utohexstr(prevState)
361 << " | 0x" << utohexstr(resourceMask);
363 dbgs() << " | 0x" << utohexstr(combo);
364 dbgs() << " = 0x" << utohexstr(ResultingResourceState) << " ";
368 // If this is the final stage for this class
372 // Check if the resulting resource state can be accommodated in this
374 // We compute resource OR prevState (originally started as origState).
375 // If the result of the OR is different than origState, it implies
376 // that there is at least one resource that can be used to schedule
377 // thisStage in the current packet.
378 // Insert ResultingResourceState into PossibleStates only if we haven't
379 // processed ResultingResourceState before.
381 if (ResultingResourceState != prevState) {
382 if (VisitedResourceStates.count(ResultingResourceState) == 0) {
383 VisitedResourceStates.insert(ResultingResourceState);
384 PossibleStates.insert(ResultingResourceState);
385 DEBUG(dbgs() << "\tResultingResourceState: 0x"
386 << utohexstr(ResultingResourceState) << "\n");
388 DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
391 DEBUG(dbgs() << "\tSkipped Add - no final resources available\n");
395 // If the current resource can be accommodated, check the next
396 // stage in InsnClass for available resources.
398 if (ResultingResourceState != prevState) {
399 DEBUG(dbgs() << "\n");
400 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
401 chkstage - 1, numstages,
402 ResultingResourceState, origState,
403 VisitedResourceStates, PossibleStates);
405 DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
414 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
415 // may be a valid transition from this state i.e., can an instruction of type
416 // InsnClass be added to the packet represented by this state.
418 // Note that this routine is performing conservative checks that can be
419 // quickly executed acting as a filter before calling AddInsnClassStages.
420 // Any cases allowed through here will be caught later in AddInsnClassStages
421 // which performs the more expensive exact check.
423 bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
424 std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
425 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
426 SI != stateInfo.end(); ++SI) {
428 // Check to see if all required resources are available.
429 bool available = true;
431 // Inspect each stage independently.
432 // note: This is a conservative check as we aren't checking for
433 // possible resource competition between the stages themselves
434 // The full cross product is examined later in AddInsnClass.
435 for (unsigned i = 0; i < InsnClass.size(); ++i) {
436 unsigned resources = *SI;
437 if ((~resources & InsnClass[i]) == 0) {
441 // Make sure _all_ resources for a combo function are available.
442 // note: This is a quick conservative check as it won't catch an
443 // unscheduleable combo if this stage is an OR expression
444 // containing a combo.
445 // These cases are caught later in AddInsnClass.
446 unsigned combo = ComboBitToBitsMap[InsnClass[i]];
447 if (combo && ((~resources & combo) != combo)) {
448 DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x" << utohexstr(resources)
449 << " - combo op 0x" << utohexstr(InsnClass[i])
450 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
464 const State &DFA::newState() {
465 auto IterPair = states.insert(State());
466 assert(IterPair.second && "State already exists");
467 return *IterPair.first;
470 int State::currentStateNum = 0;
472 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
473 TargetName(CodeGenTarget(R).getName()),
474 allInsnClasses(), Records(R) {}
478 // writeTableAndAPI - Print out a table representing the DFA and the
479 // associated API to create a DFA packetizer.
482 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
484 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
488 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
490 int maxResources, int numCombos, int maxStages) {
492 unsigned numStates = states.size();
494 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
495 DEBUG(dbgs() << "writeTableAndAPI\n");
496 DEBUG(dbgs() << "Total states: " << numStates << "\n");
498 OS << "namespace llvm {\n";
500 OS << "\n// Input format:\n";
501 OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
502 << "\t// maximum AND'ed resource terms\n";
503 OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
504 << "\t// maximum resource bits in one term\n";
506 OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
507 << "pairs of <Input, NextState> for all valid\n";
508 OS << "// transitions.\n";
509 OS << "// " << numStates << "\tstates\n";
510 OS << "// " << numInsnClasses << "\tinstruction classes\n";
511 OS << "// " << maxResources << "\tresources max\n";
512 OS << "// " << numCombos << "\tcombo resources\n";
513 OS << "// " << maxStages << "\tstages max\n";
514 OS << "const " << DFA_TBLTYPE << " "
515 << TargetName << "DFAStateInputTable[][2] = {\n";
517 // This table provides a map to the beginning of the transitions for State s
518 // in DFAStateInputTable.
519 std::vector<int> StateEntry(numStates+1);
520 static const std::string SentinelEntry = "{-1, -1}";
522 // Tracks the total valid transitions encountered so far. It is used
523 // to construct the StateEntry table.
524 int ValidTransitions = 0;
525 DFA::StateSet::iterator SI = states.begin();
526 for (unsigned i = 0; i < numStates; ++i, ++SI) {
527 assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
528 StateEntry[i] = ValidTransitions;
529 for (State::TransitionMap::iterator
530 II = SI->Transitions.begin(), IE = SI->Transitions.end();
532 OS << "{0x" << utohexstr(getDFAInsnInput(II->first)) << ", "
533 << II->second->stateNum
536 ValidTransitions += SI->Transitions.size();
538 // If there are no valid transitions from this stage, we need a sentinel
540 if (ValidTransitions == StateEntry[i]) {
541 OS << SentinelEntry << ",\t";
545 OS << " // state " << i << ": " << StateEntry[i];
546 if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
547 OS << "-" << (ValidTransitions-1);
552 // Print out a sentinel entry at the end of the StateInputTable. This is
553 // needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
554 OS << SentinelEntry << "\t";
555 OS << " // state " << numStates << ": " << ValidTransitions;
559 OS << "// " << TargetName << "DFAStateEntryTable[i] = "
560 << "Index of the first entry in DFAStateInputTable for\n";
562 << "the ith state.\n";
563 OS << "// " << numStates << " states\n";
564 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
566 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
568 unsigned lastState = 0;
569 for (unsigned i = 0; i < numStates; ++i) {
570 if (i && ((i % 10) == 0)) {
572 OS << " // states " << (i-10) << ":" << lastState << "\n";
574 OS << StateEntry[i] << ", ";
577 // Print out the index to the sentinel entry in StateInputTable
578 OS << ValidTransitions << ", ";
579 OS << " // states " << (lastState+1) << ":" << numStates << "\n";
582 OS << "} // namespace\n";
586 // Emit DFA Packetizer tables if the target is a VLIW machine.
588 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
589 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
590 OS << "namespace llvm {\n";
591 OS << "DFAPacketizer *" << SubTargetClassName << "::"
592 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
593 << " return new DFAPacketizer(IID, " << TargetName
594 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
595 OS << "} // End llvm namespace \n";
600 // collectAllFuncUnits - Construct a map of function unit names to bits.
602 int DFAPacketizerEmitter::collectAllFuncUnits(
603 std::vector<Record*> &ProcItinList,
604 std::map<std::string, unsigned> &FUNameToBitsMap,
607 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
608 DEBUG(dbgs() << "collectAllFuncUnits");
609 DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
612 // Parse functional units for all the itineraries.
613 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
614 Record *Proc = ProcItinList[i];
615 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
617 DEBUG(dbgs() << " FU:" << i
618 << " (" << FUs.size() << " FUs) "
622 // Convert macros to bits for each stage.
623 unsigned numFUs = FUs.size();
624 for (unsigned j = 0; j < numFUs; ++j) {
625 assert ((j < DFA_MAX_RESOURCES) &&
626 "Exceeded maximum number of representable resources");
627 unsigned FuncResources = (unsigned) (1U << j);
628 FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
629 DEBUG(dbgs() << " " << FUs[j]->getName()
630 << ":0x" << utohexstr(FuncResources));
632 if (((int) numFUs) > maxFUs) {
636 DEBUG(dbgs() << "\n");
642 // collectAllComboFuncs - Construct a map from a combo function unit bit to
643 // the bits of all included functional units.
645 int DFAPacketizerEmitter::collectAllComboFuncs(
646 std::vector<Record*> &ComboFuncList,
647 std::map<std::string, unsigned> &FUNameToBitsMap,
648 std::map<unsigned, unsigned> &ComboBitToBitsMap,
650 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
651 DEBUG(dbgs() << "collectAllComboFuncs");
652 DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
655 for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
656 Record *Func = ComboFuncList[i];
657 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
659 DEBUG(dbgs() << " CFD:" << i
660 << " (" << FUs.size() << " combo FUs) "
661 << Func->getName() << "\n");
663 // Convert macros to bits for each stage.
664 for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
665 assert ((j < DFA_MAX_RESOURCES) &&
666 "Exceeded maximum number of DFA resources");
667 Record *FuncData = FUs[j];
668 Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
669 const std::vector<Record*> &FuncList =
670 FuncData->getValueAsListOfDefs("FuncList");
671 std::string ComboFuncName = ComboFunc->getName();
672 unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
673 unsigned ComboResources = ComboBit;
674 DEBUG(dbgs() << " combo: " << ComboFuncName
675 << ":0x" << utohexstr(ComboResources) << "\n");
676 for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
677 std::string FuncName = FuncList[k]->getName();
678 unsigned FuncResources = FUNameToBitsMap[FuncName];
679 DEBUG(dbgs() << " " << FuncName
680 << ":0x" << utohexstr(FuncResources) << "\n");
681 ComboResources |= FuncResources;
683 ComboBitToBitsMap[ComboBit] = ComboResources;
685 DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
686 << utohexstr(ComboBit) << " = 0x"
687 << utohexstr(ComboResources) << "\n");
695 // collectOneInsnClass - Populate allInsnClasses with one instruction class
697 int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
698 std::vector<Record*> &ProcItinList,
699 std::map<std::string, unsigned> &FUNameToBitsMap,
702 const std::vector<Record*> &StageList =
703 ItinData->getValueAsListOfDefs("Stages");
705 // The number of stages.
706 unsigned NStages = StageList.size();
708 DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName()
711 std::vector<unsigned> UnitBits;
713 // Compute the bitwise or of each unit used in this stage.
714 for (unsigned i = 0; i < NStages; ++i) {
715 const Record *Stage = StageList[i];
718 const std::vector<Record*> &UnitList =
719 Stage->getValueAsListOfDefs("Units");
721 DEBUG(dbgs() << " stage:" << i
722 << " [" << UnitList.size() << " units]:");
723 unsigned dbglen = 26; // cursor after stage dbgs
725 // Compute the bitwise or of each unit used in this stage.
726 unsigned UnitBitValue = 0;
727 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
728 // Conduct bitwise or.
729 std::string UnitName = UnitList[j]->getName();
730 DEBUG(dbgs() << " " << j << ":" << UnitName);
731 dbglen += 3 + UnitName.length();
732 assert(FUNameToBitsMap.count(UnitName));
733 UnitBitValue |= FUNameToBitsMap[UnitName];
736 if (UnitBitValue != 0)
737 UnitBits.push_back(UnitBitValue);
739 while (dbglen <= 64) { // line up bits dbgs
741 DEBUG(dbgs() << "\t");
743 DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
746 if (UnitBits.size() > 0)
747 allInsnClasses.push_back(UnitBits);
751 dbgsInsnClass(UnitBits);
759 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
760 // used in each stage.
762 int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
763 std::vector<Record*> &ProcItinList,
764 std::map<std::string, unsigned> &FUNameToBitsMap,
765 std::vector<Record*> &ItinDataList,
768 // Collect all instruction classes.
769 unsigned M = ItinDataList.size();
771 int numInsnClasses = 0;
772 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"
773 << "collectAllInsnClasses "
775 << " (" << M << " classes)\n");
777 // Collect stages for each instruction class for all itinerary data
778 for (unsigned j = 0; j < M; j++) {
779 Record *ItinData = ItinDataList[j];
780 int NStages = collectOneInsnClass(ProcName, ProcItinList,
781 FUNameToBitsMap, ItinData, OS);
782 if (NStages > maxStages) {
787 return numInsnClasses;
791 // Run the worklist algorithm to generate the DFA.
793 void DFAPacketizerEmitter::run(raw_ostream &OS) {
795 // Collect processor iteraries.
796 std::vector<Record*> ProcItinList =
797 Records.getAllDerivedDefinitions("ProcessorItineraries");
800 // Collect the Functional units.
802 std::map<std::string, unsigned> FUNameToBitsMap;
803 int maxResources = 0;
804 collectAllFuncUnits(ProcItinList,
805 FUNameToBitsMap, maxResources, OS);
808 // Collect the Combo Functional units.
810 std::map<unsigned, unsigned> ComboBitToBitsMap;
811 std::vector<Record*> ComboFuncList =
812 Records.getAllDerivedDefinitions("ComboFuncUnits");
813 int numCombos = collectAllComboFuncs(ComboFuncList,
814 FUNameToBitsMap, ComboBitToBitsMap, OS);
817 // Collect the itineraries.
820 int numInsnClasses = 0;
821 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
822 Record *Proc = ProcItinList[i];
824 // Get processor itinerary name.
825 const std::string &ProcName = Proc->getName();
828 if (ProcName == "NoItineraries")
831 // Sanity check for at least one instruction itinerary class.
832 unsigned NItinClasses =
833 Records.getAllDerivedDefinitions("InstrItinClass").size();
834 if (NItinClasses == 0)
837 // Get itinerary data list.
838 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
840 // Collect all instruction classes
841 numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
842 FUNameToBitsMap, ItinDataList, maxStages, OS);
846 // Run a worklist algorithm to generate the DFA.
849 const State *Initial = &D.newState();
850 Initial->isInitial = true;
851 Initial->stateInfo.insert(0x0);
852 SmallVector<const State*, 32> WorkList;
853 // std::queue<State*> WorkList;
854 std::map<std::set<unsigned>, const State*> Visited;
856 WorkList.push_back(Initial);
859 // Worklist algorithm to create a DFA for processor resource tracking.
860 // C = {set of InsnClasses}
861 // Begin with initial node in worklist. Initial node does not have
862 // any consumed resources,
863 // ResourceState = 0x0
865 // While worklist != empty
866 // S = first element of worklist
867 // For every instruction class C
868 // if we can accommodate C in S:
869 // S' = state with resource states = {S Union C}
870 // Add a new transition: S x C -> S'
871 // If S' is not in Visited:
872 // Add S' to worklist
875 while (!WorkList.empty()) {
876 const State *current = WorkList.pop_back_val();
878 dbgs() << "---------------------\n";
879 dbgs() << "Processing state: " << current->stateNum << " - ";
880 dbgsStateInfo(current->stateInfo);
883 for (unsigned i = 0; i < allInsnClasses.size(); i++) {
884 std::vector<unsigned> InsnClass = allInsnClasses[i];
887 dbgsInsnClass(InsnClass);
891 std::set<unsigned> NewStateResources;
893 // If we haven't already created a transition for this input
894 // and the state can accommodate this InsnClass, create a transition.
896 if (!current->hasTransition(InsnClass) &&
897 current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
898 const State *NewState = NULL;
899 current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
900 if (NewStateResources.size() == 0) {
901 DEBUG(dbgs() << " Skipped - no new states generated\n");
907 dbgsStateInfo(NewStateResources);
912 // If we have seen this state before, then do not create a new state.
914 auto VI = Visited.find(NewStateResources);
915 if (VI != Visited.end()) {
916 NewState = VI->second;
918 dbgs() << "\tFound existing state: " << NewState->stateNum
920 dbgsStateInfo(NewState->stateInfo);
924 NewState = &D.newState();
925 NewState->stateInfo = NewStateResources;
926 Visited[NewStateResources] = NewState;
927 WorkList.push_back(NewState);
929 dbgs() << "\tAccepted new state: " << NewState->stateNum << " - ";
930 dbgsStateInfo(NewState->stateInfo);
935 current->addTransition(InsnClass, NewState);
940 // Print out the table.
941 D.writeTableAndAPI(OS, TargetName,
942 numInsnClasses, maxResources, numCombos, maxStages);
947 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
948 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
949 DFAPacketizerEmitter(RK).run(OS);
952 } // End llvm namespace