1 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class parses the Schedule.td file and produces an API that can be used
11 // to reason about whether an instruction can be added to a packet on a VLIW
12 // architecture. The class internally generates a deterministic finite
13 // automaton (DFA) that models all possible mappings of machine instructions
14 // to functional units as instructions are added to a packet.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "dfa-emitter"
20 #include "CodeGenTarget.h"
21 #include "llvm/ADT/DenseSet.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/CodeGen/DFAPacketizer.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include "llvm/Support/Debug.h"
34 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
36 // dbgsInsnClass - When debugging, print instruction class stages.
38 void dbgsInsnClass(const std::vector<unsigned> &InsnClass);
40 // dbgsStateInfo - When debugging, print the set of state info.
42 void dbgsStateInfo(const std::set<unsigned> &stateInfo);
44 // dbgsIndent - When debugging, indent by the specified amount.
46 void dbgsIndent(unsigned indent);
49 // class DFAPacketizerEmitter: class that generates and prints out the DFA
50 // for resource tracking.
53 class DFAPacketizerEmitter {
55 std::string TargetName;
57 // allInsnClasses is the set of all possible resources consumed by an
60 std::vector<std::vector<unsigned>> allInsnClasses;
61 RecordKeeper &Records;
64 DFAPacketizerEmitter(RecordKeeper &R);
67 // collectAllFuncUnits - Construct a map of function unit names to bits.
69 int collectAllFuncUnits(std::vector<Record*> &ProcItinList,
70 std::map<std::string, unsigned> &FUNameToBitsMap,
75 // collectAllComboFuncs - Construct a map from a combo function unit bit to
76 // the bits of all included functional units.
78 int collectAllComboFuncs(std::vector<Record*> &ComboFuncList,
79 std::map<std::string, unsigned> &FUNameToBitsMap,
80 std::map<unsigned, unsigned> &ComboBitToBitsMap,
84 // collectOneInsnClass - Populate allInsnClasses with one instruction class.
86 int collectOneInsnClass(const std::string &ProcName,
87 std::vector<Record*> &ProcItinList,
88 std::map<std::string, unsigned> &FUNameToBitsMap,
93 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
94 // used in each stage.
96 int collectAllInsnClasses(const std::string &ProcName,
97 std::vector<Record*> &ProcItinList,
98 std::map<std::string, unsigned> &FUNameToBitsMap,
99 std::vector<Record*> &ItinDataList,
103 void run(raw_ostream &OS);
105 } // End anonymous namespace.
109 // State represents the usage of machine resources if the packet contains
110 // a set of instruction classes.
112 // Specifically, currentState is a set of bit-masks.
113 // The nth bit in a bit-mask indicates whether the nth resource is being used
114 // by this state. The set of bit-masks in a state represent the different
115 // possible outcomes of transitioning to this state.
116 // For example: consider a two resource architecture: resource L and resource M
117 // with three instruction classes: L, M, and L_or_M.
118 // From the initial state (currentState = 0x00), if we add instruction class
119 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
120 // represents the possible resource states that can result from adding a L_or_M
123 // Another way of thinking about this transition is we are mapping a NDFA with
124 // two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
126 // A State instance also contains a collection of transitions from that state:
127 // a map from inputs to new states.
132 static int currentStateNum;
133 // stateNum is the only member used for equality/ordering, all other members
134 // can be mutated even in const State objects.
136 mutable bool isInitial;
137 mutable std::set<unsigned> stateInfo;
138 typedef std::map<std::vector<unsigned>, const State *> TransitionMap;
139 mutable TransitionMap Transitions;
143 bool operator<(const State &s) const {
144 return stateNum < s.stateNum;
148 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
149 // may be a valid transition from this state i.e., can an instruction of type
150 // InsnClass be added to the packet represented by this state.
152 // Note that for multiple stages, this quick check does not take into account
153 // any possible resource competition between the stages themselves. That is
154 // enforced in AddInsnClassStages which checks the cross product of all
155 // stages for resource availability (which is a more involved check).
157 bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
158 std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
160 // AddInsnClass - Return all combinations of resource reservation
161 // which are possible from this state (PossibleStates).
163 // PossibleStates is the set of valid resource states that ensue from valid
166 void AddInsnClass(std::vector<unsigned> &InsnClass,
167 std::map<unsigned, unsigned> &ComboBitToBitsMap,
168 std::set<unsigned> &PossibleStates) const;
170 // AddInsnClassStages - Return all combinations of resource reservation
171 // resulting from the cross product of all stages for this InsnClass
172 // which are possible from this state (PossibleStates).
174 void AddInsnClassStages(std::vector<unsigned> &InsnClass,
175 std::map<unsigned, unsigned> &ComboBitToBitsMap,
176 unsigned chkstage, unsigned numstages,
177 unsigned prevState, unsigned origState,
178 DenseSet<unsigned> &VisitedResourceStates,
179 std::set<unsigned> &PossibleStates) const;
181 // addTransition - Add a transition from this state given the input InsnClass
183 void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
185 // hasTransition - Returns true if there is a transition from this state
186 // given the input InsnClass
188 bool hasTransition(std::vector<unsigned> InsnClass) const;
190 } // End anonymous namespace.
193 // class DFA: deterministic finite automaton for processor resource tracking.
200 // Set of states. Need to keep this sorted to emit the transition table.
201 typedef std::set<State> StateSet;
209 const State &newState();
212 // writeTable: Print out a table representing the DFA.
214 void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName,
215 int numInsnClasses = 0,
216 int maxResources = 0, int numCombos = 0, int maxStages = 0);
218 } // End anonymous namespace.
220 // To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
222 // dbgsInsnClass - When debugging, print instruction class stages.
224 void dbgsInsnClass(const std::vector<unsigned> &InsnClass) {
225 DEBUG(dbgs() << "InsnClass: ");
226 for (unsigned i = 0; i < InsnClass.size(); ++i) {
228 DEBUG(dbgs() << ", ");
230 DEBUG(dbgs() << "0x" << utohexstr(InsnClass[i]));
232 DFAInput InsnInput = DFAPacketizer::getInsnInput(InsnClass);
233 DEBUG(dbgs() << " (input: 0x" << utohexstr(InsnInput) << ")");
237 // dbgsStateInfo - When debugging, print the set of state info.
239 void dbgsStateInfo(const std::set<unsigned> &stateInfo) {
240 DEBUG(dbgs() << "StateInfo: ");
242 for (std::set<unsigned>::iterator SI = stateInfo.begin();
243 SI != stateInfo.end(); ++SI, ++i) {
244 unsigned thisState = *SI;
246 DEBUG(dbgs() << ", ");
248 DEBUG(dbgs() << "0x" << utohexstr(thisState));
253 // dbgsIndent - When debugging, indent by the specified amount.
255 void dbgsIndent(unsigned indent) {
256 for (unsigned i = 0; i < indent; ++i) {
257 DEBUG(dbgs() << " ");
262 // Constructors and destructors for State and DFA
265 stateNum(currentStateNum++), isInitial(false) {}
267 DFA::DFA(): currentState(nullptr) {}
270 // addTransition - Add a transition from this state given the input InsnClass
272 void State::addTransition(std::vector<unsigned> InsnClass, const State *To)
274 assert(!Transitions.count(InsnClass) &&
275 "Cannot have multiple transitions for the same input");
276 Transitions[InsnClass] = To;
280 // hasTransition - Returns true if there is a transition from this state
281 // given the input InsnClass
283 bool State::hasTransition(std::vector<unsigned> InsnClass) const {
284 return Transitions.count(InsnClass) > 0;
288 // AddInsnClass - Return all combinations of resource reservation
289 // which are possible from this state (PossibleStates).
291 // PossibleStates is the set of valid resource states that ensue from valid
294 void State::AddInsnClass(std::vector<unsigned> &InsnClass,
295 std::map<unsigned, unsigned> &ComboBitToBitsMap,
296 std::set<unsigned> &PossibleStates) const {
298 // Iterate over all resource states in currentState.
300 unsigned numstages = InsnClass.size();
301 assert((numstages > 0) && "InsnClass has no stages");
303 for (std::set<unsigned>::iterator SI = stateInfo.begin();
304 SI != stateInfo.end(); ++SI) {
305 unsigned thisState = *SI;
307 DenseSet<unsigned> VisitedResourceStates;
309 DEBUG(dbgs() << " thisState: 0x" << utohexstr(thisState) << "\n");
310 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
311 numstages - 1, numstages,
312 thisState, thisState,
313 VisitedResourceStates, PossibleStates);
317 void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
318 std::map<unsigned, unsigned> &ComboBitToBitsMap,
319 unsigned chkstage, unsigned numstages,
320 unsigned prevState, unsigned origState,
321 DenseSet<unsigned> &VisitedResourceStates,
322 std::set<unsigned> &PossibleStates) const {
324 assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
325 unsigned thisStage = InsnClass[chkstage];
327 dbgsIndent((1 + numstages - chkstage) << 1);
328 DEBUG(dbgs() << "AddInsnClassStages " << chkstage
329 << " (0x" << utohexstr(thisStage) << ") from ");
330 dbgsInsnClass(InsnClass);
331 DEBUG(dbgs() << "\n");
334 // Iterate over all possible resources used in thisStage.
335 // For ex: for thisStage = 0x11, all resources = {0x01, 0x10}.
337 for (unsigned int j = 0; j < DFA_MAX_RESOURCES; ++j) {
338 unsigned resourceMask = (0x1 << j);
339 if (resourceMask & thisStage) {
340 unsigned combo = ComboBitToBitsMap[resourceMask];
341 if (combo && ((~prevState & combo) != combo)) {
342 DEBUG(dbgs() << "\tSkipped Add 0x" << utohexstr(prevState)
343 << " - combo op 0x" << utohexstr(resourceMask)
344 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
348 // For each possible resource used in thisStage, generate the
349 // resource state if that resource was used.
351 unsigned ResultingResourceState = prevState | resourceMask | combo;
352 dbgsIndent((2 + numstages - chkstage) << 1);
353 DEBUG(dbgs() << "0x" << utohexstr(prevState)
354 << " | 0x" << utohexstr(resourceMask));
356 DEBUG(dbgs() << " | 0x" << utohexstr(combo));
358 DEBUG(dbgs() << " = 0x" << utohexstr(ResultingResourceState) << " ");
361 // If this is the final stage for this class
365 // Check if the resulting resource state can be accommodated in this
367 // We compute resource OR prevState (originally started as origState).
368 // If the result of the OR is different than origState, it implies
369 // that there is at least one resource that can be used to schedule
370 // thisStage in the current packet.
371 // Insert ResultingResourceState into PossibleStates only if we haven't
372 // processed ResultingResourceState before.
374 if (ResultingResourceState != prevState) {
375 if (VisitedResourceStates.count(ResultingResourceState) == 0) {
376 VisitedResourceStates.insert(ResultingResourceState);
377 PossibleStates.insert(ResultingResourceState);
378 DEBUG(dbgs() << "\tResultingResourceState: 0x"
379 << utohexstr(ResultingResourceState) << "\n");
381 DEBUG(dbgs() << "\tSkipped Add - state already seen\n");
384 DEBUG(dbgs() << "\tSkipped Add - no final resources available\n");
388 // If the current resource can be accommodated, check the next
389 // stage in InsnClass for available resources.
391 if (ResultingResourceState != prevState) {
392 DEBUG(dbgs() << "\n");
393 AddInsnClassStages(InsnClass, ComboBitToBitsMap,
394 chkstage - 1, numstages,
395 ResultingResourceState, origState,
396 VisitedResourceStates, PossibleStates);
398 DEBUG(dbgs() << "\tSkipped Add - no resources available\n");
407 // canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
408 // may be a valid transition from this state i.e., can an instruction of type
409 // InsnClass be added to the packet represented by this state.
411 // Note that this routine is performing conservative checks that can be
412 // quickly executed acting as a filter before calling AddInsnClassStages.
413 // Any cases allowed through here will be caught later in AddInsnClassStages
414 // which performs the more expensive exact check.
416 bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
417 std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
418 for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
419 SI != stateInfo.end(); ++SI) {
421 // Check to see if all required resources are available.
422 bool available = true;
424 // Inspect each stage independently.
425 // note: This is a conservative check as we aren't checking for
426 // possible resource competition between the stages themselves
427 // The full cross product is examined later in AddInsnClass.
428 for (unsigned i = 0; i < InsnClass.size(); ++i) {
429 unsigned resources = *SI;
430 if ((~resources & InsnClass[i]) == 0) {
434 // Make sure _all_ resources for a combo function are available.
435 // note: This is a quick conservative check as it won't catch an
436 // unscheduleable combo if this stage is an OR expression
437 // containing a combo.
438 // These cases are caught later in AddInsnClass.
439 unsigned combo = ComboBitToBitsMap[InsnClass[i]];
440 if (combo && ((~resources & combo) != combo)) {
441 DEBUG(dbgs() << "\tSkipped canMaybeAdd 0x" << utohexstr(resources)
442 << " - combo op 0x" << utohexstr(InsnClass[i])
443 << " (0x" << utohexstr(combo) <<") cannot be scheduled\n");
457 const State &DFA::newState() {
458 auto IterPair = states.insert(State());
459 assert(IterPair.second && "State already exists");
460 return *IterPair.first;
463 int State::currentStateNum = 0;
465 DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
466 TargetName(CodeGenTarget(R).getName()),
467 allInsnClasses(), Records(R) {}
471 // writeTableAndAPI - Print out a table representing the DFA and the
472 // associated API to create a DFA packetizer.
475 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
477 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
481 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
483 int maxResources, int numCombos, int maxStages) {
485 unsigned numStates = states.size();
487 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
488 DEBUG(dbgs() << "writeTableAndAPI\n");
489 DEBUG(dbgs() << "Total states: " << numStates << "\n");
491 OS << "namespace llvm {\n";
493 OS << "\n// Input format:\n";
494 OS << "#define DFA_MAX_RESTERMS " << DFA_MAX_RESTERMS
495 << "\t// maximum AND'ed resource terms\n";
496 OS << "#define DFA_MAX_RESOURCES " << DFA_MAX_RESOURCES
497 << "\t// maximum resource bits in one term\n";
499 OS << "\n// " << TargetName << "DFAStateInputTable[][2] = "
500 << "pairs of <Input, NextState> for all valid\n";
501 OS << "// transitions.\n";
502 OS << "// " << numStates << "\tstates\n";
503 OS << "// " << numInsnClasses << "\tinstruction classes\n";
504 OS << "// " << maxResources << "\tresources max\n";
505 OS << "// " << numCombos << "\tcombo resources\n";
506 OS << "// " << maxStages << "\tstages max\n";
507 OS << "const " << DFA_TBLTYPE << " "
508 << TargetName << "DFAStateInputTable[][2] = {\n";
510 // This table provides a map to the beginning of the transitions for State s
511 // in DFAStateInputTable.
512 std::vector<int> StateEntry(numStates+1);
513 static const std::string SentinelEntry = "{-1, -1}";
515 // Tracks the total valid transitions encountered so far. It is used
516 // to construct the StateEntry table.
517 int ValidTransitions = 0;
518 DFA::StateSet::iterator SI = states.begin();
519 for (unsigned i = 0; i < numStates; ++i, ++SI) {
520 assert ((SI->stateNum == (int) i) && "Mismatch in state numbers");
521 StateEntry[i] = ValidTransitions;
522 for (State::TransitionMap::iterator
523 II = SI->Transitions.begin(), IE = SI->Transitions.end();
525 OS << "{0x" << utohexstr(DFAPacketizer::getInsnInput(II->first)) << ", "
526 << II->second->stateNum
529 ValidTransitions += SI->Transitions.size();
531 // If there are no valid transitions from this stage, we need a sentinel
533 if (ValidTransitions == StateEntry[i]) {
534 OS << SentinelEntry << ",\t";
538 OS << " // state " << i << ": " << StateEntry[i];
539 if (StateEntry[i] != (ValidTransitions-1)) { // More than one transition.
540 OS << "-" << (ValidTransitions-1);
545 // Print out a sentinel entry at the end of the StateInputTable. This is
546 // needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
547 OS << SentinelEntry << "\t";
548 OS << " // state " << numStates << ": " << ValidTransitions;
552 OS << "// " << TargetName << "DFAStateEntryTable[i] = "
553 << "Index of the first entry in DFAStateInputTable for\n";
555 << "the ith state.\n";
556 OS << "// " << numStates << " states\n";
557 OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
559 // Multiply i by 2 since each entry in DFAStateInputTable is a set of
561 unsigned lastState = 0;
562 for (unsigned i = 0; i < numStates; ++i) {
563 if (i && ((i % 10) == 0)) {
565 OS << " // states " << (i-10) << ":" << lastState << "\n";
567 OS << StateEntry[i] << ", ";
570 // Print out the index to the sentinel entry in StateInputTable
571 OS << ValidTransitions << ", ";
572 OS << " // states " << (lastState+1) << ":" << numStates << "\n";
575 OS << "} // namespace\n";
579 // Emit DFA Packetizer tables if the target is a VLIW machine.
581 std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
582 OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
583 OS << "namespace llvm {\n";
584 OS << "DFAPacketizer *" << SubTargetClassName << "::"
585 << "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
586 << " return new DFAPacketizer(IID, " << TargetName
587 << "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
588 OS << "} // End llvm namespace \n";
593 // collectAllFuncUnits - Construct a map of function unit names to bits.
595 int DFAPacketizerEmitter::collectAllFuncUnits(
596 std::vector<Record*> &ProcItinList,
597 std::map<std::string, unsigned> &FUNameToBitsMap,
600 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
601 DEBUG(dbgs() << "collectAllFuncUnits");
602 DEBUG(dbgs() << " (" << ProcItinList.size() << " itineraries)\n");
605 // Parse functional units for all the itineraries.
606 for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
607 Record *Proc = ProcItinList[i];
608 const std::string &ProcName = Proc->getName();
609 std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
611 DEBUG(dbgs() << " FU:" << i
612 << " (" << FUs.size() << " FUs) "
616 // Convert macros to bits for each stage.
617 unsigned numFUs = FUs.size();
618 for (unsigned j = 0; j < numFUs; ++j) {
619 assert ((j < DFA_MAX_RESOURCES) &&
620 "Exceeded maximum number of representable resources");
621 unsigned FuncResources = (unsigned) (1U << j);
622 FUNameToBitsMap[FUs[j]->getName()] = FuncResources;
623 DEBUG(dbgs() << " " << FUs[j]->getName()
624 << ":0x" << utohexstr(FuncResources));
626 if (((int) numFUs) > maxFUs) {
630 DEBUG(dbgs() << "\n");
636 // collectAllComboFuncs - Construct a map from a combo function unit bit to
637 // the bits of all included functional units.
639 int DFAPacketizerEmitter::collectAllComboFuncs(
640 std::vector<Record*> &ComboFuncList,
641 std::map<std::string, unsigned> &FUNameToBitsMap,
642 std::map<unsigned, unsigned> &ComboBitToBitsMap,
644 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
645 DEBUG(dbgs() << "collectAllComboFuncs");
646 DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n");
649 for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) {
650 Record *Func = ComboFuncList[i];
651 const std::string &ProcName = Func->getName();
652 std::vector<Record*> FUs = Func->getValueAsListOfDefs("CFD");
654 DEBUG(dbgs() << " CFD:" << i
655 << " (" << FUs.size() << " combo FUs) "
656 << ProcName << "\n");
658 // Convert macros to bits for each stage.
659 for (unsigned j = 0, N = FUs.size(); j < N; ++j) {
660 assert ((j < DFA_MAX_RESOURCES) &&
661 "Exceeded maximum number of DFA resources");
662 Record *FuncData = FUs[j];
663 Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc");
664 const std::vector<Record*> &FuncList =
665 FuncData->getValueAsListOfDefs("FuncList");
666 std::string ComboFuncName = ComboFunc->getName();
667 unsigned ComboBit = FUNameToBitsMap[ComboFuncName];
668 unsigned ComboResources = ComboBit;
669 DEBUG(dbgs() << " combo: " << ComboFuncName
670 << ":0x" << utohexstr(ComboResources) << "\n");
671 for (unsigned k = 0, M = FuncList.size(); k < M; ++k) {
672 std::string FuncName = FuncList[k]->getName();
673 unsigned FuncResources = FUNameToBitsMap[FuncName];
674 DEBUG(dbgs() << " " << FuncName
675 << ":0x" << utohexstr(FuncResources) << "\n");
676 ComboResources |= FuncResources;
678 ComboBitToBitsMap[ComboBit] = ComboResources;
680 DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x"
681 << utohexstr(ComboBit) << " = 0x"
682 << utohexstr(ComboResources) << "\n");
690 // collectOneInsnClass - Populate allInsnClasses with one instruction class
692 int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName,
693 std::vector<Record*> &ProcItinList,
694 std::map<std::string, unsigned> &FUNameToBitsMap,
697 // Collect instruction classes.
698 Record *ItinDef = ItinData->getValueAsDef("TheClass");
700 const std::vector<Record*> &StageList =
701 ItinData->getValueAsListOfDefs("Stages");
703 // The number of stages.
704 unsigned NStages = StageList.size();
706 DEBUG(dbgs() << " " << ItinDef->getName()
709 std::vector<unsigned> UnitBits;
711 // Compute the bitwise or of each unit used in this stage.
712 for (unsigned i = 0; i < NStages; ++i) {
713 const Record *Stage = StageList[i];
716 const std::vector<Record*> &UnitList =
717 Stage->getValueAsListOfDefs("Units");
719 DEBUG(dbgs() << " stage:" << i
720 << " [" << UnitList.size() << " units]:");
721 unsigned dbglen = 26; // cursor after stage dbgs
723 // Compute the bitwise or of each unit used in this stage.
724 unsigned UnitBitValue = 0;
725 for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
726 // Conduct bitwise or.
727 std::string UnitName = UnitList[j]->getName();
728 DEBUG(dbgs() << " " << j << ":" << UnitName);
729 dbglen += 3 + UnitName.length();
730 assert(FUNameToBitsMap.count(UnitName));
731 UnitBitValue |= FUNameToBitsMap[UnitName];
734 if (UnitBitValue != 0)
735 UnitBits.push_back(UnitBitValue);
737 while (dbglen <= 64) { // line up bits dbgs
739 DEBUG(dbgs() << "\t");
741 DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
744 if (UnitBits.size() > 0)
745 allInsnClasses.push_back(UnitBits);
747 DEBUG(dbgs() << " ");
748 dbgsInsnClass(UnitBits);
749 DEBUG(dbgs() << "\n");
755 // collectAllInsnClasses - Populate allInsnClasses which is a set of units
756 // used in each stage.
758 int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName,
759 std::vector<Record*> &ProcItinList,
760 std::map<std::string, unsigned> &FUNameToBitsMap,
761 std::vector<Record*> &ItinDataList,
764 // Collect all instruction classes.
765 unsigned M = ItinDataList.size();
767 int numInsnClasses = 0;
768 DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"
769 << "collectAllInsnClasses "
771 << " (" << M << " classes)\n");
773 // Collect stages for each instruction class for all itinerary data
774 for (unsigned j = 0; j < M; j++) {
775 Record *ItinData = ItinDataList[j];
776 int NStages = collectOneInsnClass(ProcName, ProcItinList,
777 FUNameToBitsMap, ItinData, OS);
778 if (NStages > maxStages) {
783 return numInsnClasses;
787 // Run the worklist algorithm to generate the DFA.
789 void DFAPacketizerEmitter::run(raw_ostream &OS) {
791 // Collect processor iteraries.
792 std::vector<Record*> ProcItinList =
793 Records.getAllDerivedDefinitions("ProcessorItineraries");
796 // Collect the Functional units.
798 std::map<std::string, unsigned> FUNameToBitsMap;
799 int maxResources = 0;
800 collectAllFuncUnits(ProcItinList,
801 FUNameToBitsMap, maxResources, OS);
804 // Collect the Combo Functional units.
806 std::map<unsigned, unsigned> ComboBitToBitsMap;
807 std::vector<Record*> ComboFuncList =
808 Records.getAllDerivedDefinitions("ComboFuncUnits");
809 int numCombos = collectAllComboFuncs(ComboFuncList,
810 FUNameToBitsMap, ComboBitToBitsMap, OS);
813 // Collect the itineraries.
816 int numInsnClasses = 0;
817 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
818 Record *Proc = ProcItinList[i];
820 // Get processor itinerary name.
821 const std::string &ProcName = Proc->getName();
824 if (ProcName == "NoItineraries")
827 // Sanity check for at least one instruction itinerary class.
828 unsigned NItinClasses =
829 Records.getAllDerivedDefinitions("InstrItinClass").size();
830 if (NItinClasses == 0)
833 // Get itinerary data list.
834 std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
836 // Collect all instruction classes
837 numInsnClasses += collectAllInsnClasses(ProcName, ProcItinList,
838 FUNameToBitsMap, ItinDataList, maxStages, OS);
842 // Run a worklist algorithm to generate the DFA.
845 const State *Initial = &D.newState();
846 Initial->isInitial = true;
847 Initial->stateInfo.insert(0x0);
848 SmallVector<const State*, 32> WorkList;
849 // std::queue<State*> WorkList;
850 std::map<std::set<unsigned>, const State*> Visited;
852 WorkList.push_back(Initial);
855 // Worklist algorithm to create a DFA for processor resource tracking.
856 // C = {set of InsnClasses}
857 // Begin with initial node in worklist. Initial node does not have
858 // any consumed resources,
859 // ResourceState = 0x0
861 // While worklist != empty
862 // S = first element of worklist
863 // For every instruction class C
864 // if we can accommodate C in S:
865 // S' = state with resource states = {S Union C}
866 // Add a new transition: S x C -> S'
867 // If S' is not in Visited:
868 // Add S' to worklist
871 while (!WorkList.empty()) {
872 const State *current = WorkList.pop_back_val();
873 DEBUG(dbgs() << "---------------------\n");
874 DEBUG(dbgs() << "Processing state: " << current->stateNum << " - ");
875 dbgsStateInfo(current->stateInfo);
876 DEBUG(dbgs() << "\n");
877 for (unsigned i = 0; i < allInsnClasses.size(); i++) {
878 std::vector<unsigned> InsnClass = allInsnClasses[i];
879 DEBUG(dbgs() << i << " ");
880 dbgsInsnClass(InsnClass);
881 DEBUG(dbgs() << "\n");
883 std::set<unsigned> NewStateResources;
885 // If we haven't already created a transition for this input
886 // and the state can accommodate this InsnClass, create a transition.
888 if (!current->hasTransition(InsnClass) &&
889 current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
890 const State *NewState = NULL;
891 current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
892 if (NewStateResources.size() == 0) {
893 DEBUG(dbgs() << " Skipped - no new states generated\n");
897 DEBUG(dbgs() << "\t");
898 dbgsStateInfo(NewStateResources);
899 DEBUG(dbgs() << "\n");
902 // If we have seen this state before, then do not create a new state.
904 auto VI = Visited.find(NewStateResources);
905 if (VI != Visited.end()) {
906 NewState = VI->second;
907 DEBUG(dbgs() << "\tFound existing state: "
908 << NewState->stateNum << " - ");
909 dbgsStateInfo(NewState->stateInfo);
910 DEBUG(dbgs() << "\n");
912 NewState = &D.newState();
913 NewState->stateInfo = NewStateResources;
914 Visited[NewStateResources] = NewState;
915 WorkList.push_back(NewState);
916 DEBUG(dbgs() << "\tAccepted new state: "
917 << NewState->stateNum << " - ");
918 dbgsStateInfo(NewState->stateInfo);
919 DEBUG(dbgs() << "\n");
922 current->addTransition(InsnClass, NewState);
927 // Print out the table.
928 D.writeTableAndAPI(OS, TargetName,
929 numInsnClasses, maxResources, numCombos, maxStages);
934 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
935 emitSourceFileHeader("Target DFA Packetizer Tables", OS);
936 DFAPacketizerEmitter(RK).run(OS);
939 } // End llvm namespace