1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits a target specifier matcher for converting parsed
11 // assembly operands in the MCInst structures. It also emits a matcher for
12 // custom operand parsing.
14 // Converting assembly operands into MCInst structures
15 // ---------------------------------------------------
17 // The input to the target specific matcher is a list of literal tokens and
18 // operands. The target specific parser should generally eliminate any syntax
19 // which is not relevant for matching; for example, comma tokens should have
20 // already been consumed and eliminated by the parser. Most instructions will
21 // end up with a single literal token (the instruction name) and some number of
24 // Some example inputs, for X86:
25 // 'addl' (immediate ...) (register ...)
26 // 'add' (immediate ...) (memory ...)
29 // The assembly matcher is responsible for converting this input into a precise
30 // machine instruction (i.e., an instruction with a well defined encoding). This
31 // mapping has several properties which complicate matching:
33 // - It may be ambiguous; many architectures can legally encode particular
34 // variants of an instruction in different ways (for example, using a smaller
35 // encoding for small immediates). Such ambiguities should never be
36 // arbitrarily resolved by the assembler, the assembler is always responsible
37 // for choosing the "best" available instruction.
39 // - It may depend on the subtarget or the assembler context. Instructions
40 // which are invalid for the current mode, but otherwise unambiguous (e.g.,
41 // an SSE instruction in a file being assembled for i486) should be accepted
42 // and rejected by the assembler front end. However, if the proper encoding
43 // for an instruction is dependent on the assembler context then the matcher
44 // is responsible for selecting the correct machine instruction for the
47 // The core matching algorithm attempts to exploit the regularity in most
48 // instruction sets to quickly determine the set of possibly matching
49 // instructions, and the simplify the generated code. Additionally, this helps
50 // to ensure that the ambiguities are intentionally resolved by the user.
52 // The matching is divided into two distinct phases:
54 // 1. Classification: Each operand is mapped to the unique set which (a)
55 // contains it, and (b) is the largest such subset for which a single
56 // instruction could match all members.
58 // For register classes, we can generate these subgroups automatically. For
59 // arbitrary operands, we expect the user to define the classes and their
60 // relations to one another (for example, 8-bit signed immediates as a
61 // subset of 32-bit immediates).
63 // By partitioning the operands in this way, we guarantee that for any
64 // tuple of classes, any single instruction must match either all or none
65 // of the sets of operands which could classify to that tuple.
67 // In addition, the subset relation amongst classes induces a partial order
68 // on such tuples, which we use to resolve ambiguities.
70 // 2. The input can now be treated as a tuple of classes (static tokens are
71 // simple singleton sets). Each such tuple should generally map to a single
72 // instruction (we currently ignore cases where this isn't true, whee!!!),
73 // which we can emit a simple matcher for.
75 // Custom Operand Parsing
76 // ----------------------
78 // Some targets need a custom way to parse operands, some specific instructions
79 // can contain arguments that can represent processor flags and other kinds of
80 // identifiers that need to be mapped to specific values in the final encoded
81 // instructions. The target specific custom operand parsing works in the
84 // 1. A operand match table is built, each entry contains a mnemonic, an
85 // operand class, a mask for all operand positions for that same
86 // class/mnemonic and target features to be checked while trying to match.
88 // 2. The operand matcher will try every possible entry with the same
89 // mnemonic and will check if the target feature for this mnemonic also
90 // matches. After that, if the operand to be matched has its index
91 // present in the mask, a successful match occurs. Otherwise, fallback
92 // to the regular operand parsing.
94 // 3. For a match success, each operand class that has a 'ParserMethod'
95 // becomes part of a switch from where the custom method is called.
97 //===----------------------------------------------------------------------===//
99 #include "CodeGenTarget.h"
100 #include "llvm/ADT/PointerUnion.h"
101 #include "llvm/ADT/STLExtras.h"
102 #include "llvm/ADT/SmallPtrSet.h"
103 #include "llvm/ADT/SmallVector.h"
104 #include "llvm/ADT/StringExtras.h"
105 #include "llvm/Support/CommandLine.h"
106 #include "llvm/Support/Debug.h"
107 #include "llvm/Support/ErrorHandling.h"
108 #include "llvm/TableGen/Error.h"
109 #include "llvm/TableGen/Record.h"
110 #include "llvm/TableGen/StringMatcher.h"
111 #include "llvm/TableGen/StringToOffsetTable.h"
112 #include "llvm/TableGen/TableGenBackend.h"
118 using namespace llvm;
120 #define DEBUG_TYPE "asm-matcher-emitter"
122 static cl::opt<std::string>
123 MatchPrefix("match-prefix", cl::init(""),
124 cl::desc("Only match instructions with the given prefix"));
127 class AsmMatcherInfo;
128 struct SubtargetFeatureInfo;
130 // Register sets are used as keys in some second-order sets TableGen creates
131 // when generating its data structures. This means that the order of two
132 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
133 // can even affect compiler output (at least seen in diagnostics produced when
134 // all matches fail). So we use a type that sorts them consistently.
135 typedef std::set<Record*, LessRecordByID> RegisterSet;
137 class AsmMatcherEmitter {
138 RecordKeeper &Records;
140 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
142 void run(raw_ostream &o);
145 /// ClassInfo - Helper class for storing the information about a particular
146 /// class of operands which can be matched.
149 /// Invalid kind, for use as a sentinel value.
152 /// The class for a particular token.
155 /// The (first) register class, subsequent register classes are
156 /// RegisterClass0+1, and so on.
159 /// The (first) user defined class, subsequent user defined classes are
160 /// UserClass0+1, and so on.
164 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
165 /// N) for the Nth user defined class.
168 /// SuperClasses - The super classes of this class. Note that for simplicities
169 /// sake user operands only record their immediate super class, while register
170 /// operands include all superclasses.
171 std::vector<ClassInfo*> SuperClasses;
173 /// Name - The full class name, suitable for use in an enum.
176 /// ClassName - The unadorned generic name for this class (e.g., Token).
177 std::string ClassName;
179 /// ValueName - The name of the value this class represents; for a token this
180 /// is the literal token string, for an operand it is the TableGen class (or
181 /// empty if this is a derived class).
182 std::string ValueName;
184 /// PredicateMethod - The name of the operand method to test whether the
185 /// operand matches this class; this is not valid for Token or register kinds.
186 std::string PredicateMethod;
188 /// RenderMethod - The name of the operand method to add this operand to an
189 /// MCInst; this is not valid for Token or register kinds.
190 std::string RenderMethod;
192 /// ParserMethod - The name of the operand method to do a target specific
193 /// parsing on the operand.
194 std::string ParserMethod;
196 /// For register classes: the records for all the registers in this class.
197 RegisterSet Registers;
199 /// For custom match classes: the diagnostic kind for when the predicate fails.
200 std::string DiagnosticType;
202 /// isRegisterClass() - Check if this is a register class.
203 bool isRegisterClass() const {
204 return Kind >= RegisterClass0 && Kind < UserClass0;
207 /// isUserClass() - Check if this is a user defined class.
208 bool isUserClass() const {
209 return Kind >= UserClass0;
212 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
213 /// are related if they are in the same class hierarchy.
214 bool isRelatedTo(const ClassInfo &RHS) const {
215 // Tokens are only related to tokens.
216 if (Kind == Token || RHS.Kind == Token)
217 return Kind == Token && RHS.Kind == Token;
219 // Registers classes are only related to registers classes, and only if
220 // their intersection is non-empty.
221 if (isRegisterClass() || RHS.isRegisterClass()) {
222 if (!isRegisterClass() || !RHS.isRegisterClass())
226 std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
227 std::set_intersection(Registers.begin(), Registers.end(),
228 RHS.Registers.begin(), RHS.Registers.end(),
229 II, LessRecordByID());
234 // Otherwise we have two users operands; they are related if they are in the
235 // same class hierarchy.
237 // FIXME: This is an oversimplification, they should only be related if they
238 // intersect, however we don't have that information.
239 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
240 const ClassInfo *Root = this;
241 while (!Root->SuperClasses.empty())
242 Root = Root->SuperClasses.front();
244 const ClassInfo *RHSRoot = &RHS;
245 while (!RHSRoot->SuperClasses.empty())
246 RHSRoot = RHSRoot->SuperClasses.front();
248 return Root == RHSRoot;
251 /// isSubsetOf - Test whether this class is a subset of \p RHS.
252 bool isSubsetOf(const ClassInfo &RHS) const {
253 // This is a subset of RHS if it is the same class...
257 // ... or if any of its super classes are a subset of RHS.
258 for (const ClassInfo *CI : SuperClasses)
259 if (CI->isSubsetOf(RHS))
265 /// operator< - Compare two classes.
266 bool operator<(const ClassInfo &RHS) const {
270 // Unrelated classes can be ordered by kind.
271 if (!isRelatedTo(RHS))
272 return Kind < RHS.Kind;
276 llvm_unreachable("Invalid kind!");
279 // This class precedes the RHS if it is a proper subset of the RHS.
282 if (RHS.isSubsetOf(*this))
285 // Otherwise, order by name to ensure we have a total ordering.
286 return ValueName < RHS.ValueName;
291 /// MatchableInfo - Helper class for storing the necessary information for an
292 /// instruction or alias which is capable of being matched.
293 struct MatchableInfo {
295 /// Token - This is the token that the operand came from.
298 /// The unique class instance this operand should match.
301 /// The operand name this is, if anything.
304 /// The suboperand index within SrcOpName, or -1 for the entire operand.
307 /// Register record if this token is singleton register.
308 Record *SingletonReg;
310 explicit AsmOperand(StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1),
311 SingletonReg(nullptr) {}
314 /// ResOperand - This represents a single operand in the result instruction
315 /// generated by the match. In cases (like addressing modes) where a single
316 /// assembler operand expands to multiple MCOperands, this represents the
317 /// single assembler operand, not the MCOperand.
320 /// RenderAsmOperand - This represents an operand result that is
321 /// generated by calling the render method on the assembly operand. The
322 /// corresponding AsmOperand is specified by AsmOperandNum.
325 /// TiedOperand - This represents a result operand that is a duplicate of
326 /// a previous result operand.
329 /// ImmOperand - This represents an immediate value that is dumped into
333 /// RegOperand - This represents a fixed register that is dumped in.
338 /// This is the operand # in the AsmOperands list that this should be
340 unsigned AsmOperandNum;
342 /// TiedOperandNum - This is the (earlier) result operand that should be
344 unsigned TiedOperandNum;
346 /// ImmVal - This is the immediate value added to the instruction.
349 /// Register - This is the register record.
353 /// MINumOperands - The number of MCInst operands populated by this
355 unsigned MINumOperands;
357 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
359 X.Kind = RenderAsmOperand;
360 X.AsmOperandNum = AsmOpNum;
361 X.MINumOperands = NumOperands;
365 static ResOperand getTiedOp(unsigned TiedOperandNum) {
367 X.Kind = TiedOperand;
368 X.TiedOperandNum = TiedOperandNum;
373 static ResOperand getImmOp(int64_t Val) {
381 static ResOperand getRegOp(Record *Reg) {
390 /// AsmVariantID - Target's assembly syntax variant no.
393 /// TheDef - This is the definition of the instruction or InstAlias that this
394 /// matchable came from.
395 Record *const TheDef;
397 /// DefRec - This is the definition that it came from.
398 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
400 const CodeGenInstruction *getResultInst() const {
401 if (DefRec.is<const CodeGenInstruction*>())
402 return DefRec.get<const CodeGenInstruction*>();
403 return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
406 /// ResOperands - This is the operand list that should be built for the result
408 SmallVector<ResOperand, 8> ResOperands;
410 /// AsmString - The assembly string for this instruction (with variants
411 /// removed), e.g. "movsx $src, $dst".
412 std::string AsmString;
414 /// Mnemonic - This is the first token of the matched instruction, its
418 /// AsmOperands - The textual operands that this instruction matches,
419 /// annotated with a class and where in the OperandList they were defined.
420 /// This directly corresponds to the tokenized AsmString after the mnemonic is
422 SmallVector<AsmOperand, 8> AsmOperands;
424 /// Predicates - The required subtarget features to match this instruction.
425 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
427 /// ConversionFnKind - The enum value which is passed to the generated
428 /// convertToMCInst to convert parsed operands into an MCInst for this
430 std::string ConversionFnKind;
432 /// If this instruction is deprecated in some form.
435 MatchableInfo(const CodeGenInstruction &CGI)
436 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
437 AsmString(CGI.AsmString) {
440 MatchableInfo(const CodeGenInstAlias *Alias)
441 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
442 AsmString(Alias->AsmString) {
445 // Two-operand aliases clone from the main matchable, but mark the second
446 // operand as a tied operand of the first for purposes of the assembler.
447 void formTwoOperandAlias(StringRef Constraint);
449 void initialize(const AsmMatcherInfo &Info,
450 SmallPtrSetImpl<Record*> &SingletonRegisters,
451 int AsmVariantNo, std::string &RegisterPrefix);
453 /// validate - Return true if this matchable is a valid thing to match against
454 /// and perform a bunch of validity checking.
455 bool validate(StringRef CommentDelimiter, bool Hack) const;
457 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
458 /// if present, from specified token.
460 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info,
461 std::string &RegisterPrefix);
463 /// findAsmOperand - Find the AsmOperand with the specified name and
464 /// suboperand index.
465 int findAsmOperand(StringRef N, int SubOpIdx) const {
466 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
467 if (N == AsmOperands[i].SrcOpName &&
468 SubOpIdx == AsmOperands[i].SubOpIdx)
473 /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
474 /// This does not check the suboperand index.
475 int findAsmOperandNamed(StringRef N) const {
476 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
477 if (N == AsmOperands[i].SrcOpName)
482 void buildInstructionResultOperands();
483 void buildAliasResultOperands();
485 /// operator< - Compare two matchables.
486 bool operator<(const MatchableInfo &RHS) const {
487 // The primary comparator is the instruction mnemonic.
488 if (Mnemonic != RHS.Mnemonic)
489 return Mnemonic < RHS.Mnemonic;
491 if (AsmOperands.size() != RHS.AsmOperands.size())
492 return AsmOperands.size() < RHS.AsmOperands.size();
494 // Compare lexicographically by operand. The matcher validates that other
495 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
496 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
497 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
499 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
503 // Give matches that require more features higher precedence. This is useful
504 // because we cannot define AssemblerPredicates with the negation of
505 // processor features. For example, ARM v6 "nop" may be either a HINT or
506 // MOV. With v6, we want to match HINT. The assembler has no way to
507 // predicate MOV under "NoV6", but HINT will always match first because it
508 // requires V6 while MOV does not.
509 if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
510 return RequiredFeatures.size() > RHS.RequiredFeatures.size();
515 /// couldMatchAmbiguouslyWith - Check whether this matchable could
516 /// ambiguously match the same set of operands as \p RHS (without being a
517 /// strictly superior match).
518 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) {
519 // The primary comparator is the instruction mnemonic.
520 if (Mnemonic != RHS.Mnemonic)
523 // The number of operands is unambiguous.
524 if (AsmOperands.size() != RHS.AsmOperands.size())
527 // Otherwise, make sure the ordering of the two instructions is unambiguous
528 // by checking that either (a) a token or operand kind discriminates them,
529 // or (b) the ordering among equivalent kinds is consistent.
531 // Tokens and operand kinds are unambiguous (assuming a correct target
533 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
534 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
535 AsmOperands[i].Class->Kind == ClassInfo::Token)
536 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
537 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
540 // Otherwise, this operand could commute if all operands are equivalent, or
541 // there is a pair of operands that compare less than and a pair that
542 // compare greater than.
543 bool HasLT = false, HasGT = false;
544 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
545 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
547 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
551 return !(HasLT ^ HasGT);
557 void tokenizeAsmString(const AsmMatcherInfo &Info);
560 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget
561 /// feature which participates in instruction matching.
562 struct SubtargetFeatureInfo {
563 /// \brief The predicate record for this feature.
566 /// \brief An unique index assigned to represent this feature.
569 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
571 /// \brief The name of the enumerated constant identifying this feature.
572 std::string getEnumName() const {
573 return "Feature_" + TheDef->getName();
577 errs() << getEnumName() << " " << Index << "\n";
582 struct OperandMatchEntry {
583 unsigned OperandMask;
587 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci,
590 X.OperandMask = opMask;
598 class AsmMatcherInfo {
601 RecordKeeper &Records;
603 /// The tablegen AsmParser record.
606 /// Target - The target information.
607 CodeGenTarget &Target;
609 /// The classes which are needed for matching.
610 std::vector<ClassInfo*> Classes;
612 /// The information on the matchables to match.
613 std::vector<MatchableInfo*> Matchables;
615 /// Info for custom matching operands by user defined methods.
616 std::vector<OperandMatchEntry> OperandMatchInfo;
618 /// Map of Register records to their class information.
619 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
620 RegisterClassesTy RegisterClasses;
622 /// Map of Predicate records to their subtarget information.
623 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures;
625 /// Map of AsmOperandClass records to their class information.
626 std::map<Record*, ClassInfo*> AsmOperandClasses;
629 /// Map of token to class information which has already been constructed.
630 std::map<std::string, ClassInfo*> TokenClasses;
632 /// Map of RegisterClass records to their class information.
633 std::map<Record*, ClassInfo*> RegisterClassClasses;
636 /// getTokenClass - Lookup or create the class for the given token.
637 ClassInfo *getTokenClass(StringRef Token);
639 /// getOperandClass - Lookup or create the class for the given operand.
640 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
642 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
644 /// buildRegisterClasses - Build the ClassInfo* instances for register
646 void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
648 /// buildOperandClasses - Build the ClassInfo* instances for user defined
650 void buildOperandClasses();
652 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
654 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
655 MatchableInfo::AsmOperand &Op);
658 AsmMatcherInfo(Record *AsmParser,
659 CodeGenTarget &Target,
660 RecordKeeper &Records);
662 /// buildInfo - Construct the various tables used during matching.
665 /// buildOperandMatchInfo - Build the necessary information to handle user
666 /// defined operand parsing methods.
667 void buildOperandMatchInfo();
669 /// getSubtargetFeature - Lookup or create the subtarget feature info for the
671 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
672 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
673 std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I =
674 SubtargetFeatures.find(Def);
675 return I == SubtargetFeatures.end() ? nullptr : I->second;
678 RecordKeeper &getRecords() const {
683 } // End anonymous namespace
685 void MatchableInfo::dump() {
686 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
688 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
689 AsmOperand &Op = AsmOperands[i];
690 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - ";
691 errs() << '\"' << Op.Token << "\"\n";
695 static std::pair<StringRef, StringRef>
696 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
697 // Split via the '='.
698 std::pair<StringRef, StringRef> Ops = S.split('=');
699 if (Ops.second == "")
700 PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
701 // Trim whitespace and the leading '$' on the operand names.
702 size_t start = Ops.first.find_first_of('$');
703 if (start == std::string::npos)
704 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
705 Ops.first = Ops.first.slice(start + 1, std::string::npos);
706 size_t end = Ops.first.find_last_of(" \t");
707 Ops.first = Ops.first.slice(0, end);
708 // Now the second operand.
709 start = Ops.second.find_first_of('$');
710 if (start == std::string::npos)
711 PrintFatalError(Loc, "expected '$' prefix on asm operand name");
712 Ops.second = Ops.second.slice(start + 1, std::string::npos);
713 end = Ops.second.find_last_of(" \t");
714 Ops.first = Ops.first.slice(0, end);
718 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
719 // Figure out which operands are aliased and mark them as tied.
720 std::pair<StringRef, StringRef> Ops =
721 parseTwoOperandConstraint(Constraint, TheDef->getLoc());
723 // Find the AsmOperands that refer to the operands we're aliasing.
724 int SrcAsmOperand = findAsmOperandNamed(Ops.first);
725 int DstAsmOperand = findAsmOperandNamed(Ops.second);
726 if (SrcAsmOperand == -1)
727 PrintFatalError(TheDef->getLoc(),
728 "unknown source two-operand alias operand '" + Ops.first +
730 if (DstAsmOperand == -1)
731 PrintFatalError(TheDef->getLoc(),
732 "unknown destination two-operand alias operand '" +
735 // Find the ResOperand that refers to the operand we're aliasing away
736 // and update it to refer to the combined operand instead.
737 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
738 ResOperand &Op = ResOperands[i];
739 if (Op.Kind == ResOperand::RenderAsmOperand &&
740 Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
741 Op.AsmOperandNum = DstAsmOperand;
745 // Remove the AsmOperand for the alias operand.
746 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
747 // Adjust the ResOperand references to any AsmOperands that followed
748 // the one we just deleted.
749 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) {
750 ResOperand &Op = ResOperands[i];
753 // Nothing to do for operands that don't reference AsmOperands.
755 case ResOperand::RenderAsmOperand:
756 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
759 case ResOperand::TiedOperand:
760 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand)
767 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
768 SmallPtrSetImpl<Record*> &SingletonRegisters,
769 int AsmVariantNo, std::string &RegisterPrefix) {
770 AsmVariantID = AsmVariantNo;
772 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo);
774 tokenizeAsmString(Info);
776 // Compute the require features.
777 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates");
778 for (unsigned i = 0, e = Predicates.size(); i != e; ++i)
779 if (SubtargetFeatureInfo *Feature =
780 Info.getSubtargetFeature(Predicates[i]))
781 RequiredFeatures.push_back(Feature);
783 // Collect singleton registers, if used.
784 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
785 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix);
786 if (Record *Reg = AsmOperands[i].SingletonReg)
787 SingletonRegisters.insert(Reg);
790 const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
792 DepMask = TheDef->getValue("ComplexDeprecationPredicate");
795 DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
798 /// tokenizeAsmString - Tokenize a simplified assembly string.
799 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) {
800 StringRef String = AsmString;
803 for (unsigned i = 0, e = String.size(); i != e; ++i) {
813 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
816 if (!isspace(String[i]) && String[i] != ',')
817 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
823 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
827 assert(i != String.size() && "Invalid quoted character");
828 AsmOperands.push_back(AsmOperand(String.substr(i, 1)));
834 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
838 // If this isn't "${", treat like a normal token.
839 if (i + 1 == String.size() || String[i + 1] != '{') {
844 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}');
845 assert(End != String.end() && "Missing brace in operand reference!");
846 size_t EndPos = End - String.begin();
847 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1)));
854 if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) {
856 AsmOperands.push_back(AsmOperand(String.slice(Prev, i)));
866 if (InTok && Prev != String.size())
867 AsmOperands.push_back(AsmOperand(String.substr(Prev)));
869 // The first token of the instruction is the mnemonic, which must be a
870 // simple string, not a $foo variable or a singleton register.
871 if (AsmOperands.empty())
872 PrintFatalError(TheDef->getLoc(),
873 "Instruction '" + TheDef->getName() + "' has no tokens");
874 Mnemonic = AsmOperands[0].Token;
875 if (Mnemonic.empty())
876 PrintFatalError(TheDef->getLoc(),
877 "Missing instruction mnemonic");
878 // FIXME : Check and raise an error if it is a register.
879 if (Mnemonic[0] == '$')
880 PrintFatalError(TheDef->getLoc(),
881 "Invalid instruction mnemonic '" + Mnemonic + "'!");
883 // Remove the first operand, it is tracked in the mnemonic field.
884 AsmOperands.erase(AsmOperands.begin());
887 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const {
888 // Reject matchables with no .s string.
889 if (AsmString.empty())
890 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
892 // Reject any matchables with a newline in them, they should be marked
893 // isCodeGenOnly if they are pseudo instructions.
894 if (AsmString.find('\n') != std::string::npos)
895 PrintFatalError(TheDef->getLoc(),
896 "multiline instruction is not valid for the asmparser, "
897 "mark it isCodeGenOnly");
899 // Remove comments from the asm string. We know that the asmstring only
901 if (!CommentDelimiter.empty() &&
902 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
903 PrintFatalError(TheDef->getLoc(),
904 "asmstring for instruction has comment character in it, "
905 "mark it isCodeGenOnly");
907 // Reject matchables with operand modifiers, these aren't something we can
908 // handle, the target should be refactored to use operands instead of
911 // Also, check for instructions which reference the operand multiple times;
912 // this implies a constraint we would not honor.
913 std::set<std::string> OperandNames;
914 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
915 StringRef Tok = AsmOperands[i].Token;
916 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
917 PrintFatalError(TheDef->getLoc(),
918 "matchable with operand modifier '" + Tok +
919 "' not supported by asm matcher. Mark isCodeGenOnly!");
921 // Verify that any operand is only mentioned once.
922 // We reject aliases and ignore instructions for now.
923 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) {
925 PrintFatalError(TheDef->getLoc(),
926 "ERROR: matchable with tied operand '" + Tok +
927 "' can never be matched!");
928 // FIXME: Should reject these. The ARM backend hits this with $lane in a
929 // bunch of instructions. It is unclear what the right answer is.
931 errs() << "warning: '" << TheDef->getName() << "': "
932 << "ignoring instruction with tied operand '"
942 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
943 /// if present, from specified token.
945 extractSingletonRegisterForAsmOperand(unsigned OperandNo,
946 const AsmMatcherInfo &Info,
947 std::string &RegisterPrefix) {
948 StringRef Tok = AsmOperands[OperandNo].Token;
949 if (RegisterPrefix.empty()) {
950 std::string LoweredTok = Tok.lower();
951 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
952 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
956 if (!Tok.startswith(RegisterPrefix))
959 StringRef RegName = Tok.substr(RegisterPrefix.size());
960 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
961 AsmOperands[OperandNo].SingletonReg = Reg->TheDef;
963 // If there is no register prefix (i.e. "%" in "%eax"), then this may
964 // be some random non-register token, just ignore it.
968 static std::string getEnumNameForToken(StringRef Str) {
971 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
973 case '*': Res += "_STAR_"; break;
974 case '%': Res += "_PCT_"; break;
975 case ':': Res += "_COLON_"; break;
976 case '!': Res += "_EXCLAIM_"; break;
977 case '.': Res += "_DOT_"; break;
978 case '<': Res += "_LT_"; break;
979 case '>': Res += "_GT_"; break;
981 if ((*it >= 'A' && *it <= 'Z') ||
982 (*it >= 'a' && *it <= 'z') ||
983 (*it >= '0' && *it <= '9'))
986 Res += "_" + utostr((unsigned) *it) + "_";
993 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
994 ClassInfo *&Entry = TokenClasses[Token];
997 Entry = new ClassInfo();
998 Entry->Kind = ClassInfo::Token;
999 Entry->ClassName = "Token";
1000 Entry->Name = "MCK_" + getEnumNameForToken(Token);
1001 Entry->ValueName = Token;
1002 Entry->PredicateMethod = "<invalid>";
1003 Entry->RenderMethod = "<invalid>";
1004 Entry->ParserMethod = "";
1005 Entry->DiagnosticType = "";
1006 Classes.push_back(Entry);
1013 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1015 Record *Rec = OI.Rec;
1017 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1018 return getOperandClass(Rec, SubOpIdx);
1022 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1023 if (Rec->isSubClassOf("RegisterOperand")) {
1024 // RegisterOperand may have an associated ParserMatchClass. If it does,
1025 // use it, else just fall back to the underlying register class.
1026 const RecordVal *R = Rec->getValue("ParserMatchClass");
1027 if (!R || !R->getValue())
1028 PrintFatalError("Record `" + Rec->getName() +
1029 "' does not have a ParserMatchClass!\n");
1031 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1032 Record *MatchClass = DI->getDef();
1033 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1037 // No custom match class. Just use the register class.
1038 Record *ClassRec = Rec->getValueAsDef("RegClass");
1040 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1041 "' has no associated register class!\n");
1042 if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1044 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1048 if (Rec->isSubClassOf("RegisterClass")) {
1049 if (ClassInfo *CI = RegisterClassClasses[Rec])
1051 PrintFatalError(Rec->getLoc(), "register class has no class info!");
1054 if (!Rec->isSubClassOf("Operand"))
1055 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1056 "' does not derive from class Operand!\n");
1057 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1058 if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1061 PrintFatalError(Rec->getLoc(), "operand has no match class!");
1064 struct LessRegisterSet {
1065 bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1066 // std::set<T> defines its own compariso "operator<", but it
1067 // performs a lexicographical comparison by T's innate comparison
1068 // for some reason. We don't want non-deterministic pointer
1069 // comparisons so use this instead.
1070 return std::lexicographical_compare(LHS.begin(), LHS.end(),
1071 RHS.begin(), RHS.end(),
1076 void AsmMatcherInfo::
1077 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1078 const std::vector<CodeGenRegister*> &Registers =
1079 Target.getRegBank().getRegisters();
1080 ArrayRef<CodeGenRegisterClass*> RegClassList =
1081 Target.getRegBank().getRegClasses();
1083 typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1085 // The register sets used for matching.
1086 RegisterSetSet RegisterSets;
1088 // Gather the defined sets.
1089 for (const CodeGenRegisterClass *RC : RegClassList)
1090 RegisterSets.insert(RegisterSet(RC->getOrder().begin(),
1091 RC->getOrder().end()));
1093 // Add any required singleton sets.
1094 for (Record *Rec : SingletonRegisters) {
1095 RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1098 // Introduce derived sets where necessary (when a register does not determine
1099 // a unique register set class), and build the mapping of registers to the set
1100 // they should classify to.
1101 std::map<Record*, RegisterSet> RegisterMap;
1102 for (const CodeGenRegister *CGR : Registers) {
1103 // Compute the intersection of all sets containing this register.
1104 RegisterSet ContainingSet;
1106 for (const RegisterSet &RS : RegisterSets) {
1107 if (!RS.count(CGR->TheDef))
1110 if (ContainingSet.empty()) {
1116 std::swap(Tmp, ContainingSet);
1117 std::insert_iterator<RegisterSet> II(ContainingSet,
1118 ContainingSet.begin());
1119 std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1123 if (!ContainingSet.empty()) {
1124 RegisterSets.insert(ContainingSet);
1125 RegisterMap.insert(std::make_pair(CGR->TheDef, ContainingSet));
1129 // Construct the register classes.
1130 std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1132 for (const RegisterSet &RS : RegisterSets) {
1133 ClassInfo *CI = new ClassInfo();
1134 CI->Kind = ClassInfo::RegisterClass0 + Index;
1135 CI->ClassName = "Reg" + utostr(Index);
1136 CI->Name = "MCK_Reg" + utostr(Index);
1138 CI->PredicateMethod = ""; // unused
1139 CI->RenderMethod = "addRegOperands";
1141 // FIXME: diagnostic type.
1142 CI->DiagnosticType = "";
1143 Classes.push_back(CI);
1144 RegisterSetClasses.insert(std::make_pair(RS, CI));
1148 // Find the superclasses; we could compute only the subgroup lattice edges,
1149 // but there isn't really a point.
1150 for (const RegisterSet &RS : RegisterSets) {
1151 ClassInfo *CI = RegisterSetClasses[RS];
1152 for (const RegisterSet &RS2 : RegisterSets)
1154 std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1156 CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1159 // Name the register classes which correspond to a user defined RegisterClass.
1160 for (const CodeGenRegisterClass *RC : RegClassList) {
1161 // Def will be NULL for non-user defined register classes.
1162 Record *Def = RC->getDef();
1165 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC->getOrder().begin(),
1166 RC->getOrder().end())];
1167 if (CI->ValueName.empty()) {
1168 CI->ClassName = RC->getName();
1169 CI->Name = "MCK_" + RC->getName();
1170 CI->ValueName = RC->getName();
1172 CI->ValueName = CI->ValueName + "," + RC->getName();
1174 RegisterClassClasses.insert(std::make_pair(Def, CI));
1177 // Populate the map for individual registers.
1178 for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1179 ie = RegisterMap.end(); it != ie; ++it)
1180 RegisterClasses[it->first] = RegisterSetClasses[it->second];
1182 // Name the register classes which correspond to singleton registers.
1183 for (Record *Rec : SingletonRegisters) {
1184 ClassInfo *CI = RegisterClasses[Rec];
1185 assert(CI && "Missing singleton register class info!");
1187 if (CI->ValueName.empty()) {
1188 CI->ClassName = Rec->getName();
1189 CI->Name = "MCK_" + Rec->getName();
1190 CI->ValueName = Rec->getName();
1192 CI->ValueName = CI->ValueName + "," + Rec->getName();
1196 void AsmMatcherInfo::buildOperandClasses() {
1197 std::vector<Record*> AsmOperands =
1198 Records.getAllDerivedDefinitions("AsmOperandClass");
1200 // Pre-populate AsmOperandClasses map.
1201 for (Record *Rec : AsmOperands)
1202 AsmOperandClasses[Rec] = new ClassInfo();
1205 for (Record *Rec : AsmOperands) {
1206 ClassInfo *CI = AsmOperandClasses[Rec];
1207 CI->Kind = ClassInfo::UserClass0 + Index;
1209 ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1210 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) {
1211 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i));
1213 PrintError(Rec->getLoc(), "Invalid super class reference!");
1217 ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1219 PrintError(Rec->getLoc(), "Invalid super class reference!");
1221 CI->SuperClasses.push_back(SC);
1223 CI->ClassName = Rec->getValueAsString("Name");
1224 CI->Name = "MCK_" + CI->ClassName;
1225 CI->ValueName = Rec->getName();
1227 // Get or construct the predicate method name.
1228 Init *PMName = Rec->getValueInit("PredicateMethod");
1229 if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1230 CI->PredicateMethod = SI->getValue();
1232 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1233 CI->PredicateMethod = "is" + CI->ClassName;
1236 // Get or construct the render method name.
1237 Init *RMName = Rec->getValueInit("RenderMethod");
1238 if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1239 CI->RenderMethod = SI->getValue();
1241 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1242 CI->RenderMethod = "add" + CI->ClassName + "Operands";
1245 // Get the parse method name or leave it as empty.
1246 Init *PRMName = Rec->getValueInit("ParserMethod");
1247 if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1248 CI->ParserMethod = SI->getValue();
1250 // Get the diagnostic type or leave it as empty.
1251 // Get the parse method name or leave it as empty.
1252 Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1253 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1254 CI->DiagnosticType = SI->getValue();
1256 AsmOperandClasses[Rec] = CI;
1257 Classes.push_back(CI);
1262 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1263 CodeGenTarget &target,
1264 RecordKeeper &records)
1265 : Records(records), AsmParser(asmParser), Target(target) {
1268 /// buildOperandMatchInfo - Build the necessary information to handle user
1269 /// defined operand parsing methods.
1270 void AsmMatcherInfo::buildOperandMatchInfo() {
1272 /// Map containing a mask with all operands indices that can be found for
1273 /// that class inside a instruction.
1274 typedef std::map<ClassInfo *, unsigned, less_ptr<ClassInfo>> OpClassMaskTy;
1275 OpClassMaskTy OpClassMask;
1277 for (std::vector<MatchableInfo*>::const_iterator it =
1278 Matchables.begin(), ie = Matchables.end();
1280 MatchableInfo &II = **it;
1281 OpClassMask.clear();
1283 // Keep track of all operands of this instructions which belong to the
1285 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
1286 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
1287 if (Op.Class->ParserMethod.empty())
1289 unsigned &OperandMask = OpClassMask[Op.Class];
1290 OperandMask |= (1 << i);
1293 // Generate operand match info for each mnemonic/operand class pair.
1294 for (OpClassMaskTy::iterator iit = OpClassMask.begin(),
1295 iie = OpClassMask.end(); iit != iie; ++iit) {
1296 unsigned OpMask = iit->second;
1297 ClassInfo *CI = iit->first;
1298 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask));
1303 void AsmMatcherInfo::buildInfo() {
1304 // Build information about all of the AssemblerPredicates.
1305 std::vector<Record*> AllPredicates =
1306 Records.getAllDerivedDefinitions("Predicate");
1307 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) {
1308 Record *Pred = AllPredicates[i];
1309 // Ignore predicates that are not intended for the assembler.
1310 if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
1313 if (Pred->getName().empty())
1314 PrintFatalError(Pred->getLoc(), "Predicate has no name!");
1316 uint64_t FeatureNo = SubtargetFeatures.size();
1317 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
1318 DEBUG(SubtargetFeatures[Pred]->dump());
1319 assert(FeatureNo < 64 && "Too many subtarget features!");
1322 // Parse the instructions; we need to do this first so that we can gather the
1323 // singleton register classes.
1324 SmallPtrSet<Record*, 16> SingletonRegisters;
1325 unsigned VariantCount = Target.getAsmParserVariantCount();
1326 for (unsigned VC = 0; VC != VariantCount; ++VC) {
1327 Record *AsmVariant = Target.getAsmParserVariant(VC);
1328 std::string CommentDelimiter =
1329 AsmVariant->getValueAsString("CommentDelimiter");
1330 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1331 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1333 for (const CodeGenInstruction *CGI : Target.instructions()) {
1335 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1336 // filter the set of instructions we consider.
1337 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1340 // Ignore "codegen only" instructions.
1341 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1344 std::unique_ptr<MatchableInfo> II(new MatchableInfo(*CGI));
1346 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1348 // Ignore instructions which shouldn't be matched and diagnose invalid
1349 // instruction definitions with an error.
1350 if (!II->validate(CommentDelimiter, true))
1353 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
1355 // FIXME: This is a total hack.
1356 if (StringRef(II->TheDef->getName()).startswith("Int_") ||
1357 StringRef(II->TheDef->getName()).endswith("_Int"))
1360 Matchables.push_back(II.release());
1363 // Parse all of the InstAlias definitions and stick them in the list of
1365 std::vector<Record*> AllInstAliases =
1366 Records.getAllDerivedDefinitions("InstAlias");
1367 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1368 CodeGenInstAlias *Alias =
1369 new CodeGenInstAlias(AllInstAliases[i], AsmVariantNo, Target);
1371 // If the tblgen -match-prefix option is specified (for tblgen hackers),
1372 // filter the set of instruction aliases we consider, based on the target
1374 if (!StringRef(Alias->ResultInst->TheDef->getName())
1375 .startswith( MatchPrefix))
1378 std::unique_ptr<MatchableInfo> II(new MatchableInfo(Alias));
1380 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix);
1382 // Validate the alias definitions.
1383 II->validate(CommentDelimiter, false);
1385 Matchables.push_back(II.release());
1389 // Build info for the register classes.
1390 buildRegisterClasses(SingletonRegisters);
1392 // Build info for the user defined assembly operand classes.
1393 buildOperandClasses();
1395 // Build the information about matchables, now that we have fully formed
1397 std::vector<MatchableInfo*> NewMatchables;
1398 for (MatchableInfo *II : Matchables) {
1399 // Parse the tokens after the mnemonic.
1400 // Note: buildInstructionOperandReference may insert new AsmOperands, so
1401 // don't precompute the loop bound.
1402 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1403 MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1404 StringRef Token = Op.Token;
1406 // Check for singleton registers.
1407 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) {
1408 Op.Class = RegisterClasses[RegRecord];
1409 assert(Op.Class && Op.Class->Registers.size() == 1 &&
1410 "Unexpected class for singleton register");
1414 // Check for simple tokens.
1415 if (Token[0] != '$') {
1416 Op.Class = getTokenClass(Token);
1420 if (Token.size() > 1 && isdigit(Token[1])) {
1421 Op.Class = getTokenClass(Token);
1425 // Otherwise this is an operand reference.
1426 StringRef OperandName;
1427 if (Token[1] == '{')
1428 OperandName = Token.substr(2, Token.size() - 3);
1430 OperandName = Token.substr(1);
1432 if (II->DefRec.is<const CodeGenInstruction*>())
1433 buildInstructionOperandReference(II, OperandName, i);
1435 buildAliasOperandReference(II, OperandName, Op);
1438 if (II->DefRec.is<const CodeGenInstruction*>()) {
1439 II->buildInstructionResultOperands();
1440 // If the instruction has a two-operand alias, build up the
1441 // matchable here. We'll add them in bulk at the end to avoid
1442 // confusing this loop.
1443 std::string Constraint =
1444 II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1445 if (Constraint != "") {
1446 // Start by making a copy of the original matchable.
1447 std::unique_ptr<MatchableInfo> AliasII(new MatchableInfo(*II));
1449 // Adjust it to be a two-operand alias.
1450 AliasII->formTwoOperandAlias(Constraint);
1452 // Add the alias to the matchables list.
1453 NewMatchables.push_back(AliasII.release());
1456 II->buildAliasResultOperands();
1458 if (!NewMatchables.empty())
1459 Matchables.insert(Matchables.end(), NewMatchables.begin(),
1460 NewMatchables.end());
1462 // Process token alias definitions and set up the associated superclass
1464 std::vector<Record*> AllTokenAliases =
1465 Records.getAllDerivedDefinitions("TokenAlias");
1466 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) {
1467 Record *Rec = AllTokenAliases[i];
1468 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1469 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1470 if (FromClass == ToClass)
1471 PrintFatalError(Rec->getLoc(),
1472 "error: Destination value identical to source value.");
1473 FromClass->SuperClasses.push_back(ToClass);
1476 // Reorder classes so that classes precede super classes.
1477 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>());
1480 /// buildInstructionOperandReference - The specified operand is a reference to a
1481 /// named operand such as $src. Resolve the Class and OperandInfo pointers.
1482 void AsmMatcherInfo::
1483 buildInstructionOperandReference(MatchableInfo *II,
1484 StringRef OperandName,
1485 unsigned AsmOpIdx) {
1486 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1487 const CGIOperandList &Operands = CGI.Operands;
1488 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1490 // Map this token to an operand.
1492 if (!Operands.hasOperandNamed(OperandName, Idx))
1493 PrintFatalError(II->TheDef->getLoc(),
1494 "error: unable to find operand: '" + OperandName + "'");
1496 // If the instruction operand has multiple suboperands, but the parser
1497 // match class for the asm operand is still the default "ImmAsmOperand",
1498 // then handle each suboperand separately.
1499 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1500 Record *Rec = Operands[Idx].Rec;
1501 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1502 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1503 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1504 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1505 StringRef Token = Op->Token; // save this in case Op gets moved
1506 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1507 MatchableInfo::AsmOperand NewAsmOp(Token);
1508 NewAsmOp.SubOpIdx = SI;
1509 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1511 // Replace Op with first suboperand.
1512 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1517 // Set up the operand class.
1518 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1520 // If the named operand is tied, canonicalize it to the untied operand.
1521 // For example, something like:
1522 // (outs GPR:$dst), (ins GPR:$src)
1523 // with an asmstring of
1525 // we want to canonicalize to:
1527 // so that we know how to provide the $dst operand when filling in the result.
1529 if (Operands[Idx].MINumOperands == 1)
1530 OITied = Operands[Idx].getTiedRegister();
1532 // The tied operand index is an MIOperand index, find the operand that
1534 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1535 OperandName = Operands[Idx.first].Name;
1536 Op->SubOpIdx = Idx.second;
1539 Op->SrcOpName = OperandName;
1542 /// buildAliasOperandReference - When parsing an operand reference out of the
1543 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1544 /// operand reference is by looking it up in the result pattern definition.
1545 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1546 StringRef OperandName,
1547 MatchableInfo::AsmOperand &Op) {
1548 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1550 // Set up the operand class.
1551 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1552 if (CGA.ResultOperands[i].isRecord() &&
1553 CGA.ResultOperands[i].getName() == OperandName) {
1554 // It's safe to go with the first one we find, because CodeGenInstAlias
1555 // validates that all operands with the same name have the same record.
1556 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1557 // Use the match class from the Alias definition, not the
1558 // destination instruction, as we may have an immediate that's
1559 // being munged by the match class.
1560 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1562 Op.SrcOpName = OperandName;
1566 PrintFatalError(II->TheDef->getLoc(),
1567 "error: unable to find operand: '" + OperandName + "'");
1570 void MatchableInfo::buildInstructionResultOperands() {
1571 const CodeGenInstruction *ResultInst = getResultInst();
1573 // Loop over all operands of the result instruction, determining how to
1575 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1576 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i];
1578 // If this is a tied operand, just copy from the previously handled operand.
1580 if (OpInfo.MINumOperands == 1)
1581 TiedOp = OpInfo.getTiedRegister();
1583 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1587 // Find out what operand from the asmparser this MCInst operand comes from.
1588 int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1589 if (OpInfo.Name.empty() || SrcOperand == -1) {
1590 // This may happen for operands that are tied to a suboperand of a
1591 // complex operand. Simply use a dummy value here; nobody should
1592 // use this operand slot.
1593 // FIXME: The long term goal is for the MCOperand list to not contain
1594 // tied operands at all.
1595 ResOperands.push_back(ResOperand::getImmOp(0));
1599 // Check if the one AsmOperand populates the entire operand.
1600 unsigned NumOperands = OpInfo.MINumOperands;
1601 if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1602 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1606 // Add a separate ResOperand for each suboperand.
1607 for (unsigned AI = 0; AI < NumOperands; ++AI) {
1608 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1609 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1610 "unexpected AsmOperands for suboperands");
1611 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1616 void MatchableInfo::buildAliasResultOperands() {
1617 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1618 const CodeGenInstruction *ResultInst = getResultInst();
1620 // Loop over all operands of the result instruction, determining how to
1622 unsigned AliasOpNo = 0;
1623 unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1624 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1625 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1627 // If this is a tied operand, just copy from the previously handled operand.
1629 if (OpInfo->MINumOperands == 1)
1630 TiedOp = OpInfo->getTiedRegister();
1632 ResOperands.push_back(ResOperand::getTiedOp(TiedOp));
1636 // Handle all the suboperands for this operand.
1637 const std::string &OpName = OpInfo->Name;
1638 for ( ; AliasOpNo < LastOpNo &&
1639 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1640 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1642 // Find out what operand from the asmparser that this MCInst operand
1644 switch (CGA.ResultOperands[AliasOpNo].Kind) {
1645 case CodeGenInstAlias::ResultOperand::K_Record: {
1646 StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1647 int SrcOperand = findAsmOperand(Name, SubIdx);
1648 if (SrcOperand == -1)
1649 PrintFatalError(TheDef->getLoc(), "Instruction '" +
1650 TheDef->getName() + "' has operand '" + OpName +
1651 "' that doesn't appear in asm string!");
1652 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1653 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1657 case CodeGenInstAlias::ResultOperand::K_Imm: {
1658 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1659 ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1662 case CodeGenInstAlias::ResultOperand::K_Reg: {
1663 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1664 ResOperands.push_back(ResOperand::getRegOp(Reg));
1672 static unsigned getConverterOperandID(const std::string &Name,
1673 SetVector<std::string> &Table,
1675 IsNew = Table.insert(Name);
1677 unsigned ID = IsNew ? Table.size() - 1 :
1678 std::find(Table.begin(), Table.end(), Name) - Table.begin();
1680 assert(ID < Table.size());
1686 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1687 std::vector<MatchableInfo*> &Infos,
1689 SetVector<std::string> OperandConversionKinds;
1690 SetVector<std::string> InstructionConversionKinds;
1691 std::vector<std::vector<uint8_t> > ConversionTable;
1692 size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1694 // TargetOperandClass - This is the target's operand class, like X86Operand.
1695 std::string TargetOperandClass = Target.getName() + "Operand";
1697 // Write the convert function to a separate stream, so we can drop it after
1698 // the enum. We'll build up the conversion handlers for the individual
1699 // operand types opportunistically as we encounter them.
1700 std::string ConvertFnBody;
1701 raw_string_ostream CvtOS(ConvertFnBody);
1702 // Start the unified conversion function.
1703 CvtOS << "void " << Target.getName() << ClassName << "::\n"
1704 << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1705 << "unsigned Opcode,\n"
1706 << " const OperandVector"
1707 << " &Operands) {\n"
1708 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1709 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1710 << " Inst.setOpcode(Opcode);\n"
1711 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1712 << " switch (*p) {\n"
1713 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1714 << " case CVT_Reg:\n"
1715 << " static_cast<" << TargetOperandClass
1716 << "&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);\n"
1718 << " case CVT_Tied:\n"
1719 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n"
1722 std::string OperandFnBody;
1723 raw_string_ostream OpOS(OperandFnBody);
1724 // Start the operand number lookup function.
1725 OpOS << "void " << Target.getName() << ClassName << "::\n"
1726 << "convertToMapAndConstraints(unsigned Kind,\n";
1728 OpOS << "const OperandVector &Operands) {\n"
1729 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
1730 << " unsigned NumMCOperands = 0;\n"
1731 << " const uint8_t *Converter = ConversionTable[Kind];\n"
1732 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n"
1733 << " switch (*p) {\n"
1734 << " default: llvm_unreachable(\"invalid conversion entry!\");\n"
1735 << " case CVT_Reg:\n"
1736 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1737 << " Operands[*(p + 1)]->setConstraint(\"r\");\n"
1738 << " ++NumMCOperands;\n"
1740 << " case CVT_Tied:\n"
1741 << " ++NumMCOperands;\n"
1744 // Pre-populate the operand conversion kinds with the standard always
1745 // available entries.
1746 OperandConversionKinds.insert("CVT_Done");
1747 OperandConversionKinds.insert("CVT_Reg");
1748 OperandConversionKinds.insert("CVT_Tied");
1749 enum { CVT_Done, CVT_Reg, CVT_Tied };
1751 for (MatchableInfo *II : Infos) {
1752 // Check if we have a custom match function.
1753 std::string AsmMatchConverter =
1754 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
1755 if (!AsmMatchConverter.empty()) {
1756 std::string Signature = "ConvertCustom_" + AsmMatchConverter;
1757 II->ConversionFnKind = Signature;
1759 // Check if we have already generated this signature.
1760 if (!InstructionConversionKinds.insert(Signature))
1763 // Remember this converter for the kind enum.
1764 unsigned KindID = OperandConversionKinds.size();
1765 OperandConversionKinds.insert("CVT_" +
1766 getEnumNameForToken(AsmMatchConverter));
1768 // Add the converter row for this instruction.
1769 ConversionTable.push_back(std::vector<uint8_t>());
1770 ConversionTable.back().push_back(KindID);
1771 ConversionTable.back().push_back(CVT_Done);
1773 // Add the handler to the conversion driver function.
1774 CvtOS << " case CVT_"
1775 << getEnumNameForToken(AsmMatchConverter) << ":\n"
1776 << " " << AsmMatchConverter << "(Inst, Operands);\n"
1779 // FIXME: Handle the operand number lookup for custom match functions.
1783 // Build the conversion function signature.
1784 std::string Signature = "Convert";
1786 std::vector<uint8_t> ConversionRow;
1788 // Compute the convert enum and the case body.
1789 MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
1791 for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
1792 const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
1794 // Generate code to populate each result operand.
1795 switch (OpInfo.Kind) {
1796 case MatchableInfo::ResOperand::RenderAsmOperand: {
1797 // This comes from something we parsed.
1798 const MatchableInfo::AsmOperand &Op =
1799 II->AsmOperands[OpInfo.AsmOperandNum];
1801 // Registers are always converted the same, don't duplicate the
1802 // conversion function based on them.
1805 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
1807 Signature += utostr(OpInfo.MINumOperands);
1808 Signature += "_" + itostr(OpInfo.AsmOperandNum);
1810 // Add the conversion kind, if necessary, and get the associated ID
1811 // the index of its entry in the vector).
1812 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
1813 Op.Class->RenderMethod);
1814 Name = getEnumNameForToken(Name);
1816 bool IsNewConverter = false;
1817 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1820 // Add the operand entry to the instruction kind conversion row.
1821 ConversionRow.push_back(ID);
1822 ConversionRow.push_back(OpInfo.AsmOperandNum + 1);
1824 if (!IsNewConverter)
1827 // This is a new operand kind. Add a handler for it to the
1828 // converter driver.
1829 CvtOS << " case " << Name << ":\n"
1830 << " static_cast<" << TargetOperandClass
1831 << "&>(*Operands[*(p + 1)])." << Op.Class->RenderMethod
1832 << "(Inst, " << OpInfo.MINumOperands << ");\n"
1835 // Add a handler for the operand number lookup.
1836 OpOS << " case " << Name << ":\n"
1837 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
1839 if (Op.Class->isRegisterClass())
1840 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n";
1842 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n";
1843 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
1847 case MatchableInfo::ResOperand::TiedOperand: {
1848 // If this operand is tied to a previous one, just copy the MCInst
1849 // operand from the earlier one.We can only tie single MCOperand values.
1850 assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
1851 unsigned TiedOp = OpInfo.TiedOperandNum;
1852 assert(i > TiedOp && "Tied operand precedes its target!");
1853 Signature += "__Tie" + utostr(TiedOp);
1854 ConversionRow.push_back(CVT_Tied);
1855 ConversionRow.push_back(TiedOp);
1858 case MatchableInfo::ResOperand::ImmOperand: {
1859 int64_t Val = OpInfo.ImmVal;
1860 std::string Ty = "imm_" + itostr(Val);
1861 Signature += "__" + Ty;
1863 std::string Name = "CVT_" + Ty;
1864 bool IsNewConverter = false;
1865 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1867 // Add the operand entry to the instruction kind conversion row.
1868 ConversionRow.push_back(ID);
1869 ConversionRow.push_back(0);
1871 if (!IsNewConverter)
1874 CvtOS << " case " << Name << ":\n"
1875 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
1878 OpOS << " case " << Name << ":\n"
1879 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1880 << " Operands[*(p + 1)]->setConstraint(\"\");\n"
1881 << " ++NumMCOperands;\n"
1885 case MatchableInfo::ResOperand::RegOperand: {
1886 std::string Reg, Name;
1887 if (!OpInfo.Register) {
1891 Reg = getQualifiedName(OpInfo.Register);
1892 Name = "reg" + OpInfo.Register->getName();
1894 Signature += "__" + Name;
1895 Name = "CVT_" + Name;
1896 bool IsNewConverter = false;
1897 unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
1899 // Add the operand entry to the instruction kind conversion row.
1900 ConversionRow.push_back(ID);
1901 ConversionRow.push_back(0);
1903 if (!IsNewConverter)
1905 CvtOS << " case " << Name << ":\n"
1906 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
1909 OpOS << " case " << Name << ":\n"
1910 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
1911 << " Operands[*(p + 1)]->setConstraint(\"m\");\n"
1912 << " ++NumMCOperands;\n"
1918 // If there were no operands, add to the signature to that effect
1919 if (Signature == "Convert")
1920 Signature += "_NoOperands";
1922 II->ConversionFnKind = Signature;
1924 // Save the signature. If we already have it, don't add a new row
1926 if (!InstructionConversionKinds.insert(Signature))
1929 // Add the row to the table.
1930 ConversionTable.push_back(ConversionRow);
1933 // Finish up the converter driver function.
1934 CvtOS << " }\n }\n}\n\n";
1936 // Finish up the operand number lookup function.
1937 OpOS << " }\n }\n}\n\n";
1939 OS << "namespace {\n";
1941 // Output the operand conversion kind enum.
1942 OS << "enum OperatorConversionKind {\n";
1943 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i)
1944 OS << " " << OperandConversionKinds[i] << ",\n";
1945 OS << " CVT_NUM_CONVERTERS\n";
1948 // Output the instruction conversion kind enum.
1949 OS << "enum InstructionConversionKind {\n";
1950 for (SetVector<std::string>::const_iterator
1951 i = InstructionConversionKinds.begin(),
1952 e = InstructionConversionKinds.end(); i != e; ++i)
1953 OS << " " << *i << ",\n";
1954 OS << " CVT_NUM_SIGNATURES\n";
1958 OS << "} // end anonymous namespace\n\n";
1960 // Output the conversion table.
1961 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
1962 << MaxRowLength << "] = {\n";
1964 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
1965 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
1966 OS << " // " << InstructionConversionKinds[Row] << "\n";
1968 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2)
1969 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", "
1970 << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
1971 OS << "CVT_Done },\n";
1976 // Spit out the conversion driver function.
1979 // Spit out the operand number lookup function.
1983 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
1984 static void emitMatchClassEnumeration(CodeGenTarget &Target,
1985 std::vector<ClassInfo*> &Infos,
1987 OS << "namespace {\n\n";
1989 OS << "/// MatchClassKind - The kinds of classes which participate in\n"
1990 << "/// instruction matching.\n";
1991 OS << "enum MatchClassKind {\n";
1992 OS << " InvalidMatchClass = 0,\n";
1993 for (const ClassInfo *CI : Infos) {
1994 OS << " " << CI->Name << ", // ";
1995 if (CI->Kind == ClassInfo::Token) {
1996 OS << "'" << CI->ValueName << "'\n";
1997 } else if (CI->isRegisterClass()) {
1998 if (!CI->ValueName.empty())
1999 OS << "register class '" << CI->ValueName << "'\n";
2001 OS << "derived register class\n";
2003 OS << "user defined class '" << CI->ValueName << "'\n";
2006 OS << " NumMatchClassKinds\n";
2012 /// emitValidateOperandClass - Emit the function to validate an operand class.
2013 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2015 OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2016 << "MatchClassKind Kind) {\n";
2017 OS << " " << Info.Target.getName() << "Operand &Operand = ("
2018 << Info.Target.getName() << "Operand&)GOp;\n";
2020 // The InvalidMatchClass is not to match any operand.
2021 OS << " if (Kind == InvalidMatchClass)\n";
2022 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2024 // Check for Token operands first.
2025 // FIXME: Use a more specific diagnostic type.
2026 OS << " if (Operand.isToken())\n";
2027 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2028 << " MCTargetAsmParser::Match_Success :\n"
2029 << " MCTargetAsmParser::Match_InvalidOperand;\n\n";
2031 // Check the user classes. We don't care what order since we're only
2032 // actually matching against one of them.
2033 for (const ClassInfo *CI : Info.Classes) {
2034 if (!CI->isUserClass())
2037 OS << " // '" << CI->ClassName << "' class\n";
2038 OS << " if (Kind == " << CI->Name << ") {\n";
2039 OS << " if (Operand." << CI->PredicateMethod << "())\n";
2040 OS << " return MCTargetAsmParser::Match_Success;\n";
2041 if (!CI->DiagnosticType.empty())
2042 OS << " return " << Info.Target.getName() << "AsmParser::Match_"
2043 << CI->DiagnosticType << ";\n";
2047 // Check for register operands, including sub-classes.
2048 OS << " if (Operand.isReg()) {\n";
2049 OS << " MatchClassKind OpKind;\n";
2050 OS << " switch (Operand.getReg()) {\n";
2051 OS << " default: OpKind = InvalidMatchClass; break;\n";
2052 for (const auto &RC : Info.RegisterClasses)
2053 OS << " case " << Info.Target.getName() << "::"
2054 << RC.first->getName() << ": OpKind = " << RC.second->Name
2057 OS << " return isSubclass(OpKind, Kind) ? "
2058 << "MCTargetAsmParser::Match_Success :\n "
2059 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n";
2061 // Generic fallthrough match failure case for operands that don't have
2062 // specialized diagnostic types.
2063 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n";
2067 /// emitIsSubclass - Emit the subclass predicate function.
2068 static void emitIsSubclass(CodeGenTarget &Target,
2069 std::vector<ClassInfo*> &Infos,
2071 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2072 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2073 OS << " if (A == B)\n";
2074 OS << " return true;\n\n";
2077 raw_string_ostream SS(OStr);
2079 SS << " switch (A) {\n";
2080 SS << " default:\n";
2081 SS << " return false;\n";
2082 for (const ClassInfo *A : Infos) {
2083 std::vector<StringRef> SuperClasses;
2084 for (const ClassInfo *B : Infos) {
2085 if (A != B && A->isSubsetOf(*B))
2086 SuperClasses.push_back(B->Name);
2089 if (SuperClasses.empty())
2093 SS << "\n case " << A->Name << ":\n";
2095 if (SuperClasses.size() == 1) {
2096 SS << " return B == " << SuperClasses.back().str() << ";\n";
2100 if (!SuperClasses.empty()) {
2101 SS << " switch (B) {\n";
2102 SS << " default: return false;\n";
2103 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
2104 SS << " case " << SuperClasses[i].str() << ": return true;\n";
2107 // No case statement to emit
2108 SS << " return false;\n";
2113 // If there were case statements emitted into the string stream, write them
2114 // to the output stream, otherwise write the default.
2118 OS << " return false;\n";
2123 /// emitMatchTokenString - Emit the function to match a token string to the
2124 /// appropriate match class value.
2125 static void emitMatchTokenString(CodeGenTarget &Target,
2126 std::vector<ClassInfo*> &Infos,
2128 // Construct the match list.
2129 std::vector<StringMatcher::StringPair> Matches;
2130 for (const ClassInfo *CI : Infos) {
2131 if (CI->Kind == ClassInfo::Token)
2132 Matches.push_back(StringMatcher::StringPair(CI->ValueName,
2133 "return " + CI->Name + ";"));
2136 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2138 StringMatcher("Name", Matches, OS).Emit();
2140 OS << " return InvalidMatchClass;\n";
2144 /// emitMatchRegisterName - Emit the function to match a string to the target
2145 /// specific register enum.
2146 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2148 // Construct the match list.
2149 std::vector<StringMatcher::StringPair> Matches;
2150 const std::vector<CodeGenRegister*> &Regs =
2151 Target.getRegBank().getRegisters();
2152 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2153 const CodeGenRegister *Reg = Regs[i];
2154 if (Reg->TheDef->getValueAsString("AsmName").empty())
2157 Matches.push_back(StringMatcher::StringPair(
2158 Reg->TheDef->getValueAsString("AsmName"),
2159 "return " + utostr(Reg->EnumValue) + ";"));
2162 OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2164 StringMatcher("Name", Matches, OS).Emit();
2166 OS << " return 0;\n";
2170 static const char *getMinimalTypeForRange(uint64_t Range) {
2171 assert(Range <= 0xFFFFFFFFFFFFFFFFULL && "Enum too large");
2172 if (Range > 0xFFFFFFFFULL)
2181 static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
2182 uint64_t MaxIndex = Info.SubtargetFeatures.size();
2185 return getMinimalTypeForRange(1ULL << MaxIndex);
2188 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
2190 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
2192 OS << "// Flags for subtarget features that participate in "
2193 << "instruction matching.\n";
2194 OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
2196 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2197 it = Info.SubtargetFeatures.begin(),
2198 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2199 SubtargetFeatureInfo &SFI = *it->second;
2200 OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
2202 OS << " Feature_None = 0\n";
2206 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2207 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2208 // Get the set of diagnostic types from all of the operand classes.
2209 std::set<StringRef> Types;
2210 for (std::map<Record*, ClassInfo*>::const_iterator
2211 I = Info.AsmOperandClasses.begin(),
2212 E = Info.AsmOperandClasses.end(); I != E; ++I) {
2213 if (!I->second->DiagnosticType.empty())
2214 Types.insert(I->second->DiagnosticType);
2217 if (Types.empty()) return;
2219 // Now emit the enum entries.
2220 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end();
2222 OS << " Match_" << *I << ",\n";
2223 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n";
2226 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2227 /// user-level name for a subtarget feature.
2228 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2229 OS << "// User-level names for subtarget features that participate in\n"
2230 << "// instruction matching.\n"
2231 << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2232 if (!Info.SubtargetFeatures.empty()) {
2233 OS << " switch(Val) {\n";
2234 typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap;
2235 for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(),
2236 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2237 SubtargetFeatureInfo &SFI = *it->second;
2238 // FIXME: Totally just a placeholder name to get the algorithm working.
2239 OS << " case " << SFI.getEnumName() << ": return \""
2240 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2242 OS << " default: return \"(unknown)\";\n";
2245 // Nothing to emit, so skip the switch
2246 OS << " return \"(unknown)\";\n";
2251 /// emitComputeAvailableFeatures - Emit the function to compute the list of
2252 /// available features given a subtarget.
2253 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info,
2255 std::string ClassName =
2256 Info.AsmParser->getValueAsString("AsmParserClassName");
2258 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2259 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2260 OS << " uint64_t Features = 0;\n";
2261 for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator
2262 it = Info.SubtargetFeatures.begin(),
2263 ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
2264 SubtargetFeatureInfo &SFI = *it->second;
2267 std::string CondStorage =
2268 SFI.TheDef->getValueAsString("AssemblerCondString");
2269 StringRef Conds = CondStorage;
2270 std::pair<StringRef,StringRef> Comma = Conds.split(',');
2277 StringRef Cond = Comma.first;
2278 if (Cond[0] == '!') {
2280 Cond = Cond.substr(1);
2283 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2290 if (Comma.second.empty())
2294 Comma = Comma.second.split(',');
2298 OS << " Features |= " << SFI.getEnumName() << ";\n";
2300 OS << " return Features;\n";
2304 static std::string GetAliasRequiredFeatures(Record *R,
2305 const AsmMatcherInfo &Info) {
2306 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2308 unsigned NumFeatures = 0;
2309 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2310 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2313 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2314 "' is not marked as an AssemblerPredicate!");
2319 Result += F->getEnumName();
2323 if (NumFeatures > 1)
2324 Result = '(' + Result + ')';
2328 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2329 std::vector<Record*> &Aliases,
2330 unsigned Indent = 0,
2331 StringRef AsmParserVariantName = StringRef()){
2332 // Keep track of all the aliases from a mnemonic. Use an std::map so that the
2333 // iteration order of the map is stable.
2334 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2336 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
2337 Record *R = Aliases[i];
2338 // FIXME: Allow AssemblerVariantName to be a comma separated list.
2339 std::string AsmVariantName = R->getValueAsString("AsmVariantName");
2340 if (AsmVariantName != AsmParserVariantName)
2342 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2344 if (AliasesFromMnemonic.empty())
2347 // Process each alias a "from" mnemonic at a time, building the code executed
2348 // by the string remapper.
2349 std::vector<StringMatcher::StringPair> Cases;
2350 for (std::map<std::string, std::vector<Record*> >::iterator
2351 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end();
2353 const std::vector<Record*> &ToVec = I->second;
2355 // Loop through each alias and emit code that handles each case. If there
2356 // are two instructions without predicates, emit an error. If there is one,
2358 std::string MatchCode;
2359 int AliasWithNoPredicate = -1;
2361 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2362 Record *R = ToVec[i];
2363 std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2365 // If this unconditionally matches, remember it for later and diagnose
2367 if (FeatureMask.empty()) {
2368 if (AliasWithNoPredicate != -1) {
2369 // We can't have two aliases from the same mnemonic with no predicate.
2370 PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2371 "two MnemonicAliases with the same 'from' mnemonic!");
2372 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2375 AliasWithNoPredicate = i;
2378 if (R->getValueAsString("ToMnemonic") == I->first)
2379 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2381 if (!MatchCode.empty())
2382 MatchCode += "else ";
2383 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n";
2384 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n";
2387 if (AliasWithNoPredicate != -1) {
2388 Record *R = ToVec[AliasWithNoPredicate];
2389 if (!MatchCode.empty())
2390 MatchCode += "else\n ";
2391 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n";
2394 MatchCode += "return;";
2396 Cases.push_back(std::make_pair(I->first, MatchCode));
2398 StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2401 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2402 /// emit a function for them and return true, otherwise return false.
2403 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2404 CodeGenTarget &Target) {
2405 // Ignore aliases when match-prefix is set.
2406 if (!MatchPrefix.empty())
2409 std::vector<Record*> Aliases =
2410 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2411 if (Aliases.empty()) return false;
2413 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2414 "uint64_t Features, unsigned VariantID) {\n";
2415 OS << " switch (VariantID) {\n";
2416 unsigned VariantCount = Target.getAsmParserVariantCount();
2417 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2418 Record *AsmVariant = Target.getAsmParserVariant(VC);
2419 int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2420 std::string AsmParserVariantName = AsmVariant->getValueAsString("Name");
2421 OS << " case " << AsmParserVariantNo << ":\n";
2422 emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2423 AsmParserVariantName);
2428 // Emit aliases that apply to all variants.
2429 emitMnemonicAliasVariant(OS, Info, Aliases);
2436 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2437 const AsmMatcherInfo &Info, StringRef ClassName,
2438 StringToOffsetTable &StringTable,
2439 unsigned MaxMnemonicIndex) {
2440 unsigned MaxMask = 0;
2441 for (std::vector<OperandMatchEntry>::const_iterator it =
2442 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2444 MaxMask |= it->OperandMask;
2447 // Emit the static custom operand parsing table;
2448 OS << "namespace {\n";
2449 OS << " struct OperandMatchEntry {\n";
2450 OS << " " << getMinimalRequiredFeaturesType(Info)
2451 << " RequiredFeatures;\n";
2452 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2454 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2456 OS << " " << getMinimalTypeForRange(MaxMask)
2457 << " OperandMask;\n\n";
2458 OS << " StringRef getMnemonic() const {\n";
2459 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2460 OS << " MnemonicTable[Mnemonic]);\n";
2464 OS << " // Predicate for searching for an opcode.\n";
2465 OS << " struct LessOpcodeOperand {\n";
2466 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2467 OS << " return LHS.getMnemonic() < RHS;\n";
2469 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2470 OS << " return LHS < RHS.getMnemonic();\n";
2472 OS << " bool operator()(const OperandMatchEntry &LHS,";
2473 OS << " const OperandMatchEntry &RHS) {\n";
2474 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2478 OS << "} // end anonymous namespace.\n\n";
2480 OS << "static const OperandMatchEntry OperandMatchTable["
2481 << Info.OperandMatchInfo.size() << "] = {\n";
2483 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n";
2484 for (std::vector<OperandMatchEntry>::const_iterator it =
2485 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end();
2487 const OperandMatchEntry &OMI = *it;
2488 const MatchableInfo &II = *OMI.MI;
2492 // Write the required features mask.
2493 if (!II.RequiredFeatures.empty()) {
2494 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2496 OS << II.RequiredFeatures[i]->getEnumName();
2501 // Store a pascal-style length byte in the mnemonic.
2502 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2503 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2504 << " /* " << II.Mnemonic << " */, ";
2508 OS << ", " << OMI.OperandMask;
2510 bool printComma = false;
2511 for (int i = 0, e = 31; i !=e; ++i)
2512 if (OMI.OperandMask & (1 << i)) {
2524 // Emit the operand class switch to call the correct custom parser for
2525 // the found operand class.
2526 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2527 << Target.getName() << ClassName << "::\n"
2528 << "tryCustomParseOperand(OperandVector"
2529 << " &Operands,\n unsigned MCK) {\n\n"
2530 << " switch(MCK) {\n";
2532 for (const ClassInfo *CI : Info.Classes) {
2533 if (CI->ParserMethod.empty())
2535 OS << " case " << CI->Name << ":\n"
2536 << " return " << CI->ParserMethod << "(Operands);\n";
2539 OS << " default:\n";
2540 OS << " return MatchOperand_NoMatch;\n";
2542 OS << " return MatchOperand_NoMatch;\n";
2545 // Emit the static custom operand parser. This code is very similar with
2546 // the other matcher. Also use MatchResultTy here just in case we go for
2547 // a better error handling.
2548 OS << Target.getName() << ClassName << "::OperandMatchResultTy "
2549 << Target.getName() << ClassName << "::\n"
2550 << "MatchOperandParserImpl(OperandVector"
2551 << " &Operands,\n StringRef Mnemonic) {\n";
2553 // Emit code to get the available features.
2554 OS << " // Get the current feature set.\n";
2555 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2557 OS << " // Get the next operand index.\n";
2558 OS << " unsigned NextOpNum = Operands.size()-1;\n";
2560 // Emit code to search the table.
2561 OS << " // Search the table.\n";
2562 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>";
2563 OS << " MnemonicRange =\n";
2564 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+"
2565 << Info.OperandMatchInfo.size() << ", Mnemonic,\n"
2566 << " LessOpcodeOperand());\n\n";
2568 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2569 OS << " return MatchOperand_NoMatch;\n\n";
2571 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2572 << " *ie = MnemonicRange.second; it != ie; ++it) {\n";
2574 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2575 OS << " assert(Mnemonic == it->getMnemonic());\n\n";
2577 // Emit check that the required features are available.
2578 OS << " // check if the available features match\n";
2579 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2580 << "!= it->RequiredFeatures) {\n";
2581 OS << " continue;\n";
2584 // Emit check to ensure the operand number matches.
2585 OS << " // check if the operand in question has a custom parser.\n";
2586 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n";
2587 OS << " continue;\n\n";
2589 // Emit call to the custom parser method
2590 OS << " // call custom parse method to handle the operand\n";
2591 OS << " OperandMatchResultTy Result = ";
2592 OS << "tryCustomParseOperand(Operands, it->Class);\n";
2593 OS << " if (Result != MatchOperand_NoMatch)\n";
2594 OS << " return Result;\n";
2597 OS << " // Okay, we had no match.\n";
2598 OS << " return MatchOperand_NoMatch;\n";
2602 void AsmMatcherEmitter::run(raw_ostream &OS) {
2603 CodeGenTarget Target(Records);
2604 Record *AsmParser = Target.getAsmParser();
2605 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
2607 // Compute the information on the instructions to match.
2608 AsmMatcherInfo Info(AsmParser, Target, Records);
2611 // Sort the instruction table using the partial order on classes. We use
2612 // stable_sort to ensure that ambiguous instructions are still
2613 // deterministically ordered.
2614 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(),
2615 less_ptr<MatchableInfo>());
2617 DEBUG_WITH_TYPE("instruction_info", {
2618 for (std::vector<MatchableInfo*>::iterator
2619 it = Info.Matchables.begin(), ie = Info.Matchables.end();
2624 // Check for ambiguous matchables.
2625 DEBUG_WITH_TYPE("ambiguous_instrs", {
2626 unsigned NumAmbiguous = 0;
2627 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) {
2628 for (unsigned j = i + 1; j != e; ++j) {
2629 MatchableInfo &A = *Info.Matchables[i];
2630 MatchableInfo &B = *Info.Matchables[j];
2632 if (A.couldMatchAmbiguouslyWith(B)) {
2633 errs() << "warning: ambiguous matchables:\n";
2635 errs() << "\nis incomparable with:\n";
2643 errs() << "warning: " << NumAmbiguous
2644 << " ambiguous matchables!\n";
2647 // Compute the information on the custom operand parsing.
2648 Info.buildOperandMatchInfo();
2650 // Write the output.
2652 // Information for the class declaration.
2653 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
2654 OS << "#undef GET_ASSEMBLER_HEADER\n";
2655 OS << " // This should be included into the middle of the declaration of\n";
2656 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2657 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2658 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
2659 << "unsigned Opcode,\n"
2660 << " const OperandVector "
2662 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2663 OS << " const OperandVector &Operands) override;\n";
2664 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
2665 OS << " unsigned MatchInstructionImpl(\n";
2667 OS << "const OperandVector &Operands,\n"
2668 << " MCInst &Inst,\n"
2669 << " uint64_t &ErrorInfo,"
2670 << " bool matchingInlineAsm,\n"
2671 << " unsigned VariantID = 0);\n";
2673 if (Info.OperandMatchInfo.size()) {
2674 OS << "\n enum OperandMatchResultTy {\n";
2675 OS << " MatchOperand_Success, // operand matched successfully\n";
2676 OS << " MatchOperand_NoMatch, // operand did not match\n";
2677 OS << " MatchOperand_ParseFail // operand matched but had errors\n";
2679 OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
2680 OS << " OperandVector &Operands,\n";
2681 OS << " StringRef Mnemonic);\n";
2683 OS << " OperandMatchResultTy tryCustomParseOperand(\n";
2684 OS << " OperandVector &Operands,\n";
2685 OS << " unsigned MCK);\n\n";
2688 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
2690 // Emit the operand match diagnostic enum names.
2691 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
2692 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2693 emitOperandDiagnosticTypes(Info, OS);
2694 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
2697 OS << "\n#ifdef GET_REGISTER_MATCHER\n";
2698 OS << "#undef GET_REGISTER_MATCHER\n\n";
2700 // Emit the subtarget feature enumeration.
2701 emitSubtargetFeatureFlagEnumeration(Info, OS);
2703 // Emit the function to match a register name to number.
2704 // This should be omitted for Mips target
2705 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
2706 emitMatchRegisterName(Target, AsmParser, OS);
2708 OS << "#endif // GET_REGISTER_MATCHER\n\n";
2710 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
2711 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
2713 // Generate the helper function to get the names for subtarget features.
2714 emitGetSubtargetFeatureName(Info, OS);
2716 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
2718 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
2719 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
2721 // Generate the function that remaps for mnemonic aliases.
2722 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
2724 // Generate the convertToMCInst function to convert operands into an MCInst.
2725 // Also, generate the convertToMapAndConstraints function for MS-style inline
2726 // assembly. The latter doesn't actually generate a MCInst.
2727 emitConvertFuncs(Target, ClassName, Info.Matchables, OS);
2729 // Emit the enumeration for classes which participate in matching.
2730 emitMatchClassEnumeration(Target, Info.Classes, OS);
2732 // Emit the routine to match token strings to their match class.
2733 emitMatchTokenString(Target, Info.Classes, OS);
2735 // Emit the subclass predicate routine.
2736 emitIsSubclass(Target, Info.Classes, OS);
2738 // Emit the routine to validate an operand against a match class.
2739 emitValidateOperandClass(Info, OS);
2741 // Emit the available features compute function.
2742 emitComputeAvailableFeatures(Info, OS);
2745 StringToOffsetTable StringTable;
2747 size_t MaxNumOperands = 0;
2748 unsigned MaxMnemonicIndex = 0;
2749 bool HasDeprecation = false;
2750 for (std::vector<MatchableInfo*>::const_iterator it =
2751 Info.Matchables.begin(), ie = Info.Matchables.end();
2753 MatchableInfo &II = **it;
2754 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size());
2755 HasDeprecation |= II.HasDeprecation;
2757 // Store a pascal-style length byte in the mnemonic.
2758 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2759 MaxMnemonicIndex = std::max(MaxMnemonicIndex,
2760 StringTable.GetOrAddStringOffset(LenMnemonic, false));
2763 OS << "static const char *const MnemonicTable =\n";
2764 StringTable.EmitString(OS);
2767 // Emit the static match table; unused classes get initalized to 0 which is
2768 // guaranteed to be InvalidMatchClass.
2770 // FIXME: We can reduce the size of this table very easily. First, we change
2771 // it so that store the kinds in separate bit-fields for each index, which
2772 // only needs to be the max width used for classes at that index (we also need
2773 // to reject based on this during classification). If we then make sure to
2774 // order the match kinds appropriately (putting mnemonics last), then we
2775 // should only end up using a few bits for each class, especially the ones
2776 // following the mnemonic.
2777 OS << "namespace {\n";
2778 OS << " struct MatchEntry {\n";
2779 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex)
2781 OS << " uint16_t Opcode;\n";
2782 OS << " " << getMinimalTypeForRange(Info.Matchables.size())
2784 OS << " " << getMinimalRequiredFeaturesType(Info)
2785 << " RequiredFeatures;\n";
2786 OS << " " << getMinimalTypeForRange(Info.Classes.size())
2787 << " Classes[" << MaxNumOperands << "];\n";
2788 OS << " StringRef getMnemonic() const {\n";
2789 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n";
2790 OS << " MnemonicTable[Mnemonic]);\n";
2794 OS << " // Predicate for searching for an opcode.\n";
2795 OS << " struct LessOpcode {\n";
2796 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
2797 OS << " return LHS.getMnemonic() < RHS;\n";
2799 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
2800 OS << " return LHS < RHS.getMnemonic();\n";
2802 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
2803 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n";
2807 OS << "} // end anonymous namespace.\n\n";
2809 unsigned VariantCount = Target.getAsmParserVariantCount();
2810 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2811 Record *AsmVariant = Target.getAsmParserVariant(VC);
2812 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2814 OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
2816 for (std::vector<MatchableInfo*>::const_iterator it =
2817 Info.Matchables.begin(), ie = Info.Matchables.end();
2819 MatchableInfo &II = **it;
2820 if (II.AsmVariantID != AsmVariantNo)
2823 // Store a pascal-style length byte in the mnemonic.
2824 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2825 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2826 << " /* " << II.Mnemonic << " */, "
2827 << Target.getName() << "::"
2828 << II.getResultInst()->TheDef->getName() << ", "
2829 << II.ConversionFnKind << ", ";
2831 // Write the required features mask.
2832 if (!II.RequiredFeatures.empty()) {
2833 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
2835 OS << II.RequiredFeatures[i]->getEnumName();
2841 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) {
2842 MatchableInfo::AsmOperand &Op = II.AsmOperands[i];
2845 OS << Op.Class->Name;
2853 // A method to determine if a mnemonic is in the list.
2854 OS << "bool " << Target.getName() << ClassName << "::\n"
2855 << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n";
2856 OS << " // Find the appropriate table for this asm variant.\n";
2857 OS << " const MatchEntry *Start, *End;\n";
2858 OS << " switch (VariantID) {\n";
2859 OS << " default: // unreachable\n";
2860 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2861 Record *AsmVariant = Target.getAsmParserVariant(VC);
2862 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2863 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2864 << "); End = std::end(MatchTable" << VC << "); break;\n";
2867 OS << " // Search the table.\n";
2868 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2869 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n";
2870 OS << " return MnemonicRange.first != MnemonicRange.second;\n";
2873 // Finally, build the match function.
2874 OS << "unsigned " << Target.getName() << ClassName << "::\n"
2875 << "MatchInstructionImpl(const OperandVector"
2877 OS << " MCInst &Inst,\n"
2878 << "uint64_t &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n";
2880 OS << " // Eliminate obvious mismatches.\n";
2881 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n";
2882 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n";
2883 OS << " return Match_InvalidOperand;\n";
2886 // Emit code to get the available features.
2887 OS << " // Get the current feature set.\n";
2888 OS << " uint64_t AvailableFeatures = getAvailableFeatures();\n\n";
2890 OS << " // Get the instruction mnemonic, which is the first token.\n";
2891 OS << " StringRef Mnemonic = ((" << Target.getName()
2892 << "Operand&)*Operands[0]).getToken();\n\n";
2894 if (HasMnemonicAliases) {
2895 OS << " // Process all MnemonicAliases to remap the mnemonic.\n";
2896 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
2899 // Emit code to compute the class list for this operand vector.
2900 OS << " // Some state to try to produce better error messages.\n";
2901 OS << " bool HadMatchOtherThanFeatures = false;\n";
2902 OS << " bool HadMatchOtherThanPredicate = false;\n";
2903 OS << " unsigned RetCode = Match_InvalidOperand;\n";
2904 OS << " uint64_t MissingFeatures = ~0ULL;\n";
2905 OS << " // Set ErrorInfo to the operand that mismatches if it is\n";
2906 OS << " // wrong for all instances of the instruction.\n";
2907 OS << " ErrorInfo = ~0U;\n";
2909 // Emit code to search the table.
2910 OS << " // Find the appropriate table for this asm variant.\n";
2911 OS << " const MatchEntry *Start, *End;\n";
2912 OS << " switch (VariantID) {\n";
2913 OS << " default: // unreachable\n";
2914 for (unsigned VC = 0; VC != VariantCount; ++VC) {
2915 Record *AsmVariant = Target.getAsmParserVariant(VC);
2916 int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
2917 OS << " case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
2918 << "); End = std::end(MatchTable" << VC << "); break;\n";
2921 OS << " // Search the table.\n";
2922 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
2923 OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
2925 OS << " // Return a more specific error code if no mnemonics match.\n";
2926 OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
2927 OS << " return Match_MnemonicFail;\n\n";
2929 OS << " for (const MatchEntry *it = MnemonicRange.first, "
2930 << "*ie = MnemonicRange.second;\n";
2931 OS << " it != ie; ++it) {\n";
2933 OS << " // equal_range guarantees that instruction mnemonic matches.\n";
2934 OS << " assert(Mnemonic == it->getMnemonic());\n";
2936 // Emit check that the subclasses match.
2937 OS << " bool OperandsValid = true;\n";
2938 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
2939 OS << " if (i + 1 >= Operands.size()) {\n";
2940 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n";
2941 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n";
2944 OS << " unsigned Diag = validateOperandClass(*Operands[i+1],\n";
2946 OS << "(MatchClassKind)it->Classes[i]);\n";
2947 OS << " if (Diag == Match_Success)\n";
2948 OS << " continue;\n";
2949 OS << " // If the generic handler indicates an invalid operand\n";
2950 OS << " // failure, check for a special case.\n";
2951 OS << " if (Diag == Match_InvalidOperand) {\n";
2952 OS << " Diag = validateTargetOperandClass(*Operands[i+1],\n";
2954 OS << "(MatchClassKind)it->Classes[i]);\n";
2955 OS << " if (Diag == Match_Success)\n";
2956 OS << " continue;\n";
2958 OS << " // If this operand is broken for all of the instances of this\n";
2959 OS << " // mnemonic, keep track of it so we can report loc info.\n";
2960 OS << " // If we already had a match that only failed due to a\n";
2961 OS << " // target predicate, that diagnostic is preferred.\n";
2962 OS << " if (!HadMatchOtherThanPredicate &&\n";
2963 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n";
2964 OS << " ErrorInfo = i+1;\n";
2965 OS << " // InvalidOperand is the default. Prefer specificity.\n";
2966 OS << " if (Diag != Match_InvalidOperand)\n";
2967 OS << " RetCode = Diag;\n";
2969 OS << " // Otherwise, just reject this instance of the mnemonic.\n";
2970 OS << " OperandsValid = false;\n";
2974 OS << " if (!OperandsValid) continue;\n";
2976 // Emit check that the required features are available.
2977 OS << " if ((AvailableFeatures & it->RequiredFeatures) "
2978 << "!= it->RequiredFeatures) {\n";
2979 OS << " HadMatchOtherThanFeatures = true;\n";
2980 OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & "
2981 "~AvailableFeatures;\n";
2982 OS << " if (CountPopulation_64(NewMissingFeatures) <=\n"
2983 " CountPopulation_64(MissingFeatures))\n";
2984 OS << " MissingFeatures = NewMissingFeatures;\n";
2985 OS << " continue;\n";
2988 OS << " if (matchingInlineAsm) {\n";
2989 OS << " Inst.setOpcode(it->Opcode);\n";
2990 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n";
2991 OS << " return Match_Success;\n";
2993 OS << " // We have selected a definite instruction, convert the parsed\n"
2994 << " // operands into the appropriate MCInst.\n";
2995 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
2998 // Verify the instruction with the target-specific match predicate function.
2999 OS << " // We have a potential match. Check the target predicate to\n"
3000 << " // handle any context sensitive constraints.\n"
3001 << " unsigned MatchResult;\n"
3002 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3003 << " Match_Success) {\n"
3004 << " Inst.clear();\n"
3005 << " RetCode = MatchResult;\n"
3006 << " HadMatchOtherThanPredicate = true;\n"
3010 // Call the post-processing function, if used.
3011 std::string InsnCleanupFn =
3012 AsmParser->getValueAsString("AsmParserInstCleanup");
3013 if (!InsnCleanupFn.empty())
3014 OS << " " << InsnCleanupFn << "(Inst);\n";
3016 if (HasDeprecation) {
3017 OS << " std::string Info;\n";
3018 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3019 OS << " SMLoc Loc = ((" << Target.getName()
3020 << "Operand&)*Operands[0]).getStartLoc();\n";
3021 OS << " getParser().Warning(Loc, Info, None);\n";
3025 OS << " return Match_Success;\n";
3028 OS << " // Okay, we had no match. Try to return a useful error code.\n";
3029 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3030 OS << " return RetCode;\n\n";
3031 OS << " // Missing feature matches return which features were missing\n";
3032 OS << " ErrorInfo = MissingFeatures;\n";
3033 OS << " return Match_MissingFeature;\n";
3036 if (Info.OperandMatchInfo.size())
3037 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3040 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3045 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3046 emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3047 AsmMatcherEmitter(RK).run(OS);
3050 } // End llvm namespace