test/MC/Disassembler/ARM/armv8.1a.txt

   1 # RUN: llvm-mc -triple armv8 -mattr=+v8.1a  --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
   2 # RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
   3
   4 [0x54,0x0b,0x12,0xf3]
   5 [0x12,0x0b,0x21,0xf3]
   6 [0x54,0x0c,0x12,0xf3]
   7 [0x12,0x0c,0x21,0xf3]
   8 # CHECK-V81a:  vqrdmlah.s16  q0, q1, q2
   9 # CHECK-V81a:  vqrdmlah.s32  d0, d1, d2
  10 # CHECK-V81a:  vqrdmlsh.s16  q0, q1, q2
  11 # CHECK-V81a:  vqrdmlsh.s32  d0, d1, d2
  12 # CHECK-V8: warning: invalid instruction encoding
  13 # CHECK-V8: [0x54,0x0b,0x12,0xf3]
  14 # CHECK-V8: warning: invalid instruction encoding
  15 # CHECK-V8: [0x12,0x0b,0x21,0xf3]
  16 # CHECK-V8: warning: invalid instruction encoding
  17 # CHECK-V8: [0x54,0x0c,0x12,0xf3]
  18 # CHECK-V8: warning: invalid instruction encoding
  19 # CHECK-V8: [0x12,0x0c,0x21,0xf3]
  20
  21 [0x42,0x0e,0x92,0xf3]
  22 [0x42,0x0e,0xa1,0xf2]
  23 [0x42,0x0f,0x92,0xf3]
  24 [0x42,0x0f,0xa1,0xf2]
  25 # CHECK-V81a:  vqrdmlah.s16 q0, q1, d2[0]
  26 # CHECK-V81a:  vqrdmlah.s32 d0, d1, d2[0]
  27 # CHECK-V81a:  vqrdmlsh.s16 q0, q1, d2[0]
  28 # CHECK-V81a:  vqrdmlsh.s32 d0, d1, d2[0]
  29 # CHECK-V8: warning: invalid instruction encoding
  30 # CHECK-V8: [0x42,0x0e,0x92,0xf3]
  31 # CHECK-V8: warning: invalid instruction encoding
  32 # CHECK-V8: [0x42,0x0e,0xa1,0xf2]
  33 # CHECK-V8: warning: invalid instruction encoding
  34 # CHECK-V8: [0x42,0x0f,0x92,0xf3]
  35 # CHECK-V8: warning: invalid instruction encoding
  36 # CHECK-V8: [0x42,0x0f,0xa1,0xf2]
  37
  38 # The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN
  39 # uses the encoding for the invalid NV predicate operand. This test checks that
  40 # the disassembler is correctly disambiguating and decoding these instructions.
  41
  42 [0x00 0x00 0x10 0xf1]
  43 # CHECK: setpan #0
  44
  45 [0x00 0x02 0x10 0xf1]
  46 # CHECK: setpan #1
  47
  48 [0x00 0x00 0x10 0xe1]
  49 # CHECK: tst r0, r0
  50
  51 [0x00 0x02 0x10 0xe1]
  52 # CHECK: tst r0, r0, lsl #4