[AArch64] Add ARMv8.2-A FP16 vector instructions
[oota-llvm.git] / test / MC / AArch64 / neon-across.s
1 // RUN: llvm-mc -triple=arm64 -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
2
3 // Check that the assembler can handle the documented syntax for AArch64
4
5 //------------------------------------------------------------------------------
6 // Instructions across vector registers
7 //------------------------------------------------------------------------------
8
9         saddlv h0, v1.8b
10         saddlv h0, v1.16b
11         saddlv s0, v1.4h
12         saddlv s0, v1.8h
13         saddlv d0, v1.4s
14
15 // CHECK: saddlv        h0, v1.8b               // encoding: [0x20,0x38,0x30,0x0e]
16 // CHECK: saddlv        h0, v1.16b              // encoding: [0x20,0x38,0x30,0x4e]
17 // CHECK: saddlv        s0, v1.4h               // encoding: [0x20,0x38,0x70,0x0e]
18 // CHECK: saddlv        s0, v1.8h               // encoding: [0x20,0x38,0x70,0x4e]
19 // CHECK: saddlv        d0, v1.4s               // encoding: [0x20,0x38,0xb0,0x4e]
20
21         uaddlv h0, v1.8b
22         uaddlv h0, v1.16b
23         uaddlv s0, v1.4h
24         uaddlv s0, v1.8h
25         uaddlv d0, v1.4s
26
27 // CHECK: uaddlv        h0, v1.8b               // encoding: [0x20,0x38,0x30,0x2e]
28 // CHECK: uaddlv        h0, v1.16b              // encoding: [0x20,0x38,0x30,0x6e]
29 // CHECK: uaddlv        s0, v1.4h               // encoding: [0x20,0x38,0x70,0x2e]
30 // CHECK: uaddlv        s0, v1.8h               // encoding: [0x20,0x38,0x70,0x6e]
31 // CHECK: uaddlv        d0, v1.4s               // encoding: [0x20,0x38,0xb0,0x6e]
32
33         smaxv b0, v1.8b
34         smaxv b0, v1.16b
35         smaxv h0, v1.4h
36         smaxv h0, v1.8h
37         smaxv s0, v1.4s
38
39 // CHECK: smaxv b0, v1.8b               // encoding: [0x20,0xa8,0x30,0x0e]
40 // CHECK: smaxv b0, v1.16b              // encoding: [0x20,0xa8,0x30,0x4e]
41 // CHECK: smaxv h0, v1.4h               // encoding: [0x20,0xa8,0x70,0x0e]
42 // CHECK: smaxv h0, v1.8h               // encoding: [0x20,0xa8,0x70,0x4e]
43 // CHECK: smaxv s0, v1.4s               // encoding: [0x20,0xa8,0xb0,0x4e]
44
45         sminv b0, v1.8b
46         sminv b0, v1.16b
47         sminv h0, v1.4h
48         sminv h0, v1.8h
49         sminv s0, v1.4s
50
51 // CHECK: sminv b0, v1.8b               // encoding: [0x20,0xa8,0x31,0x0e]
52 // CHECK: sminv b0, v1.16b              // encoding: [0x20,0xa8,0x31,0x4e]
53 // CHECK: sminv h0, v1.4h               // encoding: [0x20,0xa8,0x71,0x0e]
54 // CHECK: sminv h0, v1.8h               // encoding: [0x20,0xa8,0x71,0x4e]
55 // CHECK: sminv s0, v1.4s               // encoding: [0x20,0xa8,0xb1,0x4e]
56
57         umaxv b0, v1.8b
58         umaxv b0, v1.16b
59         umaxv h0, v1.4h
60         umaxv h0, v1.8h
61         umaxv s0, v1.4s
62
63 // CHECK: umaxv b0, v1.8b               // encoding: [0x20,0xa8,0x30,0x2e]
64 // CHECK: umaxv b0, v1.16b              // encoding: [0x20,0xa8,0x30,0x6e]
65 // CHECK: umaxv h0, v1.4h               // encoding: [0x20,0xa8,0x70,0x2e]
66 // CHECK: umaxv h0, v1.8h               // encoding: [0x20,0xa8,0x70,0x6e]
67 // CHECK: umaxv s0, v1.4s               // encoding: [0x20,0xa8,0xb0,0x6e]
68
69         uminv b0, v1.8b
70         uminv b0, v1.16b
71         uminv h0, v1.4h
72         uminv h0, v1.8h
73         uminv s0, v1.4s
74
75 // CHECK: uminv b0, v1.8b               // encoding: [0x20,0xa8,0x31,0x2e]
76 // CHECK: uminv b0, v1.16b              // encoding: [0x20,0xa8,0x31,0x6e]
77 // CHECK: uminv h0, v1.4h               // encoding: [0x20,0xa8,0x71,0x2e]
78 // CHECK: uminv h0, v1.8h               // encoding: [0x20,0xa8,0x71,0x6e]
79 // CHECK: uminv s0, v1.4s               // encoding: [0x20,0xa8,0xb1,0x6e]
80
81         addv b0, v1.8b
82         addv b0, v1.16b
83         addv h0, v1.4h
84         addv h0, v1.8h
85         addv s0, v1.4s
86
87 // CHECK: addv  b0, v1.8b               // encoding: [0x20,0xb8,0x31,0x0e]
88 // CHECK: addv  b0, v1.16b              // encoding: [0x20,0xb8,0x31,0x4e]
89 // CHECK: addv  h0, v1.4h               // encoding: [0x20,0xb8,0x71,0x0e]
90 // CHECK: addv  h0, v1.8h               // encoding: [0x20,0xb8,0x71,0x4e]
91 // CHECK: addv  s0, v1.4s               // encoding: [0x20,0xb8,0xb1,0x4e]
92
93         fmaxnmv h0, v1.4h
94         fminnmv h0, v1.4h
95         fmaxv h0, v1.4h
96         fminv h0, v1.4h
97         fmaxnmv h0, v1.8h
98         fminnmv h0, v1.8h
99         fmaxv h0, v1.8h
100         fminv h0, v1.8h
101         fmaxnmv s0, v1.4s
102         fminnmv s0, v1.4s
103         fmaxv s0, v1.4s
104         fminv s0, v1.4s
105
106 // CHECK: fmaxnmv h0, v1.4h               // encoding: [0x20,0xc8,0x30,0x0e]
107 // CHECK: fminnmv h0, v1.4h               // encoding: [0x20,0xc8,0xb0,0x0e]
108 // CHECK: fmaxv   h0, v1.4h               // encoding: [0x20,0xf8,0x30,0x0e]
109 // CHECK: fminv   h0, v1.4h               // encoding: [0x20,0xf8,0xb0,0x0e]
110 // CHECK: fmaxnmv h0, v1.8h               // encoding: [0x20,0xc8,0x30,0x4e]
111 // CHECK: fminnmv h0, v1.8h               // encoding: [0x20,0xc8,0xb0,0x4e]
112 // CHECK: fmaxv   h0, v1.8h               // encoding: [0x20,0xf8,0x30,0x4e]
113 // CHECK: fminv   h0, v1.8h               // encoding: [0x20,0xf8,0xb0,0x4e]
114 // CHECK: fmaxnmv       s0, v1.4s               // encoding: [0x20,0xc8,0x30,0x6e]
115 // CHECK: fminnmv       s0, v1.4s               // encoding: [0x20,0xc8,0xb0,0x6e]
116 // CHECK: fmaxv s0, v1.4s               // encoding: [0x20,0xf8,0x30,0x6e]
117 // CHECK: fminv s0, v1.4s               // encoding: [0x20,0xf8,0xb0,0x6e]