1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
2 ; RUN: < %s | FileCheck %s
3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
4 ; RUN: < %s | FileCheck %s
6 @c = global i32 4, align 4
7 @d = global i32 9, align 4
8 @uc = global i32 4, align 4
9 @ud = global i32 9, align 4
10 @b1 = common global i32 0, align 4
12 ; Function Attrs: nounwind
15 ; CHECK-LABEL: .ent eq
17 %0 = load i32* @c, align 4
18 %1 = load i32* @d, align 4
19 %cmp = icmp eq i32 %0, %1
20 %conv = zext i1 %cmp to i32
21 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
22 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
24 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
25 ; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
26 ; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
27 ; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
28 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
30 store i32 %conv, i32* @b1, align 4
34 ; Function Attrs: nounwind
37 ; CHECK-LABEL: .ent ne
38 %0 = load i32* @c, align 4
39 %1 = load i32* @d, align 4
40 %cmp = icmp ne i32 %0, %1
41 %conv = zext i1 %cmp to i32
42 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
43 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
45 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
46 ; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
47 ; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
48 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
50 store i32 %conv, i32* @b1, align 4
54 ; Function Attrs: nounwind
57 ; CHECK-LABEL: .ent ugt
58 %0 = load i32* @uc, align 4
59 %1 = load i32* @ud, align 4
60 %cmp = icmp ugt i32 %0, %1
61 %conv = zext i1 %cmp to i32
62 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
63 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
64 ; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
65 ; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
66 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
67 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
69 store i32 %conv, i32* @b1, align 4
73 ; Function Attrs: nounwind
76 ; CHECK-LABEL: .ent ult
77 %0 = load i32* @uc, align 4
78 %1 = load i32* @ud, align 4
79 %cmp = icmp ult i32 %0, %1
80 %conv = zext i1 %cmp to i32
81 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
82 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
83 ; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
84 ; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
85 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
86 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
87 store i32 %conv, i32* @b1, align 4
91 ; Function Attrs: nounwind
94 ; CHECK-LABEL: .ent uge
95 %0 = load i32* @uc, align 4
96 %1 = load i32* @ud, align 4
97 %cmp = icmp uge i32 %0, %1
98 %conv = zext i1 %cmp to i32
99 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
100 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
101 ; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
102 ; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
103 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
104 ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
105 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
106 store i32 %conv, i32* @b1, align 4
110 ; Function Attrs: nounwind
113 ; CHECK-LABEL: .ent ule
114 %0 = load i32* @uc, align 4
115 %1 = load i32* @ud, align 4
116 %cmp = icmp ule i32 %0, %1
117 %conv = zext i1 %cmp to i32
118 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
119 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
120 ; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
121 ; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
122 ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
123 ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
124 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
125 store i32 %conv, i32* @b1, align 4
129 ; Function Attrs: nounwind
132 ; CHECK-LABEL: .ent sgt
133 %0 = load i32* @c, align 4
134 %1 = load i32* @d, align 4
135 %cmp = icmp sgt i32 %0, %1
136 %conv = zext i1 %cmp to i32
137 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
138 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
139 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
140 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
141 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
142 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
143 store i32 %conv, i32* @b1, align 4
147 ; Function Attrs: nounwind
150 ; CHECK-LABEL: .ent slt
151 %0 = load i32* @c, align 4
152 %1 = load i32* @d, align 4
153 %cmp = icmp slt i32 %0, %1
154 %conv = zext i1 %cmp to i32
155 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
156 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
157 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
158 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
159 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
160 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
161 store i32 %conv, i32* @b1, align 4
165 ; Function Attrs: nounwind
168 ; CHECK-LABEL: .ent sge
169 %0 = load i32* @c, align 4
170 %1 = load i32* @d, align 4
171 %cmp = icmp sge i32 %0, %1
172 %conv = zext i1 %cmp to i32
173 store i32 %conv, i32* @b1, align 4
174 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
175 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
176 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
177 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
178 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
179 ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
180 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
184 ; Function Attrs: nounwind
187 ; CHECK-LABEL: .ent sle
188 %0 = load i32* @c, align 4
189 %1 = load i32* @d, align 4
190 %cmp = icmp sle i32 %0, %1
191 %conv = zext i1 %cmp to i32
192 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
193 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
194 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
195 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
196 ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
197 ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
198 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
199 store i32 %conv, i32* @b1, align 4