1 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
3 define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
4 ; CHECK-LABEL: test_vcvt_f64_f32:
5 %vcvt1.i = fpext <2 x float> %x to <2 x double>
6 ; CHECK: fcvtl v0.2d, v0.2s
7 ret <2 x double> %vcvt1.i
11 define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
12 ; CHECK-LABEL: test_vcvt_high_f64_f32:
13 %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
14 %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
15 ; CHECK: fcvtl2 v0.2d, v0.4s
16 ret <2 x double> %vcvt1.i
20 define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
21 ; CHECK-LABEL: test_vcvt_f32_f64:
22 %vcvt1.i = fptrunc <2 x double> %v to <2 x float>
24 ret <2 x float> %vcvt1.i
28 define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
29 ; CHECK-LABEL: test_vcvt_high_f32_f64:
31 %cvt = fptrunc <2 x double> %v to <2 x float>
32 %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
34 ret <4 x float> %vcvt2.i
38 define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
39 ; CHECK-LABEL: test_vcvtx_f32_f64:
40 %vcvtx1.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
42 ret <2 x float> %vcvtx1.i
46 define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
47 ; CHECK-LABEL: test_vcvtx_high_f32_f64:
48 %vcvtx2.i = tail call <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
49 %res = shufflevector <2 x float> %x, <2 x float> %vcvtx2.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
56 declare <2 x double> @llvm.arm64.neon.vcvthighfp2df(<4 x float>) nounwind readnone
57 declare <2 x double> @llvm.arm64.neon.vcvtfp2df(<2 x float>) nounwind readnone
59 declare <2 x float> @llvm.arm64.neon.vcvtdf2fp(<2 x double>) nounwind readnone
60 declare <4 x float> @llvm.arm64.neon.vcvthighdf2fp(<2 x float>, <2 x double>) nounwind readnone
62 declare <2 x float> @llvm.arm64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
64 define i16 @to_half(float %in) {
65 ; CHECK-LABEL: to_half:
66 ; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0
67 ; CHECK: fmov w0, s[[HALFVAL]]
69 %res = call i16 @llvm.convert.to.fp16(float %in)
73 define float @from_half(i16 %in) {
74 ; CHECK-LABEL: from_half:
75 ; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
76 ; CHECK: fcvt s0, h[[HALFVAL]]
77 %res = call float @llvm.convert.from.fp16(i16 %in)
81 declare float @llvm.convert.from.fp16(i16) #1
82 declare i16 @llvm.convert.to.fp16(float) #1