1 ; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
3 ; These tests just check that the plumbing is in place for @llvm.bitreverse. The
4 ; actual output is massive at the moment as llvm.bitreverse is not yet legal.
6 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
8 define <2 x i16> @f(<2 x i16> %a) {
11 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
15 declare i8 @llvm.bitreverse.i8(i8) readnone
17 ; Unfortunately some of the shift-and-inserts become BFIs, and some do not :(
20 ; CHECK-DAG: lsr [[S5:w.*]], w0, #5
21 ; CHECK-DAG: lsr [[S4:w.*]], w0, #4
22 ; CHECK-DAG: lsr [[S3:w.*]], w0, #3
23 ; CHECK-DAG: lsr [[S2:w.*]], w0, #2
24 ; CHECK-DAG: lsl [[L1:w.*]], w0, #29
25 ; CHECK-DAG: lsl [[L2:w.*]], w0, #19
26 ; CHECK-DAG: lsl [[L3:w.*]], w0, #17
28 ; CHECK-DAG: and [[T1:w.*]], [[L1]], #0x40000000
29 ; CHECK-DAG: bfi [[T1]], w0, #31, #1
30 ; CHECK-DAG: bfi [[T1]], [[S2]], #29, #1
31 ; CHECK-DAG: bfi [[T1]], [[S3]], #28, #1
32 ; CHECK-DAG: bfi [[T1]], [[S4]], #27, #1
33 ; CHECK-DAG: bfi [[T1]], [[S5]], #26, #1
34 ; CHECK-DAG: and [[T2:w.*]], [[L2]], #0x2000000
35 ; CHECK-DAG: and [[T3:w.*]], [[L3]], #0x1000000
36 ; CHECK-DAG: orr [[T4:w.*]], [[T1]], [[T2]]
37 ; CHECK-DAG: orr [[T5:w.*]], [[T4]], [[T3]]
38 ; CHECK: lsr w0, [[T5]], #24
40 %b = call i8 @llvm.bitreverse.i8(i8 %a)
44 declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone
46 define <8 x i8> @g_vec(<8 x i8> %a) {
47 ; Try and match as much of the sequence as precisely as possible.
50 ; CHECK-DAG: movi [[M1:v.*]], #0x80
51 ; CHECK-DAG: movi [[M2:v.*]], #0x40
52 ; CHECK-DAG: movi [[M3:v.*]], #0x20
53 ; CHECK-DAG: movi [[M4:v.*]], #0x10
54 ; CHECK-DAG: movi [[M5:v.*]], #0x8
55 ; CHECK-DAG: movi [[M6:v.*]], #0x4{{$}}
56 ; CHECK-DAG: movi [[M7:v.*]], #0x2{{$}}
57 ; CHECK-DAG: movi [[M8:v.*]], #0x1{{$}}
58 ; CHECK-DAG: shl [[S1:v.*]], v0.8b, #7
59 ; CHECK-DAG: shl [[S2:v.*]], v0.8b, #5
60 ; CHECK-DAG: shl [[S3:v.*]], v0.8b, #3
61 ; CHECK-DAG: shl [[S4:v.*]], v0.8b, #1
62 ; CHECK-DAG: ushr [[S5:v.*]], v0.8b, #1
63 ; CHECK-DAG: ushr [[S6:v.*]], v0.8b, #3
64 ; CHECK-DAG: ushr [[S7:v.*]], v0.8b, #5
65 ; CHECK-DAG: ushr [[S8:v.*]], v0.8b, #7
66 ; CHECK-DAG: and [[A1:v.*]], [[S1]], [[M1]]
67 ; CHECK-DAG: and [[A2:v.*]], [[S2]], [[M2]]
68 ; CHECK-DAG: and [[A3:v.*]], [[S3]], [[M3]]
69 ; CHECK-DAG: and [[A4:v.*]], [[S4]], [[M4]]
70 ; CHECK-DAG: and [[A5:v.*]], [[S5]], [[M5]]
71 ; CHECK-DAG: and [[A6:v.*]], [[S6]], [[M6]]
72 ; CHECK-DAG: and [[A7:v.*]], [[S7]], [[M7]]
73 ; CHECK-DAG: and [[A8:v.*]], [[S8]], [[M8]]
75 ; The rest can be ORRed together in any order; it's not worth the test
76 ; maintenance to match them precisely.
85 %b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)