1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI LLVM_FINAL : public ImmutablePass, public TargetTransformInfo {
36 const X86Subtarget *ST;
37 const X86TargetLowering *TLI;
39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
40 /// are set if the result needs to be inserted and/or extracted from vectors.
41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
44 X86TTI() : ImmutablePass(ID), ST(0), TLI(0) {
45 llvm_unreachable("This pass cannot be directly constructed");
48 X86TTI(const X86TargetMachine *TM)
49 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
50 TLI(TM->getTargetLowering()) {
51 initializeX86TTIPass(*PassRegistry::getPassRegistry());
54 virtual void initializePass() LLVM_OVERRIDE {
58 virtual void finalizePass() {
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const LLVM_OVERRIDE {
63 TargetTransformInfo::getAnalysisUsage(AU);
66 /// Pass identification.
69 /// Provide necessary pointer adjustments for the two base classes.
70 virtual void *getAdjustedAnalysisPointer(const void *ID) LLVM_OVERRIDE {
71 if (ID == &TargetTransformInfo::ID)
72 return (TargetTransformInfo*)this;
76 /// \name Scalar TTI Implementations
78 virtual PopcntSupportKind
79 getPopcntSupport(unsigned TyWidth) const LLVM_OVERRIDE;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const LLVM_OVERRIDE;
87 virtual unsigned getRegisterBitWidth(bool Vector) const LLVM_OVERRIDE;
88 virtual unsigned getMaximumUnrollFactor() const LLVM_OVERRIDE;
89 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
91 OperandValueKind) const LLVM_OVERRIDE;
92 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
93 int Index, Type *SubTp) const LLVM_OVERRIDE;
94 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
95 Type *Src) const LLVM_OVERRIDE;
96 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
97 Type *CondTy) const LLVM_OVERRIDE;
98 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
99 unsigned Index) const LLVM_OVERRIDE;
100 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
102 unsigned AddressSpace) const LLVM_OVERRIDE;
105 getAddressComputationCost(Type *PtrTy, bool IsComplex) const LLVM_OVERRIDE;
107 virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
108 bool IsPairwiseForm) const LLVM_OVERRIDE;
113 } // end anonymous namespace
115 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
116 "X86 Target Transform Info", true, true, false)
120 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
121 return new X86TTI(TM);
125 //===----------------------------------------------------------------------===//
129 //===----------------------------------------------------------------------===//
131 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
132 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
133 // TODO: Currently the __builtin_popcount() implementation using SSE3
134 // instructions is inefficient. Once the problem is fixed, we should
135 // call ST->hasSSE3() instead of ST->hasPOPCNT().
136 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
139 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
140 if (Vector && !ST->hasSSE1())
148 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
150 if (ST->hasAVX()) return 256;
151 if (ST->hasSSE1()) return 128;
161 unsigned X86TTI::getMaximumUnrollFactor() const {
165 // Sandybridge and Haswell have multiple execution ports and pipelined
173 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
174 OperandValueKind Op1Info,
175 OperandValueKind Op2Info) const {
176 // Legalize the type.
177 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
179 int ISD = TLI->InstructionOpcodeToISD(Opcode);
180 assert(ISD && "Invalid opcode");
182 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
183 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
184 // customize them to detect the cases where shift amount is a scalar one.
185 { ISD::SHL, MVT::v4i32, 1 },
186 { ISD::SRL, MVT::v4i32, 1 },
187 { ISD::SRA, MVT::v4i32, 1 },
188 { ISD::SHL, MVT::v8i32, 1 },
189 { ISD::SRL, MVT::v8i32, 1 },
190 { ISD::SRA, MVT::v8i32, 1 },
191 { ISD::SHL, MVT::v2i64, 1 },
192 { ISD::SRL, MVT::v2i64, 1 },
193 { ISD::SHL, MVT::v4i64, 1 },
194 { ISD::SRL, MVT::v4i64, 1 },
196 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
197 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
199 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
200 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
202 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
203 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
204 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
206 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
207 { ISD::SDIV, MVT::v32i8, 32*20 },
208 { ISD::SDIV, MVT::v16i16, 16*20 },
209 { ISD::SDIV, MVT::v8i32, 8*20 },
210 { ISD::SDIV, MVT::v4i64, 4*20 },
211 { ISD::UDIV, MVT::v32i8, 32*20 },
212 { ISD::UDIV, MVT::v16i16, 16*20 },
213 { ISD::UDIV, MVT::v8i32, 8*20 },
214 { ISD::UDIV, MVT::v4i64, 4*20 },
217 // Look for AVX2 lowering tricks.
219 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
221 return LT.first * AVX2CostTable[Idx].Cost;
224 static const CostTblEntry<MVT::SimpleValueType>
225 SSE2UniformConstCostTable[] = {
226 // We don't correctly identify costs of casts because they are marked as
228 // Constant splats are cheaper for the following instructions.
229 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
230 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
231 { ISD::SHL, MVT::v4i32, 1 }, // pslld
232 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
234 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
235 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
236 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
237 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
239 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
240 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
241 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
244 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
246 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
248 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
252 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
253 // We don't correctly identify costs of casts because they are marked as
255 // For some cases, where the shift amount is a scalar we would be able
256 // to generate better code. Unfortunately, when this is the case the value
257 // (the splat) will get hoisted out of the loop, thereby making it invisible
258 // to ISel. The cost model must return worst case assumptions because it is
259 // used for vectorization and we don't want to make vectorized code worse
261 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
262 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
263 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
264 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
266 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
267 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
268 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
269 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
271 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
272 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
273 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
274 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
276 // It is not a good idea to vectorize division. We have to scalarize it and
277 // in the process we will often end up having to spilling regular
278 // registers. The overhead of division is going to dominate most kernels
279 // anyways so try hard to prevent vectorization of division - it is
280 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
281 // to hide "20 cycles" for each lane.
282 { ISD::SDIV, MVT::v16i8, 16*20 },
283 { ISD::SDIV, MVT::v8i16, 8*20 },
284 { ISD::SDIV, MVT::v4i32, 4*20 },
285 { ISD::SDIV, MVT::v2i64, 2*20 },
286 { ISD::UDIV, MVT::v16i8, 16*20 },
287 { ISD::UDIV, MVT::v8i16, 8*20 },
288 { ISD::UDIV, MVT::v4i32, 4*20 },
289 { ISD::UDIV, MVT::v2i64, 2*20 },
293 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
295 return LT.first * SSE2CostTable[Idx].Cost;
298 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
299 // We don't have to scalarize unsupported ops. We can issue two half-sized
300 // operations and we only need to extract the upper YMM half.
301 // Two ops + 1 extract + 1 insert = 4.
302 { ISD::MUL, MVT::v8i32, 4 },
303 { ISD::SUB, MVT::v8i32, 4 },
304 { ISD::ADD, MVT::v8i32, 4 },
305 { ISD::SUB, MVT::v4i64, 4 },
306 { ISD::ADD, MVT::v4i64, 4 },
307 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
308 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
309 // Because we believe v4i64 to be a legal type, we must also include the
310 // split factor of two in the cost table. Therefore, the cost here is 18
312 { ISD::MUL, MVT::v4i64, 18 },
315 // Look for AVX1 lowering tricks.
316 if (ST->hasAVX() && !ST->hasAVX2()) {
317 int Idx = CostTableLookup(AVX1CostTable, ISD, LT.second);
319 return LT.first * AVX1CostTable[Idx].Cost;
322 // Custom lowering of vectors.
323 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
324 // A v2i64/v4i64 and multiply is custom lowered as a series of long
325 // multiplies(3), shifts(4) and adds(2).
326 { ISD::MUL, MVT::v2i64, 9 },
327 { ISD::MUL, MVT::v4i64, 9 },
329 int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
331 return LT.first * CustomLowered[Idx].Cost;
333 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
334 // 2x pmuludq, 2x shuffle.
335 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
339 // Fallback to the default implementation.
340 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
344 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
346 // We only estimate the cost of reverse shuffles.
347 if (Kind != SK_Reverse)
348 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
350 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
352 if (LT.second.getSizeInBits() > 128)
353 Cost = 3; // Extract + insert + copy.
355 // Multiple by the number of parts.
356 return Cost * LT.first;
359 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
360 int ISD = TLI->InstructionOpcodeToISD(Opcode);
361 assert(ISD && "Invalid opcode");
363 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
364 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
366 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
368 // These are somewhat magic numbers justified by looking at the output of
369 // Intel's IACA, running some kernels and making sure when we take
370 // legalization into account the throughput will be overestimated.
371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
373 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
374 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
377 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
378 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
379 // There are faster sequences for float conversions.
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
383 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
387 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
390 if (ST->hasSSE2() && !ST->hasAVX()) {
392 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
394 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
397 EVT SrcTy = TLI->getValueType(Src);
398 EVT DstTy = TLI->getValueType(Dst);
400 // The function getSimpleVT only handles simple value types.
401 if (!SrcTy.isSimple() || !DstTy.isSimple())
402 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
404 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
405 AVXConversionTbl[] = {
406 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
407 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
408 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
409 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
410 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
411 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
412 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
413 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
414 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 },
416 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
417 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
418 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
419 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
420 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
421 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
422 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
423 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
424 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
425 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
426 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
427 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
429 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
430 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
431 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
432 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
433 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
434 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
435 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
436 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
437 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
438 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
439 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
440 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
442 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
443 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
444 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
445 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
446 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
447 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
448 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
449 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
453 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
454 SrcTy.getSimpleVT());
456 return AVXConversionTbl[Idx].Cost;
459 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
462 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
463 Type *CondTy) const {
464 // Legalize the type.
465 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
469 int ISD = TLI->InstructionOpcodeToISD(Opcode);
470 assert(ISD && "Invalid opcode");
472 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
473 { ISD::SETCC, MVT::v2f64, 1 },
474 { ISD::SETCC, MVT::v4f32, 1 },
475 { ISD::SETCC, MVT::v2i64, 1 },
476 { ISD::SETCC, MVT::v4i32, 1 },
477 { ISD::SETCC, MVT::v8i16, 1 },
478 { ISD::SETCC, MVT::v16i8, 1 },
481 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
482 { ISD::SETCC, MVT::v4f64, 1 },
483 { ISD::SETCC, MVT::v8f32, 1 },
484 // AVX1 does not support 8-wide integer compare.
485 { ISD::SETCC, MVT::v4i64, 4 },
486 { ISD::SETCC, MVT::v8i32, 4 },
487 { ISD::SETCC, MVT::v16i16, 4 },
488 { ISD::SETCC, MVT::v32i8, 4 },
491 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
492 { ISD::SETCC, MVT::v4i64, 1 },
493 { ISD::SETCC, MVT::v8i32, 1 },
494 { ISD::SETCC, MVT::v16i16, 1 },
495 { ISD::SETCC, MVT::v32i8, 1 },
499 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
501 return LT.first * AVX2CostTbl[Idx].Cost;
505 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
507 return LT.first * AVX1CostTbl[Idx].Cost;
510 if (ST->hasSSE42()) {
511 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
513 return LT.first * SSE42CostTbl[Idx].Cost;
516 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
519 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
520 unsigned Index) const {
521 assert(Val->isVectorTy() && "This must be a vector type");
524 // Legalize the type.
525 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
527 // This type is legalized to a scalar type.
528 if (!LT.second.isVector())
531 // The type may be split. Normalize the index to the new type.
532 unsigned Width = LT.second.getVectorNumElements();
533 Index = Index % Width;
535 // Floating point scalars are already located in index #0.
536 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
540 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
543 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
544 bool Extract) const {
545 assert (Ty->isVectorTy() && "Can only scalarize vectors");
548 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
550 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
552 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
558 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
559 unsigned AddressSpace) const {
560 // Handle non-power-of-two vectors such as <3 x float>
561 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
562 unsigned NumElem = VTy->getVectorNumElements();
564 // Handle a few common cases:
566 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
567 // Cost = 64 bit store + extract + 32 bit store.
571 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
572 // Cost = 128 bit store + unpack + 64 bit store.
575 // Assume that all other non-power-of-two numbers are scalarized.
576 if (!isPowerOf2_32(NumElem)) {
577 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
578 VTy->getScalarType(),
581 unsigned SplitCost = getScalarizationOverhead(Src,
582 Opcode == Instruction::Load,
583 Opcode==Instruction::Store);
584 return NumElem * Cost + SplitCost;
588 // Legalize the type.
589 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
590 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
593 // Each load/store unit costs 1.
594 unsigned Cost = LT.first * 1;
596 // On Sandybridge 256bit load/stores are double pumped
597 // (but not on Haswell).
598 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
604 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
605 // Address computations in vectorized code with non-consecutive addresses will
606 // likely result in more instructions compared to scalar code where the
607 // computation can more often be merged into the index mode. The resulting
608 // extra micro-ops can significantly decrease throughput.
609 unsigned NumVectorInstToHideOverhead = 10;
611 if (Ty->isVectorTy() && IsComplex)
612 return NumVectorInstToHideOverhead;
614 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
617 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
618 bool IsPairwise) const {
620 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
624 int ISD = TLI->InstructionOpcodeToISD(Opcode);
625 assert(ISD && "Invalid opcode");
627 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
628 // and make it as the cost.
630 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
631 { ISD::FADD, MVT::v2f64, 2 },
632 { ISD::FADD, MVT::v4f32, 4 },
633 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
634 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
635 { ISD::ADD, MVT::v8i16, 5 },
638 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
639 { ISD::FADD, MVT::v4f32, 4 },
640 { ISD::FADD, MVT::v4f64, 5 },
641 { ISD::FADD, MVT::v8f32, 7 },
642 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
643 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
644 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
645 { ISD::ADD, MVT::v8i16, 5 },
646 { ISD::ADD, MVT::v8i32, 5 },
649 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
650 { ISD::FADD, MVT::v2f64, 2 },
651 { ISD::FADD, MVT::v4f32, 4 },
652 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
653 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
654 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
657 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
658 { ISD::FADD, MVT::v4f32, 3 },
659 { ISD::FADD, MVT::v4f64, 3 },
660 { ISD::FADD, MVT::v8f32, 4 },
661 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
662 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
663 { ISD::ADD, MVT::v4i64, 3 },
664 { ISD::ADD, MVT::v8i16, 4 },
665 { ISD::ADD, MVT::v8i32, 5 },
670 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
672 return LT.first * AVX1CostTblPairWise[Idx].Cost;
675 if (ST->hasSSE42()) {
676 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
678 return LT.first * SSE42CostTblPairWise[Idx].Cost;
682 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
684 return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
687 if (ST->hasSSE42()) {
688 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
690 return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
694 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);