1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/IR/IntrinsicInst.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Target/CostTable.h"
24 #include "llvm/Target/TargetLowering.h"
27 // Declare the pass initialization routine locally as target-specific passes
28 // don't havve a target-wide initialization entry point, and so we rely on the
29 // pass constructor initialization.
31 void initializeX86TTIPass(PassRegistry &);
36 class X86TTI final : public ImmutablePass, public TargetTransformInfo {
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() override {
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
60 TargetTransformInfo::getAnalysisUsage(AU);
63 /// Pass identification.
66 /// Provide necessary pointer adjustments for the two base classes.
67 virtual void *getAdjustedAnalysisPointer(const void *ID) override {
68 if (ID == &TargetTransformInfo::ID)
69 return (TargetTransformInfo*)this;
73 /// \name Scalar TTI Implementations
75 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
79 /// \name Vector TTI Implementations
82 virtual unsigned getNumberOfRegisters(bool Vector) const override;
83 virtual unsigned getRegisterBitWidth(bool Vector) const override;
84 virtual unsigned getMaximumUnrollFactor() const override;
85 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
87 OperandValueKind) const override;
88 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
89 int Index, Type *SubTp) const override;
90 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
91 Type *Src) const override;
92 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
93 Type *CondTy) const override;
94 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
95 unsigned Index) const override;
96 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
98 unsigned AddressSpace) const override;
101 getAddressComputationCost(Type *PtrTy, bool IsComplex) const override;
103 virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
104 bool IsPairwiseForm) const override;
106 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
108 virtual unsigned getIntImmCost(unsigned Opcode, const APInt &Imm,
109 Type *Ty) const override;
110 virtual unsigned getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
111 Type *Ty) const override;
116 } // end anonymous namespace
118 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
119 "X86 Target Transform Info", true, true, false)
123 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
124 return new X86TTI(TM);
128 //===----------------------------------------------------------------------===//
132 //===----------------------------------------------------------------------===//
134 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
135 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
136 // TODO: Currently the __builtin_popcount() implementation using SSE3
137 // instructions is inefficient. Once the problem is fixed, we should
138 // call ST->hasSSE3() instead of ST->hasPOPCNT().
139 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
142 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
143 if (Vector && !ST->hasSSE1())
151 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
153 if (ST->hasAVX()) return 256;
154 if (ST->hasSSE1()) return 128;
164 unsigned X86TTI::getMaximumUnrollFactor() const {
168 // Sandybridge and Haswell have multiple execution ports and pipelined
176 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
177 OperandValueKind Op1Info,
178 OperandValueKind Op2Info) const {
179 // Legalize the type.
180 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
182 int ISD = TLI->InstructionOpcodeToISD(Opcode);
183 assert(ISD && "Invalid opcode");
185 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
186 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
187 // customize them to detect the cases where shift amount is a scalar one.
188 { ISD::SHL, MVT::v4i32, 1 },
189 { ISD::SRL, MVT::v4i32, 1 },
190 { ISD::SRA, MVT::v4i32, 1 },
191 { ISD::SHL, MVT::v8i32, 1 },
192 { ISD::SRL, MVT::v8i32, 1 },
193 { ISD::SRA, MVT::v8i32, 1 },
194 { ISD::SHL, MVT::v2i64, 1 },
195 { ISD::SRL, MVT::v2i64, 1 },
196 { ISD::SHL, MVT::v4i64, 1 },
197 { ISD::SRL, MVT::v4i64, 1 },
199 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
200 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
202 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
203 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
205 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
206 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
207 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
209 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
210 { ISD::SDIV, MVT::v32i8, 32*20 },
211 { ISD::SDIV, MVT::v16i16, 16*20 },
212 { ISD::SDIV, MVT::v8i32, 8*20 },
213 { ISD::SDIV, MVT::v4i64, 4*20 },
214 { ISD::UDIV, MVT::v32i8, 32*20 },
215 { ISD::UDIV, MVT::v16i16, 16*20 },
216 { ISD::UDIV, MVT::v8i32, 8*20 },
217 { ISD::UDIV, MVT::v4i64, 4*20 },
220 // Look for AVX2 lowering tricks.
222 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
223 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
224 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
225 // On AVX2, a packed v16i16 shift left by a constant build_vector
226 // is lowered into a vector multiply (vpmullw).
229 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
231 return LT.first * AVX2CostTable[Idx].Cost;
234 static const CostTblEntry<MVT::SimpleValueType>
235 SSE2UniformConstCostTable[] = {
236 // We don't correctly identify costs of casts because they are marked as
238 // Constant splats are cheaper for the following instructions.
239 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
240 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
241 { ISD::SHL, MVT::v4i32, 1 }, // pslld
242 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
244 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
245 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
246 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
247 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
249 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
250 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
251 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
254 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
256 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
258 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
261 if (ISD == ISD::SHL &&
262 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
264 if ((VT == MVT::v8i16 && ST->hasSSE2()) ||
265 (VT == MVT::v4i32 && ST->hasSSE41()))
266 // Vector shift left by non uniform constant can be lowered
267 // into vector multiply (pmullw/pmulld).
269 if (VT == MVT::v4i32 && ST->hasSSE2())
270 // A vector shift left by non uniform constant is converted
271 // into a vector multiply; the new multiply is eventually
272 // lowered into a sequence of shuffles and 2 x pmuludq.
276 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
277 // We don't correctly identify costs of casts because they are marked as
279 // For some cases, where the shift amount is a scalar we would be able
280 // to generate better code. Unfortunately, when this is the case the value
281 // (the splat) will get hoisted out of the loop, thereby making it invisible
282 // to ISel. The cost model must return worst case assumptions because it is
283 // used for vectorization and we don't want to make vectorized code worse
285 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
286 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
287 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
288 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
289 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
291 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
292 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
293 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
294 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
296 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
297 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
298 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
299 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
301 // It is not a good idea to vectorize division. We have to scalarize it and
302 // in the process we will often end up having to spilling regular
303 // registers. The overhead of division is going to dominate most kernels
304 // anyways so try hard to prevent vectorization of division - it is
305 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
306 // to hide "20 cycles" for each lane.
307 { ISD::SDIV, MVT::v16i8, 16*20 },
308 { ISD::SDIV, MVT::v8i16, 8*20 },
309 { ISD::SDIV, MVT::v4i32, 4*20 },
310 { ISD::SDIV, MVT::v2i64, 2*20 },
311 { ISD::UDIV, MVT::v16i8, 16*20 },
312 { ISD::UDIV, MVT::v8i16, 8*20 },
313 { ISD::UDIV, MVT::v4i32, 4*20 },
314 { ISD::UDIV, MVT::v2i64, 2*20 },
318 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
320 return LT.first * SSE2CostTable[Idx].Cost;
323 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
324 // We don't have to scalarize unsupported ops. We can issue two half-sized
325 // operations and we only need to extract the upper YMM half.
326 // Two ops + 1 extract + 1 insert = 4.
327 { ISD::MUL, MVT::v16i16, 4 },
328 { ISD::MUL, MVT::v8i32, 4 },
329 { ISD::SUB, MVT::v8i32, 4 },
330 { ISD::ADD, MVT::v8i32, 4 },
331 { ISD::SUB, MVT::v4i64, 4 },
332 { ISD::ADD, MVT::v4i64, 4 },
333 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
334 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
335 // Because we believe v4i64 to be a legal type, we must also include the
336 // split factor of two in the cost table. Therefore, the cost here is 18
338 { ISD::MUL, MVT::v4i64, 18 },
341 // Look for AVX1 lowering tricks.
342 if (ST->hasAVX() && !ST->hasAVX2()) {
345 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
346 // sequence of extract + two vector multiply + insert.
347 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
348 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)
351 int Idx = CostTableLookup(AVX1CostTable, ISD, VT);
353 return LT.first * AVX1CostTable[Idx].Cost;
356 // Custom lowering of vectors.
357 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
358 // A v2i64/v4i64 and multiply is custom lowered as a series of long
359 // multiplies(3), shifts(4) and adds(2).
360 { ISD::MUL, MVT::v2i64, 9 },
361 { ISD::MUL, MVT::v4i64, 9 },
363 int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
365 return LT.first * CustomLowered[Idx].Cost;
367 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
368 // 2x pmuludq, 2x shuffle.
369 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
373 // Fallback to the default implementation.
374 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
378 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
380 // We only estimate the cost of reverse shuffles.
381 if (Kind != SK_Reverse)
382 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
384 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
386 if (LT.second.getSizeInBits() > 128)
387 Cost = 3; // Extract + insert + copy.
389 // Multiple by the number of parts.
390 return Cost * LT.first;
393 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
394 int ISD = TLI->InstructionOpcodeToISD(Opcode);
395 assert(ISD && "Invalid opcode");
397 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
398 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
400 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
402 // These are somewhat magic numbers justified by looking at the output of
403 // Intel's IACA, running some kernels and making sure when we take
404 // legalization into account the throughput will be overestimated.
405 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
406 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
407 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
408 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
409 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
410 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
411 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
412 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
413 // There are faster sequences for float conversions.
414 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
415 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
416 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
417 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
418 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
419 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
420 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
421 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
424 if (ST->hasSSE2() && !ST->hasAVX()) {
426 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
428 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
431 EVT SrcTy = TLI->getValueType(Src);
432 EVT DstTy = TLI->getValueType(Dst);
434 // The function getSimpleVT only handles simple value types.
435 if (!SrcTy.isSimple() || !DstTy.isSimple())
436 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
438 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
439 AVX2ConversionTbl[] = {
440 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
441 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
442 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
443 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
444 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
445 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
446 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
447 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
448 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
449 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
450 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
451 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
452 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
453 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
454 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
455 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
457 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
458 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
459 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
460 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
461 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
462 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
465 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
466 AVXConversionTbl[] = {
467 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
468 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
469 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
470 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
471 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
472 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
473 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
474 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
475 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
476 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
477 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
478 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
479 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
480 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
481 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
482 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
484 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
485 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
486 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
487 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
488 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
489 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
490 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
492 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
493 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
494 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
495 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
496 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
497 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
498 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
499 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
500 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
501 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
502 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
503 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
505 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
506 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
507 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
508 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
509 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
510 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
511 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
512 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
513 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
514 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
515 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
516 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
518 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
519 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
523 int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
524 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
526 return AVX2ConversionTbl[Idx].Cost;
530 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
531 SrcTy.getSimpleVT());
533 return AVXConversionTbl[Idx].Cost;
536 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
539 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
540 Type *CondTy) const {
541 // Legalize the type.
542 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
546 int ISD = TLI->InstructionOpcodeToISD(Opcode);
547 assert(ISD && "Invalid opcode");
549 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
550 { ISD::SETCC, MVT::v2f64, 1 },
551 { ISD::SETCC, MVT::v4f32, 1 },
552 { ISD::SETCC, MVT::v2i64, 1 },
553 { ISD::SETCC, MVT::v4i32, 1 },
554 { ISD::SETCC, MVT::v8i16, 1 },
555 { ISD::SETCC, MVT::v16i8, 1 },
558 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
559 { ISD::SETCC, MVT::v4f64, 1 },
560 { ISD::SETCC, MVT::v8f32, 1 },
561 // AVX1 does not support 8-wide integer compare.
562 { ISD::SETCC, MVT::v4i64, 4 },
563 { ISD::SETCC, MVT::v8i32, 4 },
564 { ISD::SETCC, MVT::v16i16, 4 },
565 { ISD::SETCC, MVT::v32i8, 4 },
568 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
569 { ISD::SETCC, MVT::v4i64, 1 },
570 { ISD::SETCC, MVT::v8i32, 1 },
571 { ISD::SETCC, MVT::v16i16, 1 },
572 { ISD::SETCC, MVT::v32i8, 1 },
576 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
578 return LT.first * AVX2CostTbl[Idx].Cost;
582 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
584 return LT.first * AVX1CostTbl[Idx].Cost;
587 if (ST->hasSSE42()) {
588 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
590 return LT.first * SSE42CostTbl[Idx].Cost;
593 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
596 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
597 unsigned Index) const {
598 assert(Val->isVectorTy() && "This must be a vector type");
601 // Legalize the type.
602 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
604 // This type is legalized to a scalar type.
605 if (!LT.second.isVector())
608 // The type may be split. Normalize the index to the new type.
609 unsigned Width = LT.second.getVectorNumElements();
610 Index = Index % Width;
612 // Floating point scalars are already located in index #0.
613 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
617 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
620 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
621 bool Extract) const {
622 assert (Ty->isVectorTy() && "Can only scalarize vectors");
625 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
627 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
629 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
635 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
636 unsigned AddressSpace) const {
637 // Handle non-power-of-two vectors such as <3 x float>
638 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
639 unsigned NumElem = VTy->getVectorNumElements();
641 // Handle a few common cases:
643 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
644 // Cost = 64 bit store + extract + 32 bit store.
648 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
649 // Cost = 128 bit store + unpack + 64 bit store.
652 // Assume that all other non-power-of-two numbers are scalarized.
653 if (!isPowerOf2_32(NumElem)) {
654 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
655 VTy->getScalarType(),
658 unsigned SplitCost = getScalarizationOverhead(Src,
659 Opcode == Instruction::Load,
660 Opcode==Instruction::Store);
661 return NumElem * Cost + SplitCost;
665 // Legalize the type.
666 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
667 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
670 // Each load/store unit costs 1.
671 unsigned Cost = LT.first * 1;
673 // On Sandybridge 256bit load/stores are double pumped
674 // (but not on Haswell).
675 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
681 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
682 // Address computations in vectorized code with non-consecutive addresses will
683 // likely result in more instructions compared to scalar code where the
684 // computation can more often be merged into the index mode. The resulting
685 // extra micro-ops can significantly decrease throughput.
686 unsigned NumVectorInstToHideOverhead = 10;
688 if (Ty->isVectorTy() && IsComplex)
689 return NumVectorInstToHideOverhead;
691 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
694 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
695 bool IsPairwise) const {
697 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
701 int ISD = TLI->InstructionOpcodeToISD(Opcode);
702 assert(ISD && "Invalid opcode");
704 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
705 // and make it as the cost.
707 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
708 { ISD::FADD, MVT::v2f64, 2 },
709 { ISD::FADD, MVT::v4f32, 4 },
710 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
711 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
712 { ISD::ADD, MVT::v8i16, 5 },
715 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
716 { ISD::FADD, MVT::v4f32, 4 },
717 { ISD::FADD, MVT::v4f64, 5 },
718 { ISD::FADD, MVT::v8f32, 7 },
719 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
720 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
721 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
722 { ISD::ADD, MVT::v8i16, 5 },
723 { ISD::ADD, MVT::v8i32, 5 },
726 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
727 { ISD::FADD, MVT::v2f64, 2 },
728 { ISD::FADD, MVT::v4f32, 4 },
729 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
730 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
731 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
734 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
735 { ISD::FADD, MVT::v4f32, 3 },
736 { ISD::FADD, MVT::v4f64, 3 },
737 { ISD::FADD, MVT::v8f32, 4 },
738 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
739 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
740 { ISD::ADD, MVT::v4i64, 3 },
741 { ISD::ADD, MVT::v8i16, 4 },
742 { ISD::ADD, MVT::v8i32, 5 },
747 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
749 return LT.first * AVX1CostTblPairWise[Idx].Cost;
752 if (ST->hasSSE42()) {
753 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
755 return LT.first * SSE42CostTblPairWise[Idx].Cost;
759 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
761 return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
764 if (ST->hasSSE42()) {
765 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
767 return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
771 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);
774 unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
775 assert(Ty->isIntegerTy());
777 unsigned BitSize = Ty->getPrimitiveSizeInBits();
781 if (Imm.getBitWidth() <= 64 &&
782 (isInt<32>(Imm.getSExtValue()) || isUInt<32>(Imm.getZExtValue())))
785 return 2 * TCC_Basic;
788 unsigned X86TTI::getIntImmCost(unsigned Opcode, const APInt &Imm,
790 assert(Ty->isIntegerTy());
792 unsigned BitSize = Ty->getPrimitiveSizeInBits();
797 case Instruction::Add:
798 case Instruction::Sub:
799 case Instruction::Mul:
800 case Instruction::UDiv:
801 case Instruction::SDiv:
802 case Instruction::URem:
803 case Instruction::SRem:
804 case Instruction::Shl:
805 case Instruction::LShr:
806 case Instruction::AShr:
807 case Instruction::And:
808 case Instruction::Or:
809 case Instruction::Xor:
810 case Instruction::ICmp:
811 if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
814 return X86TTI::getIntImmCost(Imm, Ty);
815 case Instruction::Trunc:
816 case Instruction::ZExt:
817 case Instruction::SExt:
818 case Instruction::IntToPtr:
819 case Instruction::PtrToInt:
820 case Instruction::BitCast:
821 case Instruction::Call:
822 case Instruction::Select:
823 case Instruction::Ret:
824 case Instruction::Load:
825 case Instruction::Store:
826 return X86TTI::getIntImmCost(Imm, Ty);
828 return TargetTransformInfo::getIntImmCost(Opcode, Imm, Ty);
831 unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
833 assert(Ty->isIntegerTy());
835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
840 default: return TargetTransformInfo::getIntImmCost(IID, Imm, Ty);
841 case Intrinsic::sadd_with_overflow:
842 case Intrinsic::uadd_with_overflow:
843 case Intrinsic::ssub_with_overflow:
844 case Intrinsic::usub_with_overflow:
845 case Intrinsic::smul_with_overflow:
846 case Intrinsic::umul_with_overflow:
847 if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
850 return X86TTI::getIntImmCost(Imm, Ty);
851 case Intrinsic::experimental_stackmap:
852 case Intrinsic::experimental_patchpoint_void:
853 case Intrinsic::experimental_patchpoint_i64:
854 if (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))
857 return X86TTI::getIntImmCost(Imm, Ty);