1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
161 def X86vastart_save_xmm_regs :
162 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
163 SDT_X86VASTART_SAVE_XMM_REGS,
164 [SDNPHasChain, SDNPVariadic]>;
166 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
167 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
169 def X86callseq_start :
170 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
171 [SDNPHasChain, SDNPOutGlue]>;
173 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
177 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
180 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
181 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
182 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
186 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
187 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
188 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
189 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
190 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
191 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
193 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
194 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
196 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
197 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
199 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
205 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
206 SDTypeProfile<1, 1, [SDTCisInt<0>,
208 [SDNPHasChain, SDNPSideEffect]>;
209 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
210 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
211 [SDNPHasChain, SDNPSideEffect]>;
213 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
214 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
216 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
218 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
219 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
221 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
223 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
224 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
226 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
227 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
228 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
230 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
232 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
235 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
237 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
239 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
240 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
242 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
245 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
246 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
248 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
249 [SDNPHasChain, SDNPOutGlue]>;
251 //===----------------------------------------------------------------------===//
252 // X86 Operand Definitions.
255 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
256 // the index operand of an address, to conform to x86 encoding restrictions.
257 def ptr_rc_nosp : PointerLikeRegClass<1>;
259 // *mem - Operand definitions for the funky X86 addressing mode operands.
261 def X86MemAsmOperand : AsmOperandClass {
264 let RenderMethod = "addMemOperands" in {
265 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
266 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
267 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
268 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
269 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
270 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
271 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
272 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
273 // Gather mem operands
274 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
275 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
276 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
277 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
278 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
279 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
282 def X86AbsMemAsmOperand : AsmOperandClass {
284 let SuperClasses = [X86MemAsmOperand];
287 class X86MemOperand<string printMethod,
288 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
289 let PrintMethod = printMethod;
290 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
291 let ParserMatchClass = parserMatchClass;
292 let OperandType = "OPERAND_MEMORY";
295 // Gather mem operands
296 class X86VMemOperand<RegisterClass RC, string printMethod,
297 AsmOperandClass parserMatchClass>
298 : X86MemOperand<printMethod, parserMatchClass> {
299 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
302 def opaque32mem : X86MemOperand<"printopaquemem">;
303 def opaque48mem : X86MemOperand<"printopaquemem">;
304 def opaque80mem : X86MemOperand<"printopaquemem">;
305 def opaque512mem : X86MemOperand<"printopaquemem">;
307 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
308 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
309 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
310 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
311 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
312 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
313 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
314 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
315 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
316 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
317 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
318 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
319 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
321 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
323 // Gather mem operands
324 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
325 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
326 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
327 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
328 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
329 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
330 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
332 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
333 // plain GR64, so that it doesn't potentially require a REX prefix.
334 def i8mem_NOREX : Operand<i64> {
335 let PrintMethod = "printi8mem";
336 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
337 let ParserMatchClass = X86Mem8AsmOperand;
338 let OperandType = "OPERAND_MEMORY";
341 // GPRs available for tailcall.
342 // It represents GR32_TC, GR64_TC or GR64_TCW64.
343 def ptr_rc_tailcall : PointerLikeRegClass<2>;
345 // Special i32mem for addresses of load folding tail calls. These are not
346 // allowed to use callee-saved registers since they must be scheduled
347 // after callee-saved register are popped.
348 def i32mem_TC : Operand<i32> {
349 let PrintMethod = "printi32mem";
350 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
352 let ParserMatchClass = X86Mem32AsmOperand;
353 let OperandType = "OPERAND_MEMORY";
356 // Special i64mem for addresses of load folding tail calls. These are not
357 // allowed to use callee-saved registers since they must be scheduled
358 // after callee-saved register are popped.
359 def i64mem_TC : Operand<i64> {
360 let PrintMethod = "printi64mem";
361 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
362 ptr_rc_tailcall, i32imm, i8imm);
363 let ParserMatchClass = X86Mem64AsmOperand;
364 let OperandType = "OPERAND_MEMORY";
367 let OperandType = "OPERAND_PCREL",
368 ParserMatchClass = X86AbsMemAsmOperand,
369 PrintMethod = "printPCRelImm" in {
370 def i32imm_pcrel : Operand<i32>;
371 def i16imm_pcrel : Operand<i16>;
373 // Branch targets have OtherVT type and print as pc-relative values.
374 def brtarget : Operand<OtherVT>;
375 def brtarget8 : Operand<OtherVT>;
379 let RenderMethod = "addSrcIdxOperands" in {
380 def X86SrcIdx8Operand : AsmOperandClass {
381 let Name = "SrcIdx8";
382 let SuperClasses = [X86Mem8AsmOperand];
384 def X86SrcIdx16Operand : AsmOperandClass {
385 let Name = "SrcIdx16";
386 let SuperClasses = [X86Mem16AsmOperand];
388 def X86SrcIdx32Operand : AsmOperandClass {
389 let Name = "SrcIdx32";
390 let SuperClasses = [X86Mem32AsmOperand];
392 def X86SrcIdx64Operand : AsmOperandClass {
393 let Name = "SrcIdx64";
394 let SuperClasses = [X86Mem64AsmOperand];
396 } // RenderMethod = "addSrcIdxOperands"
398 let RenderMethod = "addDstIdxOperands" in {
399 def X86DstIdx8Operand : AsmOperandClass {
400 let Name = "DstIdx8";
401 let SuperClasses = [X86Mem8AsmOperand];
403 def X86DstIdx16Operand : AsmOperandClass {
404 let Name = "DstIdx16";
405 let SuperClasses = [X86Mem16AsmOperand];
407 def X86DstIdx32Operand : AsmOperandClass {
408 let Name = "DstIdx32";
409 let SuperClasses = [X86Mem32AsmOperand];
411 def X86DstIdx64Operand : AsmOperandClass {
412 let Name = "DstIdx64";
413 let SuperClasses = [X86Mem64AsmOperand];
415 } // RenderMethod = "addDstIdxOperands"
417 let RenderMethod = "addMemOffsOperands" in {
418 def X86MemOffs16_8AsmOperand : AsmOperandClass {
419 let Name = "MemOffs16_8";
420 let SuperClasses = [X86Mem8AsmOperand];
422 def X86MemOffs16_16AsmOperand : AsmOperandClass {
423 let Name = "MemOffs16_16";
424 let SuperClasses = [X86Mem16AsmOperand];
426 def X86MemOffs16_32AsmOperand : AsmOperandClass {
427 let Name = "MemOffs16_32";
428 let SuperClasses = [X86Mem32AsmOperand];
430 def X86MemOffs32_8AsmOperand : AsmOperandClass {
431 let Name = "MemOffs32_8";
432 let SuperClasses = [X86Mem8AsmOperand];
434 def X86MemOffs32_16AsmOperand : AsmOperandClass {
435 let Name = "MemOffs32_16";
436 let SuperClasses = [X86Mem16AsmOperand];
438 def X86MemOffs32_32AsmOperand : AsmOperandClass {
439 let Name = "MemOffs32_32";
440 let SuperClasses = [X86Mem32AsmOperand];
442 def X86MemOffs32_64AsmOperand : AsmOperandClass {
443 let Name = "MemOffs32_64";
444 let SuperClasses = [X86Mem64AsmOperand];
446 def X86MemOffs64_8AsmOperand : AsmOperandClass {
447 let Name = "MemOffs64_8";
448 let SuperClasses = [X86Mem8AsmOperand];
450 def X86MemOffs64_16AsmOperand : AsmOperandClass {
451 let Name = "MemOffs64_16";
452 let SuperClasses = [X86Mem16AsmOperand];
454 def X86MemOffs64_32AsmOperand : AsmOperandClass {
455 let Name = "MemOffs64_32";
456 let SuperClasses = [X86Mem32AsmOperand];
458 def X86MemOffs64_64AsmOperand : AsmOperandClass {
459 let Name = "MemOffs64_64";
460 let SuperClasses = [X86Mem64AsmOperand];
462 } // RenderMethod = "addMemOffsOperands"
464 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
465 : X86MemOperand<printMethod, parserMatchClass> {
466 let MIOperandInfo = (ops ptr_rc, i8imm);
469 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
470 : X86MemOperand<printMethod, parserMatchClass> {
471 let MIOperandInfo = (ops ptr_rc);
474 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
475 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
476 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
477 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
478 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
479 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
480 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
481 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
483 class X86MemOffsOperand<Operand immOperand, string printMethod,
484 AsmOperandClass parserMatchClass>
485 : X86MemOperand<printMethod, parserMatchClass> {
486 let MIOperandInfo = (ops immOperand, i8imm);
489 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
490 X86MemOffs16_8AsmOperand>;
491 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
492 X86MemOffs16_16AsmOperand>;
493 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
494 X86MemOffs16_32AsmOperand>;
495 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
496 X86MemOffs32_8AsmOperand>;
497 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
498 X86MemOffs32_16AsmOperand>;
499 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
500 X86MemOffs32_32AsmOperand>;
501 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
502 X86MemOffs32_64AsmOperand>;
503 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
504 X86MemOffs64_8AsmOperand>;
505 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
506 X86MemOffs64_16AsmOperand>;
507 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
508 X86MemOffs64_32AsmOperand>;
509 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
510 X86MemOffs64_64AsmOperand>;
512 def SSECC : Operand<i8> {
513 let PrintMethod = "printSSECC";
514 let OperandType = "OPERAND_IMMEDIATE";
517 def i8immZExt3 : ImmLeaf<i8, [{
518 return Imm >= 0 && Imm < 8;
521 def AVXCC : Operand<i8> {
522 let PrintMethod = "printAVXCC";
523 let OperandType = "OPERAND_IMMEDIATE";
526 def i8immZExt5 : ImmLeaf<i8, [{
527 return Imm >= 0 && Imm < 32;
529 // AVX-512 uses a 32-bit immediate in their intrinsics
530 def i32immZExt5 : ImmLeaf<i32, [{
531 return Imm >= 0 && Imm < 32;
534 class ImmSExtAsmOperandClass : AsmOperandClass {
535 let SuperClasses = [ImmAsmOperand];
536 let RenderMethod = "addImmOperands";
539 def X86GR32orGR64AsmOperand : AsmOperandClass {
540 let Name = "GR32orGR64";
543 def GR32orGR64 : RegisterOperand<GR32> {
544 let ParserMatchClass = X86GR32orGR64AsmOperand;
547 def AVX512RC : Operand<i32> {
548 let PrintMethod = "printRoundingControl";
549 let OperandType = "OPERAND_IMMEDIATE";
552 // Sign-extended immediate classes. We don't need to define the full lattice
553 // here because there is no instruction with an ambiguity between ImmSExti64i32
556 // The strange ranges come from the fact that the assembler always works with
557 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
558 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
561 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
562 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
563 let Name = "ImmSExti64i32";
566 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
567 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
568 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
569 let Name = "ImmSExti16i8";
570 let SuperClasses = [ImmSExti64i32AsmOperand];
573 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
574 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
575 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
576 let Name = "ImmSExti32i8";
580 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
581 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
582 let Name = "ImmSExti64i8";
583 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
584 ImmSExti64i32AsmOperand];
587 // A couple of more descriptive operand definitions.
588 // 16-bits but only 8 bits are significant.
589 def i16i8imm : Operand<i16> {
590 let ParserMatchClass = ImmSExti16i8AsmOperand;
591 let OperandType = "OPERAND_IMMEDIATE";
593 // 32-bits but only 8 bits are significant.
594 def i32i8imm : Operand<i32> {
595 let ParserMatchClass = ImmSExti32i8AsmOperand;
596 let OperandType = "OPERAND_IMMEDIATE";
599 // 64-bits but only 32 bits are significant.
600 def i64i32imm : Operand<i64> {
601 let ParserMatchClass = ImmSExti64i32AsmOperand;
602 let OperandType = "OPERAND_IMMEDIATE";
605 // 64-bits but only 32 bits are significant, and those bits are treated as being
607 def i64i32imm_pcrel : Operand<i64> {
608 let PrintMethod = "printPCRelImm";
609 let ParserMatchClass = X86AbsMemAsmOperand;
610 let OperandType = "OPERAND_PCREL";
613 // 64-bits but only 8 bits are significant.
614 def i64i8imm : Operand<i64> {
615 let ParserMatchClass = ImmSExti64i8AsmOperand;
616 let OperandType = "OPERAND_IMMEDIATE";
619 def lea64_32mem : Operand<i32> {
620 let PrintMethod = "printi32mem";
621 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
622 let ParserMatchClass = X86MemAsmOperand;
625 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
626 def lea64mem : Operand<i64> {
627 let PrintMethod = "printi64mem";
628 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
629 let ParserMatchClass = X86MemAsmOperand;
633 //===----------------------------------------------------------------------===//
634 // X86 Complex Pattern Definitions.
637 // Define X86 specific addressing mode.
638 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
639 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
640 [add, sub, mul, X86mul_imm, shl, or, frameindex],
642 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
643 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
644 [add, sub, mul, X86mul_imm, shl, or,
645 frameindex, X86WrapperRIP],
648 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
649 [tglobaltlsaddr], []>;
651 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
652 [tglobaltlsaddr], []>;
654 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
655 [add, sub, mul, X86mul_imm, shl, or, frameindex,
658 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
659 [tglobaltlsaddr], []>;
661 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
662 [tglobaltlsaddr], []>;
664 //===----------------------------------------------------------------------===//
665 // X86 Instruction Predicate Definitions.
666 def HasCMov : Predicate<"Subtarget->hasCMov()">;
667 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
669 def HasMMX : Predicate<"Subtarget->hasMMX()">;
670 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
671 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
672 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
673 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
674 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
675 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
676 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
677 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
678 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
679 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
680 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
681 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
682 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
683 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
684 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
685 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
686 def HasAVX : Predicate<"Subtarget->hasAVX()">;
687 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
688 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
689 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
690 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
691 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
692 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
693 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
694 def HasCDI : Predicate<"Subtarget->hasCDI()">;
695 def HasPFI : Predicate<"Subtarget->hasPFI()">;
696 def HasERI : Predicate<"Subtarget->hasERI()">;
697 def HasDQI : Predicate<"Subtarget->hasDQI()">;
698 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
699 def HasBWI : Predicate<"Subtarget->hasBWI()">;
700 def HasVLX : Predicate<"Subtarget->hasVLX()">,
701 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
702 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
704 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
705 def HasAES : Predicate<"Subtarget->hasAES()">;
706 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
707 def HasFMA : Predicate<"Subtarget->hasFMA()">;
708 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
709 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
710 def HasXOP : Predicate<"Subtarget->hasXOP()">;
711 def HasTBM : Predicate<"Subtarget->hasTBM()">;
712 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
713 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
714 def HasF16C : Predicate<"Subtarget->hasF16C()">;
715 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
716 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
717 def HasBMI : Predicate<"Subtarget->hasBMI()">;
718 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
719 def HasRTM : Predicate<"Subtarget->hasRTM()">;
720 def HasHLE : Predicate<"Subtarget->hasHLE()">;
721 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
722 def HasADX : Predicate<"Subtarget->hasADX()">;
723 def HasSHA : Predicate<"Subtarget->hasSHA()">;
724 def HasSGX : Predicate<"Subtarget->hasSGX()">;
725 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
726 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
727 def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
728 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
729 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
730 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
731 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
732 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
733 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
734 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
735 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
736 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
737 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
738 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
739 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
740 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
741 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
742 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
743 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
744 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
745 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
746 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
747 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
748 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
749 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
750 "TM.getCodeModel() != CodeModel::Kernel">;
751 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
752 "TM.getCodeModel() == CodeModel::Kernel">;
753 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
754 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
755 def OptForSize : Predicate<"OptForSize">;
756 def OptForSpeed : Predicate<"!OptForSize">;
757 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
758 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
759 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
760 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
761 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
763 //===----------------------------------------------------------------------===//
764 // X86 Instruction Format Definitions.
767 include "X86InstrFormats.td"
769 //===----------------------------------------------------------------------===//
770 // Pattern fragments.
773 // X86 specific condition code. These correspond to CondCode in
774 // X86InstrInfo.h. They must be kept in synch.
775 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
776 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
777 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
778 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
779 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
780 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
781 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
782 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
783 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
784 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
785 def X86_COND_NO : PatLeaf<(i8 10)>;
786 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
787 def X86_COND_NS : PatLeaf<(i8 12)>;
788 def X86_COND_O : PatLeaf<(i8 13)>;
789 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
790 def X86_COND_S : PatLeaf<(i8 15)>;
792 // Predicate used to help when pattern matching LZCNT/TZCNT.
793 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
794 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
797 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
798 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
799 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
800 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
803 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
806 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
808 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
810 def i64immZExt32SExt8 : ImmLeaf<i64, [{
811 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
814 // Helper fragments for loads.
815 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
816 // known to be 32-bit aligned or better. Ditto for i8 to i16.
817 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
818 LoadSDNode *LD = cast<LoadSDNode>(N);
819 ISD::LoadExtType ExtType = LD->getExtensionType();
820 if (ExtType == ISD::NON_EXTLOAD)
822 if (ExtType == ISD::EXTLOAD)
823 return LD->getAlignment() >= 2 && !LD->isVolatile();
827 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
828 LoadSDNode *LD = cast<LoadSDNode>(N);
829 ISD::LoadExtType ExtType = LD->getExtensionType();
830 if (ExtType == ISD::EXTLOAD)
831 return LD->getAlignment() >= 2 && !LD->isVolatile();
835 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
836 LoadSDNode *LD = cast<LoadSDNode>(N);
837 ISD::LoadExtType ExtType = LD->getExtensionType();
838 if (ExtType == ISD::NON_EXTLOAD)
840 if (ExtType == ISD::EXTLOAD)
841 return LD->getAlignment() >= 4 && !LD->isVolatile();
845 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
846 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
847 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
848 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
849 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
851 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
852 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
853 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
854 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
855 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
856 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
858 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
859 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
860 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
861 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
862 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
863 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
864 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
865 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
866 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
867 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
869 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
870 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
871 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
872 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
873 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
874 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
875 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
876 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
877 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
878 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
881 // An 'and' node with a single use.
882 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
883 return N->hasOneUse();
885 // An 'srl' node with a single use.
886 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
887 return N->hasOneUse();
889 // An 'trunc' node with a single use.
890 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
891 return N->hasOneUse();
894 //===----------------------------------------------------------------------===//
899 let hasSideEffects = 0, SchedRW = [WriteZero] in {
900 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
901 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
902 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
903 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
904 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
908 // Constructing a stack frame.
909 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
910 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
912 let SchedRW = [WriteALU] in {
913 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
914 def LEAVE : I<0xC9, RawFrm,
915 (outs), (ins), "leave", [], IIC_LEAVE>,
916 Requires<[Not64BitMode]>;
918 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
919 def LEAVE64 : I<0xC9, RawFrm,
920 (outs), (ins), "leave", [], IIC_LEAVE>,
921 Requires<[In64BitMode]>;
924 //===----------------------------------------------------------------------===//
925 // Miscellaneous Instructions.
928 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
929 let mayLoad = 1, SchedRW = [WriteLoad] in {
930 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
931 IIC_POP_REG16>, OpSize16;
932 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
933 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
934 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
935 IIC_POP_REG>, OpSize16;
936 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
937 IIC_POP_MEM>, OpSize16;
938 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
939 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
940 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
941 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
942 } // mayLoad, SchedRW
944 let mayStore = 1, SchedRW = [WriteStore] in {
945 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
946 IIC_PUSH_REG>, OpSize16;
947 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
948 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
949 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
950 IIC_PUSH_REG>, OpSize16;
951 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
952 IIC_PUSH_MEM>, OpSize16;
953 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
954 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
955 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
956 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
958 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
959 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
960 Requires<[Not64BitMode]>;
961 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
962 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
963 Requires<[Not64BitMode]>;
964 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
965 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
966 Requires<[Not64BitMode]>;
967 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
968 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
969 Requires<[Not64BitMode]>;
970 } // mayStore, SchedRW
973 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
974 SchedRW = [WriteLoad] in {
975 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
977 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
978 OpSize32, Requires<[Not64BitMode]>;
981 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
982 SchedRW = [WriteStore] in {
983 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
985 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
986 OpSize32, Requires<[Not64BitMode]>;
989 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
990 let mayLoad = 1, SchedRW = [WriteLoad] in {
991 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
992 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
993 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
994 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
995 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
996 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
997 } // mayLoad, SchedRW
998 let mayStore = 1, SchedRW = [WriteStore] in {
999 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1000 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1001 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1002 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1003 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1004 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1005 } // mayStore, SchedRW
1008 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1009 SchedRW = [WriteStore] in {
1010 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1011 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1012 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1013 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1014 Requires<[In64BitMode]>;
1015 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1016 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1017 Requires<[In64BitMode]>;
1020 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1021 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1022 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1023 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1024 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1025 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1027 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1028 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1029 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1030 OpSize32, Requires<[Not64BitMode]>;
1031 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1032 OpSize16, Requires<[Not64BitMode]>;
1034 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1035 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1036 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1037 OpSize32, Requires<[Not64BitMode]>;
1038 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1039 OpSize16, Requires<[Not64BitMode]>;
1042 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1043 // GR32 = bswap GR32
1044 def BSWAP32r : I<0xC8, AddRegFrm,
1045 (outs GR32:$dst), (ins GR32:$src),
1047 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1049 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1051 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1052 } // Constraints = "$src = $dst", SchedRW
1054 // Bit scan instructions.
1055 let Defs = [EFLAGS] in {
1056 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1057 "bsf{w}\t{$src, $dst|$dst, $src}",
1058 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1059 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1060 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1061 "bsf{w}\t{$src, $dst|$dst, $src}",
1062 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1063 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1064 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1065 "bsf{l}\t{$src, $dst|$dst, $src}",
1066 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1067 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1068 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1069 "bsf{l}\t{$src, $dst|$dst, $src}",
1070 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1071 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1072 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1073 "bsf{q}\t{$src, $dst|$dst, $src}",
1074 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1075 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1076 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1077 "bsf{q}\t{$src, $dst|$dst, $src}",
1078 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1079 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1081 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1082 "bsr{w}\t{$src, $dst|$dst, $src}",
1083 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1084 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1085 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1086 "bsr{w}\t{$src, $dst|$dst, $src}",
1087 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1088 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1089 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1090 "bsr{l}\t{$src, $dst|$dst, $src}",
1091 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1092 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1093 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1094 "bsr{l}\t{$src, $dst|$dst, $src}",
1095 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1096 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1097 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1098 "bsr{q}\t{$src, $dst|$dst, $src}",
1099 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1100 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1101 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1102 "bsr{q}\t{$src, $dst|$dst, $src}",
1103 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1104 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1105 } // Defs = [EFLAGS]
1107 let SchedRW = [WriteMicrocoded] in {
1108 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1109 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1110 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1111 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1112 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1113 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1114 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1115 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1116 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1117 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1120 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1121 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1122 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1123 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1124 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1125 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1126 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1127 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1128 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1129 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1130 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1131 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1132 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1134 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1135 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1136 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1137 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1138 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1139 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1140 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1141 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1142 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1143 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1144 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1145 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1146 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1148 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1149 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1150 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1151 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1152 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1153 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1154 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1155 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1156 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1157 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1161 //===----------------------------------------------------------------------===//
1162 // Move Instructions.
1164 let SchedRW = [WriteMove] in {
1165 let hasSideEffects = 0 in {
1166 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1167 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1168 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1169 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1170 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1171 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1172 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1173 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1176 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1177 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1178 "mov{b}\t{$src, $dst|$dst, $src}",
1179 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1180 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1181 "mov{w}\t{$src, $dst|$dst, $src}",
1182 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1183 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1184 "mov{l}\t{$src, $dst|$dst, $src}",
1185 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1186 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1187 "mov{q}\t{$src, $dst|$dst, $src}",
1188 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1190 let isReMaterializable = 1 in {
1191 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1192 "movabs{q}\t{$src, $dst|$dst, $src}",
1193 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1196 // Longer forms that use a ModR/M byte. Needed for disassembler
1197 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1198 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1199 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1200 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1201 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1202 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1203 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1207 let SchedRW = [WriteStore] in {
1208 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1209 "mov{b}\t{$src, $dst|$dst, $src}",
1210 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1211 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1212 "mov{w}\t{$src, $dst|$dst, $src}",
1213 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1214 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1215 "mov{l}\t{$src, $dst|$dst, $src}",
1216 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1217 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1218 "mov{q}\t{$src, $dst|$dst, $src}",
1219 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1222 let hasSideEffects = 0 in {
1224 /// Memory offset versions of moves. The immediate is an address mode sized
1225 /// offset from the segment base.
1226 let SchedRW = [WriteALU] in {
1227 let mayLoad = 1 in {
1229 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1230 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1233 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1234 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1237 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1238 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1241 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1242 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1246 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1247 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1249 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1250 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1253 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1254 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1257 let mayStore = 1 in {
1259 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1260 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1262 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1263 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1266 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1267 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1270 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1271 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1275 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1276 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1278 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1279 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1282 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1283 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1288 // These forms all have full 64-bit absolute addresses in their instructions
1289 // and use the movabs mnemonic to indicate this specific form.
1290 let mayLoad = 1 in {
1292 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1293 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1295 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1296 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1298 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1299 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1302 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1303 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1306 let mayStore = 1 in {
1308 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1309 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1311 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1312 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1314 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1315 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1318 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1319 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1321 } // hasSideEffects = 0
1323 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1324 SchedRW = [WriteMove] in {
1325 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1326 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1327 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1328 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1329 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1330 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1331 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1332 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1335 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1336 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1337 "mov{b}\t{$src, $dst|$dst, $src}",
1338 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1339 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1340 "mov{w}\t{$src, $dst|$dst, $src}",
1341 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1342 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1343 "mov{l}\t{$src, $dst|$dst, $src}",
1344 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1345 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1346 "mov{q}\t{$src, $dst|$dst, $src}",
1347 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1350 let SchedRW = [WriteStore] in {
1351 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1352 "mov{b}\t{$src, $dst|$dst, $src}",
1353 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1354 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1355 "mov{w}\t{$src, $dst|$dst, $src}",
1356 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1357 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1358 "mov{l}\t{$src, $dst|$dst, $src}",
1359 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1360 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1361 "mov{q}\t{$src, $dst|$dst, $src}",
1362 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1365 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1366 // that they can be used for copying and storing h registers, which can't be
1367 // encoded when a REX prefix is present.
1368 let isCodeGenOnly = 1 in {
1369 let hasSideEffects = 0 in
1370 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1371 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1372 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1374 let mayStore = 1, hasSideEffects = 0 in
1375 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1376 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1377 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1378 IIC_MOV_MEM>, Sched<[WriteStore]>;
1379 let mayLoad = 1, hasSideEffects = 0,
1380 canFoldAsLoad = 1, isReMaterializable = 1 in
1381 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1382 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1383 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1384 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1388 // Condition code ops, incl. set if equal/not equal/...
1389 let SchedRW = [WriteALU] in {
1390 let Defs = [EFLAGS], Uses = [AH] in
1391 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1392 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1393 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1394 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1395 IIC_AHF>; // AH = flags
1398 //===----------------------------------------------------------------------===//
1399 // Bit tests instructions: BT, BTS, BTR, BTC.
1401 let Defs = [EFLAGS] in {
1402 let SchedRW = [WriteALU] in {
1403 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1404 "bt{w}\t{$src2, $src1|$src1, $src2}",
1405 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1407 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1408 "bt{l}\t{$src2, $src1|$src1, $src2}",
1409 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1411 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1412 "bt{q}\t{$src2, $src1|$src1, $src2}",
1413 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1416 // Unlike with the register+register form, the memory+register form of the
1417 // bt instruction does not ignore the high bits of the index. From ISel's
1418 // perspective, this is pretty bizarre. Make these instructions disassembly
1421 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1422 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1423 "bt{w}\t{$src2, $src1|$src1, $src2}",
1424 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1425 // (implicit EFLAGS)]
1427 >, OpSize16, TB, Requires<[FastBTMem]>;
1428 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1429 "bt{l}\t{$src2, $src1|$src1, $src2}",
1430 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1431 // (implicit EFLAGS)]
1433 >, OpSize32, TB, Requires<[FastBTMem]>;
1434 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1435 "bt{q}\t{$src2, $src1|$src1, $src2}",
1436 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1437 // (implicit EFLAGS)]
1442 let SchedRW = [WriteALU] in {
1443 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1444 "bt{w}\t{$src2, $src1|$src1, $src2}",
1445 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1446 IIC_BT_RI>, OpSize16, TB;
1447 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1448 "bt{l}\t{$src2, $src1|$src1, $src2}",
1449 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1450 IIC_BT_RI>, OpSize32, TB;
1451 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1452 "bt{q}\t{$src2, $src1|$src1, $src2}",
1453 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1457 // Note that these instructions don't need FastBTMem because that
1458 // only applies when the other operand is in a register. When it's
1459 // an immediate, bt is still fast.
1460 let SchedRW = [WriteALU] in {
1461 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1462 "bt{w}\t{$src2, $src1|$src1, $src2}",
1463 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1464 ], IIC_BT_MI>, OpSize16, TB;
1465 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1466 "bt{l}\t{$src2, $src1|$src1, $src2}",
1467 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1468 ], IIC_BT_MI>, OpSize32, TB;
1469 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1470 "bt{q}\t{$src2, $src1|$src1, $src2}",
1471 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1472 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1475 let hasSideEffects = 0 in {
1476 let SchedRW = [WriteALU] in {
1477 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1478 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1480 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1481 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1483 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1484 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1487 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1488 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1489 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1491 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1492 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1494 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1495 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1498 let SchedRW = [WriteALU] in {
1499 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1500 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1502 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1503 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1505 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1506 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1509 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1510 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1511 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1513 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1514 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1516 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1517 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1520 let SchedRW = [WriteALU] in {
1521 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1522 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1524 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1525 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1527 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1528 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1531 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1532 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1533 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1535 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1536 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1538 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1539 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1542 let SchedRW = [WriteALU] in {
1543 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1544 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1546 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1547 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1549 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1550 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1553 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1554 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1555 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1557 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1558 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1560 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1561 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1564 let SchedRW = [WriteALU] in {
1565 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1566 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1568 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1569 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1571 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1572 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1575 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1576 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1577 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1579 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1580 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1582 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1583 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1586 let SchedRW = [WriteALU] in {
1587 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1588 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1590 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1591 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1593 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1594 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1597 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1598 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1599 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1601 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1602 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1604 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1605 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1607 } // hasSideEffects = 0
1608 } // Defs = [EFLAGS]
1611 //===----------------------------------------------------------------------===//
1615 // Atomic swap. These are just normal xchg instructions. But since a memory
1616 // operand is referenced, the atomicity is ensured.
1617 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1618 InstrItinClass itin> {
1619 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1620 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1621 (ins GR8:$val, i8mem:$ptr),
1622 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1625 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1627 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1628 (ins GR16:$val, i16mem:$ptr),
1629 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1632 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1634 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1635 (ins GR32:$val, i32mem:$ptr),
1636 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1639 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1641 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1642 (ins GR64:$val, i64mem:$ptr),
1643 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1646 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1651 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1653 // Swap between registers.
1654 let SchedRW = [WriteALU] in {
1655 let Constraints = "$val = $dst" in {
1656 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1657 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1658 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1659 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1661 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1662 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1664 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1665 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1668 // Swap between EAX and other registers.
1669 let Uses = [AX], Defs = [AX] in
1670 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1671 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1672 let Uses = [EAX], Defs = [EAX] in
1673 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1674 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1675 OpSize32, Requires<[Not64BitMode]>;
1676 let Uses = [EAX], Defs = [EAX] in
1677 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1678 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1679 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1680 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1681 OpSize32, Requires<[In64BitMode]>;
1682 let Uses = [RAX], Defs = [RAX] in
1683 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1684 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1687 let SchedRW = [WriteALU] in {
1688 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1689 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1690 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1691 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1693 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1694 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1696 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1697 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1700 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1701 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1702 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1703 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1704 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1706 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1707 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1709 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1710 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1714 let SchedRW = [WriteALU] in {
1715 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1716 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1717 IIC_CMPXCHG_REG8>, TB;
1718 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1719 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1720 IIC_CMPXCHG_REG>, TB, OpSize16;
1721 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1722 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1723 IIC_CMPXCHG_REG>, TB, OpSize32;
1724 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1725 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1726 IIC_CMPXCHG_REG>, TB;
1729 let SchedRW = [WriteALULd, WriteRMW] in {
1730 let mayLoad = 1, mayStore = 1 in {
1731 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1732 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1733 IIC_CMPXCHG_MEM8>, TB;
1734 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1735 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1736 IIC_CMPXCHG_MEM>, TB, OpSize16;
1737 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1738 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1739 IIC_CMPXCHG_MEM>, TB, OpSize32;
1740 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1741 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1742 IIC_CMPXCHG_MEM>, TB;
1745 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1746 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1747 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1749 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1750 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1751 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1752 TB, Requires<[HasCmpxchg16b]>;
1756 // Lock instruction prefix
1757 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1759 // Rex64 instruction prefix
1760 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1761 Requires<[In64BitMode]>;
1763 // Data16 instruction prefix
1764 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1766 // Repeat string operation instruction prefixes
1767 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1768 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1769 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1770 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1771 // Repeat while not equal (used with CMPS and SCAS)
1772 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1776 // String manipulation instructions
1777 let SchedRW = [WriteMicrocoded] in {
1778 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1779 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1780 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1781 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1782 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1783 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1784 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1785 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1786 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1787 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1788 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1789 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1790 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1793 let SchedRW = [WriteSystem] in {
1794 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1795 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1796 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1797 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1798 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1799 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1800 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1801 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1804 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1805 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1806 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1807 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1808 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1809 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1810 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1811 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1815 // Flag instructions
1816 let SchedRW = [WriteALU] in {
1817 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1818 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1819 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1820 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1821 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1822 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1823 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1825 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1828 // Table lookup instructions
1829 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1832 let SchedRW = [WriteMicrocoded] in {
1833 // ASCII Adjust After Addition
1834 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1835 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1836 Requires<[Not64BitMode]>;
1838 // ASCII Adjust AX Before Division
1839 // sets AL, AH and EFLAGS and uses AL and AH
1840 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1841 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1843 // ASCII Adjust AX After Multiply
1844 // sets AL, AH and EFLAGS and uses AL
1845 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1846 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1848 // ASCII Adjust AL After Subtraction - sets
1849 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1850 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1851 Requires<[Not64BitMode]>;
1853 // Decimal Adjust AL after Addition
1854 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1855 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1856 Requires<[Not64BitMode]>;
1858 // Decimal Adjust AL after Subtraction
1859 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1860 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1861 Requires<[Not64BitMode]>;
1864 let SchedRW = [WriteSystem] in {
1865 // Check Array Index Against Bounds
1866 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1867 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1868 Requires<[Not64BitMode]>;
1869 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1870 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1871 Requires<[Not64BitMode]>;
1873 // Adjust RPL Field of Segment Selector
1874 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1875 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1876 Requires<[Not64BitMode]>;
1877 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1878 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1879 Requires<[Not64BitMode]>;
1882 //===----------------------------------------------------------------------===//
1883 // MOVBE Instructions
1885 let Predicates = [HasMOVBE] in {
1886 let SchedRW = [WriteALULd] in {
1887 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1888 "movbe{w}\t{$src, $dst|$dst, $src}",
1889 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1891 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1892 "movbe{l}\t{$src, $dst|$dst, $src}",
1893 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1895 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1896 "movbe{q}\t{$src, $dst|$dst, $src}",
1897 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1900 let SchedRW = [WriteStore] in {
1901 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1902 "movbe{w}\t{$src, $dst|$dst, $src}",
1903 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1905 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1906 "movbe{l}\t{$src, $dst|$dst, $src}",
1907 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1909 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1910 "movbe{q}\t{$src, $dst|$dst, $src}",
1911 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1916 //===----------------------------------------------------------------------===//
1917 // RDRAND Instruction
1919 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1920 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1922 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1923 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1925 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1926 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1928 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1931 //===----------------------------------------------------------------------===//
1932 // RDSEED Instruction
1934 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1935 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1937 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1938 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1940 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1941 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1943 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1946 //===----------------------------------------------------------------------===//
1947 // LZCNT Instruction
1949 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1950 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1951 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1952 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1954 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1955 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1956 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1957 (implicit EFLAGS)]>, XS, OpSize16;
1959 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1960 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1961 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1963 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1964 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1965 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1966 (implicit EFLAGS)]>, XS, OpSize32;
1968 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1969 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1970 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1972 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1973 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1974 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1975 (implicit EFLAGS)]>, XS;
1978 let Predicates = [HasLZCNT] in {
1979 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
1980 (X86cmp GR16:$src, (i16 0))),
1981 (LZCNT16rr GR16:$src)>;
1982 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
1983 (X86cmp GR32:$src, (i32 0))),
1984 (LZCNT32rr GR32:$src)>;
1985 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
1986 (X86cmp GR64:$src, (i64 0))),
1987 (LZCNT64rr GR64:$src)>;
1988 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
1989 (X86cmp GR16:$src, (i16 0))),
1990 (LZCNT16rr GR16:$src)>;
1991 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
1992 (X86cmp GR32:$src, (i32 0))),
1993 (LZCNT32rr GR32:$src)>;
1994 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
1995 (X86cmp GR64:$src, (i64 0))),
1996 (LZCNT64rr GR64:$src)>;
1998 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
1999 (X86cmp (loadi16 addr:$src), (i16 0))),
2000 (LZCNT16rm addr:$src)>;
2001 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2002 (X86cmp (loadi32 addr:$src), (i32 0))),
2003 (LZCNT32rm addr:$src)>;
2004 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2005 (X86cmp (loadi64 addr:$src), (i64 0))),
2006 (LZCNT64rm addr:$src)>;
2007 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2008 (X86cmp (loadi16 addr:$src), (i16 0))),
2009 (LZCNT16rm addr:$src)>;
2010 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2011 (X86cmp (loadi32 addr:$src), (i32 0))),
2012 (LZCNT32rm addr:$src)>;
2013 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2014 (X86cmp (loadi64 addr:$src), (i64 0))),
2015 (LZCNT64rm addr:$src)>;
2018 //===----------------------------------------------------------------------===//
2021 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2022 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2023 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2024 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2026 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2027 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2028 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2029 (implicit EFLAGS)]>, XS, OpSize16;
2031 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2032 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2033 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2035 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2036 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2037 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2038 (implicit EFLAGS)]>, XS, OpSize32;
2040 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2041 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2042 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2044 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2045 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2046 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2047 (implicit EFLAGS)]>, XS;
2050 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2051 RegisterClass RC, X86MemOperand x86memop> {
2052 let hasSideEffects = 0 in {
2053 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2054 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2057 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2058 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2063 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2064 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2065 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2066 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2067 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2068 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2069 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2072 //===----------------------------------------------------------------------===//
2073 // Pattern fragments to auto generate BMI instructions.
2074 //===----------------------------------------------------------------------===//
2076 let Predicates = [HasBMI] in {
2077 // FIXME: patterns for the load versions are not implemented
2078 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2079 (BLSR32rr GR32:$src)>;
2080 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2081 (BLSR64rr GR64:$src)>;
2083 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2084 (BLSMSK32rr GR32:$src)>;
2085 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2086 (BLSMSK64rr GR64:$src)>;
2088 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2089 (BLSI32rr GR32:$src)>;
2090 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2091 (BLSI64rr GR64:$src)>;
2094 let Predicates = [HasBMI] in {
2095 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2096 (X86cmp GR16:$src, (i16 0))),
2097 (TZCNT16rr GR16:$src)>;
2098 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2099 (X86cmp GR32:$src, (i32 0))),
2100 (TZCNT32rr GR32:$src)>;
2101 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2102 (X86cmp GR64:$src, (i64 0))),
2103 (TZCNT64rr GR64:$src)>;
2104 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2105 (X86cmp GR16:$src, (i16 0))),
2106 (TZCNT16rr GR16:$src)>;
2107 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2108 (X86cmp GR32:$src, (i32 0))),
2109 (TZCNT32rr GR32:$src)>;
2110 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2111 (X86cmp GR64:$src, (i64 0))),
2112 (TZCNT64rr GR64:$src)>;
2114 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2115 (X86cmp (loadi16 addr:$src), (i16 0))),
2116 (TZCNT16rm addr:$src)>;
2117 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2118 (X86cmp (loadi32 addr:$src), (i32 0))),
2119 (TZCNT32rm addr:$src)>;
2120 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2121 (X86cmp (loadi64 addr:$src), (i64 0))),
2122 (TZCNT64rm addr:$src)>;
2123 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2124 (X86cmp (loadi16 addr:$src), (i16 0))),
2125 (TZCNT16rm addr:$src)>;
2126 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2127 (X86cmp (loadi32 addr:$src), (i32 0))),
2128 (TZCNT32rm addr:$src)>;
2129 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2130 (X86cmp (loadi64 addr:$src), (i64 0))),
2131 (TZCNT64rm addr:$src)>;
2135 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2136 X86MemOperand x86memop, Intrinsic Int,
2138 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2139 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2140 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2142 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2143 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2144 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2145 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2148 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2149 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2150 int_x86_bmi_bextr_32, loadi32>;
2151 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2152 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2155 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2156 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2157 int_x86_bmi_bzhi_32, loadi32>;
2158 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2159 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2163 def CountTrailingOnes : SDNodeXForm<imm, [{
2164 // Count the trailing ones in the immediate.
2165 return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
2168 def BZHIMask : ImmLeaf<i64, [{
2169 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
2172 let Predicates = [HasBMI2] in {
2173 def : Pat<(and GR64:$src, BZHIMask:$mask),
2174 (BZHI64rr GR64:$src,
2175 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2176 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2178 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2179 (BZHI32rr GR32:$src,
2180 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2182 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2183 (BZHI32rm addr:$src,
2184 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2186 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2187 (BZHI64rr GR64:$src,
2188 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2190 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2191 (BZHI64rm addr:$src,
2192 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2195 let Predicates = [HasBMI] in {
2196 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2197 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2198 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2199 (BEXTR32rm addr:$src1, GR32:$src2)>;
2200 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2201 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2202 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2203 (BEXTR64rm addr:$src1, GR64:$src2)>;
2206 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2207 X86MemOperand x86memop, Intrinsic Int,
2209 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2210 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2211 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2213 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2214 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2215 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2218 let Predicates = [HasBMI2] in {
2219 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2220 int_x86_bmi_pdep_32, loadi32>, T8XD;
2221 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2222 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2223 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2224 int_x86_bmi_pext_32, loadi32>, T8XS;
2225 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2226 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2229 //===----------------------------------------------------------------------===//
2232 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2234 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2235 X86MemOperand x86memop, PatFrag ld_frag,
2236 Intrinsic Int, Operand immtype,
2237 SDPatternOperator immoperator> {
2238 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2239 !strconcat(OpcodeStr,
2240 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2241 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2243 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2244 (ins x86memop:$src1, immtype:$cntl),
2245 !strconcat(OpcodeStr,
2246 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2247 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2251 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2252 int_x86_tbm_bextri_u32, i32imm, imm>;
2253 let ImmT = Imm32S in
2254 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2255 int_x86_tbm_bextri_u64, i64i32imm,
2256 i64immSExt32>, VEX_W;
2258 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2259 RegisterClass RC, string OpcodeStr,
2260 X86MemOperand x86memop, PatFrag ld_frag> {
2261 let hasSideEffects = 0 in {
2262 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2263 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2266 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2267 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2272 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2273 Format FormReg, Format FormMem> {
2274 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2276 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2280 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2281 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2282 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2283 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2284 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2285 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2286 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2287 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2288 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2291 //===----------------------------------------------------------------------===//
2292 // Pattern fragments to auto generate TBM instructions.
2293 //===----------------------------------------------------------------------===//
2295 let Predicates = [HasTBM] in {
2296 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2297 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2298 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2299 (BEXTRI32mi addr:$src1, imm:$src2)>;
2300 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2301 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2302 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2303 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2305 // FIXME: patterns for the load versions are not implemented
2306 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2307 (BLCFILL32rr GR32:$src)>;
2308 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2309 (BLCFILL64rr GR64:$src)>;
2311 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2312 (BLCI32rr GR32:$src)>;
2313 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2314 (BLCI64rr GR64:$src)>;
2316 // Extra patterns because opt can optimize the above patterns to this.
2317 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2318 (BLCI32rr GR32:$src)>;
2319 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2320 (BLCI64rr GR64:$src)>;
2322 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2323 (BLCIC32rr GR32:$src)>;
2324 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2325 (BLCIC64rr GR64:$src)>;
2327 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2328 (BLCMSK32rr GR32:$src)>;
2329 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2330 (BLCMSK64rr GR64:$src)>;
2332 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2333 (BLCS32rr GR32:$src)>;
2334 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2335 (BLCS64rr GR64:$src)>;
2337 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2338 (BLSFILL32rr GR32:$src)>;
2339 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2340 (BLSFILL64rr GR64:$src)>;
2342 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2343 (BLSIC32rr GR32:$src)>;
2344 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2345 (BLSIC64rr GR64:$src)>;
2347 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2348 (T1MSKC32rr GR32:$src)>;
2349 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2350 (T1MSKC64rr GR64:$src)>;
2352 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2353 (TZMSK32rr GR32:$src)>;
2354 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2355 (TZMSK64rr GR64:$src)>;
2358 //===----------------------------------------------------------------------===//
2360 //===----------------------------------------------------------------------===//
2362 include "X86InstrArithmetic.td"
2363 include "X86InstrCMovSetCC.td"
2364 include "X86InstrExtension.td"
2365 include "X86InstrControl.td"
2366 include "X86InstrShiftRotate.td"
2368 // X87 Floating Point Stack.
2369 include "X86InstrFPStack.td"
2371 // SIMD support (SSE, MMX and AVX)
2372 include "X86InstrFragmentsSIMD.td"
2374 // FMA - Fused Multiply-Add support (requires FMA)
2375 include "X86InstrFMA.td"
2378 include "X86InstrXOP.td"
2380 // SSE, MMX and 3DNow! vector support.
2381 include "X86InstrSSE.td"
2382 include "X86InstrAVX512.td"
2383 include "X86InstrMMX.td"
2384 include "X86Instr3DNow.td"
2386 include "X86InstrVMX.td"
2387 include "X86InstrSVM.td"
2389 include "X86InstrTSX.td"
2390 include "X86InstrSGX.td"
2392 // System instructions.
2393 include "X86InstrSystem.td"
2395 // Compiler Pseudo Instructions and Pat Patterns
2396 include "X86InstrCompiler.td"
2398 //===----------------------------------------------------------------------===//
2399 // Assembler Mnemonic Aliases
2400 //===----------------------------------------------------------------------===//
2402 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2403 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2404 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2406 def : MnemonicAlias<"cbw", "cbtw", "att">;
2407 def : MnemonicAlias<"cwde", "cwtl", "att">;
2408 def : MnemonicAlias<"cwd", "cwtd", "att">;
2409 def : MnemonicAlias<"cdq", "cltd", "att">;
2410 def : MnemonicAlias<"cdqe", "cltq", "att">;
2411 def : MnemonicAlias<"cqo", "cqto", "att">;
2413 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2414 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2415 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2417 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2418 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2420 def : MnemonicAlias<"loopz", "loope", "att">;
2421 def : MnemonicAlias<"loopnz", "loopne", "att">;
2423 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2424 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2425 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2426 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2427 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2428 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2429 def : MnemonicAlias<"popfd", "popfl", "att">;
2431 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2432 // all modes. However: "push (addr)" and "push $42" should default to
2433 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2434 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2435 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2436 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2437 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2438 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2439 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2440 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2442 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2443 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2444 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2445 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2446 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2447 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2449 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2450 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2451 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2452 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2454 def : MnemonicAlias<"repe", "rep", "att">;
2455 def : MnemonicAlias<"repz", "rep", "att">;
2456 def : MnemonicAlias<"repnz", "repne", "att">;
2458 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2459 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2460 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2462 def : MnemonicAlias<"salb", "shlb", "att">;
2463 def : MnemonicAlias<"salw", "shlw", "att">;
2464 def : MnemonicAlias<"sall", "shll", "att">;
2465 def : MnemonicAlias<"salq", "shlq", "att">;
2467 def : MnemonicAlias<"smovb", "movsb", "att">;
2468 def : MnemonicAlias<"smovw", "movsw", "att">;
2469 def : MnemonicAlias<"smovl", "movsl", "att">;
2470 def : MnemonicAlias<"smovq", "movsq", "att">;
2472 def : MnemonicAlias<"ud2a", "ud2", "att">;
2473 def : MnemonicAlias<"verrw", "verr", "att">;
2475 // System instruction aliases.
2476 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2477 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2478 def : MnemonicAlias<"sysret", "sysretl", "att">;
2479 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2481 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2482 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2483 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2484 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2485 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2486 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2487 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2488 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2489 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2490 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2491 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2492 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2495 // Floating point stack aliases.
2496 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2497 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2498 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2499 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2500 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2501 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2502 def : MnemonicAlias<"fildq", "fildll", "att">;
2503 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2504 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2505 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2506 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2507 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2508 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2509 def : MnemonicAlias<"fwait", "wait">;
2512 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2514 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2515 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2517 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2518 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2519 /// example "setz" -> "sete".
2520 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2522 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2523 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2524 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2525 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2526 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2527 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2528 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2529 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2530 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2531 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2533 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2534 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2535 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2536 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2539 // Aliases for set<CC>
2540 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2541 // Aliases for j<CC>
2542 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2543 // Aliases for cmov<CC>{w,l,q}
2544 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2545 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2546 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2547 // No size suffix for intel-style asm.
2548 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2551 //===----------------------------------------------------------------------===//
2552 // Assembler Instruction Aliases
2553 //===----------------------------------------------------------------------===//
2555 // aad/aam default to base 10 if no operand is specified.
2556 def : InstAlias<"aad", (AAD8i8 10)>;
2557 def : InstAlias<"aam", (AAM8i8 10)>;
2559 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2560 // Likewise for btc/btr/bts.
2561 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2562 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2563 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2564 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2565 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2566 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2567 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2568 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2571 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2572 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2573 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2574 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2576 // lods aliases. Accept the destination being omitted because it's implicit
2577 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2578 // in the destination.
2579 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2580 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2581 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2582 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2583 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2584 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2585 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2586 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2588 // stos aliases. Accept the source being omitted because it's implicit in
2589 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2591 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2592 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2593 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2594 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2595 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2596 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2597 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2598 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2600 // scas aliases. Accept the destination being omitted because it's implicit
2601 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2602 // in the destination.
2603 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2604 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2605 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2606 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2607 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2608 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2609 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2610 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2612 // div and idiv aliases for explicit A register.
2613 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2614 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2615 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2616 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2617 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2618 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2619 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2620 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2621 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2622 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2623 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2624 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2625 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2626 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2627 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2628 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2632 // Various unary fpstack operations default to operating on on ST1.
2633 // For example, "fxch" -> "fxch %st(1)"
2634 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2635 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2636 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2637 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2638 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2639 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2640 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2641 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2642 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2643 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2644 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2645 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2646 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2647 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2648 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2650 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2651 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2652 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2654 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2655 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2656 (Inst RST:$op), EmitAlias>;
2657 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2658 (Inst ST0), EmitAlias>;
2661 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2662 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2663 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2664 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2665 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2666 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2667 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2668 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2669 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2670 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2671 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2672 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2673 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2674 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2675 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2676 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2679 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2680 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2681 // solely because gas supports it.
2682 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2683 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2684 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2685 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2686 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2687 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2689 // We accept "fnstsw %eax" even though it only writes %ax.
2690 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2691 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2692 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2694 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2695 // this is compatible with what GAS does.
2696 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2697 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2698 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2699 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2700 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2701 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2702 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2703 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2705 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2706 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2707 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2708 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2709 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2710 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2713 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2714 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2715 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2716 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2717 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2718 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2719 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2721 // inb %dx -> inb %al, %dx
2722 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2723 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2724 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2725 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2726 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2727 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2730 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2731 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2732 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2733 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2734 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2735 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2736 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2737 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2738 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2740 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2741 // the move. All segment/mem forms are equivalent, this has the shortest
2743 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2744 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2746 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2747 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2749 // Match 'movq GR64, MMX' as an alias for movd.
2750 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2751 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2752 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2753 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2756 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2757 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2758 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2759 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2760 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2761 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2762 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2765 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2766 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2767 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2768 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2769 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2770 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2771 // Note: No GR32->GR64 movzx form.
2773 // outb %dx -> outb %al, %dx
2774 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2775 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2776 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2777 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2778 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2779 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2781 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2782 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2783 // errors, since its encoding is the most compact.
2784 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2786 // shld/shrd op,op -> shld op, op, CL
2787 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2788 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2789 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2790 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2791 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2792 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2794 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2795 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2796 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2797 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2798 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2799 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2801 /* FIXME: This is disabled because the asm matcher is currently incapable of
2802 * matching a fixed immediate like $1.
2803 // "shl X, $1" is an alias for "shl X".
2804 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2805 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2806 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2807 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2808 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2809 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2810 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2811 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2812 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2813 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2814 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2815 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2816 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2817 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2818 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2819 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2820 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2823 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2824 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2825 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2826 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2829 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2830 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2831 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2832 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2833 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2834 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2835 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2836 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2837 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2839 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2840 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2841 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2842 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2843 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2844 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2845 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2846 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2847 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2849 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2850 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2851 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2852 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2853 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2854 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2855 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;