1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
111 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
113 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
115 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
116 [SDNPHasChain,SDNPSideEffect]>;
117 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
119 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
121 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
125 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
126 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
127 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
128 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
130 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
131 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
134 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
136 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
137 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
139 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
141 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
142 [SDNPHasChain, SDNPSideEffect]>;
144 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
145 [SDNPHasChain, SDNPSideEffect]>;
147 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
148 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
149 SDNPMayLoad, SDNPMemOperand]>;
150 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
151 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
152 SDNPMayLoad, SDNPMemOperand]>;
153 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
155 SDNPMayLoad, SDNPMemOperand]>;
157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
160 def X86vastart_save_xmm_regs :
161 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
162 SDT_X86VASTART_SAVE_XMM_REGS,
163 [SDNPHasChain, SDNPVariadic]>;
165 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
166 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
168 def X86callseq_start :
169 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
170 [SDNPHasChain, SDNPOutGlue]>;
172 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
175 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
176 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
179 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
180 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
181 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
185 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
186 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
187 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
192 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
193 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
195 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
196 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
199 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
203 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
205 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
208 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
209 SDTypeProfile<1, 1, [SDTCisInt<0>,
211 [SDNPHasChain, SDNPSideEffect]>;
212 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
213 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
214 [SDNPHasChain, SDNPSideEffect]>;
216 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
217 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
219 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
221 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
222 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
224 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
226 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
227 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
229 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
230 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
231 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
233 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
235 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
238 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
240 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
242 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
243 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
245 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
248 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
249 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
251 //===----------------------------------------------------------------------===//
252 // X86 Operand Definitions.
255 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
256 // the index operand of an address, to conform to x86 encoding restrictions.
257 def ptr_rc_nosp : PointerLikeRegClass<1>;
259 // *mem - Operand definitions for the funky X86 addressing mode operands.
261 def X86MemAsmOperand : AsmOperandClass {
264 let RenderMethod = "addMemOperands" in {
265 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
266 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
267 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
268 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
269 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
270 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
271 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
272 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
273 // Gather mem operands
274 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
275 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
276 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
277 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
278 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
279 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
280 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; }
281 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; }
282 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; }
283 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; }
286 def X86AbsMemAsmOperand : AsmOperandClass {
288 let SuperClasses = [X86MemAsmOperand];
291 class X86MemOperand<string printMethod,
292 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
293 let PrintMethod = printMethod;
294 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
295 let ParserMatchClass = parserMatchClass;
296 let OperandType = "OPERAND_MEMORY";
299 // Gather mem operands
300 class X86VMemOperand<RegisterClass RC, string printMethod,
301 AsmOperandClass parserMatchClass>
302 : X86MemOperand<printMethod, parserMatchClass> {
303 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
306 def anymem : X86MemOperand<"printanymem">;
308 def opaque32mem : X86MemOperand<"printopaquemem">;
309 def opaque48mem : X86MemOperand<"printopaquemem">;
310 def opaque80mem : X86MemOperand<"printopaquemem">;
311 def opaque512mem : X86MemOperand<"printopaquemem">;
313 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
314 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
315 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
316 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
317 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
318 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
319 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
320 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
321 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
322 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
323 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
324 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
325 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
327 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
329 // Gather mem operands
330 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
331 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
332 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
333 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>;
336 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>;
337 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>;
338 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>;
339 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
340 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
342 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
343 // of a plain GPR, so that it doesn't potentially require a REX prefix.
344 def ptr_rc_norex : PointerLikeRegClass<2>;
345 def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
347 def i8mem_NOREX : Operand<iPTR> {
348 let PrintMethod = "printi8mem";
349 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, i8imm);
350 let ParserMatchClass = X86Mem8AsmOperand;
351 let OperandType = "OPERAND_MEMORY";
354 // GPRs available for tailcall.
355 // It represents GR32_TC, GR64_TC or GR64_TCW64.
356 def ptr_rc_tailcall : PointerLikeRegClass<4>;
358 // Special i32mem for addresses of load folding tail calls. These are not
359 // allowed to use callee-saved registers since they must be scheduled
360 // after callee-saved register are popped.
361 def i32mem_TC : Operand<i32> {
362 let PrintMethod = "printi32mem";
363 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
365 let ParserMatchClass = X86Mem32AsmOperand;
366 let OperandType = "OPERAND_MEMORY";
369 // Special i64mem for addresses of load folding tail calls. These are not
370 // allowed to use callee-saved registers since they must be scheduled
371 // after callee-saved register are popped.
372 def i64mem_TC : Operand<i64> {
373 let PrintMethod = "printi64mem";
374 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
375 ptr_rc_tailcall, i32imm, i8imm);
376 let ParserMatchClass = X86Mem64AsmOperand;
377 let OperandType = "OPERAND_MEMORY";
380 let OperandType = "OPERAND_PCREL",
381 ParserMatchClass = X86AbsMemAsmOperand,
382 PrintMethod = "printPCRelImm" in {
383 def i32imm_pcrel : Operand<i32>;
384 def i16imm_pcrel : Operand<i16>;
386 // Branch targets have OtherVT type and print as pc-relative values.
387 def brtarget : Operand<OtherVT>;
388 def brtarget8 : Operand<OtherVT>;
392 // Special parser to detect 16-bit mode to select 16-bit displacement.
393 def X86AbsMem16AsmOperand : AsmOperandClass {
394 let Name = "AbsMem16";
395 let RenderMethod = "addAbsMemOperands";
396 let SuperClasses = [X86AbsMemAsmOperand];
399 // Branch targets have OtherVT type and print as pc-relative values.
400 let OperandType = "OPERAND_PCREL",
401 PrintMethod = "printPCRelImm" in {
402 let ParserMatchClass = X86AbsMem16AsmOperand in
403 def brtarget16 : Operand<OtherVT>;
404 let ParserMatchClass = X86AbsMemAsmOperand in
405 def brtarget32 : Operand<OtherVT>;
408 let RenderMethod = "addSrcIdxOperands" in {
409 def X86SrcIdx8Operand : AsmOperandClass {
410 let Name = "SrcIdx8";
411 let SuperClasses = [X86Mem8AsmOperand];
413 def X86SrcIdx16Operand : AsmOperandClass {
414 let Name = "SrcIdx16";
415 let SuperClasses = [X86Mem16AsmOperand];
417 def X86SrcIdx32Operand : AsmOperandClass {
418 let Name = "SrcIdx32";
419 let SuperClasses = [X86Mem32AsmOperand];
421 def X86SrcIdx64Operand : AsmOperandClass {
422 let Name = "SrcIdx64";
423 let SuperClasses = [X86Mem64AsmOperand];
425 } // RenderMethod = "addSrcIdxOperands"
427 let RenderMethod = "addDstIdxOperands" in {
428 def X86DstIdx8Operand : AsmOperandClass {
429 let Name = "DstIdx8";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86DstIdx16Operand : AsmOperandClass {
433 let Name = "DstIdx16";
434 let SuperClasses = [X86Mem16AsmOperand];
436 def X86DstIdx32Operand : AsmOperandClass {
437 let Name = "DstIdx32";
438 let SuperClasses = [X86Mem32AsmOperand];
440 def X86DstIdx64Operand : AsmOperandClass {
441 let Name = "DstIdx64";
442 let SuperClasses = [X86Mem64AsmOperand];
444 } // RenderMethod = "addDstIdxOperands"
446 let RenderMethod = "addMemOffsOperands" in {
447 def X86MemOffs16_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs16_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs16_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs16_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs32_8AsmOperand : AsmOperandClass {
460 let Name = "MemOffs32_8";
461 let SuperClasses = [X86Mem8AsmOperand];
463 def X86MemOffs32_16AsmOperand : AsmOperandClass {
464 let Name = "MemOffs32_16";
465 let SuperClasses = [X86Mem16AsmOperand];
467 def X86MemOffs32_32AsmOperand : AsmOperandClass {
468 let Name = "MemOffs32_32";
469 let SuperClasses = [X86Mem32AsmOperand];
471 def X86MemOffs32_64AsmOperand : AsmOperandClass {
472 let Name = "MemOffs32_64";
473 let SuperClasses = [X86Mem64AsmOperand];
475 def X86MemOffs64_8AsmOperand : AsmOperandClass {
476 let Name = "MemOffs64_8";
477 let SuperClasses = [X86Mem8AsmOperand];
479 def X86MemOffs64_16AsmOperand : AsmOperandClass {
480 let Name = "MemOffs64_16";
481 let SuperClasses = [X86Mem16AsmOperand];
483 def X86MemOffs64_32AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64_32";
485 let SuperClasses = [X86Mem32AsmOperand];
487 def X86MemOffs64_64AsmOperand : AsmOperandClass {
488 let Name = "MemOffs64_64";
489 let SuperClasses = [X86Mem64AsmOperand];
491 } // RenderMethod = "addMemOffsOperands"
493 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
494 : X86MemOperand<printMethod, parserMatchClass> {
495 let MIOperandInfo = (ops ptr_rc, i8imm);
498 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
499 : X86MemOperand<printMethod, parserMatchClass> {
500 let MIOperandInfo = (ops ptr_rc);
503 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
504 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
505 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
506 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
507 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
508 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
509 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
510 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
512 class X86MemOffsOperand<Operand immOperand, string printMethod,
513 AsmOperandClass parserMatchClass>
514 : X86MemOperand<printMethod, parserMatchClass> {
515 let MIOperandInfo = (ops immOperand, i8imm);
518 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
519 X86MemOffs16_8AsmOperand>;
520 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
521 X86MemOffs16_16AsmOperand>;
522 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
523 X86MemOffs16_32AsmOperand>;
524 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
525 X86MemOffs32_8AsmOperand>;
526 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
527 X86MemOffs32_16AsmOperand>;
528 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
529 X86MemOffs32_32AsmOperand>;
530 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
531 X86MemOffs32_64AsmOperand>;
532 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
533 X86MemOffs64_8AsmOperand>;
534 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
535 X86MemOffs64_16AsmOperand>;
536 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
537 X86MemOffs64_32AsmOperand>;
538 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
539 X86MemOffs64_64AsmOperand>;
541 def SSECC : Operand<i8> {
542 let PrintMethod = "printSSEAVXCC";
543 let OperandType = "OPERAND_IMMEDIATE";
546 def i8immZExt3 : ImmLeaf<i8, [{
547 return Imm >= 0 && Imm < 8;
550 def AVXCC : Operand<i8> {
551 let PrintMethod = "printSSEAVXCC";
552 let OperandType = "OPERAND_IMMEDIATE";
555 def i8immZExt5 : ImmLeaf<i8, [{
556 return Imm >= 0 && Imm < 32;
559 def AVX512ICC : Operand<i8> {
560 let PrintMethod = "printSSEAVXCC";
561 let OperandType = "OPERAND_IMMEDIATE";
564 def XOPCC : Operand<i8> {
565 let PrintMethod = "printXOPCC";
566 let OperandType = "OPERAND_IMMEDIATE";
569 class ImmSExtAsmOperandClass : AsmOperandClass {
570 let SuperClasses = [ImmAsmOperand];
571 let RenderMethod = "addImmOperands";
574 def X86GR32orGR64AsmOperand : AsmOperandClass {
575 let Name = "GR32orGR64";
578 def GR32orGR64 : RegisterOperand<GR32> {
579 let ParserMatchClass = X86GR32orGR64AsmOperand;
581 def AVX512RCOperand : AsmOperandClass {
582 let Name = "AVX512RC";
584 def AVX512RC : Operand<i32> {
585 let PrintMethod = "printRoundingControl";
586 let OperandType = "OPERAND_IMMEDIATE";
587 let ParserMatchClass = AVX512RCOperand;
590 // Sign-extended immediate classes. We don't need to define the full lattice
591 // here because there is no instruction with an ambiguity between ImmSExti64i32
594 // The strange ranges come from the fact that the assembler always works with
595 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
596 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
599 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
600 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
601 let Name = "ImmSExti64i32";
604 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
605 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
606 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
607 let Name = "ImmSExti16i8";
608 let SuperClasses = [ImmSExti64i32AsmOperand];
611 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
612 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
613 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
614 let Name = "ImmSExti32i8";
618 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
619 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
620 let Name = "ImmSExti64i8";
621 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
622 ImmSExti64i32AsmOperand];
625 // Unsigned immediate used by SSE/AVX instructions
627 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
628 def ImmUnsignedi8AsmOperand : AsmOperandClass {
629 let Name = "ImmUnsignedi8";
630 let RenderMethod = "addImmOperands";
633 // A couple of more descriptive operand definitions.
634 // 16-bits but only 8 bits are significant.
635 def i16i8imm : Operand<i16> {
636 let ParserMatchClass = ImmSExti16i8AsmOperand;
637 let OperandType = "OPERAND_IMMEDIATE";
639 // 32-bits but only 8 bits are significant.
640 def i32i8imm : Operand<i32> {
641 let ParserMatchClass = ImmSExti32i8AsmOperand;
642 let OperandType = "OPERAND_IMMEDIATE";
645 // 64-bits but only 32 bits are significant.
646 def i64i32imm : Operand<i64> {
647 let ParserMatchClass = ImmSExti64i32AsmOperand;
648 let OperandType = "OPERAND_IMMEDIATE";
651 // 64-bits but only 8 bits are significant.
652 def i64i8imm : Operand<i64> {
653 let ParserMatchClass = ImmSExti64i8AsmOperand;
654 let OperandType = "OPERAND_IMMEDIATE";
657 // Unsigned 8-bit immediate used by SSE/AVX instructions.
658 def u8imm : Operand<i8> {
659 let PrintMethod = "printU8Imm";
660 let ParserMatchClass = ImmUnsignedi8AsmOperand;
661 let OperandType = "OPERAND_IMMEDIATE";
664 // 32-bit immediate but only 8-bits are significant and they are unsigned.
665 // Used by some SSE/AVX instructions that use intrinsics.
666 def i32u8imm : Operand<i32> {
667 let PrintMethod = "printU8Imm";
668 let ParserMatchClass = ImmUnsignedi8AsmOperand;
669 let OperandType = "OPERAND_IMMEDIATE";
672 // 64-bits but only 32 bits are significant, and those bits are treated as being
674 def i64i32imm_pcrel : Operand<i64> {
675 let PrintMethod = "printPCRelImm";
676 let ParserMatchClass = X86AbsMemAsmOperand;
677 let OperandType = "OPERAND_PCREL";
680 def lea64_32mem : Operand<i32> {
681 let PrintMethod = "printanymem";
682 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
683 let ParserMatchClass = X86MemAsmOperand;
686 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
687 def lea64mem : Operand<i64> {
688 let PrintMethod = "printanymem";
689 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
690 let ParserMatchClass = X86MemAsmOperand;
694 //===----------------------------------------------------------------------===//
695 // X86 Complex Pattern Definitions.
698 // Define X86-specific addressing mode.
699 def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
700 def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
701 [add, sub, mul, X86mul_imm, shl, or, frameindex],
703 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
704 def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
705 [add, sub, mul, X86mul_imm, shl, or,
706 frameindex, X86WrapperRIP],
709 def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
710 [tglobaltlsaddr], []>;
712 def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
713 [tglobaltlsaddr], []>;
715 def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
716 [add, sub, mul, X86mul_imm, shl, or, frameindex,
719 def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
720 [tglobaltlsaddr], []>;
722 def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
723 [tglobaltlsaddr], []>;
725 def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
727 //===----------------------------------------------------------------------===//
728 // X86 Instruction Predicate Definitions.
729 def HasCMov : Predicate<"Subtarget->hasCMov()">;
730 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
732 def HasMMX : Predicate<"Subtarget->hasMMX()">;
733 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
734 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
735 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
736 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
737 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
738 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
739 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
740 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
741 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
742 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
743 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
744 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
745 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
746 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
747 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
748 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
749 def HasAVX : Predicate<"Subtarget->hasAVX()">;
750 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
751 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
752 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
753 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
754 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
755 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
756 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
757 def HasCDI : Predicate<"Subtarget->hasCDI()">,
758 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
759 def HasPFI : Predicate<"Subtarget->hasPFI()">,
760 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
761 def HasERI : Predicate<"Subtarget->hasERI()">,
762 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
763 def HasDQI : Predicate<"Subtarget->hasDQI()">,
764 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
765 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
766 def HasBWI : Predicate<"Subtarget->hasBWI()">,
767 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
768 def NoBWI : Predicate<"!Subtarget->hasBWI()">;
769 def HasVLX : Predicate<"Subtarget->hasVLX()">,
770 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
771 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
772 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
773 def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
774 def PKU : Predicate<"!Subtarget->hasPKU()">;
776 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
777 def HasAES : Predicate<"Subtarget->hasAES()">;
778 def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
779 def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
780 def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
781 def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">;
782 def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">;
783 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
784 def HasFMA : Predicate<"Subtarget->hasFMA()">;
785 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
786 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
787 def HasXOP : Predicate<"Subtarget->hasXOP()">;
788 def HasTBM : Predicate<"Subtarget->hasTBM()">;
789 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
790 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
791 def HasF16C : Predicate<"Subtarget->hasF16C()">;
792 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
793 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
794 def HasBMI : Predicate<"Subtarget->hasBMI()">;
795 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
796 def HasRTM : Predicate<"Subtarget->hasRTM()">;
797 def HasHLE : Predicate<"Subtarget->hasHLE()">;
798 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
799 def HasADX : Predicate<"Subtarget->hasADX()">;
800 def HasSHA : Predicate<"Subtarget->hasSHA()">;
801 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
802 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
803 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
804 def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
805 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
806 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
807 def HasMPX : Predicate<"Subtarget->hasMPX()">;
808 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
809 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
810 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
811 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
812 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
813 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
814 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
815 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
816 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
817 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
818 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
819 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
820 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
821 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
822 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
823 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
824 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
825 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
826 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
827 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
828 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
829 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
830 "TM.getCodeModel() != CodeModel::Kernel">;
831 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
832 "TM.getCodeModel() == CodeModel::Kernel">;
833 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
834 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
835 def OptForSize : Predicate<"OptForSize">;
836 def OptForSpeed : Predicate<"!OptForSize">;
837 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
838 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
839 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
840 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
841 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
843 //===----------------------------------------------------------------------===//
844 // X86 Instruction Format Definitions.
847 include "X86InstrFormats.td"
849 //===----------------------------------------------------------------------===//
850 // Pattern fragments.
853 // X86 specific condition code. These correspond to CondCode in
854 // X86InstrInfo.h. They must be kept in synch.
855 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
856 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
857 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
858 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
859 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
860 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
861 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
862 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
863 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
864 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
865 def X86_COND_NO : PatLeaf<(i8 10)>;
866 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
867 def X86_COND_NS : PatLeaf<(i8 12)>;
868 def X86_COND_O : PatLeaf<(i8 13)>;
869 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
870 def X86_COND_S : PatLeaf<(i8 15)>;
872 // Predicate used to help when pattern matching LZCNT/TZCNT.
873 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
874 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
878 def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
879 def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
880 def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
882 // If we have multiple users of an immediate, it's much smaller to reuse
883 // the register, rather than encode the immediate in every instruction.
884 // This has the risk of increasing register pressure from stretched live
885 // ranges, however, the immediates should be trivial to rematerialize by
886 // the RA in the event of high register pressure.
887 // TODO : This is currently enabled for stores and binary ops. There are more
888 // cases for which this can be enabled, though this catches the bulk of the
890 // TODO2 : This should really also be enabled under O2, but there's currently
891 // an issue with RA where we don't pull the constants into their users
892 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that
894 // TODO3 : This is currently limited to single basic blocks (DAG creation
895 // pulls block immediates to the top and merges them if necessary).
896 // Eventually, it would be nice to allow ConstantHoisting to merge constants
897 // globally for potentially added savings.
899 def imm8_su : PatLeaf<(i8 imm), [{
900 return !shouldAvoidImmediateInstFormsForSize(N);
902 def imm16_su : PatLeaf<(i16 imm), [{
903 return !shouldAvoidImmediateInstFormsForSize(N);
905 def imm32_su : PatLeaf<(i32 imm), [{
906 return !shouldAvoidImmediateInstFormsForSize(N);
909 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
910 return !shouldAvoidImmediateInstFormsForSize(N);
912 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
913 return !shouldAvoidImmediateInstFormsForSize(N);
917 def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
920 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
922 def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
924 def i64immZExt32SExt8 : ImmLeaf<i64, [{
925 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
928 // Helper fragments for loads.
929 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
930 // known to be 32-bit aligned or better. Ditto for i8 to i16.
931 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
932 LoadSDNode *LD = cast<LoadSDNode>(N);
933 ISD::LoadExtType ExtType = LD->getExtensionType();
934 if (ExtType == ISD::NON_EXTLOAD)
936 if (ExtType == ISD::EXTLOAD)
937 return LD->getAlignment() >= 2 && !LD->isVolatile();
941 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
942 LoadSDNode *LD = cast<LoadSDNode>(N);
943 ISD::LoadExtType ExtType = LD->getExtensionType();
944 if (ExtType == ISD::EXTLOAD)
945 return LD->getAlignment() >= 2 && !LD->isVolatile();
949 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
950 LoadSDNode *LD = cast<LoadSDNode>(N);
951 ISD::LoadExtType ExtType = LD->getExtensionType();
952 if (ExtType == ISD::NON_EXTLOAD)
954 if (ExtType == ISD::EXTLOAD)
955 return LD->getAlignment() >= 4 && !LD->isVolatile();
959 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
960 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
961 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
962 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
963 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
964 def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>;
966 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
967 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
968 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
969 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
970 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
971 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
973 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
974 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
975 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
976 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
977 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
978 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
979 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
980 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
981 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
982 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
984 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
985 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
986 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
987 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
988 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
989 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
990 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
991 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
992 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
993 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
996 // An 'and' node with a single use.
997 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
998 return N->hasOneUse();
1000 // An 'srl' node with a single use.
1001 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
1002 return N->hasOneUse();
1004 // An 'trunc' node with a single use.
1005 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
1006 return N->hasOneUse();
1009 //===----------------------------------------------------------------------===//
1010 // Instruction list.
1014 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1015 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
1016 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
1017 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
1018 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
1019 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1023 // Constructing a stack frame.
1024 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
1025 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
1027 let SchedRW = [WriteALU] in {
1028 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
1029 def LEAVE : I<0xC9, RawFrm,
1030 (outs), (ins), "leave", [], IIC_LEAVE>,
1031 Requires<[Not64BitMode]>;
1033 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1034 def LEAVE64 : I<0xC9, RawFrm,
1035 (outs), (ins), "leave", [], IIC_LEAVE>,
1036 Requires<[In64BitMode]>;
1039 //===----------------------------------------------------------------------===//
1040 // Miscellaneous Instructions.
1043 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1044 let mayLoad = 1, SchedRW = [WriteLoad] in {
1045 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1046 IIC_POP_REG16>, OpSize16;
1047 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1048 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1049 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1050 IIC_POP_REG>, OpSize16;
1051 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1052 IIC_POP_MEM>, OpSize16;
1053 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1054 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1055 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1056 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1057 } // mayLoad, SchedRW
1059 let mayStore = 1, SchedRW = [WriteStore] in {
1060 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1061 IIC_PUSH_REG>, OpSize16;
1062 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1063 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1064 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1065 IIC_PUSH_REG>, OpSize16;
1066 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1067 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1069 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1070 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1071 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1072 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1074 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1075 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1076 Requires<[Not64BitMode]>;
1077 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1078 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1079 Requires<[Not64BitMode]>;
1080 } // mayStore, SchedRW
1082 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1083 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1084 IIC_PUSH_MEM>, OpSize16;
1085 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1086 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1087 } // mayLoad, mayStore, SchedRW
1091 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1092 SchedRW = [WriteLoad] in {
1093 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1095 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1096 OpSize32, Requires<[Not64BitMode]>;
1099 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1100 SchedRW = [WriteStore] in {
1101 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1103 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1104 OpSize32, Requires<[Not64BitMode]>;
1107 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1108 let mayLoad = 1, SchedRW = [WriteLoad] in {
1109 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1110 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1111 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1112 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1113 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1114 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1115 } // mayLoad, SchedRW
1116 let mayStore = 1, SchedRW = [WriteStore] in {
1117 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1118 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1119 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1120 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1121 } // mayStore, SchedRW
1122 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1123 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1124 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1125 } // mayLoad, mayStore, SchedRW
1128 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1129 SchedRW = [WriteStore] in {
1130 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1131 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1132 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1133 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1134 Requires<[In64BitMode]>;
1137 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1138 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1139 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1140 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1141 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1142 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1144 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1145 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1146 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1147 OpSize32, Requires<[Not64BitMode]>;
1148 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1149 OpSize16, Requires<[Not64BitMode]>;
1151 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1152 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1153 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1154 OpSize32, Requires<[Not64BitMode]>;
1155 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1156 OpSize16, Requires<[Not64BitMode]>;
1159 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1160 // GR32 = bswap GR32
1161 def BSWAP32r : I<0xC8, AddRegFrm,
1162 (outs GR32:$dst), (ins GR32:$src),
1164 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1166 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1168 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1169 } // Constraints = "$src = $dst", SchedRW
1171 // Bit scan instructions.
1172 let Defs = [EFLAGS] in {
1173 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1174 "bsf{w}\t{$src, $dst|$dst, $src}",
1175 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1176 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1177 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1178 "bsf{w}\t{$src, $dst|$dst, $src}",
1179 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1180 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1181 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1182 "bsf{l}\t{$src, $dst|$dst, $src}",
1183 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1184 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1185 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1186 "bsf{l}\t{$src, $dst|$dst, $src}",
1187 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1188 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1189 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1190 "bsf{q}\t{$src, $dst|$dst, $src}",
1191 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1192 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1193 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1194 "bsf{q}\t{$src, $dst|$dst, $src}",
1195 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1196 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1198 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1199 "bsr{w}\t{$src, $dst|$dst, $src}",
1200 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1201 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1202 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1203 "bsr{w}\t{$src, $dst|$dst, $src}",
1204 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1205 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1206 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1207 "bsr{l}\t{$src, $dst|$dst, $src}",
1208 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1209 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1210 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1211 "bsr{l}\t{$src, $dst|$dst, $src}",
1212 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1213 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1214 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1215 "bsr{q}\t{$src, $dst|$dst, $src}",
1216 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1217 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1218 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1219 "bsr{q}\t{$src, $dst|$dst, $src}",
1220 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1221 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1222 } // Defs = [EFLAGS]
1224 let SchedRW = [WriteMicrocoded] in {
1225 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1226 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1227 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1228 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1229 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1230 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1231 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1232 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1233 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1234 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1237 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1238 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1239 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1240 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1241 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1242 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1243 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1244 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1245 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1246 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1247 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1248 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1249 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1251 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1252 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1253 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1254 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1255 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1256 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1257 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1258 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1259 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1260 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1261 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1262 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1263 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1265 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1266 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1267 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1268 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1269 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1270 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1271 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1272 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1273 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1274 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1278 //===----------------------------------------------------------------------===//
1279 // Move Instructions.
1281 let SchedRW = [WriteMove] in {
1282 let hasSideEffects = 0 in {
1283 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1284 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1285 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1286 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1287 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1288 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1289 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1290 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1293 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1294 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1295 "mov{b}\t{$src, $dst|$dst, $src}",
1296 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1297 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1298 "mov{w}\t{$src, $dst|$dst, $src}",
1299 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1300 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1301 "mov{l}\t{$src, $dst|$dst, $src}",
1302 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1303 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1304 "mov{q}\t{$src, $dst|$dst, $src}",
1305 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1307 let isReMaterializable = 1 in {
1308 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1309 "movabs{q}\t{$src, $dst|$dst, $src}",
1310 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1313 // Longer forms that use a ModR/M byte. Needed for disassembler
1314 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1315 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1316 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1317 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1318 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1319 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1320 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1324 let SchedRW = [WriteStore] in {
1325 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1326 "mov{b}\t{$src, $dst|$dst, $src}",
1327 [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>;
1328 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1329 "mov{w}\t{$src, $dst|$dst, $src}",
1330 [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1331 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1332 "mov{l}\t{$src, $dst|$dst, $src}",
1333 [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1334 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1335 "mov{q}\t{$src, $dst|$dst, $src}",
1336 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1339 let hasSideEffects = 0 in {
1341 /// Memory offset versions of moves. The immediate is an address mode sized
1342 /// offset from the segment base.
1343 let SchedRW = [WriteALU] in {
1344 let mayLoad = 1 in {
1346 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1347 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1350 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1351 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1354 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1355 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1358 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1359 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1363 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1364 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1366 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1367 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1370 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1371 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1374 let mayStore = 1 in {
1376 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1377 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1379 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1380 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1383 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1384 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1387 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1388 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1392 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1393 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1395 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1396 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1399 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1400 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1405 // These forms all have full 64-bit absolute addresses in their instructions
1406 // and use the movabs mnemonic to indicate this specific form.
1407 let mayLoad = 1 in {
1409 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1410 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1412 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1413 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1415 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1416 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1419 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1420 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1423 let mayStore = 1 in {
1425 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1426 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1428 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1429 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1431 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1432 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1435 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1436 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1438 } // hasSideEffects = 0
1440 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1441 SchedRW = [WriteMove] in {
1442 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1443 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1444 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1445 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1446 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1447 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1448 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1449 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1452 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1453 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1454 "mov{b}\t{$src, $dst|$dst, $src}",
1455 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1456 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1457 "mov{w}\t{$src, $dst|$dst, $src}",
1458 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1459 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1460 "mov{l}\t{$src, $dst|$dst, $src}",
1461 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1462 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1463 "mov{q}\t{$src, $dst|$dst, $src}",
1464 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1467 let SchedRW = [WriteStore] in {
1468 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1469 "mov{b}\t{$src, $dst|$dst, $src}",
1470 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1471 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1472 "mov{w}\t{$src, $dst|$dst, $src}",
1473 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1474 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1475 "mov{l}\t{$src, $dst|$dst, $src}",
1476 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1477 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1478 "mov{q}\t{$src, $dst|$dst, $src}",
1479 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1482 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1483 // that they can be used for copying and storing h registers, which can't be
1484 // encoded when a REX prefix is present.
1485 let isCodeGenOnly = 1 in {
1486 let hasSideEffects = 0 in
1487 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1488 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1489 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1491 let mayStore = 1, hasSideEffects = 0 in
1492 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1493 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1494 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1495 IIC_MOV_MEM>, Sched<[WriteStore]>;
1496 let mayLoad = 1, hasSideEffects = 0,
1497 canFoldAsLoad = 1, isReMaterializable = 1 in
1498 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1499 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1500 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1501 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1505 // Condition code ops, incl. set if equal/not equal/...
1506 let SchedRW = [WriteALU] in {
1507 let Defs = [EFLAGS], Uses = [AH] in
1508 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1509 [(set EFLAGS, (X86sahf AH))], IIC_AHF>,
1510 Requires<[HasLAHFSAHF]>;
1511 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1512 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1513 IIC_AHF>, // AH = flags
1514 Requires<[HasLAHFSAHF]>;
1517 //===----------------------------------------------------------------------===//
1518 // Bit tests instructions: BT, BTS, BTR, BTC.
1520 let Defs = [EFLAGS] in {
1521 let SchedRW = [WriteALU] in {
1522 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1523 "bt{w}\t{$src2, $src1|$src1, $src2}",
1524 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1526 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1527 "bt{l}\t{$src2, $src1|$src1, $src2}",
1528 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1530 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1531 "bt{q}\t{$src2, $src1|$src1, $src2}",
1532 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1535 // Unlike with the register+register form, the memory+register form of the
1536 // bt instruction does not ignore the high bits of the index. From ISel's
1537 // perspective, this is pretty bizarre. Make these instructions disassembly
1540 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1541 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1542 "bt{w}\t{$src2, $src1|$src1, $src2}",
1543 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1544 // (implicit EFLAGS)]
1546 >, OpSize16, TB, Requires<[FastBTMem]>;
1547 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1548 "bt{l}\t{$src2, $src1|$src1, $src2}",
1549 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1550 // (implicit EFLAGS)]
1552 >, OpSize32, TB, Requires<[FastBTMem]>;
1553 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1554 "bt{q}\t{$src2, $src1|$src1, $src2}",
1555 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1556 // (implicit EFLAGS)]
1561 let SchedRW = [WriteALU] in {
1562 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1563 "bt{w}\t{$src2, $src1|$src1, $src2}",
1564 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1565 IIC_BT_RI>, OpSize16, TB;
1566 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1567 "bt{l}\t{$src2, $src1|$src1, $src2}",
1568 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1569 IIC_BT_RI>, OpSize32, TB;
1570 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1571 "bt{q}\t{$src2, $src1|$src1, $src2}",
1572 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1576 // Note that these instructions don't need FastBTMem because that
1577 // only applies when the other operand is in a register. When it's
1578 // an immediate, bt is still fast.
1579 let SchedRW = [WriteALU] in {
1580 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1581 "bt{w}\t{$src2, $src1|$src1, $src2}",
1582 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1583 ], IIC_BT_MI>, OpSize16, TB;
1584 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1585 "bt{l}\t{$src2, $src1|$src1, $src2}",
1586 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1587 ], IIC_BT_MI>, OpSize32, TB;
1588 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1589 "bt{q}\t{$src2, $src1|$src1, $src2}",
1590 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1591 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1594 let hasSideEffects = 0 in {
1595 let SchedRW = [WriteALU] in {
1596 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1597 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1599 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1600 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1602 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1603 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1606 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1607 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1608 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1610 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1611 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1613 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1614 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1617 let SchedRW = [WriteALU] in {
1618 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1619 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1621 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1622 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1624 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1625 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1628 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1629 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1630 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1632 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1633 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1635 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1636 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1639 let SchedRW = [WriteALU] in {
1640 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1641 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1643 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1644 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1646 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1647 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1650 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1651 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1652 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1654 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1655 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1657 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1658 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1661 let SchedRW = [WriteALU] in {
1662 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1663 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1665 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1666 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1668 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1669 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1672 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1673 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1674 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1676 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1677 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1679 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1680 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1683 let SchedRW = [WriteALU] in {
1684 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1685 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1687 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1688 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1690 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1691 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1694 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1695 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1696 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1698 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1699 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1701 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1702 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1705 let SchedRW = [WriteALU] in {
1706 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1707 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1709 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1710 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1712 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1713 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1716 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1717 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1718 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1720 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1721 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1723 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1724 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1726 } // hasSideEffects = 0
1727 } // Defs = [EFLAGS]
1730 //===----------------------------------------------------------------------===//
1734 // Atomic swap. These are just normal xchg instructions. But since a memory
1735 // operand is referenced, the atomicity is ensured.
1736 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1737 InstrItinClass itin> {
1738 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1739 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1740 (ins GR8:$val, i8mem:$ptr),
1741 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1744 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1746 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1747 (ins GR16:$val, i16mem:$ptr),
1748 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1751 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1753 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1754 (ins GR32:$val, i32mem:$ptr),
1755 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1758 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1760 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1761 (ins GR64:$val, i64mem:$ptr),
1762 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1765 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1770 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1772 // Swap between registers.
1773 let SchedRW = [WriteALU] in {
1774 let Constraints = "$val = $dst" in {
1775 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1776 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1777 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1778 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1780 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1781 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1783 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1784 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1787 // Swap between EAX and other registers.
1788 let Uses = [AX], Defs = [AX] in
1789 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1790 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1791 let Uses = [EAX], Defs = [EAX] in
1792 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1793 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1794 OpSize32, Requires<[Not64BitMode]>;
1795 let Uses = [EAX], Defs = [EAX] in
1796 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1797 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1798 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1799 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1800 OpSize32, Requires<[In64BitMode]>;
1801 let Uses = [RAX], Defs = [RAX] in
1802 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1803 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1806 let SchedRW = [WriteALU] in {
1807 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1808 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1809 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1810 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1812 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1813 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1815 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1816 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1819 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1820 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1821 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1822 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1823 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1825 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1826 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1828 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1829 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1833 let SchedRW = [WriteALU] in {
1834 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1835 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1836 IIC_CMPXCHG_REG8>, TB;
1837 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1838 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1839 IIC_CMPXCHG_REG>, TB, OpSize16;
1840 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1841 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1842 IIC_CMPXCHG_REG>, TB, OpSize32;
1843 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1844 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1845 IIC_CMPXCHG_REG>, TB;
1848 let SchedRW = [WriteALULd, WriteRMW] in {
1849 let mayLoad = 1, mayStore = 1 in {
1850 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1851 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1852 IIC_CMPXCHG_MEM8>, TB;
1853 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1854 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1855 IIC_CMPXCHG_MEM>, TB, OpSize16;
1856 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1857 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1858 IIC_CMPXCHG_MEM>, TB, OpSize32;
1859 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1860 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1861 IIC_CMPXCHG_MEM>, TB;
1864 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1865 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1866 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1868 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1869 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1870 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1871 TB, Requires<[HasCmpxchg16b]>;
1875 // Lock instruction prefix
1876 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1878 // Rex64 instruction prefix
1879 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1880 Requires<[In64BitMode]>;
1882 // Data16 instruction prefix
1883 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1885 // Repeat string operation instruction prefixes
1886 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1887 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1888 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1889 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1890 // Repeat while not equal (used with CMPS and SCAS)
1891 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1895 // String manipulation instructions
1896 let SchedRW = [WriteMicrocoded] in {
1897 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1898 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1899 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1900 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1901 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1902 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1903 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1904 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1905 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1906 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1907 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1908 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1909 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1912 let SchedRW = [WriteSystem] in {
1913 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1914 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1915 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1916 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1917 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1918 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1919 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1920 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1923 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1924 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1925 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1926 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1927 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1928 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1929 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1930 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1934 // Flag instructions
1935 let SchedRW = [WriteALU] in {
1936 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1937 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1938 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1939 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1940 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1941 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1942 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1944 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1947 // Table lookup instructions
1948 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1951 let SchedRW = [WriteMicrocoded] in {
1952 // ASCII Adjust After Addition
1953 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1954 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1955 Requires<[Not64BitMode]>;
1957 // ASCII Adjust AX Before Division
1958 // sets AL, AH and EFLAGS and uses AL and AH
1959 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1960 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1962 // ASCII Adjust AX After Multiply
1963 // sets AL, AH and EFLAGS and uses AL
1964 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1965 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1967 // ASCII Adjust AL After Subtraction - sets
1968 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1969 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1970 Requires<[Not64BitMode]>;
1972 // Decimal Adjust AL after Addition
1973 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1974 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1975 Requires<[Not64BitMode]>;
1977 // Decimal Adjust AL after Subtraction
1978 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1979 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1980 Requires<[Not64BitMode]>;
1983 let SchedRW = [WriteSystem] in {
1984 // Check Array Index Against Bounds
1985 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1986 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1987 Requires<[Not64BitMode]>;
1988 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1989 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1990 Requires<[Not64BitMode]>;
1992 // Adjust RPL Field of Segment Selector
1993 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1994 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1995 Requires<[Not64BitMode]>;
1996 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1997 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1998 Requires<[Not64BitMode]>;
2001 //===----------------------------------------------------------------------===//
2002 // MOVBE Instructions
2004 let Predicates = [HasMOVBE] in {
2005 let SchedRW = [WriteALULd] in {
2006 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2007 "movbe{w}\t{$src, $dst|$dst, $src}",
2008 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
2010 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2011 "movbe{l}\t{$src, $dst|$dst, $src}",
2012 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
2014 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2015 "movbe{q}\t{$src, $dst|$dst, $src}",
2016 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
2019 let SchedRW = [WriteStore] in {
2020 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2021 "movbe{w}\t{$src, $dst|$dst, $src}",
2022 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
2024 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2025 "movbe{l}\t{$src, $dst|$dst, $src}",
2026 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
2028 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2029 "movbe{q}\t{$src, $dst|$dst, $src}",
2030 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
2035 //===----------------------------------------------------------------------===//
2036 // RDRAND Instruction
2038 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
2039 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2041 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
2042 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2044 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
2045 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2047 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2050 //===----------------------------------------------------------------------===//
2051 // RDSEED Instruction
2053 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2054 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2056 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2057 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2059 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2060 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2062 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2065 //===----------------------------------------------------------------------===//
2066 // LZCNT Instruction
2068 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2069 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2070 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2071 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2073 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2074 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2075 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2076 (implicit EFLAGS)]>, XS, OpSize16;
2078 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2079 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2080 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2082 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2083 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2084 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2085 (implicit EFLAGS)]>, XS, OpSize32;
2087 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2088 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2089 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2091 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2092 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2093 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2094 (implicit EFLAGS)]>, XS;
2097 let Predicates = [HasLZCNT] in {
2098 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2099 (X86cmp GR16:$src, (i16 0))),
2100 (LZCNT16rr GR16:$src)>;
2101 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2102 (X86cmp GR32:$src, (i32 0))),
2103 (LZCNT32rr GR32:$src)>;
2104 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2105 (X86cmp GR64:$src, (i64 0))),
2106 (LZCNT64rr GR64:$src)>;
2107 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2108 (X86cmp GR16:$src, (i16 0))),
2109 (LZCNT16rr GR16:$src)>;
2110 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2111 (X86cmp GR32:$src, (i32 0))),
2112 (LZCNT32rr GR32:$src)>;
2113 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2114 (X86cmp GR64:$src, (i64 0))),
2115 (LZCNT64rr GR64:$src)>;
2117 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2118 (X86cmp (loadi16 addr:$src), (i16 0))),
2119 (LZCNT16rm addr:$src)>;
2120 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2121 (X86cmp (loadi32 addr:$src), (i32 0))),
2122 (LZCNT32rm addr:$src)>;
2123 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2124 (X86cmp (loadi64 addr:$src), (i64 0))),
2125 (LZCNT64rm addr:$src)>;
2126 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2127 (X86cmp (loadi16 addr:$src), (i16 0))),
2128 (LZCNT16rm addr:$src)>;
2129 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2130 (X86cmp (loadi32 addr:$src), (i32 0))),
2131 (LZCNT32rm addr:$src)>;
2132 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2133 (X86cmp (loadi64 addr:$src), (i64 0))),
2134 (LZCNT64rm addr:$src)>;
2137 //===----------------------------------------------------------------------===//
2140 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2141 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2142 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2143 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2145 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2146 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2147 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2148 (implicit EFLAGS)]>, XS, OpSize16;
2150 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2151 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2152 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2154 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2155 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2156 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2157 (implicit EFLAGS)]>, XS, OpSize32;
2159 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2160 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2161 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2163 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2164 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2165 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2166 (implicit EFLAGS)]>, XS;
2169 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2170 RegisterClass RC, X86MemOperand x86memop> {
2171 let hasSideEffects = 0 in {
2172 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2173 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2176 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2177 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2182 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2183 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2184 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2185 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2186 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2187 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2188 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2191 //===----------------------------------------------------------------------===//
2192 // Pattern fragments to auto generate BMI instructions.
2193 //===----------------------------------------------------------------------===//
2195 let Predicates = [HasBMI] in {
2196 // FIXME: patterns for the load versions are not implemented
2197 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2198 (BLSR32rr GR32:$src)>;
2199 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2200 (BLSR64rr GR64:$src)>;
2202 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2203 (BLSMSK32rr GR32:$src)>;
2204 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2205 (BLSMSK64rr GR64:$src)>;
2207 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2208 (BLSI32rr GR32:$src)>;
2209 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2210 (BLSI64rr GR64:$src)>;
2213 let Predicates = [HasBMI] in {
2214 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2215 (X86cmp GR16:$src, (i16 0))),
2216 (TZCNT16rr GR16:$src)>;
2217 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2218 (X86cmp GR32:$src, (i32 0))),
2219 (TZCNT32rr GR32:$src)>;
2220 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2221 (X86cmp GR64:$src, (i64 0))),
2222 (TZCNT64rr GR64:$src)>;
2223 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2224 (X86cmp GR16:$src, (i16 0))),
2225 (TZCNT16rr GR16:$src)>;
2226 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2227 (X86cmp GR32:$src, (i32 0))),
2228 (TZCNT32rr GR32:$src)>;
2229 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2230 (X86cmp GR64:$src, (i64 0))),
2231 (TZCNT64rr GR64:$src)>;
2233 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2234 (X86cmp (loadi16 addr:$src), (i16 0))),
2235 (TZCNT16rm addr:$src)>;
2236 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2237 (X86cmp (loadi32 addr:$src), (i32 0))),
2238 (TZCNT32rm addr:$src)>;
2239 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2240 (X86cmp (loadi64 addr:$src), (i64 0))),
2241 (TZCNT64rm addr:$src)>;
2242 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2243 (X86cmp (loadi16 addr:$src), (i16 0))),
2244 (TZCNT16rm addr:$src)>;
2245 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2246 (X86cmp (loadi32 addr:$src), (i32 0))),
2247 (TZCNT32rm addr:$src)>;
2248 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2249 (X86cmp (loadi64 addr:$src), (i64 0))),
2250 (TZCNT64rm addr:$src)>;
2254 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2255 X86MemOperand x86memop, Intrinsic Int,
2257 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2258 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2259 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2261 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2262 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2263 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2264 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2267 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2268 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2269 int_x86_bmi_bextr_32, loadi32>;
2270 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2271 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2274 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2275 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2276 int_x86_bmi_bzhi_32, loadi32>;
2277 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2278 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2282 def CountTrailingOnes : SDNodeXForm<imm, [{
2283 // Count the trailing ones in the immediate.
2284 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2287 def BZHIMask : ImmLeaf<i64, [{
2288 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2291 let Predicates = [HasBMI2] in {
2292 def : Pat<(and GR64:$src, BZHIMask:$mask),
2293 (BZHI64rr GR64:$src,
2294 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2295 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2297 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2298 (BZHI32rr GR32:$src,
2299 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2301 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2302 (BZHI32rm addr:$src,
2303 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2305 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2306 (BZHI64rr GR64:$src,
2307 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2309 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2310 (BZHI64rm addr:$src,
2311 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2314 let Predicates = [HasBMI] in {
2315 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2316 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2317 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2318 (BEXTR32rm addr:$src1, GR32:$src2)>;
2319 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2320 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2321 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2322 (BEXTR64rm addr:$src1, GR64:$src2)>;
2325 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2326 X86MemOperand x86memop, Intrinsic Int,
2328 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2329 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2330 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2332 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2333 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2334 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2337 let Predicates = [HasBMI2] in {
2338 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2339 int_x86_bmi_pdep_32, loadi32>, T8XD;
2340 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2341 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2342 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2343 int_x86_bmi_pext_32, loadi32>, T8XS;
2344 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2345 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2348 //===----------------------------------------------------------------------===//
2351 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2353 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2354 X86MemOperand x86memop, PatFrag ld_frag,
2355 Intrinsic Int, Operand immtype,
2356 SDPatternOperator immoperator> {
2357 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2358 !strconcat(OpcodeStr,
2359 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2360 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2362 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2363 (ins x86memop:$src1, immtype:$cntl),
2364 !strconcat(OpcodeStr,
2365 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2366 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2370 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2371 int_x86_tbm_bextri_u32, i32imm, imm>;
2372 let ImmT = Imm32S in
2373 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2374 int_x86_tbm_bextri_u64, i64i32imm,
2375 i64immSExt32>, VEX_W;
2377 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2378 RegisterClass RC, string OpcodeStr,
2379 X86MemOperand x86memop, PatFrag ld_frag> {
2380 let hasSideEffects = 0 in {
2381 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2382 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2385 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2386 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2391 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2392 Format FormReg, Format FormMem> {
2393 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2395 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2399 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2400 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2401 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2402 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2403 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2404 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2405 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2406 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2407 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2410 //===----------------------------------------------------------------------===//
2411 // MONITORX/MWAITX Instructions
2413 let SchedRW = [WriteSystem] in {
2414 let Uses = [EAX, ECX, EDX] in
2415 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", [],
2416 IIC_SSE_MONITOR>, TB;
2417 let Uses = [ECX, EAX, EBX] in
2418 def MWAITXrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", [], IIC_SSE_MWAIT>,
2422 def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrr)>, Requires<[Not64BitMode]>;
2423 def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrr)>, Requires<[In64BitMode]>;
2425 def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>,
2426 Requires<[Not64BitMode]>;
2427 def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>,
2428 Requires<[In64BitMode]>;
2430 //===----------------------------------------------------------------------===//
2431 // CLZERO Instruction
2434 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, TB;
2436 //===----------------------------------------------------------------------===//
2437 // Pattern fragments to auto generate TBM instructions.
2438 //===----------------------------------------------------------------------===//
2440 let Predicates = [HasTBM] in {
2441 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2442 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2443 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2444 (BEXTRI32mi addr:$src1, imm:$src2)>;
2445 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2446 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2447 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2448 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2450 // FIXME: patterns for the load versions are not implemented
2451 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2452 (BLCFILL32rr GR32:$src)>;
2453 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2454 (BLCFILL64rr GR64:$src)>;
2456 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2457 (BLCI32rr GR32:$src)>;
2458 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2459 (BLCI64rr GR64:$src)>;
2461 // Extra patterns because opt can optimize the above patterns to this.
2462 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2463 (BLCI32rr GR32:$src)>;
2464 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2465 (BLCI64rr GR64:$src)>;
2467 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2468 (BLCIC32rr GR32:$src)>;
2469 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2470 (BLCIC64rr GR64:$src)>;
2472 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2473 (BLCMSK32rr GR32:$src)>;
2474 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2475 (BLCMSK64rr GR64:$src)>;
2477 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2478 (BLCS32rr GR32:$src)>;
2479 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2480 (BLCS64rr GR64:$src)>;
2482 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2483 (BLSFILL32rr GR32:$src)>;
2484 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2485 (BLSFILL64rr GR64:$src)>;
2487 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2488 (BLSIC32rr GR32:$src)>;
2489 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2490 (BLSIC64rr GR64:$src)>;
2492 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2493 (T1MSKC32rr GR32:$src)>;
2494 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2495 (T1MSKC64rr GR64:$src)>;
2497 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2498 (TZMSK32rr GR32:$src)>;
2499 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2500 (TZMSK64rr GR64:$src)>;
2503 //===----------------------------------------------------------------------===//
2504 // Memory Instructions
2507 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2508 "clflushopt\t$src", []>, PD;
2509 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2510 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2513 //===----------------------------------------------------------------------===//
2515 //===----------------------------------------------------------------------===//
2517 include "X86InstrArithmetic.td"
2518 include "X86InstrCMovSetCC.td"
2519 include "X86InstrExtension.td"
2520 include "X86InstrControl.td"
2521 include "X86InstrShiftRotate.td"
2523 // X87 Floating Point Stack.
2524 include "X86InstrFPStack.td"
2526 // SIMD support (SSE, MMX and AVX)
2527 include "X86InstrFragmentsSIMD.td"
2529 // FMA - Fused Multiply-Add support (requires FMA)
2530 include "X86InstrFMA.td"
2533 include "X86InstrXOP.td"
2535 // SSE, MMX and 3DNow! vector support.
2536 include "X86InstrSSE.td"
2537 include "X86InstrAVX512.td"
2538 include "X86InstrMMX.td"
2539 include "X86Instr3DNow.td"
2542 include "X86InstrMPX.td"
2544 include "X86InstrVMX.td"
2545 include "X86InstrSVM.td"
2547 include "X86InstrTSX.td"
2548 include "X86InstrSGX.td"
2550 // System instructions.
2551 include "X86InstrSystem.td"
2553 // Compiler Pseudo Instructions and Pat Patterns
2554 include "X86InstrCompiler.td"
2556 //===----------------------------------------------------------------------===//
2557 // Assembler Mnemonic Aliases
2558 //===----------------------------------------------------------------------===//
2560 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2561 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2562 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2564 def : MnemonicAlias<"cbw", "cbtw", "att">;
2565 def : MnemonicAlias<"cwde", "cwtl", "att">;
2566 def : MnemonicAlias<"cwd", "cwtd", "att">;
2567 def : MnemonicAlias<"cdq", "cltd", "att">;
2568 def : MnemonicAlias<"cdqe", "cltq", "att">;
2569 def : MnemonicAlias<"cqo", "cqto", "att">;
2571 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2572 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2573 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2575 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2576 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2578 def : MnemonicAlias<"loopz", "loope">;
2579 def : MnemonicAlias<"loopnz", "loopne">;
2581 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2582 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2583 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2584 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2585 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2586 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2587 def : MnemonicAlias<"popfd", "popfl", "att">;
2589 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2590 // all modes. However: "push (addr)" and "push $42" should default to
2591 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2592 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2593 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2594 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2595 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2596 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2597 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2598 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2600 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2601 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2602 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2603 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2604 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2605 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2607 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2608 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2609 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2610 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2612 def : MnemonicAlias<"repe", "rep">;
2613 def : MnemonicAlias<"repz", "rep">;
2614 def : MnemonicAlias<"repnz", "repne">;
2616 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2617 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2618 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2620 def : MnemonicAlias<"sal", "shl", "intel">;
2621 def : MnemonicAlias<"salb", "shlb", "att">;
2622 def : MnemonicAlias<"salw", "shlw", "att">;
2623 def : MnemonicAlias<"sall", "shll", "att">;
2624 def : MnemonicAlias<"salq", "shlq", "att">;
2626 def : MnemonicAlias<"smovb", "movsb", "att">;
2627 def : MnemonicAlias<"smovw", "movsw", "att">;
2628 def : MnemonicAlias<"smovl", "movsl", "att">;
2629 def : MnemonicAlias<"smovq", "movsq", "att">;
2631 def : MnemonicAlias<"ud2a", "ud2", "att">;
2632 def : MnemonicAlias<"verrw", "verr", "att">;
2634 // System instruction aliases.
2635 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2636 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2637 def : MnemonicAlias<"sysret", "sysretl", "att">;
2638 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2640 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2641 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2642 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2643 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2644 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2645 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2646 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2647 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2648 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2649 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2650 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2651 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2654 // Floating point stack aliases.
2655 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2656 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2657 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2658 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2659 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2660 def : MnemonicAlias<"fcomip", "fcompi">;
2661 def : MnemonicAlias<"fildq", "fildll", "att">;
2662 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2663 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2664 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2665 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2666 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2667 def : MnemonicAlias<"fucomip", "fucompi">;
2668 def : MnemonicAlias<"fwait", "wait">;
2670 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2671 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2672 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2673 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2674 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2675 def : MnemonicAlias<"xrstorsq", "xrstors64", "att">;
2676 def : MnemonicAlias<"xsavecq", "xsavec64", "att">;
2677 def : MnemonicAlias<"xsavesq", "xsaves64", "att">;
2679 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2681 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2682 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2684 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2685 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2686 /// example "setz" -> "sete".
2687 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2689 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2690 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2691 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2692 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2693 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2694 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2695 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2696 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2697 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2698 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2700 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2701 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2702 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2703 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2706 // Aliases for set<CC>
2707 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2708 // Aliases for j<CC>
2709 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2710 // Aliases for cmov<CC>{w,l,q}
2711 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2712 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2713 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2714 // No size suffix for intel-style asm.
2715 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2718 //===----------------------------------------------------------------------===//
2719 // Assembler Instruction Aliases
2720 //===----------------------------------------------------------------------===//
2722 // aad/aam default to base 10 if no operand is specified.
2723 def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>;
2724 def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>;
2726 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2727 // Likewise for btc/btr/bts.
2728 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2729 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2730 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2731 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2732 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2733 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2734 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2735 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2738 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2739 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2740 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2741 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2743 // lods aliases. Accept the destination being omitted because it's implicit
2744 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2745 // in the destination.
2746 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2747 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2748 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2749 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2750 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2751 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2752 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2753 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2755 // stos aliases. Accept the source being omitted because it's implicit in
2756 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2758 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2759 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2760 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2761 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2762 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2763 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2764 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2765 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2767 // scas aliases. Accept the destination being omitted because it's implicit
2768 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2769 // in the destination.
2770 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2771 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2772 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2773 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2774 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2775 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2776 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2777 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2779 // div and idiv aliases for explicit A register.
2780 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2781 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2782 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2783 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2784 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2785 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2786 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2787 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2788 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2789 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2790 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2791 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2792 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2793 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2794 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2795 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2799 // Various unary fpstack operations default to operating on on ST1.
2800 // For example, "fxch" -> "fxch %st(1)"
2801 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2802 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
2803 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2804 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2805 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
2806 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2807 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2808 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2809 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2810 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2811 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2812 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2813 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2814 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2815 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2816 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2817 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2819 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2820 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2821 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2823 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2824 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2825 (Inst RST:$op), EmitAlias>;
2826 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2827 (Inst ST0), EmitAlias>;
2830 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2831 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2832 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2833 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2834 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2835 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2836 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2837 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2838 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2839 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2840 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2841 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2842 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2843 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2844 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2845 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2848 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2849 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2850 // solely because gas supports it.
2851 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2852 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2853 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2854 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2855 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2856 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2858 // We accept "fnstsw %eax" even though it only writes %ax.
2859 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2860 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2861 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2863 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2864 // this is compatible with what GAS does.
2865 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2866 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2867 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2868 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2869 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2870 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2871 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2872 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2874 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2875 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2876 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2877 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2878 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2879 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2882 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2883 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2884 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2885 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2886 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2887 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2888 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2890 // inb %dx -> inb %al, %dx
2891 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2892 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2893 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2894 def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>;
2895 def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>;
2896 def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>;
2899 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2900 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2901 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2902 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2903 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2904 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2905 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2906 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2907 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2909 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2910 // the move. All segment/mem forms are equivalent, this has the shortest
2912 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2913 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2915 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2916 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2918 // Match 'movq GR64, MMX' as an alias for movd.
2919 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2920 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2921 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2922 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2925 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2926 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2927 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2928 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2929 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2930 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2931 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2934 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2935 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2936 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2937 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2938 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2939 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2940 // Note: No GR32->GR64 movzx form.
2942 // outb %dx -> outb %al, %dx
2943 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2944 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2945 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2946 def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>;
2947 def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>;
2948 def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>;
2950 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2951 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2952 // errors, since its encoding is the most compact.
2953 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2955 // shld/shrd op,op -> shld op, op, CL
2956 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2957 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2958 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2959 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2960 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2961 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2963 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2964 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2965 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2966 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2967 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2968 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2970 /* FIXME: This is disabled because the asm matcher is currently incapable of
2971 * matching a fixed immediate like $1.
2972 // "shl X, $1" is an alias for "shl X".
2973 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2974 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2975 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2976 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2977 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2978 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2979 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2980 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2981 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2982 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2983 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2984 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2985 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2986 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2987 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2988 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2989 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2992 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2993 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2994 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2995 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2998 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2999 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
3000 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
3001 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
3002 (TEST16rm GR16:$val, i16mem:$mem), 0>;
3003 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
3004 (TEST32rm GR32:$val, i32mem:$mem), 0>;
3005 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
3006 (TEST64rm GR64:$val, i64mem:$mem), 0>;
3008 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
3009 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
3010 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
3011 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
3012 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
3013 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
3014 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
3015 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
3016 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
3018 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
3019 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
3020 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3021 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
3022 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3023 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
3024 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;
3026 // These aliases exist to get the parser to prioritize matching 8-bit
3027 // immediate encodings over matching the implicit ax/eax/rax encodings. By
3028 // explicitly mentioning the A register here, these entries will be ordered
3029 // first due to the more explicit immediate type.
3030 def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>;
3031 def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>;
3032 def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>;
3033 def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>;
3034 def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>;
3035 def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>;
3036 def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>;
3037 def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>;
3039 def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>;
3040 def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>;
3041 def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>;
3042 def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>;
3043 def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>;
3044 def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>;
3045 def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>;
3046 def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>;
3048 def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;
3049 def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;
3050 def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;
3051 def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;
3052 def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>;
3053 def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;
3054 def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;
3055 def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;