1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
44 NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
57 // Select which memory operand is being unfolded.
58 // (stored in bits 0 - 3)
65 // Do not insert the reverse map (MemOp -> RegOp) into the table.
66 // This may be needed because there is a many -> one mapping.
67 TB_NO_REVERSE = 1 << 4,
69 // Do not insert the forward map (RegOp -> MemOp) into the table.
70 // This is needed for Native Client, which prohibits branch
71 // instructions from using a memory operand.
72 TB_NO_FORWARD = 1 << 5,
74 TB_FOLDED_LOAD = 1 << 6,
75 TB_FOLDED_STORE = 1 << 7,
77 // Minimum alignment required for load/store.
78 // Used for RegOp->MemOp conversion.
79 // (stored in bits 8 - 15)
81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
87 struct X86OpTblEntry {
93 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
95 ? X86::ADJCALLSTACKDOWN64
96 : X86::ADJCALLSTACKDOWN32),
97 (tm.getSubtarget<X86Subtarget>().is64Bit()
98 ? X86::ADJCALLSTACKUP64
99 : X86::ADJCALLSTACKUP32)),
100 TM(tm), RI(tm, *this) {
102 static const X86OpTblEntry OpTbl2Addr[] = {
103 { X86::ADC32ri, X86::ADC32mi, 0 },
104 { X86::ADC32ri8, X86::ADC32mi8, 0 },
105 { X86::ADC32rr, X86::ADC32mr, 0 },
106 { X86::ADC64ri32, X86::ADC64mi32, 0 },
107 { X86::ADC64ri8, X86::ADC64mi8, 0 },
108 { X86::ADC64rr, X86::ADC64mr, 0 },
109 { X86::ADD16ri, X86::ADD16mi, 0 },
110 { X86::ADD16ri8, X86::ADD16mi8, 0 },
111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
113 { X86::ADD16rr, X86::ADD16mr, 0 },
114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
115 { X86::ADD32ri, X86::ADD32mi, 0 },
116 { X86::ADD32ri8, X86::ADD32mi8, 0 },
117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
119 { X86::ADD32rr, X86::ADD32mr, 0 },
120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
121 { X86::ADD64ri32, X86::ADD64mi32, 0 },
122 { X86::ADD64ri8, X86::ADD64mi8, 0 },
123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
125 { X86::ADD64rr, X86::ADD64mr, 0 },
126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
127 { X86::ADD8ri, X86::ADD8mi, 0 },
128 { X86::ADD8rr, X86::ADD8mr, 0 },
129 { X86::AND16ri, X86::AND16mi, 0 },
130 { X86::AND16ri8, X86::AND16mi8, 0 },
131 { X86::AND16rr, X86::AND16mr, 0 },
132 { X86::AND32ri, X86::AND32mi, 0 },
133 { X86::AND32ri8, X86::AND32mi8, 0 },
134 { X86::AND32rr, X86::AND32mr, 0 },
135 { X86::AND64ri32, X86::AND64mi32, 0 },
136 { X86::AND64ri8, X86::AND64mi8, 0 },
137 { X86::AND64rr, X86::AND64mr, 0 },
138 { X86::AND8ri, X86::AND8mi, 0 },
139 { X86::AND8rr, X86::AND8mr, 0 },
140 { X86::DEC16r, X86::DEC16m, 0 },
141 { X86::DEC32r, X86::DEC32m, 0 },
142 { X86::DEC64_16r, X86::DEC64_16m, 0 },
143 { X86::DEC64_32r, X86::DEC64_32m, 0 },
144 { X86::DEC64r, X86::DEC64m, 0 },
145 { X86::DEC8r, X86::DEC8m, 0 },
146 { X86::INC16r, X86::INC16m, 0 },
147 { X86::INC32r, X86::INC32m, 0 },
148 { X86::INC64_16r, X86::INC64_16m, 0 },
149 { X86::INC64_32r, X86::INC64_32m, 0 },
150 { X86::INC64r, X86::INC64m, 0 },
151 { X86::INC8r, X86::INC8m, 0 },
152 { X86::NEG16r, X86::NEG16m, 0 },
153 { X86::NEG32r, X86::NEG32m, 0 },
154 { X86::NEG64r, X86::NEG64m, 0 },
155 { X86::NEG8r, X86::NEG8m, 0 },
156 { X86::NOT16r, X86::NOT16m, 0 },
157 { X86::NOT32r, X86::NOT32m, 0 },
158 { X86::NOT64r, X86::NOT64m, 0 },
159 { X86::NOT8r, X86::NOT8m, 0 },
160 { X86::OR16ri, X86::OR16mi, 0 },
161 { X86::OR16ri8, X86::OR16mi8, 0 },
162 { X86::OR16rr, X86::OR16mr, 0 },
163 { X86::OR32ri, X86::OR32mi, 0 },
164 { X86::OR32ri8, X86::OR32mi8, 0 },
165 { X86::OR32rr, X86::OR32mr, 0 },
166 { X86::OR64ri32, X86::OR64mi32, 0 },
167 { X86::OR64ri8, X86::OR64mi8, 0 },
168 { X86::OR64rr, X86::OR64mr, 0 },
169 { X86::OR8ri, X86::OR8mi, 0 },
170 { X86::OR8rr, X86::OR8mr, 0 },
171 { X86::ROL16r1, X86::ROL16m1, 0 },
172 { X86::ROL16rCL, X86::ROL16mCL, 0 },
173 { X86::ROL16ri, X86::ROL16mi, 0 },
174 { X86::ROL32r1, X86::ROL32m1, 0 },
175 { X86::ROL32rCL, X86::ROL32mCL, 0 },
176 { X86::ROL32ri, X86::ROL32mi, 0 },
177 { X86::ROL64r1, X86::ROL64m1, 0 },
178 { X86::ROL64rCL, X86::ROL64mCL, 0 },
179 { X86::ROL64ri, X86::ROL64mi, 0 },
180 { X86::ROL8r1, X86::ROL8m1, 0 },
181 { X86::ROL8rCL, X86::ROL8mCL, 0 },
182 { X86::ROL8ri, X86::ROL8mi, 0 },
183 { X86::ROR16r1, X86::ROR16m1, 0 },
184 { X86::ROR16rCL, X86::ROR16mCL, 0 },
185 { X86::ROR16ri, X86::ROR16mi, 0 },
186 { X86::ROR32r1, X86::ROR32m1, 0 },
187 { X86::ROR32rCL, X86::ROR32mCL, 0 },
188 { X86::ROR32ri, X86::ROR32mi, 0 },
189 { X86::ROR64r1, X86::ROR64m1, 0 },
190 { X86::ROR64rCL, X86::ROR64mCL, 0 },
191 { X86::ROR64ri, X86::ROR64mi, 0 },
192 { X86::ROR8r1, X86::ROR8m1, 0 },
193 { X86::ROR8rCL, X86::ROR8mCL, 0 },
194 { X86::ROR8ri, X86::ROR8mi, 0 },
195 { X86::SAR16r1, X86::SAR16m1, 0 },
196 { X86::SAR16rCL, X86::SAR16mCL, 0 },
197 { X86::SAR16ri, X86::SAR16mi, 0 },
198 { X86::SAR32r1, X86::SAR32m1, 0 },
199 { X86::SAR32rCL, X86::SAR32mCL, 0 },
200 { X86::SAR32ri, X86::SAR32mi, 0 },
201 { X86::SAR64r1, X86::SAR64m1, 0 },
202 { X86::SAR64rCL, X86::SAR64mCL, 0 },
203 { X86::SAR64ri, X86::SAR64mi, 0 },
204 { X86::SAR8r1, X86::SAR8m1, 0 },
205 { X86::SAR8rCL, X86::SAR8mCL, 0 },
206 { X86::SAR8ri, X86::SAR8mi, 0 },
207 { X86::SBB32ri, X86::SBB32mi, 0 },
208 { X86::SBB32ri8, X86::SBB32mi8, 0 },
209 { X86::SBB32rr, X86::SBB32mr, 0 },
210 { X86::SBB64ri32, X86::SBB64mi32, 0 },
211 { X86::SBB64ri8, X86::SBB64mi8, 0 },
212 { X86::SBB64rr, X86::SBB64mr, 0 },
213 { X86::SHL16rCL, X86::SHL16mCL, 0 },
214 { X86::SHL16ri, X86::SHL16mi, 0 },
215 { X86::SHL32rCL, X86::SHL32mCL, 0 },
216 { X86::SHL32ri, X86::SHL32mi, 0 },
217 { X86::SHL64rCL, X86::SHL64mCL, 0 },
218 { X86::SHL64ri, X86::SHL64mi, 0 },
219 { X86::SHL8rCL, X86::SHL8mCL, 0 },
220 { X86::SHL8ri, X86::SHL8mi, 0 },
221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
227 { X86::SHR16r1, X86::SHR16m1, 0 },
228 { X86::SHR16rCL, X86::SHR16mCL, 0 },
229 { X86::SHR16ri, X86::SHR16mi, 0 },
230 { X86::SHR32r1, X86::SHR32m1, 0 },
231 { X86::SHR32rCL, X86::SHR32mCL, 0 },
232 { X86::SHR32ri, X86::SHR32mi, 0 },
233 { X86::SHR64r1, X86::SHR64m1, 0 },
234 { X86::SHR64rCL, X86::SHR64mCL, 0 },
235 { X86::SHR64ri, X86::SHR64mi, 0 },
236 { X86::SHR8r1, X86::SHR8m1, 0 },
237 { X86::SHR8rCL, X86::SHR8mCL, 0 },
238 { X86::SHR8ri, X86::SHR8mi, 0 },
239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
245 { X86::SUB16ri, X86::SUB16mi, 0 },
246 { X86::SUB16ri8, X86::SUB16mi8, 0 },
247 { X86::SUB16rr, X86::SUB16mr, 0 },
248 { X86::SUB32ri, X86::SUB32mi, 0 },
249 { X86::SUB32ri8, X86::SUB32mi8, 0 },
250 { X86::SUB32rr, X86::SUB32mr, 0 },
251 { X86::SUB64ri32, X86::SUB64mi32, 0 },
252 { X86::SUB64ri8, X86::SUB64mi8, 0 },
253 { X86::SUB64rr, X86::SUB64mr, 0 },
254 { X86::SUB8ri, X86::SUB8mi, 0 },
255 { X86::SUB8rr, X86::SUB8mr, 0 },
256 { X86::XOR16ri, X86::XOR16mi, 0 },
257 { X86::XOR16ri8, X86::XOR16mi8, 0 },
258 { X86::XOR16rr, X86::XOR16mr, 0 },
259 { X86::XOR32ri, X86::XOR32mi, 0 },
260 { X86::XOR32ri8, X86::XOR32mi8, 0 },
261 { X86::XOR32rr, X86::XOR32mr, 0 },
262 { X86::XOR64ri32, X86::XOR64mi32, 0 },
263 { X86::XOR64ri8, X86::XOR64mi8, 0 },
264 { X86::XOR64rr, X86::XOR64mr, 0 },
265 { X86::XOR8ri, X86::XOR8mi, 0 },
266 { X86::XOR8rr, X86::XOR8mr, 0 }
269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
270 unsigned RegOp = OpTbl2Addr[i].RegOp;
271 unsigned MemOp = OpTbl2Addr[i].MemOp;
272 unsigned Flags = OpTbl2Addr[i].Flags;
273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
275 // Index 0, folded load and store, no alignment requirement.
276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
279 static const X86OpTblEntry OpTbl0[] = {
280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
357 // AVX 128-bit versions of foldable instructions
358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
371 // AVX 256-bit foldable instructions
372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
381 unsigned RegOp = OpTbl0[i].RegOp;
382 unsigned MemOp = OpTbl0[i].MemOp;
383 unsigned Flags = OpTbl0[i].Flags;
384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385 RegOp, MemOp, TB_INDEX_0 | Flags);
388 static const X86OpTblEntry OpTbl1[] = {
389 { X86::CMP16rr, X86::CMP16rm, 0 },
390 { X86::CMP32rr, X86::CMP32rm, 0 },
391 { X86::CMP64rr, X86::CMP64rm, 0 },
392 { X86::CMP8rr, X86::CMP8rm, 0 },
393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
405 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
407 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
417 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
418 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
419 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
420 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
421 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
422 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
423 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
424 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
425 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
426 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
427 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
428 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
429 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
430 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
431 { X86::MOV16rr, X86::MOV16rm, 0 },
432 { X86::MOV32rr, X86::MOV32rm, 0 },
433 { X86::MOV64rr, X86::MOV64rm, 0 },
434 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
435 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
436 { X86::MOV8rr, X86::MOV8rm, 0 },
437 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
438 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
439 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
440 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
441 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
442 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
443 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
444 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
445 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
446 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
447 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
448 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
449 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
450 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
451 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
452 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
453 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
454 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
455 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
456 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
457 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
458 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
459 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
460 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
461 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
462 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
463 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
464 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
465 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
466 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
467 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
468 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
469 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
470 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
471 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
472 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
473 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
474 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
475 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
476 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
477 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
478 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
479 { X86::SQRTSDr, X86::SQRTSDm, 0 },
480 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
481 { X86::SQRTSSr, X86::SQRTSSm, 0 },
482 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
483 { X86::TEST16rr, X86::TEST16rm, 0 },
484 { X86::TEST32rr, X86::TEST32rm, 0 },
485 { X86::TEST64rr, X86::TEST64rm, 0 },
486 { X86::TEST8rr, X86::TEST8rm, 0 },
487 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
488 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
489 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
490 // AVX 128-bit versions of foldable instructions
491 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
492 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
493 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
494 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
495 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
496 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
497 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
498 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
499 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
500 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
501 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
502 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
503 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
504 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
505 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
506 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
507 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
508 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
509 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
510 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
511 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
512 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
513 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
514 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
515 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
516 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
517 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
518 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
519 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
520 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
521 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
522 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
523 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
524 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
525 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
526 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
527 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 },
528 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 },
529 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
530 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
531 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
532 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
533 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
534 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
535 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
536 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
537 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
538 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
539 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
540 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
541 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
542 // AVX 256-bit foldable instructions
543 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
544 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
545 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
546 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
547 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
548 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 },
549 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 },
550 // AVX2 foldable instructions
551 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 },
552 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 },
553 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 },
554 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 },
555 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 },
556 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 },
557 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 },
558 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 },
559 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 },
560 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 },
561 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 },
562 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 },
563 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 },
564 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 },
567 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
568 unsigned RegOp = OpTbl1[i].RegOp;
569 unsigned MemOp = OpTbl1[i].MemOp;
570 unsigned Flags = OpTbl1[i].Flags;
571 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
573 // Index 1, folded load
574 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
577 static const X86OpTblEntry OpTbl2[] = {
578 { X86::ADC32rr, X86::ADC32rm, 0 },
579 { X86::ADC64rr, X86::ADC64rm, 0 },
580 { X86::ADD16rr, X86::ADD16rm, 0 },
581 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
582 { X86::ADD32rr, X86::ADD32rm, 0 },
583 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
584 { X86::ADD64rr, X86::ADD64rm, 0 },
585 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
586 { X86::ADD8rr, X86::ADD8rm, 0 },
587 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
588 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
589 { X86::ADDSDrr, X86::ADDSDrm, 0 },
590 { X86::ADDSSrr, X86::ADDSSrm, 0 },
591 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
592 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
593 { X86::AND16rr, X86::AND16rm, 0 },
594 { X86::AND32rr, X86::AND32rm, 0 },
595 { X86::AND64rr, X86::AND64rm, 0 },
596 { X86::AND8rr, X86::AND8rm, 0 },
597 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
598 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
599 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
600 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
601 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
602 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
603 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
604 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
605 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
606 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
607 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
608 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
609 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
610 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
611 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
612 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
613 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
614 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
615 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
616 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
617 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
618 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
619 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
620 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
621 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
622 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
623 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
624 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
625 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
626 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
627 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
628 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
629 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
630 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
631 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
632 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
633 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
634 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
635 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
636 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
637 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
638 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
639 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
640 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
641 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
642 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
643 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
644 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
645 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
646 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
647 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
648 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
649 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
650 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
651 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
652 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
653 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
654 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
655 { X86::CMPSDrr, X86::CMPSDrm, 0 },
656 { X86::CMPSSrr, X86::CMPSSrm, 0 },
657 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
658 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
659 { X86::DIVSDrr, X86::DIVSDrm, 0 },
660 { X86::DIVSSrr, X86::DIVSSrm, 0 },
661 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
662 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
663 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
664 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
665 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
666 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
667 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
668 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
669 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
670 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
671 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
672 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
673 { X86::IMUL16rr, X86::IMUL16rm, 0 },
674 { X86::IMUL32rr, X86::IMUL32rm, 0 },
675 { X86::IMUL64rr, X86::IMUL64rm, 0 },
676 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
677 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
678 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
679 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
680 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
681 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
682 { X86::MAXSDrr, X86::MAXSDrm, 0 },
683 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
684 { X86::MAXSSrr, X86::MAXSSrm, 0 },
685 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
686 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
687 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
688 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
689 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
690 { X86::MINSDrr, X86::MINSDrm, 0 },
691 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
692 { X86::MINSSrr, X86::MINSSrm, 0 },
693 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
694 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
695 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
696 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
697 { X86::MULSDrr, X86::MULSDrm, 0 },
698 { X86::MULSSrr, X86::MULSSrm, 0 },
699 { X86::OR16rr, X86::OR16rm, 0 },
700 { X86::OR32rr, X86::OR32rm, 0 },
701 { X86::OR64rr, X86::OR64rm, 0 },
702 { X86::OR8rr, X86::OR8rm, 0 },
703 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
704 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
705 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
706 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
707 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
708 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
709 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
710 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
711 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
712 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
713 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
714 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
715 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
716 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
717 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
718 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
719 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
720 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
721 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
722 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
723 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
724 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
725 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
726 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
727 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
728 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
729 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
730 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
731 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
732 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
733 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
734 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
735 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
736 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
737 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
738 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
739 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
740 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
741 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
742 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
743 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
744 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
745 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
746 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
747 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
748 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
749 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
750 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
751 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
752 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
753 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
754 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
755 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
756 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
757 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
758 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
759 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
760 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
761 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
762 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
763 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
764 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
765 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
766 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
767 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
768 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
769 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
770 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
771 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
772 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
773 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
774 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
775 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
776 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
777 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
778 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
779 { X86::SBB32rr, X86::SBB32rm, 0 },
780 { X86::SBB64rr, X86::SBB64rm, 0 },
781 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
782 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
783 { X86::SUB16rr, X86::SUB16rm, 0 },
784 { X86::SUB32rr, X86::SUB32rm, 0 },
785 { X86::SUB64rr, X86::SUB64rm, 0 },
786 { X86::SUB8rr, X86::SUB8rm, 0 },
787 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
788 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
789 { X86::SUBSDrr, X86::SUBSDrm, 0 },
790 { X86::SUBSSrr, X86::SUBSSrm, 0 },
791 // FIXME: TEST*rr -> swapped operand of TEST*mr.
792 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
793 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
794 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
795 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
796 { X86::XOR16rr, X86::XOR16rm, 0 },
797 { X86::XOR32rr, X86::XOR32rm, 0 },
798 { X86::XOR64rr, X86::XOR64rm, 0 },
799 { X86::XOR8rr, X86::XOR8rm, 0 },
800 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
801 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
802 // AVX 128-bit versions of foldable instructions
803 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
804 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
805 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
806 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
807 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
808 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
809 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
810 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
811 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
812 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
813 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
814 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
815 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, TB_ALIGN_16 },
816 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
817 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
818 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
819 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
820 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
821 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
822 { X86::VADDSDrr, X86::VADDSDrm, 0 },
823 { X86::VADDSSrr, X86::VADDSSrm, 0 },
824 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
825 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
826 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
827 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
828 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
829 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
830 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 },
831 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 },
832 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 },
833 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 },
834 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
835 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
836 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
837 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
838 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
839 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
840 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
841 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
842 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
843 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
844 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
845 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
846 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
847 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
848 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
849 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
850 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
851 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
852 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
853 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
854 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
855 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
856 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
857 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
858 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
859 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
860 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
861 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
862 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
863 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
864 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
865 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
866 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
867 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
868 { X86::VMINSDrr, X86::VMINSDrm, 0 },
869 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
870 { X86::VMINSSrr, X86::VMINSSrm, 0 },
871 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
872 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
873 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
874 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
875 { X86::VMULSDrr, X86::VMULSDrm, 0 },
876 { X86::VMULSSrr, X86::VMULSSrm, 0 },
877 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
878 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
879 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
880 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
881 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
882 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
883 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
884 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
885 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
886 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
887 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
888 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
889 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
890 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
891 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
892 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
893 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
894 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
895 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
896 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 },
897 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
898 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
899 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
900 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
901 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
902 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
903 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
904 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
905 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 },
906 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
907 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 },
908 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 },
909 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
910 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 },
911 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 },
912 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 },
913 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
914 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
915 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
916 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
917 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
918 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
919 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
920 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
921 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
922 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
923 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
924 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
925 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
926 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
927 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
928 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
929 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 },
930 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 },
931 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 },
932 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 },
933 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
934 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
935 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
936 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
937 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
938 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
939 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
940 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
941 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
942 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
943 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
944 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
945 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
946 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
947 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
948 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
949 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
950 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
951 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
952 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
953 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
954 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
955 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
956 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
957 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
958 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
959 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
960 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
961 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
962 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
963 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
964 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
965 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
966 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
967 // AVX 256-bit foldable instructions
968 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 },
969 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 },
970 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 },
971 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 },
972 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 },
973 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 },
974 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 },
975 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 },
976 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 },
977 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 },
978 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 },
979 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 },
980 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 },
981 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 },
982 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 },
983 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 },
984 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 },
985 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 },
986 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 },
987 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 },
988 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 },
989 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 },
990 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 },
991 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 },
992 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 },
993 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 },
994 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 },
995 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 },
996 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 },
997 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 },
998 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 },
999 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 },
1000 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 },
1001 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 },
1002 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 },
1003 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 },
1004 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 },
1005 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 },
1006 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 },
1007 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 },
1008 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 },
1009 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 },
1010 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 },
1011 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 },
1012 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 },
1013 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 },
1014 // AVX2 foldable instructions
1015 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 },
1016 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 },
1017 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 },
1018 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 },
1019 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 },
1020 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 },
1021 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 },
1022 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 },
1023 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 },
1024 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 },
1025 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 },
1026 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 },
1027 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 },
1028 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 },
1029 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 },
1030 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 },
1031 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 },
1032 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 },
1033 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 },
1034 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 },
1035 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 },
1036 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 },
1037 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 },
1038 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 },
1039 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 },
1040 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 },
1041 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 },
1042 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 },
1043 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 },
1044 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 },
1045 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 },
1046 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 },
1047 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 },
1048 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 },
1049 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 },
1050 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 },
1051 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 },
1052 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 },
1053 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 },
1054 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 },
1055 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 },
1056 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 },
1057 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 },
1058 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 },
1059 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 },
1060 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 },
1061 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 },
1062 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 },
1063 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 },
1064 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 },
1065 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 },
1066 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 },
1067 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 },
1068 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
1069 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
1070 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
1071 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 },
1072 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 },
1073 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 },
1074 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 },
1075 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
1076 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
1077 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
1078 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
1079 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 },
1080 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
1081 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 },
1082 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1083 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1084 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
1085 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 },
1086 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1087 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1088 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1089 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
1090 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 },
1091 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
1092 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 },
1093 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 },
1094 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 },
1095 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 },
1096 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 },
1097 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 },
1098 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 },
1099 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 },
1100 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
1101 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 },
1102 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 },
1103 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 },
1104 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 },
1105 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 },
1106 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 },
1107 // FIXME: add AVX 256-bit foldable instructions
1110 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1111 unsigned RegOp = OpTbl2[i].RegOp;
1112 unsigned MemOp = OpTbl2[i].MemOp;
1113 unsigned Flags = OpTbl2[i].Flags;
1114 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1116 // Index 2, folded load
1117 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1120 static const X86OpTblEntry OpTbl3[] = {
1121 // FMA foldable instructions
1122 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 },
1123 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 },
1124 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 },
1125 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 },
1126 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 },
1127 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 },
1128 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, 0 },
1129 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, 0 },
1131 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 },
1132 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 },
1133 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 },
1134 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 },
1135 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 },
1136 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 },
1137 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 },
1138 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 },
1139 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 },
1140 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
1141 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
1142 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
1143 { X86::VFMADDPSr132r_Int, X86::VFMADDPSr132m_Int, TB_ALIGN_16 },
1144 { X86::VFMADDPDr132r_Int, X86::VFMADDPDr132m_Int, TB_ALIGN_16 },
1145 { X86::VFMADDPSr132rY_Int, X86::VFMADDPSr132mY_Int, TB_ALIGN_32 },
1146 { X86::VFMADDPDr132rY_Int, X86::VFMADDPDr132mY_Int, TB_ALIGN_32 },
1148 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
1149 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
1150 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 },
1151 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 },
1152 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 },
1153 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 },
1154 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, 0 },
1155 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, 0 },
1157 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 },
1158 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 },
1159 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 },
1160 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 },
1161 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 },
1162 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 },
1163 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 },
1164 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 },
1165 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 },
1166 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
1167 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
1168 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
1169 { X86::VFNMADDPSr132r_Int, X86::VFNMADDPSr132m_Int, TB_ALIGN_16 },
1170 { X86::VFNMADDPDr132r_Int, X86::VFNMADDPDr132m_Int, TB_ALIGN_16 },
1171 { X86::VFNMADDPSr132rY_Int, X86::VFNMADDPSr132mY_Int, TB_ALIGN_32 },
1172 { X86::VFNMADDPDr132rY_Int, X86::VFNMADDPDr132mY_Int, TB_ALIGN_32 },
1174 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
1175 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
1176 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 },
1177 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 },
1178 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 },
1179 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 },
1180 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, 0 },
1181 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, 0 },
1183 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 },
1184 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 },
1185 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 },
1186 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 },
1187 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 },
1188 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 },
1189 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 },
1190 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 },
1191 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 },
1192 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
1193 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
1194 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
1195 { X86::VFMSUBPSr132r_Int, X86::VFMSUBPSr132m_Int, TB_ALIGN_16 },
1196 { X86::VFMSUBPDr132r_Int, X86::VFMSUBPDr132m_Int, TB_ALIGN_16 },
1197 { X86::VFMSUBPSr132rY_Int, X86::VFMSUBPSr132mY_Int, TB_ALIGN_32 },
1198 { X86::VFMSUBPDr132rY_Int, X86::VFMSUBPDr132mY_Int, TB_ALIGN_32 },
1200 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 },
1201 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 },
1202 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 },
1203 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 },
1204 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 },
1205 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 },
1206 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, 0 },
1207 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, 0 },
1209 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 },
1210 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 },
1211 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 },
1212 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 },
1213 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 },
1214 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 },
1215 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 },
1216 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 },
1217 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 },
1218 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 },
1219 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 },
1220 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 },
1221 { X86::VFNMSUBPSr132r_Int, X86::VFNMSUBPSr132m_Int, TB_ALIGN_16 },
1222 { X86::VFNMSUBPDr132r_Int, X86::VFNMSUBPDr132m_Int, TB_ALIGN_16 },
1223 { X86::VFNMSUBPSr132rY_Int, X86::VFNMSUBPSr132mY_Int, TB_ALIGN_32 },
1224 { X86::VFNMSUBPDr132rY_Int, X86::VFNMSUBPDr132mY_Int, TB_ALIGN_32 },
1226 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 },
1227 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 },
1228 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 },
1229 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 },
1230 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 },
1231 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 },
1232 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 },
1233 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 },
1234 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 },
1235 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 },
1236 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 },
1237 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 },
1238 { X86::VFMADDSUBPSr132r_Int, X86::VFMADDSUBPSr132m_Int, TB_ALIGN_16 },
1239 { X86::VFMADDSUBPDr132r_Int, X86::VFMADDSUBPDr132m_Int, TB_ALIGN_16 },
1240 { X86::VFMADDSUBPSr132rY_Int, X86::VFMADDSUBPSr132mY_Int, TB_ALIGN_32 },
1241 { X86::VFMADDSUBPDr132rY_Int, X86::VFMADDSUBPDr132mY_Int, TB_ALIGN_32 },
1243 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 },
1244 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 },
1245 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 },
1246 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 },
1247 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 },
1248 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 },
1249 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 },
1250 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 },
1251 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 },
1252 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 },
1253 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 },
1254 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 },
1255 { X86::VFMSUBADDPSr132r_Int, X86::VFMSUBADDPSr132m_Int, TB_ALIGN_16 },
1256 { X86::VFMSUBADDPDr132r_Int, X86::VFMSUBADDPDr132m_Int, TB_ALIGN_16 },
1257 { X86::VFMSUBADDPSr132rY_Int, X86::VFMSUBADDPSr132mY_Int, TB_ALIGN_32 },
1258 { X86::VFMSUBADDPDr132rY_Int, X86::VFMSUBADDPDr132mY_Int, TB_ALIGN_32 },
1261 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1262 unsigned RegOp = OpTbl3[i].RegOp;
1263 unsigned MemOp = OpTbl3[i].MemOp;
1264 unsigned Flags = OpTbl3[i].Flags;
1265 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1267 // Index 3, folded load
1268 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1274 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1275 MemOp2RegOpTableType &M2RTable,
1276 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1277 if ((Flags & TB_NO_FORWARD) == 0) {
1278 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1279 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1281 if ((Flags & TB_NO_REVERSE) == 0) {
1282 assert(!M2RTable.count(MemOp) &&
1283 "Duplicated entries in unfolding maps?");
1284 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1289 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1290 unsigned &SrcReg, unsigned &DstReg,
1291 unsigned &SubIdx) const {
1292 switch (MI.getOpcode()) {
1294 case X86::MOVSX16rr8:
1295 case X86::MOVZX16rr8:
1296 case X86::MOVSX32rr8:
1297 case X86::MOVZX32rr8:
1298 case X86::MOVSX64rr8:
1299 case X86::MOVZX64rr8:
1300 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1301 // It's not always legal to reference the low 8-bit of the larger
1302 // register in 32-bit mode.
1304 case X86::MOVSX32rr16:
1305 case X86::MOVZX32rr16:
1306 case X86::MOVSX64rr16:
1307 case X86::MOVZX64rr16:
1308 case X86::MOVSX64rr32:
1309 case X86::MOVZX64rr32: {
1310 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1313 SrcReg = MI.getOperand(1).getReg();
1314 DstReg = MI.getOperand(0).getReg();
1315 switch (MI.getOpcode()) {
1317 llvm_unreachable(0);
1318 case X86::MOVSX16rr8:
1319 case X86::MOVZX16rr8:
1320 case X86::MOVSX32rr8:
1321 case X86::MOVZX32rr8:
1322 case X86::MOVSX64rr8:
1323 case X86::MOVZX64rr8:
1324 SubIdx = X86::sub_8bit;
1326 case X86::MOVSX32rr16:
1327 case X86::MOVZX32rr16:
1328 case X86::MOVSX64rr16:
1329 case X86::MOVZX64rr16:
1330 SubIdx = X86::sub_16bit;
1332 case X86::MOVSX64rr32:
1333 case X86::MOVZX64rr32:
1334 SubIdx = X86::sub_32bit;
1343 /// isFrameOperand - Return true and the FrameIndex if the specified
1344 /// operand and follow operands form a reference to the stack frame.
1345 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1346 int &FrameIndex) const {
1347 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1348 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1349 MI->getOperand(Op+1).getImm() == 1 &&
1350 MI->getOperand(Op+2).getReg() == 0 &&
1351 MI->getOperand(Op+3).getImm() == 0) {
1352 FrameIndex = MI->getOperand(Op).getIndex();
1358 static bool isFrameLoadOpcode(int Opcode) {
1374 case X86::VMOVAPSrm:
1375 case X86::VMOVAPDrm:
1376 case X86::VMOVDQArm:
1377 case X86::VMOVAPSYrm:
1378 case X86::VMOVAPDYrm:
1379 case X86::VMOVDQAYrm:
1380 case X86::MMX_MOVD64rm:
1381 case X86::MMX_MOVQ64rm:
1386 static bool isFrameStoreOpcode(int Opcode) {
1393 case X86::ST_FpP64m:
1401 case X86::VMOVAPSmr:
1402 case X86::VMOVAPDmr:
1403 case X86::VMOVDQAmr:
1404 case X86::VMOVAPSYmr:
1405 case X86::VMOVAPDYmr:
1406 case X86::VMOVDQAYmr:
1407 case X86::MMX_MOVD64mr:
1408 case X86::MMX_MOVQ64mr:
1409 case X86::MMX_MOVNTQmr:
1415 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1416 int &FrameIndex) const {
1417 if (isFrameLoadOpcode(MI->getOpcode()))
1418 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1419 return MI->getOperand(0).getReg();
1423 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1424 int &FrameIndex) const {
1425 if (isFrameLoadOpcode(MI->getOpcode())) {
1427 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1429 // Check for post-frame index elimination operations
1430 const MachineMemOperand *Dummy;
1431 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1437 int &FrameIndex) const {
1438 if (isFrameStoreOpcode(MI->getOpcode()))
1439 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1440 isFrameOperand(MI, 0, FrameIndex))
1441 return MI->getOperand(X86::AddrNumOperands).getReg();
1445 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1446 int &FrameIndex) const {
1447 if (isFrameStoreOpcode(MI->getOpcode())) {
1449 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1451 // Check for post-frame index elimination operations
1452 const MachineMemOperand *Dummy;
1453 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1458 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1460 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1461 bool isPICBase = false;
1462 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1463 E = MRI.def_end(); I != E; ++I) {
1464 MachineInstr *DefMI = I.getOperand().getParent();
1465 if (DefMI->getOpcode() != X86::MOVPC32r)
1467 assert(!isPICBase && "More than one PIC base?");
1474 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1475 AliasAnalysis *AA) const {
1476 switch (MI->getOpcode()) {
1491 case X86::VMOVAPSrm:
1492 case X86::VMOVUPSrm:
1493 case X86::VMOVAPDrm:
1494 case X86::VMOVDQArm:
1495 case X86::VMOVAPSYrm:
1496 case X86::VMOVUPSYrm:
1497 case X86::VMOVAPDYrm:
1498 case X86::VMOVDQAYrm:
1499 case X86::MMX_MOVD64rm:
1500 case X86::MMX_MOVQ64rm:
1501 case X86::FsVMOVAPSrm:
1502 case X86::FsVMOVAPDrm:
1503 case X86::FsMOVAPSrm:
1504 case X86::FsMOVAPDrm: {
1505 // Loads from constant pools are trivially rematerializable.
1506 if (MI->getOperand(1).isReg() &&
1507 MI->getOperand(2).isImm() &&
1508 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1509 MI->isInvariantLoad(AA)) {
1510 unsigned BaseReg = MI->getOperand(1).getReg();
1511 if (BaseReg == 0 || BaseReg == X86::RIP)
1513 // Allow re-materialization of PIC load.
1514 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1516 const MachineFunction &MF = *MI->getParent()->getParent();
1517 const MachineRegisterInfo &MRI = MF.getRegInfo();
1518 bool isPICBase = false;
1519 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1520 E = MRI.def_end(); I != E; ++I) {
1521 MachineInstr *DefMI = I.getOperand().getParent();
1522 if (DefMI->getOpcode() != X86::MOVPC32r)
1524 assert(!isPICBase && "More than one PIC base?");
1534 if (MI->getOperand(2).isImm() &&
1535 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1536 !MI->getOperand(4).isReg()) {
1537 // lea fi#, lea GV, etc. are all rematerializable.
1538 if (!MI->getOperand(1).isReg())
1540 unsigned BaseReg = MI->getOperand(1).getReg();
1543 // Allow re-materialization of lea PICBase + x.
1544 const MachineFunction &MF = *MI->getParent()->getParent();
1545 const MachineRegisterInfo &MRI = MF.getRegInfo();
1546 return regIsPICBase(BaseReg, MRI);
1552 // All other instructions marked M_REMATERIALIZABLE are always trivially
1553 // rematerializable.
1557 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1558 /// would clobber the EFLAGS condition register. Note the result may be
1559 /// conservative. If it cannot definitely determine the safety after visiting
1560 /// a few instructions in each direction it assumes it's not safe.
1561 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1562 MachineBasicBlock::iterator I) {
1563 MachineBasicBlock::iterator E = MBB.end();
1565 // For compile time consideration, if we are not able to determine the
1566 // safety after visiting 4 instructions in each direction, we will assume
1568 MachineBasicBlock::iterator Iter = I;
1569 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1570 bool SeenDef = false;
1571 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1572 MachineOperand &MO = Iter->getOperand(j);
1573 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1577 if (MO.getReg() == X86::EFLAGS) {
1585 // This instruction defines EFLAGS, no need to look any further.
1588 // Skip over DBG_VALUE.
1589 while (Iter != E && Iter->isDebugValue())
1593 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1596 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1597 SE = MBB.succ_end(); SI != SE; ++SI)
1598 if ((*SI)->isLiveIn(X86::EFLAGS))
1603 MachineBasicBlock::iterator B = MBB.begin();
1605 for (unsigned i = 0; i < 4; ++i) {
1606 // If we make it to the beginning of the block, it's safe to clobber
1607 // EFLAGS iff EFLAGS is not live-in.
1609 return !MBB.isLiveIn(X86::EFLAGS);
1612 // Skip over DBG_VALUE.
1613 while (Iter != B && Iter->isDebugValue())
1616 bool SawKill = false;
1617 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1618 MachineOperand &MO = Iter->getOperand(j);
1619 // A register mask may clobber EFLAGS, but we should still look for a
1621 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1623 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1624 if (MO.isDef()) return MO.isDead();
1625 if (MO.isKill()) SawKill = true;
1630 // This instruction kills EFLAGS and doesn't redefine it, so
1631 // there's no need to look further.
1635 // Conservative answer.
1639 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1640 MachineBasicBlock::iterator I,
1641 unsigned DestReg, unsigned SubIdx,
1642 const MachineInstr *Orig,
1643 const TargetRegisterInfo &TRI) const {
1644 DebugLoc DL = Orig->getDebugLoc();
1646 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1647 // Re-materialize them as movri instructions to avoid side effects.
1649 unsigned Opc = Orig->getOpcode();
1655 case X86::MOV64r0: {
1656 if (!isSafeToClobberEFLAGS(MBB, I)) {
1659 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1660 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1661 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1662 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1671 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1674 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1677 MachineInstr *NewMI = prior(I);
1678 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1681 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1682 /// is not marked dead.
1683 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1684 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1685 MachineOperand &MO = MI->getOperand(i);
1686 if (MO.isReg() && MO.isDef() &&
1687 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1694 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1695 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1696 /// to a 32-bit superregister and then truncating back down to a 16-bit
1699 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1700 MachineFunction::iterator &MFI,
1701 MachineBasicBlock::iterator &MBBI,
1702 LiveVariables *LV) const {
1703 MachineInstr *MI = MBBI;
1704 unsigned Dest = MI->getOperand(0).getReg();
1705 unsigned Src = MI->getOperand(1).getReg();
1706 bool isDead = MI->getOperand(0).isDead();
1707 bool isKill = MI->getOperand(1).isKill();
1709 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1710 ? X86::LEA64_32r : X86::LEA32r;
1711 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1712 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1713 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1715 // Build and insert into an implicit UNDEF value. This is OK because
1716 // well be shifting and then extracting the lower 16-bits.
1717 // This has the potential to cause partial register stall. e.g.
1718 // movw (%rbp,%rcx,2), %dx
1719 // leal -65(%rdx), %esi
1720 // But testing has shown this *does* help performance in 64-bit mode (at
1721 // least on modern x86 machines).
1722 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1723 MachineInstr *InsMI =
1724 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1725 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1726 .addReg(Src, getKillRegState(isKill));
1728 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1729 get(Opc), leaOutReg);
1732 llvm_unreachable(0);
1733 case X86::SHL16ri: {
1734 unsigned ShAmt = MI->getOperand(2).getImm();
1735 MIB.addReg(0).addImm(1 << ShAmt)
1736 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1740 case X86::INC64_16r:
1741 addRegOffset(MIB, leaInReg, true, 1);
1744 case X86::DEC64_16r:
1745 addRegOffset(MIB, leaInReg, true, -1);
1749 case X86::ADD16ri_DB:
1750 case X86::ADD16ri8_DB:
1751 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1754 case X86::ADD16rr_DB: {
1755 unsigned Src2 = MI->getOperand(2).getReg();
1756 bool isKill2 = MI->getOperand(2).isKill();
1757 unsigned leaInReg2 = 0;
1758 MachineInstr *InsMI2 = 0;
1760 // ADD16rr %reg1028<kill>, %reg1028
1761 // just a single insert_subreg.
1762 addRegReg(MIB, leaInReg, true, leaInReg, false);
1764 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1765 // Build and insert into an implicit UNDEF value. This is OK because
1766 // well be shifting and then extracting the lower 16-bits.
1767 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1769 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1770 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1771 .addReg(Src2, getKillRegState(isKill2));
1772 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1774 if (LV && isKill2 && InsMI2)
1775 LV->replaceKillInstruction(Src2, MI, InsMI2);
1780 MachineInstr *NewMI = MIB;
1781 MachineInstr *ExtMI =
1782 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1783 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1784 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1787 // Update live variables
1788 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1789 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1791 LV->replaceKillInstruction(Src, MI, InsMI);
1793 LV->replaceKillInstruction(Dest, MI, ExtMI);
1799 /// convertToThreeAddress - This method must be implemented by targets that
1800 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1801 /// may be able to convert a two-address instruction into a true
1802 /// three-address instruction on demand. This allows the X86 target (for
1803 /// example) to convert ADD and SHL instructions into LEA instructions if they
1804 /// would require register copies due to two-addressness.
1806 /// This method returns a null pointer if the transformation cannot be
1807 /// performed, otherwise it returns the new instruction.
1810 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1811 MachineBasicBlock::iterator &MBBI,
1812 LiveVariables *LV) const {
1813 MachineInstr *MI = MBBI;
1814 MachineFunction &MF = *MI->getParent()->getParent();
1815 // All instructions input are two-addr instructions. Get the known operands.
1816 unsigned Dest = MI->getOperand(0).getReg();
1817 unsigned Src = MI->getOperand(1).getReg();
1818 bool isDead = MI->getOperand(0).isDead();
1819 bool isKill = MI->getOperand(1).isKill();
1821 MachineInstr *NewMI = NULL;
1822 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1823 // we have better subtarget support, enable the 16-bit LEA generation here.
1824 // 16-bit LEA is also slow on Core2.
1825 bool DisableLEA16 = true;
1826 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1828 unsigned MIOpc = MI->getOpcode();
1830 case X86::SHUFPSrri: {
1831 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1832 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1834 unsigned B = MI->getOperand(1).getReg();
1835 unsigned C = MI->getOperand(2).getReg();
1836 if (B != C) return 0;
1837 unsigned A = MI->getOperand(0).getReg();
1838 unsigned M = MI->getOperand(3).getImm();
1839 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1840 .addReg(A, RegState::Define | getDeadRegState(isDead))
1841 .addReg(B, getKillRegState(isKill)).addImm(M);
1844 case X86::SHUFPDrri: {
1845 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1846 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1848 unsigned B = MI->getOperand(1).getReg();
1849 unsigned C = MI->getOperand(2).getReg();
1850 if (B != C) return 0;
1851 unsigned A = MI->getOperand(0).getReg();
1852 unsigned M = MI->getOperand(3).getImm();
1854 // Convert to PSHUFD mask.
1855 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1857 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1858 .addReg(A, RegState::Define | getDeadRegState(isDead))
1859 .addReg(B, getKillRegState(isKill)).addImm(M);
1862 case X86::SHL64ri: {
1863 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1864 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1865 // the flags produced by a shift yet, so this is safe.
1866 unsigned ShAmt = MI->getOperand(2).getImm();
1867 if (ShAmt == 0 || ShAmt >= 4) return 0;
1869 // LEA can't handle RSP.
1870 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1871 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1874 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1875 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1876 .addReg(0).addImm(1 << ShAmt)
1877 .addReg(Src, getKillRegState(isKill))
1878 .addImm(0).addReg(0);
1881 case X86::SHL32ri: {
1882 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1883 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1884 // the flags produced by a shift yet, so this is safe.
1885 unsigned ShAmt = MI->getOperand(2).getImm();
1886 if (ShAmt == 0 || ShAmt >= 4) return 0;
1888 // LEA can't handle ESP.
1889 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1890 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1893 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1894 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1895 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1896 .addReg(0).addImm(1 << ShAmt)
1897 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1900 case X86::SHL16ri: {
1901 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1902 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1903 // the flags produced by a shift yet, so this is safe.
1904 unsigned ShAmt = MI->getOperand(2).getImm();
1905 if (ShAmt == 0 || ShAmt >= 4) return 0;
1908 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1909 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1910 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1911 .addReg(0).addImm(1 << ShAmt)
1912 .addReg(Src, getKillRegState(isKill))
1913 .addImm(0).addReg(0);
1917 // The following opcodes also sets the condition code register(s). Only
1918 // convert them to equivalent lea if the condition code register def's
1920 if (hasLiveCondCodeDef(MI))
1927 case X86::INC64_32r: {
1928 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1929 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1930 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1931 const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
1932 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1933 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1935 // LEA can't handle RSP.
1936 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1937 !MF.getRegInfo().constrainRegClass(Src, RC))
1940 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1941 .addReg(Dest, RegState::Define |
1942 getDeadRegState(isDead)),
1947 case X86::INC64_16r:
1949 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1950 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1951 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1952 .addReg(Dest, RegState::Define |
1953 getDeadRegState(isDead)),
1958 case X86::DEC64_32r: {
1959 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1960 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1961 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1962 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
1963 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1964 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1965 // LEA can't handle RSP.
1966 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1967 !MF.getRegInfo().constrainRegClass(Src, RC))
1970 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1971 .addReg(Dest, RegState::Define |
1972 getDeadRegState(isDead)),
1977 case X86::DEC64_16r:
1979 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1980 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1981 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1982 .addReg(Dest, RegState::Define |
1983 getDeadRegState(isDead)),
1987 case X86::ADD64rr_DB:
1989 case X86::ADD32rr_DB: {
1990 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1992 const TargetRegisterClass *RC;
1993 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1995 RC = &X86::GR64_NOSPRegClass;
1997 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1998 RC = &X86::GR32_NOSPRegClass;
2002 unsigned Src2 = MI->getOperand(2).getReg();
2003 bool isKill2 = MI->getOperand(2).isKill();
2005 // LEA can't handle RSP.
2006 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
2007 !MF.getRegInfo().constrainRegClass(Src2, RC))
2010 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2011 .addReg(Dest, RegState::Define |
2012 getDeadRegState(isDead)),
2013 Src, isKill, Src2, isKill2);
2015 LV->replaceKillInstruction(Src2, MI, NewMI);
2019 case X86::ADD16rr_DB: {
2021 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2022 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2023 unsigned Src2 = MI->getOperand(2).getReg();
2024 bool isKill2 = MI->getOperand(2).isKill();
2025 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2026 .addReg(Dest, RegState::Define |
2027 getDeadRegState(isDead)),
2028 Src, isKill, Src2, isKill2);
2030 LV->replaceKillInstruction(Src2, MI, NewMI);
2033 case X86::ADD64ri32:
2035 case X86::ADD64ri32_DB:
2036 case X86::ADD64ri8_DB:
2037 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2038 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2039 .addReg(Dest, RegState::Define |
2040 getDeadRegState(isDead)),
2041 Src, isKill, MI->getOperand(2).getImm());
2045 case X86::ADD32ri_DB:
2046 case X86::ADD32ri8_DB: {
2047 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2048 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2049 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2050 .addReg(Dest, RegState::Define |
2051 getDeadRegState(isDead)),
2052 Src, isKill, MI->getOperand(2).getImm());
2057 case X86::ADD16ri_DB:
2058 case X86::ADD16ri8_DB:
2060 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2061 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2062 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2063 .addReg(Dest, RegState::Define |
2064 getDeadRegState(isDead)),
2065 Src, isKill, MI->getOperand(2).getImm());
2071 if (!NewMI) return 0;
2073 if (LV) { // Update live variables
2075 LV->replaceKillInstruction(Src, MI, NewMI);
2077 LV->replaceKillInstruction(Dest, MI, NewMI);
2080 MFI->insert(MBBI, NewMI); // Insert the new inst
2084 /// commuteInstruction - We have a few instructions that must be hacked on to
2088 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2089 switch (MI->getOpcode()) {
2090 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2091 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2092 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2093 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2094 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2095 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2098 switch (MI->getOpcode()) {
2099 default: llvm_unreachable("Unreachable!");
2100 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2101 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2102 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2103 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2104 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2105 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2107 unsigned Amt = MI->getOperand(3).getImm();
2109 MachineFunction &MF = *MI->getParent()->getParent();
2110 MI = MF.CloneMachineInstr(MI);
2113 MI->setDesc(get(Opc));
2114 MI->getOperand(3).setImm(Size-Amt);
2115 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2117 case X86::CMOVB16rr:
2118 case X86::CMOVB32rr:
2119 case X86::CMOVB64rr:
2120 case X86::CMOVAE16rr:
2121 case X86::CMOVAE32rr:
2122 case X86::CMOVAE64rr:
2123 case X86::CMOVE16rr:
2124 case X86::CMOVE32rr:
2125 case X86::CMOVE64rr:
2126 case X86::CMOVNE16rr:
2127 case X86::CMOVNE32rr:
2128 case X86::CMOVNE64rr:
2129 case X86::CMOVBE16rr:
2130 case X86::CMOVBE32rr:
2131 case X86::CMOVBE64rr:
2132 case X86::CMOVA16rr:
2133 case X86::CMOVA32rr:
2134 case X86::CMOVA64rr:
2135 case X86::CMOVL16rr:
2136 case X86::CMOVL32rr:
2137 case X86::CMOVL64rr:
2138 case X86::CMOVGE16rr:
2139 case X86::CMOVGE32rr:
2140 case X86::CMOVGE64rr:
2141 case X86::CMOVLE16rr:
2142 case X86::CMOVLE32rr:
2143 case X86::CMOVLE64rr:
2144 case X86::CMOVG16rr:
2145 case X86::CMOVG32rr:
2146 case X86::CMOVG64rr:
2147 case X86::CMOVS16rr:
2148 case X86::CMOVS32rr:
2149 case X86::CMOVS64rr:
2150 case X86::CMOVNS16rr:
2151 case X86::CMOVNS32rr:
2152 case X86::CMOVNS64rr:
2153 case X86::CMOVP16rr:
2154 case X86::CMOVP32rr:
2155 case X86::CMOVP64rr:
2156 case X86::CMOVNP16rr:
2157 case X86::CMOVNP32rr:
2158 case X86::CMOVNP64rr:
2159 case X86::CMOVO16rr:
2160 case X86::CMOVO32rr:
2161 case X86::CMOVO64rr:
2162 case X86::CMOVNO16rr:
2163 case X86::CMOVNO32rr:
2164 case X86::CMOVNO64rr: {
2166 switch (MI->getOpcode()) {
2168 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2169 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2170 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2171 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2172 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2173 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2174 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2175 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2176 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2177 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2178 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2179 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2180 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2181 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2182 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2183 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2184 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2185 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2186 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2187 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2188 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2189 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2190 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2191 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2192 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2193 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2194 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2195 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2196 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2197 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2198 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2199 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2200 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2201 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2202 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2203 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2204 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2205 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2206 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2207 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2208 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2209 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2210 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2211 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2212 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2213 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2214 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2215 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2218 MachineFunction &MF = *MI->getParent()->getParent();
2219 MI = MF.CloneMachineInstr(MI);
2222 MI->setDesc(get(Opc));
2223 // Fallthrough intended.
2226 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2230 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2232 default: return X86::COND_INVALID;
2233 case X86::JE_4: return X86::COND_E;
2234 case X86::JNE_4: return X86::COND_NE;
2235 case X86::JL_4: return X86::COND_L;
2236 case X86::JLE_4: return X86::COND_LE;
2237 case X86::JG_4: return X86::COND_G;
2238 case X86::JGE_4: return X86::COND_GE;
2239 case X86::JB_4: return X86::COND_B;
2240 case X86::JBE_4: return X86::COND_BE;
2241 case X86::JA_4: return X86::COND_A;
2242 case X86::JAE_4: return X86::COND_AE;
2243 case X86::JS_4: return X86::COND_S;
2244 case X86::JNS_4: return X86::COND_NS;
2245 case X86::JP_4: return X86::COND_P;
2246 case X86::JNP_4: return X86::COND_NP;
2247 case X86::JO_4: return X86::COND_O;
2248 case X86::JNO_4: return X86::COND_NO;
2252 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2254 default: llvm_unreachable("Illegal condition code!");
2255 case X86::COND_E: return X86::JE_4;
2256 case X86::COND_NE: return X86::JNE_4;
2257 case X86::COND_L: return X86::JL_4;
2258 case X86::COND_LE: return X86::JLE_4;
2259 case X86::COND_G: return X86::JG_4;
2260 case X86::COND_GE: return X86::JGE_4;
2261 case X86::COND_B: return X86::JB_4;
2262 case X86::COND_BE: return X86::JBE_4;
2263 case X86::COND_A: return X86::JA_4;
2264 case X86::COND_AE: return X86::JAE_4;
2265 case X86::COND_S: return X86::JS_4;
2266 case X86::COND_NS: return X86::JNS_4;
2267 case X86::COND_P: return X86::JP_4;
2268 case X86::COND_NP: return X86::JNP_4;
2269 case X86::COND_O: return X86::JO_4;
2270 case X86::COND_NO: return X86::JNO_4;
2274 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2275 /// e.g. turning COND_E to COND_NE.
2276 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2278 default: llvm_unreachable("Illegal condition code!");
2279 case X86::COND_E: return X86::COND_NE;
2280 case X86::COND_NE: return X86::COND_E;
2281 case X86::COND_L: return X86::COND_GE;
2282 case X86::COND_LE: return X86::COND_G;
2283 case X86::COND_G: return X86::COND_LE;
2284 case X86::COND_GE: return X86::COND_L;
2285 case X86::COND_B: return X86::COND_AE;
2286 case X86::COND_BE: return X86::COND_A;
2287 case X86::COND_A: return X86::COND_BE;
2288 case X86::COND_AE: return X86::COND_B;
2289 case X86::COND_S: return X86::COND_NS;
2290 case X86::COND_NS: return X86::COND_S;
2291 case X86::COND_P: return X86::COND_NP;
2292 case X86::COND_NP: return X86::COND_P;
2293 case X86::COND_O: return X86::COND_NO;
2294 case X86::COND_NO: return X86::COND_O;
2298 /// getCMovFromCond - Return a cmov(rr) opcode for the given condition and
2299 /// register size in bytes.
2300 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes) {
2301 static const unsigned Opc[16][3] = {
2302 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2303 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2304 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2305 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2306 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2307 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2308 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2309 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2310 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2311 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2312 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2313 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2314 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2315 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2316 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2317 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }
2320 assert(CC < 16 && "Can only handle standard cond codes");
2322 default: llvm_unreachable("Illegal register size!");
2323 case 2: return Opc[CC][0];
2324 case 4: return Opc[CC][1];
2325 case 8: return Opc[CC][2];
2329 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2330 if (!MI->isTerminator()) return false;
2332 // Conditional branch is a special case.
2333 if (MI->isBranch() && !MI->isBarrier())
2335 if (!MI->isPredicable())
2337 return !isPredicated(MI);
2340 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2341 MachineBasicBlock *&TBB,
2342 MachineBasicBlock *&FBB,
2343 SmallVectorImpl<MachineOperand> &Cond,
2344 bool AllowModify) const {
2345 // Start from the bottom of the block and work up, examining the
2346 // terminator instructions.
2347 MachineBasicBlock::iterator I = MBB.end();
2348 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2349 while (I != MBB.begin()) {
2351 if (I->isDebugValue())
2354 // Working from the bottom, when we see a non-terminator instruction, we're
2356 if (!isUnpredicatedTerminator(I))
2359 // A terminator that isn't a branch can't easily be handled by this
2364 // Handle unconditional branches.
2365 if (I->getOpcode() == X86::JMP_4) {
2369 TBB = I->getOperand(0).getMBB();
2373 // If the block has any instructions after a JMP, delete them.
2374 while (llvm::next(I) != MBB.end())
2375 llvm::next(I)->eraseFromParent();
2380 // Delete the JMP if it's equivalent to a fall-through.
2381 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2383 I->eraseFromParent();
2385 UnCondBrIter = MBB.end();
2389 // TBB is used to indicate the unconditional destination.
2390 TBB = I->getOperand(0).getMBB();
2394 // Handle conditional branches.
2395 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2396 if (BranchCode == X86::COND_INVALID)
2397 return true; // Can't handle indirect branch.
2399 // Working from the bottom, handle the first conditional branch.
2401 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2402 if (AllowModify && UnCondBrIter != MBB.end() &&
2403 MBB.isLayoutSuccessor(TargetBB)) {
2404 // If we can modify the code and it ends in something like:
2412 // Then we can change this to:
2419 // Which is a bit more efficient.
2420 // We conditionally jump to the fall-through block.
2421 BranchCode = GetOppositeBranchCondition(BranchCode);
2422 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2423 MachineBasicBlock::iterator OldInst = I;
2425 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2426 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2427 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2430 OldInst->eraseFromParent();
2431 UnCondBrIter->eraseFromParent();
2433 // Restart the analysis.
2434 UnCondBrIter = MBB.end();
2440 TBB = I->getOperand(0).getMBB();
2441 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2445 // Handle subsequent conditional branches. Only handle the case where all
2446 // conditional branches branch to the same destination and their condition
2447 // opcodes fit one of the special multi-branch idioms.
2448 assert(Cond.size() == 1);
2451 // Only handle the case where all conditional branches branch to the same
2453 if (TBB != I->getOperand(0).getMBB())
2456 // If the conditions are the same, we can leave them alone.
2457 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2458 if (OldBranchCode == BranchCode)
2461 // If they differ, see if they fit one of the known patterns. Theoretically,
2462 // we could handle more patterns here, but we shouldn't expect to see them
2463 // if instruction selection has done a reasonable job.
2464 if ((OldBranchCode == X86::COND_NP &&
2465 BranchCode == X86::COND_E) ||
2466 (OldBranchCode == X86::COND_E &&
2467 BranchCode == X86::COND_NP))
2468 BranchCode = X86::COND_NP_OR_E;
2469 else if ((OldBranchCode == X86::COND_P &&
2470 BranchCode == X86::COND_NE) ||
2471 (OldBranchCode == X86::COND_NE &&
2472 BranchCode == X86::COND_P))
2473 BranchCode = X86::COND_NE_OR_P;
2477 // Update the MachineOperand.
2478 Cond[0].setImm(BranchCode);
2484 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2485 MachineBasicBlock::iterator I = MBB.end();
2488 while (I != MBB.begin()) {
2490 if (I->isDebugValue())
2492 if (I->getOpcode() != X86::JMP_4 &&
2493 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2495 // Remove the branch.
2496 I->eraseFromParent();
2505 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2506 MachineBasicBlock *FBB,
2507 const SmallVectorImpl<MachineOperand> &Cond,
2508 DebugLoc DL) const {
2509 // Shouldn't be a fall through.
2510 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2511 assert((Cond.size() == 1 || Cond.size() == 0) &&
2512 "X86 branch conditions have one component!");
2515 // Unconditional branch?
2516 assert(!FBB && "Unconditional branch with multiple successors!");
2517 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2521 // Conditional branch.
2523 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2525 case X86::COND_NP_OR_E:
2526 // Synthesize NP_OR_E with two branches.
2527 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2529 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2532 case X86::COND_NE_OR_P:
2533 // Synthesize NE_OR_P with two branches.
2534 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2536 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2540 unsigned Opc = GetCondBranchFromCond(CC);
2541 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2546 // Two-way Conditional branch. Insert the second branch.
2547 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2554 canInsertSelect(const MachineBasicBlock &MBB,
2555 const SmallVectorImpl<MachineOperand> &Cond,
2556 unsigned TrueReg, unsigned FalseReg,
2557 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2558 // Not all subtargets have cmov instructions.
2559 if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2561 if (Cond.size() != 1)
2563 // We cannot do the composite conditions, at least not in SSA form.
2564 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2567 // Check register classes.
2568 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2569 const TargetRegisterClass *RC =
2570 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2574 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2575 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2576 X86::GR32RegClass.hasSubClassEq(RC) ||
2577 X86::GR64RegClass.hasSubClassEq(RC)) {
2578 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2579 // Bridge. Probably Ivy Bridge as well.
2586 // Can't do vectors.
2590 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2591 MachineBasicBlock::iterator I, DebugLoc DL,
2593 const SmallVectorImpl<MachineOperand> &Cond,
2594 unsigned TrueReg, unsigned FalseReg) const {
2595 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2596 assert(Cond.size() == 1 && "Invalid Cond array");
2597 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2598 MRI.getRegClass(DstReg)->getSize());
2599 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2602 /// isHReg - Test if the given register is a physical h register.
2603 static bool isHReg(unsigned Reg) {
2604 return X86::GR8_ABCD_HRegClass.contains(Reg);
2607 // Try and copy between VR128/VR64 and GR64 registers.
2608 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2610 // SrcReg(VR128) -> DestReg(GR64)
2611 // SrcReg(VR64) -> DestReg(GR64)
2612 // SrcReg(GR64) -> DestReg(VR128)
2613 // SrcReg(GR64) -> DestReg(VR64)
2615 if (X86::GR64RegClass.contains(DestReg)) {
2616 if (X86::VR128RegClass.contains(SrcReg)) {
2617 // Copy from a VR128 register to a GR64 register.
2618 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2619 } else if (X86::VR64RegClass.contains(SrcReg)) {
2620 // Copy from a VR64 register to a GR64 register.
2621 return X86::MOVSDto64rr;
2623 } else if (X86::GR64RegClass.contains(SrcReg)) {
2624 // Copy from a GR64 register to a VR128 register.
2625 if (X86::VR128RegClass.contains(DestReg))
2626 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2627 // Copy from a GR64 register to a VR64 register.
2628 else if (X86::VR64RegClass.contains(DestReg))
2629 return X86::MOV64toSDrr;
2632 // SrcReg(FR32) -> DestReg(GR32)
2633 // SrcReg(GR32) -> DestReg(FR32)
2635 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2636 // Copy from a FR32 register to a GR32 register.
2637 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2639 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2640 // Copy from a GR32 register to a FR32 register.
2641 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2646 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2647 MachineBasicBlock::iterator MI, DebugLoc DL,
2648 unsigned DestReg, unsigned SrcReg,
2649 bool KillSrc) const {
2650 // First deal with the normal symmetric copies.
2651 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2653 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2655 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2657 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2659 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2660 // Copying to or from a physical H register on x86-64 requires a NOREX
2661 // move. Otherwise use a normal move.
2662 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2663 TM.getSubtarget<X86Subtarget>().is64Bit()) {
2664 Opc = X86::MOV8rr_NOREX;
2665 // Both operands must be encodable without an REX prefix.
2666 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2667 "8-bit H register can not be copied outside GR8_NOREX");
2670 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2671 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2672 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2673 Opc = X86::VMOVAPSYrr;
2674 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2675 Opc = X86::MMX_MOVQ64rr;
2677 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2680 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2681 .addReg(SrcReg, getKillRegState(KillSrc));
2685 // Moving EFLAGS to / from another register requires a push and a pop.
2686 if (SrcReg == X86::EFLAGS) {
2687 if (X86::GR64RegClass.contains(DestReg)) {
2688 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2689 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2691 } else if (X86::GR32RegClass.contains(DestReg)) {
2692 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2693 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2697 if (DestReg == X86::EFLAGS) {
2698 if (X86::GR64RegClass.contains(SrcReg)) {
2699 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2700 .addReg(SrcReg, getKillRegState(KillSrc));
2701 BuildMI(MBB, MI, DL, get(X86::POPF64));
2703 } else if (X86::GR32RegClass.contains(SrcReg)) {
2704 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2705 .addReg(SrcReg, getKillRegState(KillSrc));
2706 BuildMI(MBB, MI, DL, get(X86::POPF32));
2711 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2712 << " to " << RI.getName(DestReg) << '\n');
2713 llvm_unreachable("Cannot emit physreg copy instruction");
2716 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2717 const TargetRegisterClass *RC,
2718 bool isStackAligned,
2719 const TargetMachine &TM,
2721 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2722 switch (RC->getSize()) {
2724 llvm_unreachable("Unknown spill size");
2726 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2727 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2728 // Copying to or from a physical H register on x86-64 requires a NOREX
2729 // move. Otherwise use a normal move.
2730 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2731 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2732 return load ? X86::MOV8rm : X86::MOV8mr;
2734 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2735 return load ? X86::MOV16rm : X86::MOV16mr;
2737 if (X86::GR32RegClass.hasSubClassEq(RC))
2738 return load ? X86::MOV32rm : X86::MOV32mr;
2739 if (X86::FR32RegClass.hasSubClassEq(RC))
2741 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2742 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2743 if (X86::RFP32RegClass.hasSubClassEq(RC))
2744 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2745 llvm_unreachable("Unknown 4-byte regclass");
2747 if (X86::GR64RegClass.hasSubClassEq(RC))
2748 return load ? X86::MOV64rm : X86::MOV64mr;
2749 if (X86::FR64RegClass.hasSubClassEq(RC))
2751 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2752 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2753 if (X86::VR64RegClass.hasSubClassEq(RC))
2754 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2755 if (X86::RFP64RegClass.hasSubClassEq(RC))
2756 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2757 llvm_unreachable("Unknown 8-byte regclass");
2759 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2760 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2762 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2763 // If stack is realigned we can use aligned stores.
2766 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2767 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2770 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2771 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2774 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2775 // If stack is realigned we can use aligned stores.
2777 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2779 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2783 static unsigned getStoreRegOpcode(unsigned SrcReg,
2784 const TargetRegisterClass *RC,
2785 bool isStackAligned,
2786 TargetMachine &TM) {
2787 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2791 static unsigned getLoadRegOpcode(unsigned DestReg,
2792 const TargetRegisterClass *RC,
2793 bool isStackAligned,
2794 const TargetMachine &TM) {
2795 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2798 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2799 MachineBasicBlock::iterator MI,
2800 unsigned SrcReg, bool isKill, int FrameIdx,
2801 const TargetRegisterClass *RC,
2802 const TargetRegisterInfo *TRI) const {
2803 const MachineFunction &MF = *MBB.getParent();
2804 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2805 "Stack slot too small for store");
2806 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2807 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2808 RI.canRealignStack(MF);
2809 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2810 DebugLoc DL = MBB.findDebugLoc(MI);
2811 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2812 .addReg(SrcReg, getKillRegState(isKill));
2815 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2817 SmallVectorImpl<MachineOperand> &Addr,
2818 const TargetRegisterClass *RC,
2819 MachineInstr::mmo_iterator MMOBegin,
2820 MachineInstr::mmo_iterator MMOEnd,
2821 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2822 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2823 bool isAligned = MMOBegin != MMOEnd &&
2824 (*MMOBegin)->getAlignment() >= Alignment;
2825 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2827 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2828 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2829 MIB.addOperand(Addr[i]);
2830 MIB.addReg(SrcReg, getKillRegState(isKill));
2831 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2832 NewMIs.push_back(MIB);
2836 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2837 MachineBasicBlock::iterator MI,
2838 unsigned DestReg, int FrameIdx,
2839 const TargetRegisterClass *RC,
2840 const TargetRegisterInfo *TRI) const {
2841 const MachineFunction &MF = *MBB.getParent();
2842 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2843 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2844 RI.canRealignStack(MF);
2845 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2846 DebugLoc DL = MBB.findDebugLoc(MI);
2847 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2850 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2851 SmallVectorImpl<MachineOperand> &Addr,
2852 const TargetRegisterClass *RC,
2853 MachineInstr::mmo_iterator MMOBegin,
2854 MachineInstr::mmo_iterator MMOEnd,
2855 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2856 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2857 bool isAligned = MMOBegin != MMOEnd &&
2858 (*MMOBegin)->getAlignment() >= Alignment;
2859 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2861 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2862 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2863 MIB.addOperand(Addr[i]);
2864 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2865 NewMIs.push_back(MIB);
2869 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2870 int &CmpMask, int &CmpValue) const {
2871 switch (MI->getOpcode()) {
2873 case X86::CMP64ri32:
2880 SrcReg = MI->getOperand(0).getReg();
2883 CmpValue = MI->getOperand(1).getImm();
2889 SrcReg = MI->getOperand(0).getReg();
2890 SrcReg2 = MI->getOperand(1).getReg();
2898 /// getSwappedConditionForSET - assume the flags are set by MI(a,b), return
2899 /// the opcode if we modify the instructions such that flags are
2901 static unsigned getSwappedConditionForSET(unsigned SETOpc) {
2904 case X86::SETEr: return X86::SETEr;
2905 case X86::SETEm: return X86::SETEm;
2906 case X86::SETNEr: return X86::SETNEr;
2907 case X86::SETNEm: return X86::SETNEm;
2908 case X86::SETLr: return X86::SETGr;
2909 case X86::SETLm: return X86::SETGm;
2910 case X86::SETLEr: return X86::SETGEr;
2911 case X86::SETLEm: return X86::SETGEm;
2912 case X86::SETGr: return X86::SETLr;
2913 case X86::SETGm: return X86::SETLm;
2914 case X86::SETGEr: return X86::SETLEr;
2915 case X86::SETGEm: return X86::SETLEm;
2916 case X86::SETBr: return X86::SETAr;
2917 case X86::SETBm: return X86::SETAm;
2918 case X86::SETBEr: return X86::SETAEr;
2919 case X86::SETBEm: return X86::SETAEm;
2920 case X86::SETAr: return X86::SETBr;
2921 case X86::SETAm: return X86::SETBm;
2922 case X86::SETAEr: return X86::SETBEr;
2923 case X86::SETAEm: return X86::SETBEm;
2927 /// getSwappedConditionForBranch - assume the flags are set by MI(a,b), return
2928 /// the opcode if we modify the instructions such that flags are
2930 static unsigned getSwappedConditionForBranch(unsigned BranchOpc) {
2931 switch (BranchOpc) {
2933 case X86::JE_4: return X86::JE_4;
2934 case X86::JNE_4: return X86::JNE_4;
2935 case X86::JL_4: return X86::JG_4;
2936 case X86::JLE_4: return X86::JGE_4;
2937 case X86::JG_4: return X86::JL_4;
2938 case X86::JGE_4: return X86::JLE_4;
2939 case X86::JB_4: return X86::JA_4;
2940 case X86::JBE_4: return X86::JAE_4;
2941 case X86::JA_4: return X86::JB_4;
2942 case X86::JAE_4: return X86::JBE_4;
2946 /// getSwappedConditionForCMov - assume the flags are set by MI(a,b), return
2947 /// the opcode if we modify the instructions such that flags are
2949 static unsigned getSwappedConditionForCMov(unsigned CMovOpc) {
2952 case X86::CMOVE16rm: return X86::CMOVE16rm;
2953 case X86::CMOVE16rr: return X86::CMOVE16rr;
2954 case X86::CMOVE32rm: return X86::CMOVE32rm;
2955 case X86::CMOVE32rr: return X86::CMOVE32rr;
2956 case X86::CMOVE64rm: return X86::CMOVE64rm;
2957 case X86::CMOVE64rr: return X86::CMOVE64rr;
2958 case X86::CMOVNE16rm: return X86::CMOVNE16rm;
2959 case X86::CMOVNE16rr: return X86::CMOVNE16rr;
2960 case X86::CMOVNE32rm: return X86::CMOVNE32rm;
2961 case X86::CMOVNE32rr: return X86::CMOVNE32rr;
2962 case X86::CMOVNE64rm: return X86::CMOVNE64rm;
2963 case X86::CMOVNE64rr: return X86::CMOVNE64rr;
2965 case X86::CMOVL16rm: return X86::CMOVG16rm;
2966 case X86::CMOVL16rr: return X86::CMOVG16rr;
2967 case X86::CMOVL32rm: return X86::CMOVG32rm;
2968 case X86::CMOVL32rr: return X86::CMOVG32rr;
2969 case X86::CMOVL64rm: return X86::CMOVG64rm;
2970 case X86::CMOVL64rr: return X86::CMOVG64rr;
2971 case X86::CMOVLE16rm: return X86::CMOVGE16rm;
2972 case X86::CMOVLE16rr: return X86::CMOVGE16rr;
2973 case X86::CMOVLE32rm: return X86::CMOVGE32rm;
2974 case X86::CMOVLE32rr: return X86::CMOVGE32rr;
2975 case X86::CMOVLE64rm: return X86::CMOVGE64rm;
2976 case X86::CMOVLE64rr: return X86::CMOVGE64rr;
2978 case X86::CMOVG16rm: return X86::CMOVL16rm;
2979 case X86::CMOVG16rr: return X86::CMOVL16rr;
2980 case X86::CMOVG32rm: return X86::CMOVL32rm;
2981 case X86::CMOVG32rr: return X86::CMOVL32rr;
2982 case X86::CMOVG64rm: return X86::CMOVL64rm;
2983 case X86::CMOVG64rr: return X86::CMOVL64rr;
2984 case X86::CMOVGE16rm: return X86::CMOVLE16rm;
2985 case X86::CMOVGE16rr: return X86::CMOVLE16rr;
2986 case X86::CMOVGE32rm: return X86::CMOVLE32rm;
2987 case X86::CMOVGE32rr: return X86::CMOVLE32rr;
2988 case X86::CMOVGE64rm: return X86::CMOVLE64rm;
2989 case X86::CMOVGE64rr: return X86::CMOVLE64rr;
2991 case X86::CMOVB16rm: return X86::CMOVA16rm;
2992 case X86::CMOVB16rr: return X86::CMOVA16rr;
2993 case X86::CMOVB32rm: return X86::CMOVA32rm;
2994 case X86::CMOVB32rr: return X86::CMOVA32rr;
2995 case X86::CMOVB64rm: return X86::CMOVA64rm;
2996 case X86::CMOVB64rr: return X86::CMOVA64rr;
2997 case X86::CMOVBE16rm: return X86::CMOVAE16rm;
2998 case X86::CMOVBE16rr: return X86::CMOVAE16rr;
2999 case X86::CMOVBE32rm: return X86::CMOVAE32rm;
3000 case X86::CMOVBE32rr: return X86::CMOVAE32rr;
3001 case X86::CMOVBE64rm: return X86::CMOVAE64rm;
3002 case X86::CMOVBE64rr: return X86::CMOVAE64rr;
3004 case X86::CMOVA16rm: return X86::CMOVB16rm;
3005 case X86::CMOVA16rr: return X86::CMOVB16rr;
3006 case X86::CMOVA32rm: return X86::CMOVB32rm;
3007 case X86::CMOVA32rr: return X86::CMOVB32rr;
3008 case X86::CMOVA64rm: return X86::CMOVB64rm;
3009 case X86::CMOVA64rr: return X86::CMOVB64rr;
3010 case X86::CMOVAE16rm: return X86::CMOVBE16rm;
3011 case X86::CMOVAE16rr: return X86::CMOVBE16rr;
3012 case X86::CMOVAE32rm: return X86::CMOVBE32rm;
3013 case X86::CMOVAE32rr: return X86::CMOVBE32rr;
3014 case X86::CMOVAE64rm: return X86::CMOVBE64rm;
3015 case X86::CMOVAE64rr: return X86::CMOVBE64rr;
3019 /// isRedundantFlagInstr - check whether the first instruction, whose only
3020 /// purpose is to update flags, can be made redundant.
3021 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3022 /// This function can be extended later on.
3023 /// SrcReg, SrcRegs: register operands for FlagI.
3024 /// ImmValue: immediate for FlagI if it takes an immediate.
3025 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3026 unsigned SrcReg2, int ImmValue,
3028 if (((FlagI->getOpcode() == X86::CMP64rr &&
3029 OI->getOpcode() == X86::SUB64rr) ||
3030 (FlagI->getOpcode() == X86::CMP32rr &&
3031 OI->getOpcode() == X86::SUB32rr)||
3032 (FlagI->getOpcode() == X86::CMP16rr &&
3033 OI->getOpcode() == X86::SUB16rr)||
3034 (FlagI->getOpcode() == X86::CMP8rr &&
3035 OI->getOpcode() == X86::SUB8rr)) &&
3036 ((OI->getOperand(1).getReg() == SrcReg &&
3037 OI->getOperand(2).getReg() == SrcReg2) ||
3038 (OI->getOperand(1).getReg() == SrcReg2 &&
3039 OI->getOperand(2).getReg() == SrcReg)))
3042 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3043 OI->getOpcode() == X86::SUB64ri32) ||
3044 (FlagI->getOpcode() == X86::CMP64ri8 &&
3045 OI->getOpcode() == X86::SUB64ri8) ||
3046 (FlagI->getOpcode() == X86::CMP32ri &&
3047 OI->getOpcode() == X86::SUB32ri) ||
3048 (FlagI->getOpcode() == X86::CMP32ri8 &&
3049 OI->getOpcode() == X86::SUB32ri8) ||
3050 (FlagI->getOpcode() == X86::CMP16ri &&
3051 OI->getOpcode() == X86::SUB16ri) ||
3052 (FlagI->getOpcode() == X86::CMP16ri8 &&
3053 OI->getOpcode() == X86::SUB16ri8) ||
3054 (FlagI->getOpcode() == X86::CMP8ri &&
3055 OI->getOpcode() == X86::SUB8ri)) &&
3056 OI->getOperand(1).getReg() == SrcReg &&
3057 OI->getOperand(2).getImm() == ImmValue)
3062 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3063 /// operates on the same source operands and sets flags in the same way as
3064 /// Compare; remove Compare if possible.
3066 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3067 int CmpMask, int CmpValue,
3068 const MachineRegisterInfo *MRI) const {
3069 // Get the unique definition of SrcReg.
3070 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3071 if (!MI) return false;
3073 // CmpInstr is the first instruction of the BB.
3074 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3076 // We are searching for an earlier instruction that can make CmpInstr
3077 // redundant and that instruction will be saved in Sub.
3078 MachineInstr *Sub = NULL;
3079 const TargetRegisterInfo *TRI = &getRegisterInfo();
3081 // We iterate backward, starting from the instruction before CmpInstr and
3082 // stop when reaching the definition of a source register or done with the BB.
3083 // RI points to the instruction before CmpInstr.
3084 // If the definition is in this basic block, RE points to the definition;
3085 // otherwise, RE is the rend of the basic block.
3086 MachineBasicBlock::reverse_iterator
3087 RI = MachineBasicBlock::reverse_iterator(I),
3088 RE = CmpInstr->getParent() == MI->getParent() ?
3089 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3090 CmpInstr->getParent()->rend();
3091 for (; RI != RE; ++RI) {
3092 MachineInstr *Instr = &*RI;
3093 // Check whether CmpInstr can be made redundant by the current instruction.
3094 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3099 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3100 Instr->readsRegister(X86::EFLAGS, TRI))
3101 // This instruction modifies or uses EFLAGS.
3102 // We can't remove CmpInstr.
3106 // Return false if no candidates exist.
3110 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3111 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3112 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3113 for (++I; I != E; ++I) {
3114 const MachineInstr &Instr = *I;
3115 if (Instr.modifiesRegister(X86::EFLAGS, TRI))
3116 // It is safe to remove CmpInstr if EFLAGS is updated again.
3119 if (!Instr.readsRegister(X86::EFLAGS, TRI))
3122 // EFLAGS is used by this instruction.
3123 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3124 Sub->getOperand(2).getReg() == SrcReg) {
3126 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3127 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3128 unsigned NewOpc = getSwappedConditionForSET(Instr.getOpcode());
3129 if (!NewOpc) NewOpc = getSwappedConditionForBranch(Instr.getOpcode());
3130 if (!NewOpc) NewOpc = getSwappedConditionForCMov(Instr.getOpcode());
3131 if (!NewOpc) return false;
3133 // Push the MachineInstr to OpsToUpdate.
3134 // If it is safe to remove CmpInstr, the condition code of these
3135 // instructions will be modified.
3136 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3140 // Make sure Sub instruction defines EFLAGS.
3141 assert(Sub->getNumOperands() >= 4 && Sub->getOperand(3).isReg() &&
3142 Sub->getOperand(3).getReg() == X86::EFLAGS &&
3143 "EFLAGS should be the 4th operand of SUBrr or SUBri.");
3144 Sub->getOperand(3).setIsDef(true);
3145 CmpInstr->eraseFromParent();
3147 // Modify the condition code of instructions in OpsToUpdate.
3148 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3149 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3153 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3154 /// instruction with two undef reads of the register being defined. This is
3155 /// used for mapping:
3158 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3160 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
3161 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3162 unsigned Reg = MI->getOperand(0).getReg();
3165 // MachineInstr::addOperand() will insert explicit operands before any
3166 // implicit operands.
3167 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
3168 .addReg(Reg, RegState::Undef);
3169 // But we don't trust that.
3170 assert(MI->getOperand(1).getReg() == Reg &&
3171 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
3175 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3176 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3177 switch (MI->getOpcode()) {
3181 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3182 case X86::TEST8ri_NOREX:
3183 MI->setDesc(get(X86::TEST8ri));
3190 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
3191 int FrameIx, uint64_t Offset,
3192 const MDNode *MDPtr,
3193 DebugLoc DL) const {
3195 AM.BaseType = X86AddressMode::FrameIndexBase;
3196 AM.Base.FrameIndex = FrameIx;
3197 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
3198 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
3202 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3203 const SmallVectorImpl<MachineOperand> &MOs,
3205 const TargetInstrInfo &TII) {
3206 // Create the base instruction with the memory operand as the first part.
3207 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3208 MI->getDebugLoc(), true);
3209 MachineInstrBuilder MIB(NewMI);
3210 unsigned NumAddrOps = MOs.size();
3211 for (unsigned i = 0; i != NumAddrOps; ++i)
3212 MIB.addOperand(MOs[i]);
3213 if (NumAddrOps < 4) // FrameIndex only
3216 // Loop over the rest of the ri operands, converting them over.
3217 unsigned NumOps = MI->getDesc().getNumOperands()-2;
3218 for (unsigned i = 0; i != NumOps; ++i) {
3219 MachineOperand &MO = MI->getOperand(i+2);
3222 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3223 MachineOperand &MO = MI->getOperand(i);
3229 static MachineInstr *FuseInst(MachineFunction &MF,
3230 unsigned Opcode, unsigned OpNo,
3231 const SmallVectorImpl<MachineOperand> &MOs,
3232 MachineInstr *MI, const TargetInstrInfo &TII) {
3233 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3234 MI->getDebugLoc(), true);
3235 MachineInstrBuilder MIB(NewMI);
3237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3238 MachineOperand &MO = MI->getOperand(i);
3240 assert(MO.isReg() && "Expected to fold into reg operand!");
3241 unsigned NumAddrOps = MOs.size();
3242 for (unsigned i = 0; i != NumAddrOps; ++i)
3243 MIB.addOperand(MOs[i]);
3244 if (NumAddrOps < 4) // FrameIndex only
3253 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3254 const SmallVectorImpl<MachineOperand> &MOs,
3256 MachineFunction &MF = *MI->getParent()->getParent();
3257 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3259 unsigned NumAddrOps = MOs.size();
3260 for (unsigned i = 0; i != NumAddrOps; ++i)
3261 MIB.addOperand(MOs[i]);
3262 if (NumAddrOps < 4) // FrameIndex only
3264 return MIB.addImm(0);
3268 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3269 MachineInstr *MI, unsigned i,
3270 const SmallVectorImpl<MachineOperand> &MOs,
3271 unsigned Size, unsigned Align) const {
3272 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3273 bool isTwoAddrFold = false;
3274 unsigned NumOps = MI->getDesc().getNumOperands();
3275 bool isTwoAddr = NumOps > 1 &&
3276 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3278 // FIXME: AsmPrinter doesn't know how to handle
3279 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3280 if (MI->getOpcode() == X86::ADD32ri &&
3281 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3284 MachineInstr *NewMI = NULL;
3285 // Folding a memory location into the two-address part of a two-address
3286 // instruction is different than folding it other places. It requires
3287 // replacing the *two* registers with the memory location.
3288 if (isTwoAddr && NumOps >= 2 && i < 2 &&
3289 MI->getOperand(0).isReg() &&
3290 MI->getOperand(1).isReg() &&
3291 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3292 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3293 isTwoAddrFold = true;
3294 } else if (i == 0) { // If operand 0
3295 if (MI->getOpcode() == X86::MOV64r0)
3296 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
3297 else if (MI->getOpcode() == X86::MOV32r0)
3298 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
3299 else if (MI->getOpcode() == X86::MOV16r0)
3300 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
3301 else if (MI->getOpcode() == X86::MOV8r0)
3302 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
3306 OpcodeTablePtr = &RegOp2MemOpTable0;
3307 } else if (i == 1) {
3308 OpcodeTablePtr = &RegOp2MemOpTable1;
3309 } else if (i == 2) {
3310 OpcodeTablePtr = &RegOp2MemOpTable2;
3313 // If table selected...
3314 if (OpcodeTablePtr) {
3315 // Find the Opcode to fuse
3316 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3317 OpcodeTablePtr->find(MI->getOpcode());
3318 if (I != OpcodeTablePtr->end()) {
3319 unsigned Opcode = I->second.first;
3320 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
3321 if (Align < MinAlign)
3323 bool NarrowToMOV32rm = false;
3325 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
3326 if (Size < RCSize) {
3327 // Check if it's safe to fold the load. If the size of the object is
3328 // narrower than the load width, then it's not.
3329 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
3331 // If this is a 64-bit load, but the spill slot is 32, then we can do
3332 // a 32-bit load which is implicitly zero-extended. This likely is due
3333 // to liveintervalanalysis remat'ing a load from stack slot.
3334 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
3336 Opcode = X86::MOV32rm;
3337 NarrowToMOV32rm = true;
3342 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
3344 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
3346 if (NarrowToMOV32rm) {
3347 // If this is the special case where we use a MOV32rm to load a 32-bit
3348 // value and zero-extend the top bits. Change the destination register
3350 unsigned DstReg = NewMI->getOperand(0).getReg();
3351 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
3352 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
3355 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
3362 if (PrintFailedFusing && !MI->isCopy())
3363 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
3367 /// hasPartialRegUpdate - Return true for all instructions that only update
3368 /// the first 32 or 64-bits of the destination register and leave the rest
3369 /// unmodified. This can be used to avoid folding loads if the instructions
3370 /// only update part of the destination register, and the non-updated part is
3371 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
3372 /// instructions breaks the partial register dependency and it can improve
3373 /// performance. e.g.:
3375 /// movss (%rdi), %xmm0
3376 /// cvtss2sd %xmm0, %xmm0
3379 /// cvtss2sd (%rdi), %xmm0
3381 /// FIXME: This should be turned into a TSFlags.
3383 static bool hasPartialRegUpdate(unsigned Opcode) {
3385 case X86::CVTSI2SSrr:
3386 case X86::CVTSI2SS64rr:
3387 case X86::CVTSI2SDrr:
3388 case X86::CVTSI2SD64rr:
3389 case X86::CVTSD2SSrr:
3390 case X86::Int_CVTSD2SSrr:
3391 case X86::CVTSS2SDrr:
3392 case X86::Int_CVTSS2SDrr:
3394 case X86::RCPSSr_Int:
3396 case X86::ROUNDSDr_Int:
3398 case X86::ROUNDSSr_Int:
3400 case X86::RSQRTSSr_Int:
3402 case X86::SQRTSSr_Int:
3403 // AVX encoded versions
3404 case X86::VCVTSD2SSrr:
3405 case X86::Int_VCVTSD2SSrr:
3406 case X86::VCVTSS2SDrr:
3407 case X86::Int_VCVTSS2SDrr:
3409 case X86::VROUNDSDr:
3410 case X86::VROUNDSDr_Int:
3411 case X86::VROUNDSSr:
3412 case X86::VROUNDSSr_Int:
3413 case X86::VRSQRTSSr:
3421 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3422 /// instructions we would like before a partial register update.
3423 unsigned X86InstrInfo::
3424 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3425 const TargetRegisterInfo *TRI) const {
3426 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3429 // If MI is marked as reading Reg, the partial register update is wanted.
3430 const MachineOperand &MO = MI->getOperand(0);
3431 unsigned Reg = MO.getReg();
3432 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3433 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3436 if (MI->readsRegister(Reg, TRI))
3440 // If any of the preceding 16 instructions are reading Reg, insert a
3441 // dependency breaking instruction. The magic number is based on a few
3442 // Nehalem experiments.
3447 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3448 const TargetRegisterInfo *TRI) const {
3449 unsigned Reg = MI->getOperand(OpNum).getReg();
3450 if (X86::VR128RegClass.contains(Reg)) {
3451 // These instructions are all floating point domain, so xorps is the best
3453 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3454 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3455 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3456 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3457 } else if (X86::VR256RegClass.contains(Reg)) {
3458 // Use vxorps to clear the full ymm register.
3459 // It wants to read and write the xmm sub-register.
3460 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3461 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3462 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3463 .addReg(Reg, RegState::ImplicitDefine);
3466 MI->addRegisterKilled(Reg, TRI, true);
3469 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3471 const SmallVectorImpl<unsigned> &Ops,
3472 int FrameIndex) const {
3473 // Check switch flag
3474 if (NoFusing) return NULL;
3476 // Unless optimizing for size, don't fold to avoid partial
3477 // register update stalls
3478 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3479 hasPartialRegUpdate(MI->getOpcode()))
3482 const MachineFrameInfo *MFI = MF.getFrameInfo();
3483 unsigned Size = MFI->getObjectSize(FrameIndex);
3484 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
3485 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3486 unsigned NewOpc = 0;
3487 unsigned RCSize = 0;
3488 switch (MI->getOpcode()) {
3489 default: return NULL;
3490 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
3491 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3492 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3493 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
3495 // Check if it's safe to fold the load. If the size of the object is
3496 // narrower than the load width, then it's not.
3499 // Change to CMPXXri r, 0 first.
3500 MI->setDesc(get(NewOpc));
3501 MI->getOperand(1).ChangeToImmediate(0);
3502 } else if (Ops.size() != 1)
3505 SmallVector<MachineOperand,4> MOs;
3506 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
3507 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
3510 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3512 const SmallVectorImpl<unsigned> &Ops,
3513 MachineInstr *LoadMI) const {
3514 // Check switch flag
3515 if (NoFusing) return NULL;
3517 // Unless optimizing for size, don't fold to avoid partial
3518 // register update stalls
3519 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3520 hasPartialRegUpdate(MI->getOpcode()))
3523 // Determine the alignment of the load.
3524 unsigned Alignment = 0;
3525 if (LoadMI->hasOneMemOperand())
3526 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3528 switch (LoadMI->getOpcode()) {
3529 case X86::AVX_SET0PSY:
3530 case X86::AVX_SET0PDY:
3531 case X86::AVX2_SETALLONES:
3532 case X86::AVX2_SET0:
3536 case X86::V_SETALLONES:
3537 case X86::AVX_SETALLONES:
3549 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3550 unsigned NewOpc = 0;
3551 switch (MI->getOpcode()) {
3552 default: return NULL;
3553 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
3554 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3555 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3556 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3558 // Change to CMPXXri r, 0 first.
3559 MI->setDesc(get(NewOpc));
3560 MI->getOperand(1).ChangeToImmediate(0);
3561 } else if (Ops.size() != 1)
3564 // Make sure the subregisters match.
3565 // Otherwise we risk changing the size of the load.
3566 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3569 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3570 switch (LoadMI->getOpcode()) {
3572 case X86::V_SETALLONES:
3573 case X86::AVX_SET0PSY:
3574 case X86::AVX_SET0PDY:
3575 case X86::AVX_SETALLONES:
3576 case X86::AVX2_SETALLONES:
3577 case X86::AVX2_SET0:
3579 case X86::FsFLD0SS: {
3580 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3581 // Create a constant-pool entry and operands to load from it.
3583 // Medium and large mode can't fold loads this way.
3584 if (TM.getCodeModel() != CodeModel::Small &&
3585 TM.getCodeModel() != CodeModel::Kernel)
3588 // x86-32 PIC requires a PIC base register for constant pools.
3589 unsigned PICBase = 0;
3590 if (TM.getRelocationModel() == Reloc::PIC_) {
3591 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3594 // FIXME: PICBase = getGlobalBaseReg(&MF);
3595 // This doesn't work for several reasons.
3596 // 1. GlobalBaseReg may have been spilled.
3597 // 2. It may not be live at MI.
3601 // Create a constant-pool entry.
3602 MachineConstantPool &MCP = *MF.getConstantPool();
3604 unsigned Opc = LoadMI->getOpcode();
3605 if (Opc == X86::FsFLD0SS)
3606 Ty = Type::getFloatTy(MF.getFunction()->getContext());
3607 else if (Opc == X86::FsFLD0SD)
3608 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3609 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3610 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3611 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3612 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3614 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3616 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3617 Opc == X86::AVX2_SETALLONES);
3618 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3619 Constant::getNullValue(Ty);
3620 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3622 // Create operands to load from the constant pool entry.
3623 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3624 MOs.push_back(MachineOperand::CreateImm(1));
3625 MOs.push_back(MachineOperand::CreateReg(0, false));
3626 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3627 MOs.push_back(MachineOperand::CreateReg(0, false));
3631 // Folding a normal load. Just copy the load's address operands.
3632 unsigned NumOps = LoadMI->getDesc().getNumOperands();
3633 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3634 MOs.push_back(LoadMI->getOperand(i));
3638 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3642 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3643 const SmallVectorImpl<unsigned> &Ops) const {
3644 // Check switch flag
3645 if (NoFusing) return 0;
3647 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3648 switch (MI->getOpcode()) {
3649 default: return false;
3656 // FIXME: AsmPrinter doesn't know how to handle
3657 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3658 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3664 if (Ops.size() != 1)
3667 unsigned OpNum = Ops[0];
3668 unsigned Opc = MI->getOpcode();
3669 unsigned NumOps = MI->getDesc().getNumOperands();
3670 bool isTwoAddr = NumOps > 1 &&
3671 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3673 // Folding a memory location into the two-address part of a two-address
3674 // instruction is different than folding it other places. It requires
3675 // replacing the *two* registers with the memory location.
3676 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3677 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3678 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3679 } else if (OpNum == 0) { // If operand 0
3684 case X86::MOV64r0: return true;
3687 OpcodeTablePtr = &RegOp2MemOpTable0;
3688 } else if (OpNum == 1) {
3689 OpcodeTablePtr = &RegOp2MemOpTable1;
3690 } else if (OpNum == 2) {
3691 OpcodeTablePtr = &RegOp2MemOpTable2;
3694 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3696 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3699 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3700 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3701 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3702 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3703 MemOp2RegOpTable.find(MI->getOpcode());
3704 if (I == MemOp2RegOpTable.end())
3706 unsigned Opc = I->second.first;
3707 unsigned Index = I->second.second & TB_INDEX_MASK;
3708 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3709 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3710 if (UnfoldLoad && !FoldedLoad)
3712 UnfoldLoad &= FoldedLoad;
3713 if (UnfoldStore && !FoldedStore)
3715 UnfoldStore &= FoldedStore;
3717 const MCInstrDesc &MCID = get(Opc);
3718 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3719 if (!MI->hasOneMemOperand() &&
3720 RC == &X86::VR128RegClass &&
3721 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3722 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3723 // conservatively assume the address is unaligned. That's bad for
3726 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3727 SmallVector<MachineOperand,2> BeforeOps;
3728 SmallVector<MachineOperand,2> AfterOps;
3729 SmallVector<MachineOperand,4> ImpOps;
3730 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3731 MachineOperand &Op = MI->getOperand(i);
3732 if (i >= Index && i < Index + X86::AddrNumOperands)
3733 AddrOps.push_back(Op);
3734 else if (Op.isReg() && Op.isImplicit())
3735 ImpOps.push_back(Op);
3737 BeforeOps.push_back(Op);
3739 AfterOps.push_back(Op);
3742 // Emit the load instruction.
3744 std::pair<MachineInstr::mmo_iterator,
3745 MachineInstr::mmo_iterator> MMOs =
3746 MF.extractLoadMemRefs(MI->memoperands_begin(),
3747 MI->memoperands_end());
3748 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3750 // Address operands cannot be marked isKill.
3751 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3752 MachineOperand &MO = NewMIs[0]->getOperand(i);
3754 MO.setIsKill(false);
3759 // Emit the data processing instruction.
3760 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3761 MachineInstrBuilder MIB(DataMI);
3764 MIB.addReg(Reg, RegState::Define);
3765 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3766 MIB.addOperand(BeforeOps[i]);
3769 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3770 MIB.addOperand(AfterOps[i]);
3771 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3772 MachineOperand &MO = ImpOps[i];
3773 MIB.addReg(MO.getReg(),
3774 getDefRegState(MO.isDef()) |
3775 RegState::Implicit |
3776 getKillRegState(MO.isKill()) |
3777 getDeadRegState(MO.isDead()) |
3778 getUndefRegState(MO.isUndef()));
3780 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3781 unsigned NewOpc = 0;
3782 switch (DataMI->getOpcode()) {
3784 case X86::CMP64ri32:
3791 MachineOperand &MO0 = DataMI->getOperand(0);
3792 MachineOperand &MO1 = DataMI->getOperand(1);
3793 if (MO1.getImm() == 0) {
3794 switch (DataMI->getOpcode()) {
3797 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3799 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
3801 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
3802 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
3804 DataMI->setDesc(get(NewOpc));
3805 MO1.ChangeToRegister(MO0.getReg(), false);
3809 NewMIs.push_back(DataMI);
3811 // Emit the store instruction.
3813 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
3814 std::pair<MachineInstr::mmo_iterator,
3815 MachineInstr::mmo_iterator> MMOs =
3816 MF.extractStoreMemRefs(MI->memoperands_begin(),
3817 MI->memoperands_end());
3818 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3825 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3826 SmallVectorImpl<SDNode*> &NewNodes) const {
3827 if (!N->isMachineOpcode())
3830 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3831 MemOp2RegOpTable.find(N->getMachineOpcode());
3832 if (I == MemOp2RegOpTable.end())
3834 unsigned Opc = I->second.first;
3835 unsigned Index = I->second.second & TB_INDEX_MASK;
3836 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3837 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3838 const MCInstrDesc &MCID = get(Opc);
3839 MachineFunction &MF = DAG.getMachineFunction();
3840 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3841 unsigned NumDefs = MCID.NumDefs;
3842 std::vector<SDValue> AddrOps;
3843 std::vector<SDValue> BeforeOps;
3844 std::vector<SDValue> AfterOps;
3845 DebugLoc dl = N->getDebugLoc();
3846 unsigned NumOps = N->getNumOperands();
3847 for (unsigned i = 0; i != NumOps-1; ++i) {
3848 SDValue Op = N->getOperand(i);
3849 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3850 AddrOps.push_back(Op);
3851 else if (i < Index-NumDefs)
3852 BeforeOps.push_back(Op);
3853 else if (i > Index-NumDefs)
3854 AfterOps.push_back(Op);
3856 SDValue Chain = N->getOperand(NumOps-1);
3857 AddrOps.push_back(Chain);
3859 // Emit the load instruction.
3862 EVT VT = *RC->vt_begin();
3863 std::pair<MachineInstr::mmo_iterator,
3864 MachineInstr::mmo_iterator> MMOs =
3865 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3866 cast<MachineSDNode>(N)->memoperands_end());
3867 if (!(*MMOs.first) &&
3868 RC == &X86::VR128RegClass &&
3869 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3870 // Do not introduce a slow unaligned load.
3872 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3873 bool isAligned = (*MMOs.first) &&
3874 (*MMOs.first)->getAlignment() >= Alignment;
3875 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3876 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3877 NewNodes.push_back(Load);
3879 // Preserve memory reference information.
3880 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3883 // Emit the data processing instruction.
3884 std::vector<EVT> VTs;
3885 const TargetRegisterClass *DstRC = 0;
3886 if (MCID.getNumDefs() > 0) {
3887 DstRC = getRegClass(MCID, 0, &RI, MF);
3888 VTs.push_back(*DstRC->vt_begin());
3890 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3891 EVT VT = N->getValueType(i);
3892 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3896 BeforeOps.push_back(SDValue(Load, 0));
3897 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3898 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3900 NewNodes.push_back(NewNode);
3902 // Emit the store instruction.
3905 AddrOps.push_back(SDValue(NewNode, 0));
3906 AddrOps.push_back(Chain);
3907 std::pair<MachineInstr::mmo_iterator,
3908 MachineInstr::mmo_iterator> MMOs =
3909 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3910 cast<MachineSDNode>(N)->memoperands_end());
3911 if (!(*MMOs.first) &&
3912 RC == &X86::VR128RegClass &&
3913 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3914 // Do not introduce a slow unaligned store.
3916 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3917 bool isAligned = (*MMOs.first) &&
3918 (*MMOs.first)->getAlignment() >= Alignment;
3919 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3922 &AddrOps[0], AddrOps.size());
3923 NewNodes.push_back(Store);
3925 // Preserve memory reference information.
3926 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3932 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3933 bool UnfoldLoad, bool UnfoldStore,
3934 unsigned *LoadRegIndex) const {
3935 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3936 MemOp2RegOpTable.find(Opc);
3937 if (I == MemOp2RegOpTable.end())
3939 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3940 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3941 if (UnfoldLoad && !FoldedLoad)
3943 if (UnfoldStore && !FoldedStore)
3946 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3947 return I->second.first;
3951 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3952 int64_t &Offset1, int64_t &Offset2) const {
3953 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3955 unsigned Opc1 = Load1->getMachineOpcode();
3956 unsigned Opc2 = Load2->getMachineOpcode();
3958 default: return false;
3968 case X86::MMX_MOVD64rm:
3969 case X86::MMX_MOVQ64rm:
3970 case X86::FsMOVAPSrm:
3971 case X86::FsMOVAPDrm:
3977 // AVX load instructions
3980 case X86::FsVMOVAPSrm:
3981 case X86::FsVMOVAPDrm:
3982 case X86::VMOVAPSrm:
3983 case X86::VMOVUPSrm:
3984 case X86::VMOVAPDrm:
3985 case X86::VMOVDQArm:
3986 case X86::VMOVDQUrm:
3987 case X86::VMOVAPSYrm:
3988 case X86::VMOVUPSYrm:
3989 case X86::VMOVAPDYrm:
3990 case X86::VMOVDQAYrm:
3991 case X86::VMOVDQUYrm:
3995 default: return false;
4005 case X86::MMX_MOVD64rm:
4006 case X86::MMX_MOVQ64rm:
4007 case X86::FsMOVAPSrm:
4008 case X86::FsMOVAPDrm:
4014 // AVX load instructions
4017 case X86::FsVMOVAPSrm:
4018 case X86::FsVMOVAPDrm:
4019 case X86::VMOVAPSrm:
4020 case X86::VMOVUPSrm:
4021 case X86::VMOVAPDrm:
4022 case X86::VMOVDQArm:
4023 case X86::VMOVDQUrm:
4024 case X86::VMOVAPSYrm:
4025 case X86::VMOVUPSYrm:
4026 case X86::VMOVAPDYrm:
4027 case X86::VMOVDQAYrm:
4028 case X86::VMOVDQUYrm:
4032 // Check if chain operands and base addresses match.
4033 if (Load1->getOperand(0) != Load2->getOperand(0) ||
4034 Load1->getOperand(5) != Load2->getOperand(5))
4036 // Segment operands should match as well.
4037 if (Load1->getOperand(4) != Load2->getOperand(4))
4039 // Scale should be 1, Index should be Reg0.
4040 if (Load1->getOperand(1) == Load2->getOperand(1) &&
4041 Load1->getOperand(2) == Load2->getOperand(2)) {
4042 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4045 // Now let's examine the displacements.
4046 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4047 isa<ConstantSDNode>(Load2->getOperand(3))) {
4048 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4049 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4056 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4057 int64_t Offset1, int64_t Offset2,
4058 unsigned NumLoads) const {
4059 assert(Offset2 > Offset1);
4060 if ((Offset2 - Offset1) / 8 > 64)
4063 unsigned Opc1 = Load1->getMachineOpcode();
4064 unsigned Opc2 = Load2->getMachineOpcode();
4066 return false; // FIXME: overly conservative?
4073 case X86::MMX_MOVD64rm:
4074 case X86::MMX_MOVQ64rm:
4078 EVT VT = Load1->getValueType(0);
4079 switch (VT.getSimpleVT().SimpleTy) {
4081 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4082 // have 16 of them to play with.
4083 if (TM.getSubtargetImpl()->is64Bit()) {
4086 } else if (NumLoads) {
4106 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
4107 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
4108 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
4109 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
4111 Cond[0].setImm(GetOppositeBranchCondition(CC));
4116 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
4117 // FIXME: Return false for x87 stack register classes for now. We can't
4118 // allow any loads of these registers before FpGet_ST0_80.
4119 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
4120 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
4123 /// getGlobalBaseReg - Return a virtual register initialized with the
4124 /// the global base register value. Output instructions required to
4125 /// initialize the register in the function entry block, if necessary.
4127 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
4129 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
4130 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
4131 "X86-64 PIC uses RIP relative addressing");
4133 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
4134 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4135 if (GlobalBaseReg != 0)
4136 return GlobalBaseReg;
4138 // Create the register. The code to initialize it is inserted
4139 // later, by the CGBR pass (below).
4140 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4141 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4142 X86FI->setGlobalBaseReg(GlobalBaseReg);
4143 return GlobalBaseReg;
4146 // These are the replaceable SSE instructions. Some of these have Int variants
4147 // that we don't include here. We don't want to replace instructions selected
4149 static const uint16_t ReplaceableInstrs[][3] = {
4150 //PackedSingle PackedDouble PackedInt
4151 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
4152 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
4153 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
4154 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
4155 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
4156 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
4157 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
4158 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
4159 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
4160 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
4161 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
4162 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
4163 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
4164 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
4165 // AVX 128-bit support
4166 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
4167 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
4168 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
4169 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
4170 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
4171 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
4172 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
4173 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
4174 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
4175 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
4176 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
4177 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
4178 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
4179 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
4180 // AVX 256-bit support
4181 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
4182 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
4183 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
4184 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
4185 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
4186 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
4189 static const uint16_t ReplaceableInstrsAVX2[][3] = {
4190 //PackedSingle PackedDouble PackedInt
4191 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
4192 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
4193 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
4194 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
4195 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
4196 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
4197 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
4198 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
4199 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
4200 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
4201 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
4202 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
4203 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
4204 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
4207 // FIXME: Some shuffle and unpack instructions have equivalents in different
4208 // domains, but they require a bit more work than just switching opcodes.
4210 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
4211 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
4212 if (ReplaceableInstrs[i][domain-1] == opcode)
4213 return ReplaceableInstrs[i];
4217 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
4218 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
4219 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
4220 return ReplaceableInstrsAVX2[i];
4224 std::pair<uint16_t, uint16_t>
4225 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4226 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
4227 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
4228 uint16_t validDomains = 0;
4229 if (domain && lookup(MI->getOpcode(), domain))
4231 else if (domain && lookupAVX2(MI->getOpcode(), domain))
4232 validDomains = hasAVX2 ? 0xe : 0x6;
4233 return std::make_pair(domain, validDomains);
4236 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4237 assert(Domain>0 && Domain<4 && "Invalid execution domain");
4238 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
4239 assert(dom && "Not an SSE instruction");
4240 const uint16_t *table = lookup(MI->getOpcode(), dom);
4241 if (!table) { // try the other table
4242 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
4243 "256-bit vector operations only available in AVX2");
4244 table = lookupAVX2(MI->getOpcode(), dom);
4246 assert(table && "Cannot change domain");
4247 MI->setDesc(get(table[Domain-1]));
4250 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
4251 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
4252 NopInst.setOpcode(X86::NOOP);
4255 bool X86InstrInfo::isHighLatencyDef(int opc) const {
4257 default: return false;
4259 case X86::DIVSDrm_Int:
4261 case X86::DIVSDrr_Int:
4263 case X86::DIVSSrm_Int:
4265 case X86::DIVSSrr_Int:
4267 case X86::SQRTPDm_Int:
4269 case X86::SQRTPDr_Int:
4271 case X86::SQRTPSm_Int:
4273 case X86::SQRTPSr_Int:
4275 case X86::SQRTSDm_Int:
4277 case X86::SQRTSDr_Int:
4279 case X86::SQRTSSm_Int:
4281 case X86::SQRTSSr_Int:
4282 // AVX instructions with high latency
4284 case X86::VDIVSDrm_Int:
4286 case X86::VDIVSDrr_Int:
4288 case X86::VDIVSSrm_Int:
4290 case X86::VDIVSSrr_Int:
4292 case X86::VSQRTPDm_Int:
4294 case X86::VSQRTPDr_Int:
4296 case X86::VSQRTPSm_Int:
4298 case X86::VSQRTPSr_Int:
4300 case X86::VSQRTSDm_Int:
4303 case X86::VSQRTSSm_Int:
4310 hasHighOperandLatency(const InstrItineraryData *ItinData,
4311 const MachineRegisterInfo *MRI,
4312 const MachineInstr *DefMI, unsigned DefIdx,
4313 const MachineInstr *UseMI, unsigned UseIdx) const {
4314 return isHighLatencyDef(DefMI->getOpcode());
4318 /// CGBR - Create Global Base Reg pass. This initializes the PIC
4319 /// global base register for x86-32.
4320 struct CGBR : public MachineFunctionPass {
4322 CGBR() : MachineFunctionPass(ID) {}
4324 virtual bool runOnMachineFunction(MachineFunction &MF) {
4325 const X86TargetMachine *TM =
4326 static_cast<const X86TargetMachine *>(&MF.getTarget());
4328 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
4329 "X86-64 PIC uses RIP relative addressing");
4331 // Only emit a global base reg in PIC mode.
4332 if (TM->getRelocationModel() != Reloc::PIC_)
4335 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
4336 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4338 // If we didn't need a GlobalBaseReg, don't insert code.
4339 if (GlobalBaseReg == 0)
4342 // Insert the set of GlobalBaseReg into the first MBB of the function
4343 MachineBasicBlock &FirstMBB = MF.front();
4344 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
4345 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
4346 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4347 const X86InstrInfo *TII = TM->getInstrInfo();
4350 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
4351 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4355 // Operand of MovePCtoStack is completely ignored by asm printer. It's
4356 // only used in JIT code emission as displacement to pc.
4357 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
4359 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
4360 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
4361 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
4362 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
4363 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4364 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
4365 X86II::MO_GOT_ABSOLUTE_ADDRESS);
4371 virtual const char *getPassName() const {
4372 return "X86 PIC Global Base Reg Initialization";
4375 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4376 AU.setPreservesCFG();
4377 MachineFunctionPass::getAnalysisUsage(AU);
4384 llvm::createGlobalBaseRegPass() { return new CGBR(); }
4387 struct LDTLSCleanup : public MachineFunctionPass {
4389 LDTLSCleanup() : MachineFunctionPass(ID) {}
4391 virtual bool runOnMachineFunction(MachineFunction &MF) {
4392 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
4393 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
4394 // No point folding accesses if there isn't at least two.
4398 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
4399 return VisitNode(DT->getRootNode(), 0);
4402 // Visit the dominator subtree rooted at Node in pre-order.
4403 // If TLSBaseAddrReg is non-null, then use that to replace any
4404 // TLS_base_addr instructions. Otherwise, create the register
4405 // when the first such instruction is seen, and then use it
4406 // as we encounter more instructions.
4407 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
4408 MachineBasicBlock *BB = Node->getBlock();
4409 bool Changed = false;
4411 // Traverse the current block.
4412 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
4414 switch (I->getOpcode()) {
4415 case X86::TLS_base_addr32:
4416 case X86::TLS_base_addr64:
4418 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
4420 I = SetRegister(I, &TLSBaseAddrReg);
4428 // Visit the children of this block in the dominator tree.
4429 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
4431 Changed |= VisitNode(*I, TLSBaseAddrReg);
4437 // Replace the TLS_base_addr instruction I with a copy from
4438 // TLSBaseAddrReg, returning the new instruction.
4439 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
4440 unsigned TLSBaseAddrReg) {
4441 MachineFunction *MF = I->getParent()->getParent();
4442 const X86TargetMachine *TM =
4443 static_cast<const X86TargetMachine *>(&MF->getTarget());
4444 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4445 const X86InstrInfo *TII = TM->getInstrInfo();
4447 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
4448 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
4449 TII->get(TargetOpcode::COPY),
4450 is64Bit ? X86::RAX : X86::EAX)
4451 .addReg(TLSBaseAddrReg);
4453 // Erase the TLS_base_addr instruction.
4454 I->eraseFromParent();
4459 // Create a virtal register in *TLSBaseAddrReg, and populate it by
4460 // inserting a copy instruction after I. Returns the new instruction.
4461 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
4462 MachineFunction *MF = I->getParent()->getParent();
4463 const X86TargetMachine *TM =
4464 static_cast<const X86TargetMachine *>(&MF->getTarget());
4465 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4466 const X86InstrInfo *TII = TM->getInstrInfo();
4468 // Create a virtual register for the TLS base address.
4469 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4470 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
4471 ? &X86::GR64RegClass
4472 : &X86::GR32RegClass);
4474 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
4475 MachineInstr *Next = I->getNextNode();
4476 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
4477 TII->get(TargetOpcode::COPY),
4479 .addReg(is64Bit ? X86::RAX : X86::EAX);
4484 virtual const char *getPassName() const {
4485 return "Local Dynamic TLS Access Clean-up";
4488 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4489 AU.setPreservesCFG();
4490 AU.addRequired<MachineDominatorTree>();
4491 MachineFunctionPass::getAnalysisUsage(AU);
4496 char LDTLSCleanup::ID = 0;
4498 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
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