1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
44 NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
57 // Select which memory operand is being unfolded.
58 // (stored in bits 0 - 3)
65 // Do not insert the reverse map (MemOp -> RegOp) into the table.
66 // This may be needed because there is a many -> one mapping.
67 TB_NO_REVERSE = 1 << 4,
69 // Do not insert the forward map (RegOp -> MemOp) into the table.
70 // This is needed for Native Client, which prohibits branch
71 // instructions from using a memory operand.
72 TB_NO_FORWARD = 1 << 5,
74 TB_FOLDED_LOAD = 1 << 6,
75 TB_FOLDED_STORE = 1 << 7,
77 // Minimum alignment required for load/store.
78 // Used for RegOp->MemOp conversion.
79 // (stored in bits 8 - 15)
81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
84 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
85 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
88 struct X86OpTblEntry {
94 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
95 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
96 ? X86::ADJCALLSTACKDOWN64
97 : X86::ADJCALLSTACKDOWN32),
98 (tm.getSubtarget<X86Subtarget>().is64Bit()
99 ? X86::ADJCALLSTACKUP64
100 : X86::ADJCALLSTACKUP32)),
103 static const X86OpTblEntry OpTbl2Addr[] = {
104 { X86::ADC32ri, X86::ADC32mi, 0 },
105 { X86::ADC32ri8, X86::ADC32mi8, 0 },
106 { X86::ADC32rr, X86::ADC32mr, 0 },
107 { X86::ADC64ri32, X86::ADC64mi32, 0 },
108 { X86::ADC64ri8, X86::ADC64mi8, 0 },
109 { X86::ADC64rr, X86::ADC64mr, 0 },
110 { X86::ADD16ri, X86::ADD16mi, 0 },
111 { X86::ADD16ri8, X86::ADD16mi8, 0 },
112 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
113 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
114 { X86::ADD16rr, X86::ADD16mr, 0 },
115 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
116 { X86::ADD32ri, X86::ADD32mi, 0 },
117 { X86::ADD32ri8, X86::ADD32mi8, 0 },
118 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
119 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
120 { X86::ADD32rr, X86::ADD32mr, 0 },
121 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
122 { X86::ADD64ri32, X86::ADD64mi32, 0 },
123 { X86::ADD64ri8, X86::ADD64mi8, 0 },
124 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
125 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
126 { X86::ADD64rr, X86::ADD64mr, 0 },
127 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
128 { X86::ADD8ri, X86::ADD8mi, 0 },
129 { X86::ADD8rr, X86::ADD8mr, 0 },
130 { X86::AND16ri, X86::AND16mi, 0 },
131 { X86::AND16ri8, X86::AND16mi8, 0 },
132 { X86::AND16rr, X86::AND16mr, 0 },
133 { X86::AND32ri, X86::AND32mi, 0 },
134 { X86::AND32ri8, X86::AND32mi8, 0 },
135 { X86::AND32rr, X86::AND32mr, 0 },
136 { X86::AND64ri32, X86::AND64mi32, 0 },
137 { X86::AND64ri8, X86::AND64mi8, 0 },
138 { X86::AND64rr, X86::AND64mr, 0 },
139 { X86::AND8ri, X86::AND8mi, 0 },
140 { X86::AND8rr, X86::AND8mr, 0 },
141 { X86::DEC16r, X86::DEC16m, 0 },
142 { X86::DEC32r, X86::DEC32m, 0 },
143 { X86::DEC64_16r, X86::DEC64_16m, 0 },
144 { X86::DEC64_32r, X86::DEC64_32m, 0 },
145 { X86::DEC64r, X86::DEC64m, 0 },
146 { X86::DEC8r, X86::DEC8m, 0 },
147 { X86::INC16r, X86::INC16m, 0 },
148 { X86::INC32r, X86::INC32m, 0 },
149 { X86::INC64_16r, X86::INC64_16m, 0 },
150 { X86::INC64_32r, X86::INC64_32m, 0 },
151 { X86::INC64r, X86::INC64m, 0 },
152 { X86::INC8r, X86::INC8m, 0 },
153 { X86::NEG16r, X86::NEG16m, 0 },
154 { X86::NEG32r, X86::NEG32m, 0 },
155 { X86::NEG64r, X86::NEG64m, 0 },
156 { X86::NEG8r, X86::NEG8m, 0 },
157 { X86::NOT16r, X86::NOT16m, 0 },
158 { X86::NOT32r, X86::NOT32m, 0 },
159 { X86::NOT64r, X86::NOT64m, 0 },
160 { X86::NOT8r, X86::NOT8m, 0 },
161 { X86::OR16ri, X86::OR16mi, 0 },
162 { X86::OR16ri8, X86::OR16mi8, 0 },
163 { X86::OR16rr, X86::OR16mr, 0 },
164 { X86::OR32ri, X86::OR32mi, 0 },
165 { X86::OR32ri8, X86::OR32mi8, 0 },
166 { X86::OR32rr, X86::OR32mr, 0 },
167 { X86::OR64ri32, X86::OR64mi32, 0 },
168 { X86::OR64ri8, X86::OR64mi8, 0 },
169 { X86::OR64rr, X86::OR64mr, 0 },
170 { X86::OR8ri, X86::OR8mi, 0 },
171 { X86::OR8rr, X86::OR8mr, 0 },
172 { X86::ROL16r1, X86::ROL16m1, 0 },
173 { X86::ROL16rCL, X86::ROL16mCL, 0 },
174 { X86::ROL16ri, X86::ROL16mi, 0 },
175 { X86::ROL32r1, X86::ROL32m1, 0 },
176 { X86::ROL32rCL, X86::ROL32mCL, 0 },
177 { X86::ROL32ri, X86::ROL32mi, 0 },
178 { X86::ROL64r1, X86::ROL64m1, 0 },
179 { X86::ROL64rCL, X86::ROL64mCL, 0 },
180 { X86::ROL64ri, X86::ROL64mi, 0 },
181 { X86::ROL8r1, X86::ROL8m1, 0 },
182 { X86::ROL8rCL, X86::ROL8mCL, 0 },
183 { X86::ROL8ri, X86::ROL8mi, 0 },
184 { X86::ROR16r1, X86::ROR16m1, 0 },
185 { X86::ROR16rCL, X86::ROR16mCL, 0 },
186 { X86::ROR16ri, X86::ROR16mi, 0 },
187 { X86::ROR32r1, X86::ROR32m1, 0 },
188 { X86::ROR32rCL, X86::ROR32mCL, 0 },
189 { X86::ROR32ri, X86::ROR32mi, 0 },
190 { X86::ROR64r1, X86::ROR64m1, 0 },
191 { X86::ROR64rCL, X86::ROR64mCL, 0 },
192 { X86::ROR64ri, X86::ROR64mi, 0 },
193 { X86::ROR8r1, X86::ROR8m1, 0 },
194 { X86::ROR8rCL, X86::ROR8mCL, 0 },
195 { X86::ROR8ri, X86::ROR8mi, 0 },
196 { X86::SAR16r1, X86::SAR16m1, 0 },
197 { X86::SAR16rCL, X86::SAR16mCL, 0 },
198 { X86::SAR16ri, X86::SAR16mi, 0 },
199 { X86::SAR32r1, X86::SAR32m1, 0 },
200 { X86::SAR32rCL, X86::SAR32mCL, 0 },
201 { X86::SAR32ri, X86::SAR32mi, 0 },
202 { X86::SAR64r1, X86::SAR64m1, 0 },
203 { X86::SAR64rCL, X86::SAR64mCL, 0 },
204 { X86::SAR64ri, X86::SAR64mi, 0 },
205 { X86::SAR8r1, X86::SAR8m1, 0 },
206 { X86::SAR8rCL, X86::SAR8mCL, 0 },
207 { X86::SAR8ri, X86::SAR8mi, 0 },
208 { X86::SBB32ri, X86::SBB32mi, 0 },
209 { X86::SBB32ri8, X86::SBB32mi8, 0 },
210 { X86::SBB32rr, X86::SBB32mr, 0 },
211 { X86::SBB64ri32, X86::SBB64mi32, 0 },
212 { X86::SBB64ri8, X86::SBB64mi8, 0 },
213 { X86::SBB64rr, X86::SBB64mr, 0 },
214 { X86::SHL16rCL, X86::SHL16mCL, 0 },
215 { X86::SHL16ri, X86::SHL16mi, 0 },
216 { X86::SHL32rCL, X86::SHL32mCL, 0 },
217 { X86::SHL32ri, X86::SHL32mi, 0 },
218 { X86::SHL64rCL, X86::SHL64mCL, 0 },
219 { X86::SHL64ri, X86::SHL64mi, 0 },
220 { X86::SHL8rCL, X86::SHL8mCL, 0 },
221 { X86::SHL8ri, X86::SHL8mi, 0 },
222 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
223 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
224 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
225 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
226 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
227 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
228 { X86::SHR16r1, X86::SHR16m1, 0 },
229 { X86::SHR16rCL, X86::SHR16mCL, 0 },
230 { X86::SHR16ri, X86::SHR16mi, 0 },
231 { X86::SHR32r1, X86::SHR32m1, 0 },
232 { X86::SHR32rCL, X86::SHR32mCL, 0 },
233 { X86::SHR32ri, X86::SHR32mi, 0 },
234 { X86::SHR64r1, X86::SHR64m1, 0 },
235 { X86::SHR64rCL, X86::SHR64mCL, 0 },
236 { X86::SHR64ri, X86::SHR64mi, 0 },
237 { X86::SHR8r1, X86::SHR8m1, 0 },
238 { X86::SHR8rCL, X86::SHR8mCL, 0 },
239 { X86::SHR8ri, X86::SHR8mi, 0 },
240 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
241 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
242 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
243 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
244 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
245 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
246 { X86::SUB16ri, X86::SUB16mi, 0 },
247 { X86::SUB16ri8, X86::SUB16mi8, 0 },
248 { X86::SUB16rr, X86::SUB16mr, 0 },
249 { X86::SUB32ri, X86::SUB32mi, 0 },
250 { X86::SUB32ri8, X86::SUB32mi8, 0 },
251 { X86::SUB32rr, X86::SUB32mr, 0 },
252 { X86::SUB64ri32, X86::SUB64mi32, 0 },
253 { X86::SUB64ri8, X86::SUB64mi8, 0 },
254 { X86::SUB64rr, X86::SUB64mr, 0 },
255 { X86::SUB8ri, X86::SUB8mi, 0 },
256 { X86::SUB8rr, X86::SUB8mr, 0 },
257 { X86::XOR16ri, X86::XOR16mi, 0 },
258 { X86::XOR16ri8, X86::XOR16mi8, 0 },
259 { X86::XOR16rr, X86::XOR16mr, 0 },
260 { X86::XOR32ri, X86::XOR32mi, 0 },
261 { X86::XOR32ri8, X86::XOR32mi8, 0 },
262 { X86::XOR32rr, X86::XOR32mr, 0 },
263 { X86::XOR64ri32, X86::XOR64mi32, 0 },
264 { X86::XOR64ri8, X86::XOR64mi8, 0 },
265 { X86::XOR64rr, X86::XOR64mr, 0 },
266 { X86::XOR8ri, X86::XOR8mi, 0 },
267 { X86::XOR8rr, X86::XOR8mr, 0 }
270 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
271 unsigned RegOp = OpTbl2Addr[i].RegOp;
272 unsigned MemOp = OpTbl2Addr[i].MemOp;
273 unsigned Flags = OpTbl2Addr[i].Flags;
274 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
276 // Index 0, folded load and store, no alignment requirement.
277 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280 static const X86OpTblEntry OpTbl0[] = {
281 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
282 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
283 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
284 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
285 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
286 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
287 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
288 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
289 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
290 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
291 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
292 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
293 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
294 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
295 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
296 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
297 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
298 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
299 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
300 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
301 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
302 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
303 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
336 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
337 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
338 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
339 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
340 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
341 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
342 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
343 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
344 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
345 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
346 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
347 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
348 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
349 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
350 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
351 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
352 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
353 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
354 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
355 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
356 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
357 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
358 // AVX 128-bit versions of foldable instructions
359 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
360 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
361 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
362 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
367 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
369 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
370 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
371 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
372 // AVX 256-bit foldable instructions
373 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
374 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
377 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
378 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
379 // AVX-512 foldable instructions
380 { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }
383 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
384 unsigned RegOp = OpTbl0[i].RegOp;
385 unsigned MemOp = OpTbl0[i].MemOp;
386 unsigned Flags = OpTbl0[i].Flags;
387 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
388 RegOp, MemOp, TB_INDEX_0 | Flags);
391 static const X86OpTblEntry OpTbl1[] = {
392 { X86::CMP16rr, X86::CMP16rm, 0 },
393 { X86::CMP32rr, X86::CMP32rm, 0 },
394 { X86::CMP64rr, X86::CMP64rm, 0 },
395 { X86::CMP8rr, X86::CMP8rm, 0 },
396 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
397 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
398 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
399 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
400 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
401 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
402 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
403 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
404 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
405 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
406 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
407 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
408 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
409 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
410 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
411 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
412 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
413 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
414 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
415 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
416 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
417 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
418 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
419 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
420 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
421 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
422 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
423 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
424 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
425 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
426 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
427 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
428 { X86::MOV16rr, X86::MOV16rm, 0 },
429 { X86::MOV32rr, X86::MOV32rm, 0 },
430 { X86::MOV64rr, X86::MOV64rm, 0 },
431 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
432 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
433 { X86::MOV8rr, X86::MOV8rm, 0 },
434 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
435 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
436 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
437 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
438 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
439 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
440 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
441 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
442 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
443 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
444 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
445 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
446 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
447 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
448 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
449 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
450 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
451 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
452 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
453 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
454 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
455 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
456 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
457 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
458 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
459 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
460 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
461 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
462 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
463 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
464 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
465 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
466 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
467 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
468 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
469 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
470 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
471 { X86::SQRTSDr, X86::SQRTSDm, 0 },
472 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
473 { X86::SQRTSSr, X86::SQRTSSm, 0 },
474 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
475 { X86::TEST16rr, X86::TEST16rm, 0 },
476 { X86::TEST32rr, X86::TEST32rm, 0 },
477 { X86::TEST64rr, X86::TEST64rm, 0 },
478 { X86::TEST8rr, X86::TEST8rm, 0 },
479 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
480 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
481 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
482 // AVX 128-bit versions of foldable instructions
483 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
484 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
485 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
486 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
487 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
488 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
489 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
490 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
491 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
492 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
493 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
494 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
495 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
496 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
497 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
498 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
499 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
500 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
501 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
502 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
503 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
504 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
505 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
506 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
507 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
508 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
509 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
510 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
511 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
512 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
513 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
514 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
515 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
516 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
517 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
518 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
519 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
520 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
521 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
522 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
523 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
524 { X86::VRCPPSr, X86::VRCPPSm, 0 },
525 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
526 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
527 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
528 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
529 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
530 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
531 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
532 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
534 // AVX 256-bit foldable instructions
535 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
536 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
537 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
538 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
539 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
540 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
541 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
543 // AVX2 foldable instructions
544 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
545 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
546 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
547 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
548 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
549 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
550 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
551 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
552 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
553 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
554 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
555 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
556 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
558 // BMI/BMI2/LZCNT/POPCNT foldable instructions
559 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
560 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
561 { X86::BLSI32rr, X86::BLSI32rm, 0 },
562 { X86::BLSI64rr, X86::BLSI64rm, 0 },
563 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
564 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
565 { X86::BLSR32rr, X86::BLSR32rm, 0 },
566 { X86::BLSR64rr, X86::BLSR64rm, 0 },
567 { X86::BZHI32rr, X86::BZHI32rm, 0 },
568 { X86::BZHI64rr, X86::BZHI64rm, 0 },
569 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
570 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
571 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
572 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
573 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
574 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
575 { X86::RORX32ri, X86::RORX32mi, 0 },
576 { X86::RORX64ri, X86::RORX64mi, 0 },
577 { X86::SARX32rr, X86::SARX32rm, 0 },
578 { X86::SARX64rr, X86::SARX64rm, 0 },
579 { X86::SHRX32rr, X86::SHRX32rm, 0 },
580 { X86::SHRX64rr, X86::SHRX64rm, 0 },
581 { X86::SHLX32rr, X86::SHLX32rm, 0 },
582 { X86::SHLX64rr, X86::SHLX64rm, 0 },
583 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
584 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
585 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
587 // AVX-512 foldable instructions
588 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
589 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
590 { X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 },
591 { X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 },
592 { X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 },
593 { X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 },
596 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
597 unsigned RegOp = OpTbl1[i].RegOp;
598 unsigned MemOp = OpTbl1[i].MemOp;
599 unsigned Flags = OpTbl1[i].Flags;
600 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
602 // Index 1, folded load
603 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
606 static const X86OpTblEntry OpTbl2[] = {
607 { X86::ADC32rr, X86::ADC32rm, 0 },
608 { X86::ADC64rr, X86::ADC64rm, 0 },
609 { X86::ADD16rr, X86::ADD16rm, 0 },
610 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
611 { X86::ADD32rr, X86::ADD32rm, 0 },
612 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
613 { X86::ADD64rr, X86::ADD64rm, 0 },
614 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
615 { X86::ADD8rr, X86::ADD8rm, 0 },
616 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
617 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
618 { X86::ADDSDrr, X86::ADDSDrm, 0 },
619 { X86::ADDSSrr, X86::ADDSSrm, 0 },
620 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
621 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
622 { X86::AND16rr, X86::AND16rm, 0 },
623 { X86::AND32rr, X86::AND32rm, 0 },
624 { X86::AND64rr, X86::AND64rm, 0 },
625 { X86::AND8rr, X86::AND8rm, 0 },
626 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
627 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
628 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
629 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
630 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
631 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
632 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
633 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
634 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
635 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
636 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
637 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
638 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
639 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
640 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
641 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
642 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
643 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
644 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
645 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
646 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
647 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
648 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
649 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
650 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
651 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
652 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
653 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
654 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
655 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
656 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
657 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
658 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
659 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
660 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
661 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
662 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
663 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
664 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
665 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
666 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
667 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
668 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
669 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
670 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
671 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
672 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
673 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
674 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
675 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
676 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
677 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
678 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
679 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
680 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
681 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
682 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
683 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
684 { X86::CMPSDrr, X86::CMPSDrm, 0 },
685 { X86::CMPSSrr, X86::CMPSSrm, 0 },
686 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
687 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
688 { X86::DIVSDrr, X86::DIVSDrm, 0 },
689 { X86::DIVSSrr, X86::DIVSSrm, 0 },
690 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
691 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
692 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
693 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
694 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
695 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
696 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
697 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
698 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
699 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
700 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
701 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
702 { X86::IMUL16rr, X86::IMUL16rm, 0 },
703 { X86::IMUL32rr, X86::IMUL32rm, 0 },
704 { X86::IMUL64rr, X86::IMUL64rm, 0 },
705 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
706 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
707 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
708 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
709 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
710 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
711 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
712 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
713 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
714 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
715 { X86::MAXSDrr, X86::MAXSDrm, 0 },
716 { X86::MAXSSrr, X86::MAXSSrm, 0 },
717 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
718 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
719 { X86::MINSDrr, X86::MINSDrm, 0 },
720 { X86::MINSSrr, X86::MINSSrm, 0 },
721 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
722 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
723 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
724 { X86::MULSDrr, X86::MULSDrm, 0 },
725 { X86::MULSSrr, X86::MULSSrm, 0 },
726 { X86::OR16rr, X86::OR16rm, 0 },
727 { X86::OR32rr, X86::OR32rm, 0 },
728 { X86::OR64rr, X86::OR64rm, 0 },
729 { X86::OR8rr, X86::OR8rm, 0 },
730 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
731 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
732 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
733 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
734 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
735 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
736 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
737 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
738 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
739 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
740 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
741 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
742 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
743 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
744 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
745 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
746 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
747 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
748 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
749 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
750 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
751 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
752 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
753 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
754 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
755 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
756 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
757 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
758 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
759 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
760 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
761 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
762 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
763 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
764 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
765 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
766 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
767 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
768 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
769 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
770 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
771 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
772 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
773 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
774 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
775 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
776 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
777 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
778 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
779 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
780 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
781 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
782 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
783 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
784 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
785 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
786 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
787 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
788 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
789 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
790 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
791 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
792 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
793 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
794 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
795 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
796 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
797 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
798 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
799 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
800 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
801 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
802 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
803 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
804 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
805 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
806 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
807 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
808 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
809 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
810 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
811 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
812 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
813 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
814 { X86::SBB32rr, X86::SBB32rm, 0 },
815 { X86::SBB64rr, X86::SBB64rm, 0 },
816 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
817 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
818 { X86::SUB16rr, X86::SUB16rm, 0 },
819 { X86::SUB32rr, X86::SUB32rm, 0 },
820 { X86::SUB64rr, X86::SUB64rm, 0 },
821 { X86::SUB8rr, X86::SUB8rm, 0 },
822 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
823 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
824 { X86::SUBSDrr, X86::SUBSDrm, 0 },
825 { X86::SUBSSrr, X86::SUBSSrm, 0 },
826 // FIXME: TEST*rr -> swapped operand of TEST*mr.
827 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
828 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
829 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
830 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
831 { X86::XOR16rr, X86::XOR16rm, 0 },
832 { X86::XOR32rr, X86::XOR32rm, 0 },
833 { X86::XOR64rr, X86::XOR64rm, 0 },
834 { X86::XOR8rr, X86::XOR8rm, 0 },
835 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
836 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
837 // AVX 128-bit versions of foldable instructions
838 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
839 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
840 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
841 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
842 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
843 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
844 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
845 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
846 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
847 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
848 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
849 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
850 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
851 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
852 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
853 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
854 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
855 { X86::VADDPDrr, X86::VADDPDrm, 0 },
856 { X86::VADDPSrr, X86::VADDPSrm, 0 },
857 { X86::VADDSDrr, X86::VADDSDrm, 0 },
858 { X86::VADDSSrr, X86::VADDSSrm, 0 },
859 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
860 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
861 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
862 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
863 { X86::VANDPDrr, X86::VANDPDrm, 0 },
864 { X86::VANDPSrr, X86::VANDPSrm, 0 },
865 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
866 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
867 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
868 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
869 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
870 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
871 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
872 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
873 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
874 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
875 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
876 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
877 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
878 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
879 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
880 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
881 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
882 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
883 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
884 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
885 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
886 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
887 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
888 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
889 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
890 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
891 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
892 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
893 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
894 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
895 { X86::VMINPDrr, X86::VMINPDrm, 0 },
896 { X86::VMINPSrr, X86::VMINPSrm, 0 },
897 { X86::VMINSDrr, X86::VMINSDrm, 0 },
898 { X86::VMINSSrr, X86::VMINSSrm, 0 },
899 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
900 { X86::VMULPDrr, X86::VMULPDrm, 0 },
901 { X86::VMULPSrr, X86::VMULPSrm, 0 },
902 { X86::VMULSDrr, X86::VMULSDrm, 0 },
903 { X86::VMULSSrr, X86::VMULSSrm, 0 },
904 { X86::VORPDrr, X86::VORPDrm, 0 },
905 { X86::VORPSrr, X86::VORPSrm, 0 },
906 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
907 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
908 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
909 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
910 { X86::VPADDBrr, X86::VPADDBrm, 0 },
911 { X86::VPADDDrr, X86::VPADDDrm, 0 },
912 { X86::VPADDQrr, X86::VPADDQrm, 0 },
913 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
914 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
915 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
916 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
917 { X86::VPADDWrr, X86::VPADDWrm, 0 },
918 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
919 { X86::VPANDNrr, X86::VPANDNrm, 0 },
920 { X86::VPANDrr, X86::VPANDrm, 0 },
921 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
922 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
923 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
924 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
925 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
926 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
927 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
928 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
929 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
930 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
931 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
932 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
933 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
934 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
935 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
936 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
937 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
938 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
939 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
940 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
941 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
942 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
943 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
944 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
945 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
946 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
947 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
948 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
949 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
950 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
951 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
952 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
953 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
954 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
955 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
956 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
957 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
958 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
959 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
960 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
961 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
962 { X86::VPORrr, X86::VPORrm, 0 },
963 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
964 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
965 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
966 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
967 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
968 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
969 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
970 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
971 { X86::VPSRADrr, X86::VPSRADrm, 0 },
972 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
973 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
974 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
975 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
976 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
977 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
978 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
979 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
980 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
981 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
982 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
983 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
984 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
985 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
986 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
987 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
988 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
989 { X86::VPXORrr, X86::VPXORrm, 0 },
990 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
991 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
992 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
993 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
994 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
995 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
996 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
997 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
998 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
999 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1000 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1001 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1002 // AVX 256-bit foldable instructions
1003 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1004 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1005 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1006 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1007 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1008 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1009 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1010 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1011 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1012 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1013 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1014 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1015 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1016 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1017 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1018 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1019 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1020 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1021 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1022 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1023 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1024 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1025 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1026 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1027 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1028 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1029 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1030 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1031 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1032 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1033 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1034 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1035 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1036 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1037 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1038 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1039 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1040 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1041 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1042 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1043 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1044 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1045 // AVX2 foldable instructions
1046 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1047 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1048 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1049 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1050 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1051 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1052 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1053 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1054 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1055 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1056 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1057 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1058 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1059 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1060 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1061 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1062 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1063 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1064 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1065 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1066 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1067 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1068 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1069 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1070 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1071 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1072 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1073 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1074 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1075 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1076 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1077 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
1078 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1079 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
1080 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1081 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1082 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1083 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1084 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1085 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1086 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1087 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1088 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1089 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1090 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1091 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1092 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1093 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1094 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1095 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1096 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1097 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1098 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1099 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1100 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1101 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1102 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1103 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1104 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1105 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1106 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1107 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1108 { X86::VPORYrr, X86::VPORYrm, 0 },
1109 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1110 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1111 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1112 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1113 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1114 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1115 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1116 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1117 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1118 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1119 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1120 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1121 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1122 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1123 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1124 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1125 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1126 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1127 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1128 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1129 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1130 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1131 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1132 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1133 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1134 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1135 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1136 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1137 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1138 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1139 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1140 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1141 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1142 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1143 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1144 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1145 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1146 // FIXME: add AVX 256-bit foldable instructions
1148 // FMA4 foldable patterns
1149 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1150 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1151 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1152 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1153 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1154 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
1155 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1156 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1157 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1158 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1159 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1160 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
1161 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1162 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1163 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1164 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1165 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1166 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
1167 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1168 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1169 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1170 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1171 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1172 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1173 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1174 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1175 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1176 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1177 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1178 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1179 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1180 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
1182 // BMI/BMI2 foldable instructions
1183 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1184 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1185 { X86::MULX32rr, X86::MULX32rm, 0 },
1186 { X86::MULX64rr, X86::MULX64rm, 0 },
1187 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1188 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1189 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1190 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1192 // AVX-512 foldable instructions
1193 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1194 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1195 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1196 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1197 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1198 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1199 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1200 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1201 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1202 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1203 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1204 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1205 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1206 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1207 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1208 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1209 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1210 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1211 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1212 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
1213 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1214 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1215 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1216 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1217 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1218 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1219 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1220 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1221 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
1224 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1225 unsigned RegOp = OpTbl2[i].RegOp;
1226 unsigned MemOp = OpTbl2[i].MemOp;
1227 unsigned Flags = OpTbl2[i].Flags;
1228 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1230 // Index 2, folded load
1231 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1234 static const X86OpTblEntry OpTbl3[] = {
1235 // FMA foldable instructions
1236 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 },
1237 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 },
1238 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 },
1239 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 },
1240 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 },
1241 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 },
1242 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 },
1243 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 },
1245 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 },
1246 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 },
1247 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 },
1248 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 },
1249 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 },
1250 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 },
1251 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 },
1252 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 },
1253 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 },
1254 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
1255 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
1256 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
1258 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
1259 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
1260 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 },
1261 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 },
1262 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 },
1263 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 },
1264 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 },
1265 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 },
1267 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 },
1268 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 },
1269 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 },
1270 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 },
1271 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 },
1272 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 },
1273 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 },
1274 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 },
1275 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 },
1276 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
1277 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
1278 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
1280 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
1281 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
1282 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 },
1283 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 },
1284 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 },
1285 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 },
1286 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 },
1287 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 },
1289 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 },
1290 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 },
1291 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 },
1292 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 },
1293 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 },
1294 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 },
1295 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 },
1296 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 },
1297 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 },
1298 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
1299 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
1300 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
1302 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 },
1303 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 },
1304 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 },
1305 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 },
1306 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 },
1307 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 },
1308 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 },
1309 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 },
1311 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 },
1312 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 },
1313 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 },
1314 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 },
1315 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 },
1316 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 },
1317 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 },
1318 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 },
1319 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 },
1320 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 },
1321 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 },
1322 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 },
1324 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 },
1325 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 },
1326 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 },
1327 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 },
1328 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 },
1329 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 },
1330 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 },
1331 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 },
1332 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 },
1333 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 },
1334 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 },
1335 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 },
1337 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 },
1338 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 },
1339 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 },
1340 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 },
1341 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 },
1342 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 },
1343 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 },
1344 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 },
1345 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 },
1346 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 },
1347 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 },
1348 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 },
1350 // FMA4 foldable patterns
1351 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1352 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
1353 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1354 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1355 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1356 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
1357 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1358 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
1359 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1360 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1361 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1362 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
1363 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1364 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
1365 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1366 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1367 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1368 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
1369 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1370 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
1371 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1372 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1373 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1374 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1375 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1376 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1377 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1378 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1379 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1380 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1381 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1382 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
1385 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1386 unsigned RegOp = OpTbl3[i].RegOp;
1387 unsigned MemOp = OpTbl3[i].MemOp;
1388 unsigned Flags = OpTbl3[i].Flags;
1389 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1391 // Index 3, folded load
1392 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1398 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1399 MemOp2RegOpTableType &M2RTable,
1400 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1401 if ((Flags & TB_NO_FORWARD) == 0) {
1402 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1403 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1405 if ((Flags & TB_NO_REVERSE) == 0) {
1406 assert(!M2RTable.count(MemOp) &&
1407 "Duplicated entries in unfolding maps?");
1408 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1413 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1414 unsigned &SrcReg, unsigned &DstReg,
1415 unsigned &SubIdx) const {
1416 switch (MI.getOpcode()) {
1418 case X86::MOVSX16rr8:
1419 case X86::MOVZX16rr8:
1420 case X86::MOVSX32rr8:
1421 case X86::MOVZX32rr8:
1422 case X86::MOVSX64rr8:
1423 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1424 // It's not always legal to reference the low 8-bit of the larger
1425 // register in 32-bit mode.
1427 case X86::MOVSX32rr16:
1428 case X86::MOVZX32rr16:
1429 case X86::MOVSX64rr16:
1430 case X86::MOVSX64rr32: {
1431 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1434 SrcReg = MI.getOperand(1).getReg();
1435 DstReg = MI.getOperand(0).getReg();
1436 switch (MI.getOpcode()) {
1437 default: llvm_unreachable("Unreachable!");
1438 case X86::MOVSX16rr8:
1439 case X86::MOVZX16rr8:
1440 case X86::MOVSX32rr8:
1441 case X86::MOVZX32rr8:
1442 case X86::MOVSX64rr8:
1443 SubIdx = X86::sub_8bit;
1445 case X86::MOVSX32rr16:
1446 case X86::MOVZX32rr16:
1447 case X86::MOVSX64rr16:
1448 SubIdx = X86::sub_16bit;
1450 case X86::MOVSX64rr32:
1451 SubIdx = X86::sub_32bit;
1460 /// isFrameOperand - Return true and the FrameIndex if the specified
1461 /// operand and follow operands form a reference to the stack frame.
1462 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1463 int &FrameIndex) const {
1464 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1465 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1466 MI->getOperand(Op+1).getImm() == 1 &&
1467 MI->getOperand(Op+2).getReg() == 0 &&
1468 MI->getOperand(Op+3).getImm() == 0) {
1469 FrameIndex = MI->getOperand(Op).getIndex();
1475 static bool isFrameLoadOpcode(int Opcode) {
1491 case X86::VMOVAPSrm:
1492 case X86::VMOVAPDrm:
1493 case X86::VMOVDQArm:
1494 case X86::VMOVAPSYrm:
1495 case X86::VMOVAPDYrm:
1496 case X86::VMOVDQAYrm:
1497 case X86::MMX_MOVD64rm:
1498 case X86::MMX_MOVQ64rm:
1499 case X86::VMOVDQA32rm:
1500 case X86::VMOVDQA64rm:
1505 static bool isFrameStoreOpcode(int Opcode) {
1512 case X86::ST_FpP64m:
1520 case X86::VMOVAPSmr:
1521 case X86::VMOVAPDmr:
1522 case X86::VMOVDQAmr:
1523 case X86::VMOVAPSYmr:
1524 case X86::VMOVAPDYmr:
1525 case X86::VMOVDQAYmr:
1526 case X86::MMX_MOVD64mr:
1527 case X86::MMX_MOVQ64mr:
1528 case X86::MMX_MOVNTQmr:
1534 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1535 int &FrameIndex) const {
1536 if (isFrameLoadOpcode(MI->getOpcode()))
1537 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1538 return MI->getOperand(0).getReg();
1542 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1543 int &FrameIndex) const {
1544 if (isFrameLoadOpcode(MI->getOpcode())) {
1546 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1548 // Check for post-frame index elimination operations
1549 const MachineMemOperand *Dummy;
1550 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1555 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1556 int &FrameIndex) const {
1557 if (isFrameStoreOpcode(MI->getOpcode()))
1558 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1559 isFrameOperand(MI, 0, FrameIndex))
1560 return MI->getOperand(X86::AddrNumOperands).getReg();
1564 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1565 int &FrameIndex) const {
1566 if (isFrameStoreOpcode(MI->getOpcode())) {
1568 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1570 // Check for post-frame index elimination operations
1571 const MachineMemOperand *Dummy;
1572 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1577 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1579 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1580 // Don't waste compile time scanning use-def chains of physregs.
1581 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1583 bool isPICBase = false;
1584 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1585 E = MRI.def_end(); I != E; ++I) {
1586 MachineInstr *DefMI = I.getOperand().getParent();
1587 if (DefMI->getOpcode() != X86::MOVPC32r)
1589 assert(!isPICBase && "More than one PIC base?");
1596 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1597 AliasAnalysis *AA) const {
1598 switch (MI->getOpcode()) {
1614 case X86::VMOVAPSrm:
1615 case X86::VMOVUPSrm:
1616 case X86::VMOVAPDrm:
1617 case X86::VMOVDQArm:
1618 case X86::VMOVDQUrm:
1619 case X86::VMOVAPSYrm:
1620 case X86::VMOVUPSYrm:
1621 case X86::VMOVAPDYrm:
1622 case X86::VMOVDQAYrm:
1623 case X86::VMOVDQUYrm:
1624 case X86::MMX_MOVD64rm:
1625 case X86::MMX_MOVQ64rm:
1626 case X86::FsVMOVAPSrm:
1627 case X86::FsVMOVAPDrm:
1628 case X86::FsMOVAPSrm:
1629 case X86::FsMOVAPDrm: {
1630 // Loads from constant pools are trivially rematerializable.
1631 if (MI->getOperand(1).isReg() &&
1632 MI->getOperand(2).isImm() &&
1633 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1634 MI->isInvariantLoad(AA)) {
1635 unsigned BaseReg = MI->getOperand(1).getReg();
1636 if (BaseReg == 0 || BaseReg == X86::RIP)
1638 // Allow re-materialization of PIC load.
1639 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1641 const MachineFunction &MF = *MI->getParent()->getParent();
1642 const MachineRegisterInfo &MRI = MF.getRegInfo();
1643 return regIsPICBase(BaseReg, MRI);
1650 if (MI->getOperand(2).isImm() &&
1651 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1652 !MI->getOperand(4).isReg()) {
1653 // lea fi#, lea GV, etc. are all rematerializable.
1654 if (!MI->getOperand(1).isReg())
1656 unsigned BaseReg = MI->getOperand(1).getReg();
1659 // Allow re-materialization of lea PICBase + x.
1660 const MachineFunction &MF = *MI->getParent()->getParent();
1661 const MachineRegisterInfo &MRI = MF.getRegInfo();
1662 return regIsPICBase(BaseReg, MRI);
1668 // All other instructions marked M_REMATERIALIZABLE are always trivially
1669 // rematerializable.
1673 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1674 /// would clobber the EFLAGS condition register. Note the result may be
1675 /// conservative. If it cannot definitely determine the safety after visiting
1676 /// a few instructions in each direction it assumes it's not safe.
1677 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1678 MachineBasicBlock::iterator I) {
1679 MachineBasicBlock::iterator E = MBB.end();
1681 // For compile time consideration, if we are not able to determine the
1682 // safety after visiting 4 instructions in each direction, we will assume
1684 MachineBasicBlock::iterator Iter = I;
1685 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1686 bool SeenDef = false;
1687 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1688 MachineOperand &MO = Iter->getOperand(j);
1689 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1693 if (MO.getReg() == X86::EFLAGS) {
1701 // This instruction defines EFLAGS, no need to look any further.
1704 // Skip over DBG_VALUE.
1705 while (Iter != E && Iter->isDebugValue())
1709 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1712 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1713 SE = MBB.succ_end(); SI != SE; ++SI)
1714 if ((*SI)->isLiveIn(X86::EFLAGS))
1719 MachineBasicBlock::iterator B = MBB.begin();
1721 for (unsigned i = 0; i < 4; ++i) {
1722 // If we make it to the beginning of the block, it's safe to clobber
1723 // EFLAGS iff EFLAGS is not live-in.
1725 return !MBB.isLiveIn(X86::EFLAGS);
1728 // Skip over DBG_VALUE.
1729 while (Iter != B && Iter->isDebugValue())
1732 bool SawKill = false;
1733 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1734 MachineOperand &MO = Iter->getOperand(j);
1735 // A register mask may clobber EFLAGS, but we should still look for a
1737 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1739 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1740 if (MO.isDef()) return MO.isDead();
1741 if (MO.isKill()) SawKill = true;
1746 // This instruction kills EFLAGS and doesn't redefine it, so
1747 // there's no need to look further.
1751 // Conservative answer.
1755 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1756 MachineBasicBlock::iterator I,
1757 unsigned DestReg, unsigned SubIdx,
1758 const MachineInstr *Orig,
1759 const TargetRegisterInfo &TRI) const {
1760 // MOV32r0 is implemented with a xor which clobbers condition code.
1761 // Re-materialize it as movri instructions to avoid side effects.
1762 unsigned Opc = Orig->getOpcode();
1763 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1764 DebugLoc DL = Orig->getDebugLoc();
1765 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1768 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1772 MachineInstr *NewMI = prior(I);
1773 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1776 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1777 /// is not marked dead.
1778 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1779 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1780 MachineOperand &MO = MI->getOperand(i);
1781 if (MO.isReg() && MO.isDef() &&
1782 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1789 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1791 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1792 unsigned ShiftAmtOperandIdx) {
1793 // The shift count is six bits with the REX.W prefix and five bits without.
1794 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1795 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1796 return Imm & ShiftCountMask;
1799 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1800 /// can be represented by a LEA instruction.
1801 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1802 // Left shift instructions can be transformed into load-effective-address
1803 // instructions if we can encode them appropriately.
1804 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1805 // The SIB.scale field is two bits wide which means that we can encode any
1806 // shift amount less than 4.
1807 return ShAmt < 4 && ShAmt > 0;
1810 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1811 unsigned Opc, bool AllowSP,
1812 unsigned &NewSrc, bool &isKill, bool &isUndef,
1813 MachineOperand &ImplicitOp) const {
1814 MachineFunction &MF = *MI->getParent()->getParent();
1815 const TargetRegisterClass *RC;
1817 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1819 RC = Opc != X86::LEA32r ?
1820 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1822 unsigned SrcReg = Src.getReg();
1824 // For both LEA64 and LEA32 the register already has essentially the right
1825 // type (32-bit or 64-bit) we may just need to forbid SP.
1826 if (Opc != X86::LEA64_32r) {
1828 isKill = Src.isKill();
1829 isUndef = Src.isUndef();
1831 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1832 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1838 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1839 // another we need to add 64-bit registers to the final MI.
1840 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1842 ImplicitOp.setImplicit();
1844 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1845 MachineBasicBlock::LivenessQueryResult LQR =
1846 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1849 case MachineBasicBlock::LQR_Unknown:
1850 // We can't give sane liveness flags to the instruction, abandon LEA
1853 case MachineBasicBlock::LQR_Live:
1854 isKill = MI->killsRegister(SrcReg);
1858 // The physreg itself is dead, so we have to use it as an <undef>.
1864 // Virtual register of the wrong class, we have to create a temporary 64-bit
1865 // vreg to feed into the LEA.
1866 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1867 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1868 get(TargetOpcode::COPY))
1869 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1872 // Which is obviously going to be dead after we're done with it.
1877 // We've set all the parameters without issue.
1881 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1882 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1883 /// to a 32-bit superregister and then truncating back down to a 16-bit
1886 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1887 MachineFunction::iterator &MFI,
1888 MachineBasicBlock::iterator &MBBI,
1889 LiveVariables *LV) const {
1890 MachineInstr *MI = MBBI;
1891 unsigned Dest = MI->getOperand(0).getReg();
1892 unsigned Src = MI->getOperand(1).getReg();
1893 bool isDead = MI->getOperand(0).isDead();
1894 bool isKill = MI->getOperand(1).isKill();
1896 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1897 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1898 unsigned Opc, leaInReg;
1899 if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1900 Opc = X86::LEA64_32r;
1901 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1904 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1907 // Build and insert into an implicit UNDEF value. This is OK because
1908 // well be shifting and then extracting the lower 16-bits.
1909 // This has the potential to cause partial register stall. e.g.
1910 // movw (%rbp,%rcx,2), %dx
1911 // leal -65(%rdx), %esi
1912 // But testing has shown this *does* help performance in 64-bit mode (at
1913 // least on modern x86 machines).
1914 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1915 MachineInstr *InsMI =
1916 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1917 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1918 .addReg(Src, getKillRegState(isKill));
1920 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1921 get(Opc), leaOutReg);
1923 default: llvm_unreachable("Unreachable!");
1924 case X86::SHL16ri: {
1925 unsigned ShAmt = MI->getOperand(2).getImm();
1926 MIB.addReg(0).addImm(1 << ShAmt)
1927 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1931 case X86::INC64_16r:
1932 addRegOffset(MIB, leaInReg, true, 1);
1935 case X86::DEC64_16r:
1936 addRegOffset(MIB, leaInReg, true, -1);
1940 case X86::ADD16ri_DB:
1941 case X86::ADD16ri8_DB:
1942 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1945 case X86::ADD16rr_DB: {
1946 unsigned Src2 = MI->getOperand(2).getReg();
1947 bool isKill2 = MI->getOperand(2).isKill();
1948 unsigned leaInReg2 = 0;
1949 MachineInstr *InsMI2 = 0;
1951 // ADD16rr %reg1028<kill>, %reg1028
1952 // just a single insert_subreg.
1953 addRegReg(MIB, leaInReg, true, leaInReg, false);
1955 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1956 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1958 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1959 // Build and insert into an implicit UNDEF value. This is OK because
1960 // well be shifting and then extracting the lower 16-bits.
1961 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1963 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1964 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1965 .addReg(Src2, getKillRegState(isKill2));
1966 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1968 if (LV && isKill2 && InsMI2)
1969 LV->replaceKillInstruction(Src2, MI, InsMI2);
1974 MachineInstr *NewMI = MIB;
1975 MachineInstr *ExtMI =
1976 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1977 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1978 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1981 // Update live variables
1982 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1983 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1985 LV->replaceKillInstruction(Src, MI, InsMI);
1987 LV->replaceKillInstruction(Dest, MI, ExtMI);
1993 /// convertToThreeAddress - This method must be implemented by targets that
1994 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1995 /// may be able to convert a two-address instruction into a true
1996 /// three-address instruction on demand. This allows the X86 target (for
1997 /// example) to convert ADD and SHL instructions into LEA instructions if they
1998 /// would require register copies due to two-addressness.
2000 /// This method returns a null pointer if the transformation cannot be
2001 /// performed, otherwise it returns the new instruction.
2004 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2005 MachineBasicBlock::iterator &MBBI,
2006 LiveVariables *LV) const {
2007 MachineInstr *MI = MBBI;
2009 // The following opcodes also sets the condition code register(s). Only
2010 // convert them to equivalent lea if the condition code register def's
2012 if (hasLiveCondCodeDef(MI))
2015 MachineFunction &MF = *MI->getParent()->getParent();
2016 // All instructions input are two-addr instructions. Get the known operands.
2017 const MachineOperand &Dest = MI->getOperand(0);
2018 const MachineOperand &Src = MI->getOperand(1);
2020 MachineInstr *NewMI = NULL;
2021 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
2022 // we have better subtarget support, enable the 16-bit LEA generation here.
2023 // 16-bit LEA is also slow on Core2.
2024 bool DisableLEA16 = true;
2025 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2027 unsigned MIOpc = MI->getOpcode();
2029 case X86::SHUFPSrri: {
2030 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2031 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2033 unsigned B = MI->getOperand(1).getReg();
2034 unsigned C = MI->getOperand(2).getReg();
2035 if (B != C) return 0;
2036 unsigned M = MI->getOperand(3).getImm();
2037 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2038 .addOperand(Dest).addOperand(Src).addImm(M);
2041 case X86::SHUFPDrri: {
2042 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2043 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2045 unsigned B = MI->getOperand(1).getReg();
2046 unsigned C = MI->getOperand(2).getReg();
2047 if (B != C) return 0;
2048 unsigned M = MI->getOperand(3).getImm();
2050 // Convert to PSHUFD mask.
2051 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2053 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2054 .addOperand(Dest).addOperand(Src).addImm(M);
2057 case X86::SHL64ri: {
2058 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2059 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2060 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2062 // LEA can't handle RSP.
2063 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2064 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2065 &X86::GR64_NOSPRegClass))
2068 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2070 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2073 case X86::SHL32ri: {
2074 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2075 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2076 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2078 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2080 // LEA can't handle ESP.
2081 bool isKill, isUndef;
2083 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2084 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2085 SrcReg, isKill, isUndef, ImplicitOp))
2088 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2090 .addReg(0).addImm(1 << ShAmt)
2091 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2092 .addImm(0).addReg(0);
2093 if (ImplicitOp.getReg() != 0)
2094 MIB.addOperand(ImplicitOp);
2099 case X86::SHL16ri: {
2100 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2101 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2102 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2105 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2106 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2108 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2117 case X86::INC64_32r: {
2118 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2119 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2120 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2121 bool isKill, isUndef;
2123 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2124 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2125 SrcReg, isKill, isUndef, ImplicitOp))
2128 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2130 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2131 if (ImplicitOp.getReg() != 0)
2132 MIB.addOperand(ImplicitOp);
2134 NewMI = addOffset(MIB, 1);
2138 case X86::INC64_16r:
2140 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2141 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2142 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2143 .addOperand(Dest).addOperand(Src), 1);
2147 case X86::DEC64_32r: {
2148 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2149 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2150 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2152 bool isKill, isUndef;
2154 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2155 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2156 SrcReg, isKill, isUndef, ImplicitOp))
2159 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2161 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2162 if (ImplicitOp.getReg() != 0)
2163 MIB.addOperand(ImplicitOp);
2165 NewMI = addOffset(MIB, -1);
2170 case X86::DEC64_16r:
2172 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2173 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2174 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2175 .addOperand(Dest).addOperand(Src), -1);
2178 case X86::ADD64rr_DB:
2180 case X86::ADD32rr_DB: {
2181 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2183 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2186 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2188 bool isKill, isUndef;
2190 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2191 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2192 SrcReg, isKill, isUndef, ImplicitOp))
2195 const MachineOperand &Src2 = MI->getOperand(2);
2196 bool isKill2, isUndef2;
2198 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2199 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2200 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2203 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2205 if (ImplicitOp.getReg() != 0)
2206 MIB.addOperand(ImplicitOp);
2207 if (ImplicitOp2.getReg() != 0)
2208 MIB.addOperand(ImplicitOp2);
2210 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2212 // Preserve undefness of the operands.
2213 NewMI->getOperand(1).setIsUndef(isUndef);
2214 NewMI->getOperand(3).setIsUndef(isUndef2);
2216 if (LV && Src2.isKill())
2217 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2221 case X86::ADD16rr_DB: {
2223 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2224 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2225 unsigned Src2 = MI->getOperand(2).getReg();
2226 bool isKill2 = MI->getOperand(2).isKill();
2227 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2229 Src.getReg(), Src.isKill(), Src2, isKill2);
2231 // Preserve undefness of the operands.
2232 bool isUndef = MI->getOperand(1).isUndef();
2233 bool isUndef2 = MI->getOperand(2).isUndef();
2234 NewMI->getOperand(1).setIsUndef(isUndef);
2235 NewMI->getOperand(3).setIsUndef(isUndef2);
2238 LV->replaceKillInstruction(Src2, MI, NewMI);
2241 case X86::ADD64ri32:
2243 case X86::ADD64ri32_DB:
2244 case X86::ADD64ri8_DB:
2245 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2246 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2247 .addOperand(Dest).addOperand(Src),
2248 MI->getOperand(2).getImm());
2252 case X86::ADD32ri_DB:
2253 case X86::ADD32ri8_DB: {
2254 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2255 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2257 bool isKill, isUndef;
2259 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2260 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2261 SrcReg, isKill, isUndef, ImplicitOp))
2264 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2266 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2267 if (ImplicitOp.getReg() != 0)
2268 MIB.addOperand(ImplicitOp);
2270 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2275 case X86::ADD16ri_DB:
2276 case X86::ADD16ri8_DB:
2278 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2279 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2280 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2281 .addOperand(Dest).addOperand(Src),
2282 MI->getOperand(2).getImm());
2288 if (!NewMI) return 0;
2290 if (LV) { // Update live variables
2292 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2294 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2297 MFI->insert(MBBI, NewMI); // Insert the new inst
2301 /// commuteInstruction - We have a few instructions that must be hacked on to
2305 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2306 switch (MI->getOpcode()) {
2307 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2308 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2309 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2310 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2311 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2312 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2315 switch (MI->getOpcode()) {
2316 default: llvm_unreachable("Unreachable!");
2317 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2318 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2319 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2320 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2321 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2322 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2324 unsigned Amt = MI->getOperand(3).getImm();
2326 MachineFunction &MF = *MI->getParent()->getParent();
2327 MI = MF.CloneMachineInstr(MI);
2330 MI->setDesc(get(Opc));
2331 MI->getOperand(3).setImm(Size-Amt);
2332 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2334 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2335 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2336 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2337 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2338 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2339 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2340 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2341 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2342 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2343 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2344 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2345 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2346 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2347 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2348 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2349 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2351 switch (MI->getOpcode()) {
2352 default: llvm_unreachable("Unreachable!");
2353 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2354 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2355 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2356 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2357 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2358 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2359 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2360 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2361 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2362 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2363 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2364 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2365 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2366 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2367 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2368 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2369 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2370 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2371 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2372 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2373 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2374 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2375 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2376 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2377 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2378 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2379 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2380 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2381 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2382 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2383 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2384 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2385 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2386 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2387 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2388 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2389 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2390 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2391 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2392 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2393 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2394 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2395 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2396 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2397 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2398 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2399 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2400 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2403 MachineFunction &MF = *MI->getParent()->getParent();
2404 MI = MF.CloneMachineInstr(MI);
2407 MI->setDesc(get(Opc));
2408 // Fallthrough intended.
2411 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2415 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2417 default: return X86::COND_INVALID;
2418 case X86::JE_4: return X86::COND_E;
2419 case X86::JNE_4: return X86::COND_NE;
2420 case X86::JL_4: return X86::COND_L;
2421 case X86::JLE_4: return X86::COND_LE;
2422 case X86::JG_4: return X86::COND_G;
2423 case X86::JGE_4: return X86::COND_GE;
2424 case X86::JB_4: return X86::COND_B;
2425 case X86::JBE_4: return X86::COND_BE;
2426 case X86::JA_4: return X86::COND_A;
2427 case X86::JAE_4: return X86::COND_AE;
2428 case X86::JS_4: return X86::COND_S;
2429 case X86::JNS_4: return X86::COND_NS;
2430 case X86::JP_4: return X86::COND_P;
2431 case X86::JNP_4: return X86::COND_NP;
2432 case X86::JO_4: return X86::COND_O;
2433 case X86::JNO_4: return X86::COND_NO;
2437 /// getCondFromSETOpc - return condition code of a SET opcode.
2438 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2440 default: return X86::COND_INVALID;
2441 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2442 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2443 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2444 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2445 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2446 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2447 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2448 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2449 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2450 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2451 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2452 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2453 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2454 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2455 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2456 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2460 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2461 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2463 default: return X86::COND_INVALID;
2464 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2465 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2467 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2468 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2469 return X86::COND_AE;
2470 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2471 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2473 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2474 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2475 return X86::COND_BE;
2476 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2477 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2479 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2480 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2482 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2483 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2484 return X86::COND_GE;
2485 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2486 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2488 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2489 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2490 return X86::COND_LE;
2491 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2492 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2493 return X86::COND_NE;
2494 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2495 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2496 return X86::COND_NO;
2497 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2498 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2499 return X86::COND_NP;
2500 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2501 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2502 return X86::COND_NS;
2503 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2504 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2506 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2507 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2509 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2510 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2515 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2517 default: llvm_unreachable("Illegal condition code!");
2518 case X86::COND_E: return X86::JE_4;
2519 case X86::COND_NE: return X86::JNE_4;
2520 case X86::COND_L: return X86::JL_4;
2521 case X86::COND_LE: return X86::JLE_4;
2522 case X86::COND_G: return X86::JG_4;
2523 case X86::COND_GE: return X86::JGE_4;
2524 case X86::COND_B: return X86::JB_4;
2525 case X86::COND_BE: return X86::JBE_4;
2526 case X86::COND_A: return X86::JA_4;
2527 case X86::COND_AE: return X86::JAE_4;
2528 case X86::COND_S: return X86::JS_4;
2529 case X86::COND_NS: return X86::JNS_4;
2530 case X86::COND_P: return X86::JP_4;
2531 case X86::COND_NP: return X86::JNP_4;
2532 case X86::COND_O: return X86::JO_4;
2533 case X86::COND_NO: return X86::JNO_4;
2537 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2538 /// e.g. turning COND_E to COND_NE.
2539 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2541 default: llvm_unreachable("Illegal condition code!");
2542 case X86::COND_E: return X86::COND_NE;
2543 case X86::COND_NE: return X86::COND_E;
2544 case X86::COND_L: return X86::COND_GE;
2545 case X86::COND_LE: return X86::COND_G;
2546 case X86::COND_G: return X86::COND_LE;
2547 case X86::COND_GE: return X86::COND_L;
2548 case X86::COND_B: return X86::COND_AE;
2549 case X86::COND_BE: return X86::COND_A;
2550 case X86::COND_A: return X86::COND_BE;
2551 case X86::COND_AE: return X86::COND_B;
2552 case X86::COND_S: return X86::COND_NS;
2553 case X86::COND_NS: return X86::COND_S;
2554 case X86::COND_P: return X86::COND_NP;
2555 case X86::COND_NP: return X86::COND_P;
2556 case X86::COND_O: return X86::COND_NO;
2557 case X86::COND_NO: return X86::COND_O;
2561 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2562 /// the condition code if we modify the instructions such that flags are
2564 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2566 default: return X86::COND_INVALID;
2567 case X86::COND_E: return X86::COND_E;
2568 case X86::COND_NE: return X86::COND_NE;
2569 case X86::COND_L: return X86::COND_G;
2570 case X86::COND_LE: return X86::COND_GE;
2571 case X86::COND_G: return X86::COND_L;
2572 case X86::COND_GE: return X86::COND_LE;
2573 case X86::COND_B: return X86::COND_A;
2574 case X86::COND_BE: return X86::COND_AE;
2575 case X86::COND_A: return X86::COND_B;
2576 case X86::COND_AE: return X86::COND_BE;
2580 /// getSETFromCond - Return a set opcode for the given condition and
2581 /// whether it has memory operand.
2582 static unsigned getSETFromCond(X86::CondCode CC,
2583 bool HasMemoryOperand) {
2584 static const uint16_t Opc[16][2] = {
2585 { X86::SETAr, X86::SETAm },
2586 { X86::SETAEr, X86::SETAEm },
2587 { X86::SETBr, X86::SETBm },
2588 { X86::SETBEr, X86::SETBEm },
2589 { X86::SETEr, X86::SETEm },
2590 { X86::SETGr, X86::SETGm },
2591 { X86::SETGEr, X86::SETGEm },
2592 { X86::SETLr, X86::SETLm },
2593 { X86::SETLEr, X86::SETLEm },
2594 { X86::SETNEr, X86::SETNEm },
2595 { X86::SETNOr, X86::SETNOm },
2596 { X86::SETNPr, X86::SETNPm },
2597 { X86::SETNSr, X86::SETNSm },
2598 { X86::SETOr, X86::SETOm },
2599 { X86::SETPr, X86::SETPm },
2600 { X86::SETSr, X86::SETSm }
2603 assert(CC < 16 && "Can only handle standard cond codes");
2604 return Opc[CC][HasMemoryOperand ? 1 : 0];
2607 /// getCMovFromCond - Return a cmov opcode for the given condition,
2608 /// register size in bytes, and operand type.
2609 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2610 bool HasMemoryOperand) {
2611 static const uint16_t Opc[32][3] = {
2612 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2613 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2614 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2615 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2616 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2617 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2618 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2619 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2620 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2621 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2622 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2623 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2624 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2625 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2626 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
2627 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2628 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2629 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2630 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2631 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2632 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2633 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2634 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2635 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2636 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2637 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2638 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2639 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2640 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2641 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2642 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2643 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
2646 assert(CC < 16 && "Can only handle standard cond codes");
2647 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2649 default: llvm_unreachable("Illegal register size!");
2650 case 2: return Opc[Idx][0];
2651 case 4: return Opc[Idx][1];
2652 case 8: return Opc[Idx][2];
2656 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2657 if (!MI->isTerminator()) return false;
2659 // Conditional branch is a special case.
2660 if (MI->isBranch() && !MI->isBarrier())
2662 if (!MI->isPredicable())
2664 return !isPredicated(MI);
2667 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2668 MachineBasicBlock *&TBB,
2669 MachineBasicBlock *&FBB,
2670 SmallVectorImpl<MachineOperand> &Cond,
2671 bool AllowModify) const {
2672 // Start from the bottom of the block and work up, examining the
2673 // terminator instructions.
2674 MachineBasicBlock::iterator I = MBB.end();
2675 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2676 while (I != MBB.begin()) {
2678 if (I->isDebugValue())
2681 // Working from the bottom, when we see a non-terminator instruction, we're
2683 if (!isUnpredicatedTerminator(I))
2686 // A terminator that isn't a branch can't easily be handled by this
2691 // Handle unconditional branches.
2692 if (I->getOpcode() == X86::JMP_4) {
2696 TBB = I->getOperand(0).getMBB();
2700 // If the block has any instructions after a JMP, delete them.
2701 while (llvm::next(I) != MBB.end())
2702 llvm::next(I)->eraseFromParent();
2707 // Delete the JMP if it's equivalent to a fall-through.
2708 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2710 I->eraseFromParent();
2712 UnCondBrIter = MBB.end();
2716 // TBB is used to indicate the unconditional destination.
2717 TBB = I->getOperand(0).getMBB();
2721 // Handle conditional branches.
2722 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2723 if (BranchCode == X86::COND_INVALID)
2724 return true; // Can't handle indirect branch.
2726 // Working from the bottom, handle the first conditional branch.
2728 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2729 if (AllowModify && UnCondBrIter != MBB.end() &&
2730 MBB.isLayoutSuccessor(TargetBB)) {
2731 // If we can modify the code and it ends in something like:
2739 // Then we can change this to:
2746 // Which is a bit more efficient.
2747 // We conditionally jump to the fall-through block.
2748 BranchCode = GetOppositeBranchCondition(BranchCode);
2749 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2750 MachineBasicBlock::iterator OldInst = I;
2752 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2753 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2754 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2757 OldInst->eraseFromParent();
2758 UnCondBrIter->eraseFromParent();
2760 // Restart the analysis.
2761 UnCondBrIter = MBB.end();
2767 TBB = I->getOperand(0).getMBB();
2768 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2772 // Handle subsequent conditional branches. Only handle the case where all
2773 // conditional branches branch to the same destination and their condition
2774 // opcodes fit one of the special multi-branch idioms.
2775 assert(Cond.size() == 1);
2778 // Only handle the case where all conditional branches branch to the same
2780 if (TBB != I->getOperand(0).getMBB())
2783 // If the conditions are the same, we can leave them alone.
2784 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2785 if (OldBranchCode == BranchCode)
2788 // If they differ, see if they fit one of the known patterns. Theoretically,
2789 // we could handle more patterns here, but we shouldn't expect to see them
2790 // if instruction selection has done a reasonable job.
2791 if ((OldBranchCode == X86::COND_NP &&
2792 BranchCode == X86::COND_E) ||
2793 (OldBranchCode == X86::COND_E &&
2794 BranchCode == X86::COND_NP))
2795 BranchCode = X86::COND_NP_OR_E;
2796 else if ((OldBranchCode == X86::COND_P &&
2797 BranchCode == X86::COND_NE) ||
2798 (OldBranchCode == X86::COND_NE &&
2799 BranchCode == X86::COND_P))
2800 BranchCode = X86::COND_NE_OR_P;
2804 // Update the MachineOperand.
2805 Cond[0].setImm(BranchCode);
2811 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2812 MachineBasicBlock::iterator I = MBB.end();
2815 while (I != MBB.begin()) {
2817 if (I->isDebugValue())
2819 if (I->getOpcode() != X86::JMP_4 &&
2820 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2822 // Remove the branch.
2823 I->eraseFromParent();
2832 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2833 MachineBasicBlock *FBB,
2834 const SmallVectorImpl<MachineOperand> &Cond,
2835 DebugLoc DL) const {
2836 // Shouldn't be a fall through.
2837 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2838 assert((Cond.size() == 1 || Cond.size() == 0) &&
2839 "X86 branch conditions have one component!");
2842 // Unconditional branch?
2843 assert(!FBB && "Unconditional branch with multiple successors!");
2844 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2848 // Conditional branch.
2850 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2852 case X86::COND_NP_OR_E:
2853 // Synthesize NP_OR_E with two branches.
2854 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2856 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2859 case X86::COND_NE_OR_P:
2860 // Synthesize NE_OR_P with two branches.
2861 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2863 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2867 unsigned Opc = GetCondBranchFromCond(CC);
2868 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2873 // Two-way Conditional branch. Insert the second branch.
2874 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2881 canInsertSelect(const MachineBasicBlock &MBB,
2882 const SmallVectorImpl<MachineOperand> &Cond,
2883 unsigned TrueReg, unsigned FalseReg,
2884 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2885 // Not all subtargets have cmov instructions.
2886 if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2888 if (Cond.size() != 1)
2890 // We cannot do the composite conditions, at least not in SSA form.
2891 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2894 // Check register classes.
2895 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2896 const TargetRegisterClass *RC =
2897 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2901 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2902 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2903 X86::GR32RegClass.hasSubClassEq(RC) ||
2904 X86::GR64RegClass.hasSubClassEq(RC)) {
2905 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2906 // Bridge. Probably Ivy Bridge as well.
2913 // Can't do vectors.
2917 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2918 MachineBasicBlock::iterator I, DebugLoc DL,
2920 const SmallVectorImpl<MachineOperand> &Cond,
2921 unsigned TrueReg, unsigned FalseReg) const {
2922 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2923 assert(Cond.size() == 1 && "Invalid Cond array");
2924 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2925 MRI.getRegClass(DstReg)->getSize(),
2926 false/*HasMemoryOperand*/);
2927 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2930 /// isHReg - Test if the given register is a physical h register.
2931 static bool isHReg(unsigned Reg) {
2932 return X86::GR8_ABCD_HRegClass.contains(Reg);
2935 // Try and copy between VR128/VR64 and GR64 registers.
2936 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2937 const X86Subtarget& Subtarget) {
2940 // SrcReg(VR128) -> DestReg(GR64)
2941 // SrcReg(VR64) -> DestReg(GR64)
2942 // SrcReg(GR64) -> DestReg(VR128)
2943 // SrcReg(GR64) -> DestReg(VR64)
2945 bool HasAVX = Subtarget.hasAVX();
2946 bool HasAVX512 = Subtarget.hasAVX512();
2947 if (X86::GR64RegClass.contains(DestReg)) {
2948 if (X86::VR128XRegClass.contains(SrcReg))
2949 // Copy from a VR128 register to a GR64 register.
2950 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
2952 if (X86::VR64RegClass.contains(SrcReg))
2953 // Copy from a VR64 register to a GR64 register.
2954 return X86::MOVSDto64rr;
2955 } else if (X86::GR64RegClass.contains(SrcReg)) {
2956 // Copy from a GR64 register to a VR128 register.
2957 if (X86::VR128XRegClass.contains(DestReg))
2958 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
2960 // Copy from a GR64 register to a VR64 register.
2961 if (X86::VR64RegClass.contains(DestReg))
2962 return X86::MOV64toSDrr;
2965 // SrcReg(FR32) -> DestReg(GR32)
2966 // SrcReg(GR32) -> DestReg(FR32)
2968 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
2969 // Copy from a FR32 register to a GR32 register.
2970 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
2972 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2973 // Copy from a GR32 register to a FR32 register.
2974 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
2979 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
2980 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
2981 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
2982 X86::VR512RegClass.contains(DestReg, SrcReg)) {
2983 DestReg = get512BitSuperRegister(DestReg);
2984 SrcReg = get512BitSuperRegister(SrcReg);
2985 return X86::VMOVAPSZrr;
2987 if ((X86::VK8RegClass.contains(DestReg) ||
2988 X86::VK16RegClass.contains(DestReg)) &&
2989 (X86::VK8RegClass.contains(SrcReg) ||
2990 X86::VK16RegClass.contains(SrcReg)))
2991 return X86::KMOVWkk;
2995 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2996 MachineBasicBlock::iterator MI, DebugLoc DL,
2997 unsigned DestReg, unsigned SrcReg,
2998 bool KillSrc) const {
2999 // First deal with the normal symmetric copies.
3000 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3001 bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3003 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3005 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3007 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3009 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3010 // Copying to or from a physical H register on x86-64 requires a NOREX
3011 // move. Otherwise use a normal move.
3012 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3013 TM.getSubtarget<X86Subtarget>().is64Bit()) {
3014 Opc = X86::MOV8rr_NOREX;
3015 // Both operands must be encodable without an REX prefix.
3016 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3017 "8-bit H register can not be copied outside GR8_NOREX");
3021 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3022 Opc = X86::MMX_MOVQ64rr;
3024 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3025 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3026 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3027 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3028 Opc = X86::VMOVAPSYrr;
3030 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
3033 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3034 .addReg(SrcReg, getKillRegState(KillSrc));
3038 // Moving EFLAGS to / from another register requires a push and a pop.
3039 // Notice that we have to adjust the stack if we don't want to clobber the
3040 // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
3041 if (SrcReg == X86::EFLAGS) {
3042 if (X86::GR64RegClass.contains(DestReg)) {
3043 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3044 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3047 if (X86::GR32RegClass.contains(DestReg)) {
3048 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3049 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3053 if (DestReg == X86::EFLAGS) {
3054 if (X86::GR64RegClass.contains(SrcReg)) {
3055 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3056 .addReg(SrcReg, getKillRegState(KillSrc));
3057 BuildMI(MBB, MI, DL, get(X86::POPF64));
3060 if (X86::GR32RegClass.contains(SrcReg)) {
3061 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3062 .addReg(SrcReg, getKillRegState(KillSrc));
3063 BuildMI(MBB, MI, DL, get(X86::POPF32));
3068 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3069 << " to " << RI.getName(DestReg) << '\n');
3070 llvm_unreachable("Cannot emit physreg copy instruction");
3073 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3074 const TargetRegisterClass *RC,
3075 bool isStackAligned,
3076 const TargetMachine &TM,
3078 if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
3079 if (X86::VK8RegClass.hasSubClassEq(RC) ||
3080 X86::VK16RegClass.hasSubClassEq(RC))
3081 return load ? X86::KMOVWkm : X86::KMOVWmk;
3083 if (X86::FR32XRegClass.hasSubClassEq(RC))
3084 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3085 if (X86::FR64XRegClass.hasSubClassEq(RC))
3086 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3087 if (X86::VR128XRegClass.hasSubClassEq(RC) ||
3088 X86::VR256XRegClass.hasSubClassEq(RC) ||
3089 X86::VR512RegClass.hasSubClassEq(RC))
3090 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3093 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3094 switch (RC->getSize()) {
3096 llvm_unreachable("Unknown spill size");
3098 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3099 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3100 // Copying to or from a physical H register on x86-64 requires a NOREX
3101 // move. Otherwise use a normal move.
3102 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3103 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3104 return load ? X86::MOV8rm : X86::MOV8mr;
3106 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3107 return load ? X86::MOV16rm : X86::MOV16mr;
3109 if (X86::GR32RegClass.hasSubClassEq(RC))
3110 return load ? X86::MOV32rm : X86::MOV32mr;
3111 if (X86::FR32RegClass.hasSubClassEq(RC))
3113 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3114 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3115 if (X86::RFP32RegClass.hasSubClassEq(RC))
3116 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3117 llvm_unreachable("Unknown 4-byte regclass");
3119 if (X86::GR64RegClass.hasSubClassEq(RC))
3120 return load ? X86::MOV64rm : X86::MOV64mr;
3121 if (X86::FR64RegClass.hasSubClassEq(RC))
3123 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3124 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3125 if (X86::VR64RegClass.hasSubClassEq(RC))
3126 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3127 if (X86::RFP64RegClass.hasSubClassEq(RC))
3128 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3129 llvm_unreachable("Unknown 8-byte regclass");
3131 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3132 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3134 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
3135 // If stack is realigned we can use aligned stores.
3138 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3139 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3142 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3143 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3146 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3147 // If stack is realigned we can use aligned stores.
3149 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3151 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3153 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3155 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3157 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
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