[X86] Preserve mem refs on newly created 'Store' node instead of 'Load' node when...
[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "x86-instr-info"
44
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
70
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
74
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
79
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
82
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
93
94 struct X86OpTblEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
99
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
102
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo(
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107       Subtarget(STI), RI(STI) {
108
109   static const X86OpTblEntry OpTbl2Addr[] = {
110     { X86::ADC32ri,     X86::ADC32mi,    0 },
111     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
112     { X86::ADC32rr,     X86::ADC32mr,    0 },
113     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
114     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
115     { X86::ADC64rr,     X86::ADC64mr,    0 },
116     { X86::ADD16ri,     X86::ADD16mi,    0 },
117     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
118     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
119     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
120     { X86::ADD16rr,     X86::ADD16mr,    0 },
121     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
122     { X86::ADD32ri,     X86::ADD32mi,    0 },
123     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
124     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
125     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
126     { X86::ADD32rr,     X86::ADD32mr,    0 },
127     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
128     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
129     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
130     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
131     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
132     { X86::ADD64rr,     X86::ADD64mr,    0 },
133     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
134     { X86::ADD8ri,      X86::ADD8mi,     0 },
135     { X86::ADD8rr,      X86::ADD8mr,     0 },
136     { X86::AND16ri,     X86::AND16mi,    0 },
137     { X86::AND16ri8,    X86::AND16mi8,   0 },
138     { X86::AND16rr,     X86::AND16mr,    0 },
139     { X86::AND32ri,     X86::AND32mi,    0 },
140     { X86::AND32ri8,    X86::AND32mi8,   0 },
141     { X86::AND32rr,     X86::AND32mr,    0 },
142     { X86::AND64ri32,   X86::AND64mi32,  0 },
143     { X86::AND64ri8,    X86::AND64mi8,   0 },
144     { X86::AND64rr,     X86::AND64mr,    0 },
145     { X86::AND8ri,      X86::AND8mi,     0 },
146     { X86::AND8rr,      X86::AND8mr,     0 },
147     { X86::DEC16r,      X86::DEC16m,     0 },
148     { X86::DEC32r,      X86::DEC32m,     0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64r,      X86::INC64m,     0 },
154     { X86::INC8r,       X86::INC8m,      0 },
155     { X86::NEG16r,      X86::NEG16m,     0 },
156     { X86::NEG32r,      X86::NEG32m,     0 },
157     { X86::NEG64r,      X86::NEG64m,     0 },
158     { X86::NEG8r,       X86::NEG8m,      0 },
159     { X86::NOT16r,      X86::NOT16m,     0 },
160     { X86::NOT32r,      X86::NOT32m,     0 },
161     { X86::NOT64r,      X86::NOT64m,     0 },
162     { X86::NOT8r,       X86::NOT8m,      0 },
163     { X86::OR16ri,      X86::OR16mi,     0 },
164     { X86::OR16ri8,     X86::OR16mi8,    0 },
165     { X86::OR16rr,      X86::OR16mr,     0 },
166     { X86::OR32ri,      X86::OR32mi,     0 },
167     { X86::OR32ri8,     X86::OR32mi8,    0 },
168     { X86::OR32rr,      X86::OR32mr,     0 },
169     { X86::OR64ri32,    X86::OR64mi32,   0 },
170     { X86::OR64ri8,     X86::OR64mi8,    0 },
171     { X86::OR64rr,      X86::OR64mr,     0 },
172     { X86::OR8ri,       X86::OR8mi,      0 },
173     { X86::OR8rr,       X86::OR8mr,      0 },
174     { X86::ROL16r1,     X86::ROL16m1,    0 },
175     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
176     { X86::ROL16ri,     X86::ROL16mi,    0 },
177     { X86::ROL32r1,     X86::ROL32m1,    0 },
178     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
179     { X86::ROL32ri,     X86::ROL32mi,    0 },
180     { X86::ROL64r1,     X86::ROL64m1,    0 },
181     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
182     { X86::ROL64ri,     X86::ROL64mi,    0 },
183     { X86::ROL8r1,      X86::ROL8m1,     0 },
184     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
185     { X86::ROL8ri,      X86::ROL8mi,     0 },
186     { X86::ROR16r1,     X86::ROR16m1,    0 },
187     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
188     { X86::ROR16ri,     X86::ROR16mi,    0 },
189     { X86::ROR32r1,     X86::ROR32m1,    0 },
190     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
191     { X86::ROR32ri,     X86::ROR32mi,    0 },
192     { X86::ROR64r1,     X86::ROR64m1,    0 },
193     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
194     { X86::ROR64ri,     X86::ROR64mi,    0 },
195     { X86::ROR8r1,      X86::ROR8m1,     0 },
196     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
197     { X86::ROR8ri,      X86::ROR8mi,     0 },
198     { X86::SAR16r1,     X86::SAR16m1,    0 },
199     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
200     { X86::SAR16ri,     X86::SAR16mi,    0 },
201     { X86::SAR32r1,     X86::SAR32m1,    0 },
202     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
203     { X86::SAR32ri,     X86::SAR32mi,    0 },
204     { X86::SAR64r1,     X86::SAR64m1,    0 },
205     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
206     { X86::SAR64ri,     X86::SAR64mi,    0 },
207     { X86::SAR8r1,      X86::SAR8m1,     0 },
208     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
209     { X86::SAR8ri,      X86::SAR8mi,     0 },
210     { X86::SBB32ri,     X86::SBB32mi,    0 },
211     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
212     { X86::SBB32rr,     X86::SBB32mr,    0 },
213     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
214     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
215     { X86::SBB64rr,     X86::SBB64mr,    0 },
216     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
217     { X86::SHL16ri,     X86::SHL16mi,    0 },
218     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
219     { X86::SHL32ri,     X86::SHL32mi,    0 },
220     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
221     { X86::SHL64ri,     X86::SHL64mi,    0 },
222     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
223     { X86::SHL8ri,      X86::SHL8mi,     0 },
224     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
225     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
226     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
227     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
228     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
229     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
230     { X86::SHR16r1,     X86::SHR16m1,    0 },
231     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
232     { X86::SHR16ri,     X86::SHR16mi,    0 },
233     { X86::SHR32r1,     X86::SHR32m1,    0 },
234     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
235     { X86::SHR32ri,     X86::SHR32mi,    0 },
236     { X86::SHR64r1,     X86::SHR64m1,    0 },
237     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
238     { X86::SHR64ri,     X86::SHR64mi,    0 },
239     { X86::SHR8r1,      X86::SHR8m1,     0 },
240     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
241     { X86::SHR8ri,      X86::SHR8mi,     0 },
242     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
243     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
244     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
245     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
246     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
247     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
248     { X86::SUB16ri,     X86::SUB16mi,    0 },
249     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
250     { X86::SUB16rr,     X86::SUB16mr,    0 },
251     { X86::SUB32ri,     X86::SUB32mi,    0 },
252     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
253     { X86::SUB32rr,     X86::SUB32mr,    0 },
254     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
255     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
256     { X86::SUB64rr,     X86::SUB64mr,    0 },
257     { X86::SUB8ri,      X86::SUB8mi,     0 },
258     { X86::SUB8rr,      X86::SUB8mr,     0 },
259     { X86::XOR16ri,     X86::XOR16mi,    0 },
260     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
261     { X86::XOR16rr,     X86::XOR16mr,    0 },
262     { X86::XOR32ri,     X86::XOR32mi,    0 },
263     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
264     { X86::XOR32rr,     X86::XOR32mr,    0 },
265     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
266     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
267     { X86::XOR64rr,     X86::XOR64mr,    0 },
268     { X86::XOR8ri,      X86::XOR8mi,     0 },
269     { X86::XOR8rr,      X86::XOR8mr,     0 }
270   };
271
272   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
273     unsigned RegOp = OpTbl2Addr[i].RegOp;
274     unsigned MemOp = OpTbl2Addr[i].MemOp;
275     unsigned Flags = OpTbl2Addr[i].Flags;
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   RegOp, MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
281
282   static const X86OpTblEntry OpTbl0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
357     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
358     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
359     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
360     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
361     // AVX 128-bit versions of foldable instructions
362     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
363     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
368     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
369     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
370     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
371     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
372     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
373     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
374     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
375     // AVX 256-bit foldable instructions
376     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
377     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
378     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
379     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
380     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
381     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
382     // AVX-512 foldable instructions
383     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
384     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
385     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
386     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
387     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
388     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
389     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
390     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
391     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
392     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
393     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
394     // AVX-512 foldable instructions (256-bit versions)
395     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
398     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
399     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
400     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
401     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
402     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
403     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
404     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
405     // AVX-512 foldable instructions (128-bit versions)
406     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
407     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
408     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
409     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
410     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
411     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
412     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
413     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
414     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
415     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
416     // F16C foldable instructions
417     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
418     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
419   };
420
421   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
422     unsigned RegOp      = OpTbl0[i].RegOp;
423     unsigned MemOp      = OpTbl0[i].MemOp;
424     unsigned Flags      = OpTbl0[i].Flags;
425     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
426                   RegOp, MemOp, TB_INDEX_0 | Flags);
427   }
428
429   static const X86OpTblEntry OpTbl1[] = {
430     { X86::CMP16rr,         X86::CMP16rm,             0 },
431     { X86::CMP32rr,         X86::CMP32rm,             0 },
432     { X86::CMP64rr,         X86::CMP64rm,             0 },
433     { X86::CMP8rr,          X86::CMP8rm,              0 },
434     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
435     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
436     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
437     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
438     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
439     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
440     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
441     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
442     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
443     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
444     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
445     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
446     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
447     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
448     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
449     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
450     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
451     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
452     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
453     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
454     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
455     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
456     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
457     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
458     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
459     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
460     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
461     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
462     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
463     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
464     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
465     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
466     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
467     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
468     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
469     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
470     { X86::MOV16rr,         X86::MOV16rm,             0 },
471     { X86::MOV32rr,         X86::MOV32rm,             0 },
472     { X86::MOV64rr,         X86::MOV64rm,             0 },
473     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
474     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
475     { X86::MOV8rr,          X86::MOV8rm,              0 },
476     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
477     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
478     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
479     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
480     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
481     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
482     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
483     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
484     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
485     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
486     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
487     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
488     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
489     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
490     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
491     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
492     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
493     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
494     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
495     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
496     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
497     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
498     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
499     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
500     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
501     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
502     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
503     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
504     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
505     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
506     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
507     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
508     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
509     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
510     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
511     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
512     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
513     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
514     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
515     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
516     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
517     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
518     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
519     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
520     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
521     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
522     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
523     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
524     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
525     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
526     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
527     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
528     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
529     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
530     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
531     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
532     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
533     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
534     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
535     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
536     { X86::TEST16rr,        X86::TEST16rm,            0 },
537     { X86::TEST32rr,        X86::TEST32rm,            0 },
538     { X86::TEST64rr,        X86::TEST64rm,            0 },
539     { X86::TEST8rr,         X86::TEST8rm,             0 },
540     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
541     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
542     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
543     // AVX 128-bit versions of foldable instructions
544     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
545     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
546     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
547     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
548     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
549     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
550     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
551     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
552     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
553     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
554     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
555     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
556     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
557     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
558     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
559     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
560     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
561     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
562     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
563     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
564     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
565     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
566     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
567     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
568     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
569     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
570     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
571     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
572     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
573     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
574     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
575     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
576     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
577     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
578     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
579     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
580     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
581     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
582     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
583     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
584     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
585     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
586     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
587     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
588     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
589     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
590     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
591     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
592     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
593     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
594     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
595     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
596     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
597     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
598     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
599     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
600     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
601     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
602     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
603     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
604     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
605     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
606     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
607     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
608     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
609     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
610     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
611     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
612     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
613     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
614     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
615     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
616     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
617     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
618     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
619     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
620
621     // AVX 256-bit foldable instructions
622     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
623     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
624     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
625     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
626     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
627     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
628     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
629     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
630     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
631     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
632     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
633     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
634     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
635     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
636     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
637     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
638     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
639     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
640     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
641     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
642     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
643     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
644     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
645     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
646     { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      0 },
647     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
648     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
649     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
650     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
651
652     // AVX2 foldable instructions
653     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
654     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
655     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
656     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
657     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
658     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
659     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
660     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
661     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
662
663     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
664     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
665     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
666     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
667     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
668     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
669     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
670     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
671     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
672     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
673     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
674     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
675     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
676     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
677     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
678     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
679     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
680     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
681     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
682     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
683     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
684     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
685     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
686     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
687     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
688     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
689     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
690     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
691     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
692     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
693     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
694     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
695     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
696     { X86::RORX32ri,        X86::RORX32mi,            0 },
697     { X86::RORX64ri,        X86::RORX64mi,            0 },
698     { X86::SARX32rr,        X86::SARX32rm,            0 },
699     { X86::SARX64rr,        X86::SARX64rm,            0 },
700     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
701     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
702     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
703     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
704     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
705     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
706     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
707     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
708     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
709     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
710     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
711
712     // AVX-512 foldable instructions
713     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
714     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
715     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
716     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
717     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
718     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
719     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
720     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
721     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
722     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
723     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
724     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
725     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
726     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
727     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
728     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
729     // AVX-512 foldable instructions (256-bit versions)
730     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
731     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
732     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
733     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
734     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
735     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
736     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
737     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
738     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
739     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
740     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
741     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
742     // AVX-512 foldable instructions (256-bit versions)
743     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
744     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
745     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
746     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
747     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
748     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
749     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
750     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
751     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
752     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
753     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
754     // F16C foldable instructions
755     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
756     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
757     // AES foldable instructions
758     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
759     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
760     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
761     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
762   };
763
764   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
765     unsigned RegOp = OpTbl1[i].RegOp;
766     unsigned MemOp = OpTbl1[i].MemOp;
767     unsigned Flags = OpTbl1[i].Flags;
768     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
769                   RegOp, MemOp,
770                   // Index 1, folded load
771                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
772   }
773
774   static const X86OpTblEntry OpTbl2[] = {
775     { X86::ADC32rr,         X86::ADC32rm,       0 },
776     { X86::ADC64rr,         X86::ADC64rm,       0 },
777     { X86::ADD16rr,         X86::ADD16rm,       0 },
778     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
779     { X86::ADD32rr,         X86::ADD32rm,       0 },
780     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
781     { X86::ADD64rr,         X86::ADD64rm,       0 },
782     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
783     { X86::ADD8rr,          X86::ADD8rm,        0 },
784     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
785     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
786     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
787     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
788     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
789     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
790     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
791     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
792     { X86::AND16rr,         X86::AND16rm,       0 },
793     { X86::AND32rr,         X86::AND32rm,       0 },
794     { X86::AND64rr,         X86::AND64rm,       0 },
795     { X86::AND8rr,          X86::AND8rm,        0 },
796     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
797     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
798     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
799     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
800     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
801     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
802     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
803     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
804     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
805     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
806     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
807     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
808     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
809     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
810     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
811     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
812     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
813     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
814     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
815     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
816     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
817     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
818     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
819     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
820     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
821     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
822     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
823     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
824     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
825     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
826     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
827     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
828     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
829     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
830     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
831     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
832     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
833     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
834     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
835     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
836     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
837     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
838     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
839     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
840     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
841     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
842     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
843     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
844     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
845     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
846     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
847     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
848     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
849     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
850     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
851     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
852     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
853     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
854     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
855     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
856     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
857     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
858     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
859     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
860     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
861     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
862     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
863     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
864     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
865     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
866     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
867     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
868     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
869     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
870     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
871     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
872     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
873     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
874     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
875     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
876     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
877     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
878     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
879     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
880     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
881     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
882     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
883     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
884     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
885     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
886     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
887     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
888     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
889     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
890     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
891     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
892     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
893     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
894     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
895     { X86::MINSDrr,         X86::MINSDrm,       0 },
896     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
897     { X86::MINSSrr,         X86::MINSSrm,       0 },
898     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
899     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
900     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
901     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
902     { X86::MULSDrr,         X86::MULSDrm,       0 },
903     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
904     { X86::MULSSrr,         X86::MULSSrm,       0 },
905     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
906     { X86::OR16rr,          X86::OR16rm,        0 },
907     { X86::OR32rr,          X86::OR32rm,        0 },
908     { X86::OR64rr,          X86::OR64rm,        0 },
909     { X86::OR8rr,           X86::OR8rm,         0 },
910     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
911     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
912     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
913     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
914     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
915     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
916     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
917     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
918     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
919     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
920     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
921     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
922     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
923     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
924     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
925     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
926     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
927     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
928     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
929     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
930     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
931     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
932     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
933     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
934     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
935     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
936     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
937     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
938     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
939     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
940     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
941     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
942     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
943     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
944     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
945     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
946     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
947     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
948     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
949     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
950     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
951     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
952     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
953     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
954     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
955     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
956     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
957     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
958     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
959     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
960     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
961     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
962     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
963     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
964     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
965     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
966     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
967     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
968     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
969     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
970     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
971     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
972     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
973     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
974     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
975     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
976     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
977     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
978     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
979     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
980     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
981     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
982     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
983     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
984     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
985     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
986     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
987     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
988     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
989     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
990     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
991     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
992     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
993     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
994     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
995     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
996     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
997     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
998     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
999     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1000     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1001     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1002     { X86::SBB32rr,         X86::SBB32rm,       0 },
1003     { X86::SBB64rr,         X86::SBB64rm,       0 },
1004     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1005     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1006     { X86::SUB16rr,         X86::SUB16rm,       0 },
1007     { X86::SUB32rr,         X86::SUB32rm,       0 },
1008     { X86::SUB64rr,         X86::SUB64rm,       0 },
1009     { X86::SUB8rr,          X86::SUB8rm,        0 },
1010     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1011     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1012     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1013     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1014     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1015     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1016     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1017     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1018     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1019     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1020     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1021     { X86::XOR16rr,         X86::XOR16rm,       0 },
1022     { X86::XOR32rr,         X86::XOR32rm,       0 },
1023     { X86::XOR64rr,         X86::XOR64rm,       0 },
1024     { X86::XOR8rr,          X86::XOR8rm,        0 },
1025     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1026     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1027     // AVX 128-bit versions of foldable instructions
1028     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1029     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1030     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1031     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1032     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1033     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1034     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1035     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1036     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1037     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1038     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1039     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1040     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1041     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1042     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1043     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1044     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1045     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1046     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1047     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1048     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1049     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1050     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1051     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1052     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1053     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1054     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1055     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1056     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1057     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1058     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1059     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1060     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1061     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1062     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1063     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1064     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1065     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1066     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1067     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1068     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1069     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1070     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1071     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1072     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        0 },
1073     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        0 },
1074     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         0 },
1075     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         0 },
1076     { X86::VFsORPDrr,         X86::VFsORPDrm,          0 },
1077     { X86::VFsORPSrr,         X86::VFsORPSrm,          0 },
1078     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         0 },
1079     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         0 },
1080     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1081     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1082     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1083     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1084     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1085     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1086     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1087     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1088     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1089     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1090     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1091     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1092     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1093     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1094     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1095     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1096     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1097     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1098     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1099     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1100     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1101     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1102     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1103     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1104     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1105     { X86::VORPDrr,           X86::VORPDrm,            0 },
1106     { X86::VORPSrr,           X86::VORPSrm,            0 },
1107     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1108     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1109     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1110     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1111     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1112     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1113     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1114     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1115     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1116     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1117     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1118     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1119     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1120     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1121     { X86::VPANDrr,           X86::VPANDrm,            0 },
1122     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1123     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1124     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1125     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1126     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1127     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1128     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1129     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1130     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1131     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1132     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1133     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1134     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1135     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1136     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1137     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1138     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1139     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1140     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1141     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1142     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1143     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1144     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1145     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1146     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1147     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1148     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1149     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1150     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1151     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1152     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1153     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1154     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1155     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1156     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1157     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1158     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1159     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1160     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1161     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1162     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1163     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1164     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1165     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1166     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1167     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1168     { X86::VPORrr,            X86::VPORrm,             0 },
1169     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1170     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1171     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1172     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1173     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1174     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1175     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1176     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1177     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1178     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1179     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1180     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1181     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1182     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1183     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1184     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1185     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1186     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1187     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1188     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1189     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1190     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1191     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1192     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1193     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1194     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1195     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1196     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1197     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1198     { X86::VPXORrr,           X86::VPXORrm,            0 },
1199     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1200     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1201     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1202     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1203     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1204     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1205     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1206     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1207     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1208     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1209     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1210     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1211     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1212     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1213     // AVX 256-bit foldable instructions
1214     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1215     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1216     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1217     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1218     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1219     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1220     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1221     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1222     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1223     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1224     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1225     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1226     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1227     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1228     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1229     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1230     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1231     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1232     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1233     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1234     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1235     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1236     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1237     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1238     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1239     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1240     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1241     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1242     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1243     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1244     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1245     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1246     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1247     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1248     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1249     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1250     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1251     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1252     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1253     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1254     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1255     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1256     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1257     // AVX2 foldable instructions
1258     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1259     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1260     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1261     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1262     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1263     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1264     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1265     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1266     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1267     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1268     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1269     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1270     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1271     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1272     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1273     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1274     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1275     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1276     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1277     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1278     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1279     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1280     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1281     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1282     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1283     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1284     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1285     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1286     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1287     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1288     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1289     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1290     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1291     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1292     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1293     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1294     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1295     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1296     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1297     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1298     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1299     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1300     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1301     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1302     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1303     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1304     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1305     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1306     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1307     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1308     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1309     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1310     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1311     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1312     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1313     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1314     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1315     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1316     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1317     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1318     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1319     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1320     { X86::VPORYrr,           X86::VPORYrm,            0 },
1321     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1322     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1323     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1324     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1325     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1326     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1327     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1328     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1329     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1330     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1331     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1332     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1333     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1334     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1335     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1336     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1337     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1338     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1339     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1340     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1341     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1342     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1343     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1344     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1345     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1346     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1347     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1348     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1349     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1350     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1351     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1352     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1353     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1354     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1355     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1356     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1357     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1358     // FIXME: add AVX 256-bit foldable instructions
1359
1360     // FMA4 foldable patterns
1361     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0 },
1362     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0 },
1363     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        0 },
1364     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        0 },
1365     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       0 },
1366     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       0 },
1367     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0 },
1368     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0 },
1369     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       0 },
1370     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       0 },
1371     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      0 },
1372     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      0 },
1373     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0 },
1374     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0 },
1375     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        0 },
1376     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        0 },
1377     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       0 },
1378     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       0 },
1379     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0 },
1380     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0 },
1381     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       0 },
1382     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       0 },
1383     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      0 },
1384     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      0 },
1385     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     0 },
1386     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     0 },
1387     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    0 },
1388     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    0 },
1389     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     0 },
1390     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     0 },
1391     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    0 },
1392     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    0 },
1393
1394     // BMI/BMI2 foldable instructions
1395     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1396     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1397     { X86::MULX32rr,          X86::MULX32rm,            0 },
1398     { X86::MULX64rr,          X86::MULX64rm,            0 },
1399     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1400     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1401     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1402     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1403
1404     // AVX-512 foldable instructions
1405     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1406     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1407     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1408     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1409     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1410     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1411     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1412     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1413     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1414     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1415     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1416     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1417     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1418     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1419     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1420     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1421     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1422     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1423     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1424     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1425     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1426     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1427     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1428     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1429     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1430     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1431     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1432     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1433     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1434     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1435     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1436     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1437     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1438     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1439     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1440     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1441     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1442     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1443     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1444
1445     // AVX-512{F,VL} foldable instructions
1446     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1447     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1448     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1449
1450     // AVX-512{F,VL} foldable instructions
1451     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1452     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1453     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1454     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1455
1456     // AES foldable instructions
1457     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1458     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1459     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1460     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1461     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1462     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1463     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1464     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1465
1466     // SHA foldable instructions
1467     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1468     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1469     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1470     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1471     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1472     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1473     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1474   };
1475
1476   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1477     unsigned RegOp = OpTbl2[i].RegOp;
1478     unsigned MemOp = OpTbl2[i].MemOp;
1479     unsigned Flags = OpTbl2[i].Flags;
1480     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1481                   RegOp, MemOp,
1482                   // Index 2, folded load
1483                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1484   }
1485
1486   static const X86OpTblEntry OpTbl3[] = {
1487     // FMA foldable instructions
1488     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1489     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1490     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1491     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1492     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1493     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1494
1495     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1496     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1497     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1498     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1499     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1500     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1501     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1502     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1503     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1504     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1505     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1506     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1507
1508     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1509     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1510     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1511     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1512     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1513     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1514
1515     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1516     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1517     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1518     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1519     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1520     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1521     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1522     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1523     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1524     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1525     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1526     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1527
1528     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1529     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1530     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1531     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1532     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1533     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1534
1535     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1536     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1537     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1538     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1539     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1540     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1541     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1542     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1543     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1544     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1545     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1546     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1547
1548     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1549     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1550     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1551     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1552     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1553     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1554
1555     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1556     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1557     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1558     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1559     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1560     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1561     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1562     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1563     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1564     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1565     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1566     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1567
1568     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1569     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1570     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1571     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1572     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1573     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1574     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1575     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1576     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1577     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1578     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1579     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1580
1581     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1582     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1583     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1584     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1585     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1586     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1587     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1588     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1589     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1590     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1591     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1592     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1593
1594     // FMA4 foldable patterns
1595     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1596     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1597     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1598     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1599     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1600     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1601     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1602     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1603     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1604     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1605     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1606     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1607     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1608     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1609     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1610     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1611     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1612     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1613     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1614     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1615     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1616     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1617     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1618     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1619     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1620     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1621     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1622     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1623     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1624     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1625     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1626     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1627     // AVX-512 VPERMI instructions with 3 source operands.
1628     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1629     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1630     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1631     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1632     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1633     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1634     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1635     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1636     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1637     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1638     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1639     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1640     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1641      // AVX-512 arithmetic instructions
1642     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1643     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1644     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1645     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1646     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1647     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1648     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1649     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1650     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1651     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1652     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1653     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1654     // AVX-512{F,VL} arithmetic instructions 256-bit
1655     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1656     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1657     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1658     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1659     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1660     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1661     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1662     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1663     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1664     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1665     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1666     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1667     // AVX-512{F,VL} arithmetic instructions 128-bit
1668     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1669     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1670     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1671     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1672     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1673     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1674     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1675     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1676     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1677     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1678     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1679     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1680   };
1681
1682   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1683     unsigned RegOp = OpTbl3[i].RegOp;
1684     unsigned MemOp = OpTbl3[i].MemOp;
1685     unsigned Flags = OpTbl3[i].Flags;
1686     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1687                   RegOp, MemOp,
1688                   // Index 3, folded load
1689                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1690   }
1691
1692   static const X86OpTblEntry OpTbl4[] = {
1693      // AVX-512 foldable instructions
1694     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1695     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1696     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1697     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1698     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1699     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1700     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1701     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1702     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1703     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1704     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1705     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1706     // AVX-512{F,VL} foldable instructions 256-bit
1707     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1708     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1709     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1710     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1711     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1712     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1713     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1714     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1715     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1716     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1717     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1718     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1719     // AVX-512{F,VL} foldable instructions 128-bit
1720     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
1721     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
1722     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
1723     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
1724     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
1725     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
1726     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
1727     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
1728     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
1729     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
1730     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
1731     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
1732   };
1733
1734   for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1735     unsigned RegOp = OpTbl4[i].RegOp;
1736     unsigned MemOp = OpTbl4[i].MemOp;
1737     unsigned Flags = OpTbl4[i].Flags;
1738     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1739                   RegOp, MemOp,
1740                   // Index 4, folded load
1741                   Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1742   }
1743 }
1744
1745 void
1746 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1747                             MemOp2RegOpTableType &M2RTable,
1748                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1749     if ((Flags & TB_NO_FORWARD) == 0) {
1750       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1751       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1752     }
1753     if ((Flags & TB_NO_REVERSE) == 0) {
1754       assert(!M2RTable.count(MemOp) &&
1755            "Duplicated entries in unfolding maps?");
1756       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1757     }
1758 }
1759
1760 bool
1761 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1762                                     unsigned &SrcReg, unsigned &DstReg,
1763                                     unsigned &SubIdx) const {
1764   switch (MI.getOpcode()) {
1765   default: break;
1766   case X86::MOVSX16rr8:
1767   case X86::MOVZX16rr8:
1768   case X86::MOVSX32rr8:
1769   case X86::MOVZX32rr8:
1770   case X86::MOVSX64rr8:
1771     if (!Subtarget.is64Bit())
1772       // It's not always legal to reference the low 8-bit of the larger
1773       // register in 32-bit mode.
1774       return false;
1775   case X86::MOVSX32rr16:
1776   case X86::MOVZX32rr16:
1777   case X86::MOVSX64rr16:
1778   case X86::MOVSX64rr32: {
1779     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1780       // Be conservative.
1781       return false;
1782     SrcReg = MI.getOperand(1).getReg();
1783     DstReg = MI.getOperand(0).getReg();
1784     switch (MI.getOpcode()) {
1785     default: llvm_unreachable("Unreachable!");
1786     case X86::MOVSX16rr8:
1787     case X86::MOVZX16rr8:
1788     case X86::MOVSX32rr8:
1789     case X86::MOVZX32rr8:
1790     case X86::MOVSX64rr8:
1791       SubIdx = X86::sub_8bit;
1792       break;
1793     case X86::MOVSX32rr16:
1794     case X86::MOVZX32rr16:
1795     case X86::MOVSX64rr16:
1796       SubIdx = X86::sub_16bit;
1797       break;
1798     case X86::MOVSX64rr32:
1799       SubIdx = X86::sub_32bit;
1800       break;
1801     }
1802     return true;
1803   }
1804   }
1805   return false;
1806 }
1807
1808 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
1809   const MachineFunction *MF = MI->getParent()->getParent();
1810   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1811
1812   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
1813       MI->getOpcode() == getCallFrameDestroyOpcode()) {
1814     unsigned StackAlign = TFI->getStackAlignment();
1815     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign * 
1816                  StackAlign;
1817
1818     SPAdj -= MI->getOperand(1).getImm();
1819
1820     if (MI->getOpcode() == getCallFrameSetupOpcode())
1821       return SPAdj;
1822     else
1823       return -SPAdj;
1824   }
1825   
1826   // To know whether a call adjusts the stack, we need information 
1827   // that is bound to the following ADJCALLSTACKUP pseudo.
1828   // Look for the next ADJCALLSTACKUP that follows the call.
1829   if (MI->isCall()) {
1830     const MachineBasicBlock* MBB = MI->getParent();
1831     auto I = ++MachineBasicBlock::const_iterator(MI);
1832     for (auto E = MBB->end(); I != E; ++I) {
1833       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
1834           I->isCall())
1835         break;
1836     }
1837
1838     // If we could not find a frame destroy opcode, then it has already
1839     // been simplified, so we don't care.
1840     if (I->getOpcode() != getCallFrameDestroyOpcode())
1841       return 0;
1842
1843     return -(I->getOperand(1).getImm());
1844   }
1845
1846   // Currently handle only PUSHes we can reasonably expect to see
1847   // in call sequences
1848   switch (MI->getOpcode()) {
1849   default: 
1850     return 0;
1851   case X86::PUSH32i8:
1852   case X86::PUSH32r:
1853   case X86::PUSH32rmm:
1854   case X86::PUSH32rmr:
1855   case X86::PUSHi32:
1856     return 4;
1857   }
1858 }
1859
1860 /// isFrameOperand - Return true and the FrameIndex if the specified
1861 /// operand and follow operands form a reference to the stack frame.
1862 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1863                                   int &FrameIndex) const {
1864   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1865       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1866       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1867       MI->getOperand(Op+X86::AddrDisp).isImm() &&
1868       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1869       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1870       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1871     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1872     return true;
1873   }
1874   return false;
1875 }
1876
1877 static bool isFrameLoadOpcode(int Opcode) {
1878   switch (Opcode) {
1879   default:
1880     return false;
1881   case X86::MOV8rm:
1882   case X86::MOV16rm:
1883   case X86::MOV32rm:
1884   case X86::MOV64rm:
1885   case X86::LD_Fp64m:
1886   case X86::MOVSSrm:
1887   case X86::MOVSDrm:
1888   case X86::MOVAPSrm:
1889   case X86::MOVAPDrm:
1890   case X86::MOVDQArm:
1891   case X86::VMOVSSrm:
1892   case X86::VMOVSDrm:
1893   case X86::VMOVAPSrm:
1894   case X86::VMOVAPDrm:
1895   case X86::VMOVDQArm:
1896   case X86::VMOVUPSYrm:
1897   case X86::VMOVAPSYrm:
1898   case X86::VMOVUPDYrm:
1899   case X86::VMOVAPDYrm:
1900   case X86::VMOVDQUYrm:
1901   case X86::VMOVDQAYrm:
1902   case X86::MMX_MOVD64rm:
1903   case X86::MMX_MOVQ64rm:
1904   case X86::VMOVAPSZrm:
1905   case X86::VMOVUPSZrm:
1906     return true;
1907   }
1908 }
1909
1910 static bool isFrameStoreOpcode(int Opcode) {
1911   switch (Opcode) {
1912   default: break;
1913   case X86::MOV8mr:
1914   case X86::MOV16mr:
1915   case X86::MOV32mr:
1916   case X86::MOV64mr:
1917   case X86::ST_FpP64m:
1918   case X86::MOVSSmr:
1919   case X86::MOVSDmr:
1920   case X86::MOVAPSmr:
1921   case X86::MOVAPDmr:
1922   case X86::MOVDQAmr:
1923   case X86::VMOVSSmr:
1924   case X86::VMOVSDmr:
1925   case X86::VMOVAPSmr:
1926   case X86::VMOVAPDmr:
1927   case X86::VMOVDQAmr:
1928   case X86::VMOVUPSYmr:
1929   case X86::VMOVAPSYmr:
1930   case X86::VMOVUPDYmr:
1931   case X86::VMOVAPDYmr:
1932   case X86::VMOVDQUYmr:
1933   case X86::VMOVDQAYmr:
1934   case X86::VMOVUPSZmr:
1935   case X86::VMOVAPSZmr:
1936   case X86::MMX_MOVD64mr:
1937   case X86::MMX_MOVQ64mr:
1938   case X86::MMX_MOVNTQmr:
1939     return true;
1940   }
1941   return false;
1942 }
1943
1944 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1945                                            int &FrameIndex) const {
1946   if (isFrameLoadOpcode(MI->getOpcode()))
1947     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1948       return MI->getOperand(0).getReg();
1949   return 0;
1950 }
1951
1952 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1953                                                  int &FrameIndex) const {
1954   if (isFrameLoadOpcode(MI->getOpcode())) {
1955     unsigned Reg;
1956     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1957       return Reg;
1958     // Check for post-frame index elimination operations
1959     const MachineMemOperand *Dummy;
1960     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1961   }
1962   return 0;
1963 }
1964
1965 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1966                                           int &FrameIndex) const {
1967   if (isFrameStoreOpcode(MI->getOpcode()))
1968     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1969         isFrameOperand(MI, 0, FrameIndex))
1970       return MI->getOperand(X86::AddrNumOperands).getReg();
1971   return 0;
1972 }
1973
1974 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1975                                                 int &FrameIndex) const {
1976   if (isFrameStoreOpcode(MI->getOpcode())) {
1977     unsigned Reg;
1978     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1979       return Reg;
1980     // Check for post-frame index elimination operations
1981     const MachineMemOperand *Dummy;
1982     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1983   }
1984   return 0;
1985 }
1986
1987 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1988 /// X86::MOVPC32r.
1989 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1990   // Don't waste compile time scanning use-def chains of physregs.
1991   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1992     return false;
1993   bool isPICBase = false;
1994   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1995          E = MRI.def_instr_end(); I != E; ++I) {
1996     MachineInstr *DefMI = &*I;
1997     if (DefMI->getOpcode() != X86::MOVPC32r)
1998       return false;
1999     assert(!isPICBase && "More than one PIC base?");
2000     isPICBase = true;
2001   }
2002   return isPICBase;
2003 }
2004
2005 bool
2006 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2007                                                 AliasAnalysis *AA) const {
2008   switch (MI->getOpcode()) {
2009   default: break;
2010   case X86::MOV8rm:
2011   case X86::MOV16rm:
2012   case X86::MOV32rm:
2013   case X86::MOV64rm:
2014   case X86::LD_Fp64m:
2015   case X86::MOVSSrm:
2016   case X86::MOVSDrm:
2017   case X86::MOVAPSrm:
2018   case X86::MOVUPSrm:
2019   case X86::MOVAPDrm:
2020   case X86::MOVDQArm:
2021   case X86::MOVDQUrm:
2022   case X86::VMOVSSrm:
2023   case X86::VMOVSDrm:
2024   case X86::VMOVAPSrm:
2025   case X86::VMOVUPSrm:
2026   case X86::VMOVAPDrm:
2027   case X86::VMOVDQArm:
2028   case X86::VMOVDQUrm:
2029   case X86::VMOVAPSYrm:
2030   case X86::VMOVUPSYrm:
2031   case X86::VMOVAPDYrm:
2032   case X86::VMOVDQAYrm:
2033   case X86::VMOVDQUYrm:
2034   case X86::MMX_MOVD64rm:
2035   case X86::MMX_MOVQ64rm:
2036   case X86::FsVMOVAPSrm:
2037   case X86::FsVMOVAPDrm:
2038   case X86::FsMOVAPSrm:
2039   case X86::FsMOVAPDrm: {
2040     // Loads from constant pools are trivially rematerializable.
2041     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2042         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2043         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2044         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2045         MI->isInvariantLoad(AA)) {
2046       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2047       if (BaseReg == 0 || BaseReg == X86::RIP)
2048         return true;
2049       // Allow re-materialization of PIC load.
2050       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2051         return false;
2052       const MachineFunction &MF = *MI->getParent()->getParent();
2053       const MachineRegisterInfo &MRI = MF.getRegInfo();
2054       return regIsPICBase(BaseReg, MRI);
2055     }
2056     return false;
2057   }
2058
2059   case X86::LEA32r:
2060   case X86::LEA64r: {
2061     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2062         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2063         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2064         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2065       // lea fi#, lea GV, etc. are all rematerializable.
2066       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2067         return true;
2068       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2069       if (BaseReg == 0)
2070         return true;
2071       // Allow re-materialization of lea PICBase + x.
2072       const MachineFunction &MF = *MI->getParent()->getParent();
2073       const MachineRegisterInfo &MRI = MF.getRegInfo();
2074       return regIsPICBase(BaseReg, MRI);
2075     }
2076     return false;
2077   }
2078   }
2079
2080   // All other instructions marked M_REMATERIALIZABLE are always trivially
2081   // rematerializable.
2082   return true;
2083 }
2084
2085 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2086                                          MachineBasicBlock::iterator I) const {
2087   MachineBasicBlock::iterator E = MBB.end();
2088
2089   // For compile time consideration, if we are not able to determine the
2090   // safety after visiting 4 instructions in each direction, we will assume
2091   // it's not safe.
2092   MachineBasicBlock::iterator Iter = I;
2093   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2094     bool SeenDef = false;
2095     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2096       MachineOperand &MO = Iter->getOperand(j);
2097       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2098         SeenDef = true;
2099       if (!MO.isReg())
2100         continue;
2101       if (MO.getReg() == X86::EFLAGS) {
2102         if (MO.isUse())
2103           return false;
2104         SeenDef = true;
2105       }
2106     }
2107
2108     if (SeenDef)
2109       // This instruction defines EFLAGS, no need to look any further.
2110       return true;
2111     ++Iter;
2112     // Skip over DBG_VALUE.
2113     while (Iter != E && Iter->isDebugValue())
2114       ++Iter;
2115   }
2116
2117   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2118   // live in.
2119   if (Iter == E) {
2120     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2121            SE = MBB.succ_end(); SI != SE; ++SI)
2122       if ((*SI)->isLiveIn(X86::EFLAGS))
2123         return false;
2124     return true;
2125   }
2126
2127   MachineBasicBlock::iterator B = MBB.begin();
2128   Iter = I;
2129   for (unsigned i = 0; i < 4; ++i) {
2130     // If we make it to the beginning of the block, it's safe to clobber
2131     // EFLAGS iff EFLAGS is not live-in.
2132     if (Iter == B)
2133       return !MBB.isLiveIn(X86::EFLAGS);
2134
2135     --Iter;
2136     // Skip over DBG_VALUE.
2137     while (Iter != B && Iter->isDebugValue())
2138       --Iter;
2139
2140     bool SawKill = false;
2141     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2142       MachineOperand &MO = Iter->getOperand(j);
2143       // A register mask may clobber EFLAGS, but we should still look for a
2144       // live EFLAGS def.
2145       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2146         SawKill = true;
2147       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2148         if (MO.isDef()) return MO.isDead();
2149         if (MO.isKill()) SawKill = true;
2150       }
2151     }
2152
2153     if (SawKill)
2154       // This instruction kills EFLAGS and doesn't redefine it, so
2155       // there's no need to look further.
2156       return true;
2157   }
2158
2159   // Conservative answer.
2160   return false;
2161 }
2162
2163 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2164                                  MachineBasicBlock::iterator I,
2165                                  unsigned DestReg, unsigned SubIdx,
2166                                  const MachineInstr *Orig,
2167                                  const TargetRegisterInfo &TRI) const {
2168   // MOV32r0 is implemented with a xor which clobbers condition code.
2169   // Re-materialize it as movri instructions to avoid side effects.
2170   unsigned Opc = Orig->getOpcode();
2171   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2172     DebugLoc DL = Orig->getDebugLoc();
2173     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2174       .addImm(0);
2175   } else {
2176     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2177     MBB.insert(I, MI);
2178   }
2179
2180   MachineInstr *NewMI = std::prev(I);
2181   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2182 }
2183
2184 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2185 /// is not marked dead.
2186 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2187   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2188     MachineOperand &MO = MI->getOperand(i);
2189     if (MO.isReg() && MO.isDef() &&
2190         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2191       return true;
2192     }
2193   }
2194   return false;
2195 }
2196
2197 /// getTruncatedShiftCount - check whether the shift count for a machine operand
2198 /// is non-zero.
2199 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2200                                               unsigned ShiftAmtOperandIdx) {
2201   // The shift count is six bits with the REX.W prefix and five bits without.
2202   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2203   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2204   return Imm & ShiftCountMask;
2205 }
2206
2207 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2208 /// can be represented by a LEA instruction.
2209 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2210   // Left shift instructions can be transformed into load-effective-address
2211   // instructions if we can encode them appropriately.
2212   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2213   // The SIB.scale field is two bits wide which means that we can encode any
2214   // shift amount less than 4.
2215   return ShAmt < 4 && ShAmt > 0;
2216 }
2217
2218 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2219                                   unsigned Opc, bool AllowSP,
2220                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2221                                   MachineOperand &ImplicitOp) const {
2222   MachineFunction &MF = *MI->getParent()->getParent();
2223   const TargetRegisterClass *RC;
2224   if (AllowSP) {
2225     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2226   } else {
2227     RC = Opc != X86::LEA32r ?
2228       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2229   }
2230   unsigned SrcReg = Src.getReg();
2231
2232   // For both LEA64 and LEA32 the register already has essentially the right
2233   // type (32-bit or 64-bit) we may just need to forbid SP.
2234   if (Opc != X86::LEA64_32r) {
2235     NewSrc = SrcReg;
2236     isKill = Src.isKill();
2237     isUndef = Src.isUndef();
2238
2239     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2240         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2241       return false;
2242
2243     return true;
2244   }
2245
2246   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2247   // another we need to add 64-bit registers to the final MI.
2248   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2249     ImplicitOp = Src;
2250     ImplicitOp.setImplicit();
2251
2252     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2253     MachineBasicBlock::LivenessQueryResult LQR =
2254       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2255
2256     switch (LQR) {
2257     case MachineBasicBlock::LQR_Unknown:
2258       // We can't give sane liveness flags to the instruction, abandon LEA
2259       // formation.
2260       return false;
2261     case MachineBasicBlock::LQR_Live:
2262       isKill = MI->killsRegister(SrcReg);
2263       isUndef = false;
2264       break;
2265     default:
2266       // The physreg itself is dead, so we have to use it as an <undef>.
2267       isKill = false;
2268       isUndef = true;
2269       break;
2270     }
2271   } else {
2272     // Virtual register of the wrong class, we have to create a temporary 64-bit
2273     // vreg to feed into the LEA.
2274     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2275     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2276             get(TargetOpcode::COPY))
2277       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2278         .addOperand(Src);
2279
2280     // Which is obviously going to be dead after we're done with it.
2281     isKill = true;
2282     isUndef = false;
2283   }
2284
2285   // We've set all the parameters without issue.
2286   return true;
2287 }
2288
2289 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
2290 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2291 /// to a 32-bit superregister and then truncating back down to a 16-bit
2292 /// subregister.
2293 MachineInstr *
2294 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2295                                            MachineFunction::iterator &MFI,
2296                                            MachineBasicBlock::iterator &MBBI,
2297                                            LiveVariables *LV) const {
2298   MachineInstr *MI = MBBI;
2299   unsigned Dest = MI->getOperand(0).getReg();
2300   unsigned Src = MI->getOperand(1).getReg();
2301   bool isDead = MI->getOperand(0).isDead();
2302   bool isKill = MI->getOperand(1).isKill();
2303
2304   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2305   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2306   unsigned Opc, leaInReg;
2307   if (Subtarget.is64Bit()) {
2308     Opc = X86::LEA64_32r;
2309     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2310   } else {
2311     Opc = X86::LEA32r;
2312     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2313   }
2314
2315   // Build and insert into an implicit UNDEF value. This is OK because
2316   // well be shifting and then extracting the lower 16-bits.
2317   // This has the potential to cause partial register stall. e.g.
2318   //   movw    (%rbp,%rcx,2), %dx
2319   //   leal    -65(%rdx), %esi
2320   // But testing has shown this *does* help performance in 64-bit mode (at
2321   // least on modern x86 machines).
2322   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2323   MachineInstr *InsMI =
2324     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2325     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2326     .addReg(Src, getKillRegState(isKill));
2327
2328   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2329                                     get(Opc), leaOutReg);
2330   switch (MIOpc) {
2331   default: llvm_unreachable("Unreachable!");
2332   case X86::SHL16ri: {
2333     unsigned ShAmt = MI->getOperand(2).getImm();
2334     MIB.addReg(0).addImm(1 << ShAmt)
2335        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2336     break;
2337   }
2338   case X86::INC16r:
2339     addRegOffset(MIB, leaInReg, true, 1);
2340     break;
2341   case X86::DEC16r:
2342     addRegOffset(MIB, leaInReg, true, -1);
2343     break;
2344   case X86::ADD16ri:
2345   case X86::ADD16ri8:
2346   case X86::ADD16ri_DB:
2347   case X86::ADD16ri8_DB:
2348     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2349     break;
2350   case X86::ADD16rr:
2351   case X86::ADD16rr_DB: {
2352     unsigned Src2 = MI->getOperand(2).getReg();
2353     bool isKill2 = MI->getOperand(2).isKill();
2354     unsigned leaInReg2 = 0;
2355     MachineInstr *InsMI2 = nullptr;
2356     if (Src == Src2) {
2357       // ADD16rr %reg1028<kill>, %reg1028
2358       // just a single insert_subreg.
2359       addRegReg(MIB, leaInReg, true, leaInReg, false);
2360     } else {
2361       if (Subtarget.is64Bit())
2362         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2363       else
2364         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2365       // Build and insert into an implicit UNDEF value. This is OK because
2366       // well be shifting and then extracting the lower 16-bits.
2367       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2368       InsMI2 =
2369         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2370         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2371         .addReg(Src2, getKillRegState(isKill2));
2372       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2373     }
2374     if (LV && isKill2 && InsMI2)
2375       LV->replaceKillInstruction(Src2, MI, InsMI2);
2376     break;
2377   }
2378   }
2379
2380   MachineInstr *NewMI = MIB;
2381   MachineInstr *ExtMI =
2382     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2383     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2384     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2385
2386   if (LV) {
2387     // Update live variables
2388     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2389     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2390     if (isKill)
2391       LV->replaceKillInstruction(Src, MI, InsMI);
2392     if (isDead)
2393       LV->replaceKillInstruction(Dest, MI, ExtMI);
2394   }
2395
2396   return ExtMI;
2397 }
2398
2399 /// convertToThreeAddress - This method must be implemented by targets that
2400 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2401 /// may be able to convert a two-address instruction into a true
2402 /// three-address instruction on demand.  This allows the X86 target (for
2403 /// example) to convert ADD and SHL instructions into LEA instructions if they
2404 /// would require register copies due to two-addressness.
2405 ///
2406 /// This method returns a null pointer if the transformation cannot be
2407 /// performed, otherwise it returns the new instruction.
2408 ///
2409 MachineInstr *
2410 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2411                                     MachineBasicBlock::iterator &MBBI,
2412                                     LiveVariables *LV) const {
2413   MachineInstr *MI = MBBI;
2414
2415   // The following opcodes also sets the condition code register(s). Only
2416   // convert them to equivalent lea if the condition code register def's
2417   // are dead!
2418   if (hasLiveCondCodeDef(MI))
2419     return nullptr;
2420
2421   MachineFunction &MF = *MI->getParent()->getParent();
2422   // All instructions input are two-addr instructions.  Get the known operands.
2423   const MachineOperand &Dest = MI->getOperand(0);
2424   const MachineOperand &Src = MI->getOperand(1);
2425
2426   MachineInstr *NewMI = nullptr;
2427   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2428   // we have better subtarget support, enable the 16-bit LEA generation here.
2429   // 16-bit LEA is also slow on Core2.
2430   bool DisableLEA16 = true;
2431   bool is64Bit = Subtarget.is64Bit();
2432
2433   unsigned MIOpc = MI->getOpcode();
2434   switch (MIOpc) {
2435   default: return nullptr;
2436   case X86::SHL64ri: {
2437     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2438     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2439     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2440
2441     // LEA can't handle RSP.
2442     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2443         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2444                                            &X86::GR64_NOSPRegClass))
2445       return nullptr;
2446
2447     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2448       .addOperand(Dest)
2449       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2450     break;
2451   }
2452   case X86::SHL32ri: {
2453     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2454     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2455     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2456
2457     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2458
2459     // LEA can't handle ESP.
2460     bool isKill, isUndef;
2461     unsigned SrcReg;
2462     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2463     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2464                         SrcReg, isKill, isUndef, ImplicitOp))
2465       return nullptr;
2466
2467     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2468       .addOperand(Dest)
2469       .addReg(0).addImm(1 << ShAmt)
2470       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2471       .addImm(0).addReg(0);
2472     if (ImplicitOp.getReg() != 0)
2473       MIB.addOperand(ImplicitOp);
2474     NewMI = MIB;
2475
2476     break;
2477   }
2478   case X86::SHL16ri: {
2479     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2480     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2481     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2482
2483     if (DisableLEA16)
2484       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2485     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2486       .addOperand(Dest)
2487       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2488     break;
2489   }
2490   case X86::INC64r:
2491   case X86::INC32r: {
2492     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2493     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2494       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2495     bool isKill, isUndef;
2496     unsigned SrcReg;
2497     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2498     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2499                         SrcReg, isKill, isUndef, ImplicitOp))
2500       return nullptr;
2501
2502     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2503         .addOperand(Dest)
2504         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2505     if (ImplicitOp.getReg() != 0)
2506       MIB.addOperand(ImplicitOp);
2507
2508     NewMI = addOffset(MIB, 1);
2509     break;
2510   }
2511   case X86::INC16r:
2512     if (DisableLEA16)
2513       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2514                      : nullptr;
2515     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2516     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2517                       .addOperand(Dest).addOperand(Src), 1);
2518     break;
2519   case X86::DEC64r:
2520   case X86::DEC32r: {
2521     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2522     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2523       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2524
2525     bool isKill, isUndef;
2526     unsigned SrcReg;
2527     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2528     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2529                         SrcReg, isKill, isUndef, ImplicitOp))
2530       return nullptr;
2531
2532     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2533         .addOperand(Dest)
2534         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2535     if (ImplicitOp.getReg() != 0)
2536       MIB.addOperand(ImplicitOp);
2537
2538     NewMI = addOffset(MIB, -1);
2539
2540     break;
2541   }
2542   case X86::DEC16r:
2543     if (DisableLEA16)
2544       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2545                      : nullptr;
2546     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2547     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2548                       .addOperand(Dest).addOperand(Src), -1);
2549     break;
2550   case X86::ADD64rr:
2551   case X86::ADD64rr_DB:
2552   case X86::ADD32rr:
2553   case X86::ADD32rr_DB: {
2554     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2555     unsigned Opc;
2556     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2557       Opc = X86::LEA64r;
2558     else
2559       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2560
2561     bool isKill, isUndef;
2562     unsigned SrcReg;
2563     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2564     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2565                         SrcReg, isKill, isUndef, ImplicitOp))
2566       return nullptr;
2567
2568     const MachineOperand &Src2 = MI->getOperand(2);
2569     bool isKill2, isUndef2;
2570     unsigned SrcReg2;
2571     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2572     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2573                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2574       return nullptr;
2575
2576     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2577       .addOperand(Dest);
2578     if (ImplicitOp.getReg() != 0)
2579       MIB.addOperand(ImplicitOp);
2580     if (ImplicitOp2.getReg() != 0)
2581       MIB.addOperand(ImplicitOp2);
2582
2583     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2584
2585     // Preserve undefness of the operands.
2586     NewMI->getOperand(1).setIsUndef(isUndef);
2587     NewMI->getOperand(3).setIsUndef(isUndef2);
2588
2589     if (LV && Src2.isKill())
2590       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2591     break;
2592   }
2593   case X86::ADD16rr:
2594   case X86::ADD16rr_DB: {
2595     if (DisableLEA16)
2596       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2597                      : nullptr;
2598     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2599     unsigned Src2 = MI->getOperand(2).getReg();
2600     bool isKill2 = MI->getOperand(2).isKill();
2601     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2602                       .addOperand(Dest),
2603                       Src.getReg(), Src.isKill(), Src2, isKill2);
2604
2605     // Preserve undefness of the operands.
2606     bool isUndef = MI->getOperand(1).isUndef();
2607     bool isUndef2 = MI->getOperand(2).isUndef();
2608     NewMI->getOperand(1).setIsUndef(isUndef);
2609     NewMI->getOperand(3).setIsUndef(isUndef2);
2610
2611     if (LV && isKill2)
2612       LV->replaceKillInstruction(Src2, MI, NewMI);
2613     break;
2614   }
2615   case X86::ADD64ri32:
2616   case X86::ADD64ri8:
2617   case X86::ADD64ri32_DB:
2618   case X86::ADD64ri8_DB:
2619     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2620     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2621                       .addOperand(Dest).addOperand(Src),
2622                       MI->getOperand(2).getImm());
2623     break;
2624   case X86::ADD32ri:
2625   case X86::ADD32ri8:
2626   case X86::ADD32ri_DB:
2627   case X86::ADD32ri8_DB: {
2628     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2629     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2630
2631     bool isKill, isUndef;
2632     unsigned SrcReg;
2633     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2634     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2635                         SrcReg, isKill, isUndef, ImplicitOp))
2636       return nullptr;
2637
2638     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2639         .addOperand(Dest)
2640         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2641     if (ImplicitOp.getReg() != 0)
2642       MIB.addOperand(ImplicitOp);
2643
2644     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2645     break;
2646   }
2647   case X86::ADD16ri:
2648   case X86::ADD16ri8:
2649   case X86::ADD16ri_DB:
2650   case X86::ADD16ri8_DB:
2651     if (DisableLEA16)
2652       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2653                      : nullptr;
2654     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2655     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2656                       .addOperand(Dest).addOperand(Src),
2657                       MI->getOperand(2).getImm());
2658     break;
2659   }
2660
2661   if (!NewMI) return nullptr;
2662
2663   if (LV) {  // Update live variables
2664     if (Src.isKill())
2665       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2666     if (Dest.isDead())
2667       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2668   }
2669
2670   MFI->insert(MBBI, NewMI);          // Insert the new inst
2671   return NewMI;
2672 }
2673
2674 /// commuteInstruction - We have a few instructions that must be hacked on to
2675 /// commute them.
2676 ///
2677 MachineInstr *
2678 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2679   switch (MI->getOpcode()) {
2680   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2681   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2682   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2683   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2684   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2685   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2686     unsigned Opc;
2687     unsigned Size;
2688     switch (MI->getOpcode()) {
2689     default: llvm_unreachable("Unreachable!");
2690     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2691     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2692     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2693     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2694     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2695     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2696     }
2697     unsigned Amt = MI->getOperand(3).getImm();
2698     if (NewMI) {
2699       MachineFunction &MF = *MI->getParent()->getParent();
2700       MI = MF.CloneMachineInstr(MI);
2701       NewMI = false;
2702     }
2703     MI->setDesc(get(Opc));
2704     MI->getOperand(3).setImm(Size-Amt);
2705     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2706   }
2707   case X86::BLENDPDrri:
2708   case X86::BLENDPSrri:
2709   case X86::PBLENDWrri:
2710   case X86::VBLENDPDrri:
2711   case X86::VBLENDPSrri:
2712   case X86::VBLENDPDYrri:
2713   case X86::VBLENDPSYrri:
2714   case X86::VPBLENDDrri:
2715   case X86::VPBLENDWrri:
2716   case X86::VPBLENDDYrri:
2717   case X86::VPBLENDWYrri:{
2718     unsigned Mask;
2719     switch (MI->getOpcode()) {
2720     default: llvm_unreachable("Unreachable!");
2721     case X86::BLENDPDrri:    Mask = 0x03; break;
2722     case X86::BLENDPSrri:    Mask = 0x0F; break;
2723     case X86::PBLENDWrri:    Mask = 0xFF; break;
2724     case X86::VBLENDPDrri:   Mask = 0x03; break;
2725     case X86::VBLENDPSrri:   Mask = 0x0F; break;
2726     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2727     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2728     case X86::VPBLENDDrri:   Mask = 0x0F; break;
2729     case X86::VPBLENDWrri:   Mask = 0xFF; break;
2730     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2731     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2732     }
2733     // Only the least significant bits of Imm are used.
2734     unsigned Imm = MI->getOperand(3).getImm() & Mask;
2735     if (NewMI) {
2736       MachineFunction &MF = *MI->getParent()->getParent();
2737       MI = MF.CloneMachineInstr(MI);
2738       NewMI = false;
2739     }
2740     MI->getOperand(3).setImm(Mask ^ Imm);
2741     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2742   }
2743   case X86::PCLMULQDQrr:
2744   case X86::VPCLMULQDQrr:{
2745     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2746     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2747     unsigned Imm = MI->getOperand(3).getImm();
2748     unsigned Src1Hi = Imm & 0x01;
2749     unsigned Src2Hi = Imm & 0x10;
2750     if (NewMI) {
2751       MachineFunction &MF = *MI->getParent()->getParent();
2752       MI = MF.CloneMachineInstr(MI);
2753       NewMI = false;
2754     }
2755     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2756     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2757   }
2758   case X86::CMPPDrri:
2759   case X86::CMPPSrri:
2760   case X86::VCMPPDrri:
2761   case X86::VCMPPSrri:
2762   case X86::VCMPPDYrri:
2763   case X86::VCMPPSYrri: {
2764     // Float comparison can be safely commuted for
2765     // Ordered/Unordered/Equal/NotEqual tests
2766     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2767     switch (Imm) {
2768     case 0x00: // EQUAL
2769     case 0x03: // UNORDERED
2770     case 0x04: // NOT EQUAL
2771     case 0x07: // ORDERED
2772       if (NewMI) {
2773         MachineFunction &MF = *MI->getParent()->getParent();
2774         MI = MF.CloneMachineInstr(MI);
2775         NewMI = false;
2776       }
2777       return TargetInstrInfo::commuteInstruction(MI, NewMI);
2778     default:
2779       return nullptr;
2780     }
2781   }
2782   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2783   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2784   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2785   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2786   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2787   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2788   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2789   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2790   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2791   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2792   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2793   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2794   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2795   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2796   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2797   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2798     unsigned Opc;
2799     switch (MI->getOpcode()) {
2800     default: llvm_unreachable("Unreachable!");
2801     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2802     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2803     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2804     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2805     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2806     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2807     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2808     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2809     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2810     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2811     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2812     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2813     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2814     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2815     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2816     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2817     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2818     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2819     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2820     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2821     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2822     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2823     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2824     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2825     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2826     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2827     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2828     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2829     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2830     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2831     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2832     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2833     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2834     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2835     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2836     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2837     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2838     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2839     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2840     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2841     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2842     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2843     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2844     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2845     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2846     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2847     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2848     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2849     }
2850     if (NewMI) {
2851       MachineFunction &MF = *MI->getParent()->getParent();
2852       MI = MF.CloneMachineInstr(MI);
2853       NewMI = false;
2854     }
2855     MI->setDesc(get(Opc));
2856     // Fallthrough intended.
2857   }
2858   default:
2859     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2860   }
2861 }
2862
2863 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2864                                          unsigned &SrcOpIdx2) const {
2865   switch (MI->getOpcode()) {
2866     case X86::CMPPDrri:
2867     case X86::CMPPSrri:
2868     case X86::VCMPPDrri:
2869     case X86::VCMPPSrri:
2870     case X86::VCMPPDYrri:
2871     case X86::VCMPPSYrri: {
2872       // Float comparison can be safely commuted for
2873       // Ordered/Unordered/Equal/NotEqual tests
2874       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2875       switch (Imm) {
2876       case 0x00: // EQUAL
2877       case 0x03: // UNORDERED
2878       case 0x04: // NOT EQUAL
2879       case 0x07: // ORDERED
2880         SrcOpIdx1 = 1;
2881         SrcOpIdx2 = 2;
2882         return true;
2883       }
2884       return false;
2885     }
2886     case X86::VFMADDPDr231r:
2887     case X86::VFMADDPSr231r:
2888     case X86::VFMADDSDr231r:
2889     case X86::VFMADDSSr231r:
2890     case X86::VFMSUBPDr231r:
2891     case X86::VFMSUBPSr231r:
2892     case X86::VFMSUBSDr231r:
2893     case X86::VFMSUBSSr231r:
2894     case X86::VFNMADDPDr231r:
2895     case X86::VFNMADDPSr231r:
2896     case X86::VFNMADDSDr231r:
2897     case X86::VFNMADDSSr231r:
2898     case X86::VFNMSUBPDr231r:
2899     case X86::VFNMSUBPSr231r:
2900     case X86::VFNMSUBSDr231r:
2901     case X86::VFNMSUBSSr231r:
2902     case X86::VFMADDPDr231rY:
2903     case X86::VFMADDPSr231rY:
2904     case X86::VFMSUBPDr231rY:
2905     case X86::VFMSUBPSr231rY:
2906     case X86::VFNMADDPDr231rY:
2907     case X86::VFNMADDPSr231rY:
2908     case X86::VFNMSUBPDr231rY:
2909     case X86::VFNMSUBPSr231rY:
2910       SrcOpIdx1 = 2;
2911       SrcOpIdx2 = 3;
2912       return true;
2913     default:
2914       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2915   }
2916 }
2917
2918 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2919   switch (BrOpc) {
2920   default: return X86::COND_INVALID;
2921   case X86::JE_1:  return X86::COND_E;
2922   case X86::JNE_1: return X86::COND_NE;
2923   case X86::JL_1:  return X86::COND_L;
2924   case X86::JLE_1: return X86::COND_LE;
2925   case X86::JG_1:  return X86::COND_G;
2926   case X86::JGE_1: return X86::COND_GE;
2927   case X86::JB_1:  return X86::COND_B;
2928   case X86::JBE_1: return X86::COND_BE;
2929   case X86::JA_1:  return X86::COND_A;
2930   case X86::JAE_1: return X86::COND_AE;
2931   case X86::JS_1:  return X86::COND_S;
2932   case X86::JNS_1: return X86::COND_NS;
2933   case X86::JP_1:  return X86::COND_P;
2934   case X86::JNP_1: return X86::COND_NP;
2935   case X86::JO_1:  return X86::COND_O;
2936   case X86::JNO_1: return X86::COND_NO;
2937   }
2938 }
2939
2940 /// getCondFromSETOpc - return condition code of a SET opcode.
2941 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2942   switch (Opc) {
2943   default: return X86::COND_INVALID;
2944   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2945   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2946   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2947   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2948   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2949   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2950   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2951   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2952   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2953   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2954   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2955   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2956   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2957   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2958   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2959   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2960   }
2961 }
2962
2963 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2964 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2965   switch (Opc) {
2966   default: return X86::COND_INVALID;
2967   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2968   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2969     return X86::COND_A;
2970   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2971   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2972     return X86::COND_AE;
2973   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2974   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2975     return X86::COND_B;
2976   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2977   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2978     return X86::COND_BE;
2979   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2980   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2981     return X86::COND_E;
2982   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2983   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2984     return X86::COND_G;
2985   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2986   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2987     return X86::COND_GE;
2988   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2989   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2990     return X86::COND_L;
2991   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2992   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2993     return X86::COND_LE;
2994   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2995   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2996     return X86::COND_NE;
2997   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2998   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2999     return X86::COND_NO;
3000   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3001   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3002     return X86::COND_NP;
3003   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3004   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3005     return X86::COND_NS;
3006   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3007   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3008     return X86::COND_O;
3009   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3010   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3011     return X86::COND_P;
3012   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3013   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3014     return X86::COND_S;
3015   }
3016 }
3017
3018 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3019   switch (CC) {
3020   default: llvm_unreachable("Illegal condition code!");
3021   case X86::COND_E:  return X86::JE_1;
3022   case X86::COND_NE: return X86::JNE_1;
3023   case X86::COND_L:  return X86::JL_1;
3024   case X86::COND_LE: return X86::JLE_1;
3025   case X86::COND_G:  return X86::JG_1;
3026   case X86::COND_GE: return X86::JGE_1;
3027   case X86::COND_B:  return X86::JB_1;
3028   case X86::COND_BE: return X86::JBE_1;
3029   case X86::COND_A:  return X86::JA_1;
3030   case X86::COND_AE: return X86::JAE_1;
3031   case X86::COND_S:  return X86::JS_1;
3032   case X86::COND_NS: return X86::JNS_1;
3033   case X86::COND_P:  return X86::JP_1;
3034   case X86::COND_NP: return X86::JNP_1;
3035   case X86::COND_O:  return X86::JO_1;
3036   case X86::COND_NO: return X86::JNO_1;
3037   }
3038 }
3039
3040 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
3041 /// e.g. turning COND_E to COND_NE.
3042 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3043   switch (CC) {
3044   default: llvm_unreachable("Illegal condition code!");
3045   case X86::COND_E:  return X86::COND_NE;
3046   case X86::COND_NE: return X86::COND_E;
3047   case X86::COND_L:  return X86::COND_GE;
3048   case X86::COND_LE: return X86::COND_G;
3049   case X86::COND_G:  return X86::COND_LE;
3050   case X86::COND_GE: return X86::COND_L;
3051   case X86::COND_B:  return X86::COND_AE;
3052   case X86::COND_BE: return X86::COND_A;
3053   case X86::COND_A:  return X86::COND_BE;
3054   case X86::COND_AE: return X86::COND_B;
3055   case X86::COND_S:  return X86::COND_NS;
3056   case X86::COND_NS: return X86::COND_S;
3057   case X86::COND_P:  return X86::COND_NP;
3058   case X86::COND_NP: return X86::COND_P;
3059   case X86::COND_O:  return X86::COND_NO;
3060   case X86::COND_NO: return X86::COND_O;
3061   }
3062 }
3063
3064 /// getSwappedCondition - assume the flags are set by MI(a,b), return
3065 /// the condition code if we modify the instructions such that flags are
3066 /// set by MI(b,a).
3067 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3068   switch (CC) {
3069   default: return X86::COND_INVALID;
3070   case X86::COND_E:  return X86::COND_E;
3071   case X86::COND_NE: return X86::COND_NE;
3072   case X86::COND_L:  return X86::COND_G;
3073   case X86::COND_LE: return X86::COND_GE;
3074   case X86::COND_G:  return X86::COND_L;
3075   case X86::COND_GE: return X86::COND_LE;
3076   case X86::COND_B:  return X86::COND_A;
3077   case X86::COND_BE: return X86::COND_AE;
3078   case X86::COND_A:  return X86::COND_B;
3079   case X86::COND_AE: return X86::COND_BE;
3080   }
3081 }
3082