lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32 def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
  33
  34 //===----------------------------------------------------------------------===//
  35 // SSE specific DAG Nodes.
  36 //===----------------------------------------------------------------------===//
  37
  38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
  39                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  40                                        SDTCisVec<1>]>;
  41
  42 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  43 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  44
  45 // Commutative and Associative FMIN and FMAX.
  46 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  49     [SDNPCommutative, SDNPAssociative]>;
  50
  51 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  56                         [SDNPCommutative, SDNPAssociative]>;
  57 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
  58                         [SDNPCommutative, SDNPAssociative]>;
  59 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  60 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT",  SDTFPBinOp>;
  62 def X86frcp14s : SDNode<"X86ISD::FRCP",    SDTFPBinOp>;
  63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
  64 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  65 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  66 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  67 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  68 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  69 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  70 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  71 //def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
  72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
  73                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  74                                       SDTCisVT<1, v4i32>]>>;
  75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
  76                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  77                                       SDTCisVT<1, v4i32>]>>;
  78 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  79                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  80                                       SDTCisSameAs<0,2>]>>;
  81 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  82                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  83                                       SDTCisSameAs<0,2>]>>;
  84 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  85                   SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
  86                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  87 def X86andnp   : SDNode<"X86ISD::ANDNP",
  88                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  89                                       SDTCisSameAs<0,2>]>>;
  90 def X86psign   : SDNode<"X86ISD::PSIGN",
  91                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  92                                       SDTCisSameAs<0,2>]>>;
  93 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  94                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
  95 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  96                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
  97 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  98                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  99                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 100 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
 101                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 102                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 103 def X86insertps : SDNode<"X86ISD::INSERTPS",
 104                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 105                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 106 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 107                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 108
 109 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 110                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 111
 112 def X86vzext   : SDNode<"X86ISD::VZEXT",
 113                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 114                                               SDTCisInt<0>, SDTCisInt<1>,
 115                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 116
 117 def X86vsext   : SDNode<"X86ISD::VSEXT",
 118                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 119                                               SDTCisInt<0>, SDTCisInt<1>,
 120                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 121
 122 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 123                                        SDTCisInt<0>, SDTCisInt<1>,
 124                                        SDTCisOpSmallerThanOp<0, 1>]>;
 125
 126 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 127 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 128 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 129
 130 def X86trunc    : SDNode<"X86ISD::TRUNC",
 131                          SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
 132                                               SDTCisOpSmallerThanOp<0, 1>]>>;
 133 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 134                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 135                                              SDTCisFP<0>, SDTCisFP<1>,
 136                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 137 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 138                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 139                                              SDTCisFP<0>, SDTCisFP<1>,
 140                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 141
 142 def X86fround: SDNode<"X86ISD::VFPROUND",
 143                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 144                                              SDTCVecEltisVT<0, f32>,
 145                                              SDTCVecEltisVT<1, f64>,
 146                                              SDTCVecEltisVT<2, f64>,
 147                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 148 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
 149                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 150                                              SDTCVecEltisVT<0, f32>,
 151                                              SDTCVecEltisVT<1, f64>,
 152                                              SDTCVecEltisVT<2, f64>,
 153                                              SDTCisOpSmallerThanOp<0, 1>,
 154                                              SDTCisInt<3>]>>;
 155
 156 def X86fpext  : SDNode<"X86ISD::VFPEXT",
 157                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 158                                              SDTCVecEltisVT<0, f64>,
 159                                              SDTCVecEltisVT<1, f32>,
 160                                              SDTCVecEltisVT<2, f32>,
 161                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 162
 163 def X86fpextRnd  : SDNode<"X86ISD::VFPEXT",
 164                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 165                                              SDTCVecEltisVT<0, f64>,
 166                                              SDTCVecEltisVT<1, f32>,
 167                                              SDTCVecEltisVT<2, f32>,
 168                                              SDTCisOpSmallerThanOp<1, 0>,
 169                                              SDTCisInt<3>]>>;
 170
 171 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 172 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 173 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 174 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 175 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 176
 177 def X86IntCmpMask : SDTypeProfile<1, 2,
 178     [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
 179 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 180 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 181
 182 def X86CmpMaskCC :
 183       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 184                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 185                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 186 def X86CmpMaskCCRound :
 187       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 188                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 189                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 190                        SDTCisInt<4>]>;
 191 def X86CmpMaskCCScalar :
 192       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 193
 194 def X86CmpMaskCCScalarRound :
 195       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 196                            SDTCisInt<4>]>;
 197
 198 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 199 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 200 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 201 def X86cmpms    : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalar>;
 202 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalarRound>;
 203
 204 def X86vshl    : SDNode<"X86ISD::VSHL",
 205                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 206                                       SDTCisVec<2>]>>;
 207 def X86vsrl    : SDNode<"X86ISD::VSRL",
 208                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 209                                       SDTCisVec<2>]>>;
 210 def X86vsra    : SDNode<"X86ISD::VSRA",
 211                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 212                                       SDTCisVec<2>]>>;
 213
 214 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 215 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 216 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 217
 218 def X86vprot   : SDNode<"X86ISD::VPROT",
 219                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 220                                       SDTCisVec<2>]>>;
 221 def X86vproti  : SDNode<"X86ISD::VPROTI",
 222                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 223                                       SDTCisVT<2, i8>]>>;
 224
 225 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 226                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 227                                       SDTCisVec<2>]>>;
 228 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 229                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 230                                       SDTCisVec<2>]>>;
 231
 232 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 233                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 234                                       SDTCisVec<2>, SDTCisVT<3, i8>]>>;
 235 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 236                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 237                                       SDTCisVec<2>, SDTCisVT<3, i8>]>>;
 238
 239 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 240                                           SDTCisVec<1>,
 241                                           SDTCisSameAs<2, 1>]>;
 242 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
 243 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 244 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
 245 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 246 def X86mulhrs  : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
 247 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
 248 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 249 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 250 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 251 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 252 def X86testm   : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 253                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 254                                           SDTCVecEltisVT<0, i1>,
 255                                           SDTCisSameNumEltsAs<0, 1>]>>;
 256 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 257                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 258                                           SDTCVecEltisVT<0, i1>,
 259                                           SDTCisSameNumEltsAs<0, 1>]>>;
 260 def X86select  : SDNode<"X86ISD::SELECT"     , SDTSelect>;
 261
 262 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 263                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 264                                       SDTCisSameAs<1,2>]>>;
 265 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 266                          SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 267                                        SDTCisSameAs<1,2>]>>;
 268
 269 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 270                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 271                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 272 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 273                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 274                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 275                                          SDTCisVT<4, i8>]>>;
 276
 277 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 278 // translated into one of the target nodes below during lowering.
 279 // Note: this is a work in progress...
 280 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 281 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 282                                 SDTCisSameAs<0,2>]>;
 283 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 284                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
 285
 286 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 287                                         SDTCisVec<2>]>;
 288 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 289                                  SDTCisSameAs<0,1>, SDTCisInt<2>]>;
 290 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 291                                  SDTCisSameAs<0,2>, SDTCisInt<3>]>;
 292 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 293                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
 294 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 295                               SDTCisInt<2>, SDTCisInt<3>]>;
 296
 297 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 298 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
 299
 300 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 301                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 302
 303 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 304                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
 305                                 SDTCisInt<4>]>;
 306
 307 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 308   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
 309
 310 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 311   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
 312
 313 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 314                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 315 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 316                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
 317 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
 318                            SDTCisVec<0>, SDTCisInt<2>]>;
 319 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 320                            SDTCisVec<0>, SDTCisInt<3>]>;
 321 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 322                            SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
 323
 324 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 325 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 326
 327 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 328 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 329
 330 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 331 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 332 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 333
 334 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 335 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 336
 337 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 338 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 339 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 340
 341 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 342 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 343
 344 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 345 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 346 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 347
 348 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 349 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 350
 351 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
 352 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 353 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 354
 355 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 356 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 357
 358 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 359 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack>;
 360
 361 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 362 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 363 def X86VPermv     : SDNode<"X86ISD::VPERMV",    SDTShuff2Op>;
 364 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 365 def X86VPermv3    : SDNode<"X86ISD::VPERMV3",   SDTShuff3Op>;
 366 def X86VPermiv3   : SDNode<"X86ISD::VPERMIV3",  SDTShuff3Op>;
 367 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 368
 369 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 370
 371 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 372 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 373 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 374 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 375 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 376 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 377                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 378                                             SDTCisVec<1>, SDTCisInt<2>]>, []>;
 379
 380 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 381                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 382                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 383 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 384 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 385                               [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
 386 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 387                               [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
 388
 389 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 390
 391 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 392
 393 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 394 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 395 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 396 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 397 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 398 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 399 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 400 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 401 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRT_RND",   STDFp2SrcRm>;
 402 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 403 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
 404
 405 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 406 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 407 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 408 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 409 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 410 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 411
 412 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 413 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 414 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 415 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 416 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 417 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 418
 419 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  STDFp1SrcRm>;
 420 def X86rcp28     : SDNode<"X86ISD::RCP28",    STDFp1SrcRm>;
 421 def X86exp2      : SDNode<"X86ISD::EXP2",     STDFp1SrcRm>;
 422
 423 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",   STDFp2SrcRm>;
 424 def X86rcp28s    : SDNode<"X86ISD::RCP28",     STDFp2SrcRm>;
 425 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
 426 def X86Reduces   : SDNode<"X86ISD::VREDUCE",   STDFp3SrcRm>;
 427 def X86GetMants  : SDNode<"X86ISD::VGETMANT",  STDFp3SrcRm>;
 428
 429 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 430                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 431                                          SDTCisVT<4, i8>]>;
 432 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 433                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 434                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 435                                          SDTCisVT<6, i8>]>;
 436
 437 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 438 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 439
 440 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 441                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 442 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 443                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 444
 445 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 446                                SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
 447
 448 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 449                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 450 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 451                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 452
 453 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 454                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 455 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
 456                                              SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
 457 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 458                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 459 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 460                                             SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
 461 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 462                                            SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
 463                                            SDTCisInt<2>]>;
 464 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 465                                            SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
 466                                            SDTCisInt<2>]>;
 467
 468 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 469                                            SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
 470                                            SDTCisInt<2>]>;
 471 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 472                                            SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
 473                                            SDTCisInt<2>]>;
 474
 475 // Scalar
 476 def X86SintToFpRnd  : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTintToFPRound>;
 477 def X86UintToFpRnd  : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTintToFPRound>;
 478
 479 def X86cvttss2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSFloatToIntRnd>;
 480 def X86cvttss2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSFloatToIntRnd>;
 481 def X86cvttsd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSDoubleToIntRnd>;
 482 def X86cvttsd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSDoubleToIntRnd>;
 483 // Vector with rounding mode
 484
 485 // cvtt fp-to-int staff
 486 def X86VFpToSintRnd   : SDNode<"ISD::FP_TO_SINT",  SDTVFPToIntRound>;
 487 def X86VFpToUintRnd   : SDNode<"ISD::FP_TO_UINT",  SDTVFPToIntRound>;
 488 def X86VFpToSlongRnd  : SDNode<"ISD::FP_TO_SINT",  SDTVFPToLongRound>;
 489 def X86VFpToUlongRnd  : SDNode<"ISD::FP_TO_UINT",  SDTVFPToLongRound>;
 490
 491 def X86VSintToFpRnd   : SDNode<"ISD::SINT_TO_FP",  SDTVintToFPRound>;
 492 def X86VUintToFpRnd   : SDNode<"ISD::UINT_TO_FP",  SDTVintToFPRound>;
 493 def X86VSlongToFpRnd  : SDNode<"ISD::SINT_TO_FP",  SDTVlongToFPRound>;
 494 def X86VUlongToFpRnd  : SDNode<"ISD::UINT_TO_FP",  SDTVlongToFPRound>;
 495
 496 // cvt fp-to-int staff
 497 def X86cvtps2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToIntRnd>;
 498 def X86cvtps2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToIntRnd>;
 499 def X86cvtpd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToIntRnd>;
 500 def X86cvtpd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToIntRnd>;
 501
 502 // Vector without rounding mode
 503 def X86cvtps2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToInt>;
 504 def X86cvtps2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToInt>;
 505 def X86cvtpd2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToInt>;
 506 def X86cvtpd2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToInt>;
 507
 508 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT",
 509                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 510                                              SDTCisFP<0>, SDTCisFP<1>,
 511                                              SDTCisOpSmallerThanOp<1, 0>,
 512                                              SDTCisInt<2>]>>;
 513 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
 514                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 515                                              SDTCisFP<0>, SDTCisFP<1>,
 516                                              SDTCVecEltisVT<0, f32>,
 517                                              SDTCVecEltisVT<1, f64>,
 518                                              SDTCisInt<2>]>>;
 519
 520 //===----------------------------------------------------------------------===//
 521 // SSE Complex Patterns
 522 //===----------------------------------------------------------------------===//
 523
 524 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 525 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 526 // forms.
 527 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 528                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 529                                    SDNPWantRoot]>;
 530 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 531                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 532                                    SDNPWantRoot]>;
 533
 534 def ssmem : Operand<v4f32> {
 535   let PrintMethod = "printf32mem";
 536   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 537   let ParserMatchClass = X86Mem32AsmOperand;
 538   let OperandType = "OPERAND_MEMORY";
 539 }
 540 def sdmem : Operand<v2f64> {
 541   let PrintMethod = "printf64mem";
 542   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 543   let ParserMatchClass = X86Mem64AsmOperand;
 544   let OperandType = "OPERAND_MEMORY";
 545 }
 546
 547 //===----------------------------------------------------------------------===//
 548 // SSE pattern fragments
 549 //===----------------------------------------------------------------------===//
 550
 551 // 128-bit load pattern fragments
 552 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 553 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 554 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 555 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 556
 557 // 256-bit load pattern fragments
 558 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 559 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 560 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 561 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 562
 563 // 512-bit load pattern fragments
 564 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 565 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 566 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
 567 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 568 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 569 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 570
 571 // 128-/256-/512-bit extload pattern fragments
 572 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 573 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 574 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 575
 576 // These are needed to match a scalar load that is used in a vector-only
 577 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 578 // The memory operand is required to be a 128-bit load, so it must be converted
 579 // from a vector to a scalar.
 580 def loadf32_128 : PatFrag<(ops node:$ptr),
 581   (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
 582 def loadf64_128 : PatFrag<(ops node:$ptr),
 583   (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
 584
 585 // Like 'store', but always requires 128-bit vector alignment.
 586 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 587                            (store node:$val, node:$ptr), [{
 588   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 589 }]>;
 590
 591 // Like 'store', but always requires 256-bit vector alignment.
 592 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 593                               (store node:$val, node:$ptr), [{
 594   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 595 }]>;
 596
 597 // Like 'store', but always requires 512-bit vector alignment.
 598 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 599                               (store node:$val, node:$ptr), [{
 600   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 601 }]>;
 602
 603 // Like 'load', but always requires 128-bit vector alignment.
 604 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 605   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 606 }]>;
 607
 608 // Like 'X86vzload', but always requires 128-bit vector alignment.
 609 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
 610   return cast<MemSDNode>(N)->getAlignment() >= 16;
 611 }]>;
 612
 613 // Like 'load', but always requires 256-bit vector alignment.
 614 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 615   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 616 }]>;
 617
 618 // Like 'load', but always requires 512-bit vector alignment.
 619 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 620   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 621 }]>;
 622
 623 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
 624                                (f32 (alignedload node:$ptr))>;
 625 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
 626                                (f64 (alignedload node:$ptr))>;
 627
 628 // 128-bit aligned load pattern fragments
 629 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 630 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 631                                (v4f32 (alignedload node:$ptr))>;
 632 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 633                                (v2f64 (alignedload node:$ptr))>;
 634 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 635                                (v2i64 (alignedload node:$ptr))>;
 636
 637 // 256-bit aligned load pattern fragments
 638 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 639 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 640                                (v8f32 (alignedload256 node:$ptr))>;
 641 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 642                                (v4f64 (alignedload256 node:$ptr))>;
 643 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 644                                (v4i64 (alignedload256 node:$ptr))>;
 645
 646 // 512-bit aligned load pattern fragments
 647 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 648                                 (v16f32 (alignedload512 node:$ptr))>;
 649 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 650                                 (v16i32 (alignedload512 node:$ptr))>;
 651 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 652                                 (v8f64  (alignedload512 node:$ptr))>;
 653 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 654                                 (v8i64  (alignedload512 node:$ptr))>;
 655
 656 // Like 'load', but uses special alignment checks suitable for use in
 657 // memory operands in most SSE instructions, which are required to
 658 // be naturally aligned on some targets but not on others.  If the subtarget
 659 // allows unaligned accesses, match any load, though this may require
 660 // setting a feature bit in the processor (on startup, for example).
 661 // Opteron 10h and later implement such a feature.
 662 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 663   return    Subtarget->hasSSEUnalignedMem()
 664          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 665 }]>;
 666
 667 def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
 668 def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
 669
 670 // 128-bit memop pattern fragments
 671 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 672 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 673 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 674 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 675
 676 // These are needed to match a scalar memop that is used in a vector-only
 677 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 678 // The memory operand is required to be a 128-bit load, so it must be converted
 679 // from a vector to a scalar.
 680 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 681   (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
 682 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 683   (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
 684
 685
 686 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 687 // 16-byte boundary.
 688 // FIXME: 8 byte alignment for mmx reads is not required
 689 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 690   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 691 }]>;
 692
 693 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 694
 695 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 696   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 697   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 698     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 699             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 700   return false;
 701 }]>;
 702
 703 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 704   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 705   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 706     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 707             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 708   return false;
 709 }]>;
 710
 711 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 712   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 713   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 714     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 715             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 716   return false;
 717 }]>;
 718 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 719   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 720   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 721     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 722             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 723   return false;
 724 }]>;
 725 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 726   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 727   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 728     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 729             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 730   return false;
 731 }]>;
 732 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 733   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 734   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 735     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 736             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 737   return false;
 738 }]>;
 739
 740 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 741   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 742   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 743     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 744             Sc->getBasePtr().getValueType() == MVT::v2i64);
 745   return false;
 746 }]>;
 747
 748 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 749   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 750   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 751     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 752             Sc->getBasePtr().getValueType() == MVT::v4i32);
 753   return false;
 754 }]>;
 755
 756 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 757   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 758   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 759     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 760             Sc->getBasePtr().getValueType() == MVT::v4i64);
 761   return false;
 762 }]>;
 763
 764 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 765   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 766   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 767     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 768             Sc->getBasePtr().getValueType() == MVT::v8i32);
 769   return false;
 770 }]>;
 771
 772 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 773   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 774   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 775     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 776             Sc->getBasePtr().getValueType() == MVT::v8i64);
 777   return false;
 778 }]>;
 779 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 780   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 781   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 782     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 783             Sc->getBasePtr().getValueType() == MVT::v16i32);
 784   return false;
 785 }]>;
 786
 787 // 128-bit bitconvert pattern fragments
 788 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 789 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 790 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 791 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 792 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 793 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 794
 795 // 256-bit bitconvert pattern fragments
 796 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 797 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 798 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 799 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 800 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 801
 802 // 512-bit bitconvert pattern fragments
 803 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 804 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 805 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 806 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 807
 808 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 809                            (bitconvert (v2i64 (X86vzmovl
 810                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 811 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 812                            (bitconvert (v4i32 (X86vzmovl
 813                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 814
 815 def vzload_v2i64 : PatFrag<(ops node:$src),
 816                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 817
 818
 819 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 820   return N->isExactlyValue(+0.0);
 821 }]>;
 822
 823 def I8Imm : SDNodeXForm<imm, [{
 824   // Transformation function: get the low 8 bits.
 825   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 826 }]>;
 827
 828 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 829 def FROUND_CURRENT : ImmLeaf<i32, [{
 830   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 831 }]>;
 832
 833 // BYTE_imm - Transform bit immediates into byte immediates.
 834 def BYTE_imm  : SDNodeXForm<imm, [{
 835   // Transformation function: imm >> 3
 836   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 837 }]>;
 838
 839 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 840 // to VEXTRACTF128/VEXTRACTI128 imm.
 841 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 842   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 843 }]>;
 844
 845 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 846 // VINSERTF128/VINSERTI128 imm.
 847 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 848   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 849 }]>;
 850
 851 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 852 // to VEXTRACTF64x4 imm.
 853 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 854   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 855 }]>;
 856
 857 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 858 // VINSERTF64x4 imm.
 859 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 860   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 861 }]>;
 862
 863 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 864                                    (extract_subvector node:$bigvec,
 865                                                       node:$index), [{
 866   return X86::isVEXTRACT128Index(N);
 867 }], EXTRACT_get_vextract128_imm>;
 868
 869 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 870                                       node:$index),
 871                                  (insert_subvector node:$bigvec, node:$smallvec,
 872                                                    node:$index), [{
 873   return X86::isVINSERT128Index(N);
 874 }], INSERT_get_vinsert128_imm>;
 875
 876
 877 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 878                                    (extract_subvector node:$bigvec,
 879                                                       node:$index), [{
 880   return X86::isVEXTRACT256Index(N);
 881 }], EXTRACT_get_vextract256_imm>;
 882
 883 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 884                                       node:$index),
 885                                  (insert_subvector node:$bigvec, node:$smallvec,
 886                                                    node:$index), [{
 887   return X86::isVINSERT256Index(N);
 888 }], INSERT_get_vinsert256_imm>;
 889
 890 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 891                          (masked_load node:$src1, node:$src2, node:$src3), [{
 892   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 893     return Load->getAlignment() >= 16;
 894   return false;
 895 }]>;
 896
 897 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 898                          (masked_load node:$src1, node:$src2, node:$src3), [{
 899   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 900     return Load->getAlignment() >= 32;
 901   return false;
 902 }]>;
 903
 904 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 905                          (masked_load node:$src1, node:$src2, node:$src3), [{
 906   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 907     return Load->getAlignment() >= 64;
 908   return false;
 909 }]>;
 910
 911 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 912                          (masked_load node:$src1, node:$src2, node:$src3), [{
 913   return isa<MaskedLoadSDNode>(N);
 914 }]>;
 915
 916 // masked store fragments.
 917 // X86mstore can't be implemented in core DAG files because some targets
 918 // doesn't support vector type ( llvm-tblgen will fail)
 919 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 920                         (masked_store node:$src1, node:$src2, node:$src3), [{
 921   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 922 }]>;
 923
 924 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 925                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 926   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 927     return Store->getAlignment() >= 16;
 928   return false;
 929 }]>;
 930
 931 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 932                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 933   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 934     return Store->getAlignment() >= 32;
 935   return false;
 936 }]>;
 937
 938 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 939                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 940   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 941     return Store->getAlignment() >= 64;
 942   return false;
 943 }]>;
 944
 945 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 946                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 947   return isa<MaskedStoreSDNode>(N);
 948 }]>;
 949
 950 // masked truncstore fragments
 951 // X86mtruncstore can't be implemented in core DAG files because some targets
 952 // doesn't support vector type ( llvm-tblgen will fail)
 953 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 954                              (masked_store node:$src1, node:$src2, node:$src3), [{
 955     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 956 }]>;
 957 def masked_truncstorevi8 :
 958   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 959           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 960   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
 961 }]>;
 962 def masked_truncstorevi16 :
 963   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 964           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 965   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
 966 }]>;
 967 def masked_truncstorevi32 :
 968   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 969           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 970   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
 971 }]>;