1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
23 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
24 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
25 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
26 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
30 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
31 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
32 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
33 [SDNPHasChain, SDNPOutFlag]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
49 //===----------------------------------------------------------------------===//
50 // FPStack pattern fragments
51 //===----------------------------------------------------------------------===//
53 def fpimm0 : PatLeaf<(fpimm), [{
54 return N->isExactlyValue(+0.0);
57 def fpimmneg0 : PatLeaf<(fpimm), [{
58 return N->isExactlyValue(-0.0);
61 def fpimm1 : PatLeaf<(fpimm), [{
62 return N->isExactlyValue(+1.0);
65 def fpimmneg1 : PatLeaf<(fpimm), [{
66 return N->isExactlyValue(-1.0);
69 // Some 'special' instructions
70 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
71 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
72 (ops i16mem:$dst, RFP32:$src),
73 "#FP32_TO_INT16_IN_MEM PSEUDO!",
74 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
75 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
76 (ops i32mem:$dst, RFP32:$src),
77 "#FP32_TO_INT32_IN_MEM PSEUDO!",
78 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
79 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
80 (ops i64mem:$dst, RFP32:$src),
81 "#FP32_TO_INT64_IN_MEM PSEUDO!",
82 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
83 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
84 (ops i16mem:$dst, RFP64:$src),
85 "#FP64_TO_INT16_IN_MEM PSEUDO!",
86 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
87 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
88 (ops i32mem:$dst, RFP64:$src),
89 "#FP64_TO_INT32_IN_MEM PSEUDO!",
90 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
91 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
92 (ops i64mem:$dst, RFP64:$src),
93 "#FP64_TO_INT64_IN_MEM PSEUDO!",
94 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 let isTerminator = 1 in
98 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
99 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
101 // All FP Stack operations are represented with three instructions here. The
102 // first two instructions, generated by the instruction selector, uses "RFP32"
103 // or "RFP64" registers: traditional register files to reference 32-bit or
104 // 64-bit floating point values. These sizes apply to the values, not the
105 // registers, which are always 64 bits; RFP32 and RFP64 can be copied to
106 // each other without losing information. These instructions are all psuedo
107 // instructions and use the "_Fp" suffix.
108 // In some cases there are additional variants with a mixture of 32-bit and
110 // The second instruction is defined with FPI, which is the actual instruction
111 // emitted by the assembler. These use "RST" registers, although frequently
112 // the actual register(s) used are implicit. These are always 64-bits.
113 // The FP stackifier pass converts one to the other after register allocation
116 // Note that the FpI instruction should have instruction selection info (e.g.
117 // a pattern) and the FPI instruction should have emission info (e.g. opcode
118 // encoding and asm printing info).
120 // FPI - Floating Point Instruction template.
121 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
123 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
124 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
125 : X86Inst<0, Pseudo, NoImm, ops, ""> {
126 let FPForm = fp; let FPFormBits = FPForm.Value;
127 let Pattern = pattern;
130 // Random Pseudo Instructions.
131 def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP,
132 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
134 def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP,
135 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
137 let noResults = 1 in {
138 def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP,
139 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
141 def FpSETRESULT64 : FpI_<(ops RFP64:$src), SpecialFP,
142 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
144 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
145 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
146 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
148 // Register copies. Just copies, the 64->32 version does not truncate.
149 def MOV_Fp3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
150 def MOV_Fp3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
151 def MOV_Fp6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
152 def MOV_Fp6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
154 // Factoring for arithmetic.
155 multiclass FPBinary_rr<SDNode OpNode> {
156 // Register op register -> register
157 // These are separated out because they have no reversed form.
158 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
159 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
160 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
161 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
163 // The FopST0 series are not included here because of the irregularities
164 // in where the 'r' goes in assembly output.
165 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
166 // ST(0) = ST(0) + [mem]
167 def _Fp32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
168 [(set RFP32:$dst, (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
169 def _Fp64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
170 [(set RFP64:$dst, (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
171 def _F32m : FPI<0xD8, fp, (ops f32mem:$src), !strconcat("f", !strconcat(asmstring, "{s} $src"))>;
172 def _F64m : FPI<0xDC, fp, (ops f64mem:$src), !strconcat("f", !strconcat(asmstring, "{l} $src"))>;
173 // ST(0) = ST(0) + [memint]
174 def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
175 [(set RFP32:$dst, (OpNode RFP32:$src1,
176 (X86fild addr:$src2, i16)))]>;
177 def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
178 [(set RFP32:$dst, (OpNode RFP32:$src1,
179 (X86fild addr:$src2, i32)))]>;
180 def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
181 [(set RFP64:$dst, (OpNode RFP64:$src1,
182 (X86fild addr:$src2, i16)))]>;
183 def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
184 [(set RFP64:$dst, (OpNode RFP64:$src1,
185 (X86fild addr:$src2, i32)))]>;
186 def _FI16m : FPI<0xDE, fp, (ops i16mem:$src), !strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
187 def _FI32m : FPI<0xDA, fp, (ops i32mem:$src), !strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
190 defm ADD : FPBinary_rr<fadd>;
191 defm SUB : FPBinary_rr<fsub>;
192 defm MUL : FPBinary_rr<fmul>;
193 defm DIV : FPBinary_rr<fdiv>;
194 defm ADD : FPBinary<fadd, MRM0m, "add">;
195 defm SUB : FPBinary<fsub, MRM4m, "sub">;
196 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
197 defm MUL : FPBinary<fmul, MRM1m, "mul">;
198 defm DIV : FPBinary<fdiv, MRM6m, "div">;
199 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
201 class FPST0rInst<bits<8> o, string asm>
202 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
203 class FPrST0Inst<bits<8> o, string asm>
204 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
205 class FPrST0PInst<bits<8> o, string asm>
206 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
208 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
209 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
210 // we have to put some 'r's in and take them out of weird places.
211 def ADD_FST0r : FPST0rInst <0xC0, "fadd $op">;
212 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
213 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp $op">;
214 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr $op">;
215 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
216 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
217 def SUB_FST0r : FPST0rInst <0xE0, "fsub $op">;
218 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
219 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
220 def MUL_FST0r : FPST0rInst <0xC8, "fmul $op">;
221 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
222 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
223 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr $op">;
224 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
225 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
226 def DIV_FST0r : FPST0rInst <0xF0, "fdiv $op">;
227 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
228 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
231 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
232 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW,
233 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
234 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW,
235 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
236 def _F : FPI<opcode, RawFrm, (ops), asmstring>, D9;
239 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
240 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
241 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
242 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
243 defm COS : FPUnary<fcos, 0xFF, "fcos">;
245 def TST_Fp32 : FpI<(ops RFP32:$src), OneArgFP,
247 def TST_Fp64 : FpI<(ops RFP64:$src), OneArgFP,
249 def TST_F : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
251 // Floating point cmovs.
252 multiclass FPCMov<PatLeaf cc> {
253 def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP,
254 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
256 def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP,
257 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
260 let isTwoAddress = 1 in {
261 defm CMOVB : FPCMov<X86_COND_B>;
262 defm CMOVBE : FPCMov<X86_COND_BE>;
263 defm CMOVE : FPCMov<X86_COND_E>;
264 defm CMOVP : FPCMov<X86_COND_P>;
265 defm CMOVNB : FPCMov<X86_COND_AE>;
266 defm CMOVNBE: FPCMov<X86_COND_A>;
267 defm CMOVNE : FPCMov<X86_COND_NE>;
268 defm CMOVNP : FPCMov<X86_COND_NP>;
271 // These are not factored because there's no clean way to pass DA/DB.
272 def CMOVB_F : FPI<0xC0, AddRegFrm, (ops RST:$op),
273 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
274 def CMOVBE_F : FPI<0xD0, AddRegFrm, (ops RST:$op),
275 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
276 def CMOVE_F : FPI<0xC8, AddRegFrm, (ops RST:$op),
277 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
278 def CMOVP_F : FPI<0xD8, AddRegFrm, (ops RST:$op),
279 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
280 def CMOVNB_F : FPI<0xC0, AddRegFrm, (ops RST:$op),
281 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
282 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (ops RST:$op),
283 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
284 def CMOVNE_F : FPI<0xC8, AddRegFrm, (ops RST:$op),
285 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
286 def CMOVNP_F : FPI<0xD8, AddRegFrm, (ops RST:$op),
287 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
289 // Floating point loads & stores.
290 def LD_Fp32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP,
291 [(set RFP32:$dst, (loadf32 addr:$src))]>;
292 def LD_Fp64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP,
293 [(set RFP64:$dst, (loadf64 addr:$src))]>;
294 def ILD_Fp16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP,
295 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
296 def ILD_Fp32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP,
297 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
298 def ILD_Fp64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP,
299 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
300 def ILD_Fp16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP,
301 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
302 def ILD_Fp32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP,
303 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
304 def ILD_Fp64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP,
305 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
307 def ST_Fp32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP,
308 [(store RFP32:$src, addr:$op)]>;
309 def ST_Fp64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP,
310 [(truncstoref32 RFP64:$src, addr:$op)]>;
311 def ST_Fp64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP,
312 [(store RFP64:$src, addr:$op)]>;
314 def ST_FpP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>;
315 def ST_FpP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>;
316 def ST_FpP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>;
317 def IST_Fp16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>;
318 def IST_Fp32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>;
319 def IST_Fp64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>;
320 def IST_Fp16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>;
321 def IST_Fp32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>;
322 def IST_Fp64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>;
324 def LD_F32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
325 def LD_F64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
326 def ILD_F16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
327 def ILD_F32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
328 def ILD_F64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
329 def ST_F32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
330 def ST_F64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
331 def ST_FP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
332 def ST_FP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
333 def IST_F16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
334 def IST_F32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
335 def IST_FP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
336 def IST_FP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
337 def IST_FP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
339 // FISTTP requires SSE3 even though it's a FPStack op.
340 def ISTT_Fp16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP,
341 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
343 def ISTT_Fp32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP,
344 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
346 def ISTT_Fp64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP,
347 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
349 def ISTT_Fp16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP,
350 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
352 def ISTT_Fp32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP,
353 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
355 def ISTT_Fp64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP,
356 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
359 def ISTT_FP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
360 def ISTT_FP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
361 def ISTT_FP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
363 // FP Stack manipulation instructions.
364 def LD_Frr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
365 def ST_Frr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
366 def ST_FPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
367 def XCH_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
369 // Floating point constant loads.
370 let isReMaterializable = 1 in {
371 def LD_Fp032 : FpI<(ops RFP32:$dst), ZeroArgFP,
372 [(set RFP32:$dst, fpimm0)]>;
373 def LD_Fp132 : FpI<(ops RFP32:$dst), ZeroArgFP,
374 [(set RFP32:$dst, fpimm1)]>;
375 def LD_Fp064 : FpI<(ops RFP64:$dst), ZeroArgFP,
376 [(set RFP64:$dst, fpimm0)]>;
377 def LD_Fp164 : FpI<(ops RFP64:$dst), ZeroArgFP,
378 [(set RFP64:$dst, fpimm1)]>;
381 def LD_F0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
382 def LD_F1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
385 // Floating point compares.
386 def UCOM_Fpr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP,
387 []>; // FPSW = cmp ST(0) with ST(i)
388 def UCOM_FpIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP,
389 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = cmp ST(0) with ST(i)
390 def UCOM_Fpr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP,
391 []>; // FPSW = cmp ST(0) with ST(i)
392 def UCOM_FpIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP,
393 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = cmp ST(0) with ST(i)
395 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
397 "fucom $reg">, DD, Imp<[ST0],[]>;
398 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
400 "fucomp $reg">, DD, Imp<[ST0],[]>;
401 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
403 "fucompp">, DA, Imp<[ST0],[]>;
405 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
407 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
408 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
410 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
412 // Floating point flag ops.
413 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
414 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
416 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
417 (ops i16mem:$dst), "fnstcw $dst", []>;
418 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
419 (ops i16mem:$dst), "fldcw $dst", []>;
421 //===----------------------------------------------------------------------===//
422 // Non-Instruction Patterns
423 //===----------------------------------------------------------------------===//
425 // Required for RET of f32 / f64 values.
426 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
427 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
429 // Required for CALL which return f32 / f64 values.
430 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
431 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
432 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
434 // Floating point constant -0.0 and -1.0
435 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
436 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
437 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
438 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
440 // Used to conv. i64 to f64 since there isn't a SSE version.
441 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
443 def : Pat<(extloadf32 addr:$src), (MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
444 def : Pat<(fextend RFP32:$src), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;