1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
35 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
36 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
37 [SDNPHasChain, SDNPOutFlag]>;
38 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
41 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
42 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
43 [SDNPHasChain, SDNPMayLoad]>;
44 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
45 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
46 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
50 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
52 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
55 //===----------------------------------------------------------------------===//
56 // FPStack pattern fragments
57 //===----------------------------------------------------------------------===//
59 def fpimm0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(+0.0);
63 def fpimmneg0 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(-0.0);
67 def fpimm1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+1.0);
71 def fpimmneg1 : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-1.0);
75 // Some 'special' instructions
76 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
77 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
78 (outs), (ins i16mem:$dst, RFP32:$src),
79 "#FP32_TO_INT16_IN_MEM PSEUDO!",
80 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
82 (outs), (ins i32mem:$dst, RFP32:$src),
83 "#FP32_TO_INT32_IN_MEM PSEUDO!",
84 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
85 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
86 (outs), (ins i64mem:$dst, RFP32:$src),
87 "#FP32_TO_INT64_IN_MEM PSEUDO!",
88 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
89 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
90 (outs), (ins i16mem:$dst, RFP64:$src),
91 "#FP64_TO_INT16_IN_MEM PSEUDO!",
92 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
94 (outs), (ins i32mem:$dst, RFP64:$src),
95 "#FP64_TO_INT32_IN_MEM PSEUDO!",
96 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
97 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
98 (outs), (ins i64mem:$dst, RFP64:$src),
99 "#FP64_TO_INT64_IN_MEM PSEUDO!",
100 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
101 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
102 (outs), (ins i16mem:$dst, RFP80:$src),
103 "#FP80_TO_INT16_IN_MEM PSEUDO!",
104 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
106 (outs), (ins i32mem:$dst, RFP80:$src),
107 "#FP80_TO_INT32_IN_MEM PSEUDO!",
108 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
109 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
110 (outs), (ins i64mem:$dst, RFP80:$src),
111 "#FP80_TO_INT64_IN_MEM PSEUDO!",
112 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
115 let isTerminator = 1 in
116 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
117 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
119 // All FP Stack operations are represented with four instructions here. The
120 // first three instructions, generated by the instruction selector, use "RFP32"
121 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
122 // 64-bit or 80-bit floating point values. These sizes apply to the values,
123 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
124 // copied to each other without losing information. These instructions are all
125 // pseudo instructions and use the "_Fp" suffix.
126 // In some cases there are additional variants with a mixture of different
128 // The second instruction is defined with FPI, which is the actual instruction
129 // emitted by the assembler. These use "RST" registers, although frequently
130 // the actual register(s) used are implicit. These are always 80 bits.
131 // The FP stackifier pass converts one to the other after register allocation
134 // Note that the FpI instruction should have instruction selection info (e.g.
135 // a pattern) and the FPI instruction should have emission info (e.g. opcode
136 // encoding and asm printing info).
138 // Pseudo Instructions for FP stack return values.
139 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
140 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
142 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
143 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
145 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
146 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
148 let Defs = [ST0] in {
149 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
150 [(X86fpset RFP32:$src)]>;// ST(0) = FPR
152 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
153 [(X86fpset RFP64:$src)]>;// ST(0) = FPR
155 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
156 [(X86fpset RFP80:$src)]>;// ST(0) = FPR
159 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
160 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
161 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
162 // f80 instructions cannot use SSE and use neither of these.
163 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
164 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
165 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
166 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
168 // Register copies. Just copies, the shortening ones do not truncate.
169 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
170 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
171 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
172 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
173 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
174 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
175 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
176 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
177 def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
179 // Factoring for arithmetic.
180 multiclass FPBinary_rr<SDNode OpNode> {
181 // Register op register -> register
182 // These are separated out because they have no reversed form.
183 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
184 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
185 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
186 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
187 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
188 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
190 // The FopST0 series are not included here because of the irregularities
191 // in where the 'r' goes in assembly output.
192 // These instructions cannot address 80-bit memory.
193 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
194 // ST(0) = ST(0) + [mem]
195 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
197 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
198 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
200 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
201 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
203 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
204 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
206 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
207 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
209 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
210 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
211 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
212 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
213 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
214 // ST(0) = ST(0) + [memint]
215 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
216 [(set RFP32:$dst, (OpNode RFP32:$src1,
217 (X86fild addr:$src2, i16)))]>;
218 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
219 [(set RFP32:$dst, (OpNode RFP32:$src1,
220 (X86fild addr:$src2, i32)))]>;
221 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
222 [(set RFP64:$dst, (OpNode RFP64:$src1,
223 (X86fild addr:$src2, i16)))]>;
224 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
225 [(set RFP64:$dst, (OpNode RFP64:$src1,
226 (X86fild addr:$src2, i32)))]>;
227 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
228 [(set RFP80:$dst, (OpNode RFP80:$src1,
229 (X86fild addr:$src2, i16)))]>;
230 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
231 [(set RFP80:$dst, (OpNode RFP80:$src1,
232 (X86fild addr:$src2, i32)))]>;
233 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
234 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
235 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
236 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
239 defm ADD : FPBinary_rr<fadd>;
240 defm SUB : FPBinary_rr<fsub>;
241 defm MUL : FPBinary_rr<fmul>;
242 defm DIV : FPBinary_rr<fdiv>;
243 defm ADD : FPBinary<fadd, MRM0m, "add">;
244 defm SUB : FPBinary<fsub, MRM4m, "sub">;
245 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
246 defm MUL : FPBinary<fmul, MRM1m, "mul">;
247 defm DIV : FPBinary<fdiv, MRM6m, "div">;
248 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
250 class FPST0rInst<bits<8> o, string asm>
251 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
252 class FPrST0Inst<bits<8> o, string asm>
253 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
254 class FPrST0PInst<bits<8> o, string asm>
255 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
257 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
258 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
259 // we have to put some 'r's in and take them out of weird places.
260 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
261 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
262 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
263 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
264 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
265 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
266 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
267 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
268 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
269 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
270 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
271 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
272 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
273 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
274 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
275 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
276 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
277 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
280 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
281 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
282 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
283 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
284 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
285 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
286 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
287 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
290 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
291 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
292 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
293 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
294 defm COS : FPUnary<fcos, 0xFF, "fcos">;
296 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP,
298 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP,
300 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP,
302 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
304 // Floating point cmovs.
305 multiclass FPCMov<PatLeaf cc> {
306 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
308 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
310 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
312 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
314 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
316 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
319 let Uses = [EFLAGS], isTwoAddress = 1 in {
320 defm CMOVB : FPCMov<X86_COND_B>;
321 defm CMOVBE : FPCMov<X86_COND_BE>;
322 defm CMOVE : FPCMov<X86_COND_E>;
323 defm CMOVP : FPCMov<X86_COND_P>;
324 defm CMOVNB : FPCMov<X86_COND_AE>;
325 defm CMOVNBE: FPCMov<X86_COND_A>;
326 defm CMOVNE : FPCMov<X86_COND_NE>;
327 defm CMOVNP : FPCMov<X86_COND_NP>;
330 // These are not factored because there's no clean way to pass DA/DB.
331 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
332 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
333 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
334 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
335 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
336 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
337 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
338 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
339 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
340 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
341 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
342 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
343 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
344 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
345 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
346 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
348 // Floating point loads & stores.
349 let isSimpleLoad = 1 in {
350 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
351 [(set RFP32:$dst, (loadf32 addr:$src))]>;
352 let isReMaterializable = 1, mayHaveSideEffects = 1 in
353 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
354 [(set RFP64:$dst, (loadf64 addr:$src))]>;
355 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
356 [(set RFP80:$dst, (loadf80 addr:$src))]>;
358 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
359 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
360 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
361 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
362 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
363 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
364 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
365 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
366 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
367 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
368 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
369 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
370 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
371 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
372 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
373 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
374 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
375 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
376 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
377 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
378 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
379 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
380 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
381 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
383 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
384 [(store RFP32:$src, addr:$op)]>;
385 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
386 [(truncstoref32 RFP64:$src, addr:$op)]>;
387 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
388 [(store RFP64:$src, addr:$op)]>;
389 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
390 [(truncstoref32 RFP80:$src, addr:$op)]>;
391 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
392 [(truncstoref64 RFP80:$src, addr:$op)]>;
393 // FST does not support 80-bit memory target; FSTP must be used.
395 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
396 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
397 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
398 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
399 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
400 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
401 [(store RFP80:$src, addr:$op)]>;
402 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
403 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
404 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
405 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
406 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
407 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
408 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
409 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
410 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
412 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
413 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
414 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
415 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
416 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
417 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
418 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
419 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
420 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
421 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
422 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
423 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
424 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
425 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
426 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
427 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
429 // FISTTP requires SSE3 even though it's a FPStack op.
430 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
431 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
433 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
434 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
436 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
437 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
439 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
440 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
442 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
443 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
445 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
446 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
448 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
449 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
451 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
452 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
454 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
455 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
458 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
459 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
460 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
462 // FP Stack manipulation instructions.
463 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
464 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
465 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
466 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
468 // Floating point constant loads.
469 let isReMaterializable = 1 in {
470 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
471 [(set RFP32:$dst, fpimm0)]>;
472 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
473 [(set RFP32:$dst, fpimm1)]>;
474 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
475 [(set RFP64:$dst, fpimm0)]>;
476 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
477 [(set RFP64:$dst, fpimm1)]>;
478 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
479 [(set RFP80:$dst, fpimm0)]>;
480 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
481 [(set RFP80:$dst, fpimm1)]>;
484 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
485 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
488 // Floating point compares.
489 let Defs = [EFLAGS] in {
490 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
491 []>; // FPSW = cmp ST(0) with ST(i)
492 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
493 [(X86cmp RFP32:$lhs, RFP32:$rhs),
494 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
495 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
496 []>; // FPSW = cmp ST(0) with ST(i)
497 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
498 [(X86cmp RFP64:$lhs, RFP64:$rhs),
499 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
500 def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
501 []>; // FPSW = cmp ST(0) with ST(i)
502 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
503 [(X86cmp RFP80:$lhs, RFP80:$rhs),
504 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
507 let Defs = [EFLAGS], Uses = [ST0] in {
508 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
509 (outs), (ins RST:$reg),
511 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
512 (outs), (ins RST:$reg),
514 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
518 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
519 (outs), (ins RST:$reg),
520 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
521 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
522 (outs), (ins RST:$reg),
523 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
526 // Floating point flag ops.
528 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
529 (outs), (ins), "fnstsw", []>, DF;
531 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
532 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
533 [(X86fp_cwd_get16 addr:$dst)]>;
534 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
535 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
537 //===----------------------------------------------------------------------===//
538 // Non-Instruction Patterns
539 //===----------------------------------------------------------------------===//
541 // Required for RET of f32 / f64 / f80 values.
542 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
543 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
544 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
546 // Required for CALL which return f32 / f64 / f80 values.
547 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
548 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
549 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
550 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
551 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
552 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
554 // Floating point constant -0.0 and -1.0
555 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
556 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
557 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
558 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
559 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
560 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
562 // Used to conv. i64 to f64 since there isn't a SSE version.
563 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
565 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStackf32]>;
566 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStackf32]>;
567 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStackf64]>;