1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
34 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
35 [SDNPHasChain, SDNPMayLoad]>;
36 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
37 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
38 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
39 [SDNPHasChain, SDNPMayLoad]>;
40 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
41 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
42 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
43 [SDNPHasChain, SDNPMayStore]>;
44 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
45 [SDNPHasChain, SDNPMayStore]>;
46 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
47 [SDNPHasChain, SDNPMayStore]>;
48 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
49 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
51 //===----------------------------------------------------------------------===//
52 // FPStack pattern fragments
53 //===----------------------------------------------------------------------===//
55 def fpimm0 : PatLeaf<(fpimm), [{
56 return N->isExactlyValue(+0.0);
59 def fpimmneg0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(-0.0);
63 def fpimm1 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+1.0);
67 def fpimmneg1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-1.0);
71 // Some 'special' instructions
72 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
73 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
74 (outs), (ins i16mem:$dst, RFP32:$src),
75 "##FP32_TO_INT16_IN_MEM PSEUDO!",
76 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
77 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
78 (outs), (ins i32mem:$dst, RFP32:$src),
79 "##FP32_TO_INT32_IN_MEM PSEUDO!",
80 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
82 (outs), (ins i64mem:$dst, RFP32:$src),
83 "##FP32_TO_INT64_IN_MEM PSEUDO!",
84 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
85 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
86 (outs), (ins i16mem:$dst, RFP64:$src),
87 "##FP64_TO_INT16_IN_MEM PSEUDO!",
88 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
89 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
90 (outs), (ins i32mem:$dst, RFP64:$src),
91 "##FP64_TO_INT32_IN_MEM PSEUDO!",
92 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
94 (outs), (ins i64mem:$dst, RFP64:$src),
95 "##FP64_TO_INT64_IN_MEM PSEUDO!",
96 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
97 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
98 (outs), (ins i16mem:$dst, RFP80:$src),
99 "##FP80_TO_INT16_IN_MEM PSEUDO!",
100 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
101 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
102 (outs), (ins i32mem:$dst, RFP80:$src),
103 "##FP80_TO_INT32_IN_MEM PSEUDO!",
104 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
106 (outs), (ins i64mem:$dst, RFP80:$src),
107 "##FP80_TO_INT64_IN_MEM PSEUDO!",
108 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
111 let isTerminator = 1 in
112 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
113 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
115 // All FP Stack operations are represented with four instructions here. The
116 // first three instructions, generated by the instruction selector, use "RFP32"
117 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
118 // 64-bit or 80-bit floating point values. These sizes apply to the values,
119 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
120 // copied to each other without losing information. These instructions are all
121 // pseudo instructions and use the "_Fp" suffix.
122 // In some cases there are additional variants with a mixture of different
124 // The second instruction is defined with FPI, which is the actual instruction
125 // emitted by the assembler. These use "RST" registers, although frequently
126 // the actual register(s) used are implicit. These are always 80 bits.
127 // The FP stackifier pass converts one to the other after register allocation
130 // Note that the FpI instruction should have instruction selection info (e.g.
131 // a pattern) and the FPI instruction should have emission info (e.g. opcode
132 // encoding and asm printing info).
134 // Pseudo Instructions for FP stack return values.
135 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
136 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
137 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
139 // FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
140 // there are two values live out on the stack from a call or inlineasm. This
141 // magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and
142 // then FpGET_ST0*. In addition, it is invalid for any FP-using operations to
143 // occur between them.
144 def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
145 def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
146 def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
148 let Defs = [ST0] in {
149 def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
150 def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
151 def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
154 let Defs = [ST1] in {
155 def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
156 def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
157 def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
160 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
161 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
162 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
163 // f80 instructions cannot use SSE and use neither of these.
164 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
165 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
166 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
167 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
169 // Register copies. Just copies, the shortening ones do not truncate.
170 let neverHasSideEffects = 1 in {
171 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
172 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
173 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
174 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
175 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
176 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
177 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
178 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
179 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
182 // Factoring for arithmetic.
183 multiclass FPBinary_rr<SDNode OpNode> {
184 // Register op register -> register
185 // These are separated out because they have no reversed form.
186 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
187 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
188 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
189 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
190 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
191 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
193 // The FopST0 series are not included here because of the irregularities
194 // in where the 'r' goes in assembly output.
195 // These instructions cannot address 80-bit memory.
196 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
197 // ST(0) = ST(0) + [mem]
198 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
200 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
201 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
203 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
204 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
206 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
207 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
209 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
210 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
212 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
213 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
214 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
215 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
216 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
217 // ST(0) = ST(0) + [memint]
218 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
219 [(set RFP32:$dst, (OpNode RFP32:$src1,
220 (X86fild addr:$src2, i16)))]>;
221 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
222 [(set RFP32:$dst, (OpNode RFP32:$src1,
223 (X86fild addr:$src2, i32)))]>;
224 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
225 [(set RFP64:$dst, (OpNode RFP64:$src1,
226 (X86fild addr:$src2, i16)))]>;
227 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
228 [(set RFP64:$dst, (OpNode RFP64:$src1,
229 (X86fild addr:$src2, i32)))]>;
230 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
231 [(set RFP80:$dst, (OpNode RFP80:$src1,
232 (X86fild addr:$src2, i16)))]>;
233 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
234 [(set RFP80:$dst, (OpNode RFP80:$src1,
235 (X86fild addr:$src2, i32)))]>;
236 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
237 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
238 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
239 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
242 defm ADD : FPBinary_rr<fadd>;
243 defm SUB : FPBinary_rr<fsub>;
244 defm MUL : FPBinary_rr<fmul>;
245 defm DIV : FPBinary_rr<fdiv>;
246 defm ADD : FPBinary<fadd, MRM0m, "add">;
247 defm SUB : FPBinary<fsub, MRM4m, "sub">;
248 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
249 defm MUL : FPBinary<fmul, MRM1m, "mul">;
250 defm DIV : FPBinary<fdiv, MRM6m, "div">;
251 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
253 class FPST0rInst<bits<8> o, string asm>
254 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
255 class FPrST0Inst<bits<8> o, string asm>
256 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
257 class FPrST0PInst<bits<8> o, string asm>
258 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
260 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
261 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
262 // we have to put some 'r's in and take them out of weird places.
263 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
264 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
265 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
266 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
267 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
268 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
269 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
270 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
271 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
272 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
273 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
274 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
275 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
276 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
277 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
278 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
279 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
280 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
283 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
284 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
285 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
286 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
287 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
288 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
289 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
290 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
293 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
294 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
295 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
296 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
297 defm COS : FPUnary<fcos, 0xFF, "fcos">;
299 let neverHasSideEffects = 1 in {
300 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
301 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
302 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
304 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
306 // Versions of FP instructions that take a single memory operand. Added for the
307 // disassembler; remove as they are included with patterns elsewhere.
308 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom\t$src">;
309 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp\t$src">;
311 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
312 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fstenv\t$dst">;
314 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
315 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
317 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom\t$src">;
318 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp\t$src">;
320 def FLD64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld\t$src">;
321 def FISTTP32m: FPI<0xDD, MRM1m, (outs i32mem:$dst), (ins), "fisttp{l}\t$dst">;
322 def FST64m : FPI<0xDD, MRM2m, (outs f64mem:$dst), (ins), "fst\t$dst">;
323 def FSTP64m : FPI<0xDD, MRM3m, (outs f64mem:$dst), (ins), "fld\t$dst">;
324 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
325 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fsave\t$dst">;
326 def FSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fstsw\t$dst">;
328 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{w}\t$src">;
329 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{w}\t$src">;
331 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
332 def FILD64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{q}\t$src">;
333 def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">;
334 def FISTP64m : FPI<0xDF, MRM7m, (outs i64mem:$dst), (ins), "fistp{q}\t$dst">;
336 // Floating point cmovs.
337 multiclass FPCMov<PatLeaf cc> {
338 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
340 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
342 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
344 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
346 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
348 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
351 let Uses = [EFLAGS], isTwoAddress = 1 in {
352 defm CMOVB : FPCMov<X86_COND_B>;
353 defm CMOVBE : FPCMov<X86_COND_BE>;
354 defm CMOVE : FPCMov<X86_COND_E>;
355 defm CMOVP : FPCMov<X86_COND_P>;
356 defm CMOVNB : FPCMov<X86_COND_AE>;
357 defm CMOVNBE: FPCMov<X86_COND_A>;
358 defm CMOVNE : FPCMov<X86_COND_NE>;
359 defm CMOVNP : FPCMov<X86_COND_NP>;
362 // These are not factored because there's no clean way to pass DA/DB.
363 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
364 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
365 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
366 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
367 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
368 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
369 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
370 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
371 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
372 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
373 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
374 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
375 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
376 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
377 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
378 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
380 // Floating point loads & stores.
381 let canFoldAsLoad = 1 in {
382 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
383 [(set RFP32:$dst, (loadf32 addr:$src))]>;
384 let isReMaterializable = 1, mayHaveSideEffects = 1 in
385 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
386 [(set RFP64:$dst, (loadf64 addr:$src))]>;
387 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
388 [(set RFP80:$dst, (loadf80 addr:$src))]>;
390 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
391 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
392 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
393 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
394 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
395 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
396 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
397 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
398 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
399 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
400 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
401 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
402 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
403 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
404 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
405 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
406 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
407 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
408 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
409 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
410 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
411 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
412 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
413 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
415 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
416 [(store RFP32:$src, addr:$op)]>;
417 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
418 [(truncstoref32 RFP64:$src, addr:$op)]>;
419 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
420 [(store RFP64:$src, addr:$op)]>;
421 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
422 [(truncstoref32 RFP80:$src, addr:$op)]>;
423 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
424 [(truncstoref64 RFP80:$src, addr:$op)]>;
425 // FST does not support 80-bit memory target; FSTP must be used.
427 let mayStore = 1, neverHasSideEffects = 1 in {
428 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
429 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
430 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
431 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
432 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
434 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
435 [(store RFP80:$src, addr:$op)]>;
436 let mayStore = 1, neverHasSideEffects = 1 in {
437 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
438 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
439 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
440 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
441 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
442 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
443 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
444 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
445 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
449 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
450 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
451 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
452 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
453 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
454 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
456 let mayStore = 1 in {
457 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
458 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
459 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
460 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
461 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
462 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
463 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
464 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
465 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
466 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
469 // FISTTP requires SSE3 even though it's a FPStack op.
470 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
471 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
473 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
474 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
476 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
477 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
479 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
480 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
482 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
483 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
485 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
486 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
488 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
489 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
491 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
492 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
494 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
495 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
498 let mayStore = 1 in {
499 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
500 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
501 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
504 // FP Stack manipulation instructions.
505 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
506 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
507 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
508 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
510 // Floating point constant loads.
511 let isReMaterializable = 1 in {
512 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
513 [(set RFP32:$dst, fpimm0)]>;
514 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
515 [(set RFP32:$dst, fpimm1)]>;
516 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
517 [(set RFP64:$dst, fpimm0)]>;
518 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
519 [(set RFP64:$dst, fpimm1)]>;
520 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
521 [(set RFP80:$dst, fpimm0)]>;
522 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
523 [(set RFP80:$dst, fpimm1)]>;
526 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
527 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
530 // Floating point compares.
531 let Defs = [EFLAGS] in {
532 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
533 []>; // FPSW = cmp ST(0) with ST(i)
534 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
535 []>; // FPSW = cmp ST(0) with ST(i)
536 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
537 []>; // FPSW = cmp ST(0) with ST(i)
539 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
540 [(X86cmp RFP32:$lhs, RFP32:$rhs),
541 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
542 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
543 [(X86cmp RFP64:$lhs, RFP64:$rhs),
544 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
545 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
546 [(X86cmp RFP80:$lhs, RFP80:$rhs),
547 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
550 let Defs = [EFLAGS], Uses = [ST0] in {
551 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
552 (outs), (ins RST:$reg),
554 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
555 (outs), (ins RST:$reg),
557 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
561 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
562 (outs), (ins RST:$reg),
563 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
564 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
565 (outs), (ins RST:$reg),
566 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
569 // Floating point flag ops.
571 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
572 (outs), (ins), "fnstsw", []>, DF;
574 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
575 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
576 [(X86fp_cwd_get16 addr:$dst)]>;
579 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
580 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
582 //===----------------------------------------------------------------------===//
583 // Non-Instruction Patterns
584 //===----------------------------------------------------------------------===//
586 // Required for RET of f32 / f64 / f80 values.
587 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
588 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
589 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
591 // Required for CALL which return f32 / f64 / f80 values.
592 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
593 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
594 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
595 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
596 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
597 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
599 // Floating point constant -0.0 and -1.0
600 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
601 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
602 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
603 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
604 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
605 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
607 // Used to conv. i64 to f64 since there isn't a SSE version.
608 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
610 // FP extensions map onto simple pseudo-value conversions if they are to/from
612 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>,
613 Requires<[FPStackf32]>;
614 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>,
615 Requires<[FPStackf32]>;
616 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>,
617 Requires<[FPStackf64]>;
619 // FP truncations map onto simple pseudo-value conversions if they are to/from
620 // the FP stack. We have validated that only value-preserving truncations make
622 def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>,
623 Requires<[FPStackf32]>;
624 def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>,
625 Requires<[FPStackf32]>;
626 def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>,
627 Requires<[FPStackf64]>;