lib/Target/X86/X86InstrFMA.td

   1 //====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes FMA (Fused Multiply-Add) instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
  16 //===----------------------------------------------------------------------===//
  17
  18 multiclass fma_rm<bits<8> opc, string OpcodeStr> {
  19   def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
  20            (ins VR128:$src1, VR128:$src2),
  21            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  22            []>;
  23   def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
  24            (ins VR128:$src1, f128mem:$src2),
  25            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  26            []>;
  27   def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
  28            (ins VR256:$src1, VR256:$src2),
  29            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  30            []>;
  31   def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
  32            (ins VR256:$src1, f256mem:$src2),
  33            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  34            []>;
  35 }
  36
  37 multiclass fma_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
  38                      string OpcodeStr, string PackTy> {
  39   defm r132 : fma_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
  40   defm r213 : fma_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
  41   defm r231 : fma_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
  42 }
  43
  44 let isAsmParserOnly = 1 in {
  45   // Fused Multiply-Add
  46   defm VFMADDPS    : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
  47   defm VFMADDPD    : fma_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
  48   defm VFMADDSUBPS : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
  49   defm VFMADDSUBPD : fma_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
  50   defm VFMSUBADDPS : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
  51   defm VFMSUBADDPD : fma_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
  52   defm VFMSUBPS    : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
  53   defm VFMSUBPD    : fma_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
  54
  55   // Fused Negative Multiply-Add
  56   defm VFNMADDPS : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
  57   defm VFNMADDPD : fma_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
  58   defm VFNMSUBPS : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
  59   defm VFNMSUBPD : fma_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
  60 }
  61
  62 //===----------------------------------------------------------------------===//
  63 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
  64 //===----------------------------------------------------------------------===//
  65
  66
  67 multiclass fma4s<bits<8> opc, string OpcodeStr> {
  68   def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
  69            (ins VR128:$src1, VR128:$src2, VR128:$src3),
  70            !strconcat(OpcodeStr,
  71            "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
  72            []>, XOP_W;
  73   def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
  74            (ins VR128:$src1, VR128:$src2, f128mem:$src3),
  75            !strconcat(OpcodeStr,
  76            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
  77            []>, XOP_W;
  78   def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
  79            (ins VR128:$src1, f128mem:$src2, VR128:$src3),
  80            !strconcat(OpcodeStr,
  81            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
  82            []>;
  83
  84 }
  85
  86 multiclass fma4p<bits<8> opc, string OpcodeStr> {
  87   def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
  88            (ins VR128:$src1, VR128:$src2, VR128:$src3),
  89            !strconcat(OpcodeStr,
  90            "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
  91            []>, XOP_W;
  92   def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
  93            (ins VR128:$src1, VR128:$src2, f128mem:$src3),
  94            !strconcat(OpcodeStr,
  95            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
  96            []>, XOP_W;
  97   def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
  98            (ins VR128:$src1, f128mem:$src2, VR128:$src3),
  99            !strconcat(OpcodeStr,
 100            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 101            []>;
 102   def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
 103            (ins VR256:$src1, VR256:$src2, VR256:$src3),
 104            !strconcat(OpcodeStr,
 105            "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
 106            []>, XOP_W;
 107   def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
 108            (ins VR256:$src1, VR256:$src2, f256mem:$src3),
 109            !strconcat(OpcodeStr,
 110            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 111            []>, XOP_W;
 112   def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
 113            (ins VR256:$src1, f256mem:$src2, VR256:$src3),
 114            !strconcat(OpcodeStr,
 115            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 116            []>;
 117 }
 118
 119 let isAsmParserOnly = 1 in {
 120   defm VFMADDSS4    : fma4s<0x6A, "vfmaddss">;
 121   defm VFMADDSD4    : fma4s<0x6B, "vfmaddsd">;
 122   defm VFMADDPS4    : fma4p<0x68, "vfmaddps">;
 123   defm VFMADDPD4    : fma4p<0x69, "vfmaddpd">;
 124   defm VFMSUBSS4    : fma4s<0x6E, "vfmsubss">;
 125   defm VFMSUBSD4    : fma4s<0x6F, "vfmsubsd">;
 126   defm VFMSUBPS4    : fma4p<0x6C, "vfmsubps">;
 127   defm VFMSUBPD4    : fma4p<0x6D, "vfmsubpd">;
 128   defm VFNMADDSS4   : fma4s<0x7A, "vfnmaddss">;
 129   defm VFNMADDSD4   : fma4s<0x7B, "vfnmaddsd">;
 130   defm VFNMADDPS4   : fma4p<0x78, "vfnmaddps">;
 131   defm VFNMADDPD4   : fma4p<0x79, "vfnmaddpd">;
 132   defm VFNMSUBSS4   : fma4s<0x7E, "vfnmsubss">;
 133   defm VFNMSUBSD4   : fma4s<0x7F, "vfnmsubsd">;
 134   defm VFNMSUBPS4   : fma4p<0x7C, "vfnmsubps">;
 135   defm VFNMSUBPD4   : fma4p<0x7D, "vfnmsubpd">;
 136   defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps">;
 137   defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd">;
 138   defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps">;
 139   defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd">;
 140 }
 141
 142 // FMA4 Intrinsics patterns
 143
 144 // VFMADD
 145 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
 146           (VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 147 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2,
 148                                   (alignedloadv4f32 addr:$src3)),
 149           (VFMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 150 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 151                                   VR128:$src3),
 152           (VFMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 153
 154 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
 155           (VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 156 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2,
 157                                   (alignedloadv2f64 addr:$src3)),
 158           (VFMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 159 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 160                                   VR128:$src3),
 161           (VFMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 162
 163 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 164           (VFMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 165 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2,
 166                                   (alignedloadv4f32 addr:$src3)),
 167           (VFMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 168 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 169                                   VR128:$src3),
 170           (VFMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 171
 172 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 173           (VFMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 174 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2,
 175                                   (alignedloadv2f64 addr:$src3)),
 176           (VFMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 177 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 178                                   VR128:$src3),
 179           (VFMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 180
 181 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 182           (VFMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 183 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2,
 184                                   (alignedloadv8f32 addr:$src3)),
 185           (VFMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 186 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1,
 187                                       (alignedloadv8f32 addr:$src2),
 188                                       VR256:$src3),
 189           (VFMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 190
 191 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 192           (VFMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 193 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2,
 194                                   (alignedloadv4f64 addr:$src3)),
 195           (VFMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 196 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1,
 197                                       (alignedloadv4f64 addr:$src2),
 198                                       VR256:$src3),
 199           (VFMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 200
 201 // VFMSUB
 202 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
 203           (VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 204 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2,
 205                                   (alignedloadv4f32 addr:$src3)),
 206           (VFMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 207 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 208                                   VR128:$src3),
 209           (VFMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 210
 211 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
 212           (VFMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 213 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2,
 214                                   (alignedloadv2f64 addr:$src3)),
 215           (VFMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 216 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 217                                   VR128:$src3),
 218           (VFMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 219
 220 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 221           (VFMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 222 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2,
 223                                   (alignedloadv4f32 addr:$src3)),
 224           (VFMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 225 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 226                                   VR128:$src3),
 227           (VFMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 228
 229 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 230           (VFMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 231 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2,
 232                                   (alignedloadv2f64 addr:$src3)),
 233           (VFMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 234 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 235                                   VR128:$src3),
 236           (VFMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 237
 238 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 239           (VFMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 240 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2,
 241                                   (alignedloadv8f32 addr:$src3)),
 242           (VFMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 243 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1,
 244                                       (alignedloadv8f32 addr:$src2),
 245                                       VR256:$src3),
 246           (VFMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 247
 248 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 249           (VFMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 250 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2,
 251                                   (alignedloadv4f64 addr:$src3)),
 252           (VFMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 253 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1,
 254                                       (alignedloadv4f64 addr:$src2),
 255                                       VR256:$src3),
 256           (VFMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 257
 258 // VFNMADD
 259 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
 260           (VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 261 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2,
 262                                   (alignedloadv4f32 addr:$src3)),
 263           (VFNMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 264 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 265                                   VR128:$src3),
 266           (VFNMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 267
 268 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
 269           (VFNMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 270 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2,
 271                                   (alignedloadv2f64 addr:$src3)),
 272           (VFNMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 273 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 274                                   VR128:$src3),
 275           (VFNMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 276
 277 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 278           (VFNMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 279 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2,
 280                                   (alignedloadv4f32 addr:$src3)),
 281           (VFNMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 282 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 283                                   VR128:$src3),
 284           (VFNMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 285
 286 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 287           (VFNMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 288 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2,
 289                                   (alignedloadv2f64 addr:$src3)),
 290           (VFNMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 291 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 292                                   VR128:$src3),
 293           (VFNMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 294
 295 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 296           (VFNMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 297 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2,
 298                                   (alignedloadv8f32 addr:$src3)),
 299           (VFNMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 300 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1,
 301                                       (alignedloadv8f32 addr:$src2),
 302                                       VR256:$src3),
 303           (VFNMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 304
 305 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 306           (VFNMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 307 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2,
 308                                   (alignedloadv4f64 addr:$src3)),
 309           (VFNMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 310 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1,
 311                                       (alignedloadv4f64 addr:$src2),
 312                                       VR256:$src3),
 313           (VFNMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 314
 315 // VFNMSUB
 316 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
 317           (VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 318 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2,
 319                                   (alignedloadv4f32 addr:$src3)),
 320           (VFNMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 321 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 322                                   VR128:$src3),
 323           (VFNMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 324
 325 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
 326           (VFNMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 327 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2,
 328                                   (alignedloadv2f64 addr:$src3)),
 329           (VFNMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 330 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 331                                   VR128:$src3),
 332           (VFNMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 333
 334 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 335           (VFNMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 336 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2,
 337                                   (alignedloadv4f32 addr:$src3)),
 338           (VFNMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 339 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 340                                   VR128:$src3),
 341           (VFNMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 342
 343 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 344           (VFNMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 345 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2,
 346                                   (alignedloadv2f64 addr:$src3)),
 347           (VFNMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 348 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 349                                   VR128:$src3),
 350           (VFNMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 351
 352 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 353           (VFNMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 354 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2,
 355                                   (alignedloadv8f32 addr:$src3)),
 356           (VFNMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 357 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1,
 358                                       (alignedloadv8f32 addr:$src2),
 359                                       VR256:$src3),
 360           (VFNMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 361
 362 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 363           (VFNMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 364 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2,
 365                                   (alignedloadv4f64 addr:$src3)),
 366           (VFNMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 367 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1,
 368                                       (alignedloadv4f64 addr:$src2),
 369                                       VR256:$src3),
 370           (VFNMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 371
 372 // VFMADDSUB
 373 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 374           (VFMADDSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 375 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2,
 376                                   (alignedloadv4f32 addr:$src3)),
 377           (VFMADDSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 378 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 379                                   VR128:$src3),
 380           (VFMADDSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 381
 382 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 383           (VFMADDSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 384 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2,
 385                                   (alignedloadv2f64 addr:$src3)),
 386           (VFMADDSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 387 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 388                                   VR128:$src3),
 389           (VFMADDSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 390
 391 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 392           (VFMADDSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 393 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2,
 394                                   (alignedloadv8f32 addr:$src3)),
 395           (VFMADDSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 396 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1,
 397                                       (alignedloadv8f32 addr:$src2),
 398                                       VR256:$src3),
 399           (VFMADDSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 400
 401 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 402           (VFMADDSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 403 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2,
 404                                   (alignedloadv4f64 addr:$src3)),
 405           (VFMADDSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 406 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1,
 407                                       (alignedloadv4f64 addr:$src2),
 408                                       VR256:$src3),
 409           (VFMADDSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 410
 411 // VFMSUBADD
 412 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 413           (VFMSUBADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 414 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2,
 415                                   (alignedloadv4f32 addr:$src3)),
 416           (VFMSUBADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 417 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 418                                   VR128:$src3),
 419           (VFMSUBADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 420
 421 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 422           (VFMSUBADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 423 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2,
 424                                   (alignedloadv2f64 addr:$src3)),
 425           (VFMSUBADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 426 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 427                                   VR128:$src3),
 428           (VFMSUBADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 429
 430 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 431           (VFMSUBADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 432 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2,
 433                                   (alignedloadv8f32 addr:$src3)),
 434           (VFMSUBADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 435 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1,
 436                                       (alignedloadv8f32 addr:$src2),
 437                                       VR256:$src3),
 438           (VFMSUBADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 439
 440 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 441           (VFMSUBADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 442 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2,
 443                                   (alignedloadv4f64 addr:$src3)),
 444           (VFMSUBADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 445 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1,
 446                                       (alignedloadv4f64 addr:$src2),
 447                                       VR256:$src3),
 448           (VFMSUBADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;