1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
156 isCodeGenOnly = 1, isReturn = 1 in {
157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
159 // CATCHRET needs a custom inserter for SEH.
160 let usesCustomInserter = 1 in
161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
163 [(catchret bb:$dst, bb:$from)]>;
166 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
167 usesCustomInserter = 1 in
168 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>;
170 // This instruction is responsible for re-establishing stack pointers after an
171 // exception has been caught and we are rejoining normal control flow in the
172 // parent function or funclet. It generally sets ESP and EBP, and optionally
173 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us
175 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in
176 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>;
178 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
179 usesCustomInserter = 1 in {
180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
183 Requires<[Not64BitMode]>;
184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
187 Requires<[In64BitMode]>;
188 let isTerminator = 1 in {
189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
190 "#EH_SJLJ_LONGJMP32",
191 [(X86eh_sjlj_longjmp addr:$buf)]>,
192 Requires<[Not64BitMode]>;
193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
194 "#EH_SJLJ_LONGJMP64",
195 [(X86eh_sjlj_longjmp addr:$buf)]>,
196 Requires<[In64BitMode]>;
201 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
203 "#EH_SjLj_Setup\t$dst", []>;
206 //===----------------------------------------------------------------------===//
207 // Pseudo instructions used by unwind info.
209 let isPseudo = 1 in {
210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
211 "#SEH_PushReg $reg", []>;
212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
213 "#SEH_SaveReg $reg, $dst", []>;
214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
215 "#SEH_SaveXMM $reg, $dst", []>;
216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
217 "#SEH_StackAlloc $size", []>;
218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
219 "#SEH_SetFrame $reg, $offset", []>;
220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
221 "#SEH_PushFrame $mode", []>;
222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
223 "#SEH_EndPrologue", []>;
224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
225 "#SEH_Epilogue", []>;
228 //===----------------------------------------------------------------------===//
229 // Pseudo instructions used by segmented stacks.
232 // This is lowered into a RET instruction by MCInstLower. We need
233 // this so that we don't have to have a MachineBasicBlock which ends
234 // with a RET and also has successors.
235 let isPseudo = 1 in {
236 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
239 // This instruction is lowered to a RET followed by a MOV. The two
240 // instructions are not generated on a higher level since then the
241 // verifier sees a MachineBasicBlock ending with a non-terminator.
242 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
246 //===----------------------------------------------------------------------===//
247 // Alias Instructions
248 //===----------------------------------------------------------------------===//
250 // Alias instruction mapping movr0 to xor.
251 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
252 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
254 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
257 // Other widths can also make use of the 32-bit xor, which may have a smaller
258 // encoding and avoid partial register updates.
259 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
260 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
262 let AddedComplexity = 20;
265 let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode],
266 AddedComplexity = 1 in {
267 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,
268 // which only require 3 bytes compared to MOV32ri which requires 5.
269 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
270 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
271 [(set GR32:$dst, 1)]>;
272 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
273 [(set GR32:$dst, -1)]>;
276 // MOV16ri is 4 bytes, so the instructions above are smaller.
277 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
278 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
281 // Materialize i64 constant where top 32-bits are zero. This could theoretically
282 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
283 // that would make it more difficult to rematerialize.
284 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
285 isCodeGenOnly = 1, hasSideEffects = 0 in
286 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
287 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
289 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
290 // actually the zero-extension of a 32-bit constant and for labels in the
291 // x86-64 small code model.
292 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
294 let AddedComplexity = 1 in
295 def : Pat<(i64 mov64imm32:$src),
296 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
298 // Use sbb to materialize carry bit.
299 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
300 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
301 // However, Pat<> can't replicate the destination reg into the inputs of the
303 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
304 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
305 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
306 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
307 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
308 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
309 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
310 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
314 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
316 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
318 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
321 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
323 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
325 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
328 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
329 // will be eliminated and that the sbb can be extended up to a wider type. When
330 // this happens, it is great. However, if we are left with an 8-bit sbb and an
331 // and, we might as well just match it as a setb.
332 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
335 // (add OP, SETB) -> (adc OP, 0)
336 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
337 (ADC8ri GR8:$op, 0)>;
338 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
339 (ADC32ri8 GR32:$op, 0)>;
340 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
341 (ADC64ri8 GR64:$op, 0)>;
343 // (sub OP, SETB) -> (sbb OP, 0)
344 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
345 (SBB8ri GR8:$op, 0)>;
346 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
347 (SBB32ri8 GR32:$op, 0)>;
348 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
349 (SBB64ri8 GR64:$op, 0)>;
351 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
352 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
353 (ADC8ri GR8:$op, 0)>;
354 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
355 (ADC32ri8 GR32:$op, 0)>;
356 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
357 (ADC64ri8 GR64:$op, 0)>;
359 //===----------------------------------------------------------------------===//
360 // String Pseudo Instructions
362 let SchedRW = [WriteMicrocoded] in {
363 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
364 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
365 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
366 Requires<[Not64BitMode]>;
367 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
368 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
369 Requires<[Not64BitMode]>;
370 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
371 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
372 Requires<[Not64BitMode]>;
375 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
376 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
377 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
378 Requires<[In64BitMode]>;
379 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
380 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
381 Requires<[In64BitMode]>;
382 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
383 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
384 Requires<[In64BitMode]>;
385 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
386 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
387 Requires<[In64BitMode]>;
390 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
391 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
392 let Uses = [AL,ECX,EDI] in
393 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
394 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
395 Requires<[Not64BitMode]>;
396 let Uses = [AX,ECX,EDI] in
397 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
398 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
399 Requires<[Not64BitMode]>;
400 let Uses = [EAX,ECX,EDI] in
401 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
402 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
403 Requires<[Not64BitMode]>;
406 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
407 let Uses = [AL,RCX,RDI] in
408 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
409 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
410 Requires<[In64BitMode]>;
411 let Uses = [AX,RCX,RDI] in
412 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
413 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
414 Requires<[In64BitMode]>;
415 let Uses = [RAX,RCX,RDI] in
416 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
417 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
418 Requires<[In64BitMode]>;
420 let Uses = [RAX,RCX,RDI] in
421 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
422 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
423 Requires<[In64BitMode]>;
427 //===----------------------------------------------------------------------===//
428 // Thread Local Storage Instructions
432 // All calls clobber the non-callee saved registers. ESP is marked as
433 // a use to prevent stack-pointer assignments that appear immediately
434 // before calls from potentially appearing dead.
435 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
436 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
437 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
438 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
439 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
441 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
443 [(X86tlsaddr tls32addr:$sym)]>,
444 Requires<[Not64BitMode]>;
445 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
447 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
448 Requires<[Not64BitMode]>;
451 // All calls clobber the non-callee saved registers. RSP is marked as
452 // a use to prevent stack-pointer assignments that appear immediately
453 // before calls from potentially appearing dead.
454 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
455 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
456 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
457 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
458 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
459 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
461 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
463 [(X86tlsaddr tls64addr:$sym)]>,
464 Requires<[In64BitMode]>;
465 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
467 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
468 Requires<[In64BitMode]>;
471 // Darwin TLS Support
472 // For i386, the address of the thunk is passed on the stack, on return the
473 // address of the variable is in %eax. %ecx is trashed during the function
474 // call. All other registers are preserved.
475 let Defs = [EAX, ECX, EFLAGS],
477 usesCustomInserter = 1 in
478 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
480 [(X86TLSCall addr:$sym)]>,
481 Requires<[Not64BitMode]>;
483 // For x86_64, the address of the thunk is passed in %rdi, on return
484 // the address of the variable is in %rax. All other registers are preserved.
485 let Defs = [RAX, EFLAGS],
487 usesCustomInserter = 1 in
488 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
490 [(X86TLSCall addr:$sym)]>,
491 Requires<[In64BitMode]>;
494 //===----------------------------------------------------------------------===//
495 // Conditional Move Pseudo Instructions
497 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
498 // instruction selection into a branch sequence.
499 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
500 def CMOV#NAME : I<0, Pseudo,
501 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
502 "#CMOV_"#NAME#" PSEUDO!",
503 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
507 let usesCustomInserter = 1, Uses = [EFLAGS] in {
508 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
509 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
510 // however that requires promoting the operands, and can induce additional
511 // i8 register pressure.
512 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
514 let Predicates = [NoCMov] in {
515 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
516 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
517 } // Predicates = [NoCMov]
519 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
521 let Predicates = [FPStackf32] in
522 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
524 let Predicates = [FPStackf64] in
525 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
527 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
529 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
530 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
531 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>;
532 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
533 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
534 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
535 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
536 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
537 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
538 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
539 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
540 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
541 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
542 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
543 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
544 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
545 } // usesCustomInserter = 1, Uses = [EFLAGS]
547 //===----------------------------------------------------------------------===//
548 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
549 //===----------------------------------------------------------------------===//
551 // FIXME: Use normal instructions and add lock prefix dynamically.
555 // TODO: Get this to fold the constant into the instruction.
556 let isCodeGenOnly = 1, Defs = [EFLAGS] in
557 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
558 "or{l}\t{$zero, $dst|$dst, $zero}", [],
559 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK,
560 Sched<[WriteALULd, WriteRMW]>;
562 let hasSideEffects = 1 in
563 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
565 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
567 // RegOpc corresponds to the mr version of the instruction
568 // ImmOpc corresponds to the mi version of the instruction
569 // ImmOpc8 corresponds to the mi8 version of the instruction
570 // ImmMod corresponds to the instruction format of the mi and mi8 versions
571 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
572 Format ImmMod, string mnemonic> {
573 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
574 SchedRW = [WriteALULd, WriteRMW] in {
576 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
577 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
578 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
579 !strconcat(mnemonic, "{b}\t",
580 "{$src2, $dst|$dst, $src2}"),
581 [], IIC_ALU_NONMEM>, LOCK;
582 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
583 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
584 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
585 !strconcat(mnemonic, "{w}\t",
586 "{$src2, $dst|$dst, $src2}"),
587 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
588 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
589 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
590 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
591 !strconcat(mnemonic, "{l}\t",
592 "{$src2, $dst|$dst, $src2}"),
593 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
594 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
595 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
596 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
597 !strconcat(mnemonic, "{q}\t",
598 "{$src2, $dst|$dst, $src2}"),
599 [], IIC_ALU_NONMEM>, LOCK;
601 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
602 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
603 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
604 !strconcat(mnemonic, "{b}\t",
605 "{$src2, $dst|$dst, $src2}"),
606 [], IIC_ALU_MEM>, LOCK;
608 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
609 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
610 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
611 !strconcat(mnemonic, "{w}\t",
612 "{$src2, $dst|$dst, $src2}"),
613 [], IIC_ALU_MEM>, OpSize16, LOCK;
615 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
616 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
617 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
618 !strconcat(mnemonic, "{l}\t",
619 "{$src2, $dst|$dst, $src2}"),
620 [], IIC_ALU_MEM>, OpSize32, LOCK;
622 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
623 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
624 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
625 !strconcat(mnemonic, "{q}\t",
626 "{$src2, $dst|$dst, $src2}"),
627 [], IIC_ALU_MEM>, LOCK;
629 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
630 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
631 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
632 !strconcat(mnemonic, "{w}\t",
633 "{$src2, $dst|$dst, $src2}"),
634 [], IIC_ALU_MEM>, OpSize16, LOCK;
635 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
636 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
637 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
638 !strconcat(mnemonic, "{l}\t",
639 "{$src2, $dst|$dst, $src2}"),
640 [], IIC_ALU_MEM>, OpSize32, LOCK;
641 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
642 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
643 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
644 !strconcat(mnemonic, "{q}\t",
645 "{$src2, $dst|$dst, $src2}"),
646 [], IIC_ALU_MEM>, LOCK;
652 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
653 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
654 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
655 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
656 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
658 // Optimized codegen when the non-memory output is not used.
659 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
661 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
662 SchedRW = [WriteALULd, WriteRMW] in {
664 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
665 !strconcat(mnemonic, "{b}\t$dst"),
666 [], IIC_UNARY_MEM>, LOCK;
667 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
668 !strconcat(mnemonic, "{w}\t$dst"),
669 [], IIC_UNARY_MEM>, OpSize16, LOCK;
670 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
671 !strconcat(mnemonic, "{l}\t$dst"),
672 [], IIC_UNARY_MEM>, OpSize32, LOCK;
673 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
674 !strconcat(mnemonic, "{q}\t$dst"),
675 [], IIC_UNARY_MEM>, LOCK;
679 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
680 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
682 // Atomic compare and swap.
683 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
684 SDPatternOperator frag, X86MemOperand x86memop,
685 InstrItinClass itin> {
686 let isCodeGenOnly = 1 in {
687 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
688 !strconcat(mnemonic, "\t$ptr"),
689 [(frag addr:$ptr)], itin>, TB, LOCK;
693 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
694 string mnemonic, SDPatternOperator frag,
695 InstrItinClass itin8, InstrItinClass itin> {
696 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
697 let Defs = [AL, EFLAGS], Uses = [AL] in
698 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
699 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
700 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
701 let Defs = [AX, EFLAGS], Uses = [AX] in
702 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
703 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
704 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
705 let Defs = [EAX, EFLAGS], Uses = [EAX] in
706 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
707 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
708 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
709 let Defs = [RAX, EFLAGS], Uses = [RAX] in
710 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
711 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
712 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
716 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
717 SchedRW = [WriteALULd, WriteRMW] in {
718 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
723 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
724 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
725 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
727 IIC_CMPX_LOCK_16B>, REX_W;
730 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
731 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
733 // Atomic exchange and add
734 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
736 InstrItinClass itin8, InstrItinClass itin> {
737 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
738 SchedRW = [WriteALULd, WriteRMW] in {
739 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
740 (ins GR8:$val, i8mem:$ptr),
741 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
743 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
745 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
746 (ins GR16:$val, i16mem:$ptr),
747 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
750 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
752 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
753 (ins GR32:$val, i32mem:$ptr),
754 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
757 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
759 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
760 (ins GR64:$val, i64mem:$ptr),
761 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
764 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
769 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
770 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
773 /* The following multiclass tries to make sure that in code like
774 * x.store (immediate op x.load(acquire), release)
776 * x.store (register op x.load(acquire), release)
777 * an operation directly on memory is generated instead of wasting a register.
778 * It is not automatic as atomic_store/load are only lowered to MOV instructions
779 * extremely late to prevent them from being accidentally reordered in the backend
780 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
782 multiclass RELEASE_BINOP_MI<SDNode op> {
783 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
784 "#BINOP "#NAME#"8mi PSEUDO!",
785 [(atomic_store_8 addr:$dst, (op
786 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
787 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
788 "#BINOP "#NAME#"8mr PSEUDO!",
789 [(atomic_store_8 addr:$dst, (op
790 (atomic_load_8 addr:$dst), GR8:$src))]>;
791 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
792 // costly and avoided as far as possible by this backend anyway
793 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
794 "#BINOP "#NAME#"32mi PSEUDO!",
795 [(atomic_store_32 addr:$dst, (op
796 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
797 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
798 "#BINOP "#NAME#"32mr PSEUDO!",
799 [(atomic_store_32 addr:$dst, (op
800 (atomic_load_32 addr:$dst), GR32:$src))]>;
801 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
802 "#BINOP "#NAME#"64mi32 PSEUDO!",
803 [(atomic_store_64 addr:$dst, (op
804 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
805 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
806 "#BINOP "#NAME#"64mr PSEUDO!",
807 [(atomic_store_64 addr:$dst, (op
808 (atomic_load_64 addr:$dst), GR64:$src))]>;
810 let Defs = [EFLAGS] in {
811 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
812 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
813 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
814 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
815 // Note: we don't deal with sub, because substractions of constants are
816 // optimized into additions before this code can run.
819 // Same as above, but for floating-point.
820 // FIXME: imm version.
821 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
822 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
823 let usesCustomInserter = 1 in {
824 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
825 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
826 "#BINOP "#NAME#"32mr PSEUDO!",
827 [(atomic_store_32 addr:$dst,
829 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
830 FR32:$src))))]>, Requires<[HasSSE1]>;
831 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
832 "#BINOP "#NAME#"64mr PSEUDO!",
833 [(atomic_store_64 addr:$dst,
835 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
836 FR64:$src))))]>, Requires<[HasSSE2]>;
838 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
839 // FIXME: Add fsub, fmul, fdiv, ...
842 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
843 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
844 "#UNOP "#NAME#"8m PSEUDO!",
845 [(atomic_store_8 addr:$dst, dag8)]>;
846 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
847 "#UNOP "#NAME#"16m PSEUDO!",
848 [(atomic_store_16 addr:$dst, dag16)]>;
849 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
850 "#UNOP "#NAME#"32m PSEUDO!",
851 [(atomic_store_32 addr:$dst, dag32)]>;
852 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
853 "#UNOP "#NAME#"64m PSEUDO!",
854 [(atomic_store_64 addr:$dst, dag64)]>;
857 let Defs = [EFLAGS] in {
858 defm RELEASE_INC : RELEASE_UNOP<
859 (add (atomic_load_8 addr:$dst), (i8 1)),
860 (add (atomic_load_16 addr:$dst), (i16 1)),
861 (add (atomic_load_32 addr:$dst), (i32 1)),
862 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
863 defm RELEASE_DEC : RELEASE_UNOP<
864 (add (atomic_load_8 addr:$dst), (i8 -1)),
865 (add (atomic_load_16 addr:$dst), (i16 -1)),
866 (add (atomic_load_32 addr:$dst), (i32 -1)),
867 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
870 TODO: These don't work because the type inference of TableGen fails.
871 TODO: find a way to fix it.
872 let Defs = [EFLAGS] in {
873 defm RELEASE_NEG : RELEASE_UNOP<
874 (ineg (atomic_load_8 addr:$dst)),
875 (ineg (atomic_load_16 addr:$dst)),
876 (ineg (atomic_load_32 addr:$dst)),
877 (ineg (atomic_load_64 addr:$dst))>;
879 // NOT doesn't set flags.
880 defm RELEASE_NOT : RELEASE_UNOP<
881 (not (atomic_load_8 addr:$dst)),
882 (not (atomic_load_16 addr:$dst)),
883 (not (atomic_load_32 addr:$dst)),
884 (not (atomic_load_64 addr:$dst))>;
887 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
888 "#RELEASE_MOV8mi PSEUDO!",
889 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
890 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
891 "#RELEASE_MOV16mi PSEUDO!",
892 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
893 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
894 "#RELEASE_MOV32mi PSEUDO!",
895 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
896 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
897 "#RELEASE_MOV64mi32 PSEUDO!",
898 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
900 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
901 "#RELEASE_MOV8mr PSEUDO!",
902 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
903 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
904 "#RELEASE_MOV16mr PSEUDO!",
905 [(atomic_store_16 addr:$dst, GR16:$src)]>;
906 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
907 "#RELEASE_MOV32mr PSEUDO!",
908 [(atomic_store_32 addr:$dst, GR32:$src)]>;
909 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
910 "#RELEASE_MOV64mr PSEUDO!",
911 [(atomic_store_64 addr:$dst, GR64:$src)]>;
913 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
914 "#ACQUIRE_MOV8rm PSEUDO!",
915 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
916 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
917 "#ACQUIRE_MOV16rm PSEUDO!",
918 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
919 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
920 "#ACQUIRE_MOV32rm PSEUDO!",
921 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
922 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
923 "#ACQUIRE_MOV64rm PSEUDO!",
924 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
926 //===----------------------------------------------------------------------===//
927 // DAG Pattern Matching Rules
928 //===----------------------------------------------------------------------===//
930 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
931 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
932 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
933 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
934 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
935 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
936 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
937 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
939 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
940 (ADD32ri GR32:$src1, tconstpool:$src2)>;
941 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
942 (ADD32ri GR32:$src1, tjumptable:$src2)>;
943 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
944 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
945 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
946 (ADD32ri GR32:$src1, texternalsym:$src2)>;
947 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
948 (ADD32ri GR32:$src1, mcsym:$src2)>;
949 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
950 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
952 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
953 (MOV32mi addr:$dst, tglobaladdr:$src)>;
954 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
955 (MOV32mi addr:$dst, texternalsym:$src)>;
956 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
957 (MOV32mi addr:$dst, mcsym:$src)>;
958 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
959 (MOV32mi addr:$dst, tblockaddress:$src)>;
961 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
962 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
963 // 'movabs' predicate should handle this sort of thing.
964 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
965 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
966 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
967 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
968 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
969 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
970 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
971 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
972 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
973 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
974 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
975 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
977 // In kernel code model, we can get the address of a label
978 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
979 // the MOV64ri32 should accept these.
980 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
981 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
982 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
983 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
984 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
985 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
986 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
987 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
988 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
989 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
990 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
991 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
993 // If we have small model and -static mode, it is safe to store global addresses
994 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
995 // for MOV64mi32 should handle this sort of thing.
996 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
997 (MOV64mi32 addr:$dst, tconstpool:$src)>,
998 Requires<[NearData, IsStatic]>;
999 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1000 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1001 Requires<[NearData, IsStatic]>;
1002 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1003 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1004 Requires<[NearData, IsStatic]>;
1005 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1006 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1007 Requires<[NearData, IsStatic]>;
1008 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
1009 (MOV64mi32 addr:$dst, mcsym:$src)>,
1010 Requires<[NearData, IsStatic]>;
1011 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1012 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1013 Requires<[NearData, IsStatic]>;
1015 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
1016 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1020 // tls has some funny stuff here...
1021 // This corresponds to movabs $foo@tpoff, %rax
1022 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1023 (MOV64ri32 tglobaltlsaddr :$dst)>;
1024 // This corresponds to add $foo@tpoff, %rax
1025 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1026 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1029 // Direct PC relative function call for small code model. 32-bit displacement
1030 // sign extended to 64-bit.
1031 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1032 (CALL64pcrel32 tglobaladdr:$dst)>;
1033 def : Pat<(X86call (i64 texternalsym:$dst)),
1034 (CALL64pcrel32 texternalsym:$dst)>;
1036 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1037 // can never use callee-saved registers. That is the purpose of the GR64_TC
1038 // register classes.
1040 // The only volatile register that is never used by the calling convention is
1041 // %r11. This happens when calling a vararg function with 6 arguments.
1043 // Match an X86tcret that uses less than 7 volatile registers.
1044 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1045 (X86tcret node:$ptr, node:$off), [{
1046 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1047 unsigned NumRegs = 0;
1048 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1049 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1054 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1055 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1056 Requires<[Not64BitMode]>;
1058 // FIXME: This is disabled for 32-bit PIC mode because the global base
1059 // register which is part of the address mode may be assigned a
1060 // callee-saved register.
1061 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1062 (TCRETURNmi addr:$dst, imm:$off)>,
1063 Requires<[Not64BitMode, IsNotPIC]>;
1065 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1066 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1067 Requires<[NotLP64]>;
1069 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1070 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1071 Requires<[NotLP64]>;
1073 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1074 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1075 Requires<[In64BitMode]>;
1077 // Don't fold loads into X86tcret requiring more than 6 regs.
1078 // There wouldn't be enough scratch registers for base+index.
1079 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1080 (TCRETURNmi64 addr:$dst, imm:$off)>,
1081 Requires<[In64BitMode]>;
1083 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1084 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1087 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1088 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1091 // Normal calls, with various flavors of addresses.
1092 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1093 (CALLpcrel32 tglobaladdr:$dst)>;
1094 def : Pat<(X86call (i32 texternalsym:$dst)),
1095 (CALLpcrel32 texternalsym:$dst)>;
1096 def : Pat<(X86call (i32 imm:$dst)),
1097 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1101 // TEST R,R is smaller than CMP R,0
1102 def : Pat<(X86cmp GR8:$src1, 0),
1103 (TEST8rr GR8:$src1, GR8:$src1)>;
1104 def : Pat<(X86cmp GR16:$src1, 0),
1105 (TEST16rr GR16:$src1, GR16:$src1)>;
1106 def : Pat<(X86cmp GR32:$src1, 0),
1107 (TEST32rr GR32:$src1, GR32:$src1)>;
1108 def : Pat<(X86cmp GR64:$src1, 0),
1109 (TEST64rr GR64:$src1, GR64:$src1)>;
1111 // Conditional moves with folded loads with operands swapped and conditions
1113 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1114 Instruction Inst64> {
1115 let Predicates = [HasCMov] in {
1116 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1117 (Inst16 GR16:$src2, addr:$src1)>;
1118 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1119 (Inst32 GR32:$src2, addr:$src1)>;
1120 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1121 (Inst64 GR64:$src2, addr:$src1)>;
1125 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1126 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1127 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1128 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1129 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1130 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1131 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1132 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1133 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1134 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1135 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1136 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1137 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1138 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1139 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1140 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1142 // zextload bool -> zextload byte
1143 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1144 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1145 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1146 def : Pat<(zextloadi64i1 addr:$src),
1147 (SUBREG_TO_REG (i64 0),
1148 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1150 // extload bool -> extload byte
1151 // When extloading from 16-bit and smaller memory locations into 64-bit
1152 // registers, use zero-extending loads so that the entire 64-bit register is
1153 // defined, avoiding partial-register updates.
1155 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1156 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1157 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1158 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1159 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1160 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1162 // For other extloads, use subregs, since the high contents of the register are
1163 // defined after an extload.
1164 def : Pat<(extloadi64i1 addr:$src),
1165 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1166 def : Pat<(extloadi64i8 addr:$src),
1167 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1168 def : Pat<(extloadi64i16 addr:$src),
1169 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1170 def : Pat<(extloadi64i32 addr:$src),
1171 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1173 // anyext. Define these to do an explicit zero-extend to
1174 // avoid partial-register updates.
1175 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1176 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1177 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1179 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1180 def : Pat<(i32 (anyext GR16:$src)),
1181 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1183 def : Pat<(i64 (anyext GR8 :$src)),
1184 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1185 def : Pat<(i64 (anyext GR16:$src)),
1186 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1187 def : Pat<(i64 (anyext GR32:$src)),
1188 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1191 // Any instruction that defines a 32-bit result leaves the high half of the
1192 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1193 // be copying from a truncate. And x86's cmov doesn't do anything if the
1194 // condition is false. But any other 32-bit operation will zero-extend
1196 def def32 : PatLeaf<(i32 GR32:$src), [{
1197 return N->getOpcode() != ISD::TRUNCATE &&
1198 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1199 N->getOpcode() != ISD::CopyFromReg &&
1200 N->getOpcode() != ISD::AssertSext &&
1201 N->getOpcode() != X86ISD::CMOV;
1204 // In the case of a 32-bit def that is known to implicitly zero-extend,
1205 // we can use a SUBREG_TO_REG.
1206 def : Pat<(i64 (zext def32:$src)),
1207 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1209 //===----------------------------------------------------------------------===//
1210 // Pattern match OR as ADD
1211 //===----------------------------------------------------------------------===//
1213 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1214 // 3-addressified into an LEA instruction to avoid copies. However, we also
1215 // want to finally emit these instructions as an or at the end of the code
1216 // generator to make the generated code easier to read. To do this, we select
1217 // into "disjoint bits" pseudo ops.
1219 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1220 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1221 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1222 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1224 APInt KnownZero0, KnownOne0;
1225 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1226 APInt KnownZero1, KnownOne1;
1227 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1228 return (~KnownZero0 & ~KnownZero1) == 0;
1232 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1233 // Try this before the selecting to OR.
1234 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1236 let isConvertibleToThreeAddress = 1,
1237 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1238 let isCommutable = 1 in {
1239 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1240 "", // orw/addw REG, REG
1241 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1242 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1243 "", // orl/addl REG, REG
1244 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1245 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1246 "", // orq/addq REG, REG
1247 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1250 // NOTE: These are order specific, we want the ri8 forms to be listed
1251 // first so that they are slightly preferred to the ri forms.
1253 def ADD16ri8_DB : I<0, Pseudo,
1254 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1255 "", // orw/addw REG, imm8
1256 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1257 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1258 "", // orw/addw REG, imm
1259 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1261 def ADD32ri8_DB : I<0, Pseudo,
1262 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1263 "", // orl/addl REG, imm8
1264 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1265 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1266 "", // orl/addl REG, imm
1267 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1270 def ADD64ri8_DB : I<0, Pseudo,
1271 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1272 "", // orq/addq REG, imm8
1273 [(set GR64:$dst, (or_is_add GR64:$src1,
1274 i64immSExt8:$src2))]>;
1275 def ADD64ri32_DB : I<0, Pseudo,
1276 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1277 "", // orq/addq REG, imm
1278 [(set GR64:$dst, (or_is_add GR64:$src1,
1279 i64immSExt32:$src2))]>;
1281 } // AddedComplexity, SchedRW
1284 //===----------------------------------------------------------------------===//
1286 //===----------------------------------------------------------------------===//
1288 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1289 // +128 doesn't, so in this special case use a sub instead of an add.
1290 def : Pat<(add GR16:$src1, 128),
1291 (SUB16ri8 GR16:$src1, -128)>;
1292 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1293 (SUB16mi8 addr:$dst, -128)>;
1295 def : Pat<(add GR32:$src1, 128),
1296 (SUB32ri8 GR32:$src1, -128)>;
1297 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1298 (SUB32mi8 addr:$dst, -128)>;
1300 def : Pat<(add GR64:$src1, 128),
1301 (SUB64ri8 GR64:$src1, -128)>;
1302 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1303 (SUB64mi8 addr:$dst, -128)>;
1305 // The same trick applies for 32-bit immediate fields in 64-bit
1307 def : Pat<(add GR64:$src1, 0x0000000080000000),
1308 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1309 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1310 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1312 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1313 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1314 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1315 // represented with a sign extension of a 8 bit constant, use that.
1316 // This can also reduce instruction size by eliminating the need for the REX
1319 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1320 let AddedComplexity = 1 in {
1321 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1325 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1326 (i32 (GetLo8XForm imm:$imm))),
1329 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1333 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1334 (i32 (GetLo32XForm imm:$imm))),
1336 } // AddedComplexity = 1
1339 // AddedComplexity is needed due to the increased complexity on the
1340 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1341 // the MOVZX patterns keeps thems together in DAGIsel tables.
1342 let AddedComplexity = 1 in {
1343 // r & (2^16-1) ==> movz
1344 def : Pat<(and GR32:$src1, 0xffff),
1345 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1346 // r & (2^8-1) ==> movz
1347 def : Pat<(and GR32:$src1, 0xff),
1348 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1351 Requires<[Not64BitMode]>;
1352 // r & (2^8-1) ==> movz
1353 def : Pat<(and GR16:$src1, 0xff),
1354 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1355 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1357 Requires<[Not64BitMode]>;
1359 // r & (2^32-1) ==> movz
1360 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1361 (SUBREG_TO_REG (i64 0),
1362 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1364 // r & (2^16-1) ==> movz
1365 def : Pat<(and GR64:$src, 0xffff),
1366 (SUBREG_TO_REG (i64 0),
1367 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1369 // r & (2^8-1) ==> movz
1370 def : Pat<(and GR64:$src, 0xff),
1371 (SUBREG_TO_REG (i64 0),
1372 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1374 // r & (2^8-1) ==> movz
1375 def : Pat<(and GR32:$src1, 0xff),
1376 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1377 Requires<[In64BitMode]>;
1378 // r & (2^8-1) ==> movz
1379 def : Pat<(and GR16:$src1, 0xff),
1380 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1381 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1382 Requires<[In64BitMode]>;
1383 } // AddedComplexity = 1
1386 // sext_inreg patterns
1387 def : Pat<(sext_inreg GR32:$src, i16),
1388 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1389 def : Pat<(sext_inreg GR32:$src, i8),
1390 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1393 Requires<[Not64BitMode]>;
1395 def : Pat<(sext_inreg GR16:$src, i8),
1396 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1397 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1399 Requires<[Not64BitMode]>;
1401 def : Pat<(sext_inreg GR64:$src, i32),
1402 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1403 def : Pat<(sext_inreg GR64:$src, i16),
1404 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1405 def : Pat<(sext_inreg GR64:$src, i8),
1406 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1407 def : Pat<(sext_inreg GR32:$src, i8),
1408 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1409 Requires<[In64BitMode]>;
1410 def : Pat<(sext_inreg GR16:$src, i8),
1411 (EXTRACT_SUBREG (MOVSX32rr8
1412 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1413 Requires<[In64BitMode]>;
1415 // sext, sext_load, zext, zext_load
1416 def: Pat<(i16 (sext GR8:$src)),
1417 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1418 def: Pat<(sextloadi16i8 addr:$src),
1419 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1420 def: Pat<(i16 (zext GR8:$src)),
1421 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1422 def: Pat<(zextloadi16i8 addr:$src),
1423 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1426 def : Pat<(i16 (trunc GR32:$src)),
1427 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1428 def : Pat<(i8 (trunc GR32:$src)),
1429 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1431 Requires<[Not64BitMode]>;
1432 def : Pat<(i8 (trunc GR16:$src)),
1433 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1435 Requires<[Not64BitMode]>;
1436 def : Pat<(i32 (trunc GR64:$src)),
1437 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1438 def : Pat<(i16 (trunc GR64:$src)),
1439 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1440 def : Pat<(i8 (trunc GR64:$src)),
1441 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1442 def : Pat<(i8 (trunc GR32:$src)),
1443 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1444 Requires<[In64BitMode]>;
1445 def : Pat<(i8 (trunc GR16:$src)),
1446 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1447 Requires<[In64BitMode]>;
1449 // h-register tricks
1450 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1451 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1453 Requires<[Not64BitMode]>;
1454 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1455 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1457 Requires<[Not64BitMode]>;
1458 def : Pat<(srl GR16:$src, (i8 8)),
1461 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1464 Requires<[Not64BitMode]>;
1465 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1466 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1469 Requires<[Not64BitMode]>;
1470 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1471 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1474 Requires<[Not64BitMode]>;
1475 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1476 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1479 Requires<[Not64BitMode]>;
1480 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1481 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1484 Requires<[Not64BitMode]>;
1486 // h-register tricks.
1487 // For now, be conservative on x86-64 and use an h-register extract only if the
1488 // value is immediately zero-extended or stored, which are somewhat common
1489 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1490 // from being allocated in the same instruction as the h register, as there's
1491 // currently no way to describe this requirement to the register allocator.
1493 // h-register extract and zero-extend.
1494 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1498 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1501 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1503 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1505 Requires<[In64BitMode]>;
1506 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1507 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1510 Requires<[In64BitMode]>;
1511 def : Pat<(srl GR16:$src, (i8 8)),
1514 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1517 Requires<[In64BitMode]>;
1518 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1520 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1522 Requires<[In64BitMode]>;
1523 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1525 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1527 Requires<[In64BitMode]>;
1528 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1535 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1539 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1543 // h-register extract and store.
1544 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1547 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1549 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1552 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1554 Requires<[In64BitMode]>;
1555 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1558 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1560 Requires<[In64BitMode]>;
1563 // (shl x, 1) ==> (add x, x)
1564 // Note that if x is undef (immediate or otherwise), we could theoretically
1565 // end up with the two uses of x getting different values, producing a result
1566 // where the least significant bit is not 0. However, the probability of this
1567 // happening is considered low enough that this is officially not a
1569 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1570 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1571 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1572 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1574 // Helper imms that check if a mask doesn't change significant shift bits.
1575 def immShift32 : ImmLeaf<i8, [{
1576 return countTrailingOnes<uint64_t>(Imm) >= 5;
1578 def immShift64 : ImmLeaf<i8, [{
1579 return countTrailingOnes<uint64_t>(Imm) >= 6;
1582 // Shift amount is implicitly masked.
1583 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1584 // (shift x (and y, 31)) ==> (shift x, y)
1585 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1586 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1587 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1588 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1589 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1590 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1591 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1592 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1593 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1594 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1595 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1596 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1598 // (shift x (and y, 63)) ==> (shift x, y)
1599 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1600 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1601 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1602 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1605 defm : MaskedShiftAmountPats<shl, "SHL">;
1606 defm : MaskedShiftAmountPats<srl, "SHR">;
1607 defm : MaskedShiftAmountPats<sra, "SAR">;
1608 defm : MaskedShiftAmountPats<rotl, "ROL">;
1609 defm : MaskedShiftAmountPats<rotr, "ROR">;
1611 // (anyext (setcc_carry)) -> (setcc_carry)
1612 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1614 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1616 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1622 //===----------------------------------------------------------------------===//
1623 // EFLAGS-defining Patterns
1624 //===----------------------------------------------------------------------===//
1627 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1628 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1629 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1632 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1633 (ADD8rm GR8:$src1, addr:$src2)>;
1634 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1635 (ADD16rm GR16:$src1, addr:$src2)>;
1636 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1637 (ADD32rm GR32:$src1, addr:$src2)>;
1640 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1641 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1642 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1643 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1644 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1645 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1646 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1649 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1650 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1651 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1654 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1655 (SUB8rm GR8:$src1, addr:$src2)>;
1656 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1657 (SUB16rm GR16:$src1, addr:$src2)>;
1658 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1659 (SUB32rm GR32:$src1, addr:$src2)>;
1662 def : Pat<(sub GR8:$src1, imm:$src2),
1663 (SUB8ri GR8:$src1, imm:$src2)>;
1664 def : Pat<(sub GR16:$src1, imm:$src2),
1665 (SUB16ri GR16:$src1, imm:$src2)>;
1666 def : Pat<(sub GR32:$src1, imm:$src2),
1667 (SUB32ri GR32:$src1, imm:$src2)>;
1668 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1669 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1670 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1671 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1674 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1675 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1676 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1677 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1680 def : Pat<(mul GR16:$src1, GR16:$src2),
1681 (IMUL16rr GR16:$src1, GR16:$src2)>;
1682 def : Pat<(mul GR32:$src1, GR32:$src2),
1683 (IMUL32rr GR32:$src1, GR32:$src2)>;
1686 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1687 (IMUL16rm GR16:$src1, addr:$src2)>;
1688 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1689 (IMUL32rm GR32:$src1, addr:$src2)>;
1692 def : Pat<(mul GR16:$src1, imm:$src2),
1693 (IMUL16rri GR16:$src1, imm:$src2)>;
1694 def : Pat<(mul GR32:$src1, imm:$src2),
1695 (IMUL32rri GR32:$src1, imm:$src2)>;
1696 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1697 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1698 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1699 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1701 // reg = mul mem, imm
1702 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1703 (IMUL16rmi addr:$src1, imm:$src2)>;
1704 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1705 (IMUL32rmi addr:$src1, imm:$src2)>;
1706 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1707 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1708 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1709 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1711 // Patterns for nodes that do not produce flags, for instructions that do.
1714 def : Pat<(add GR64:$src1, GR64:$src2),
1715 (ADD64rr GR64:$src1, GR64:$src2)>;
1716 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1717 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1718 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1719 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1720 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1721 (ADD64rm GR64:$src1, addr:$src2)>;
1724 def : Pat<(sub GR64:$src1, GR64:$src2),
1725 (SUB64rr GR64:$src1, GR64:$src2)>;
1726 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1727 (SUB64rm GR64:$src1, addr:$src2)>;
1728 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1729 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1730 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1731 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1734 def : Pat<(mul GR64:$src1, GR64:$src2),
1735 (IMUL64rr GR64:$src1, GR64:$src2)>;
1736 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1737 (IMUL64rm GR64:$src1, addr:$src2)>;
1738 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1739 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1740 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1741 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1742 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1743 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1744 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1745 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1747 // Increment/Decrement reg.
1748 // Do not make INC/DEC if it is slow
1749 let Predicates = [NotSlowIncDec] in {
1750 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1751 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1752 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1753 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1754 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1755 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1756 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1757 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1761 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1762 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1763 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1764 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1767 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1768 (OR8rm GR8:$src1, addr:$src2)>;
1769 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1770 (OR16rm GR16:$src1, addr:$src2)>;
1771 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1772 (OR32rm GR32:$src1, addr:$src2)>;
1773 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1774 (OR64rm GR64:$src1, addr:$src2)>;
1777 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1778 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1779 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1780 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1781 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1782 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1783 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1784 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1785 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1786 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1787 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1790 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1791 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1792 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1793 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1796 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1797 (XOR8rm GR8:$src1, addr:$src2)>;
1798 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1799 (XOR16rm GR16:$src1, addr:$src2)>;
1800 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1801 (XOR32rm GR32:$src1, addr:$src2)>;
1802 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1803 (XOR64rm GR64:$src1, addr:$src2)>;
1806 def : Pat<(xor GR8:$src1, imm:$src2),
1807 (XOR8ri GR8:$src1, imm:$src2)>;
1808 def : Pat<(xor GR16:$src1, imm:$src2),
1809 (XOR16ri GR16:$src1, imm:$src2)>;
1810 def : Pat<(xor GR32:$src1, imm:$src2),
1811 (XOR32ri GR32:$src1, imm:$src2)>;
1812 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1813 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1814 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1815 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1816 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1817 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1818 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1819 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1822 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1823 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1824 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1825 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1828 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1829 (AND8rm GR8:$src1, addr:$src2)>;
1830 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1831 (AND16rm GR16:$src1, addr:$src2)>;
1832 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1833 (AND32rm GR32:$src1, addr:$src2)>;
1834 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1835 (AND64rm GR64:$src1, addr:$src2)>;
1838 def : Pat<(and GR8:$src1, imm:$src2),
1839 (AND8ri GR8:$src1, imm:$src2)>;
1840 def : Pat<(and GR16:$src1, imm:$src2),
1841 (AND16ri GR16:$src1, imm:$src2)>;
1842 def : Pat<(and GR32:$src1, imm:$src2),
1843 (AND32ri GR32:$src1, imm:$src2)>;
1844 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1845 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1846 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1847 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1848 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1849 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1850 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1851 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1853 // Bit scan instruction patterns to match explicit zero-undef behavior.
1854 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1855 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1856 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1857 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1858 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1859 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1861 // When HasMOVBE is enabled it is possible to get a non-legalized
1862 // register-register 16 bit bswap. This maps it to a ROL instruction.
1863 let Predicates = [HasMOVBE] in {
1864 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;