1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
755 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
756 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
758 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
759 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
760 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
761 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
763 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
764 (COPY_TO_REGCLASS (VPCMPGTDZrr
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
766 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
768 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
769 (COPY_TO_REGCLASS (VPCMPEQDZrr
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
771 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
773 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
774 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
775 SDNode OpNode, ValueType vt, Operand CC, string asm,
777 def rri : AVX512AIi8<opc, MRMSrcReg,
778 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
779 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
780 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
784 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
785 // Accept explicit immediate argument form instead of comparison code.
786 let isAsmParserOnly = 1, hasSideEffects = 0 in {
787 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
788 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
789 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
790 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
791 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
792 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
796 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
797 X86cmpm, v16i32, AVXCC,
798 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 EVEX_V512, EVEX_CD8<32, CD8VF>;
801 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
802 X86cmpmu, v16i32, AVXCC,
803 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
805 EVEX_V512, EVEX_CD8<32, CD8VF>;
807 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
808 X86cmpm, v8i64, AVXCC,
809 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
810 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
811 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
812 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
813 X86cmpmu, v8i64, AVXCC,
814 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
815 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
816 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
818 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
819 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
820 X86MemOperand x86memop, ValueType vt,
821 string suffix, Domain d> {
822 def rri : AVX512PIi8<0xC2, MRMSrcReg,
823 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
824 !strconcat("vcmp${cc}", suffix,
825 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
826 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
827 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
828 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
829 !strconcat("vcmp${cc}", suffix,
830 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
832 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
834 !strconcat("vcmp${cc}", suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
837 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
839 // Accept explicit immediate argument form instead of comparison code.
840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
841 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
842 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
843 !strconcat("vcmp", suffix,
844 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
845 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
846 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
852 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
853 "ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512,
855 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
856 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
859 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
860 (COPY_TO_REGCLASS (VCMPPSZrri
861 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
862 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
864 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
865 (COPY_TO_REGCLASS (VPCMPDZrri
866 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
867 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
869 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
870 (COPY_TO_REGCLASS (VPCMPUDZrri
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
872 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
875 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
876 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
878 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
879 (I8Imm imm:$cc)), GR16)>;
881 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
882 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
884 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
885 (I8Imm imm:$cc)), GR8)>;
887 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
888 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
890 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
891 (I8Imm imm:$cc)), GR16)>;
893 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
894 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
896 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
897 (I8Imm imm:$cc)), GR8)>;
899 // Mask register copy, including
900 // - copy between mask registers
901 // - load/store mask registers
902 // - copy from GPR to mask register and vice versa
904 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
905 string OpcodeStr, RegisterClass KRC,
906 ValueType vt, X86MemOperand x86memop> {
907 let hasSideEffects = 0 in {
908 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
909 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
911 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
913 [(set KRC:$dst, (vt (load addr:$src)))]>;
915 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
920 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
922 RegisterClass KRC, RegisterClass GRC> {
923 let hasSideEffects = 0 in {
924 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
926 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
927 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 let Predicates = [HasAVX512] in {
932 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
934 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
938 let Predicates = [HasAVX512] in {
939 // GR16 from/to 16-bit mask
940 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
941 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
942 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
943 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
945 // Store kreg in memory
946 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
947 (KMOVWmk addr:$dst, VK16:$src)>;
949 def : Pat<(store VK8:$src, addr:$dst),
950 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
952 def : Pat<(i1 (load addr:$src)),
953 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
955 def : Pat<(v8i1 (load addr:$src)),
956 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
958 def : Pat<(i1 (trunc (i32 GR32:$src))),
959 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
961 def : Pat<(i1 (trunc (i8 GR8:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
965 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
966 def : Pat<(i8 (zext VK1:$src)),
968 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
969 def : Pat<(i64 (zext VK1:$src)),
970 (SUBREG_TO_REG (i64 0),
971 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
974 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
975 let Predicates = [HasAVX512] in {
976 // GR from/to 8-bit mask without native support
977 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
979 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
981 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
983 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
986 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
987 (COPY_TO_REGCLASS VK16:$src, VK1)>;
988 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
989 (COPY_TO_REGCLASS VK8:$src, VK1)>;
993 // Mask unary operation
995 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
996 RegisterClass KRC, SDPatternOperator OpNode> {
997 let Predicates = [HasAVX512] in
998 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
999 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1000 [(set KRC:$dst, (OpNode KRC:$src))]>;
1003 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1004 SDPatternOperator OpNode> {
1005 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1009 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1011 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1012 let Predicates = [HasAVX512] in
1013 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1015 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1016 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1018 defm : avx512_mask_unop_int<"knot", "KNOT">;
1020 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1021 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1022 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1024 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1025 def : Pat<(not VK8:$src),
1027 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1029 // Mask binary operation
1030 // - KAND, KANDN, KOR, KXNOR, KXOR
1031 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1032 RegisterClass KRC, SDPatternOperator OpNode> {
1033 let Predicates = [HasAVX512] in
1034 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1035 !strconcat(OpcodeStr,
1036 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1040 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1041 SDPatternOperator OpNode> {
1042 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1046 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1047 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1049 let isCommutable = 1 in {
1050 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1051 let isCommutable = 0 in
1052 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1053 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1054 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1055 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1058 def : Pat<(xor VK1:$src1, VK1:$src2),
1059 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1060 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1062 def : Pat<(or VK1:$src1, VK1:$src2),
1063 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1064 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1066 def : Pat<(and VK1:$src1, VK1:$src2),
1067 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1068 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1070 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1071 let Predicates = [HasAVX512] in
1072 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1073 (i16 GR16:$src1), (i16 GR16:$src2)),
1074 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1075 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1076 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1079 defm : avx512_mask_binop_int<"kand", "KAND">;
1080 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1081 defm : avx512_mask_binop_int<"kor", "KOR">;
1082 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1083 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1085 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1086 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1087 let Predicates = [HasAVX512] in
1088 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1090 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1091 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1094 defm : avx512_binop_pat<and, KANDWrr>;
1095 defm : avx512_binop_pat<andn, KANDNWrr>;
1096 defm : avx512_binop_pat<or, KORWrr>;
1097 defm : avx512_binop_pat<xnor, KXNORWrr>;
1098 defm : avx512_binop_pat<xor, KXORWrr>;
1101 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1102 RegisterClass KRC> {
1103 let Predicates = [HasAVX512] in
1104 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1105 !strconcat(OpcodeStr,
1106 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1109 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1110 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1114 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1115 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1116 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1117 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1120 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1121 let Predicates = [HasAVX512] in
1122 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1123 (i16 GR16:$src1), (i16 GR16:$src2)),
1124 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1125 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1126 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1128 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1131 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1133 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1134 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1135 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1136 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1139 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1140 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1144 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1146 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1147 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1148 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1151 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1153 let Predicates = [HasAVX512] in
1154 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1155 !strconcat(OpcodeStr,
1156 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1157 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1160 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1162 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1166 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1167 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1169 // Mask setting all 0s or 1s
1170 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1171 let Predicates = [HasAVX512] in
1172 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1173 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1174 [(set KRC:$dst, (VT Val))]>;
1177 multiclass avx512_mask_setop_w<PatFrag Val> {
1178 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1179 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1182 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1183 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1185 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1186 let Predicates = [HasAVX512] in {
1187 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1188 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1189 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1190 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1191 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1193 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1194 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1196 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1197 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1199 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1200 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1202 //===----------------------------------------------------------------------===//
1203 // AVX-512 - Aligned and unaligned load and store
1206 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1207 X86MemOperand x86memop, PatFrag ld_frag,
1208 string asm, Domain d, bit IsReMaterializable = 1> {
1209 let hasSideEffects = 0 in
1210 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1211 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1213 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1214 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1215 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1216 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1217 let Constraints = "$src1 = $dst" in {
1218 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1219 (ins RC:$src1, KRC:$mask, RC:$src2),
1221 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1223 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1224 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1226 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1227 [], d>, EVEX, EVEX_K;
1231 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1232 "vmovaps", SSEPackedSingle>,
1233 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1234 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1235 "vmovapd", SSEPackedDouble>,
1236 PD, EVEX_V512, VEX_W,
1237 EVEX_CD8<64, CD8VF>;
1238 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1239 "vmovups", SSEPackedSingle>,
1240 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1241 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1242 "vmovupd", SSEPackedDouble, 0>,
1243 PD, EVEX_V512, VEX_W,
1244 EVEX_CD8<64, CD8VF>;
1245 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1246 "vmovaps\t{$src, $dst|$dst, $src}",
1247 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1248 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1249 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1250 "vmovapd\t{$src, $dst|$dst, $src}",
1251 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1252 SSEPackedDouble>, EVEX, EVEX_V512,
1253 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1254 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1255 "vmovups\t{$src, $dst|$dst, $src}",
1256 [(store (v16f32 VR512:$src), addr:$dst)],
1257 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1258 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1259 "vmovupd\t{$src, $dst|$dst, $src}",
1260 [(store (v8f64 VR512:$src), addr:$dst)],
1261 SSEPackedDouble>, EVEX, EVEX_V512,
1262 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1264 let hasSideEffects = 0 in {
1265 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1267 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1269 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1271 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1272 EVEX, EVEX_V512, VEX_W;
1273 let mayStore = 1 in {
1274 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1275 (ins i512mem:$dst, VR512:$src),
1276 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1277 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1278 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1279 (ins i512mem:$dst, VR512:$src),
1280 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1281 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1283 let mayLoad = 1 in {
1284 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1286 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1287 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1288 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1290 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1291 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1295 // 512-bit aligned load/store
1296 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1297 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1299 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1300 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1301 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1302 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1304 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1305 RegisterClass RC, RegisterClass KRC,
1306 PatFrag ld_frag, X86MemOperand x86memop> {
1307 let hasSideEffects = 0 in
1308 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1309 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1310 let canFoldAsLoad = 1 in
1311 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1312 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1313 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1315 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1316 (ins x86memop:$dst, VR512:$src),
1317 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1318 let Constraints = "$src1 = $dst" in {
1319 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1320 (ins RC:$src1, KRC:$mask, RC:$src2),
1322 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1324 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1325 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1327 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1330 def rrkz : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1331 (ins KRC:$mask, RC:$src),
1333 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), []>,
1337 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1338 memopv16i32, i512mem>,
1339 EVEX_V512, EVEX_CD8<32, CD8VF>;
1340 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1341 memopv8i64, i512mem>,
1342 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1344 // 512-bit unaligned load/store
1345 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1346 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1348 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1349 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1350 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1351 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1353 let AddedComplexity = 20 in {
1354 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1355 (bc_v8i64 (v16i32 immAllZerosV)))),
1356 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1358 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1359 (v8i64 VR512:$src))),
1360 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1363 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1364 (v16i32 immAllZerosV))),
1365 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1367 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1368 (v16i32 VR512:$src))),
1369 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1371 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1372 (v16f32 VR512:$src2))),
1373 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1374 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1375 (v8f64 VR512:$src2))),
1376 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1377 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1378 (v16i32 VR512:$src2))),
1379 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1380 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1381 (v8i64 VR512:$src2))),
1382 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1384 // Move Int Doubleword to Packed Double Int
1386 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1387 "vmovd\t{$src, $dst|$dst, $src}",
1389 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1391 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1392 "vmovd\t{$src, $dst|$dst, $src}",
1394 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1395 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1396 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1397 "vmovq\t{$src, $dst|$dst, $src}",
1399 (v2i64 (scalar_to_vector GR64:$src)))],
1400 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1401 let isCodeGenOnly = 1 in {
1402 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1403 "vmovq\t{$src, $dst|$dst, $src}",
1404 [(set FR64:$dst, (bitconvert GR64:$src))],
1405 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1406 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1407 "vmovq\t{$src, $dst|$dst, $src}",
1408 [(set GR64:$dst, (bitconvert FR64:$src))],
1409 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1411 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1412 "vmovq\t{$src, $dst|$dst, $src}",
1413 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1414 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1415 EVEX_CD8<64, CD8VT1>;
1417 // Move Int Doubleword to Single Scalar
1419 let isCodeGenOnly = 1 in {
1420 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1421 "vmovd\t{$src, $dst|$dst, $src}",
1422 [(set FR32X:$dst, (bitconvert GR32:$src))],
1423 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1425 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1426 "vmovd\t{$src, $dst|$dst, $src}",
1427 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1428 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1431 // Move doubleword from xmm register to r/m32
1433 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1434 "vmovd\t{$src, $dst|$dst, $src}",
1435 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1436 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1438 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1439 (ins i32mem:$dst, VR128X:$src),
1440 "vmovd\t{$src, $dst|$dst, $src}",
1441 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1442 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1443 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1445 // Move quadword from xmm1 register to r/m64
1447 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1448 "vmovq\t{$src, $dst|$dst, $src}",
1449 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1451 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1452 Requires<[HasAVX512, In64BitMode]>;
1454 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1455 (ins i64mem:$dst, VR128X:$src),
1456 "vmovq\t{$src, $dst|$dst, $src}",
1457 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1458 addr:$dst)], IIC_SSE_MOVDQ>,
1459 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1460 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1462 // Move Scalar Single to Double Int
1464 let isCodeGenOnly = 1 in {
1465 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1467 "vmovd\t{$src, $dst|$dst, $src}",
1468 [(set GR32:$dst, (bitconvert FR32X:$src))],
1469 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1470 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1471 (ins i32mem:$dst, FR32X:$src),
1472 "vmovd\t{$src, $dst|$dst, $src}",
1473 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1474 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1477 // Move Quadword Int to Packed Quadword Int
1479 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1481 "vmovq\t{$src, $dst|$dst, $src}",
1483 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1484 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1486 //===----------------------------------------------------------------------===//
1487 // AVX-512 MOVSS, MOVSD
1488 //===----------------------------------------------------------------------===//
1490 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1491 SDNode OpNode, ValueType vt,
1492 X86MemOperand x86memop, PatFrag mem_pat> {
1493 let hasSideEffects = 0 in {
1494 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1495 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1496 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1497 (scalar_to_vector RC:$src2))))],
1498 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1499 let Constraints = "$src1 = $dst" in
1500 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1501 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1503 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1504 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1505 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1506 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1507 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1509 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1510 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1511 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1513 } //hasSideEffects = 0
1516 let ExeDomain = SSEPackedSingle in
1517 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1518 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1520 let ExeDomain = SSEPackedDouble in
1521 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1522 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1524 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1525 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1526 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1528 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1529 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1530 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1532 // For the disassembler
1533 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1534 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1535 (ins VR128X:$src1, FR32X:$src2),
1536 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1538 XS, EVEX_4V, VEX_LIG;
1539 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1540 (ins VR128X:$src1, FR64X:$src2),
1541 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1543 XD, EVEX_4V, VEX_LIG, VEX_W;
1546 let Predicates = [HasAVX512] in {
1547 let AddedComplexity = 15 in {
1548 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1549 // MOVS{S,D} to the lower bits.
1550 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1551 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1552 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1553 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1554 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1555 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1556 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1557 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1559 // Move low f32 and clear high bits.
1560 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1561 (SUBREG_TO_REG (i32 0),
1562 (VMOVSSZrr (v4f32 (V_SET0)),
1563 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1564 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1565 (SUBREG_TO_REG (i32 0),
1566 (VMOVSSZrr (v4i32 (V_SET0)),
1567 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1570 let AddedComplexity = 20 in {
1571 // MOVSSrm zeros the high parts of the register; represent this
1572 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1573 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1574 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1575 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1576 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1577 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1578 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1580 // MOVSDrm zeros the high parts of the register; represent this
1581 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1582 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1583 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1584 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1585 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1586 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1587 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1588 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1589 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1590 def : Pat<(v2f64 (X86vzload addr:$src)),
1591 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1593 // Represent the same patterns above but in the form they appear for
1595 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1596 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1597 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1598 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1599 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1600 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1601 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1602 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1603 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1605 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1606 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1607 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1608 FR32X:$src)), sub_xmm)>;
1609 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1610 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1611 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1612 FR64X:$src)), sub_xmm)>;
1613 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1614 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1615 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1617 // Move low f64 and clear high bits.
1618 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1619 (SUBREG_TO_REG (i32 0),
1620 (VMOVSDZrr (v2f64 (V_SET0)),
1621 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1623 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1624 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1625 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1627 // Extract and store.
1628 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1630 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1631 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1633 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1635 // Shuffle with VMOVSS
1636 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1637 (VMOVSSZrr (v4i32 VR128X:$src1),
1638 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1639 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1640 (VMOVSSZrr (v4f32 VR128X:$src1),
1641 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1644 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1645 (SUBREG_TO_REG (i32 0),
1646 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1647 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1649 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1650 (SUBREG_TO_REG (i32 0),
1651 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1652 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1655 // Shuffle with VMOVSD
1656 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1657 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1658 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1659 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1660 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1661 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1662 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1666 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1667 (SUBREG_TO_REG (i32 0),
1668 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1669 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1671 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1672 (SUBREG_TO_REG (i32 0),
1673 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1674 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1677 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1678 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1679 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1680 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1681 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1682 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1683 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1684 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1687 let AddedComplexity = 15 in
1688 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1690 "vmovq\t{$src, $dst|$dst, $src}",
1691 [(set VR128X:$dst, (v2i64 (X86vzmovl
1692 (v2i64 VR128X:$src))))],
1693 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1695 let AddedComplexity = 20 in
1696 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1698 "vmovq\t{$src, $dst|$dst, $src}",
1699 [(set VR128X:$dst, (v2i64 (X86vzmovl
1700 (loadv2i64 addr:$src))))],
1701 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1702 EVEX_CD8<8, CD8VT8>;
1704 let Predicates = [HasAVX512] in {
1705 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1706 let AddedComplexity = 20 in {
1707 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1708 (VMOVDI2PDIZrm addr:$src)>;
1709 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1710 (VMOV64toPQIZrr GR64:$src)>;
1711 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1712 (VMOVDI2PDIZrr GR32:$src)>;
1714 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1715 (VMOVDI2PDIZrm addr:$src)>;
1716 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1717 (VMOVDI2PDIZrm addr:$src)>;
1718 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1719 (VMOVZPQILo2PQIZrm addr:$src)>;
1720 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1721 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1722 def : Pat<(v2i64 (X86vzload addr:$src)),
1723 (VMOVZPQILo2PQIZrm addr:$src)>;
1726 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1727 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1728 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1729 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1730 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1731 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1732 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1735 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1736 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1738 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1739 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1741 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1742 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1744 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1745 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1747 //===----------------------------------------------------------------------===//
1748 // AVX-512 - Integer arithmetic
1750 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1751 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1752 X86MemOperand x86memop, PatFrag scalar_mfrag,
1753 X86MemOperand x86scalar_mop, string BrdcstStr,
1754 OpndItins itins, bit IsCommutable = 0> {
1755 let isCommutable = IsCommutable in
1756 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1757 (ins RC:$src1, RC:$src2),
1758 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1759 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1761 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1762 (ins RC:$src1, x86memop:$src2),
1763 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1764 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1766 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1767 (ins RC:$src1, x86scalar_mop:$src2),
1768 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1769 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1770 [(set RC:$dst, (OpNode RC:$src1,
1771 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1772 itins.rm>, EVEX_4V, EVEX_B;
1774 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1775 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1776 PatFrag memop_frag, X86MemOperand x86memop,
1778 bit IsCommutable = 0> {
1779 let isCommutable = IsCommutable in
1780 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1781 (ins RC:$src1, RC:$src2),
1782 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1783 []>, EVEX_4V, VEX_W;
1784 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1785 (ins RC:$src1, x86memop:$src2),
1786 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1787 []>, EVEX_4V, VEX_W;
1790 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1791 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1792 EVEX_V512, EVEX_CD8<32, CD8VF>;
1794 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1795 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1796 EVEX_V512, EVEX_CD8<32, CD8VF>;
1798 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1799 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1800 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1802 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1803 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1804 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1806 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1807 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1808 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1810 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1811 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1812 EVEX_V512, EVEX_CD8<64, CD8VF>;
1814 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1815 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1816 EVEX_CD8<64, CD8VF>;
1818 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1819 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1821 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1822 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1823 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1824 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1825 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1826 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1828 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1829 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1830 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1831 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1832 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1833 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1835 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1836 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1837 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1838 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1839 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1840 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1842 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1843 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1844 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1845 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1846 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1847 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1849 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1850 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1851 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1852 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1853 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1854 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1856 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1857 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1858 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1859 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1860 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1861 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1862 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1863 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1864 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1865 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1866 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1867 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1868 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1869 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1870 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1871 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1872 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1873 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1874 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1875 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1876 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1877 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1878 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1879 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1880 //===----------------------------------------------------------------------===//
1881 // AVX-512 - Unpack Instructions
1882 //===----------------------------------------------------------------------===//
1884 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1885 PatFrag mem_frag, RegisterClass RC,
1886 X86MemOperand x86memop, string asm,
1888 def rr : AVX512PI<opc, MRMSrcReg,
1889 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1891 (vt (OpNode RC:$src1, RC:$src2)))],
1893 def rm : AVX512PI<opc, MRMSrcMem,
1894 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1896 (vt (OpNode RC:$src1,
1897 (bitconvert (mem_frag addr:$src2)))))],
1901 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1902 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1903 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1904 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1905 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1906 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1907 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1908 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1909 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1910 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1911 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1912 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1914 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1915 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1916 X86MemOperand x86memop> {
1917 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1918 (ins RC:$src1, RC:$src2),
1919 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1920 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1921 IIC_SSE_UNPCK>, EVEX_4V;
1922 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1923 (ins RC:$src1, x86memop:$src2),
1924 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1925 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1926 (bitconvert (memop_frag addr:$src2)))))],
1927 IIC_SSE_UNPCK>, EVEX_4V;
1929 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1930 VR512, memopv16i32, i512mem>, EVEX_V512,
1931 EVEX_CD8<32, CD8VF>;
1932 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1933 VR512, memopv8i64, i512mem>, EVEX_V512,
1934 VEX_W, EVEX_CD8<64, CD8VF>;
1935 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1936 VR512, memopv16i32, i512mem>, EVEX_V512,
1937 EVEX_CD8<32, CD8VF>;
1938 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1939 VR512, memopv8i64, i512mem>, EVEX_V512,
1940 VEX_W, EVEX_CD8<64, CD8VF>;
1941 //===----------------------------------------------------------------------===//
1945 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1946 SDNode OpNode, PatFrag mem_frag,
1947 X86MemOperand x86memop, ValueType OpVT> {
1948 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1949 (ins RC:$src1, i8imm:$src2),
1950 !strconcat(OpcodeStr,
1951 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1953 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1955 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1956 (ins x86memop:$src1, i8imm:$src2),
1957 !strconcat(OpcodeStr,
1958 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1960 (OpVT (OpNode (mem_frag addr:$src1),
1961 (i8 imm:$src2))))]>, EVEX;
1964 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1965 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1967 let ExeDomain = SSEPackedSingle in
1968 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1969 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1970 EVEX_CD8<32, CD8VF>;
1971 let ExeDomain = SSEPackedDouble in
1972 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1973 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1974 VEX_W, EVEX_CD8<32, CD8VF>;
1976 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1977 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1978 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1979 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1981 //===----------------------------------------------------------------------===//
1982 // AVX-512 Logical Instructions
1983 //===----------------------------------------------------------------------===//
1985 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1986 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1987 EVEX_V512, EVEX_CD8<32, CD8VF>;
1988 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1989 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1990 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1991 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1992 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1993 EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1995 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1996 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1997 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1998 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1999 EVEX_V512, EVEX_CD8<32, CD8VF>;
2000 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2001 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2002 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2003 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2004 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2005 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2006 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2007 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2008 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2010 //===----------------------------------------------------------------------===//
2011 // AVX-512 FP arithmetic
2012 //===----------------------------------------------------------------------===//
2014 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2016 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2017 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2018 EVEX_CD8<32, CD8VT1>;
2019 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2020 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2021 EVEX_CD8<64, CD8VT1>;
2024 let isCommutable = 1 in {
2025 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2026 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2027 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2028 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2030 let isCommutable = 0 in {
2031 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2032 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2035 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2036 RegisterClass RC, ValueType vt,
2037 X86MemOperand x86memop, PatFrag mem_frag,
2038 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2040 Domain d, OpndItins itins, bit commutable> {
2041 let isCommutable = commutable in
2042 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2043 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2044 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2046 let mayLoad = 1 in {
2047 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2048 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2049 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2050 itins.rm, d>, EVEX_4V;
2051 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2052 (ins RC:$src1, x86scalar_mop:$src2),
2053 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2054 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2055 [(set RC:$dst, (OpNode RC:$src1,
2056 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2057 itins.rm, d>, EVEX_4V, EVEX_B;
2061 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2062 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2063 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2065 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2066 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2067 SSE_ALU_ITINS_P.d, 1>,
2068 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2070 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2071 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2072 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2073 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2074 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2075 SSE_ALU_ITINS_P.d, 1>,
2076 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2078 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2079 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2080 SSE_ALU_ITINS_P.s, 1>,
2081 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2082 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2083 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2084 SSE_ALU_ITINS_P.s, 1>,
2085 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2087 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2088 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2089 SSE_ALU_ITINS_P.d, 1>,
2090 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2091 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2092 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2093 SSE_ALU_ITINS_P.d, 1>,
2094 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2096 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2097 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2098 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2099 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2100 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2101 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2103 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2104 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2105 SSE_ALU_ITINS_P.d, 0>,
2106 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2107 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2108 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2109 SSE_ALU_ITINS_P.d, 0>,
2110 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2112 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2113 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2114 (i16 -1), FROUND_CURRENT)),
2115 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2117 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2118 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2119 (i8 -1), FROUND_CURRENT)),
2120 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2122 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2123 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2124 (i16 -1), FROUND_CURRENT)),
2125 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2127 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2128 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2129 (i8 -1), FROUND_CURRENT)),
2130 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2131 //===----------------------------------------------------------------------===//
2132 // AVX-512 VPTESTM instructions
2133 //===----------------------------------------------------------------------===//
2135 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2136 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2137 SDNode OpNode, ValueType vt> {
2138 def rr : AVX512PI<opc, MRMSrcReg,
2139 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2140 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2141 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2142 SSEPackedInt>, EVEX_4V;
2143 def rm : AVX512PI<opc, MRMSrcMem,
2144 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2145 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2146 [(set KRC:$dst, (OpNode (vt RC:$src1),
2147 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2150 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2151 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2152 EVEX_CD8<32, CD8VF>;
2153 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2154 memopv8i64, X86testm, v8i64>, T8XS, EVEX_V512, VEX_W,
2155 EVEX_CD8<64, CD8VF>;
2157 let Predicates = [HasCDI] in {
2158 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2159 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2160 EVEX_CD8<32, CD8VF>;
2161 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2162 memopv8i64, X86testnm, v8i64>, T8PD, EVEX_V512, VEX_W,
2163 EVEX_CD8<64, CD8VF>;
2166 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2167 (v16i32 VR512:$src2), (i16 -1))),
2168 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2170 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2171 (v8i64 VR512:$src2), (i8 -1))),
2172 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2173 //===----------------------------------------------------------------------===//
2174 // AVX-512 Shift instructions
2175 //===----------------------------------------------------------------------===//
2176 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2177 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2178 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2179 RegisterClass KRC> {
2180 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2181 (ins RC:$src1, i8imm:$src2),
2182 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2183 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2184 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2185 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2186 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2187 !strconcat(OpcodeStr,
2188 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2189 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2190 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2191 (ins x86memop:$src1, i8imm:$src2),
2192 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2193 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2194 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2195 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2196 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2197 !strconcat(OpcodeStr,
2198 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2199 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2202 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2203 RegisterClass RC, ValueType vt, ValueType SrcVT,
2204 PatFrag bc_frag, RegisterClass KRC> {
2205 // src2 is always 128-bit
2206 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2207 (ins RC:$src1, VR128X:$src2),
2208 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2209 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2210 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2211 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2212 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2213 !strconcat(OpcodeStr,
2214 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2215 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2216 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2217 (ins RC:$src1, i128mem:$src2),
2218 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2219 [(set RC:$dst, (vt (OpNode RC:$src1,
2220 (bc_frag (memopv2i64 addr:$src2)))))],
2221 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2222 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2223 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2224 !strconcat(OpcodeStr,
2225 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2226 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2229 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2230 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2231 EVEX_V512, EVEX_CD8<32, CD8VF>;
2232 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2233 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2234 EVEX_CD8<32, CD8VQ>;
2236 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2237 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2238 EVEX_CD8<64, CD8VF>, VEX_W;
2239 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2240 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2241 EVEX_CD8<64, CD8VQ>, VEX_W;
2243 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2244 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2245 EVEX_CD8<32, CD8VF>;
2246 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2247 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2248 EVEX_CD8<32, CD8VQ>;
2250 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2251 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2252 EVEX_CD8<64, CD8VF>, VEX_W;
2253 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2254 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2255 EVEX_CD8<64, CD8VQ>, VEX_W;
2257 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2258 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2259 EVEX_V512, EVEX_CD8<32, CD8VF>;
2260 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2261 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2262 EVEX_CD8<32, CD8VQ>;
2264 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2265 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2266 EVEX_CD8<64, CD8VF>, VEX_W;
2267 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2268 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2269 EVEX_CD8<64, CD8VQ>, VEX_W;
2271 //===-------------------------------------------------------------------===//
2272 // Variable Bit Shifts
2273 //===-------------------------------------------------------------------===//
2274 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2275 RegisterClass RC, ValueType vt,
2276 X86MemOperand x86memop, PatFrag mem_frag> {
2277 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2278 (ins RC:$src1, RC:$src2),
2279 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2281 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2283 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2284 (ins RC:$src1, x86memop:$src2),
2285 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2287 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2291 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2292 i512mem, memopv16i32>, EVEX_V512,
2293 EVEX_CD8<32, CD8VF>;
2294 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2295 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2296 EVEX_CD8<64, CD8VF>;
2297 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2298 i512mem, memopv16i32>, EVEX_V512,
2299 EVEX_CD8<32, CD8VF>;
2300 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2301 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2302 EVEX_CD8<64, CD8VF>;
2303 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2304 i512mem, memopv16i32>, EVEX_V512,
2305 EVEX_CD8<32, CD8VF>;
2306 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2307 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2308 EVEX_CD8<64, CD8VF>;
2310 //===----------------------------------------------------------------------===//
2311 // AVX-512 - MOVDDUP
2312 //===----------------------------------------------------------------------===//
2314 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2315 X86MemOperand x86memop, PatFrag memop_frag> {
2316 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2317 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2318 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2319 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2320 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2322 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2325 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2326 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2327 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2328 (VMOVDDUPZrm addr:$src)>;
2330 //===---------------------------------------------------------------------===//
2331 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2332 //===---------------------------------------------------------------------===//
2333 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2334 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2335 X86MemOperand x86memop> {
2336 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2337 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2338 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2340 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2341 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2342 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2345 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2346 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2347 EVEX_CD8<32, CD8VF>;
2348 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2349 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2350 EVEX_CD8<32, CD8VF>;
2352 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2353 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2354 (VMOVSHDUPZrm addr:$src)>;
2355 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2356 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2357 (VMOVSLDUPZrm addr:$src)>;
2359 //===----------------------------------------------------------------------===//
2360 // Move Low to High and High to Low packed FP Instructions
2361 //===----------------------------------------------------------------------===//
2362 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2363 (ins VR128X:$src1, VR128X:$src2),
2364 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2366 IIC_SSE_MOV_LH>, EVEX_4V;
2367 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2368 (ins VR128X:$src1, VR128X:$src2),
2369 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2370 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2371 IIC_SSE_MOV_LH>, EVEX_4V;
2373 let Predicates = [HasAVX512] in {
2375 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2376 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2377 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2378 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2381 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2382 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2385 //===----------------------------------------------------------------------===//
2386 // FMA - Fused Multiply Operations
2388 let Constraints = "$src1 = $dst" in {
2389 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2390 RegisterClass RC, X86MemOperand x86memop,
2391 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2392 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2393 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2394 (ins RC:$src1, RC:$src2, RC:$src3),
2395 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2396 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2399 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2400 (ins RC:$src1, RC:$src2, x86memop:$src3),
2401 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2402 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2403 (mem_frag addr:$src3))))]>;
2404 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2405 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2406 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2407 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2408 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2409 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2411 } // Constraints = "$src1 = $dst"
2413 let ExeDomain = SSEPackedSingle in {
2414 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2415 memopv16f32, f32mem, loadf32, "{1to16}",
2416 X86Fmadd, v16f32>, EVEX_V512,
2417 EVEX_CD8<32, CD8VF>;
2418 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2419 memopv16f32, f32mem, loadf32, "{1to16}",
2420 X86Fmsub, v16f32>, EVEX_V512,
2421 EVEX_CD8<32, CD8VF>;
2422 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2423 memopv16f32, f32mem, loadf32, "{1to16}",
2424 X86Fmaddsub, v16f32>,
2425 EVEX_V512, EVEX_CD8<32, CD8VF>;
2426 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2427 memopv16f32, f32mem, loadf32, "{1to16}",
2428 X86Fmsubadd, v16f32>,
2429 EVEX_V512, EVEX_CD8<32, CD8VF>;
2430 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2431 memopv16f32, f32mem, loadf32, "{1to16}",
2432 X86Fnmadd, v16f32>, EVEX_V512,
2433 EVEX_CD8<32, CD8VF>;
2434 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2435 memopv16f32, f32mem, loadf32, "{1to16}",
2436 X86Fnmsub, v16f32>, EVEX_V512,
2437 EVEX_CD8<32, CD8VF>;
2439 let ExeDomain = SSEPackedDouble in {
2440 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2441 memopv8f64, f64mem, loadf64, "{1to8}",
2442 X86Fmadd, v8f64>, EVEX_V512,
2443 VEX_W, EVEX_CD8<64, CD8VF>;
2444 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2445 memopv8f64, f64mem, loadf64, "{1to8}",
2446 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2447 EVEX_CD8<64, CD8VF>;
2448 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2449 memopv8f64, f64mem, loadf64, "{1to8}",
2450 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2451 EVEX_CD8<64, CD8VF>;
2452 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2453 memopv8f64, f64mem, loadf64, "{1to8}",
2454 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2455 EVEX_CD8<64, CD8VF>;
2456 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2457 memopv8f64, f64mem, loadf64, "{1to8}",
2458 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2459 EVEX_CD8<64, CD8VF>;
2460 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2461 memopv8f64, f64mem, loadf64, "{1to8}",
2462 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2463 EVEX_CD8<64, CD8VF>;
2466 let Constraints = "$src1 = $dst" in {
2467 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2468 RegisterClass RC, X86MemOperand x86memop,
2469 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2470 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2472 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2473 (ins RC:$src1, RC:$src3, x86memop:$src2),
2474 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2475 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2476 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2477 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2478 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2479 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2480 [(set RC:$dst, (OpNode RC:$src1,
2481 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2483 } // Constraints = "$src1 = $dst"
2486 let ExeDomain = SSEPackedSingle in {
2487 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2488 memopv16f32, f32mem, loadf32, "{1to16}",
2489 X86Fmadd, v16f32>, EVEX_V512,
2490 EVEX_CD8<32, CD8VF>;
2491 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2492 memopv16f32, f32mem, loadf32, "{1to16}",
2493 X86Fmsub, v16f32>, EVEX_V512,
2494 EVEX_CD8<32, CD8VF>;
2495 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2496 memopv16f32, f32mem, loadf32, "{1to16}",
2497 X86Fmaddsub, v16f32>,
2498 EVEX_V512, EVEX_CD8<32, CD8VF>;
2499 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2500 memopv16f32, f32mem, loadf32, "{1to16}",
2501 X86Fmsubadd, v16f32>,
2502 EVEX_V512, EVEX_CD8<32, CD8VF>;
2503 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2504 memopv16f32, f32mem, loadf32, "{1to16}",
2505 X86Fnmadd, v16f32>, EVEX_V512,
2506 EVEX_CD8<32, CD8VF>;
2507 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2508 memopv16f32, f32mem, loadf32, "{1to16}",
2509 X86Fnmsub, v16f32>, EVEX_V512,
2510 EVEX_CD8<32, CD8VF>;
2512 let ExeDomain = SSEPackedDouble in {
2513 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2514 memopv8f64, f64mem, loadf64, "{1to8}",
2515 X86Fmadd, v8f64>, EVEX_V512,
2516 VEX_W, EVEX_CD8<64, CD8VF>;
2517 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2518 memopv8f64, f64mem, loadf64, "{1to8}",
2519 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2520 EVEX_CD8<64, CD8VF>;
2521 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2522 memopv8f64, f64mem, loadf64, "{1to8}",
2523 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2524 EVEX_CD8<64, CD8VF>;
2525 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2526 memopv8f64, f64mem, loadf64, "{1to8}",
2527 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2528 EVEX_CD8<64, CD8VF>;
2529 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2530 memopv8f64, f64mem, loadf64, "{1to8}",
2531 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2532 EVEX_CD8<64, CD8VF>;
2533 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2534 memopv8f64, f64mem, loadf64, "{1to8}",
2535 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2536 EVEX_CD8<64, CD8VF>;
2540 let Constraints = "$src1 = $dst" in {
2541 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2542 RegisterClass RC, ValueType OpVT,
2543 X86MemOperand x86memop, Operand memop,
2545 let isCommutable = 1 in
2546 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2547 (ins RC:$src1, RC:$src2, RC:$src3),
2548 !strconcat(OpcodeStr,
2549 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2551 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2553 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2554 (ins RC:$src1, RC:$src2, f128mem:$src3),
2555 !strconcat(OpcodeStr,
2556 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2558 (OpVT (OpNode RC:$src2, RC:$src1,
2559 (mem_frag addr:$src3))))]>;
2562 } // Constraints = "$src1 = $dst"
2564 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2565 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2566 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2567 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2568 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2569 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2570 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2571 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2572 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2573 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2574 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2575 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2576 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2577 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2578 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2579 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2581 //===----------------------------------------------------------------------===//
2582 // AVX-512 Scalar convert from sign integer to float/double
2583 //===----------------------------------------------------------------------===//
2585 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2586 X86MemOperand x86memop, string asm> {
2587 let hasSideEffects = 0 in {
2588 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2589 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2592 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2593 (ins DstRC:$src1, x86memop:$src),
2594 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2596 } // hasSideEffects = 0
2598 let Predicates = [HasAVX512] in {
2599 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2600 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2601 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2602 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2603 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2604 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2605 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2606 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2608 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2609 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2610 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2611 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2612 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2613 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2614 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2615 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2617 def : Pat<(f32 (sint_to_fp GR32:$src)),
2618 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2619 def : Pat<(f32 (sint_to_fp GR64:$src)),
2620 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2621 def : Pat<(f64 (sint_to_fp GR32:$src)),
2622 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2623 def : Pat<(f64 (sint_to_fp GR64:$src)),
2624 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2626 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2627 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2628 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2629 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2630 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2631 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2632 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2633 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2635 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2636 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2637 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2638 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2639 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2640 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2641 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2642 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2644 def : Pat<(f32 (uint_to_fp GR32:$src)),
2645 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2646 def : Pat<(f32 (uint_to_fp GR64:$src)),
2647 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2648 def : Pat<(f64 (uint_to_fp GR32:$src)),
2649 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2650 def : Pat<(f64 (uint_to_fp GR64:$src)),
2651 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2654 //===----------------------------------------------------------------------===//
2655 // AVX-512 Scalar convert from float/double to integer
2656 //===----------------------------------------------------------------------===//
2657 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2658 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2660 let hasSideEffects = 0 in {
2661 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2662 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2663 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2664 Requires<[HasAVX512]>;
2666 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2667 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2668 Requires<[HasAVX512]>;
2669 } // hasSideEffects = 0
2671 let Predicates = [HasAVX512] in {
2672 // Convert float/double to signed/unsigned int 32/64
2673 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2674 ssmem, sse_load_f32, "cvtss2si">,
2675 XS, EVEX_CD8<32, CD8VT1>;
2676 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2677 ssmem, sse_load_f32, "cvtss2si">,
2678 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2679 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2680 ssmem, sse_load_f32, "cvtss2usi">,
2681 XS, EVEX_CD8<32, CD8VT1>;
2682 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2683 int_x86_avx512_cvtss2usi64, ssmem,
2684 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2685 EVEX_CD8<32, CD8VT1>;
2686 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2687 sdmem, sse_load_f64, "cvtsd2si">,
2688 XD, EVEX_CD8<64, CD8VT1>;
2689 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2690 sdmem, sse_load_f64, "cvtsd2si">,
2691 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2692 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2693 sdmem, sse_load_f64, "cvtsd2usi">,
2694 XD, EVEX_CD8<64, CD8VT1>;
2695 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2696 int_x86_avx512_cvtsd2usi64, sdmem,
2697 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2698 EVEX_CD8<64, CD8VT1>;
2700 let isCodeGenOnly = 1 in {
2701 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2702 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2703 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2704 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2705 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2706 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2707 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2708 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2709 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2710 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2711 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2712 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2714 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2715 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2716 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2717 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2718 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2719 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2720 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2721 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2722 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2723 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2724 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2725 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2726 } // isCodeGenOnly = 1
2728 // Convert float/double to signed/unsigned int 32/64 with truncation
2729 let isCodeGenOnly = 1 in {
2730 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2731 ssmem, sse_load_f32, "cvttss2si">,
2732 XS, EVEX_CD8<32, CD8VT1>;
2733 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2734 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2735 "cvttss2si">, XS, VEX_W,
2736 EVEX_CD8<32, CD8VT1>;
2737 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2738 sdmem, sse_load_f64, "cvttsd2si">, XD,
2739 EVEX_CD8<64, CD8VT1>;
2740 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2741 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2742 "cvttsd2si">, XD, VEX_W,
2743 EVEX_CD8<64, CD8VT1>;
2744 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2745 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2746 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2747 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2748 int_x86_avx512_cvttss2usi64, ssmem,
2749 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2750 EVEX_CD8<32, CD8VT1>;
2751 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2752 int_x86_avx512_cvttsd2usi,
2753 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2754 EVEX_CD8<64, CD8VT1>;
2755 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2756 int_x86_avx512_cvttsd2usi64, sdmem,
2757 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2758 EVEX_CD8<64, CD8VT1>;
2759 } // isCodeGenOnly = 1
2761 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2762 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2764 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2765 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2766 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2767 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2768 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2769 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2772 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2773 loadf32, "cvttss2si">, XS,
2774 EVEX_CD8<32, CD8VT1>;
2775 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2776 loadf32, "cvttss2usi">, XS,
2777 EVEX_CD8<32, CD8VT1>;
2778 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2779 loadf32, "cvttss2si">, XS, VEX_W,
2780 EVEX_CD8<32, CD8VT1>;
2781 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2782 loadf32, "cvttss2usi">, XS, VEX_W,
2783 EVEX_CD8<32, CD8VT1>;
2784 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2785 loadf64, "cvttsd2si">, XD,
2786 EVEX_CD8<64, CD8VT1>;
2787 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2788 loadf64, "cvttsd2usi">, XD,
2789 EVEX_CD8<64, CD8VT1>;
2790 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2791 loadf64, "cvttsd2si">, XD, VEX_W,
2792 EVEX_CD8<64, CD8VT1>;
2793 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2794 loadf64, "cvttsd2usi">, XD, VEX_W,
2795 EVEX_CD8<64, CD8VT1>;
2797 //===----------------------------------------------------------------------===//
2798 // AVX-512 Convert form float to double and back
2799 //===----------------------------------------------------------------------===//
2800 let hasSideEffects = 0 in {
2801 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2802 (ins FR32X:$src1, FR32X:$src2),
2803 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2804 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2806 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2807 (ins FR32X:$src1, f32mem:$src2),
2808 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2809 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2810 EVEX_CD8<32, CD8VT1>;
2812 // Convert scalar double to scalar single
2813 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2814 (ins FR64X:$src1, FR64X:$src2),
2815 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2816 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2818 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2819 (ins FR64X:$src1, f64mem:$src2),
2820 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2821 []>, EVEX_4V, VEX_LIG, VEX_W,
2822 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2825 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2826 Requires<[HasAVX512]>;
2827 def : Pat<(fextend (loadf32 addr:$src)),
2828 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2830 def : Pat<(extloadf32 addr:$src),
2831 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2832 Requires<[HasAVX512, OptForSize]>;
2834 def : Pat<(extloadf32 addr:$src),
2835 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2836 Requires<[HasAVX512, OptForSpeed]>;
2838 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2839 Requires<[HasAVX512]>;
2841 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2842 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2843 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2845 let hasSideEffects = 0 in {
2846 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2847 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2849 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2850 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2851 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2852 [], d>, EVEX, EVEX_B, EVEX_RC;
2854 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2855 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2857 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2858 } // hasSideEffects = 0
2861 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2862 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2863 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2865 let hasSideEffects = 0 in {
2866 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2867 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2869 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2871 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2872 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2874 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2875 } // hasSideEffects = 0
2878 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2879 memopv8f64, f512mem, v8f32, v8f64,
2880 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2881 EVEX_CD8<64, CD8VF>;
2883 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2884 memopv4f64, f256mem, v8f64, v8f32,
2885 SSEPackedDouble>, EVEX_V512, TB,
2886 EVEX_CD8<32, CD8VH>;
2887 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2888 (VCVTPS2PDZrm addr:$src)>;
2890 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2891 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2892 (VCVTPD2PSZrr VR512:$src)>;
2894 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2895 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2896 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2898 //===----------------------------------------------------------------------===//
2899 // AVX-512 Vector convert from sign integer to float/double
2900 //===----------------------------------------------------------------------===//
2902 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2903 memopv8i64, i512mem, v16f32, v16i32,
2904 SSEPackedSingle>, EVEX_V512, TB,
2905 EVEX_CD8<32, CD8VF>;
2907 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2908 memopv4i64, i256mem, v8f64, v8i32,
2909 SSEPackedDouble>, EVEX_V512, XS,
2910 EVEX_CD8<32, CD8VH>;
2912 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2913 memopv16f32, f512mem, v16i32, v16f32,
2914 SSEPackedSingle>, EVEX_V512, XS,
2915 EVEX_CD8<32, CD8VF>;
2917 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2918 memopv8f64, f512mem, v8i32, v8f64,
2919 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2920 EVEX_CD8<64, CD8VF>;
2922 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2923 memopv16f32, f512mem, v16i32, v16f32,
2924 SSEPackedSingle>, EVEX_V512, TB,
2925 EVEX_CD8<32, CD8VF>;
2927 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2928 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2929 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2930 (VCVTTPS2UDQZrr VR512:$src)>;
2932 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2933 memopv8f64, f512mem, v8i32, v8f64,
2934 SSEPackedDouble>, EVEX_V512, TB, VEX_W,
2935 EVEX_CD8<64, CD8VF>;
2937 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2938 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2939 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2940 (VCVTTPD2UDQZrr VR512:$src)>;
2942 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2943 memopv4i64, f256mem, v8f64, v8i32,
2944 SSEPackedDouble>, EVEX_V512, XS,
2945 EVEX_CD8<32, CD8VH>;
2947 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2948 memopv16i32, f512mem, v16f32, v16i32,
2949 SSEPackedSingle>, EVEX_V512, XD,
2950 EVEX_CD8<32, CD8VF>;
2952 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2953 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2954 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2957 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2958 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2959 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2960 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2961 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2962 (VCVTDQ2PDZrr VR256X:$src)>;
2963 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2964 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2965 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2966 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2967 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2968 (VCVTUDQ2PDZrr VR256X:$src)>;
2970 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2971 RegisterClass DstRC, PatFrag mem_frag,
2972 X86MemOperand x86memop, Domain d> {
2973 let hasSideEffects = 0 in {
2974 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2975 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2977 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2978 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2979 [], d>, EVEX, EVEX_B, EVEX_RC;
2981 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2982 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2984 } // hasSideEffects = 0
2987 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2988 memopv16f32, f512mem, SSEPackedSingle>, PD,
2989 EVEX_V512, EVEX_CD8<32, CD8VF>;
2990 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2991 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2992 EVEX_V512, EVEX_CD8<64, CD8VF>;
2994 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2995 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2996 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2998 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2999 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3000 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3002 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3003 memopv16f32, f512mem, SSEPackedSingle>,
3004 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3005 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3006 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3007 TB, EVEX_V512, EVEX_CD8<64, CD8VF>;
3009 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3010 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3011 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3013 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3014 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3015 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3017 let Predicates = [HasAVX512] in {
3018 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3019 (VCVTPD2PSZrm addr:$src)>;
3020 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3021 (VCVTPS2PDZrm addr:$src)>;
3024 //===----------------------------------------------------------------------===//
3025 // Half precision conversion instructions
3026 //===----------------------------------------------------------------------===//
3027 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3028 X86MemOperand x86memop> {
3029 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3030 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3032 let hasSideEffects = 0, mayLoad = 1 in
3033 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3034 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3037 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3038 X86MemOperand x86memop> {
3039 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3040 (ins srcRC:$src1, i32i8imm:$src2),
3041 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3043 let hasSideEffects = 0, mayStore = 1 in
3044 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3045 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3046 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3049 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3050 EVEX_CD8<32, CD8VH>;
3051 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3052 EVEX_CD8<32, CD8VH>;
3054 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3055 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3056 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3058 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3059 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3060 (VCVTPH2PSZrr VR256X:$src)>;
3062 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3063 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3064 "ucomiss">, TB, EVEX, VEX_LIG,
3065 EVEX_CD8<32, CD8VT1>;
3066 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3067 "ucomisd">, PD, EVEX,
3068 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3069 let Pattern = []<dag> in {
3070 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3071 "comiss">, TB, EVEX, VEX_LIG,
3072 EVEX_CD8<32, CD8VT1>;
3073 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3074 "comisd">, PD, EVEX,
3075 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3077 let isCodeGenOnly = 1 in {
3078 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3079 load, "ucomiss">, TB, EVEX, VEX_LIG,
3080 EVEX_CD8<32, CD8VT1>;
3081 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3082 load, "ucomisd">, PD, EVEX,
3083 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3085 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3086 load, "comiss">, TB, EVEX, VEX_LIG,
3087 EVEX_CD8<32, CD8VT1>;
3088 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3089 load, "comisd">, PD, EVEX,
3090 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3094 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3095 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3096 X86MemOperand x86memop> {
3097 let hasSideEffects = 0 in {
3098 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3099 (ins RC:$src1, RC:$src2),
3100 !strconcat(OpcodeStr,
3101 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3102 let mayLoad = 1 in {
3103 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3104 (ins RC:$src1, x86memop:$src2),
3105 !strconcat(OpcodeStr,
3106 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3111 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3112 EVEX_CD8<32, CD8VT1>;
3113 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3114 VEX_W, EVEX_CD8<64, CD8VT1>;
3115 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3116 EVEX_CD8<32, CD8VT1>;
3117 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3118 VEX_W, EVEX_CD8<64, CD8VT1>;
3120 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3121 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3122 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3123 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3125 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3126 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3127 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3128 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3130 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3131 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3132 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3133 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3135 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3136 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3137 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3138 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3140 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3141 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3142 RegisterClass RC, X86MemOperand x86memop,
3143 PatFrag mem_frag, ValueType OpVt> {
3144 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3145 !strconcat(OpcodeStr,
3146 " \t{$src, $dst|$dst, $src}"),
3147 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3149 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3150 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3151 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3154 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3155 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3156 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3157 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3158 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3159 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3160 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3161 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3163 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3164 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3165 (VRSQRT14PSZr VR512:$src)>;
3166 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3167 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3168 (VRSQRT14PDZr VR512:$src)>;
3170 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3171 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3172 (VRCP14PSZr VR512:$src)>;
3173 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3174 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3175 (VRCP14PDZr VR512:$src)>;
3177 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3178 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3179 X86MemOperand x86memop> {
3180 let hasSideEffects = 0, Predicates = [HasERI] in {
3181 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3182 (ins RC:$src1, RC:$src2),
3183 !strconcat(OpcodeStr,
3184 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3185 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3186 (ins RC:$src1, RC:$src2),
3187 !strconcat(OpcodeStr,
3188 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3189 []>, EVEX_4V, EVEX_B;
3190 let mayLoad = 1 in {
3191 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3192 (ins RC:$src1, x86memop:$src2),
3193 !strconcat(OpcodeStr,
3194 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3199 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3200 EVEX_CD8<32, CD8VT1>;
3201 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3202 VEX_W, EVEX_CD8<64, CD8VT1>;
3203 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3204 EVEX_CD8<32, CD8VT1>;
3205 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3206 VEX_W, EVEX_CD8<64, CD8VT1>;
3208 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3209 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3211 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3212 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3214 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3215 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3217 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3218 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3220 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3221 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3223 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3224 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3226 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3227 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3229 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3230 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3232 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3233 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3234 RegisterClass RC, X86MemOperand x86memop> {
3235 let hasSideEffects = 0, Predicates = [HasERI] in {
3236 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3237 !strconcat(OpcodeStr,
3238 " \t{$src, $dst|$dst, $src}"),
3240 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3241 !strconcat(OpcodeStr,
3242 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3244 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3245 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3249 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3250 EVEX_V512, EVEX_CD8<32, CD8VF>;
3251 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3252 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3253 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3254 EVEX_V512, EVEX_CD8<32, CD8VF>;
3255 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3256 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3258 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3259 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3260 (VRSQRT28PSZrb VR512:$src)>;
3261 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3262 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3263 (VRSQRT28PDZrb VR512:$src)>;
3265 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3266 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3267 (VRCP28PSZrb VR512:$src)>;
3268 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3269 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3270 (VRCP28PDZrb VR512:$src)>;
3272 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3273 Intrinsic V16F32Int, Intrinsic V8F64Int,
3274 OpndItins itins_s, OpndItins itins_d> {
3275 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3276 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3277 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3281 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3282 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3284 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3285 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3288 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3289 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3293 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3294 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3295 [(set VR512:$dst, (OpNode
3296 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3297 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3299 let isCodeGenOnly = 1 in {
3300 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3301 !strconcat(OpcodeStr,
3302 "ps\t{$src, $dst|$dst, $src}"),
3303 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3305 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3306 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3308 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3309 EVEX_V512, EVEX_CD8<32, CD8VF>;
3310 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3311 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3312 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3313 EVEX, EVEX_V512, VEX_W;
3314 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3315 !strconcat(OpcodeStr,
3316 "pd\t{$src, $dst|$dst, $src}"),
3317 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3318 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3319 } // isCodeGenOnly = 1
3322 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3323 Intrinsic F32Int, Intrinsic F64Int,
3324 OpndItins itins_s, OpndItins itins_d> {
3325 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3326 (ins FR32X:$src1, FR32X:$src2),
3327 !strconcat(OpcodeStr,
3328 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3329 [], itins_s.rr>, XS, EVEX_4V;
3330 let isCodeGenOnly = 1 in
3331 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3332 (ins VR128X:$src1, VR128X:$src2),
3333 !strconcat(OpcodeStr,
3334 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3336 (F32Int VR128X:$src1, VR128X:$src2))],
3337 itins_s.rr>, XS, EVEX_4V;
3338 let mayLoad = 1 in {
3339 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3340 (ins FR32X:$src1, f32mem:$src2),
3341 !strconcat(OpcodeStr,
3342 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3343 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3344 let isCodeGenOnly = 1 in
3345 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3346 (ins VR128X:$src1, ssmem:$src2),
3347 !strconcat(OpcodeStr,
3348 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3350 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3351 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3353 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3354 (ins FR64X:$src1, FR64X:$src2),
3355 !strconcat(OpcodeStr,
3356 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3358 let isCodeGenOnly = 1 in
3359 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3360 (ins VR128X:$src1, VR128X:$src2),
3361 !strconcat(OpcodeStr,
3362 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3364 (F64Int VR128X:$src1, VR128X:$src2))],
3365 itins_s.rr>, XD, EVEX_4V, VEX_W;
3366 let mayLoad = 1 in {
3367 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3368 (ins FR64X:$src1, f64mem:$src2),
3369 !strconcat(OpcodeStr,
3370 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3371 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3372 let isCodeGenOnly = 1 in
3373 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3374 (ins VR128X:$src1, sdmem:$src2),
3375 !strconcat(OpcodeStr,
3376 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3378 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3379 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3384 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3385 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3386 SSE_SQRTSS, SSE_SQRTSD>,
3387 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3388 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3389 SSE_SQRTPS, SSE_SQRTPD>;
3391 let Predicates = [HasAVX512] in {
3392 def : Pat<(f32 (fsqrt FR32X:$src)),
3393 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3394 def : Pat<(f32 (fsqrt (load addr:$src))),
3395 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3396 Requires<[OptForSize]>;
3397 def : Pat<(f64 (fsqrt FR64X:$src)),
3398 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3399 def : Pat<(f64 (fsqrt (load addr:$src))),
3400 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3401 Requires<[OptForSize]>;
3403 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3404 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3405 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3406 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3407 Requires<[OptForSize]>;
3409 def : Pat<(f32 (X86frcp FR32X:$src)),
3410 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3411 def : Pat<(f32 (X86frcp (load addr:$src))),
3412 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3413 Requires<[OptForSize]>;
3415 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3416 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3417 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3419 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3420 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3422 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3423 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3424 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3426 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3427 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3431 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3432 X86MemOperand x86memop, RegisterClass RC,
3433 PatFrag mem_frag32, PatFrag mem_frag64,
3434 Intrinsic V4F32Int, Intrinsic V2F64Int,
3436 let ExeDomain = SSEPackedSingle in {
3437 // Intrinsic operation, reg.
3438 // Vector intrinsic operation, reg
3439 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3440 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3441 !strconcat(OpcodeStr,
3442 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3443 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3445 // Vector intrinsic operation, mem
3446 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3447 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3448 !strconcat(OpcodeStr,
3449 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3451 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3452 EVEX_CD8<32, VForm>;
3453 } // ExeDomain = SSEPackedSingle
3455 let ExeDomain = SSEPackedDouble in {
3456 // Vector intrinsic operation, reg
3457 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3458 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3459 !strconcat(OpcodeStr,
3460 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3461 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3463 // Vector intrinsic operation, mem
3464 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3465 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3466 !strconcat(OpcodeStr,
3467 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3469 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3470 EVEX_CD8<64, VForm>;
3471 } // ExeDomain = SSEPackedDouble
3474 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3478 let ExeDomain = GenericDomain in {
3480 let hasSideEffects = 0 in
3481 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3482 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3483 !strconcat(OpcodeStr,
3484 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3487 // Intrinsic operation, reg.
3488 let isCodeGenOnly = 1 in
3489 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3490 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3491 !strconcat(OpcodeStr,
3492 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3493 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3495 // Intrinsic operation, mem.
3496 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3497 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3498 !strconcat(OpcodeStr,
3499 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3500 [(set VR128X:$dst, (F32Int VR128X:$src1,
3501 sse_load_f32:$src2, imm:$src3))]>,
3502 EVEX_CD8<32, CD8VT1>;
3505 let hasSideEffects = 0 in
3506 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3507 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3508 !strconcat(OpcodeStr,
3509 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3512 // Intrinsic operation, reg.
3513 let isCodeGenOnly = 1 in
3514 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3515 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3516 !strconcat(OpcodeStr,
3517 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3518 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3521 // Intrinsic operation, mem.
3522 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3523 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3524 !strconcat(OpcodeStr,
3525 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3527 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3528 VEX_W, EVEX_CD8<64, CD8VT1>;
3529 } // ExeDomain = GenericDomain
3532 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3533 X86MemOperand x86memop, RegisterClass RC,
3534 PatFrag mem_frag, Domain d> {
3535 let ExeDomain = d in {
3536 // Intrinsic operation, reg.
3537 // Vector intrinsic operation, reg
3538 def r : AVX512AIi8<opc, MRMSrcReg,
3539 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3540 !strconcat(OpcodeStr,
3541 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3544 // Vector intrinsic operation, mem
3545 def m : AVX512AIi8<opc, MRMSrcMem,
3546 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3547 !strconcat(OpcodeStr,
3548 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3554 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3555 memopv16f32, SSEPackedSingle>, EVEX_V512,
3556 EVEX_CD8<32, CD8VF>;
3558 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3559 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3561 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3564 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3565 memopv8f64, SSEPackedDouble>, EVEX_V512,
3566 VEX_W, EVEX_CD8<64, CD8VF>;
3568 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3569 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3571 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3573 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3574 Operand x86memop, RegisterClass RC, Domain d> {
3575 let ExeDomain = d in {
3576 def r : AVX512AIi8<opc, MRMSrcReg,
3577 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3578 !strconcat(OpcodeStr,
3579 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3582 def m : AVX512AIi8<opc, MRMSrcMem,
3583 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3584 !strconcat(OpcodeStr,
3585 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3590 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3591 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3593 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3594 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3596 def : Pat<(ffloor FR32X:$src),
3597 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3598 def : Pat<(f64 (ffloor FR64X:$src)),
3599 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3600 def : Pat<(f32 (fnearbyint FR32X:$src)),
3601 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3602 def : Pat<(f64 (fnearbyint FR64X:$src)),
3603 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3604 def : Pat<(f32 (fceil FR32X:$src)),
3605 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3606 def : Pat<(f64 (fceil FR64X:$src)),
3607 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3608 def : Pat<(f32 (frint FR32X:$src)),
3609 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3610 def : Pat<(f64 (frint FR64X:$src)),
3611 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3612 def : Pat<(f32 (ftrunc FR32X:$src)),
3613 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3614 def : Pat<(f64 (ftrunc FR64X:$src)),
3615 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3617 def : Pat<(v16f32 (ffloor VR512:$src)),
3618 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3619 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3620 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3621 def : Pat<(v16f32 (fceil VR512:$src)),
3622 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3623 def : Pat<(v16f32 (frint VR512:$src)),
3624 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3625 def : Pat<(v16f32 (ftrunc VR512:$src)),
3626 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3628 def : Pat<(v8f64 (ffloor VR512:$src)),
3629 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3630 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3631 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3632 def : Pat<(v8f64 (fceil VR512:$src)),
3633 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3634 def : Pat<(v8f64 (frint VR512:$src)),
3635 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3636 def : Pat<(v8f64 (ftrunc VR512:$src)),
3637 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3639 //-------------------------------------------------
3640 // Integer truncate and extend operations
3641 //-------------------------------------------------
3643 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3644 RegisterClass dstRC, RegisterClass srcRC,
3645 RegisterClass KRC, X86MemOperand x86memop> {
3646 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3648 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3651 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3652 (ins KRC:$mask, srcRC:$src),
3653 !strconcat(OpcodeStr,
3654 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3657 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3658 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3661 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3662 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3663 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3664 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3665 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3666 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3667 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3668 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3669 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3670 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3671 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3672 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3673 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3674 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3675 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3676 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3677 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3678 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3679 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3680 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3681 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3682 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3683 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3684 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3685 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3686 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3687 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3688 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3689 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3690 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3692 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3693 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3694 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3695 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3696 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3698 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3699 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3700 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3701 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3702 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3703 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3704 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3705 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3708 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3709 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3710 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3712 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3714 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3715 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3716 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3717 (ins x86memop:$src),
3718 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3720 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3724 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3725 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3727 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3728 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3730 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3731 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3732 EVEX_CD8<16, CD8VH>;
3733 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3734 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3735 EVEX_CD8<16, CD8VQ>;
3736 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3737 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3738 EVEX_CD8<32, CD8VH>;
3740 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3741 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3743 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3744 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3746 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3747 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3748 EVEX_CD8<16, CD8VH>;
3749 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3750 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3751 EVEX_CD8<16, CD8VQ>;
3752 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3753 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3754 EVEX_CD8<32, CD8VH>;
3756 //===----------------------------------------------------------------------===//
3757 // GATHER - SCATTER Operations
3759 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3760 RegisterClass RC, X86MemOperand memop> {
3762 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3763 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3764 (ins RC:$src1, KRC:$mask, memop:$src2),
3765 !strconcat(OpcodeStr,
3766 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3769 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3770 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3771 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3772 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3774 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3775 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3776 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3777 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3779 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3780 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3781 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3782 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3784 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3785 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3786 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3787 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3789 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3790 RegisterClass RC, X86MemOperand memop> {
3791 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3792 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3793 (ins memop:$dst, KRC:$mask, RC:$src2),
3794 !strconcat(OpcodeStr,
3795 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3799 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3800 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3801 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3802 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3804 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3806 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3807 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3809 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3810 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3811 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3812 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3814 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3815 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3816 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3817 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3819 //===----------------------------------------------------------------------===//
3820 // VSHUFPS - VSHUFPD Operations
3822 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3823 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3825 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3826 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3827 !strconcat(OpcodeStr,
3828 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3829 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3830 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3831 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3832 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3833 (ins RC:$src1, RC:$src2, i8imm:$src3),
3834 !strconcat(OpcodeStr,
3835 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3836 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3837 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3838 EVEX_4V, Sched<[WriteShuffle]>;
3841 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3842 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3843 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3844 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3846 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3847 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3848 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3849 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3850 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3852 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3853 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3854 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3855 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3856 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3858 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3859 X86MemOperand x86memop> {
3860 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3861 (ins RC:$src1, RC:$src2, i8imm:$src3),
3862 !strconcat(OpcodeStr,
3863 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3866 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3867 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3868 !strconcat(OpcodeStr,
3869 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3872 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3873 EVEX_V512, EVEX_CD8<32, CD8VF>;
3874 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3875 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3877 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3878 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3879 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3880 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3881 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3882 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3883 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3884 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3886 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3887 X86MemOperand x86memop> {
3888 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3889 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3891 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3892 (ins x86memop:$src),
3893 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3897 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3898 EVEX_CD8<32, CD8VF>;
3899 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3900 EVEX_CD8<64, CD8VF>;
3902 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3903 (v16i32 immAllZerosV), (i16 -1))),
3904 (VPABSDrr VR512:$src)>;
3905 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3906 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3907 (VPABSQrr VR512:$src)>;
3909 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3910 RegisterClass RC, RegisterClass KRC,
3911 X86MemOperand x86memop,
3912 X86MemOperand x86scalar_mop, string BrdcstStr> {
3913 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3915 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3917 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3918 (ins x86memop:$src),
3919 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3921 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3922 (ins x86scalar_mop:$src),
3923 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3924 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3926 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3927 (ins KRC:$mask, RC:$src),
3928 !strconcat(OpcodeStr,
3929 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3931 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3932 (ins KRC:$mask, x86memop:$src),
3933 !strconcat(OpcodeStr,
3934 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3936 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3937 (ins KRC:$mask, x86scalar_mop:$src),
3938 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3939 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3941 []>, EVEX, EVEX_KZ, EVEX_B;
3943 let Constraints = "$src1 = $dst" in {
3944 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3945 (ins RC:$src1, KRC:$mask, RC:$src2),
3946 !strconcat(OpcodeStr,
3947 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3949 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3950 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3951 !strconcat(OpcodeStr,
3952 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3954 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3955 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3956 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3957 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3958 []>, EVEX, EVEX_K, EVEX_B;
3962 let Predicates = [HasCDI] in {
3963 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3964 i512mem, i32mem, "{1to16}">,
3965 EVEX_V512, EVEX_CD8<32, CD8VF>;
3968 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3969 i512mem, i64mem, "{1to8}">,
3970 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3974 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3976 (VPCONFLICTDrrk VR512:$src1,
3977 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3979 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3981 (VPCONFLICTQrrk VR512:$src1,
3982 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;