1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
755 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
756 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
758 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
759 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
760 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
761 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
763 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
764 (COPY_TO_REGCLASS (VPCMPGTDZrr
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
766 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
768 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
769 (COPY_TO_REGCLASS (VPCMPEQDZrr
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
771 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
773 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
774 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
775 SDNode OpNode, ValueType vt, Operand CC, string asm,
777 def rri : AVX512AIi8<opc, MRMSrcReg,
778 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
779 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
780 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
784 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
785 // Accept explicit immediate argument form instead of comparison code.
786 let isAsmParserOnly = 1, hasSideEffects = 0 in {
787 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
788 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
789 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
790 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
791 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
792 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
796 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
797 X86cmpm, v16i32, AVXCC,
798 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 EVEX_V512, EVEX_CD8<32, CD8VF>;
801 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
802 X86cmpmu, v16i32, AVXCC,
803 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
805 EVEX_V512, EVEX_CD8<32, CD8VF>;
807 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
808 X86cmpm, v8i64, AVXCC,
809 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
810 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
811 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
812 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
813 X86cmpmu, v8i64, AVXCC,
814 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
815 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
816 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
818 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
819 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
820 X86MemOperand x86memop, ValueType vt,
821 string suffix, Domain d> {
822 def rri : AVX512PIi8<0xC2, MRMSrcReg,
823 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
824 !strconcat("vcmp${cc}", suffix,
825 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
826 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
827 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
828 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
829 !strconcat("vcmp${cc}", suffix,
830 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
832 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
834 !strconcat("vcmp${cc}", suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
837 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
839 // Accept explicit immediate argument form instead of comparison code.
840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
841 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
842 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
843 !strconcat("vcmp", suffix,
844 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
845 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
846 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
852 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
853 "ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512,
855 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
856 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
859 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
860 (COPY_TO_REGCLASS (VCMPPSZrri
861 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
862 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
864 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
865 (COPY_TO_REGCLASS (VPCMPDZrri
866 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
867 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
869 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
870 (COPY_TO_REGCLASS (VPCMPUDZrri
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
872 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
875 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
876 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
878 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
879 (I8Imm imm:$cc)), GR16)>;
881 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
882 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
884 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
885 (I8Imm imm:$cc)), GR8)>;
887 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
888 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
890 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
891 (I8Imm imm:$cc)), GR16)>;
893 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
894 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
896 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
897 (I8Imm imm:$cc)), GR8)>;
899 // Mask register copy, including
900 // - copy between mask registers
901 // - load/store mask registers
902 // - copy from GPR to mask register and vice versa
904 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
905 string OpcodeStr, RegisterClass KRC,
906 ValueType vt, X86MemOperand x86memop> {
907 let hasSideEffects = 0 in {
908 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
909 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
911 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
913 [(set KRC:$dst, (vt (load addr:$src)))]>;
915 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
920 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
922 RegisterClass KRC, RegisterClass GRC> {
923 let hasSideEffects = 0 in {
924 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
926 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
927 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 let Predicates = [HasAVX512] in {
932 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
934 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
938 let Predicates = [HasAVX512] in {
939 // GR16 from/to 16-bit mask
940 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
941 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
942 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
943 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
945 // Store kreg in memory
946 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
947 (KMOVWmk addr:$dst, VK16:$src)>;
949 def : Pat<(store VK8:$src, addr:$dst),
950 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
952 def : Pat<(i1 (load addr:$src)),
953 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
955 def : Pat<(v8i1 (load addr:$src)),
956 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
958 def : Pat<(i1 (trunc (i32 GR32:$src))),
959 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
961 def : Pat<(i1 (trunc (i8 GR8:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
965 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
966 def : Pat<(i8 (zext VK1:$src)),
968 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
969 def : Pat<(i64 (zext VK1:$src)),
970 (SUBREG_TO_REG (i64 0),
971 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
974 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
975 let Predicates = [HasAVX512] in {
976 // GR from/to 8-bit mask without native support
977 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
979 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
981 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
983 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
986 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
987 (COPY_TO_REGCLASS VK16:$src, VK1)>;
988 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
989 (COPY_TO_REGCLASS VK8:$src, VK1)>;
993 // Mask unary operation
995 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
996 RegisterClass KRC, SDPatternOperator OpNode> {
997 let Predicates = [HasAVX512] in
998 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
999 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1000 [(set KRC:$dst, (OpNode KRC:$src))]>;
1003 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1004 SDPatternOperator OpNode> {
1005 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1009 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1011 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1012 let Predicates = [HasAVX512] in
1013 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1015 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1016 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1018 defm : avx512_mask_unop_int<"knot", "KNOT">;
1020 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1021 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1022 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1024 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1025 def : Pat<(not VK8:$src),
1027 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1029 // Mask binary operation
1030 // - KAND, KANDN, KOR, KXNOR, KXOR
1031 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1032 RegisterClass KRC, SDPatternOperator OpNode> {
1033 let Predicates = [HasAVX512] in
1034 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1035 !strconcat(OpcodeStr,
1036 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1040 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1041 SDPatternOperator OpNode> {
1042 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1046 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1047 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1049 let isCommutable = 1 in {
1050 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1051 let isCommutable = 0 in
1052 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1053 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1054 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1055 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1058 def : Pat<(xor VK1:$src1, VK1:$src2),
1059 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1060 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1062 def : Pat<(or VK1:$src1, VK1:$src2),
1063 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1064 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1066 def : Pat<(not VK1:$src),
1067 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1068 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1069 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1071 def : Pat<(and VK1:$src1, VK1:$src2),
1072 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1073 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1075 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1076 let Predicates = [HasAVX512] in
1077 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1078 (i16 GR16:$src1), (i16 GR16:$src2)),
1079 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1080 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1081 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1084 defm : avx512_mask_binop_int<"kand", "KAND">;
1085 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1086 defm : avx512_mask_binop_int<"kor", "KOR">;
1087 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1088 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1090 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1091 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1092 let Predicates = [HasAVX512] in
1093 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1095 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1096 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1099 defm : avx512_binop_pat<and, KANDWrr>;
1100 defm : avx512_binop_pat<andn, KANDNWrr>;
1101 defm : avx512_binop_pat<or, KORWrr>;
1102 defm : avx512_binop_pat<xnor, KXNORWrr>;
1103 defm : avx512_binop_pat<xor, KXORWrr>;
1106 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1107 RegisterClass KRC> {
1108 let Predicates = [HasAVX512] in
1109 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1110 !strconcat(OpcodeStr,
1111 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1114 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1115 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1119 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1120 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1121 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1122 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1125 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1126 let Predicates = [HasAVX512] in
1127 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1128 (i16 GR16:$src1), (i16 GR16:$src2)),
1129 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1130 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1131 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1133 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1136 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1138 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1139 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1140 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1141 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1144 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1145 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1149 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1151 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1152 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1153 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1156 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1158 let Predicates = [HasAVX512] in
1159 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1160 !strconcat(OpcodeStr,
1161 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1162 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1165 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1167 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1171 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1172 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1174 // Mask setting all 0s or 1s
1175 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1176 let Predicates = [HasAVX512] in
1177 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1178 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1179 [(set KRC:$dst, (VT Val))]>;
1182 multiclass avx512_mask_setop_w<PatFrag Val> {
1183 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1184 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1187 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1188 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1190 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1191 let Predicates = [HasAVX512] in {
1192 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1193 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1194 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1195 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1196 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1198 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1199 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1201 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1202 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1204 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1205 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1207 //===----------------------------------------------------------------------===//
1208 // AVX-512 - Aligned and unaligned load and store
1211 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1212 X86MemOperand x86memop, PatFrag ld_frag,
1213 string asm, Domain d, bit IsReMaterializable = 1> {
1214 let hasSideEffects = 0 in
1215 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1216 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1218 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1219 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1220 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1221 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1222 let Constraints = "$src1 = $dst" in {
1223 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1224 (ins RC:$src1, KRC:$mask, RC:$src2),
1226 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1228 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1229 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1231 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1232 [], d>, EVEX, EVEX_K;
1236 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1237 "vmovaps", SSEPackedSingle>,
1238 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1239 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1240 "vmovapd", SSEPackedDouble>,
1241 PD, EVEX_V512, VEX_W,
1242 EVEX_CD8<64, CD8VF>;
1243 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1244 "vmovups", SSEPackedSingle>,
1245 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1246 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1247 "vmovupd", SSEPackedDouble, 0>,
1248 PD, EVEX_V512, VEX_W,
1249 EVEX_CD8<64, CD8VF>;
1250 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1251 "vmovaps\t{$src, $dst|$dst, $src}",
1252 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1253 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1254 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1255 "vmovapd\t{$src, $dst|$dst, $src}",
1256 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1257 SSEPackedDouble>, EVEX, EVEX_V512,
1258 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1259 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1260 "vmovups\t{$src, $dst|$dst, $src}",
1261 [(store (v16f32 VR512:$src), addr:$dst)],
1262 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1263 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1264 "vmovupd\t{$src, $dst|$dst, $src}",
1265 [(store (v8f64 VR512:$src), addr:$dst)],
1266 SSEPackedDouble>, EVEX, EVEX_V512,
1267 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1269 let hasSideEffects = 0 in {
1270 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1272 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1274 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1276 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1277 EVEX, EVEX_V512, VEX_W;
1278 let mayStore = 1 in {
1279 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1280 (ins i512mem:$dst, VR512:$src),
1281 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1282 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1283 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1284 (ins i512mem:$dst, VR512:$src),
1285 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1286 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1288 let mayLoad = 1 in {
1289 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1291 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1292 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1293 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1295 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1296 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1300 // 512-bit aligned load/store
1301 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1302 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1304 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1305 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1306 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1307 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1309 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1310 RegisterClass RC, RegisterClass KRC,
1311 PatFrag ld_frag, X86MemOperand x86memop> {
1312 let hasSideEffects = 0 in
1313 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1314 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1315 let canFoldAsLoad = 1 in
1316 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1317 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1318 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1320 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1321 (ins x86memop:$dst, VR512:$src),
1322 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1323 let Constraints = "$src1 = $dst" in {
1324 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1325 (ins RC:$src1, KRC:$mask, RC:$src2),
1327 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1329 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1330 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1332 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1335 def rrkz : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1336 (ins KRC:$mask, RC:$src),
1338 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), []>,
1342 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1343 memopv16i32, i512mem>,
1344 EVEX_V512, EVEX_CD8<32, CD8VF>;
1345 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1346 memopv8i64, i512mem>,
1347 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1349 // 512-bit unaligned load/store
1350 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1351 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1353 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1354 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1355 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1356 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1358 let AddedComplexity = 20 in {
1359 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1360 (bc_v8i64 (v16i32 immAllZerosV)))),
1361 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1363 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1364 (v8i64 VR512:$src))),
1365 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1368 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1369 (v16i32 immAllZerosV))),
1370 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1372 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1373 (v16i32 VR512:$src))),
1374 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1376 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1377 (v16f32 VR512:$src2))),
1378 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1379 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1380 (v8f64 VR512:$src2))),
1381 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1382 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1383 (v16i32 VR512:$src2))),
1384 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1385 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1386 (v8i64 VR512:$src2))),
1387 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1389 // Move Int Doubleword to Packed Double Int
1391 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1392 "vmovd\t{$src, $dst|$dst, $src}",
1394 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1396 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1397 "vmovd\t{$src, $dst|$dst, $src}",
1399 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1400 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1401 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1402 "vmovq\t{$src, $dst|$dst, $src}",
1404 (v2i64 (scalar_to_vector GR64:$src)))],
1405 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1406 let isCodeGenOnly = 1 in {
1407 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1408 "vmovq\t{$src, $dst|$dst, $src}",
1409 [(set FR64:$dst, (bitconvert GR64:$src))],
1410 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1411 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1412 "vmovq\t{$src, $dst|$dst, $src}",
1413 [(set GR64:$dst, (bitconvert FR64:$src))],
1414 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1416 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1417 "vmovq\t{$src, $dst|$dst, $src}",
1418 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1419 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1420 EVEX_CD8<64, CD8VT1>;
1422 // Move Int Doubleword to Single Scalar
1424 let isCodeGenOnly = 1 in {
1425 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1426 "vmovd\t{$src, $dst|$dst, $src}",
1427 [(set FR32X:$dst, (bitconvert GR32:$src))],
1428 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1430 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1431 "vmovd\t{$src, $dst|$dst, $src}",
1432 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1433 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1436 // Move doubleword from xmm register to r/m32
1438 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1439 "vmovd\t{$src, $dst|$dst, $src}",
1440 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1441 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1443 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1444 (ins i32mem:$dst, VR128X:$src),
1445 "vmovd\t{$src, $dst|$dst, $src}",
1446 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1447 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1448 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1450 // Move quadword from xmm1 register to r/m64
1452 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1453 "vmovq\t{$src, $dst|$dst, $src}",
1454 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1456 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1457 Requires<[HasAVX512, In64BitMode]>;
1459 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1460 (ins i64mem:$dst, VR128X:$src),
1461 "vmovq\t{$src, $dst|$dst, $src}",
1462 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1463 addr:$dst)], IIC_SSE_MOVDQ>,
1464 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1465 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1467 // Move Scalar Single to Double Int
1469 let isCodeGenOnly = 1 in {
1470 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1472 "vmovd\t{$src, $dst|$dst, $src}",
1473 [(set GR32:$dst, (bitconvert FR32X:$src))],
1474 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1475 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1476 (ins i32mem:$dst, FR32X:$src),
1477 "vmovd\t{$src, $dst|$dst, $src}",
1478 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1479 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1482 // Move Quadword Int to Packed Quadword Int
1484 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1486 "vmovq\t{$src, $dst|$dst, $src}",
1488 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1489 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1491 //===----------------------------------------------------------------------===//
1492 // AVX-512 MOVSS, MOVSD
1493 //===----------------------------------------------------------------------===//
1495 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1496 SDNode OpNode, ValueType vt,
1497 X86MemOperand x86memop, PatFrag mem_pat> {
1498 let hasSideEffects = 0 in {
1499 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1500 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1501 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1502 (scalar_to_vector RC:$src2))))],
1503 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1504 let Constraints = "$src1 = $dst" in
1505 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1506 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1508 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1509 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1510 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1511 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1512 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1514 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1515 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1516 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1518 } //hasSideEffects = 0
1521 let ExeDomain = SSEPackedSingle in
1522 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1523 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1525 let ExeDomain = SSEPackedDouble in
1526 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1527 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1529 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1530 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1531 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1533 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1534 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1535 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1537 // For the disassembler
1538 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1539 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1540 (ins VR128X:$src1, FR32X:$src2),
1541 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1543 XS, EVEX_4V, VEX_LIG;
1544 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1545 (ins VR128X:$src1, FR64X:$src2),
1546 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1548 XD, EVEX_4V, VEX_LIG, VEX_W;
1551 let Predicates = [HasAVX512] in {
1552 let AddedComplexity = 15 in {
1553 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1554 // MOVS{S,D} to the lower bits.
1555 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1556 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1557 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1558 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1559 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1560 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1561 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1562 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1564 // Move low f32 and clear high bits.
1565 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1566 (SUBREG_TO_REG (i32 0),
1567 (VMOVSSZrr (v4f32 (V_SET0)),
1568 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1569 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1570 (SUBREG_TO_REG (i32 0),
1571 (VMOVSSZrr (v4i32 (V_SET0)),
1572 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1575 let AddedComplexity = 20 in {
1576 // MOVSSrm zeros the high parts of the register; represent this
1577 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1578 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1579 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1580 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1581 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1582 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1583 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1585 // MOVSDrm zeros the high parts of the register; represent this
1586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1587 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1588 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1589 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1590 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1591 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1592 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1593 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1594 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1595 def : Pat<(v2f64 (X86vzload addr:$src)),
1596 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1598 // Represent the same patterns above but in the form they appear for
1600 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1601 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1602 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1603 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1604 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1605 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1606 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1607 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1608 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1610 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1611 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1612 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1613 FR32X:$src)), sub_xmm)>;
1614 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1615 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1616 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1617 FR64X:$src)), sub_xmm)>;
1618 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1619 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1620 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1622 // Move low f64 and clear high bits.
1623 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1624 (SUBREG_TO_REG (i32 0),
1625 (VMOVSDZrr (v2f64 (V_SET0)),
1626 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1628 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1629 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1630 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1632 // Extract and store.
1633 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1635 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1636 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1638 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1640 // Shuffle with VMOVSS
1641 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1642 (VMOVSSZrr (v4i32 VR128X:$src1),
1643 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1644 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1645 (VMOVSSZrr (v4f32 VR128X:$src1),
1646 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1649 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1650 (SUBREG_TO_REG (i32 0),
1651 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1652 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1654 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1655 (SUBREG_TO_REG (i32 0),
1656 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1657 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1660 // Shuffle with VMOVSD
1661 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1662 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1663 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1664 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1665 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1666 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1667 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1668 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1671 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1672 (SUBREG_TO_REG (i32 0),
1673 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1674 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1676 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1677 (SUBREG_TO_REG (i32 0),
1678 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1679 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1682 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1683 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1684 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1685 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1686 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1687 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1688 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1689 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1692 let AddedComplexity = 15 in
1693 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1695 "vmovq\t{$src, $dst|$dst, $src}",
1696 [(set VR128X:$dst, (v2i64 (X86vzmovl
1697 (v2i64 VR128X:$src))))],
1698 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1700 let AddedComplexity = 20 in
1701 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1703 "vmovq\t{$src, $dst|$dst, $src}",
1704 [(set VR128X:$dst, (v2i64 (X86vzmovl
1705 (loadv2i64 addr:$src))))],
1706 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1707 EVEX_CD8<8, CD8VT8>;
1709 let Predicates = [HasAVX512] in {
1710 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1711 let AddedComplexity = 20 in {
1712 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1713 (VMOVDI2PDIZrm addr:$src)>;
1714 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1715 (VMOV64toPQIZrr GR64:$src)>;
1716 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1717 (VMOVDI2PDIZrr GR32:$src)>;
1719 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1720 (VMOVDI2PDIZrm addr:$src)>;
1721 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1722 (VMOVDI2PDIZrm addr:$src)>;
1723 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1724 (VMOVZPQILo2PQIZrm addr:$src)>;
1725 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1726 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1727 def : Pat<(v2i64 (X86vzload addr:$src)),
1728 (VMOVZPQILo2PQIZrm addr:$src)>;
1731 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1732 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1733 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1734 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1735 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1736 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1737 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1740 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1741 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1743 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1744 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1746 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1747 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1749 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1750 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1752 //===----------------------------------------------------------------------===//
1753 // AVX-512 - Integer arithmetic
1755 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1756 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1757 X86MemOperand x86memop, PatFrag scalar_mfrag,
1758 X86MemOperand x86scalar_mop, string BrdcstStr,
1759 OpndItins itins, bit IsCommutable = 0> {
1760 let isCommutable = IsCommutable in
1761 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1762 (ins RC:$src1, RC:$src2),
1763 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1764 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1766 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1767 (ins RC:$src1, x86memop:$src2),
1768 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1769 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1771 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1772 (ins RC:$src1, x86scalar_mop:$src2),
1773 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1774 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1775 [(set RC:$dst, (OpNode RC:$src1,
1776 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1777 itins.rm>, EVEX_4V, EVEX_B;
1779 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1780 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1781 PatFrag memop_frag, X86MemOperand x86memop,
1783 bit IsCommutable = 0> {
1784 let isCommutable = IsCommutable in
1785 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1786 (ins RC:$src1, RC:$src2),
1787 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1788 []>, EVEX_4V, VEX_W;
1789 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1790 (ins RC:$src1, x86memop:$src2),
1791 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1792 []>, EVEX_4V, VEX_W;
1795 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1796 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1797 EVEX_V512, EVEX_CD8<32, CD8VF>;
1799 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1800 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1801 EVEX_V512, EVEX_CD8<32, CD8VF>;
1803 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1804 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1805 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1807 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1808 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1809 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1811 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1812 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1813 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1815 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1816 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1817 EVEX_V512, EVEX_CD8<64, CD8VF>;
1819 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1820 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1821 EVEX_CD8<64, CD8VF>;
1823 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1824 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1826 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1827 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1828 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1829 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1830 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1831 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1833 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1834 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1835 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1836 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1837 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1838 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1840 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1841 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1842 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1843 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1844 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1845 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1847 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1848 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1849 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1850 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1851 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1852 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1854 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1855 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1856 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1857 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1858 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1859 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1861 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1862 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1863 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1864 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1865 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1866 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1867 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1868 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1869 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1870 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1871 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1872 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1873 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1874 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1875 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1876 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1877 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1878 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1879 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1880 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1881 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1882 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1883 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1884 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1885 //===----------------------------------------------------------------------===//
1886 // AVX-512 - Unpack Instructions
1887 //===----------------------------------------------------------------------===//
1889 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1890 PatFrag mem_frag, RegisterClass RC,
1891 X86MemOperand x86memop, string asm,
1893 def rr : AVX512PI<opc, MRMSrcReg,
1894 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1896 (vt (OpNode RC:$src1, RC:$src2)))],
1898 def rm : AVX512PI<opc, MRMSrcMem,
1899 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1901 (vt (OpNode RC:$src1,
1902 (bitconvert (mem_frag addr:$src2)))))],
1906 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1907 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1908 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1909 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1910 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1911 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1912 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1913 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1914 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1915 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1916 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1917 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1919 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1920 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1921 X86MemOperand x86memop> {
1922 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1923 (ins RC:$src1, RC:$src2),
1924 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1925 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1926 IIC_SSE_UNPCK>, EVEX_4V;
1927 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1928 (ins RC:$src1, x86memop:$src2),
1929 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1930 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1931 (bitconvert (memop_frag addr:$src2)))))],
1932 IIC_SSE_UNPCK>, EVEX_4V;
1934 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1935 VR512, memopv16i32, i512mem>, EVEX_V512,
1936 EVEX_CD8<32, CD8VF>;
1937 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1938 VR512, memopv8i64, i512mem>, EVEX_V512,
1939 VEX_W, EVEX_CD8<64, CD8VF>;
1940 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1941 VR512, memopv16i32, i512mem>, EVEX_V512,
1942 EVEX_CD8<32, CD8VF>;
1943 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1944 VR512, memopv8i64, i512mem>, EVEX_V512,
1945 VEX_W, EVEX_CD8<64, CD8VF>;
1946 //===----------------------------------------------------------------------===//
1950 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1951 SDNode OpNode, PatFrag mem_frag,
1952 X86MemOperand x86memop, ValueType OpVT> {
1953 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1954 (ins RC:$src1, i8imm:$src2),
1955 !strconcat(OpcodeStr,
1956 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1958 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1960 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1961 (ins x86memop:$src1, i8imm:$src2),
1962 !strconcat(OpcodeStr,
1963 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1965 (OpVT (OpNode (mem_frag addr:$src1),
1966 (i8 imm:$src2))))]>, EVEX;
1969 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1970 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1972 let ExeDomain = SSEPackedSingle in
1973 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1974 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1975 EVEX_CD8<32, CD8VF>;
1976 let ExeDomain = SSEPackedDouble in
1977 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1978 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1979 VEX_W, EVEX_CD8<32, CD8VF>;
1981 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1982 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1983 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1984 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1986 //===----------------------------------------------------------------------===//
1987 // AVX-512 Logical Instructions
1988 //===----------------------------------------------------------------------===//
1990 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1991 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1992 EVEX_V512, EVEX_CD8<32, CD8VF>;
1993 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1994 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1995 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1996 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1997 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1998 EVEX_V512, EVEX_CD8<32, CD8VF>;
1999 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
2000 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2001 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2002 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
2003 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2004 EVEX_V512, EVEX_CD8<32, CD8VF>;
2005 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2006 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2007 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2008 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2009 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2010 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2011 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2012 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2013 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2015 //===----------------------------------------------------------------------===//
2016 // AVX-512 FP arithmetic
2017 //===----------------------------------------------------------------------===//
2019 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2021 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2022 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2023 EVEX_CD8<32, CD8VT1>;
2024 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2025 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2026 EVEX_CD8<64, CD8VT1>;
2029 let isCommutable = 1 in {
2030 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2031 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2032 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2033 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2035 let isCommutable = 0 in {
2036 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2037 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2040 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2041 RegisterClass RC, ValueType vt,
2042 X86MemOperand x86memop, PatFrag mem_frag,
2043 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2045 Domain d, OpndItins itins, bit commutable> {
2046 let isCommutable = commutable in
2047 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2048 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2049 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2051 let mayLoad = 1 in {
2052 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2053 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2054 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2055 itins.rm, d>, EVEX_4V;
2056 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2057 (ins RC:$src1, x86scalar_mop:$src2),
2058 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2059 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2060 [(set RC:$dst, (OpNode RC:$src1,
2061 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2062 itins.rm, d>, EVEX_4V, EVEX_B;
2066 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2067 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2068 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2070 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2071 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2072 SSE_ALU_ITINS_P.d, 1>,
2073 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2075 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2076 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2077 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2078 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2079 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2080 SSE_ALU_ITINS_P.d, 1>,
2081 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2083 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2084 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2085 SSE_ALU_ITINS_P.s, 1>,
2086 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2087 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2088 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2089 SSE_ALU_ITINS_P.s, 1>,
2090 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2092 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2093 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2094 SSE_ALU_ITINS_P.d, 1>,
2095 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2096 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2097 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2098 SSE_ALU_ITINS_P.d, 1>,
2099 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2101 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2102 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2103 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2104 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2105 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2106 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2108 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2109 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2110 SSE_ALU_ITINS_P.d, 0>,
2111 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2112 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2113 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2114 SSE_ALU_ITINS_P.d, 0>,
2115 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2117 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2118 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2119 (i16 -1), FROUND_CURRENT)),
2120 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2122 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2123 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2124 (i8 -1), FROUND_CURRENT)),
2125 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2127 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2128 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2129 (i16 -1), FROUND_CURRENT)),
2130 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2132 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2133 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2134 (i8 -1), FROUND_CURRENT)),
2135 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2136 //===----------------------------------------------------------------------===//
2137 // AVX-512 VPTESTM instructions
2138 //===----------------------------------------------------------------------===//
2140 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2141 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2142 SDNode OpNode, ValueType vt> {
2143 def rr : AVX512PI<opc, MRMSrcReg,
2144 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2145 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2146 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2147 SSEPackedInt>, EVEX_4V;
2148 def rm : AVX512PI<opc, MRMSrcMem,
2149 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2150 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2151 [(set KRC:$dst, (OpNode (vt RC:$src1),
2152 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2155 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2156 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2157 EVEX_CD8<32, CD8VF>;
2158 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2159 memopv8i64, X86testm, v8i64>, T8XS, EVEX_V512, VEX_W,
2160 EVEX_CD8<64, CD8VF>;
2162 let Predicates = [HasCDI] in {
2163 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2164 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2165 EVEX_CD8<32, CD8VF>;
2166 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2167 memopv8i64, X86testnm, v8i64>, T8PD, EVEX_V512, VEX_W,
2168 EVEX_CD8<64, CD8VF>;
2171 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2172 (v16i32 VR512:$src2), (i16 -1))),
2173 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2175 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2176 (v8i64 VR512:$src2), (i8 -1))),
2177 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2178 //===----------------------------------------------------------------------===//
2179 // AVX-512 Shift instructions
2180 //===----------------------------------------------------------------------===//
2181 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2182 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2183 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2184 RegisterClass KRC> {
2185 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2186 (ins RC:$src1, i8imm:$src2),
2187 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2188 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2189 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2190 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2191 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2192 !strconcat(OpcodeStr,
2193 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2194 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2195 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2196 (ins x86memop:$src1, i8imm:$src2),
2197 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2198 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2199 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2200 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2201 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2202 !strconcat(OpcodeStr,
2203 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2204 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2207 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2208 RegisterClass RC, ValueType vt, ValueType SrcVT,
2209 PatFrag bc_frag, RegisterClass KRC> {
2210 // src2 is always 128-bit
2211 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2212 (ins RC:$src1, VR128X:$src2),
2213 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2214 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2215 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2216 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2217 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2218 !strconcat(OpcodeStr,
2219 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2220 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2221 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2222 (ins RC:$src1, i128mem:$src2),
2223 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2224 [(set RC:$dst, (vt (OpNode RC:$src1,
2225 (bc_frag (memopv2i64 addr:$src2)))))],
2226 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2227 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2228 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2229 !strconcat(OpcodeStr,
2230 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2231 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2234 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2235 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2236 EVEX_V512, EVEX_CD8<32, CD8VF>;
2237 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2238 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2239 EVEX_CD8<32, CD8VQ>;
2241 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2242 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2243 EVEX_CD8<64, CD8VF>, VEX_W;
2244 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2245 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2246 EVEX_CD8<64, CD8VQ>, VEX_W;
2248 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2249 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2250 EVEX_CD8<32, CD8VF>;
2251 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2252 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2253 EVEX_CD8<32, CD8VQ>;
2255 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2256 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2257 EVEX_CD8<64, CD8VF>, VEX_W;
2258 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2259 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2260 EVEX_CD8<64, CD8VQ>, VEX_W;
2262 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2263 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2264 EVEX_V512, EVEX_CD8<32, CD8VF>;
2265 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2266 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2267 EVEX_CD8<32, CD8VQ>;
2269 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2270 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2271 EVEX_CD8<64, CD8VF>, VEX_W;
2272 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2273 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2274 EVEX_CD8<64, CD8VQ>, VEX_W;
2276 //===-------------------------------------------------------------------===//
2277 // Variable Bit Shifts
2278 //===-------------------------------------------------------------------===//
2279 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2280 RegisterClass RC, ValueType vt,
2281 X86MemOperand x86memop, PatFrag mem_frag> {
2282 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2283 (ins RC:$src1, RC:$src2),
2284 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2286 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2288 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2289 (ins RC:$src1, x86memop:$src2),
2290 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2292 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2296 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2297 i512mem, memopv16i32>, EVEX_V512,
2298 EVEX_CD8<32, CD8VF>;
2299 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2300 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2301 EVEX_CD8<64, CD8VF>;
2302 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2303 i512mem, memopv16i32>, EVEX_V512,
2304 EVEX_CD8<32, CD8VF>;
2305 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2306 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2307 EVEX_CD8<64, CD8VF>;
2308 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2309 i512mem, memopv16i32>, EVEX_V512,
2310 EVEX_CD8<32, CD8VF>;
2311 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2312 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2313 EVEX_CD8<64, CD8VF>;
2315 //===----------------------------------------------------------------------===//
2316 // AVX-512 - MOVDDUP
2317 //===----------------------------------------------------------------------===//
2319 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2320 X86MemOperand x86memop, PatFrag memop_frag> {
2321 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2322 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2323 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2324 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2325 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2327 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2330 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2331 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2332 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2333 (VMOVDDUPZrm addr:$src)>;
2335 //===---------------------------------------------------------------------===//
2336 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2337 //===---------------------------------------------------------------------===//
2338 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2339 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2340 X86MemOperand x86memop> {
2341 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2342 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2343 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2345 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2346 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2347 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2350 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2351 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2352 EVEX_CD8<32, CD8VF>;
2353 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2354 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2355 EVEX_CD8<32, CD8VF>;
2357 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2358 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2359 (VMOVSHDUPZrm addr:$src)>;
2360 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2361 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2362 (VMOVSLDUPZrm addr:$src)>;
2364 //===----------------------------------------------------------------------===//
2365 // Move Low to High and High to Low packed FP Instructions
2366 //===----------------------------------------------------------------------===//
2367 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2368 (ins VR128X:$src1, VR128X:$src2),
2369 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2370 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2371 IIC_SSE_MOV_LH>, EVEX_4V;
2372 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2373 (ins VR128X:$src1, VR128X:$src2),
2374 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2375 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2376 IIC_SSE_MOV_LH>, EVEX_4V;
2378 let Predicates = [HasAVX512] in {
2380 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2381 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2382 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2383 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2386 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2387 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2390 //===----------------------------------------------------------------------===//
2391 // FMA - Fused Multiply Operations
2393 let Constraints = "$src1 = $dst" in {
2394 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2395 RegisterClass RC, X86MemOperand x86memop,
2396 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2397 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2398 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2399 (ins RC:$src1, RC:$src2, RC:$src3),
2400 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2401 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2404 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2405 (ins RC:$src1, RC:$src2, x86memop:$src3),
2406 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2407 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2408 (mem_frag addr:$src3))))]>;
2409 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2410 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2411 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2412 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2413 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2414 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2416 } // Constraints = "$src1 = $dst"
2418 let ExeDomain = SSEPackedSingle in {
2419 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2420 memopv16f32, f32mem, loadf32, "{1to16}",
2421 X86Fmadd, v16f32>, EVEX_V512,
2422 EVEX_CD8<32, CD8VF>;
2423 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2424 memopv16f32, f32mem, loadf32, "{1to16}",
2425 X86Fmsub, v16f32>, EVEX_V512,
2426 EVEX_CD8<32, CD8VF>;
2427 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2428 memopv16f32, f32mem, loadf32, "{1to16}",
2429 X86Fmaddsub, v16f32>,
2430 EVEX_V512, EVEX_CD8<32, CD8VF>;
2431 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2432 memopv16f32, f32mem, loadf32, "{1to16}",
2433 X86Fmsubadd, v16f32>,
2434 EVEX_V512, EVEX_CD8<32, CD8VF>;
2435 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2436 memopv16f32, f32mem, loadf32, "{1to16}",
2437 X86Fnmadd, v16f32>, EVEX_V512,
2438 EVEX_CD8<32, CD8VF>;
2439 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2440 memopv16f32, f32mem, loadf32, "{1to16}",
2441 X86Fnmsub, v16f32>, EVEX_V512,
2442 EVEX_CD8<32, CD8VF>;
2444 let ExeDomain = SSEPackedDouble in {
2445 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2446 memopv8f64, f64mem, loadf64, "{1to8}",
2447 X86Fmadd, v8f64>, EVEX_V512,
2448 VEX_W, EVEX_CD8<64, CD8VF>;
2449 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2450 memopv8f64, f64mem, loadf64, "{1to8}",
2451 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2452 EVEX_CD8<64, CD8VF>;
2453 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2454 memopv8f64, f64mem, loadf64, "{1to8}",
2455 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2456 EVEX_CD8<64, CD8VF>;
2457 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2458 memopv8f64, f64mem, loadf64, "{1to8}",
2459 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2460 EVEX_CD8<64, CD8VF>;
2461 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2462 memopv8f64, f64mem, loadf64, "{1to8}",
2463 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2464 EVEX_CD8<64, CD8VF>;
2465 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2466 memopv8f64, f64mem, loadf64, "{1to8}",
2467 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2468 EVEX_CD8<64, CD8VF>;
2471 let Constraints = "$src1 = $dst" in {
2472 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2473 RegisterClass RC, X86MemOperand x86memop,
2474 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2475 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2477 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2478 (ins RC:$src1, RC:$src3, x86memop:$src2),
2479 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2480 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2481 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2482 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2483 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2484 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2485 [(set RC:$dst, (OpNode RC:$src1,
2486 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2488 } // Constraints = "$src1 = $dst"
2491 let ExeDomain = SSEPackedSingle in {
2492 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2493 memopv16f32, f32mem, loadf32, "{1to16}",
2494 X86Fmadd, v16f32>, EVEX_V512,
2495 EVEX_CD8<32, CD8VF>;
2496 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2497 memopv16f32, f32mem, loadf32, "{1to16}",
2498 X86Fmsub, v16f32>, EVEX_V512,
2499 EVEX_CD8<32, CD8VF>;
2500 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2501 memopv16f32, f32mem, loadf32, "{1to16}",
2502 X86Fmaddsub, v16f32>,
2503 EVEX_V512, EVEX_CD8<32, CD8VF>;
2504 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2505 memopv16f32, f32mem, loadf32, "{1to16}",
2506 X86Fmsubadd, v16f32>,
2507 EVEX_V512, EVEX_CD8<32, CD8VF>;
2508 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2509 memopv16f32, f32mem, loadf32, "{1to16}",
2510 X86Fnmadd, v16f32>, EVEX_V512,
2511 EVEX_CD8<32, CD8VF>;
2512 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2513 memopv16f32, f32mem, loadf32, "{1to16}",
2514 X86Fnmsub, v16f32>, EVEX_V512,
2515 EVEX_CD8<32, CD8VF>;
2517 let ExeDomain = SSEPackedDouble in {
2518 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2519 memopv8f64, f64mem, loadf64, "{1to8}",
2520 X86Fmadd, v8f64>, EVEX_V512,
2521 VEX_W, EVEX_CD8<64, CD8VF>;
2522 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2523 memopv8f64, f64mem, loadf64, "{1to8}",
2524 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2525 EVEX_CD8<64, CD8VF>;
2526 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2527 memopv8f64, f64mem, loadf64, "{1to8}",
2528 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2529 EVEX_CD8<64, CD8VF>;
2530 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2531 memopv8f64, f64mem, loadf64, "{1to8}",
2532 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2533 EVEX_CD8<64, CD8VF>;
2534 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2535 memopv8f64, f64mem, loadf64, "{1to8}",
2536 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2537 EVEX_CD8<64, CD8VF>;
2538 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2539 memopv8f64, f64mem, loadf64, "{1to8}",
2540 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2541 EVEX_CD8<64, CD8VF>;
2545 let Constraints = "$src1 = $dst" in {
2546 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2547 RegisterClass RC, ValueType OpVT,
2548 X86MemOperand x86memop, Operand memop,
2550 let isCommutable = 1 in
2551 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2552 (ins RC:$src1, RC:$src2, RC:$src3),
2553 !strconcat(OpcodeStr,
2554 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2556 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2558 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2559 (ins RC:$src1, RC:$src2, f128mem:$src3),
2560 !strconcat(OpcodeStr,
2561 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2563 (OpVT (OpNode RC:$src2, RC:$src1,
2564 (mem_frag addr:$src3))))]>;
2567 } // Constraints = "$src1 = $dst"
2569 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2570 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2571 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2572 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2573 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2574 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2575 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2576 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2577 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2578 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2579 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2580 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2581 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2582 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2583 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2584 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2586 //===----------------------------------------------------------------------===//
2587 // AVX-512 Scalar convert from sign integer to float/double
2588 //===----------------------------------------------------------------------===//
2590 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2591 X86MemOperand x86memop, string asm> {
2592 let hasSideEffects = 0 in {
2593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2594 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2597 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2598 (ins DstRC:$src1, x86memop:$src),
2599 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2601 } // hasSideEffects = 0
2603 let Predicates = [HasAVX512] in {
2604 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2605 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2606 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2607 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2608 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2609 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2610 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2611 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2613 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2614 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2615 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2616 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2617 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2618 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2619 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2620 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2622 def : Pat<(f32 (sint_to_fp GR32:$src)),
2623 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2624 def : Pat<(f32 (sint_to_fp GR64:$src)),
2625 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2626 def : Pat<(f64 (sint_to_fp GR32:$src)),
2627 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2628 def : Pat<(f64 (sint_to_fp GR64:$src)),
2629 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2631 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2632 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2633 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2634 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2635 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2636 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2637 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2638 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2640 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2641 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2642 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2643 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2644 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2645 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2646 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2647 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2649 def : Pat<(f32 (uint_to_fp GR32:$src)),
2650 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2651 def : Pat<(f32 (uint_to_fp GR64:$src)),
2652 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2653 def : Pat<(f64 (uint_to_fp GR32:$src)),
2654 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2655 def : Pat<(f64 (uint_to_fp GR64:$src)),
2656 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2659 //===----------------------------------------------------------------------===//
2660 // AVX-512 Scalar convert from float/double to integer
2661 //===----------------------------------------------------------------------===//
2662 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2663 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2665 let hasSideEffects = 0 in {
2666 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2667 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2668 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2669 Requires<[HasAVX512]>;
2671 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2672 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2673 Requires<[HasAVX512]>;
2674 } // hasSideEffects = 0
2676 let Predicates = [HasAVX512] in {
2677 // Convert float/double to signed/unsigned int 32/64
2678 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2679 ssmem, sse_load_f32, "cvtss2si">,
2680 XS, EVEX_CD8<32, CD8VT1>;
2681 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2682 ssmem, sse_load_f32, "cvtss2si">,
2683 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2684 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2685 ssmem, sse_load_f32, "cvtss2usi">,
2686 XS, EVEX_CD8<32, CD8VT1>;
2687 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2688 int_x86_avx512_cvtss2usi64, ssmem,
2689 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2690 EVEX_CD8<32, CD8VT1>;
2691 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2692 sdmem, sse_load_f64, "cvtsd2si">,
2693 XD, EVEX_CD8<64, CD8VT1>;
2694 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2695 sdmem, sse_load_f64, "cvtsd2si">,
2696 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2697 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2698 sdmem, sse_load_f64, "cvtsd2usi">,
2699 XD, EVEX_CD8<64, CD8VT1>;
2700 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2701 int_x86_avx512_cvtsd2usi64, sdmem,
2702 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2703 EVEX_CD8<64, CD8VT1>;
2705 let isCodeGenOnly = 1 in {
2706 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2707 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2708 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2709 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2710 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2711 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2712 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2713 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2714 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2715 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2716 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2717 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2719 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2720 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2721 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2722 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2723 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2724 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2725 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2726 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2727 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2728 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2729 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2730 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2731 } // isCodeGenOnly = 1
2733 // Convert float/double to signed/unsigned int 32/64 with truncation
2734 let isCodeGenOnly = 1 in {
2735 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2736 ssmem, sse_load_f32, "cvttss2si">,
2737 XS, EVEX_CD8<32, CD8VT1>;
2738 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2739 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2740 "cvttss2si">, XS, VEX_W,
2741 EVEX_CD8<32, CD8VT1>;
2742 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2743 sdmem, sse_load_f64, "cvttsd2si">, XD,
2744 EVEX_CD8<64, CD8VT1>;
2745 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2746 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2747 "cvttsd2si">, XD, VEX_W,
2748 EVEX_CD8<64, CD8VT1>;
2749 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2750 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2751 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2752 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2753 int_x86_avx512_cvttss2usi64, ssmem,
2754 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2755 EVEX_CD8<32, CD8VT1>;
2756 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2757 int_x86_avx512_cvttsd2usi,
2758 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2759 EVEX_CD8<64, CD8VT1>;
2760 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2761 int_x86_avx512_cvttsd2usi64, sdmem,
2762 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2763 EVEX_CD8<64, CD8VT1>;
2764 } // isCodeGenOnly = 1
2766 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2767 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2769 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2770 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2771 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2772 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2773 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2774 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2777 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2778 loadf32, "cvttss2si">, XS,
2779 EVEX_CD8<32, CD8VT1>;
2780 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2781 loadf32, "cvttss2usi">, XS,
2782 EVEX_CD8<32, CD8VT1>;
2783 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2784 loadf32, "cvttss2si">, XS, VEX_W,
2785 EVEX_CD8<32, CD8VT1>;
2786 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2787 loadf32, "cvttss2usi">, XS, VEX_W,
2788 EVEX_CD8<32, CD8VT1>;
2789 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2790 loadf64, "cvttsd2si">, XD,
2791 EVEX_CD8<64, CD8VT1>;
2792 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2793 loadf64, "cvttsd2usi">, XD,
2794 EVEX_CD8<64, CD8VT1>;
2795 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2796 loadf64, "cvttsd2si">, XD, VEX_W,
2797 EVEX_CD8<64, CD8VT1>;
2798 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2799 loadf64, "cvttsd2usi">, XD, VEX_W,
2800 EVEX_CD8<64, CD8VT1>;
2802 //===----------------------------------------------------------------------===//
2803 // AVX-512 Convert form float to double and back
2804 //===----------------------------------------------------------------------===//
2805 let hasSideEffects = 0 in {
2806 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2807 (ins FR32X:$src1, FR32X:$src2),
2808 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2809 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2811 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2812 (ins FR32X:$src1, f32mem:$src2),
2813 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2814 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2815 EVEX_CD8<32, CD8VT1>;
2817 // Convert scalar double to scalar single
2818 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2819 (ins FR64X:$src1, FR64X:$src2),
2820 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2821 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2823 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2824 (ins FR64X:$src1, f64mem:$src2),
2825 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2826 []>, EVEX_4V, VEX_LIG, VEX_W,
2827 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2830 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2831 Requires<[HasAVX512]>;
2832 def : Pat<(fextend (loadf32 addr:$src)),
2833 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2835 def : Pat<(extloadf32 addr:$src),
2836 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2837 Requires<[HasAVX512, OptForSize]>;
2839 def : Pat<(extloadf32 addr:$src),
2840 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2841 Requires<[HasAVX512, OptForSpeed]>;
2843 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2844 Requires<[HasAVX512]>;
2846 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2847 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2848 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2850 let hasSideEffects = 0 in {
2851 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2852 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2854 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2855 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2856 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2857 [], d>, EVEX, EVEX_B, EVEX_RC;
2859 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2860 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2862 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2863 } // hasSideEffects = 0
2866 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2867 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2868 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2870 let hasSideEffects = 0 in {
2871 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2872 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2874 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2876 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2877 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2879 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2880 } // hasSideEffects = 0
2883 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2884 memopv8f64, f512mem, v8f32, v8f64,
2885 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2886 EVEX_CD8<64, CD8VF>;
2888 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2889 memopv4f64, f256mem, v8f64, v8f32,
2890 SSEPackedDouble>, EVEX_V512, TB,
2891 EVEX_CD8<32, CD8VH>;
2892 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2893 (VCVTPS2PDZrm addr:$src)>;
2895 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2896 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2897 (VCVTPD2PSZrr VR512:$src)>;
2899 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2900 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2901 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2903 //===----------------------------------------------------------------------===//
2904 // AVX-512 Vector convert from sign integer to float/double
2905 //===----------------------------------------------------------------------===//
2907 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2908 memopv8i64, i512mem, v16f32, v16i32,
2909 SSEPackedSingle>, EVEX_V512, TB,
2910 EVEX_CD8<32, CD8VF>;
2912 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2913 memopv4i64, i256mem, v8f64, v8i32,
2914 SSEPackedDouble>, EVEX_V512, XS,
2915 EVEX_CD8<32, CD8VH>;
2917 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2918 memopv16f32, f512mem, v16i32, v16f32,
2919 SSEPackedSingle>, EVEX_V512, XS,
2920 EVEX_CD8<32, CD8VF>;
2922 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2923 memopv8f64, f512mem, v8i32, v8f64,
2924 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2925 EVEX_CD8<64, CD8VF>;
2927 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2928 memopv16f32, f512mem, v16i32, v16f32,
2929 SSEPackedSingle>, EVEX_V512, TB,
2930 EVEX_CD8<32, CD8VF>;
2932 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2933 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2934 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2935 (VCVTTPS2UDQZrr VR512:$src)>;
2937 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2938 memopv8f64, f512mem, v8i32, v8f64,
2939 SSEPackedDouble>, EVEX_V512, TB, VEX_W,
2940 EVEX_CD8<64, CD8VF>;
2942 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2943 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2944 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2945 (VCVTTPD2UDQZrr VR512:$src)>;
2947 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2948 memopv4i64, f256mem, v8f64, v8i32,
2949 SSEPackedDouble>, EVEX_V512, XS,
2950 EVEX_CD8<32, CD8VH>;
2952 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2953 memopv16i32, f512mem, v16f32, v16i32,
2954 SSEPackedSingle>, EVEX_V512, XD,
2955 EVEX_CD8<32, CD8VF>;
2957 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2958 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2959 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2962 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2963 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2964 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2965 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2966 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2967 (VCVTDQ2PDZrr VR256X:$src)>;
2968 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2969 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2970 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2971 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2972 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2973 (VCVTUDQ2PDZrr VR256X:$src)>;
2975 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2976 RegisterClass DstRC, PatFrag mem_frag,
2977 X86MemOperand x86memop, Domain d> {
2978 let hasSideEffects = 0 in {
2979 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2980 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2982 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2983 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2984 [], d>, EVEX, EVEX_B, EVEX_RC;
2986 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2987 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2989 } // hasSideEffects = 0
2992 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2993 memopv16f32, f512mem, SSEPackedSingle>, PD,
2994 EVEX_V512, EVEX_CD8<32, CD8VF>;
2995 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2996 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2997 EVEX_V512, EVEX_CD8<64, CD8VF>;
2999 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3000 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3001 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3003 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3004 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3005 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3007 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3008 memopv16f32, f512mem, SSEPackedSingle>,
3009 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3010 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3011 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3012 TB, EVEX_V512, EVEX_CD8<64, CD8VF>;
3014 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3015 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3016 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3018 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3019 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3020 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3022 let Predicates = [HasAVX512] in {
3023 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3024 (VCVTPD2PSZrm addr:$src)>;
3025 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3026 (VCVTPS2PDZrm addr:$src)>;
3029 //===----------------------------------------------------------------------===//
3030 // Half precision conversion instructions
3031 //===----------------------------------------------------------------------===//
3032 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3033 X86MemOperand x86memop> {
3034 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3035 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3037 let hasSideEffects = 0, mayLoad = 1 in
3038 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3039 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3042 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3043 X86MemOperand x86memop> {
3044 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3045 (ins srcRC:$src1, i32i8imm:$src2),
3046 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3048 let hasSideEffects = 0, mayStore = 1 in
3049 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3050 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3051 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3054 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3055 EVEX_CD8<32, CD8VH>;
3056 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3057 EVEX_CD8<32, CD8VH>;
3059 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3060 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3061 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3063 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3064 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3065 (VCVTPH2PSZrr VR256X:$src)>;
3067 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3068 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3069 "ucomiss">, TB, EVEX, VEX_LIG,
3070 EVEX_CD8<32, CD8VT1>;
3071 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3072 "ucomisd">, PD, EVEX,
3073 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3074 let Pattern = []<dag> in {
3075 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3076 "comiss">, TB, EVEX, VEX_LIG,
3077 EVEX_CD8<32, CD8VT1>;
3078 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3079 "comisd">, PD, EVEX,
3080 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3082 let isCodeGenOnly = 1 in {
3083 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3084 load, "ucomiss">, TB, EVEX, VEX_LIG,
3085 EVEX_CD8<32, CD8VT1>;
3086 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3087 load, "ucomisd">, PD, EVEX,
3088 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3090 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3091 load, "comiss">, TB, EVEX, VEX_LIG,
3092 EVEX_CD8<32, CD8VT1>;
3093 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3094 load, "comisd">, PD, EVEX,
3095 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3099 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3100 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3101 X86MemOperand x86memop> {
3102 let hasSideEffects = 0 in {
3103 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3104 (ins RC:$src1, RC:$src2),
3105 !strconcat(OpcodeStr,
3106 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3107 let mayLoad = 1 in {
3108 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3109 (ins RC:$src1, x86memop:$src2),
3110 !strconcat(OpcodeStr,
3111 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3116 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3117 EVEX_CD8<32, CD8VT1>;
3118 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3119 VEX_W, EVEX_CD8<64, CD8VT1>;
3120 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3121 EVEX_CD8<32, CD8VT1>;
3122 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3123 VEX_W, EVEX_CD8<64, CD8VT1>;
3125 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3126 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3127 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3128 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3130 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3131 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3132 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3133 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3135 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3136 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3137 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3138 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3140 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3141 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3142 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3143 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3145 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3146 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3147 RegisterClass RC, X86MemOperand x86memop,
3148 PatFrag mem_frag, ValueType OpVt> {
3149 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3150 !strconcat(OpcodeStr,
3151 " \t{$src, $dst|$dst, $src}"),
3152 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3154 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3155 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3156 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3159 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3160 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3161 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3162 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3163 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3164 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3165 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3166 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3168 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3169 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3170 (VRSQRT14PSZr VR512:$src)>;
3171 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3172 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3173 (VRSQRT14PDZr VR512:$src)>;
3175 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3176 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3177 (VRCP14PSZr VR512:$src)>;
3178 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3179 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3180 (VRCP14PDZr VR512:$src)>;
3182 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3183 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3184 X86MemOperand x86memop> {
3185 let hasSideEffects = 0, Predicates = [HasERI] in {
3186 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3187 (ins RC:$src1, RC:$src2),
3188 !strconcat(OpcodeStr,
3189 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3190 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3191 (ins RC:$src1, RC:$src2),
3192 !strconcat(OpcodeStr,
3193 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3194 []>, EVEX_4V, EVEX_B;
3195 let mayLoad = 1 in {
3196 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3197 (ins RC:$src1, x86memop:$src2),
3198 !strconcat(OpcodeStr,
3199 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3204 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3205 EVEX_CD8<32, CD8VT1>;
3206 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3207 VEX_W, EVEX_CD8<64, CD8VT1>;
3208 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3209 EVEX_CD8<32, CD8VT1>;
3210 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3211 VEX_W, EVEX_CD8<64, CD8VT1>;
3213 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3214 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3216 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3217 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3219 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3220 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3222 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3223 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3225 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3226 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3228 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3229 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3231 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3232 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3234 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3235 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3237 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3238 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3239 RegisterClass RC, X86MemOperand x86memop> {
3240 let hasSideEffects = 0, Predicates = [HasERI] in {
3241 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3242 !strconcat(OpcodeStr,
3243 " \t{$src, $dst|$dst, $src}"),
3245 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3246 !strconcat(OpcodeStr,
3247 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3249 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3250 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3254 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3255 EVEX_V512, EVEX_CD8<32, CD8VF>;
3256 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3257 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3258 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3259 EVEX_V512, EVEX_CD8<32, CD8VF>;
3260 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3261 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3263 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3264 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3265 (VRSQRT28PSZrb VR512:$src)>;
3266 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3267 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3268 (VRSQRT28PDZrb VR512:$src)>;
3270 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3271 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3272 (VRCP28PSZrb VR512:$src)>;
3273 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3274 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3275 (VRCP28PDZrb VR512:$src)>;
3277 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3278 Intrinsic V16F32Int, Intrinsic V8F64Int,
3279 OpndItins itins_s, OpndItins itins_d> {
3280 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3281 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3282 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3286 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3287 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3289 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3290 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3292 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3293 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3294 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3298 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3299 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3300 [(set VR512:$dst, (OpNode
3301 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3302 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3304 let isCodeGenOnly = 1 in {
3305 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3306 !strconcat(OpcodeStr,
3307 "ps\t{$src, $dst|$dst, $src}"),
3308 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3310 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3311 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3313 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3314 EVEX_V512, EVEX_CD8<32, CD8VF>;
3315 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3316 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3317 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3318 EVEX, EVEX_V512, VEX_W;
3319 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3320 !strconcat(OpcodeStr,
3321 "pd\t{$src, $dst|$dst, $src}"),
3322 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3323 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3324 } // isCodeGenOnly = 1
3327 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3328 Intrinsic F32Int, Intrinsic F64Int,
3329 OpndItins itins_s, OpndItins itins_d> {
3330 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3331 (ins FR32X:$src1, FR32X:$src2),
3332 !strconcat(OpcodeStr,
3333 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3334 [], itins_s.rr>, XS, EVEX_4V;
3335 let isCodeGenOnly = 1 in
3336 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3337 (ins VR128X:$src1, VR128X:$src2),
3338 !strconcat(OpcodeStr,
3339 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3341 (F32Int VR128X:$src1, VR128X:$src2))],
3342 itins_s.rr>, XS, EVEX_4V;
3343 let mayLoad = 1 in {
3344 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3345 (ins FR32X:$src1, f32mem:$src2),
3346 !strconcat(OpcodeStr,
3347 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3348 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3349 let isCodeGenOnly = 1 in
3350 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3351 (ins VR128X:$src1, ssmem:$src2),
3352 !strconcat(OpcodeStr,
3353 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3355 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3356 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3358 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3359 (ins FR64X:$src1, FR64X:$src2),
3360 !strconcat(OpcodeStr,
3361 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3363 let isCodeGenOnly = 1 in
3364 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3365 (ins VR128X:$src1, VR128X:$src2),
3366 !strconcat(OpcodeStr,
3367 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3369 (F64Int VR128X:$src1, VR128X:$src2))],
3370 itins_s.rr>, XD, EVEX_4V, VEX_W;
3371 let mayLoad = 1 in {
3372 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3373 (ins FR64X:$src1, f64mem:$src2),
3374 !strconcat(OpcodeStr,
3375 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3376 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3377 let isCodeGenOnly = 1 in
3378 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3379 (ins VR128X:$src1, sdmem:$src2),
3380 !strconcat(OpcodeStr,
3381 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3383 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3384 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3389 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3390 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3391 SSE_SQRTSS, SSE_SQRTSD>,
3392 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3393 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3394 SSE_SQRTPS, SSE_SQRTPD>;
3396 let Predicates = [HasAVX512] in {
3397 def : Pat<(f32 (fsqrt FR32X:$src)),
3398 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3399 def : Pat<(f32 (fsqrt (load addr:$src))),
3400 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3401 Requires<[OptForSize]>;
3402 def : Pat<(f64 (fsqrt FR64X:$src)),
3403 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3404 def : Pat<(f64 (fsqrt (load addr:$src))),
3405 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3406 Requires<[OptForSize]>;
3408 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3409 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3410 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3411 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3412 Requires<[OptForSize]>;
3414 def : Pat<(f32 (X86frcp FR32X:$src)),
3415 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3416 def : Pat<(f32 (X86frcp (load addr:$src))),
3417 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3418 Requires<[OptForSize]>;
3420 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3421 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3422 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3424 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3425 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3427 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3428 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3429 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3431 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3432 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3436 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3437 X86MemOperand x86memop, RegisterClass RC,
3438 PatFrag mem_frag32, PatFrag mem_frag64,
3439 Intrinsic V4F32Int, Intrinsic V2F64Int,
3441 let ExeDomain = SSEPackedSingle in {
3442 // Intrinsic operation, reg.
3443 // Vector intrinsic operation, reg
3444 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3445 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3446 !strconcat(OpcodeStr,
3447 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3448 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3450 // Vector intrinsic operation, mem
3451 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3452 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3453 !strconcat(OpcodeStr,
3454 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3456 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3457 EVEX_CD8<32, VForm>;
3458 } // ExeDomain = SSEPackedSingle
3460 let ExeDomain = SSEPackedDouble in {
3461 // Vector intrinsic operation, reg
3462 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3463 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3464 !strconcat(OpcodeStr,
3465 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3466 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3468 // Vector intrinsic operation, mem
3469 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3470 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3471 !strconcat(OpcodeStr,
3472 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3474 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3475 EVEX_CD8<64, VForm>;
3476 } // ExeDomain = SSEPackedDouble
3479 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3483 let ExeDomain = GenericDomain in {
3485 let hasSideEffects = 0 in
3486 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3487 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3488 !strconcat(OpcodeStr,
3489 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3492 // Intrinsic operation, reg.
3493 let isCodeGenOnly = 1 in
3494 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3495 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3496 !strconcat(OpcodeStr,
3497 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3498 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3500 // Intrinsic operation, mem.
3501 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3502 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3503 !strconcat(OpcodeStr,
3504 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3505 [(set VR128X:$dst, (F32Int VR128X:$src1,
3506 sse_load_f32:$src2, imm:$src3))]>,
3507 EVEX_CD8<32, CD8VT1>;
3510 let hasSideEffects = 0 in
3511 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3512 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3513 !strconcat(OpcodeStr,
3514 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3517 // Intrinsic operation, reg.
3518 let isCodeGenOnly = 1 in
3519 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3520 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3521 !strconcat(OpcodeStr,
3522 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3523 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3526 // Intrinsic operation, mem.
3527 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3528 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3529 !strconcat(OpcodeStr,
3530 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3532 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3533 VEX_W, EVEX_CD8<64, CD8VT1>;
3534 } // ExeDomain = GenericDomain
3537 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3538 X86MemOperand x86memop, RegisterClass RC,
3539 PatFrag mem_frag, Domain d> {
3540 let ExeDomain = d in {
3541 // Intrinsic operation, reg.
3542 // Vector intrinsic operation, reg
3543 def r : AVX512AIi8<opc, MRMSrcReg,
3544 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3545 !strconcat(OpcodeStr,
3546 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3549 // Vector intrinsic operation, mem
3550 def m : AVX512AIi8<opc, MRMSrcMem,
3551 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3552 !strconcat(OpcodeStr,
3553 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3559 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3560 memopv16f32, SSEPackedSingle>, EVEX_V512,
3561 EVEX_CD8<32, CD8VF>;
3563 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3564 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3566 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3569 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3570 memopv8f64, SSEPackedDouble>, EVEX_V512,
3571 VEX_W, EVEX_CD8<64, CD8VF>;
3573 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3574 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3576 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3578 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3579 Operand x86memop, RegisterClass RC, Domain d> {
3580 let ExeDomain = d in {
3581 def r : AVX512AIi8<opc, MRMSrcReg,
3582 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3583 !strconcat(OpcodeStr,
3584 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3587 def m : AVX512AIi8<opc, MRMSrcMem,
3588 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3589 !strconcat(OpcodeStr,
3590 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3595 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3596 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3598 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3599 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3601 def : Pat<(ffloor FR32X:$src),
3602 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3603 def : Pat<(f64 (ffloor FR64X:$src)),
3604 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3605 def : Pat<(f32 (fnearbyint FR32X:$src)),
3606 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3607 def : Pat<(f64 (fnearbyint FR64X:$src)),
3608 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3609 def : Pat<(f32 (fceil FR32X:$src)),
3610 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3611 def : Pat<(f64 (fceil FR64X:$src)),
3612 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3613 def : Pat<(f32 (frint FR32X:$src)),
3614 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3615 def : Pat<(f64 (frint FR64X:$src)),
3616 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3617 def : Pat<(f32 (ftrunc FR32X:$src)),
3618 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3619 def : Pat<(f64 (ftrunc FR64X:$src)),
3620 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3622 def : Pat<(v16f32 (ffloor VR512:$src)),
3623 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3624 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3625 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3626 def : Pat<(v16f32 (fceil VR512:$src)),
3627 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3628 def : Pat<(v16f32 (frint VR512:$src)),
3629 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3630 def : Pat<(v16f32 (ftrunc VR512:$src)),
3631 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3633 def : Pat<(v8f64 (ffloor VR512:$src)),
3634 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3635 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3636 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3637 def : Pat<(v8f64 (fceil VR512:$src)),
3638 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3639 def : Pat<(v8f64 (frint VR512:$src)),
3640 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3641 def : Pat<(v8f64 (ftrunc VR512:$src)),
3642 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3644 //-------------------------------------------------
3645 // Integer truncate and extend operations
3646 //-------------------------------------------------
3648 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3649 RegisterClass dstRC, RegisterClass srcRC,
3650 RegisterClass KRC, X86MemOperand x86memop> {
3651 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3653 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3656 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3657 (ins KRC:$mask, srcRC:$src),
3658 !strconcat(OpcodeStr,
3659 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3662 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3663 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3666 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3667 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3668 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3669 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3670 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3671 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3672 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3673 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3674 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3675 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3676 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3677 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3678 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3679 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3680 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3681 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3682 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3683 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3684 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3685 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3686 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3687 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3688 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3689 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3690 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3691 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3692 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3693 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3694 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3695 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3697 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3698 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3699 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3700 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3701 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3703 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3704 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3705 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3706 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3707 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3708 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3709 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3710 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3713 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3714 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3715 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3717 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3719 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3720 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3721 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3722 (ins x86memop:$src),
3723 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3725 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3729 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3730 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3732 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3733 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3735 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3736 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3737 EVEX_CD8<16, CD8VH>;
3738 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3739 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3740 EVEX_CD8<16, CD8VQ>;
3741 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3742 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3743 EVEX_CD8<32, CD8VH>;
3745 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3746 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3748 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3749 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3751 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3752 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3753 EVEX_CD8<16, CD8VH>;
3754 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3755 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3756 EVEX_CD8<16, CD8VQ>;
3757 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3758 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3759 EVEX_CD8<32, CD8VH>;
3761 //===----------------------------------------------------------------------===//
3762 // GATHER - SCATTER Operations
3764 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3765 RegisterClass RC, X86MemOperand memop> {
3767 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3768 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3769 (ins RC:$src1, KRC:$mask, memop:$src2),
3770 !strconcat(OpcodeStr,
3771 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3774 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3775 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3776 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3777 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3779 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3780 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3781 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3782 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3784 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3785 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3786 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3787 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3789 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3790 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3791 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3792 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3794 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3795 RegisterClass RC, X86MemOperand memop> {
3796 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3797 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3798 (ins memop:$dst, KRC:$mask, RC:$src2),
3799 !strconcat(OpcodeStr,
3800 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3804 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3806 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3807 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3809 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3810 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3811 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3812 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3814 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3815 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3816 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3817 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3819 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3820 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3821 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3822 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3824 //===----------------------------------------------------------------------===//
3825 // VSHUFPS - VSHUFPD Operations
3827 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3828 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3830 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3831 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3832 !strconcat(OpcodeStr,
3833 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3834 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3835 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3836 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3837 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3838 (ins RC:$src1, RC:$src2, i8imm:$src3),
3839 !strconcat(OpcodeStr,
3840 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3841 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3842 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3843 EVEX_4V, Sched<[WriteShuffle]>;
3846 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3847 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3848 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3849 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3851 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3852 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3853 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3854 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3855 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3857 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3858 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3859 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3860 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3861 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3863 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3864 X86MemOperand x86memop> {
3865 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3866 (ins RC:$src1, RC:$src2, i8imm:$src3),
3867 !strconcat(OpcodeStr,
3868 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3871 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3872 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3873 !strconcat(OpcodeStr,
3874 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3877 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3878 EVEX_V512, EVEX_CD8<32, CD8VF>;
3879 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3880 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3882 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3883 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3884 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3885 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3886 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3887 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3888 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3889 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3891 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3892 X86MemOperand x86memop> {
3893 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3894 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3896 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3897 (ins x86memop:$src),
3898 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3902 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3903 EVEX_CD8<32, CD8VF>;
3904 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3905 EVEX_CD8<64, CD8VF>;
3907 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3908 (v16i32 immAllZerosV), (i16 -1))),
3909 (VPABSDrr VR512:$src)>;
3910 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3911 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3912 (VPABSQrr VR512:$src)>;
3914 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3915 RegisterClass RC, RegisterClass KRC,
3916 X86MemOperand x86memop,
3917 X86MemOperand x86scalar_mop, string BrdcstStr> {
3918 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3920 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3922 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3923 (ins x86memop:$src),
3924 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3926 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3927 (ins x86scalar_mop:$src),
3928 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3929 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3931 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3932 (ins KRC:$mask, RC:$src),
3933 !strconcat(OpcodeStr,
3934 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3936 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3937 (ins KRC:$mask, x86memop:$src),
3938 !strconcat(OpcodeStr,
3939 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3941 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3942 (ins KRC:$mask, x86scalar_mop:$src),
3943 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3944 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3946 []>, EVEX, EVEX_KZ, EVEX_B;
3948 let Constraints = "$src1 = $dst" in {
3949 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3950 (ins RC:$src1, KRC:$mask, RC:$src2),
3951 !strconcat(OpcodeStr,
3952 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3954 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3955 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3956 !strconcat(OpcodeStr,
3957 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3959 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3960 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3961 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3962 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3963 []>, EVEX, EVEX_K, EVEX_B;
3967 let Predicates = [HasCDI] in {
3968 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3969 i512mem, i32mem, "{1to16}">,
3970 EVEX_V512, EVEX_CD8<32, CD8VF>;
3973 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3974 i512mem, i64mem, "{1to8}">,
3975 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3979 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3981 (VPCONFLICTDrrk VR512:$src1,
3982 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3984 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3986 (VPCONFLICTQrrk VR512:$src1,
3987 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;