1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERM2D : avx512_perm_3src<0x7E, "vperm2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERM2Q : avx512_perm_3src<0x7E, "vperm2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERM2PS : avx512_perm_3src<0x7F, "vperm2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERM2PD : avx512_perm_3src<0x7F, "vperm2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
755 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
756 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
758 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
759 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
760 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
761 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
763 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
764 (COPY_TO_REGCLASS (VPCMPGTDZrr
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
766 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
768 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
769 (COPY_TO_REGCLASS (VPCMPEQDZrr
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
771 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
773 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
774 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
775 SDNode OpNode, ValueType vt, Operand CC, string asm,
777 def rri : AVX512AIi8<opc, MRMSrcReg,
778 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
779 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
780 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
784 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
785 // Accept explicit immediate argument form instead of comparison code.
786 let isAsmParserOnly = 1, hasSideEffects = 0 in {
787 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
788 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
789 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
790 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
791 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
792 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
796 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
797 X86cmpm, v16i32, AVXCC,
798 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 EVEX_V512, EVEX_CD8<32, CD8VF>;
801 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
802 X86cmpmu, v16i32, AVXCC,
803 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
805 EVEX_V512, EVEX_CD8<32, CD8VF>;
807 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
808 X86cmpm, v8i64, AVXCC,
809 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
810 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
811 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
812 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
813 X86cmpmu, v8i64, AVXCC,
814 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
815 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
816 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
818 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
819 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
820 X86MemOperand x86memop, ValueType vt,
821 string suffix, Domain d> {
822 def rri : AVX512PIi8<0xC2, MRMSrcReg,
823 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
824 !strconcat("vcmp${cc}", suffix,
825 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
826 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
827 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
828 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
829 !strconcat("vcmp${cc}", suffix,
830 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
832 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
834 !strconcat("vcmp${cc}", suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
837 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
839 // Accept explicit immediate argument form instead of comparison code.
840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
841 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
842 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
843 !strconcat("vcmp", suffix,
844 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
845 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
846 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
852 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
853 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
854 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
855 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
858 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
859 (COPY_TO_REGCLASS (VCMPPSZrri
860 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
861 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
863 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
864 (COPY_TO_REGCLASS (VPCMPDZrri
865 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
866 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
868 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
869 (COPY_TO_REGCLASS (VPCMPUDZrri
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
874 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
875 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
877 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
878 (I8Imm imm:$cc)), GR16)>;
880 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
881 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
883 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
884 (I8Imm imm:$cc)), GR8)>;
886 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
887 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
889 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
890 (I8Imm imm:$cc)), GR16)>;
892 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
893 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
895 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
896 (I8Imm imm:$cc)), GR8)>;
898 // Mask register copy, including
899 // - copy between mask registers
900 // - load/store mask registers
901 // - copy from GPR to mask register and vice versa
903 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
904 string OpcodeStr, RegisterClass KRC,
905 ValueType vt, X86MemOperand x86memop> {
906 let hasSideEffects = 0 in {
907 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
908 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
910 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
911 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
912 [(set KRC:$dst, (vt (load addr:$src)))]>;
914 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
915 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
919 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
921 RegisterClass KRC, RegisterClass GRC> {
922 let hasSideEffects = 0 in {
923 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
924 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
925 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
926 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
930 let Predicates = [HasAVX512] in {
931 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
933 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
937 let Predicates = [HasAVX512] in {
938 // GR16 from/to 16-bit mask
939 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
940 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
941 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
942 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
944 // Store kreg in memory
945 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
946 (KMOVWmk addr:$dst, VK16:$src)>;
948 def : Pat<(store VK8:$src, addr:$dst),
949 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
951 def : Pat<(i1 (load addr:$src)),
952 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
954 def : Pat<(v8i1 (load addr:$src)),
955 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
957 def : Pat<(i1 (trunc (i32 GR32:$src))),
958 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
960 def : Pat<(i1 (trunc (i8 GR8:$src))),
962 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
964 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
965 def : Pat<(i8 (zext VK1:$src)),
967 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
968 def : Pat<(i64 (zext VK1:$src)),
969 (SUBREG_TO_REG (i64 0),
970 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
973 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
974 let Predicates = [HasAVX512] in {
975 // GR from/to 8-bit mask without native support
976 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
978 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
980 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
982 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
985 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
986 (COPY_TO_REGCLASS VK16:$src, VK1)>;
987 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
988 (COPY_TO_REGCLASS VK8:$src, VK1)>;
992 // Mask unary operation
994 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
995 RegisterClass KRC, SDPatternOperator OpNode> {
996 let Predicates = [HasAVX512] in
997 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
998 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
999 [(set KRC:$dst, (OpNode KRC:$src))]>;
1002 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1003 SDPatternOperator OpNode> {
1004 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1008 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1010 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1011 let Predicates = [HasAVX512] in
1012 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1014 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1015 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1017 defm : avx512_mask_unop_int<"knot", "KNOT">;
1019 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1020 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1021 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1023 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1024 def : Pat<(not VK8:$src),
1026 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1028 // Mask binary operation
1029 // - KAND, KANDN, KOR, KXNOR, KXOR
1030 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1031 RegisterClass KRC, SDPatternOperator OpNode> {
1032 let Predicates = [HasAVX512] in
1033 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1034 !strconcat(OpcodeStr,
1035 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1036 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1039 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1040 SDPatternOperator OpNode> {
1041 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1045 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1046 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1048 let isCommutable = 1 in {
1049 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1050 let isCommutable = 0 in
1051 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1052 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1053 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1054 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1057 def : Pat<(xor VK1:$src1, VK1:$src2),
1058 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1059 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1061 def : Pat<(or VK1:$src1, VK1:$src2),
1062 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1063 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1065 def : Pat<(not VK1:$src),
1066 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1067 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1068 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1070 def : Pat<(and VK1:$src1, VK1:$src2),
1071 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1072 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1074 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1075 let Predicates = [HasAVX512] in
1076 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1077 (i16 GR16:$src1), (i16 GR16:$src2)),
1078 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1079 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1080 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1083 defm : avx512_mask_binop_int<"kand", "KAND">;
1084 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1085 defm : avx512_mask_binop_int<"kor", "KOR">;
1086 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1087 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1089 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1090 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1091 let Predicates = [HasAVX512] in
1092 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1094 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1095 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1098 defm : avx512_binop_pat<and, KANDWrr>;
1099 defm : avx512_binop_pat<andn, KANDNWrr>;
1100 defm : avx512_binop_pat<or, KORWrr>;
1101 defm : avx512_binop_pat<xnor, KXNORWrr>;
1102 defm : avx512_binop_pat<xor, KXORWrr>;
1105 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1106 RegisterClass KRC> {
1107 let Predicates = [HasAVX512] in
1108 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1109 !strconcat(OpcodeStr,
1110 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1113 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1114 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1118 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1119 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1120 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1121 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1124 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1125 let Predicates = [HasAVX512] in
1126 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1127 (i16 GR16:$src1), (i16 GR16:$src2)),
1128 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1129 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1130 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1132 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1135 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1137 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1138 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1139 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1140 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1143 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1144 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1148 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1150 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1151 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1152 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1155 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1157 let Predicates = [HasAVX512] in
1158 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1159 !strconcat(OpcodeStr,
1160 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1161 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1164 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1166 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1170 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1171 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1173 // Mask setting all 0s or 1s
1174 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1175 let Predicates = [HasAVX512] in
1176 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1177 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1178 [(set KRC:$dst, (VT Val))]>;
1181 multiclass avx512_mask_setop_w<PatFrag Val> {
1182 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1183 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1186 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1187 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1189 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1190 let Predicates = [HasAVX512] in {
1191 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1192 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1193 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1194 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1195 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1197 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1198 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1200 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1201 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1203 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1204 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1206 //===----------------------------------------------------------------------===//
1207 // AVX-512 - Aligned and unaligned load and store
1210 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1211 X86MemOperand x86memop, PatFrag ld_frag,
1212 string asm, Domain d, bit IsReMaterializable = 1> {
1213 let hasSideEffects = 0 in
1214 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1215 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1217 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1218 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1219 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1220 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1221 let Constraints = "$src1 = $dst" in {
1222 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1223 (ins RC:$src1, KRC:$mask, RC:$src2),
1225 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1227 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1228 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1230 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1231 [], d>, EVEX, EVEX_K;
1235 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1236 "vmovaps", SSEPackedSingle>,
1237 EVEX_V512, EVEX_CD8<32, CD8VF>;
1238 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1239 "vmovapd", SSEPackedDouble>,
1240 PD, EVEX_V512, VEX_W,
1241 EVEX_CD8<64, CD8VF>;
1242 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1243 "vmovups", SSEPackedSingle>,
1244 EVEX_V512, EVEX_CD8<32, CD8VF>;
1245 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1246 "vmovupd", SSEPackedDouble, 0>,
1247 PD, EVEX_V512, VEX_W,
1248 EVEX_CD8<64, CD8VF>;
1249 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1250 "vmovaps\t{$src, $dst|$dst, $src}",
1251 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1252 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1253 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1254 "vmovapd\t{$src, $dst|$dst, $src}",
1255 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1256 SSEPackedDouble>, EVEX, EVEX_V512,
1257 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1258 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1259 "vmovups\t{$src, $dst|$dst, $src}",
1260 [(store (v16f32 VR512:$src), addr:$dst)],
1261 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1262 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1263 "vmovupd\t{$src, $dst|$dst, $src}",
1264 [(store (v8f64 VR512:$src), addr:$dst)],
1265 SSEPackedDouble>, EVEX, EVEX_V512,
1266 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1268 let hasSideEffects = 0 in {
1269 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1271 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1273 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1275 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1276 EVEX, EVEX_V512, VEX_W;
1277 let mayStore = 1 in {
1278 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1279 (ins i512mem:$dst, VR512:$src),
1280 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1281 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1282 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1283 (ins i512mem:$dst, VR512:$src),
1284 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1285 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1287 let mayLoad = 1 in {
1288 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1290 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1291 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1292 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1294 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1295 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1299 // 512-bit aligned load/store
1300 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1301 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1303 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1304 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1305 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1306 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1308 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1309 RegisterClass RC, RegisterClass KRC,
1310 PatFrag ld_frag, X86MemOperand x86memop> {
1311 let hasSideEffects = 0 in
1312 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1313 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1314 let canFoldAsLoad = 1 in
1315 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1316 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1317 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1319 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1320 (ins x86memop:$dst, VR512:$src),
1321 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1322 let Constraints = "$src1 = $dst" in {
1323 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1324 (ins RC:$src1, KRC:$mask, RC:$src2),
1326 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1328 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1329 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1331 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1336 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1337 memopv16i32, i512mem>,
1338 EVEX_V512, EVEX_CD8<32, CD8VF>;
1339 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1340 memopv8i64, i512mem>,
1341 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1343 // 512-bit unaligned load/store
1344 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1345 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1347 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1348 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1349 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1350 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1352 let AddedComplexity = 20 in {
1353 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1354 (v16f32 VR512:$src2))),
1355 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1356 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1357 (v8f64 VR512:$src2))),
1358 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1359 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1360 (v16i32 VR512:$src2))),
1361 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1362 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1363 (v8i64 VR512:$src2))),
1364 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1366 // Move Int Doubleword to Packed Double Int
1368 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1369 "vmovd\t{$src, $dst|$dst, $src}",
1371 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1373 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1374 "vmovd\t{$src, $dst|$dst, $src}",
1376 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1377 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1378 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1379 "vmovq\t{$src, $dst|$dst, $src}",
1381 (v2i64 (scalar_to_vector GR64:$src)))],
1382 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1383 let isCodeGenOnly = 1 in {
1384 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1385 "vmovq\t{$src, $dst|$dst, $src}",
1386 [(set FR64:$dst, (bitconvert GR64:$src))],
1387 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1388 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1389 "vmovq\t{$src, $dst|$dst, $src}",
1390 [(set GR64:$dst, (bitconvert FR64:$src))],
1391 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1393 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1394 "vmovq\t{$src, $dst|$dst, $src}",
1395 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1396 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1397 EVEX_CD8<64, CD8VT1>;
1399 // Move Int Doubleword to Single Scalar
1401 let isCodeGenOnly = 1 in {
1402 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1403 "vmovd\t{$src, $dst|$dst, $src}",
1404 [(set FR32X:$dst, (bitconvert GR32:$src))],
1405 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1407 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1408 "vmovd\t{$src, $dst|$dst, $src}",
1409 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1410 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1413 // Move doubleword from xmm register to r/m32
1415 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1416 "vmovd\t{$src, $dst|$dst, $src}",
1417 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1418 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1420 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1421 (ins i32mem:$dst, VR128X:$src),
1422 "vmovd\t{$src, $dst|$dst, $src}",
1423 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1424 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1425 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1427 // Move quadword from xmm1 register to r/m64
1429 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1430 "vmovq\t{$src, $dst|$dst, $src}",
1431 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1433 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1434 Requires<[HasAVX512, In64BitMode]>;
1436 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1437 (ins i64mem:$dst, VR128X:$src),
1438 "vmovq\t{$src, $dst|$dst, $src}",
1439 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1440 addr:$dst)], IIC_SSE_MOVDQ>,
1441 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1442 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1444 // Move Scalar Single to Double Int
1446 let isCodeGenOnly = 1 in {
1447 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1449 "vmovd\t{$src, $dst|$dst, $src}",
1450 [(set GR32:$dst, (bitconvert FR32X:$src))],
1451 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1452 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1453 (ins i32mem:$dst, FR32X:$src),
1454 "vmovd\t{$src, $dst|$dst, $src}",
1455 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1456 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1459 // Move Quadword Int to Packed Quadword Int
1461 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1463 "vmovq\t{$src, $dst|$dst, $src}",
1465 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1466 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1468 //===----------------------------------------------------------------------===//
1469 // AVX-512 MOVSS, MOVSD
1470 //===----------------------------------------------------------------------===//
1472 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1473 SDNode OpNode, ValueType vt,
1474 X86MemOperand x86memop, PatFrag mem_pat> {
1475 let hasSideEffects = 0 in {
1476 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1477 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1478 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1479 (scalar_to_vector RC:$src2))))],
1480 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1481 let Constraints = "$src1 = $dst" in
1482 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1483 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1485 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1486 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1487 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1488 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1489 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1491 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1492 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1493 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1495 } //hasSideEffects = 0
1498 let ExeDomain = SSEPackedSingle in
1499 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1500 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1502 let ExeDomain = SSEPackedDouble in
1503 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1504 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1506 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1507 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1508 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1510 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1511 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1512 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1514 // For the disassembler
1515 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1516 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1517 (ins VR128X:$src1, FR32X:$src2),
1518 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1520 XS, EVEX_4V, VEX_LIG;
1521 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1522 (ins VR128X:$src1, FR64X:$src2),
1523 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1525 XD, EVEX_4V, VEX_LIG, VEX_W;
1528 let Predicates = [HasAVX512] in {
1529 let AddedComplexity = 15 in {
1530 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1531 // MOVS{S,D} to the lower bits.
1532 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1533 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1534 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1535 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1536 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1537 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1538 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1539 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1541 // Move low f32 and clear high bits.
1542 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1543 (SUBREG_TO_REG (i32 0),
1544 (VMOVSSZrr (v4f32 (V_SET0)),
1545 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1546 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1547 (SUBREG_TO_REG (i32 0),
1548 (VMOVSSZrr (v4i32 (V_SET0)),
1549 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1552 let AddedComplexity = 20 in {
1553 // MOVSSrm zeros the high parts of the register; represent this
1554 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1555 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1556 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1557 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1558 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1559 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1560 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1562 // MOVSDrm zeros the high parts of the register; represent this
1563 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1564 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1565 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1566 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1567 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1568 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1569 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1570 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1571 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1572 def : Pat<(v2f64 (X86vzload addr:$src)),
1573 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1575 // Represent the same patterns above but in the form they appear for
1577 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1578 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1579 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1580 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1581 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1582 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1583 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1584 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1585 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1587 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1588 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1589 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1590 FR32X:$src)), sub_xmm)>;
1591 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1592 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1593 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1594 FR64X:$src)), sub_xmm)>;
1595 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1596 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1597 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1599 // Move low f64 and clear high bits.
1600 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1601 (SUBREG_TO_REG (i32 0),
1602 (VMOVSDZrr (v2f64 (V_SET0)),
1603 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1605 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1606 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1607 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1609 // Extract and store.
1610 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1612 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1613 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1615 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1617 // Shuffle with VMOVSS
1618 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1619 (VMOVSSZrr (v4i32 VR128X:$src1),
1620 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1621 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1622 (VMOVSSZrr (v4f32 VR128X:$src1),
1623 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1626 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1627 (SUBREG_TO_REG (i32 0),
1628 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1629 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1631 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1632 (SUBREG_TO_REG (i32 0),
1633 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1634 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1637 // Shuffle with VMOVSD
1638 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1639 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1640 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1641 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1642 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1643 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1644 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1645 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1648 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1649 (SUBREG_TO_REG (i32 0),
1650 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1651 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1653 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1654 (SUBREG_TO_REG (i32 0),
1655 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1656 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1659 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1660 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1661 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1662 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1663 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1664 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1665 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1666 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1669 let AddedComplexity = 15 in
1670 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1672 "vmovq\t{$src, $dst|$dst, $src}",
1673 [(set VR128X:$dst, (v2i64 (X86vzmovl
1674 (v2i64 VR128X:$src))))],
1675 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1677 let AddedComplexity = 20 in
1678 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1680 "vmovq\t{$src, $dst|$dst, $src}",
1681 [(set VR128X:$dst, (v2i64 (X86vzmovl
1682 (loadv2i64 addr:$src))))],
1683 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1684 EVEX_CD8<8, CD8VT8>;
1686 let Predicates = [HasAVX512] in {
1687 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1688 let AddedComplexity = 20 in {
1689 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1690 (VMOVDI2PDIZrm addr:$src)>;
1691 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1692 (VMOV64toPQIZrr GR64:$src)>;
1693 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1694 (VMOVDI2PDIZrr GR32:$src)>;
1696 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1697 (VMOVDI2PDIZrm addr:$src)>;
1698 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1699 (VMOVDI2PDIZrm addr:$src)>;
1700 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1701 (VMOVZPQILo2PQIZrm addr:$src)>;
1702 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1703 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1704 def : Pat<(v2i64 (X86vzload addr:$src)),
1705 (VMOVZPQILo2PQIZrm addr:$src)>;
1708 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1709 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1710 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1711 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1712 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1713 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1714 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1717 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1718 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1720 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1721 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1723 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1724 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1726 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1727 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1729 //===----------------------------------------------------------------------===//
1730 // AVX-512 - Integer arithmetic
1732 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1733 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1734 X86MemOperand x86memop, PatFrag scalar_mfrag,
1735 X86MemOperand x86scalar_mop, string BrdcstStr,
1736 OpndItins itins, bit IsCommutable = 0> {
1737 let isCommutable = IsCommutable in
1738 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1739 (ins RC:$src1, RC:$src2),
1740 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1741 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1743 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1744 (ins RC:$src1, x86memop:$src2),
1745 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1746 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1748 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1749 (ins RC:$src1, x86scalar_mop:$src2),
1750 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1751 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1752 [(set RC:$dst, (OpNode RC:$src1,
1753 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1754 itins.rm>, EVEX_4V, EVEX_B;
1756 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1757 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1758 PatFrag memop_frag, X86MemOperand x86memop,
1760 bit IsCommutable = 0> {
1761 let isCommutable = IsCommutable in
1762 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1763 (ins RC:$src1, RC:$src2),
1764 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1765 []>, EVEX_4V, VEX_W;
1766 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1767 (ins RC:$src1, x86memop:$src2),
1768 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1769 []>, EVEX_4V, VEX_W;
1772 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1773 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1774 EVEX_V512, EVEX_CD8<32, CD8VF>;
1776 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1777 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1778 EVEX_V512, EVEX_CD8<32, CD8VF>;
1780 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1781 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1782 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1784 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1785 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1786 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1788 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1789 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1790 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1792 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1793 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1794 EVEX_V512, EVEX_CD8<64, CD8VF>;
1796 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1797 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1798 EVEX_CD8<64, CD8VF>;
1800 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1801 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1803 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1804 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1805 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1806 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1807 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1808 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1810 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1811 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1812 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1813 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1814 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1815 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1817 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1818 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1819 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1820 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1821 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1822 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1824 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1825 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1826 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1827 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1828 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1829 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1831 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1832 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1833 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1834 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1835 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1836 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1838 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1839 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1840 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1841 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1842 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1843 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1844 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1845 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1846 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1847 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1848 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1849 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1850 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1851 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1852 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1853 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1854 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1855 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1856 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1857 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1858 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1859 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1860 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1861 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1862 //===----------------------------------------------------------------------===//
1863 // AVX-512 - Unpack Instructions
1864 //===----------------------------------------------------------------------===//
1866 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1867 PatFrag mem_frag, RegisterClass RC,
1868 X86MemOperand x86memop, string asm,
1870 def rr : AVX512PI<opc, MRMSrcReg,
1871 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1873 (vt (OpNode RC:$src1, RC:$src2)))],
1875 def rm : AVX512PI<opc, MRMSrcMem,
1876 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1878 (vt (OpNode RC:$src1,
1879 (bitconvert (mem_frag addr:$src2)))))],
1883 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1884 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1885 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1886 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1887 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1889 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1890 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1891 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1892 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1893 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1894 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1896 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1897 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1898 X86MemOperand x86memop> {
1899 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1900 (ins RC:$src1, RC:$src2),
1901 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1902 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1903 IIC_SSE_UNPCK>, EVEX_4V;
1904 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1905 (ins RC:$src1, x86memop:$src2),
1906 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1907 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1908 (bitconvert (memop_frag addr:$src2)))))],
1909 IIC_SSE_UNPCK>, EVEX_4V;
1911 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1912 VR512, memopv16i32, i512mem>, EVEX_V512,
1913 EVEX_CD8<32, CD8VF>;
1914 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1915 VR512, memopv8i64, i512mem>, EVEX_V512,
1916 VEX_W, EVEX_CD8<64, CD8VF>;
1917 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1918 VR512, memopv16i32, i512mem>, EVEX_V512,
1919 EVEX_CD8<32, CD8VF>;
1920 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1921 VR512, memopv8i64, i512mem>, EVEX_V512,
1922 VEX_W, EVEX_CD8<64, CD8VF>;
1923 //===----------------------------------------------------------------------===//
1927 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1928 SDNode OpNode, PatFrag mem_frag,
1929 X86MemOperand x86memop, ValueType OpVT> {
1930 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1931 (ins RC:$src1, i8imm:$src2),
1932 !strconcat(OpcodeStr,
1933 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1935 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1937 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1938 (ins x86memop:$src1, i8imm:$src2),
1939 !strconcat(OpcodeStr,
1940 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1942 (OpVT (OpNode (mem_frag addr:$src1),
1943 (i8 imm:$src2))))]>, EVEX;
1946 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1947 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1949 let ExeDomain = SSEPackedSingle in
1950 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1951 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1952 EVEX_CD8<32, CD8VF>;
1953 let ExeDomain = SSEPackedDouble in
1954 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1955 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1956 VEX_W, EVEX_CD8<32, CD8VF>;
1958 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1959 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1960 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1961 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1963 //===----------------------------------------------------------------------===//
1964 // AVX-512 Logical Instructions
1965 //===----------------------------------------------------------------------===//
1967 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1968 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1969 EVEX_V512, EVEX_CD8<32, CD8VF>;
1970 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1971 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1972 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1973 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1974 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1975 EVEX_V512, EVEX_CD8<32, CD8VF>;
1976 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1977 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1978 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1979 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1980 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1981 EVEX_V512, EVEX_CD8<32, CD8VF>;
1982 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1983 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1984 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1985 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1986 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1987 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1988 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1989 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1990 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1992 //===----------------------------------------------------------------------===//
1993 // AVX-512 FP arithmetic
1994 //===----------------------------------------------------------------------===//
1996 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1998 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1999 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2000 EVEX_CD8<32, CD8VT1>;
2001 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2002 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2003 EVEX_CD8<64, CD8VT1>;
2006 let isCommutable = 1 in {
2007 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2008 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2009 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2010 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2012 let isCommutable = 0 in {
2013 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2014 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2017 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2018 RegisterClass RC, ValueType vt,
2019 X86MemOperand x86memop, PatFrag mem_frag,
2020 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2022 Domain d, OpndItins itins, bit commutable> {
2023 let isCommutable = commutable in
2024 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2025 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2026 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2028 let mayLoad = 1 in {
2029 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2030 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2031 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2032 itins.rm, d>, EVEX_4V, TB;
2033 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2034 (ins RC:$src1, x86scalar_mop:$src2),
2035 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2036 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2037 [(set RC:$dst, (OpNode RC:$src1,
2038 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2039 itins.rm, d>, EVEX_4V, EVEX_B, TB;
2043 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2044 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2045 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2047 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2048 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2049 SSE_ALU_ITINS_P.d, 1>,
2050 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2052 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2053 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2054 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2055 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2056 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2057 SSE_ALU_ITINS_P.d, 1>,
2058 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2060 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2061 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2062 SSE_ALU_ITINS_P.s, 1>,
2063 EVEX_V512, EVEX_CD8<32, CD8VF>;
2064 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2065 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2066 SSE_ALU_ITINS_P.s, 1>,
2067 EVEX_V512, EVEX_CD8<32, CD8VF>;
2069 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2070 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2071 SSE_ALU_ITINS_P.d, 1>,
2072 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2073 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2074 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2075 SSE_ALU_ITINS_P.d, 1>,
2076 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2078 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2079 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2080 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2081 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2082 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2083 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2085 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2086 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2087 SSE_ALU_ITINS_P.d, 0>,
2088 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2089 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2090 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2091 SSE_ALU_ITINS_P.d, 0>,
2092 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2094 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2095 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2096 (i16 -1), FROUND_CURRENT)),
2097 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2099 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2100 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2101 (i8 -1), FROUND_CURRENT)),
2102 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2104 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2105 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2106 (i16 -1), FROUND_CURRENT)),
2107 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2109 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2110 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2111 (i8 -1), FROUND_CURRENT)),
2112 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2113 //===----------------------------------------------------------------------===//
2114 // AVX-512 VPTESTM instructions
2115 //===----------------------------------------------------------------------===//
2117 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2118 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2119 SDNode OpNode, ValueType vt> {
2120 def rr : AVX5128I<opc, MRMSrcReg,
2121 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2122 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2123 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2124 def rm : AVX5128I<opc, MRMSrcMem,
2125 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2126 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2127 [(set KRC:$dst, (OpNode (vt RC:$src1),
2128 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2131 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2132 memopv16i32, X86testm, v16i32>, EVEX_V512,
2133 EVEX_CD8<32, CD8VF>;
2134 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2135 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2136 EVEX_CD8<64, CD8VF>;
2138 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2139 (v16i32 VR512:$src2), (i16 -1))),
2140 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2142 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2143 (v8i64 VR512:$src2), (i8 -1))),
2144 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2145 //===----------------------------------------------------------------------===//
2146 // AVX-512 Shift instructions
2147 //===----------------------------------------------------------------------===//
2148 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2149 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2150 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2151 RegisterClass KRC> {
2152 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2153 (ins RC:$src1, i8imm:$src2),
2154 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2155 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2156 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2157 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2158 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2159 !strconcat(OpcodeStr,
2160 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2161 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2162 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2163 (ins x86memop:$src1, i8imm:$src2),
2164 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2165 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2166 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2167 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2168 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2169 !strconcat(OpcodeStr,
2170 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2171 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2174 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2175 RegisterClass RC, ValueType vt, ValueType SrcVT,
2176 PatFrag bc_frag, RegisterClass KRC> {
2177 // src2 is always 128-bit
2178 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2179 (ins RC:$src1, VR128X:$src2),
2180 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2181 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2182 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2183 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2184 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2185 !strconcat(OpcodeStr,
2186 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2187 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2188 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2189 (ins RC:$src1, i128mem:$src2),
2190 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2191 [(set RC:$dst, (vt (OpNode RC:$src1,
2192 (bc_frag (memopv2i64 addr:$src2)))))],
2193 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2194 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2195 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2196 !strconcat(OpcodeStr,
2197 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2198 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2201 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2202 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2203 EVEX_V512, EVEX_CD8<32, CD8VF>;
2204 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2205 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2206 EVEX_CD8<32, CD8VQ>;
2208 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2209 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2210 EVEX_CD8<64, CD8VF>, VEX_W;
2211 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2212 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2213 EVEX_CD8<64, CD8VQ>, VEX_W;
2215 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2216 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2217 EVEX_CD8<32, CD8VF>;
2218 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2219 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2220 EVEX_CD8<32, CD8VQ>;
2222 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2223 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2224 EVEX_CD8<64, CD8VF>, VEX_W;
2225 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2226 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2227 EVEX_CD8<64, CD8VQ>, VEX_W;
2229 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2230 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2231 EVEX_V512, EVEX_CD8<32, CD8VF>;
2232 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2233 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2234 EVEX_CD8<32, CD8VQ>;
2236 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2237 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2238 EVEX_CD8<64, CD8VF>, VEX_W;
2239 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2240 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2241 EVEX_CD8<64, CD8VQ>, VEX_W;
2243 //===-------------------------------------------------------------------===//
2244 // Variable Bit Shifts
2245 //===-------------------------------------------------------------------===//
2246 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2247 RegisterClass RC, ValueType vt,
2248 X86MemOperand x86memop, PatFrag mem_frag> {
2249 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2250 (ins RC:$src1, RC:$src2),
2251 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2253 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2255 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2256 (ins RC:$src1, x86memop:$src2),
2257 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2259 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2263 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2264 i512mem, memopv16i32>, EVEX_V512,
2265 EVEX_CD8<32, CD8VF>;
2266 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2267 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2268 EVEX_CD8<64, CD8VF>;
2269 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2270 i512mem, memopv16i32>, EVEX_V512,
2271 EVEX_CD8<32, CD8VF>;
2272 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2273 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2274 EVEX_CD8<64, CD8VF>;
2275 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2276 i512mem, memopv16i32>, EVEX_V512,
2277 EVEX_CD8<32, CD8VF>;
2278 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2279 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2280 EVEX_CD8<64, CD8VF>;
2282 //===----------------------------------------------------------------------===//
2283 // AVX-512 - MOVDDUP
2284 //===----------------------------------------------------------------------===//
2286 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2287 X86MemOperand x86memop, PatFrag memop_frag> {
2288 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2289 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2290 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2291 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2292 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2294 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2297 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2298 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2299 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2300 (VMOVDDUPZrm addr:$src)>;
2302 //===---------------------------------------------------------------------===//
2303 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2304 //===---------------------------------------------------------------------===//
2305 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2306 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2307 X86MemOperand x86memop> {
2308 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2309 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2310 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2312 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2313 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2314 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2317 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2318 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2319 EVEX_CD8<32, CD8VF>;
2320 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2321 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2322 EVEX_CD8<32, CD8VF>;
2324 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2325 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2326 (VMOVSHDUPZrm addr:$src)>;
2327 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2328 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2329 (VMOVSLDUPZrm addr:$src)>;
2331 //===----------------------------------------------------------------------===//
2332 // Move Low to High and High to Low packed FP Instructions
2333 //===----------------------------------------------------------------------===//
2334 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2335 (ins VR128X:$src1, VR128X:$src2),
2336 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2337 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2338 IIC_SSE_MOV_LH>, EVEX_4V;
2339 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2340 (ins VR128X:$src1, VR128X:$src2),
2341 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2342 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2343 IIC_SSE_MOV_LH>, EVEX_4V;
2345 let Predicates = [HasAVX512] in {
2347 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2348 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2349 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2350 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2353 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2354 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2357 //===----------------------------------------------------------------------===//
2358 // FMA - Fused Multiply Operations
2360 let Constraints = "$src1 = $dst" in {
2361 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2362 RegisterClass RC, X86MemOperand x86memop,
2363 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2364 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2365 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, RC:$src3),
2367 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2368 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2371 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2372 (ins RC:$src1, RC:$src2, x86memop:$src3),
2373 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2374 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2375 (mem_frag addr:$src3))))]>;
2376 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2377 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2378 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2379 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2380 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2381 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2383 } // Constraints = "$src1 = $dst"
2385 let ExeDomain = SSEPackedSingle in {
2386 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2387 memopv16f32, f32mem, loadf32, "{1to16}",
2388 X86Fmadd, v16f32>, EVEX_V512,
2389 EVEX_CD8<32, CD8VF>;
2390 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2391 memopv16f32, f32mem, loadf32, "{1to16}",
2392 X86Fmsub, v16f32>, EVEX_V512,
2393 EVEX_CD8<32, CD8VF>;
2394 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2395 memopv16f32, f32mem, loadf32, "{1to16}",
2396 X86Fmaddsub, v16f32>,
2397 EVEX_V512, EVEX_CD8<32, CD8VF>;
2398 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2399 memopv16f32, f32mem, loadf32, "{1to16}",
2400 X86Fmsubadd, v16f32>,
2401 EVEX_V512, EVEX_CD8<32, CD8VF>;
2402 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2403 memopv16f32, f32mem, loadf32, "{1to16}",
2404 X86Fnmadd, v16f32>, EVEX_V512,
2405 EVEX_CD8<32, CD8VF>;
2406 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2407 memopv16f32, f32mem, loadf32, "{1to16}",
2408 X86Fnmsub, v16f32>, EVEX_V512,
2409 EVEX_CD8<32, CD8VF>;
2411 let ExeDomain = SSEPackedDouble in {
2412 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2413 memopv8f64, f64mem, loadf64, "{1to8}",
2414 X86Fmadd, v8f64>, EVEX_V512,
2415 VEX_W, EVEX_CD8<64, CD8VF>;
2416 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2417 memopv8f64, f64mem, loadf64, "{1to8}",
2418 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2419 EVEX_CD8<64, CD8VF>;
2420 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2421 memopv8f64, f64mem, loadf64, "{1to8}",
2422 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2423 EVEX_CD8<64, CD8VF>;
2424 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2425 memopv8f64, f64mem, loadf64, "{1to8}",
2426 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2427 EVEX_CD8<64, CD8VF>;
2428 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2429 memopv8f64, f64mem, loadf64, "{1to8}",
2430 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2431 EVEX_CD8<64, CD8VF>;
2432 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2433 memopv8f64, f64mem, loadf64, "{1to8}",
2434 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2435 EVEX_CD8<64, CD8VF>;
2438 let Constraints = "$src1 = $dst" in {
2439 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2440 RegisterClass RC, X86MemOperand x86memop,
2441 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2442 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2444 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2445 (ins RC:$src1, RC:$src3, x86memop:$src2),
2446 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2447 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2448 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2449 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2450 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2451 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2452 [(set RC:$dst, (OpNode RC:$src1,
2453 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2455 } // Constraints = "$src1 = $dst"
2458 let ExeDomain = SSEPackedSingle in {
2459 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2460 memopv16f32, f32mem, loadf32, "{1to16}",
2461 X86Fmadd, v16f32>, EVEX_V512,
2462 EVEX_CD8<32, CD8VF>;
2463 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2464 memopv16f32, f32mem, loadf32, "{1to16}",
2465 X86Fmsub, v16f32>, EVEX_V512,
2466 EVEX_CD8<32, CD8VF>;
2467 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2468 memopv16f32, f32mem, loadf32, "{1to16}",
2469 X86Fmaddsub, v16f32>,
2470 EVEX_V512, EVEX_CD8<32, CD8VF>;
2471 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2472 memopv16f32, f32mem, loadf32, "{1to16}",
2473 X86Fmsubadd, v16f32>,
2474 EVEX_V512, EVEX_CD8<32, CD8VF>;
2475 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2476 memopv16f32, f32mem, loadf32, "{1to16}",
2477 X86Fnmadd, v16f32>, EVEX_V512,
2478 EVEX_CD8<32, CD8VF>;
2479 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2480 memopv16f32, f32mem, loadf32, "{1to16}",
2481 X86Fnmsub, v16f32>, EVEX_V512,
2482 EVEX_CD8<32, CD8VF>;
2484 let ExeDomain = SSEPackedDouble in {
2485 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2486 memopv8f64, f64mem, loadf64, "{1to8}",
2487 X86Fmadd, v8f64>, EVEX_V512,
2488 VEX_W, EVEX_CD8<64, CD8VF>;
2489 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2490 memopv8f64, f64mem, loadf64, "{1to8}",
2491 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2492 EVEX_CD8<64, CD8VF>;
2493 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2494 memopv8f64, f64mem, loadf64, "{1to8}",
2495 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2496 EVEX_CD8<64, CD8VF>;
2497 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2498 memopv8f64, f64mem, loadf64, "{1to8}",
2499 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2500 EVEX_CD8<64, CD8VF>;
2501 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2502 memopv8f64, f64mem, loadf64, "{1to8}",
2503 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2504 EVEX_CD8<64, CD8VF>;
2505 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2506 memopv8f64, f64mem, loadf64, "{1to8}",
2507 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2508 EVEX_CD8<64, CD8VF>;
2512 let Constraints = "$src1 = $dst" in {
2513 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2514 RegisterClass RC, ValueType OpVT,
2515 X86MemOperand x86memop, Operand memop,
2517 let isCommutable = 1 in
2518 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2519 (ins RC:$src1, RC:$src2, RC:$src3),
2520 !strconcat(OpcodeStr,
2521 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2523 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2525 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins RC:$src1, RC:$src2, f128mem:$src3),
2527 !strconcat(OpcodeStr,
2528 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2530 (OpVT (OpNode RC:$src2, RC:$src1,
2531 (mem_frag addr:$src3))))]>;
2534 } // Constraints = "$src1 = $dst"
2536 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2537 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2538 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2539 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2540 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2541 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2542 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2543 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2544 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2545 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2546 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2547 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2548 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2549 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2550 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2551 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2553 //===----------------------------------------------------------------------===//
2554 // AVX-512 Scalar convert from sign integer to float/double
2555 //===----------------------------------------------------------------------===//
2557 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2558 X86MemOperand x86memop, string asm> {
2559 let hasSideEffects = 0 in {
2560 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2561 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2564 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2565 (ins DstRC:$src1, x86memop:$src),
2566 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2568 } // hasSideEffects = 0
2570 let Predicates = [HasAVX512] in {
2571 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2572 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2573 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2574 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2575 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2576 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2577 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2578 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2580 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2581 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2582 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2583 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2584 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2585 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2586 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2587 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2589 def : Pat<(f32 (sint_to_fp GR32:$src)),
2590 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2591 def : Pat<(f32 (sint_to_fp GR64:$src)),
2592 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2593 def : Pat<(f64 (sint_to_fp GR32:$src)),
2594 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2595 def : Pat<(f64 (sint_to_fp GR64:$src)),
2596 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2598 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2599 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2600 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2601 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2602 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2603 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2604 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2605 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2607 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2608 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2609 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2610 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2611 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2612 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2613 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2614 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2616 def : Pat<(f32 (uint_to_fp GR32:$src)),
2617 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2618 def : Pat<(f32 (uint_to_fp GR64:$src)),
2619 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2620 def : Pat<(f64 (uint_to_fp GR32:$src)),
2621 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2622 def : Pat<(f64 (uint_to_fp GR64:$src)),
2623 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2626 //===----------------------------------------------------------------------===//
2627 // AVX-512 Scalar convert from float/double to integer
2628 //===----------------------------------------------------------------------===//
2629 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2630 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2632 let hasSideEffects = 0 in {
2633 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2634 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2635 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2636 Requires<[HasAVX512]>;
2638 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2639 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2640 Requires<[HasAVX512]>;
2641 } // hasSideEffects = 0
2643 let Predicates = [HasAVX512] in {
2644 // Convert float/double to signed/unsigned int 32/64
2645 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2646 ssmem, sse_load_f32, "cvtss2si">,
2647 XS, EVEX_CD8<32, CD8VT1>;
2648 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2649 ssmem, sse_load_f32, "cvtss2si">,
2650 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2651 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2652 ssmem, sse_load_f32, "cvtss2usi">,
2653 XS, EVEX_CD8<32, CD8VT1>;
2654 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2655 int_x86_avx512_cvtss2usi64, ssmem,
2656 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2657 EVEX_CD8<32, CD8VT1>;
2658 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2659 sdmem, sse_load_f64, "cvtsd2si">,
2660 XD, EVEX_CD8<64, CD8VT1>;
2661 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2662 sdmem, sse_load_f64, "cvtsd2si">,
2663 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2664 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2665 sdmem, sse_load_f64, "cvtsd2usi">,
2666 XD, EVEX_CD8<64, CD8VT1>;
2667 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2668 int_x86_avx512_cvtsd2usi64, sdmem,
2669 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2670 EVEX_CD8<64, CD8VT1>;
2672 let isCodeGenOnly = 1 in {
2673 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2674 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2675 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2676 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2677 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2678 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2679 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2680 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2681 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2682 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2683 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2684 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2686 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2687 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2688 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2689 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2690 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2691 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2692 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2693 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2694 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2695 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2696 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2697 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2698 } // isCodeGenOnly = 1
2700 // Convert float/double to signed/unsigned int 32/64 with truncation
2701 let isCodeGenOnly = 1 in {
2702 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2703 ssmem, sse_load_f32, "cvttss2si">,
2704 XS, EVEX_CD8<32, CD8VT1>;
2705 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2706 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2707 "cvttss2si">, XS, VEX_W,
2708 EVEX_CD8<32, CD8VT1>;
2709 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2710 sdmem, sse_load_f64, "cvttsd2si">, XD,
2711 EVEX_CD8<64, CD8VT1>;
2712 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2713 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2714 "cvttsd2si">, XD, VEX_W,
2715 EVEX_CD8<64, CD8VT1>;
2716 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2717 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2718 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2719 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2720 int_x86_avx512_cvttss2usi64, ssmem,
2721 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2722 EVEX_CD8<32, CD8VT1>;
2723 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2724 int_x86_avx512_cvttsd2usi,
2725 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2726 EVEX_CD8<64, CD8VT1>;
2727 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2728 int_x86_avx512_cvttsd2usi64, sdmem,
2729 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2730 EVEX_CD8<64, CD8VT1>;
2731 } // isCodeGenOnly = 1
2733 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2734 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2736 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2737 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2738 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2739 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2740 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2741 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2744 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2745 loadf32, "cvttss2si">, XS,
2746 EVEX_CD8<32, CD8VT1>;
2747 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2748 loadf32, "cvttss2usi">, XS,
2749 EVEX_CD8<32, CD8VT1>;
2750 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2751 loadf32, "cvttss2si">, XS, VEX_W,
2752 EVEX_CD8<32, CD8VT1>;
2753 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2754 loadf32, "cvttss2usi">, XS, VEX_W,
2755 EVEX_CD8<32, CD8VT1>;
2756 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2757 loadf64, "cvttsd2si">, XD,
2758 EVEX_CD8<64, CD8VT1>;
2759 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2760 loadf64, "cvttsd2usi">, XD,
2761 EVEX_CD8<64, CD8VT1>;
2762 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2763 loadf64, "cvttsd2si">, XD, VEX_W,
2764 EVEX_CD8<64, CD8VT1>;
2765 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2766 loadf64, "cvttsd2usi">, XD, VEX_W,
2767 EVEX_CD8<64, CD8VT1>;
2769 //===----------------------------------------------------------------------===//
2770 // AVX-512 Convert form float to double and back
2771 //===----------------------------------------------------------------------===//
2772 let hasSideEffects = 0 in {
2773 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2774 (ins FR32X:$src1, FR32X:$src2),
2775 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2776 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2778 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2779 (ins FR32X:$src1, f32mem:$src2),
2780 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2781 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2782 EVEX_CD8<32, CD8VT1>;
2784 // Convert scalar double to scalar single
2785 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2786 (ins FR64X:$src1, FR64X:$src2),
2787 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2788 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2790 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2791 (ins FR64X:$src1, f64mem:$src2),
2792 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2793 []>, EVEX_4V, VEX_LIG, VEX_W,
2794 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2797 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2798 Requires<[HasAVX512]>;
2799 def : Pat<(fextend (loadf32 addr:$src)),
2800 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2802 def : Pat<(extloadf32 addr:$src),
2803 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2804 Requires<[HasAVX512, OptForSize]>;
2806 def : Pat<(extloadf32 addr:$src),
2807 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2808 Requires<[HasAVX512, OptForSpeed]>;
2810 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2811 Requires<[HasAVX512]>;
2813 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2814 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2815 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2817 let hasSideEffects = 0 in {
2818 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2819 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2821 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2822 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2823 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2824 [], d>, EVEX, EVEX_B, EVEX_RC;
2826 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2827 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2829 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2830 } // hasSideEffects = 0
2833 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2834 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2835 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2837 let hasSideEffects = 0 in {
2838 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2839 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2841 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2843 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2844 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2846 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2847 } // hasSideEffects = 0
2850 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2851 memopv8f64, f512mem, v8f32, v8f64,
2852 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2853 EVEX_CD8<64, CD8VF>;
2855 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2856 memopv4f64, f256mem, v8f64, v8f32,
2857 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2858 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2859 (VCVTPS2PDZrm addr:$src)>;
2861 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2862 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2863 (VCVTPD2PSZrr VR512:$src)>;
2865 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2866 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2867 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2869 //===----------------------------------------------------------------------===//
2870 // AVX-512 Vector convert from sign integer to float/double
2871 //===----------------------------------------------------------------------===//
2873 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2874 memopv8i64, i512mem, v16f32, v16i32,
2875 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2877 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2878 memopv4i64, i256mem, v8f64, v8i32,
2879 SSEPackedDouble>, EVEX_V512, XS,
2880 EVEX_CD8<32, CD8VH>;
2882 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2883 memopv16f32, f512mem, v16i32, v16f32,
2884 SSEPackedSingle>, EVEX_V512, XS,
2885 EVEX_CD8<32, CD8VF>;
2887 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2888 memopv8f64, f512mem, v8i32, v8f64,
2889 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2890 EVEX_CD8<64, CD8VF>;
2892 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2893 memopv16f32, f512mem, v16i32, v16f32,
2894 SSEPackedSingle>, EVEX_V512,
2895 EVEX_CD8<32, CD8VF>;
2897 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2898 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2899 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2900 (VCVTTPS2UDQZrr VR512:$src)>;
2902 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2903 memopv8f64, f512mem, v8i32, v8f64,
2904 SSEPackedDouble>, EVEX_V512, VEX_W,
2905 EVEX_CD8<64, CD8VF>;
2907 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2908 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2909 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2910 (VCVTTPD2UDQZrr VR512:$src)>;
2912 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2913 memopv4i64, f256mem, v8f64, v8i32,
2914 SSEPackedDouble>, EVEX_V512, XS,
2915 EVEX_CD8<32, CD8VH>;
2917 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2918 memopv16i32, f512mem, v16f32, v16i32,
2919 SSEPackedSingle>, EVEX_V512, XD,
2920 EVEX_CD8<32, CD8VF>;
2922 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2923 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2924 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2927 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2928 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2929 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2930 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2931 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2932 (VCVTDQ2PDZrr VR256X:$src)>;
2933 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2934 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2935 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2936 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2937 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2938 (VCVTUDQ2PDZrr VR256X:$src)>;
2940 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2941 RegisterClass DstRC, PatFrag mem_frag,
2942 X86MemOperand x86memop, Domain d> {
2943 let hasSideEffects = 0 in {
2944 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2945 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2947 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2948 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2949 [], d>, EVEX, EVEX_B, EVEX_RC;
2951 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2952 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2954 } // hasSideEffects = 0
2957 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2958 memopv16f32, f512mem, SSEPackedSingle>, PD,
2959 EVEX_V512, EVEX_CD8<32, CD8VF>;
2960 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2961 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2962 EVEX_V512, EVEX_CD8<64, CD8VF>;
2964 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2965 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2966 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2968 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2969 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2970 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2972 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2973 memopv16f32, f512mem, SSEPackedSingle>,
2974 EVEX_V512, EVEX_CD8<32, CD8VF>;
2975 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2976 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2977 EVEX_V512, EVEX_CD8<64, CD8VF>;
2979 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2980 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2981 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2983 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2984 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2985 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2987 let Predicates = [HasAVX512] in {
2988 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2989 (VCVTPD2PSZrm addr:$src)>;
2990 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2991 (VCVTPS2PDZrm addr:$src)>;
2994 //===----------------------------------------------------------------------===//
2995 // Half precision conversion instructions
2996 //===----------------------------------------------------------------------===//
2997 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2998 X86MemOperand x86memop, Intrinsic Int> {
2999 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3000 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3001 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
3002 let hasSideEffects = 0, mayLoad = 1 in
3003 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3004 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3007 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
3008 X86MemOperand x86memop, Intrinsic Int> {
3009 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3010 (ins srcRC:$src1, i32i8imm:$src2),
3011 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3012 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
3013 let hasSideEffects = 0, mayStore = 1 in
3014 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3015 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3016 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3019 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
3020 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
3021 EVEX_CD8<32, CD8VH>;
3022 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
3023 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
3024 EVEX_CD8<32, CD8VH>;
3026 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3027 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3028 "ucomiss">, TB, EVEX, VEX_LIG,
3029 EVEX_CD8<32, CD8VT1>;
3030 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3031 "ucomisd">, PD, EVEX,
3032 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3033 let Pattern = []<dag> in {
3034 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3035 "comiss">, TB, EVEX, VEX_LIG,
3036 EVEX_CD8<32, CD8VT1>;
3037 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3038 "comisd">, PD, EVEX,
3039 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3041 let isCodeGenOnly = 1 in {
3042 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3043 load, "ucomiss">, TB, EVEX, VEX_LIG,
3044 EVEX_CD8<32, CD8VT1>;
3045 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3046 load, "ucomisd">, PD, EVEX,
3047 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3049 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3050 load, "comiss">, TB, EVEX, VEX_LIG,
3051 EVEX_CD8<32, CD8VT1>;
3052 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3053 load, "comisd">, PD, EVEX,
3054 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3058 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3059 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3060 X86MemOperand x86memop> {
3061 let hasSideEffects = 0 in {
3062 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3063 (ins RC:$src1, RC:$src2),
3064 !strconcat(OpcodeStr,
3065 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3066 let mayLoad = 1 in {
3067 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3068 (ins RC:$src1, x86memop:$src2),
3069 !strconcat(OpcodeStr,
3070 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3075 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3076 EVEX_CD8<32, CD8VT1>;
3077 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3078 VEX_W, EVEX_CD8<64, CD8VT1>;
3079 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3080 EVEX_CD8<32, CD8VT1>;
3081 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3082 VEX_W, EVEX_CD8<64, CD8VT1>;
3084 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3085 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3086 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3087 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3089 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3090 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3091 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3092 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3094 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3095 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3096 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3097 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3099 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3100 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3101 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3102 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3104 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3105 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3106 RegisterClass RC, X86MemOperand x86memop,
3107 PatFrag mem_frag, ValueType OpVt> {
3108 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3109 !strconcat(OpcodeStr,
3110 " \t{$src, $dst|$dst, $src}"),
3111 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3113 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3114 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3115 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3118 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3119 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3120 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3121 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3122 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3123 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3124 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3125 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3127 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3128 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3129 (VRSQRT14PSZr VR512:$src)>;
3130 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3131 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3132 (VRSQRT14PDZr VR512:$src)>;
3134 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3135 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3136 (VRCP14PSZr VR512:$src)>;
3137 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3138 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3139 (VRCP14PDZr VR512:$src)>;
3141 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3142 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3143 X86MemOperand x86memop> {
3144 let hasSideEffects = 0, Predicates = [HasERI] in {
3145 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3146 (ins RC:$src1, RC:$src2),
3147 !strconcat(OpcodeStr,
3148 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3149 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3150 (ins RC:$src1, RC:$src2),
3151 !strconcat(OpcodeStr,
3152 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3153 []>, EVEX_4V, EVEX_B;
3154 let mayLoad = 1 in {
3155 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3156 (ins RC:$src1, x86memop:$src2),
3157 !strconcat(OpcodeStr,
3158 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3163 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3164 EVEX_CD8<32, CD8VT1>;
3165 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3166 VEX_W, EVEX_CD8<64, CD8VT1>;
3167 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3168 EVEX_CD8<32, CD8VT1>;
3169 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3170 VEX_W, EVEX_CD8<64, CD8VT1>;
3172 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3173 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3175 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3176 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3178 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3179 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3181 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3182 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3184 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3185 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3187 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3188 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3190 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3191 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3193 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3194 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3196 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3197 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3198 RegisterClass RC, X86MemOperand x86memop> {
3199 let hasSideEffects = 0, Predicates = [HasERI] in {
3200 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3201 !strconcat(OpcodeStr,
3202 " \t{$src, $dst|$dst, $src}"),
3204 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3205 !strconcat(OpcodeStr,
3206 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3208 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3209 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3213 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3214 EVEX_V512, EVEX_CD8<32, CD8VF>;
3215 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3216 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3217 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3218 EVEX_V512, EVEX_CD8<32, CD8VF>;
3219 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3220 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3222 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3223 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3224 (VRSQRT28PSZrb VR512:$src)>;
3225 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3226 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3227 (VRSQRT28PDZrb VR512:$src)>;
3229 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3230 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3231 (VRCP28PSZrb VR512:$src)>;
3232 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3233 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3234 (VRCP28PDZrb VR512:$src)>;
3236 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3237 Intrinsic V16F32Int, Intrinsic V8F64Int,
3238 OpndItins itins_s, OpndItins itins_d> {
3239 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3240 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3241 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3245 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3246 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3248 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3249 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3251 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3252 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3253 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3257 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3258 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3259 [(set VR512:$dst, (OpNode
3260 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3261 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3263 let isCodeGenOnly = 1 in {
3264 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3265 !strconcat(OpcodeStr,
3266 "ps\t{$src, $dst|$dst, $src}"),
3267 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3269 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3270 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3272 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3275 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3276 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3277 EVEX, EVEX_V512, VEX_W;
3278 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3279 !strconcat(OpcodeStr,
3280 "pd\t{$src, $dst|$dst, $src}"),
3281 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3282 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3283 } // isCodeGenOnly = 1
3286 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3287 Intrinsic F32Int, Intrinsic F64Int,
3288 OpndItins itins_s, OpndItins itins_d> {
3289 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3290 (ins FR32X:$src1, FR32X:$src2),
3291 !strconcat(OpcodeStr,
3292 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3293 [], itins_s.rr>, XS, EVEX_4V;
3294 let isCodeGenOnly = 1 in
3295 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3296 (ins VR128X:$src1, VR128X:$src2),
3297 !strconcat(OpcodeStr,
3298 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3300 (F32Int VR128X:$src1, VR128X:$src2))],
3301 itins_s.rr>, XS, EVEX_4V;
3302 let mayLoad = 1 in {
3303 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3304 (ins FR32X:$src1, f32mem:$src2),
3305 !strconcat(OpcodeStr,
3306 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3307 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3308 let isCodeGenOnly = 1 in
3309 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3310 (ins VR128X:$src1, ssmem:$src2),
3311 !strconcat(OpcodeStr,
3312 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3314 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3315 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3317 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3318 (ins FR64X:$src1, FR64X:$src2),
3319 !strconcat(OpcodeStr,
3320 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3322 let isCodeGenOnly = 1 in
3323 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3324 (ins VR128X:$src1, VR128X:$src2),
3325 !strconcat(OpcodeStr,
3326 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3328 (F64Int VR128X:$src1, VR128X:$src2))],
3329 itins_s.rr>, XD, EVEX_4V, VEX_W;
3330 let mayLoad = 1 in {
3331 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3332 (ins FR64X:$src1, f64mem:$src2),
3333 !strconcat(OpcodeStr,
3334 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3335 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3336 let isCodeGenOnly = 1 in
3337 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3338 (ins VR128X:$src1, sdmem:$src2),
3339 !strconcat(OpcodeStr,
3340 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3342 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3343 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3348 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3349 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3350 SSE_SQRTSS, SSE_SQRTSD>,
3351 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3352 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3353 SSE_SQRTPS, SSE_SQRTPD>;
3355 let Predicates = [HasAVX512] in {
3356 def : Pat<(f32 (fsqrt FR32X:$src)),
3357 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3358 def : Pat<(f32 (fsqrt (load addr:$src))),
3359 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3360 Requires<[OptForSize]>;
3361 def : Pat<(f64 (fsqrt FR64X:$src)),
3362 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3363 def : Pat<(f64 (fsqrt (load addr:$src))),
3364 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3365 Requires<[OptForSize]>;
3367 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3368 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3369 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3370 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3371 Requires<[OptForSize]>;
3373 def : Pat<(f32 (X86frcp FR32X:$src)),
3374 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3375 def : Pat<(f32 (X86frcp (load addr:$src))),
3376 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3377 Requires<[OptForSize]>;
3379 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3380 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3381 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3383 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3384 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3386 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3387 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3388 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3390 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3391 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3395 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3396 X86MemOperand x86memop, RegisterClass RC,
3397 PatFrag mem_frag32, PatFrag mem_frag64,
3398 Intrinsic V4F32Int, Intrinsic V2F64Int,
3400 let ExeDomain = SSEPackedSingle in {
3401 // Intrinsic operation, reg.
3402 // Vector intrinsic operation, reg
3403 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3404 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3405 !strconcat(OpcodeStr,
3406 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3407 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3409 // Vector intrinsic operation, mem
3410 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3411 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3412 !strconcat(OpcodeStr,
3413 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3415 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3416 EVEX_CD8<32, VForm>;
3417 } // ExeDomain = SSEPackedSingle
3419 let ExeDomain = SSEPackedDouble in {
3420 // Vector intrinsic operation, reg
3421 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3422 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3423 !strconcat(OpcodeStr,
3424 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3425 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3427 // Vector intrinsic operation, mem
3428 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3429 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3430 !strconcat(OpcodeStr,
3431 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3433 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3434 EVEX_CD8<64, VForm>;
3435 } // ExeDomain = SSEPackedDouble
3438 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3442 let ExeDomain = GenericDomain in {
3444 let hasSideEffects = 0 in
3445 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3446 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3447 !strconcat(OpcodeStr,
3448 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3451 // Intrinsic operation, reg.
3452 let isCodeGenOnly = 1 in
3453 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3454 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3455 !strconcat(OpcodeStr,
3456 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3457 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3459 // Intrinsic operation, mem.
3460 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3461 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3462 !strconcat(OpcodeStr,
3463 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3464 [(set VR128X:$dst, (F32Int VR128X:$src1,
3465 sse_load_f32:$src2, imm:$src3))]>,
3466 EVEX_CD8<32, CD8VT1>;
3469 let hasSideEffects = 0 in
3470 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3471 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3472 !strconcat(OpcodeStr,
3473 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3476 // Intrinsic operation, reg.
3477 let isCodeGenOnly = 1 in
3478 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3479 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3480 !strconcat(OpcodeStr,
3481 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3482 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3485 // Intrinsic operation, mem.
3486 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3487 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3488 !strconcat(OpcodeStr,
3489 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3491 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3492 VEX_W, EVEX_CD8<64, CD8VT1>;
3493 } // ExeDomain = GenericDomain
3496 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3497 X86MemOperand x86memop, RegisterClass RC,
3498 PatFrag mem_frag, Domain d> {
3499 let ExeDomain = d in {
3500 // Intrinsic operation, reg.
3501 // Vector intrinsic operation, reg
3502 def r : AVX512AIi8<opc, MRMSrcReg,
3503 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3504 !strconcat(OpcodeStr,
3505 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3508 // Vector intrinsic operation, mem
3509 def m : AVX512AIi8<opc, MRMSrcMem,
3510 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3511 !strconcat(OpcodeStr,
3512 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3518 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3519 memopv16f32, SSEPackedSingle>, EVEX_V512,
3520 EVEX_CD8<32, CD8VF>;
3522 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3523 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3525 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3528 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3529 memopv8f64, SSEPackedDouble>, EVEX_V512,
3530 VEX_W, EVEX_CD8<64, CD8VF>;
3532 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3533 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3535 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3537 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3538 Operand x86memop, RegisterClass RC, Domain d> {
3539 let ExeDomain = d in {
3540 def r : AVX512AIi8<opc, MRMSrcReg,
3541 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3542 !strconcat(OpcodeStr,
3543 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3546 def m : AVX512AIi8<opc, MRMSrcMem,
3547 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3548 !strconcat(OpcodeStr,
3549 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3554 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3555 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3557 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3558 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3560 def : Pat<(ffloor FR32X:$src),
3561 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3562 def : Pat<(f64 (ffloor FR64X:$src)),
3563 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3564 def : Pat<(f32 (fnearbyint FR32X:$src)),
3565 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3566 def : Pat<(f64 (fnearbyint FR64X:$src)),
3567 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3568 def : Pat<(f32 (fceil FR32X:$src)),
3569 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3570 def : Pat<(f64 (fceil FR64X:$src)),
3571 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3572 def : Pat<(f32 (frint FR32X:$src)),
3573 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3574 def : Pat<(f64 (frint FR64X:$src)),
3575 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3576 def : Pat<(f32 (ftrunc FR32X:$src)),
3577 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3578 def : Pat<(f64 (ftrunc FR64X:$src)),
3579 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3581 def : Pat<(v16f32 (ffloor VR512:$src)),
3582 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3583 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3584 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3585 def : Pat<(v16f32 (fceil VR512:$src)),
3586 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3587 def : Pat<(v16f32 (frint VR512:$src)),
3588 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3589 def : Pat<(v16f32 (ftrunc VR512:$src)),
3590 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3592 def : Pat<(v8f64 (ffloor VR512:$src)),
3593 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3594 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3595 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3596 def : Pat<(v8f64 (fceil VR512:$src)),
3597 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3598 def : Pat<(v8f64 (frint VR512:$src)),
3599 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3600 def : Pat<(v8f64 (ftrunc VR512:$src)),
3601 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3603 //-------------------------------------------------
3604 // Integer truncate and extend operations
3605 //-------------------------------------------------
3607 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3608 RegisterClass dstRC, RegisterClass srcRC,
3609 RegisterClass KRC, X86MemOperand x86memop> {
3610 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3612 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3615 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3616 (ins KRC:$mask, srcRC:$src),
3617 !strconcat(OpcodeStr,
3618 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3621 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3622 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3625 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3626 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3627 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3628 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3629 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3630 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3631 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3632 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3633 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3634 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3635 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3636 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3637 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3638 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3639 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3640 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3641 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3642 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3643 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3644 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3645 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3646 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3647 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3648 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3649 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3650 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3651 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3652 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3653 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3654 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3656 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3657 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3658 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3659 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3660 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3662 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3663 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3664 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3665 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3666 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3667 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3668 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3669 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3672 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3673 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3674 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3676 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3678 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3679 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3680 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3681 (ins x86memop:$src),
3682 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3684 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3688 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3689 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3691 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3692 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3694 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3695 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3696 EVEX_CD8<16, CD8VH>;
3697 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3698 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3699 EVEX_CD8<16, CD8VQ>;
3700 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3701 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3702 EVEX_CD8<32, CD8VH>;
3704 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3705 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3707 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3708 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3710 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3711 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3712 EVEX_CD8<16, CD8VH>;
3713 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3714 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3715 EVEX_CD8<16, CD8VQ>;
3716 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3717 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3718 EVEX_CD8<32, CD8VH>;
3720 //===----------------------------------------------------------------------===//
3721 // GATHER - SCATTER Operations
3723 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3724 RegisterClass RC, X86MemOperand memop> {
3726 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3727 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3728 (ins RC:$src1, KRC:$mask, memop:$src2),
3729 !strconcat(OpcodeStr,
3730 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3733 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3734 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3735 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3736 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3738 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3739 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3740 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3741 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3743 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3744 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3745 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3746 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3748 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3749 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3750 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3751 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3753 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3754 RegisterClass RC, X86MemOperand memop> {
3755 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3756 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3757 (ins memop:$dst, KRC:$mask, RC:$src2),
3758 !strconcat(OpcodeStr,
3759 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3763 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3764 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3765 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3766 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3768 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3769 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3770 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3771 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3773 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3774 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3775 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3776 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3778 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3779 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3780 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3781 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3783 //===----------------------------------------------------------------------===//
3784 // VSHUFPS - VSHUFPD Operations
3786 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3787 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3789 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3790 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3791 !strconcat(OpcodeStr,
3792 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3793 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3794 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3795 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3796 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3797 (ins RC:$src1, RC:$src2, i8imm:$src3),
3798 !strconcat(OpcodeStr,
3799 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3800 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3801 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3802 EVEX_4V, Sched<[WriteShuffle]>;
3805 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3806 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3807 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3808 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3810 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3811 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3812 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3813 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3814 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3816 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3817 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3818 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3819 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3820 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3822 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3823 X86MemOperand x86memop> {
3824 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3825 (ins RC:$src1, RC:$src2, i8imm:$src3),
3826 !strconcat(OpcodeStr,
3827 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3830 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3831 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3832 !strconcat(OpcodeStr,
3833 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3836 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3837 EVEX_V512, EVEX_CD8<32, CD8VF>;
3838 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3839 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3841 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3842 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3843 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3844 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3845 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3846 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3847 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3848 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3850 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3851 X86MemOperand x86memop> {
3852 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3853 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3855 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3856 (ins x86memop:$src),
3857 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3861 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3862 EVEX_CD8<32, CD8VF>;
3863 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3864 EVEX_CD8<64, CD8VF>;
3866 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3867 (v16i32 immAllZerosV), (i16 -1))),
3868 (VPABSDrr VR512:$src)>;
3869 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3870 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3871 (VPABSQrr VR512:$src)>;
3873 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3874 RegisterClass RC, RegisterClass KRC,
3875 X86MemOperand x86memop,
3876 X86MemOperand x86scalar_mop, string BrdcstStr> {
3877 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3879 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3881 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3882 (ins x86memop:$src),
3883 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3885 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3886 (ins x86scalar_mop:$src),
3887 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3888 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3890 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3891 (ins KRC:$mask, RC:$src),
3892 !strconcat(OpcodeStr,
3893 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3895 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3896 (ins KRC:$mask, x86memop:$src),
3897 !strconcat(OpcodeStr,
3898 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3900 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3901 (ins KRC:$mask, x86scalar_mop:$src),
3902 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3903 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3905 []>, EVEX, EVEX_KZ, EVEX_B;
3907 let Constraints = "$src1 = $dst" in {
3908 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3909 (ins RC:$src1, KRC:$mask, RC:$src2),
3910 !strconcat(OpcodeStr,
3911 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3913 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3914 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3915 !strconcat(OpcodeStr,
3916 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3918 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3919 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3920 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3921 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3922 []>, EVEX, EVEX_K, EVEX_B;
3926 let Predicates = [HasCDI] in {
3927 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3928 i512mem, i32mem, "{1to16}">,
3929 EVEX_V512, EVEX_CD8<32, CD8VF>;
3932 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3933 i512mem, i64mem, "{1to8}">,
3934 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3938 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3940 (VPCONFLICTDrrk VR512:$src1,
3941 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3943 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3945 (VPCONFLICTQrrk VR512:$src1,
3946 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;