1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
811 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
812 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
814 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
815 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
816 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
819 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
820 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
821 (DestInfo.VT (X86VBroadcast
822 (SrcInfo.ScalarLdFrag addr:$src)))>,
823 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
842 v4f32x_info, v4f32x_info>, EVEX_V128;
846 let ExeDomain = SSEPackedDouble in {
847 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
848 avx512vl_f64_info>, VEX_W;
851 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
852 // Later, we can canonize broadcast instructions before ISel phase and
853 // eliminate additional patterns on ISel.
854 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
855 // representations of source
856 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
857 X86VectorVTInfo _, RegisterClass SrcRC_v,
858 RegisterClass SrcRC_s> {
859 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
860 (!cast<Instruction>(InstName##"r")
861 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
863 let AddedComplexity = 30 in {
864 def : Pat<(_.VT (vselect _.KRCWM:$mask,
865 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
866 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
867 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
869 def : Pat<(_.VT(vselect _.KRCWM:$mask,
870 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
871 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
872 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
876 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
878 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
881 let Predicates = [HasVLX] in {
882 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
883 v8f32x_info, VR128X, FR32X>;
884 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
885 v4f32x_info, VR128X, FR32X>;
886 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
887 v4f64x_info, VR128X, FR64X>;
890 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
891 (VBROADCASTSSZm addr:$src)>;
892 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
893 (VBROADCASTSDZm addr:$src)>;
895 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
896 (VBROADCASTSSZm addr:$src)>;
897 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
898 (VBROADCASTSDZm addr:$src)>;
900 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
901 RegisterClass SrcRC> {
902 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
903 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
904 "$src", "$src", []>, T8PD, EVEX;
907 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
908 RegisterClass SrcRC, Predicate prd> {
909 let Predicates = [prd] in
910 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
911 let Predicates = [prd, HasVLX] in {
912 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
913 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
917 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
919 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
921 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
923 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
926 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
927 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
929 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
930 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
932 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
933 (VPBROADCASTDrZr GR32:$src)>;
934 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
935 (VPBROADCASTQrZr GR64:$src)>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
938 (VPBROADCASTDrZr GR32:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
940 (VPBROADCASTQrZr GR64:$src)>;
942 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
943 (v16i32 immAllZerosV), (i16 GR16:$mask))),
944 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
945 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
946 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
947 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
949 // Provide aliases for broadcast from the same register class that
950 // automatically does the extract.
951 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
952 X86VectorVTInfo SrcInfo> {
953 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
954 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
955 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
958 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
959 AVX512VLVectorVTInfo _, Predicate prd> {
960 let Predicates = [prd] in {
961 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
962 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
964 // Defined separately to avoid redefinition.
965 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
967 let Predicates = [prd, HasVLX] in {
968 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
969 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
971 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
976 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
977 avx512vl_i8_info, HasBWI>;
978 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
979 avx512vl_i16_info, HasBWI>;
980 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
981 avx512vl_i32_info, HasAVX512>;
982 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
983 avx512vl_i64_info, HasAVX512>, VEX_W;
985 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
986 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
988 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
991 (_Dst.VT (X86SubVBroadcast
992 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
993 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
998 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1000 !strconcat(OpcodeStr,
1001 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1006 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1007 v16i32_info, v4i32x_info>,
1008 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1009 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1010 v16f32_info, v4f32x_info>,
1011 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1012 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1013 v8i64_info, v4i64x_info>, VEX_W,
1014 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1015 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1016 v8f64_info, v4f64x_info>, VEX_W,
1017 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1019 let Predicates = [HasVLX] in {
1020 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1021 v8i32x_info, v4i32x_info>,
1022 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1023 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1024 v8f32x_info, v4f32x_info>,
1025 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1027 let Predicates = [HasVLX, HasDQI] in {
1028 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1029 v4i64x_info, v2i64x_info>, VEX_W,
1030 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1031 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1032 v4f64x_info, v2f64x_info>, VEX_W,
1033 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1035 let Predicates = [HasDQI] in {
1036 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1037 v8i64_info, v2i64x_info>, VEX_W,
1038 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1039 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1040 v16i32_info, v8i32x_info>,
1041 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1042 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1043 v8f64_info, v2f64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1046 v16f32_info, v8f32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1050 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1051 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1052 SDNode OpNode = X86SubVBroadcast> {
1054 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1055 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1056 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1059 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1062 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1063 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1066 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 AVX512VLVectorVTInfo _> {
1068 let Predicates = [HasDQI] in
1069 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1071 let Predicates = [HasDQI, HasVLX] in
1072 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1076 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1077 AVX512VLVectorVTInfo _> :
1078 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1080 let Predicates = [HasDQI, HasVLX] in
1081 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1082 X86SubV32x2Broadcast>, EVEX_V128;
1085 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1087 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1090 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1091 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1092 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1093 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1095 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1096 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1097 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1098 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1101 (VBROADCASTSSZr VR128X:$src)>;
1102 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1103 (VBROADCASTSDZr VR128X:$src)>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERM2I - 3 source operands form --
1140 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1141 SDNode OpNode, X86VectorVTInfo _> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, X86VectorVTInfo _> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (OpNode _.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1171 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1172 defm NAME: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info512>,
1173 avx512_perm_i_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1174 let Predicates = [HasVLX] in {
1175 defm NAME#128: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info128>,
1176 avx512_perm_i_mb<opc, OpcodeStr, OpNode, VTInfo.info128>, EVEX_V128;
1177 defm NAME#256: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info256>,
1178 avx512_perm_i_mb<opc, OpcodeStr, OpNode, VTInfo.info256>, EVEX_V256;
1182 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1183 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1184 let Predicates = [HasBWI] in
1185 defm NAME: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1186 let Predicates = [HasBWI, HasVLX] in {
1187 defm NAME#128: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info128>, EVEX_V128;
1188 defm NAME#256: avx512_perm_i<opc, OpcodeStr, OpNode, VTInfo.info256>, EVEX_V256;
1192 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", X86VPermi2X,
1193 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1194 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", X86VPermi2X,
1195 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1196 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w", X86VPermi2X,
1197 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1198 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", X86VPermi2X,
1199 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1200 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", X86VPermi2X,
1201 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1204 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1205 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1206 let Constraints = "$src1 = $dst" in {
1207 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1208 (ins IdxVT.RC:$src2, _.RC:$src3),
1209 OpcodeStr, "$src3, $src2", "$src2, $src3",
1210 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1214 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1215 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1216 OpcodeStr, "$src3, $src2", "$src2, $src3",
1217 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1218 (bitconvert (_.LdFrag addr:$src3))))>,
1219 EVEX_4V, AVX5128IBase;
1222 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1223 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1224 let mayLoad = 1, Constraints = "$src1 = $dst" in
1225 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1226 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1227 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1228 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1229 (_.VT (X86VPermt2 _.RC:$src1,
1230 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1231 AVX5128IBase, EVEX_4V, EVEX_B;
1234 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1235 AVX512VLVectorVTInfo VTInfo,
1236 AVX512VLVectorVTInfo ShuffleMask> {
1237 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1238 ShuffleMask.info512>,
1239 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1240 ShuffleMask.info512>, EVEX_V512;
1241 let Predicates = [HasVLX] in {
1242 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1243 ShuffleMask.info128>,
1244 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1245 ShuffleMask.info128>, EVEX_V128;
1246 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1247 ShuffleMask.info256>,
1248 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1249 ShuffleMask.info256>, EVEX_V256;
1253 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1254 AVX512VLVectorVTInfo VTInfo,
1255 AVX512VLVectorVTInfo Idx> {
1256 let Predicates = [HasBWI] in
1257 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1258 Idx.info512>, EVEX_V512;
1259 let Predicates = [HasBWI, HasVLX] in {
1260 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1261 Idx.info128>, EVEX_V128;
1262 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1263 Idx.info256>, EVEX_V256;
1267 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1268 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1269 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1270 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1271 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1272 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1273 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1274 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1275 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1276 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1278 //===----------------------------------------------------------------------===//
1279 // AVX-512 - BLEND using mask
1281 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1282 let ExeDomain = _.ExeDomain in {
1283 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1284 (ins _.RC:$src1, _.RC:$src2),
1285 !strconcat(OpcodeStr,
1286 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1288 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1289 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1290 !strconcat(OpcodeStr,
1291 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1292 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1293 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1294 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1295 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1296 !strconcat(OpcodeStr,
1297 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1298 []>, EVEX_4V, EVEX_KZ;
1299 let mayLoad = 1 in {
1300 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1301 (ins _.RC:$src1, _.MemOp:$src2),
1302 !strconcat(OpcodeStr,
1303 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1304 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1305 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1306 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1307 !strconcat(OpcodeStr,
1308 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1309 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1310 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1311 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1312 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1313 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1314 !strconcat(OpcodeStr,
1315 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1316 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1320 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1322 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1323 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1324 !strconcat(OpcodeStr,
1325 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1326 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1327 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1328 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1329 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1331 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1332 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1333 !strconcat(OpcodeStr,
1334 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1335 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1336 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1340 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1341 AVX512VLVectorVTInfo VTInfo> {
1342 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1343 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1345 let Predicates = [HasVLX] in {
1346 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1347 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1348 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1349 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1353 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1354 AVX512VLVectorVTInfo VTInfo> {
1355 let Predicates = [HasBWI] in
1356 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1358 let Predicates = [HasBWI, HasVLX] in {
1359 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1360 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1365 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1366 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1367 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1368 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1369 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1370 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1373 let Predicates = [HasAVX512] in {
1374 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1375 (v8f32 VR256X:$src2))),
1377 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1378 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1379 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1381 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1382 (v8i32 VR256X:$src2))),
1384 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1385 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1386 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1388 //===----------------------------------------------------------------------===//
1389 // Compare Instructions
1390 //===----------------------------------------------------------------------===//
1392 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1394 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1396 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1398 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1399 "vcmp${cc}"#_.Suffix,
1400 "$src2, $src1", "$src1, $src2",
1401 (OpNode (_.VT _.RC:$src1),
1405 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1407 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1408 "vcmp${cc}"#_.Suffix,
1409 "$src2, $src1", "$src1, $src2",
1410 (OpNode (_.VT _.RC:$src1),
1411 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1412 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1414 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1416 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1417 "vcmp${cc}"#_.Suffix,
1418 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1419 (OpNodeRnd (_.VT _.RC:$src1),
1422 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1423 // Accept explicit immediate argument form instead of comparison code.
1424 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1425 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1427 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1429 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1430 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1432 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1434 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1435 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1437 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1439 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1441 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1443 }// let isAsmParserOnly = 1, hasSideEffects = 0
1445 let isCodeGenOnly = 1 in {
1446 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1447 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1448 !strconcat("vcmp${cc}", _.Suffix,
1449 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1450 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1453 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1455 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1457 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1458 !strconcat("vcmp${cc}", _.Suffix,
1459 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1460 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1461 (_.ScalarLdFrag addr:$src2),
1463 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1467 let Predicates = [HasAVX512] in {
1468 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1470 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1471 AVX512XDIi8Base, VEX_W;
1474 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1475 X86VectorVTInfo _> {
1476 def rr : AVX512BI<opc, MRMSrcReg,
1477 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1479 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1480 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1482 def rm : AVX512BI<opc, MRMSrcMem,
1483 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1484 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1485 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1486 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1487 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1488 def rrk : AVX512BI<opc, MRMSrcReg,
1489 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1491 "$dst {${mask}}, $src1, $src2}"),
1492 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1493 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1494 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1496 def rmk : AVX512BI<opc, MRMSrcMem,
1497 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1498 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1499 "$dst {${mask}}, $src1, $src2}"),
1500 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1501 (OpNode (_.VT _.RC:$src1),
1503 (_.LdFrag addr:$src2))))))],
1504 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1507 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1508 X86VectorVTInfo _> :
1509 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1510 let mayLoad = 1 in {
1511 def rmb : AVX512BI<opc, MRMSrcMem,
1512 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1513 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1514 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1515 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1516 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1517 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1518 def rmbk : AVX512BI<opc, MRMSrcMem,
1519 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1520 _.ScalarMemOp:$src2),
1521 !strconcat(OpcodeStr,
1522 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1523 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1524 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1525 (OpNode (_.VT _.RC:$src1),
1527 (_.ScalarLdFrag addr:$src2)))))],
1528 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1532 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1533 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1534 let Predicates = [prd] in
1535 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1538 let Predicates = [prd, HasVLX] in {
1539 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1541 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1546 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1547 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1549 let Predicates = [prd] in
1550 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1553 let Predicates = [prd, HasVLX] in {
1554 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1556 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1561 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1562 avx512vl_i8_info, HasBWI>,
1565 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1566 avx512vl_i16_info, HasBWI>,
1567 EVEX_CD8<16, CD8VF>;
1569 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1570 avx512vl_i32_info, HasAVX512>,
1571 EVEX_CD8<32, CD8VF>;
1573 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1574 avx512vl_i64_info, HasAVX512>,
1575 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1577 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1578 avx512vl_i8_info, HasBWI>,
1581 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1582 avx512vl_i16_info, HasBWI>,
1583 EVEX_CD8<16, CD8VF>;
1585 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1586 avx512vl_i32_info, HasAVX512>,
1587 EVEX_CD8<32, CD8VF>;
1589 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1590 avx512vl_i64_info, HasAVX512>,
1591 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1593 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1594 (COPY_TO_REGCLASS (VPCMPGTDZrr
1595 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1596 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1598 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1599 (COPY_TO_REGCLASS (VPCMPEQDZrr
1600 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1601 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1603 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1604 X86VectorVTInfo _> {
1605 def rri : AVX512AIi8<opc, MRMSrcReg,
1606 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1607 !strconcat("vpcmp${cc}", Suffix,
1608 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1609 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1611 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1613 def rmi : AVX512AIi8<opc, MRMSrcMem,
1614 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1615 !strconcat("vpcmp${cc}", Suffix,
1616 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1617 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1618 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1620 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1621 def rrik : AVX512AIi8<opc, MRMSrcReg,
1622 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1624 !strconcat("vpcmp${cc}", Suffix,
1625 "\t{$src2, $src1, $dst {${mask}}|",
1626 "$dst {${mask}}, $src1, $src2}"),
1627 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1628 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1630 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1632 def rmik : AVX512AIi8<opc, MRMSrcMem,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{$src2, $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, $src2}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1),
1640 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1642 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1644 // Accept explicit immediate argument form instead of comparison code.
1645 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1646 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1647 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1648 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1649 "$dst, $src1, $src2, $cc}"),
1650 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1652 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1653 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1654 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1655 "$dst, $src1, $src2, $cc}"),
1656 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1657 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1658 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1660 !strconcat("vpcmp", Suffix,
1661 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1662 "$dst {${mask}}, $src1, $src2, $cc}"),
1663 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1665 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1666 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1668 !strconcat("vpcmp", Suffix,
1669 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1670 "$dst {${mask}}, $src1, $src2, $cc}"),
1671 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1675 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1676 X86VectorVTInfo _> :
1677 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1678 def rmib : AVX512AIi8<opc, MRMSrcMem,
1679 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1681 !strconcat("vpcmp${cc}", Suffix,
1682 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1683 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1684 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1685 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1687 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1688 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1689 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1690 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1691 !strconcat("vpcmp${cc}", Suffix,
1692 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1693 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1694 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1695 (OpNode (_.VT _.RC:$src1),
1696 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1698 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1700 // Accept explicit immediate argument form instead of comparison code.
1701 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1702 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1703 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1705 !strconcat("vpcmp", Suffix,
1706 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1707 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1708 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1709 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1710 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1711 _.ScalarMemOp:$src2, u8imm:$cc),
1712 !strconcat("vpcmp", Suffix,
1713 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1714 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1715 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1719 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1720 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1721 let Predicates = [prd] in
1722 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1724 let Predicates = [prd, HasVLX] in {
1725 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1726 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1730 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1731 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1732 let Predicates = [prd] in
1733 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1736 let Predicates = [prd, HasVLX] in {
1737 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1739 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1744 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1745 HasBWI>, EVEX_CD8<8, CD8VF>;
1746 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1747 HasBWI>, EVEX_CD8<8, CD8VF>;
1749 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1750 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1751 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1752 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1754 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1755 HasAVX512>, EVEX_CD8<32, CD8VF>;
1756 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1757 HasAVX512>, EVEX_CD8<32, CD8VF>;
1759 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1760 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1761 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1762 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1764 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1766 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1767 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1768 "vcmp${cc}"#_.Suffix,
1769 "$src2, $src1", "$src1, $src2",
1770 (X86cmpm (_.VT _.RC:$src1),
1774 let mayLoad = 1 in {
1775 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1776 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1777 "vcmp${cc}"#_.Suffix,
1778 "$src2, $src1", "$src1, $src2",
1779 (X86cmpm (_.VT _.RC:$src1),
1780 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1783 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1785 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1786 "vcmp${cc}"#_.Suffix,
1787 "${src2}"##_.BroadcastStr##", $src1",
1788 "$src1, ${src2}"##_.BroadcastStr,
1789 (X86cmpm (_.VT _.RC:$src1),
1790 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1793 // Accept explicit immediate argument form instead of comparison code.
1794 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1795 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1797 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1799 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1801 let mayLoad = 1 in {
1802 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1804 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1806 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1808 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1810 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1812 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1813 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1818 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1819 // comparison code form (VCMP[EQ/LT/LE/...]
1820 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1821 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1822 "vcmp${cc}"#_.Suffix,
1823 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1824 (X86cmpmRnd (_.VT _.RC:$src1),
1827 (i32 FROUND_NO_EXC))>, EVEX_B;
1829 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1830 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1832 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1834 "$cc,{sae}, $src2, $src1",
1835 "$src1, $src2,{sae}, $cc">, EVEX_B;
1839 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1840 let Predicates = [HasAVX512] in {
1841 defm Z : avx512_vcmp_common<_.info512>,
1842 avx512_vcmp_sae<_.info512>, EVEX_V512;
1845 let Predicates = [HasAVX512,HasVLX] in {
1846 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1847 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1851 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1852 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1853 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1854 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1856 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1857 (COPY_TO_REGCLASS (VCMPPSZrri
1858 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1859 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1861 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1862 (COPY_TO_REGCLASS (VPCMPDZrri
1863 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1864 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1866 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1867 (COPY_TO_REGCLASS (VPCMPUDZrri
1868 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1869 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1872 // ----------------------------------------------------------------
1874 //handle fpclass instruction mask = op(reg_scalar,imm)
1875 // op(mem_scalar,imm)
1876 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1877 X86VectorVTInfo _, Predicate prd> {
1878 let Predicates = [prd] in {
1879 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1880 (ins _.RC:$src1, i32u8imm:$src2),
1881 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1882 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1883 (i32 imm:$src2)))], NoItinerary>;
1884 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1885 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1886 OpcodeStr##_.Suffix#
1887 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1888 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1889 (OpNode (_.VT _.RC:$src1),
1890 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1891 let mayLoad = 1, AddedComplexity = 20 in {
1892 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1893 (ins _.MemOp:$src1, i32u8imm:$src2),
1894 OpcodeStr##_.Suffix##
1895 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1897 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1898 (i32 imm:$src2)))], NoItinerary>;
1899 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1900 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1901 OpcodeStr##_.Suffix##
1902 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1903 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1904 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1905 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1910 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1911 // fpclass(reg_vec, mem_vec, imm)
1912 // fpclass(reg_vec, broadcast(eltVt), imm)
1913 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1914 X86VectorVTInfo _, string mem, string broadcast>{
1915 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1916 (ins _.RC:$src1, i32u8imm:$src2),
1917 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1918 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1919 (i32 imm:$src2)))], NoItinerary>;
1920 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1921 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1922 OpcodeStr##_.Suffix#
1923 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1924 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1925 (OpNode (_.VT _.RC:$src1),
1926 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1927 let mayLoad = 1 in {
1928 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1929 (ins _.MemOp:$src1, i32u8imm:$src2),
1930 OpcodeStr##_.Suffix##mem#
1931 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1932 [(set _.KRC:$dst,(OpNode
1933 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1934 (i32 imm:$src2)))], NoItinerary>;
1935 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1936 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1937 OpcodeStr##_.Suffix##mem#
1938 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1939 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1940 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1941 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1942 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1943 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1944 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1945 _.BroadcastStr##", $dst | $dst, ${src1}"
1946 ##_.BroadcastStr##", $src2}",
1947 [(set _.KRC:$dst,(OpNode
1948 (_.VT (X86VBroadcast
1949 (_.ScalarLdFrag addr:$src1))),
1950 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1951 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1952 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1953 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1954 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1955 _.BroadcastStr##", $src2}",
1956 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1957 (_.VT (X86VBroadcast
1958 (_.ScalarLdFrag addr:$src1))),
1959 (i32 imm:$src2))))], NoItinerary>,
1964 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1965 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1967 let Predicates = [prd] in {
1968 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1969 broadcast>, EVEX_V512;
1971 let Predicates = [prd, HasVLX] in {
1972 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1973 broadcast>, EVEX_V128;
1974 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1975 broadcast>, EVEX_V256;
1979 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1980 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1981 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1982 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1983 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1984 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1985 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1986 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1987 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1988 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1991 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1992 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1994 //-----------------------------------------------------------------
1995 // Mask register copy, including
1996 // - copy between mask registers
1997 // - load/store mask registers
1998 // - copy from GPR to mask register and vice versa
2000 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2001 string OpcodeStr, RegisterClass KRC,
2002 ValueType vvt, X86MemOperand x86memop> {
2003 let hasSideEffects = 0 in {
2004 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2005 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2007 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2008 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2009 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2011 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2012 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2013 [(store KRC:$src, addr:$dst)]>;
2017 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2019 RegisterClass KRC, RegisterClass GRC> {
2020 let hasSideEffects = 0 in {
2021 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2023 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2024 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2028 let Predicates = [HasDQI] in
2029 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2030 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2033 let Predicates = [HasAVX512] in
2034 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2035 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2038 let Predicates = [HasBWI] in {
2039 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2041 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2045 let Predicates = [HasBWI] in {
2046 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2048 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2052 // GR from/to mask register
2053 let Predicates = [HasDQI] in {
2054 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2055 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2056 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2057 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2059 let Predicates = [HasAVX512] in {
2060 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2061 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2062 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2063 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2065 let Predicates = [HasBWI] in {
2066 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2067 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2069 let Predicates = [HasBWI] in {
2070 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2071 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2075 let Predicates = [HasDQI] in {
2076 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2077 (KMOVBmk addr:$dst, VK8:$src)>;
2078 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2079 (KMOVBkm addr:$src)>;
2081 def : Pat<(store VK4:$src, addr:$dst),
2082 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2083 def : Pat<(store VK2:$src, addr:$dst),
2084 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2086 let Predicates = [HasAVX512, NoDQI] in {
2087 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2088 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2089 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2090 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2092 let Predicates = [HasAVX512] in {
2093 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2094 (KMOVWmk addr:$dst, VK16:$src)>;
2095 def : Pat<(i1 (load addr:$src)),
2096 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2097 (MOV8rm addr:$src), sub_8bit)),
2099 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2100 (KMOVWkm addr:$src)>;
2102 let Predicates = [HasBWI] in {
2103 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2104 (KMOVDmk addr:$dst, VK32:$src)>;
2105 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2106 (KMOVDkm addr:$src)>;
2108 let Predicates = [HasBWI] in {
2109 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2110 (KMOVQmk addr:$dst, VK64:$src)>;
2111 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2112 (KMOVQkm addr:$src)>;
2115 let Predicates = [HasAVX512] in {
2116 def : Pat<(i1 (trunc (i64 GR64:$src))),
2117 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2120 def : Pat<(i1 (trunc (i32 GR32:$src))),
2121 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2123 def : Pat<(i1 (trunc (i8 GR8:$src))),
2125 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2127 def : Pat<(i1 (trunc (i16 GR16:$src))),
2129 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2132 def : Pat<(i32 (zext VK1:$src)),
2133 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2134 def : Pat<(i32 (anyext VK1:$src)),
2135 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2137 def : Pat<(i8 (zext VK1:$src)),
2140 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2141 def : Pat<(i8 (anyext VK1:$src)),
2143 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2145 def : Pat<(i64 (zext VK1:$src)),
2146 (AND64ri8 (SUBREG_TO_REG (i64 0),
2147 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2148 def : Pat<(i16 (zext VK1:$src)),
2150 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2152 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2153 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2154 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2155 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2157 let Predicates = [HasBWI] in {
2158 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2159 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2160 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2161 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2165 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2166 let Predicates = [HasAVX512, NoDQI] in {
2167 // GR from/to 8-bit mask without native support
2168 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2170 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2171 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2173 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2177 let Predicates = [HasAVX512] in {
2178 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2179 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2180 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2181 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2183 let Predicates = [HasBWI] in {
2184 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2185 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2186 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2187 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2190 // Mask unary operation
2192 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2193 RegisterClass KRC, SDPatternOperator OpNode,
2195 let Predicates = [prd] in
2196 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2198 [(set KRC:$dst, (OpNode KRC:$src))]>;
2201 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2202 SDPatternOperator OpNode> {
2203 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2205 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2206 HasAVX512>, VEX, PS;
2207 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2208 HasBWI>, VEX, PD, VEX_W;
2209 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2210 HasBWI>, VEX, PS, VEX_W;
2213 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2215 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2216 let Predicates = [HasAVX512] in
2217 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2219 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2220 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2222 defm : avx512_mask_unop_int<"knot", "KNOT">;
2224 let Predicates = [HasDQI] in
2225 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2226 let Predicates = [HasAVX512] in
2227 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2228 let Predicates = [HasBWI] in
2229 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2230 let Predicates = [HasBWI] in
2231 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2233 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2234 let Predicates = [HasAVX512, NoDQI] in {
2235 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2236 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2237 def : Pat<(not VK8:$src),
2239 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2241 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2242 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2243 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2244 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2246 // Mask binary operation
2247 // - KAND, KANDN, KOR, KXNOR, KXOR
2248 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2249 RegisterClass KRC, SDPatternOperator OpNode,
2250 Predicate prd, bit IsCommutable> {
2251 let Predicates = [prd], isCommutable = IsCommutable in
2252 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2253 !strconcat(OpcodeStr,
2254 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2255 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2258 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2259 SDPatternOperator OpNode, bit IsCommutable,
2260 Predicate prdW = HasAVX512> {
2261 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2262 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2263 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2264 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2265 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2266 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2267 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2268 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2271 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2272 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2274 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2275 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2276 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2277 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2278 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2279 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2281 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2282 let Predicates = [HasAVX512] in
2283 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2284 (i16 GR16:$src1), (i16 GR16:$src2)),
2285 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2286 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2287 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2290 defm : avx512_mask_binop_int<"kand", "KAND">;
2291 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2292 defm : avx512_mask_binop_int<"kor", "KOR">;
2293 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2294 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2296 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2297 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2298 // for the DQI set, this type is legal and KxxxB instruction is used
2299 let Predicates = [NoDQI] in
2300 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2302 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2303 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2305 // All types smaller than 8 bits require conversion anyway
2306 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2307 (COPY_TO_REGCLASS (Inst
2308 (COPY_TO_REGCLASS VK1:$src1, VK16),
2309 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2310 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2311 (COPY_TO_REGCLASS (Inst
2312 (COPY_TO_REGCLASS VK2:$src1, VK16),
2313 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2314 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2315 (COPY_TO_REGCLASS (Inst
2316 (COPY_TO_REGCLASS VK4:$src1, VK16),
2317 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2320 defm : avx512_binop_pat<and, KANDWrr>;
2321 defm : avx512_binop_pat<andn, KANDNWrr>;
2322 defm : avx512_binop_pat<or, KORWrr>;
2323 defm : avx512_binop_pat<xnor, KXNORWrr>;
2324 defm : avx512_binop_pat<xor, KXORWrr>;
2326 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2327 (KXNORWrr VK16:$src1, VK16:$src2)>;
2328 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2329 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2330 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2331 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2332 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2333 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2335 let Predicates = [NoDQI] in
2336 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2337 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2338 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2340 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2341 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2342 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2344 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2345 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2346 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2348 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2349 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2350 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2353 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2354 RegisterClass KRCSrc, Predicate prd> {
2355 let Predicates = [prd] in {
2356 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2357 (ins KRC:$src1, KRC:$src2),
2358 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2361 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2362 (!cast<Instruction>(NAME##rr)
2363 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2364 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2368 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2369 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2370 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2372 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2373 let Predicates = [HasAVX512] in
2374 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2375 (i16 GR16:$src1), (i16 GR16:$src2)),
2376 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2377 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2378 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2380 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2383 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2384 SDNode OpNode, Predicate prd> {
2385 let Predicates = [prd], Defs = [EFLAGS] in
2386 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2387 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2388 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2391 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2392 Predicate prdW = HasAVX512> {
2393 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2395 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2397 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2399 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2403 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2404 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2407 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2409 let Predicates = [HasAVX512] in
2410 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2411 !strconcat(OpcodeStr,
2412 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2413 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2416 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2418 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2420 let Predicates = [HasDQI] in
2421 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2423 let Predicates = [HasBWI] in {
2424 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2426 let Predicates = [HasDQI] in
2427 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2432 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2433 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2435 // Mask setting all 0s or 1s
2436 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2437 let Predicates = [HasAVX512] in
2438 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2439 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2440 [(set KRC:$dst, (VT Val))]>;
2443 multiclass avx512_mask_setop_w<PatFrag Val> {
2444 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2445 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2446 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2447 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2450 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2451 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2453 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2454 let Predicates = [HasAVX512] in {
2455 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2456 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2457 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2458 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2459 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2460 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2461 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2463 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2464 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2466 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2467 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2469 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2470 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2472 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2473 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2475 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2476 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2478 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2479 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2480 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2481 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2483 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2484 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2486 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2487 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2488 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2489 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2491 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2492 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2493 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2494 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2495 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2496 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2497 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2498 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2500 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2501 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2502 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2503 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2504 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2505 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2506 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2507 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2508 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2509 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2512 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2513 (v8i1 (COPY_TO_REGCLASS
2514 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2515 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2517 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2518 (v8i1 (COPY_TO_REGCLASS
2519 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2520 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2522 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2523 (v4i1 (COPY_TO_REGCLASS
2524 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2525 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2527 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2528 (v4i1 (COPY_TO_REGCLASS
2529 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2530 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2532 //===----------------------------------------------------------------------===//
2533 // AVX-512 - Aligned and unaligned load and store
2537 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2538 PatFrag ld_frag, PatFrag mload,
2539 bit IsReMaterializable = 1> {
2540 let hasSideEffects = 0 in {
2541 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2544 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2545 (ins _.KRCWM:$mask, _.RC:$src),
2546 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2547 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2550 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2551 SchedRW = [WriteLoad] in
2552 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2553 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2554 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2557 let Constraints = "$src0 = $dst" in {
2558 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2559 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2560 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2561 "${dst} {${mask}}, $src1}"),
2562 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2564 (_.VT _.RC:$src0))))], _.ExeDomain>,
2566 let mayLoad = 1, SchedRW = [WriteLoad] in
2567 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2568 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2569 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2570 "${dst} {${mask}}, $src1}"),
2571 [(set _.RC:$dst, (_.VT
2572 (vselect _.KRCWM:$mask,
2573 (_.VT (bitconvert (ld_frag addr:$src1))),
2574 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2576 let mayLoad = 1, SchedRW = [WriteLoad] in
2577 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2578 (ins _.KRCWM:$mask, _.MemOp:$src),
2579 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2580 "${dst} {${mask}} {z}, $src}",
2581 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2582 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2583 _.ExeDomain>, EVEX, EVEX_KZ;
2585 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2586 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2588 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2589 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2591 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2592 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2593 _.KRCWM:$mask, addr:$ptr)>;
2596 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2597 AVX512VLVectorVTInfo _,
2599 bit IsReMaterializable = 1> {
2600 let Predicates = [prd] in
2601 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2602 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2604 let Predicates = [prd, HasVLX] in {
2605 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2606 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2607 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2608 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2612 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2613 AVX512VLVectorVTInfo _,
2615 bit IsReMaterializable = 1> {
2616 let Predicates = [prd] in
2617 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2618 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2620 let Predicates = [prd, HasVLX] in {
2621 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2622 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2623 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2624 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2628 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2629 PatFrag st_frag, PatFrag mstore> {
2631 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2632 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2633 [], _.ExeDomain>, EVEX;
2634 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2635 (ins _.KRCWM:$mask, _.RC:$src),
2636 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2637 "${dst} {${mask}}, $src}",
2638 [], _.ExeDomain>, EVEX, EVEX_K;
2639 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2640 (ins _.KRCWM:$mask, _.RC:$src),
2641 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2642 "${dst} {${mask}} {z}, $src}",
2643 [], _.ExeDomain>, EVEX, EVEX_KZ;
2645 let mayStore = 1 in {
2646 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2647 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2648 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2649 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2650 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2651 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2652 [], _.ExeDomain>, EVEX, EVEX_K;
2655 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2656 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2657 _.KRCWM:$mask, _.RC:$src)>;
2661 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2662 AVX512VLVectorVTInfo _, Predicate prd> {
2663 let Predicates = [prd] in
2664 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2665 masked_store_unaligned>, EVEX_V512;
2667 let Predicates = [prd, HasVLX] in {
2668 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2669 masked_store_unaligned>, EVEX_V256;
2670 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2671 masked_store_unaligned>, EVEX_V128;
2675 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2676 AVX512VLVectorVTInfo _, Predicate prd> {
2677 let Predicates = [prd] in
2678 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2679 masked_store_aligned512>, EVEX_V512;
2681 let Predicates = [prd, HasVLX] in {
2682 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2683 masked_store_aligned256>, EVEX_V256;
2684 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2685 masked_store_aligned128>, EVEX_V128;
2689 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2691 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2692 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2694 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2696 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2697 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2699 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2700 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2701 PS, EVEX_CD8<32, CD8VF>;
2703 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2704 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2705 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2707 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2708 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2709 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2711 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2712 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2713 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2715 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2716 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2717 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2719 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2720 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2721 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2723 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2724 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2725 (VMOVAPDZrm addr:$ptr)>;
2727 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2728 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2729 (VMOVAPSZrm addr:$ptr)>;
2731 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2733 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2735 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2737 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2740 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2742 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2744 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2746 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2749 let Predicates = [HasAVX512, NoVLX] in {
2750 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2751 (VMOVUPSZmrk addr:$ptr,
2752 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2753 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2755 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2756 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2757 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2759 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2760 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2761 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2762 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2765 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2767 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2768 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2770 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2772 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2773 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2775 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2776 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2777 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2779 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2780 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2781 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2783 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2784 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2785 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2787 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2788 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2789 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2791 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2792 (v16i32 immAllZerosV), GR16:$mask)),
2793 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2795 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2796 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2797 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2799 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2801 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2803 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2805 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2808 let AddedComplexity = 20 in {
2809 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2810 (bc_v8i64 (v16i32 immAllZerosV)))),
2811 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2813 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2814 (v8i64 VR512:$src))),
2815 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2818 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2819 (v16i32 immAllZerosV))),
2820 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2822 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2823 (v16i32 VR512:$src))),
2824 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2827 let Predicates = [HasAVX512, NoVLX] in {
2828 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2829 (VMOVDQU32Zmrk addr:$ptr,
2830 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2831 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2833 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2834 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2835 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2838 // Move Int Doubleword to Packed Double Int
2840 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2841 "vmovd\t{$src, $dst|$dst, $src}",
2843 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2845 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2846 "vmovd\t{$src, $dst|$dst, $src}",
2848 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2849 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2850 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2851 "vmovq\t{$src, $dst|$dst, $src}",
2853 (v2i64 (scalar_to_vector GR64:$src)))],
2854 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2855 let isCodeGenOnly = 1 in {
2856 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2857 "vmovq\t{$src, $dst|$dst, $src}",
2858 [(set FR64:$dst, (bitconvert GR64:$src))],
2859 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2860 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2861 "vmovq\t{$src, $dst|$dst, $src}",
2862 [(set GR64:$dst, (bitconvert FR64:$src))],
2863 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2865 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2866 "vmovq\t{$src, $dst|$dst, $src}",
2867 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2868 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2869 EVEX_CD8<64, CD8VT1>;
2871 // Move Int Doubleword to Single Scalar
2873 let isCodeGenOnly = 1 in {
2874 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2875 "vmovd\t{$src, $dst|$dst, $src}",
2876 [(set FR32X:$dst, (bitconvert GR32:$src))],
2877 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2879 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2880 "vmovd\t{$src, $dst|$dst, $src}",
2881 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2882 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2885 // Move doubleword from xmm register to r/m32
2887 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2888 "vmovd\t{$src, $dst|$dst, $src}",
2889 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2890 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2892 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2893 (ins i32mem:$dst, VR128X:$src),
2894 "vmovd\t{$src, $dst|$dst, $src}",
2895 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2896 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2897 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2899 // Move quadword from xmm1 register to r/m64
2901 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2902 "vmovq\t{$src, $dst|$dst, $src}",
2903 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2905 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2906 Requires<[HasAVX512, In64BitMode]>;
2908 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2909 (ins i64mem:$dst, VR128X:$src),
2910 "vmovq\t{$src, $dst|$dst, $src}",
2911 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2912 addr:$dst)], IIC_SSE_MOVDQ>,
2913 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2914 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2916 // Move Scalar Single to Double Int
2918 let isCodeGenOnly = 1 in {
2919 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2921 "vmovd\t{$src, $dst|$dst, $src}",
2922 [(set GR32:$dst, (bitconvert FR32X:$src))],
2923 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2924 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2925 (ins i32mem:$dst, FR32X:$src),
2926 "vmovd\t{$src, $dst|$dst, $src}",
2927 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2928 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2931 // Move Quadword Int to Packed Quadword Int
2933 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2935 "vmovq\t{$src, $dst|$dst, $src}",
2937 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2938 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2940 //===----------------------------------------------------------------------===//
2941 // AVX-512 MOVSS, MOVSD
2942 //===----------------------------------------------------------------------===//
2944 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2945 SDNode OpNode, ValueType vt,
2946 X86MemOperand x86memop, PatFrag mem_pat> {
2947 let hasSideEffects = 0 in {
2948 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2949 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2950 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2951 (scalar_to_vector RC:$src2))))],
2952 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2953 let Constraints = "$src1 = $dst" in
2954 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2955 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2957 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2958 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2959 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2960 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2961 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2963 let mayStore = 1 in {
2964 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2965 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2966 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2968 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2969 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2970 [], IIC_SSE_MOV_S_MR>,
2971 EVEX, VEX_LIG, EVEX_K;
2973 } //hasSideEffects = 0
2976 let ExeDomain = SSEPackedSingle in
2977 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2978 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2980 let ExeDomain = SSEPackedDouble in
2981 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2982 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2984 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2985 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2986 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2988 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2989 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2990 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2992 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2993 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2994 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2996 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
2997 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
2998 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
2999 XS, EVEX_4V, VEX_LIG;
3001 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3002 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3003 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3004 XD, EVEX_4V, VEX_LIG, VEX_W;
3006 let Predicates = [HasAVX512] in {
3007 let AddedComplexity = 15 in {
3008 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3009 // MOVS{S,D} to the lower bits.
3010 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3011 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3012 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3013 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3014 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3015 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3016 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3017 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3019 // Move low f32 and clear high bits.
3020 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3021 (SUBREG_TO_REG (i32 0),
3022 (VMOVSSZrr (v4f32 (V_SET0)),
3023 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3024 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3025 (SUBREG_TO_REG (i32 0),
3026 (VMOVSSZrr (v4i32 (V_SET0)),
3027 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3030 let AddedComplexity = 20 in {
3031 // MOVSSrm zeros the high parts of the register; represent this
3032 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3033 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3034 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3035 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3036 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3037 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3038 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3040 // MOVSDrm zeros the high parts of the register; represent this
3041 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3042 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3043 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3044 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3045 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3046 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3047 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3048 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3049 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3050 def : Pat<(v2f64 (X86vzload addr:$src)),
3051 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3053 // Represent the same patterns above but in the form they appear for
3055 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3056 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3057 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3058 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3059 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3060 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3061 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3062 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3063 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3065 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3066 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3067 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3068 FR32X:$src)), sub_xmm)>;
3069 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3070 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3071 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3072 FR64X:$src)), sub_xmm)>;
3073 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3074 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3075 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3077 // Move low f64 and clear high bits.
3078 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3079 (SUBREG_TO_REG (i32 0),
3080 (VMOVSDZrr (v2f64 (V_SET0)),
3081 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3083 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3084 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3085 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3087 // Extract and store.
3088 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3090 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3091 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3093 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3095 // Shuffle with VMOVSS
3096 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3097 (VMOVSSZrr (v4i32 VR128X:$src1),
3098 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3099 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3100 (VMOVSSZrr (v4f32 VR128X:$src1),
3101 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3104 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3105 (SUBREG_TO_REG (i32 0),
3106 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3107 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3109 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3110 (SUBREG_TO_REG (i32 0),
3111 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3112 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3115 // Shuffle with VMOVSD
3116 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3117 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3118 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3119 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3120 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3121 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3122 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3123 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3126 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3127 (SUBREG_TO_REG (i32 0),
3128 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3129 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3131 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3132 (SUBREG_TO_REG (i32 0),
3133 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3134 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3137 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3138 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3139 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3140 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3141 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3142 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3143 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3144 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3147 let AddedComplexity = 15 in
3148 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3150 "vmovq\t{$src, $dst|$dst, $src}",
3151 [(set VR128X:$dst, (v2i64 (X86vzmovl
3152 (v2i64 VR128X:$src))))],
3153 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3155 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3156 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3158 "vmovq\t{$src, $dst|$dst, $src}",
3159 [(set VR128X:$dst, (v2i64 (X86vzmovl
3160 (loadv2i64 addr:$src))))],
3161 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3162 EVEX_CD8<8, CD8VT8>;
3164 let Predicates = [HasAVX512] in {
3165 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3166 let AddedComplexity = 20 in {
3167 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3168 (VMOVDI2PDIZrm addr:$src)>;
3169 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3170 (VMOV64toPQIZrr GR64:$src)>;
3171 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3172 (VMOVDI2PDIZrr GR32:$src)>;
3174 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3175 (VMOVDI2PDIZrm addr:$src)>;
3176 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3177 (VMOVDI2PDIZrm addr:$src)>;
3178 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3179 (VMOVZPQILo2PQIZrm addr:$src)>;
3180 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3181 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3182 def : Pat<(v2i64 (X86vzload addr:$src)),
3183 (VMOVZPQILo2PQIZrm addr:$src)>;
3186 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3187 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3188 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3189 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3190 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3191 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3192 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3195 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3196 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3198 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3199 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3201 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3202 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3204 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3205 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3207 //===----------------------------------------------------------------------===//
3208 // AVX-512 - Non-temporals
3209 //===----------------------------------------------------------------------===//
3210 let SchedRW = [WriteLoad] in {
3211 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3212 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3213 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3214 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3215 EVEX_CD8<64, CD8VF>;
3217 let Predicates = [HasAVX512, HasVLX] in {
3218 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3220 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3221 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3222 EVEX_CD8<64, CD8VF>;
3224 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3226 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3227 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3228 EVEX_CD8<64, CD8VF>;
3232 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3233 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3234 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3235 let SchedRW = [WriteStore], mayStore = 1,
3236 AddedComplexity = 400 in
3237 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3238 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3239 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3242 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3243 string elty, string elsz, string vsz512,
3244 string vsz256, string vsz128, Domain d,
3245 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3246 let Predicates = [prd] in
3247 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3248 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3249 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3252 let Predicates = [prd, HasVLX] in {
3253 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3254 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3255 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3258 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3259 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3260 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3265 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3266 "i", "64", "8", "4", "2", SSEPackedInt,
3267 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3269 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3270 "f", "64", "8", "4", "2", SSEPackedDouble,
3271 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3273 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3274 "f", "32", "16", "8", "4", SSEPackedSingle,
3275 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3277 //===----------------------------------------------------------------------===//
3278 // AVX-512 - Integer arithmetic
3280 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3281 X86VectorVTInfo _, OpndItins itins,
3282 bit IsCommutable = 0> {
3283 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3284 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3285 "$src2, $src1", "$src1, $src2",
3286 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3287 itins.rr, IsCommutable>,
3288 AVX512BIBase, EVEX_4V;
3291 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3292 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3293 "$src2, $src1", "$src1, $src2",
3294 (_.VT (OpNode _.RC:$src1,
3295 (bitconvert (_.LdFrag addr:$src2)))),
3297 AVX512BIBase, EVEX_4V;
3300 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3301 X86VectorVTInfo _, OpndItins itins,
3302 bit IsCommutable = 0> :
3303 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3305 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3306 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3307 "${src2}"##_.BroadcastStr##", $src1",
3308 "$src1, ${src2}"##_.BroadcastStr,
3309 (_.VT (OpNode _.RC:$src1,
3311 (_.ScalarLdFrag addr:$src2)))),
3313 AVX512BIBase, EVEX_4V, EVEX_B;
3316 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3317 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3318 Predicate prd, bit IsCommutable = 0> {
3319 let Predicates = [prd] in
3320 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3321 IsCommutable>, EVEX_V512;
3323 let Predicates = [prd, HasVLX] in {
3324 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3325 IsCommutable>, EVEX_V256;
3326 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3327 IsCommutable>, EVEX_V128;
3331 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3332 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3333 Predicate prd, bit IsCommutable = 0> {
3334 let Predicates = [prd] in
3335 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3336 IsCommutable>, EVEX_V512;
3338 let Predicates = [prd, HasVLX] in {
3339 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3340 IsCommutable>, EVEX_V256;
3341 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3342 IsCommutable>, EVEX_V128;
3346 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3347 OpndItins itins, Predicate prd,
3348 bit IsCommutable = 0> {
3349 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3350 itins, prd, IsCommutable>,
3351 VEX_W, EVEX_CD8<64, CD8VF>;
3354 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3355 OpndItins itins, Predicate prd,
3356 bit IsCommutable = 0> {
3357 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3358 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3361 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3362 OpndItins itins, Predicate prd,
3363 bit IsCommutable = 0> {
3364 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3365 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3368 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3369 OpndItins itins, Predicate prd,
3370 bit IsCommutable = 0> {
3371 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3372 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3375 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3376 SDNode OpNode, OpndItins itins, Predicate prd,
3377 bit IsCommutable = 0> {
3378 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3381 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3385 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3386 SDNode OpNode, OpndItins itins, Predicate prd,
3387 bit IsCommutable = 0> {
3388 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3391 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3395 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3396 bits<8> opc_d, bits<8> opc_q,
3397 string OpcodeStr, SDNode OpNode,
3398 OpndItins itins, bit IsCommutable = 0> {
3399 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3400 itins, HasAVX512, IsCommutable>,
3401 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3402 itins, HasBWI, IsCommutable>;
3405 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3406 SDNode OpNode,X86VectorVTInfo _Src,
3407 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3408 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3409 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3410 "$src2, $src1","$src1, $src2",
3412 (_Src.VT _Src.RC:$src1),
3413 (_Src.VT _Src.RC:$src2))),
3414 itins.rr, IsCommutable>,
3415 AVX512BIBase, EVEX_4V;
3416 let mayLoad = 1 in {
3417 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3418 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3419 "$src2, $src1", "$src1, $src2",
3420 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3421 (bitconvert (_Src.LdFrag addr:$src2)))),
3423 AVX512BIBase, EVEX_4V;
3425 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3426 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3428 "${src2}"##_Dst.BroadcastStr##", $src1",
3429 "$src1, ${src2}"##_Dst.BroadcastStr,
3430 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3431 (_Dst.VT (X86VBroadcast
3432 (_Dst.ScalarLdFrag addr:$src2)))))),
3434 AVX512BIBase, EVEX_4V, EVEX_B;
3438 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3439 SSE_INTALU_ITINS_P, 1>;
3440 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3441 SSE_INTALU_ITINS_P, 0>;
3442 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3443 SSE_INTALU_ITINS_P, HasBWI, 1>;
3444 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3445 SSE_INTALU_ITINS_P, HasBWI, 0>;
3446 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3447 SSE_INTALU_ITINS_P, HasBWI, 1>;
3448 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3449 SSE_INTALU_ITINS_P, HasBWI, 0>;
3450 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3451 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3452 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3453 SSE_INTALU_ITINS_P, HasBWI, 1>;
3454 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3455 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3456 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3458 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3460 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3462 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3463 SSE_INTALU_ITINS_P, HasBWI, 1>;
3465 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3466 SDNode OpNode, bit IsCommutable = 0> {
3468 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3469 v16i32_info, v8i64_info, IsCommutable>,
3470 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3471 let Predicates = [HasVLX] in {
3472 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3473 v8i32x_info, v4i64x_info, IsCommutable>,
3474 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3475 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3476 v4i32x_info, v2i64x_info, IsCommutable>,
3477 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3481 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3483 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3486 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3487 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3488 let mayLoad = 1 in {
3489 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3490 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3492 "${src2}"##_Src.BroadcastStr##", $src1",
3493 "$src1, ${src2}"##_Src.BroadcastStr,
3494 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3495 (_Src.VT (X86VBroadcast
3496 (_Src.ScalarLdFrag addr:$src2))))))>,
3497 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3501 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3502 SDNode OpNode,X86VectorVTInfo _Src,
3503 X86VectorVTInfo _Dst> {
3504 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3505 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3506 "$src2, $src1","$src1, $src2",
3508 (_Src.VT _Src.RC:$src1),
3509 (_Src.VT _Src.RC:$src2)))>,
3510 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3511 let mayLoad = 1 in {
3512 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3513 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3514 "$src2, $src1", "$src1, $src2",
3515 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3516 (bitconvert (_Src.LdFrag addr:$src2))))>,
3517 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3521 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3523 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3525 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3526 v32i16_info>, EVEX_V512;
3527 let Predicates = [HasVLX] in {
3528 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3530 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3531 v16i16x_info>, EVEX_V256;
3532 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3534 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3535 v8i16x_info>, EVEX_V128;
3538 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3540 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3541 v64i8_info>, EVEX_V512;
3542 let Predicates = [HasVLX] in {
3543 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3544 v32i8x_info>, EVEX_V256;
3545 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3546 v16i8x_info>, EVEX_V128;
3550 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3551 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3552 AVX512VLVectorVTInfo _Dst> {
3553 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3554 _Dst.info512>, EVEX_V512;
3555 let Predicates = [HasVLX] in {
3556 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3557 _Dst.info256>, EVEX_V256;
3558 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3559 _Dst.info128>, EVEX_V128;
3563 let Predicates = [HasBWI] in {
3564 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3565 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3566 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3567 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3569 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3570 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3571 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3572 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3575 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3576 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3577 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3578 SSE_INTALU_ITINS_P, HasBWI, 1>;
3579 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3580 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3582 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3583 SSE_INTALU_ITINS_P, HasBWI, 1>;
3584 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3585 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3586 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3587 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3589 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3590 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3591 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3592 SSE_INTALU_ITINS_P, HasBWI, 1>;
3593 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3594 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3596 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3597 SSE_INTALU_ITINS_P, HasBWI, 1>;
3598 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3599 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3600 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3601 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3602 //===----------------------------------------------------------------------===//
3603 // AVX-512 Logical Instructions
3604 //===----------------------------------------------------------------------===//
3606 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3607 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3608 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3609 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3610 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3611 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3612 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3613 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3615 //===----------------------------------------------------------------------===//
3616 // AVX-512 FP arithmetic
3617 //===----------------------------------------------------------------------===//
3618 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3619 SDNode OpNode, SDNode VecNode, OpndItins itins,
3622 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3623 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3624 "$src2, $src1", "$src1, $src2",
3625 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3626 (i32 FROUND_CURRENT)),
3627 itins.rr, IsCommutable>;
3629 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3630 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3631 "$src2, $src1", "$src1, $src2",
3632 (VecNode (_.VT _.RC:$src1),
3633 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3634 (i32 FROUND_CURRENT)),
3635 itins.rm, IsCommutable>;
3636 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3637 Predicates = [HasAVX512] in {
3638 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3639 (ins _.FRC:$src1, _.FRC:$src2),
3640 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3641 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3643 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3644 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3645 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3646 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3647 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3651 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3652 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3654 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3655 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3656 "$rc, $src2, $src1", "$src1, $src2, $rc",
3657 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3658 (i32 imm:$rc)), itins.rr, IsCommutable>,
3661 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3662 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3664 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3665 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3666 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3667 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3668 (i32 FROUND_NO_EXC))>, EVEX_B;
3671 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3673 SizeItins itins, bit IsCommutable> {
3674 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3675 itins.s, IsCommutable>,
3676 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3677 itins.s, IsCommutable>,
3678 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3679 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3680 itins.d, IsCommutable>,
3681 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3682 itins.d, IsCommutable>,
3683 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3686 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3688 SizeItins itins, bit IsCommutable> {
3689 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3690 itins.s, IsCommutable>,
3691 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3692 itins.s, IsCommutable>,
3693 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3694 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3695 itins.d, IsCommutable>,
3696 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3697 itins.d, IsCommutable>,
3698 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3700 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3701 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3702 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3703 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3704 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3705 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3707 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3708 X86VectorVTInfo _, bit IsCommutable> {
3709 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3710 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3711 "$src2, $src1", "$src1, $src2",
3712 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3713 let mayLoad = 1 in {
3714 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3715 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3716 "$src2, $src1", "$src1, $src2",
3717 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3718 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3719 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3720 "${src2}"##_.BroadcastStr##", $src1",
3721 "$src1, ${src2}"##_.BroadcastStr,
3722 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3723 (_.ScalarLdFrag addr:$src2))))>,
3728 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3729 X86VectorVTInfo _> {
3730 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3731 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3732 "$rc, $src2, $src1", "$src1, $src2, $rc",
3733 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3734 EVEX_4V, EVEX_B, EVEX_RC;
3738 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3739 X86VectorVTInfo _> {
3740 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3741 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3742 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3743 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3747 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3748 bit IsCommutable = 0> {
3749 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3750 IsCommutable>, EVEX_V512, PS,
3751 EVEX_CD8<32, CD8VF>;
3752 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3753 IsCommutable>, EVEX_V512, PD, VEX_W,
3754 EVEX_CD8<64, CD8VF>;
3756 // Define only if AVX512VL feature is present.
3757 let Predicates = [HasVLX] in {
3758 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3759 IsCommutable>, EVEX_V128, PS,
3760 EVEX_CD8<32, CD8VF>;
3761 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3762 IsCommutable>, EVEX_V256, PS,
3763 EVEX_CD8<32, CD8VF>;
3764 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3765 IsCommutable>, EVEX_V128, PD, VEX_W,
3766 EVEX_CD8<64, CD8VF>;
3767 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3768 IsCommutable>, EVEX_V256, PD, VEX_W,
3769 EVEX_CD8<64, CD8VF>;
3773 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3774 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3775 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3776 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3777 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3780 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3781 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3782 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3783 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3784 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3787 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3788 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3789 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3790 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3791 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3792 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3793 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3794 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3795 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3796 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3797 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3798 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3799 let Predicates = [HasDQI] in {
3800 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3801 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3802 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3803 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3806 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3807 X86VectorVTInfo _> {
3808 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3809 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3810 "$src2, $src1", "$src1, $src2",
3811 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3812 let mayLoad = 1 in {
3813 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3814 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3815 "$src2, $src1", "$src1, $src2",
3816 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3817 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3818 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3819 "${src2}"##_.BroadcastStr##", $src1",
3820 "$src1, ${src2}"##_.BroadcastStr,
3821 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3822 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3827 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3828 X86VectorVTInfo _> {
3829 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3830 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3831 "$src2, $src1", "$src1, $src2",
3832 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3833 let mayLoad = 1 in {
3834 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3835 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3836 "$src2, $src1", "$src1, $src2",
3837 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3841 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3842 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3843 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3844 EVEX_V512, EVEX_CD8<32, CD8VF>;
3845 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3846 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3847 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3848 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3849 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3850 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3851 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3852 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3853 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3855 // Define only if AVX512VL feature is present.
3856 let Predicates = [HasVLX] in {
3857 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3858 EVEX_V128, EVEX_CD8<32, CD8VF>;
3859 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3860 EVEX_V256, EVEX_CD8<32, CD8VF>;
3861 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3862 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3863 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3864 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3867 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3869 //===----------------------------------------------------------------------===//
3870 // AVX-512 VPTESTM instructions
3871 //===----------------------------------------------------------------------===//
3873 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3874 X86VectorVTInfo _> {
3875 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3876 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3877 "$src2, $src1", "$src1, $src2",
3878 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3881 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3882 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3883 "$src2, $src1", "$src1, $src2",
3884 (OpNode (_.VT _.RC:$src1),
3885 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3887 EVEX_CD8<_.EltSize, CD8VF>;
3890 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3891 X86VectorVTInfo _> {
3893 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3894 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3895 "${src2}"##_.BroadcastStr##", $src1",
3896 "$src1, ${src2}"##_.BroadcastStr,
3897 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3898 (_.ScalarLdFrag addr:$src2))))>,
3899 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3901 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3902 AVX512VLVectorVTInfo _> {
3903 let Predicates = [HasAVX512] in
3904 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3905 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3907 let Predicates = [HasAVX512, HasVLX] in {
3908 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3909 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3910 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3911 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3915 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3916 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3918 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3919 avx512vl_i64_info>, VEX_W;
3922 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3924 let Predicates = [HasBWI] in {
3925 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3927 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3930 let Predicates = [HasVLX, HasBWI] in {
3932 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3934 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3936 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3938 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3943 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3945 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3946 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3948 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3949 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3951 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3952 (v16i32 VR512:$src2), (i16 -1))),
3953 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3955 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3956 (v8i64 VR512:$src2), (i8 -1))),
3957 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3959 //===----------------------------------------------------------------------===//
3960 // AVX-512 Shift instructions
3961 //===----------------------------------------------------------------------===//
3962 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3963 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3964 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3965 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3966 "$src2, $src1", "$src1, $src2",
3967 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3968 SSE_INTSHIFT_ITINS_P.rr>;
3970 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3971 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3972 "$src2, $src1", "$src1, $src2",
3973 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3975 SSE_INTSHIFT_ITINS_P.rm>;
3978 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3979 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3981 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3982 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3983 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3984 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3985 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3988 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3989 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3990 // src2 is always 128-bit
3991 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3992 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3993 "$src2, $src1", "$src1, $src2",
3994 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3995 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3996 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3997 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3998 "$src2, $src1", "$src1, $src2",
3999 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4000 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4004 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4005 ValueType SrcVT, PatFrag bc_frag,
4006 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4007 let Predicates = [prd] in
4008 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4009 VTInfo.info512>, EVEX_V512,
4010 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4011 let Predicates = [prd, HasVLX] in {
4012 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4013 VTInfo.info256>, EVEX_V256,
4014 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4015 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4016 VTInfo.info128>, EVEX_V128,
4017 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4021 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4022 string OpcodeStr, SDNode OpNode> {
4023 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4024 avx512vl_i32_info, HasAVX512>;
4025 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4026 avx512vl_i64_info, HasAVX512>, VEX_W;
4027 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4028 avx512vl_i16_info, HasBWI>;
4031 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4032 string OpcodeStr, SDNode OpNode,
4033 AVX512VLVectorVTInfo VTInfo> {
4034 let Predicates = [HasAVX512] in
4035 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4037 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4038 VTInfo.info512>, EVEX_V512;
4039 let Predicates = [HasAVX512, HasVLX] in {
4040 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4042 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4043 VTInfo.info256>, EVEX_V256;
4044 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4046 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4047 VTInfo.info128>, EVEX_V128;
4051 multiclass avx512_shift_rmi_w<bits<8> opcw,
4052 Format ImmFormR, Format ImmFormM,
4053 string OpcodeStr, SDNode OpNode> {
4054 let Predicates = [HasBWI] in
4055 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4056 v32i16_info>, EVEX_V512;
4057 let Predicates = [HasVLX, HasBWI] in {
4058 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4059 v16i16x_info>, EVEX_V256;
4060 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4061 v8i16x_info>, EVEX_V128;
4065 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4066 Format ImmFormR, Format ImmFormM,
4067 string OpcodeStr, SDNode OpNode> {
4068 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4069 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4070 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4071 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4074 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4075 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4077 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4078 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4080 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4081 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4083 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4084 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4086 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4087 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4088 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4090 //===-------------------------------------------------------------------===//
4091 // Variable Bit Shifts
4092 //===-------------------------------------------------------------------===//
4093 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4094 X86VectorVTInfo _> {
4095 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4096 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4097 "$src2, $src1", "$src1, $src2",
4098 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4099 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4101 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4102 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4103 "$src2, $src1", "$src1, $src2",
4104 (_.VT (OpNode _.RC:$src1,
4105 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4106 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4107 EVEX_CD8<_.EltSize, CD8VF>;
4110 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4111 X86VectorVTInfo _> {
4113 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4114 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4115 "${src2}"##_.BroadcastStr##", $src1",
4116 "$src1, ${src2}"##_.BroadcastStr,
4117 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4118 (_.ScalarLdFrag addr:$src2))))),
4119 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4120 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4122 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4123 AVX512VLVectorVTInfo _> {
4124 let Predicates = [HasAVX512] in
4125 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4126 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4128 let Predicates = [HasAVX512, HasVLX] in {
4129 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4130 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4131 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4132 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4136 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4138 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4140 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4141 avx512vl_i64_info>, VEX_W;
4144 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4146 let Predicates = [HasBWI] in
4147 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4149 let Predicates = [HasVLX, HasBWI] in {
4151 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4153 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4158 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4159 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4160 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4161 avx512_var_shift_w<0x11, "vpsravw", sra>;
4162 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4163 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4164 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4165 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4167 //===-------------------------------------------------------------------===//
4168 // 1-src variable permutation VPERMW/D/Q
4169 //===-------------------------------------------------------------------===//
4170 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4171 AVX512VLVectorVTInfo _> {
4172 let Predicates = [HasAVX512] in
4173 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4174 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4176 let Predicates = [HasAVX512, HasVLX] in
4177 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4178 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4181 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4182 string OpcodeStr, SDNode OpNode,
4183 AVX512VLVectorVTInfo VTInfo> {
4184 let Predicates = [HasAVX512] in
4185 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4187 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4188 VTInfo.info512>, EVEX_V512;
4189 let Predicates = [HasAVX512, HasVLX] in
4190 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4192 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4193 VTInfo.info256>, EVEX_V256;
4197 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4199 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4201 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4202 avx512vl_i64_info>, VEX_W;
4203 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4205 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4206 avx512vl_f64_info>, VEX_W;
4208 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4209 X86VPermi, avx512vl_i64_info>,
4210 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4211 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4212 X86VPermi, avx512vl_f64_info>,
4213 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4214 //===----------------------------------------------------------------------===//
4215 // AVX-512 - VPERMIL
4216 //===----------------------------------------------------------------------===//
4218 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4219 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4220 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4221 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4222 "$src2, $src1", "$src1, $src2",
4223 (_.VT (OpNode _.RC:$src1,
4224 (Ctrl.VT Ctrl.RC:$src2)))>,
4226 let mayLoad = 1 in {
4227 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4228 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4229 "$src2, $src1", "$src1, $src2",
4232 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4233 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4234 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4235 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4236 "${src2}"##_.BroadcastStr##", $src1",
4237 "$src1, ${src2}"##_.BroadcastStr,
4240 (Ctrl.VT (X86VBroadcast
4241 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4242 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4246 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4247 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4248 let Predicates = [HasAVX512] in {
4249 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4250 Ctrl.info512>, EVEX_V512;
4252 let Predicates = [HasAVX512, HasVLX] in {
4253 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4254 Ctrl.info128>, EVEX_V128;
4255 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4256 Ctrl.info256>, EVEX_V256;
4260 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4261 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4263 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4264 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4266 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4268 let isCodeGenOnly = 1 in {
4269 // lowering implementation with the alternative types
4270 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4271 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4272 OpcodeStr, X86VPermilpi, Ctrl>,
4273 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4277 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4279 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4280 avx512vl_i64_info>, VEX_W;
4281 //===----------------------------------------------------------------------===//
4282 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4283 //===----------------------------------------------------------------------===//
4285 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4286 X86PShufd, avx512vl_i32_info>,
4287 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4288 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4289 X86PShufhw>, EVEX, AVX512XSIi8Base;
4290 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4291 X86PShuflw>, EVEX, AVX512XDIi8Base;
4293 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4294 let Predicates = [HasBWI] in
4295 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4297 let Predicates = [HasVLX, HasBWI] in {
4298 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4299 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4303 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4305 //===----------------------------------------------------------------------===//
4306 // Move Low to High and High to Low packed FP Instructions
4307 //===----------------------------------------------------------------------===//
4308 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4309 (ins VR128X:$src1, VR128X:$src2),
4310 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4311 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4312 IIC_SSE_MOV_LH>, EVEX_4V;
4313 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4314 (ins VR128X:$src1, VR128X:$src2),
4315 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4316 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4317 IIC_SSE_MOV_LH>, EVEX_4V;
4319 let Predicates = [HasAVX512] in {
4321 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4322 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4323 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4324 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4327 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4328 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4331 //===----------------------------------------------------------------------===//
4332 // VMOVHPS/PD VMOVLPS Instructions
4333 // All patterns was taken from SSS implementation.
4334 //===----------------------------------------------------------------------===//
4335 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4336 X86VectorVTInfo _> {
4338 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4339 (ins _.RC:$src1, f64mem:$src2),
4340 !strconcat(OpcodeStr,
4341 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4345 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4346 IIC_SSE_MOV_LH>, EVEX_4V;
4349 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4350 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4351 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4352 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4353 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4354 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4355 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4356 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4358 let Predicates = [HasAVX512] in {
4360 def : Pat<(X86Movlhps VR128X:$src1,
4361 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4362 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4363 def : Pat<(X86Movlhps VR128X:$src1,
4364 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4365 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4367 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4368 (scalar_to_vector (loadf64 addr:$src2)))),
4369 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4370 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4371 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4372 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4374 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4375 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4376 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4377 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4379 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4380 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4381 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4382 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4383 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4384 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4385 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4388 let mayStore = 1 in {
4389 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4390 (ins f64mem:$dst, VR128X:$src),
4391 "vmovhps\t{$src, $dst|$dst, $src}",
4392 [(store (f64 (vector_extract
4393 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4394 (bc_v2f64 (v4f32 VR128X:$src))),
4395 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4396 EVEX, EVEX_CD8<32, CD8VT2>;
4397 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4398 (ins f64mem:$dst, VR128X:$src),
4399 "vmovhpd\t{$src, $dst|$dst, $src}",
4400 [(store (f64 (vector_extract
4401 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4402 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4403 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4404 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4405 (ins f64mem:$dst, VR128X:$src),
4406 "vmovlps\t{$src, $dst|$dst, $src}",
4407 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4408 (iPTR 0))), addr:$dst)],
4410 EVEX, EVEX_CD8<32, CD8VT2>;
4411 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4412 (ins f64mem:$dst, VR128X:$src),
4413 "vmovlpd\t{$src, $dst|$dst, $src}",
4414 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4415 (iPTR 0))), addr:$dst)],
4417 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4419 let Predicates = [HasAVX512] in {
4421 def : Pat<(store (f64 (vector_extract
4422 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4423 (iPTR 0))), addr:$dst),
4424 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4426 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4428 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4429 def : Pat<(store (v4i32 (X86Movlps
4430 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4431 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4433 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4435 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4436 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4438 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4440 //===----------------------------------------------------------------------===//
4441 // FMA - Fused Multiply Operations
4444 let Constraints = "$src1 = $dst" in {
4445 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4446 X86VectorVTInfo _> {
4447 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4448 (ins _.RC:$src2, _.RC:$src3),
4449 OpcodeStr, "$src3, $src2", "$src2, $src3",
4450 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4453 let mayLoad = 1 in {
4454 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4455 (ins _.RC:$src2, _.MemOp:$src3),
4456 OpcodeStr, "$src3, $src2", "$src2, $src3",
4457 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4460 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4461 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4462 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4463 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4465 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4466 AVX512FMA3Base, EVEX_B;
4470 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4471 X86VectorVTInfo _> {
4472 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4473 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4474 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4475 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4476 AVX512FMA3Base, EVEX_B, EVEX_RC;
4478 } // Constraints = "$src1 = $dst"
4480 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4481 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4482 let Predicates = [HasAVX512] in {
4483 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4484 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4485 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4487 let Predicates = [HasVLX, HasAVX512] in {
4488 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4489 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4490 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4491 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4495 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4496 SDNode OpNodeRnd > {
4497 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4499 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4500 avx512vl_f64_info>, VEX_W;
4503 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4504 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4505 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4506 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4507 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4508 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4511 let Constraints = "$src1 = $dst" in {
4512 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4513 X86VectorVTInfo _> {
4514 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4515 (ins _.RC:$src2, _.RC:$src3),
4516 OpcodeStr, "$src3, $src2", "$src2, $src3",
4517 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4520 let mayLoad = 1 in {
4521 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4522 (ins _.RC:$src2, _.MemOp:$src3),
4523 OpcodeStr, "$src3, $src2", "$src2, $src3",
4524 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4527 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4528 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4529 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4530 "$src2, ${src3}"##_.BroadcastStr,
4531 (_.VT (OpNode _.RC:$src2,
4532 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4533 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4537 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4538 X86VectorVTInfo _> {
4539 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4540 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4541 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4542 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4543 AVX512FMA3Base, EVEX_B, EVEX_RC;
4545 } // Constraints = "$src1 = $dst"
4547 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4548 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4549 let Predicates = [HasAVX512] in {
4550 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4551 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4552 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4554 let Predicates = [HasVLX, HasAVX512] in {
4555 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4556 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4557 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4558 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4562 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4563 SDNode OpNodeRnd > {
4564 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4566 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4567 avx512vl_f64_info>, VEX_W;
4570 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4571 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4572 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4573 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4574 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4575 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4577 let Constraints = "$src1 = $dst" in {
4578 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4579 X86VectorVTInfo _> {
4580 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4581 (ins _.RC:$src3, _.RC:$src2),
4582 OpcodeStr, "$src2, $src3", "$src3, $src2",
4583 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4586 let mayLoad = 1 in {
4587 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4588 (ins _.RC:$src3, _.MemOp:$src2),
4589 OpcodeStr, "$src2, $src3", "$src3, $src2",
4590 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4593 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4594 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4595 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4596 "$src3, ${src2}"##_.BroadcastStr,
4597 (_.VT (OpNode _.RC:$src1,
4598 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4599 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4603 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4604 X86VectorVTInfo _> {
4605 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4606 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4607 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4608 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4609 AVX512FMA3Base, EVEX_B, EVEX_RC;
4611 } // Constraints = "$src1 = $dst"
4613 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4614 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4615 let Predicates = [HasAVX512] in {
4616 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4617 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4618 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4620 let Predicates = [HasVLX, HasAVX512] in {
4621 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4622 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4623 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4624 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4628 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4629 SDNode OpNodeRnd > {
4630 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4632 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4633 avx512vl_f64_info>, VEX_W;
4636 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4637 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4638 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4639 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4640 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4641 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4644 let Constraints = "$src1 = $dst" in {
4645 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4646 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4647 dag RHS_r, dag RHS_m > {
4648 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4649 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4650 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4653 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4654 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4655 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4657 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4658 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4659 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4660 AVX512FMA3Base, EVEX_B, EVEX_RC;
4662 let isCodeGenOnly = 1 in {
4663 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4664 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4665 !strconcat(OpcodeStr,
4666 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4669 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4670 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4671 !strconcat(OpcodeStr,
4672 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4674 }// isCodeGenOnly = 1
4676 }// Constraints = "$src1 = $dst"
4678 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4679 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4682 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4683 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4684 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4685 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4686 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4688 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4690 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4691 (_.ScalarLdFrag addr:$src3))))>;
4693 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4694 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4695 (_.VT (OpNode _.RC:$src2,
4696 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4698 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4700 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4702 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4703 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4705 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4706 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4707 (_.VT (OpNode _.RC:$src1,
4708 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4710 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4712 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4714 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4715 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4718 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4719 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4720 let Predicates = [HasAVX512] in {
4721 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4722 OpNodeRnd, f32x_info, "SS">,
4723 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4724 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4725 OpNodeRnd, f64x_info, "SD">,
4726 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4730 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4731 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4732 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4733 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4735 //===----------------------------------------------------------------------===//
4736 // AVX-512 Scalar convert from sign integer to float/double
4737 //===----------------------------------------------------------------------===//
4739 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4740 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4741 PatFrag ld_frag, string asm> {
4742 let hasSideEffects = 0 in {
4743 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4744 (ins DstVT.FRC:$src1, SrcRC:$src),
4745 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4748 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4749 (ins DstVT.FRC:$src1, x86memop:$src),
4750 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4752 } // hasSideEffects = 0
4753 let isCodeGenOnly = 1 in {
4754 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4755 (ins DstVT.RC:$src1, SrcRC:$src2),
4756 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4757 [(set DstVT.RC:$dst,
4758 (OpNode (DstVT.VT DstVT.RC:$src1),
4760 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4762 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4763 (ins DstVT.RC:$src1, x86memop:$src2),
4764 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4765 [(set DstVT.RC:$dst,
4766 (OpNode (DstVT.VT DstVT.RC:$src1),
4767 (ld_frag addr:$src2),
4768 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4769 }//isCodeGenOnly = 1
4772 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4773 X86VectorVTInfo DstVT, string asm> {
4774 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4775 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4777 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4778 [(set DstVT.RC:$dst,
4779 (OpNode (DstVT.VT DstVT.RC:$src1),
4781 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4784 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4785 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4786 PatFrag ld_frag, string asm> {
4787 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4788 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4792 let Predicates = [HasAVX512] in {
4793 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4794 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4795 XS, EVEX_CD8<32, CD8VT1>;
4796 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4797 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4798 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4799 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4800 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4801 XD, EVEX_CD8<32, CD8VT1>;
4802 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4803 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4804 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4806 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4807 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4808 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4809 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4810 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4811 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4812 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4813 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4815 def : Pat<(f32 (sint_to_fp GR32:$src)),
4816 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4817 def : Pat<(f32 (sint_to_fp GR64:$src)),
4818 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4819 def : Pat<(f64 (sint_to_fp GR32:$src)),
4820 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4821 def : Pat<(f64 (sint_to_fp GR64:$src)),
4822 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4824 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4825 v4f32x_info, i32mem, loadi32,
4826 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4827 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4828 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4829 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4830 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4831 i32mem, loadi32, "cvtusi2sd{l}">,
4832 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4833 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4834 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4835 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4837 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4838 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4839 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4840 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4841 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4842 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4843 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4844 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4846 def : Pat<(f32 (uint_to_fp GR32:$src)),
4847 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4848 def : Pat<(f32 (uint_to_fp GR64:$src)),
4849 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4850 def : Pat<(f64 (uint_to_fp GR32:$src)),
4851 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4852 def : Pat<(f64 (uint_to_fp GR64:$src)),
4853 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4856 //===----------------------------------------------------------------------===//
4857 // AVX-512 Scalar convert from float/double to integer
4858 //===----------------------------------------------------------------------===//
4859 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4860 RegisterClass DstRC, Intrinsic Int,
4861 Operand memop, ComplexPattern mem_cpat, string asm> {
4862 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4863 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4864 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4865 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4866 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4867 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4868 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4870 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4871 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4872 } // hasSideEffects = 0, Predicates = [HasAVX512]
4875 // Convert float/double to signed/unsigned int 32/64
4876 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4877 ssmem, sse_load_f32, "cvtss2si">,
4878 XS, EVEX_CD8<32, CD8VT1>;
4879 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4880 int_x86_sse_cvtss2si64,
4881 ssmem, sse_load_f32, "cvtss2si">,
4882 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4883 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4884 int_x86_avx512_cvtss2usi,
4885 ssmem, sse_load_f32, "cvtss2usi">,
4886 XS, EVEX_CD8<32, CD8VT1>;
4887 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4888 int_x86_avx512_cvtss2usi64, ssmem,
4889 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4890 EVEX_CD8<32, CD8VT1>;
4891 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4892 sdmem, sse_load_f64, "cvtsd2si">,
4893 XD, EVEX_CD8<64, CD8VT1>;
4894 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4895 int_x86_sse2_cvtsd2si64,
4896 sdmem, sse_load_f64, "cvtsd2si">,
4897 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4898 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4899 int_x86_avx512_cvtsd2usi,
4900 sdmem, sse_load_f64, "cvtsd2usi">,
4901 XD, EVEX_CD8<64, CD8VT1>;
4902 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4903 int_x86_avx512_cvtsd2usi64, sdmem,
4904 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4905 EVEX_CD8<64, CD8VT1>;
4907 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4908 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4909 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4910 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4911 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4912 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4913 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4914 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4915 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4916 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4917 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4918 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4919 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4921 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4922 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4923 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4924 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4926 // Convert float/double to signed/unsigned int 32/64 with truncation
4927 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4928 X86VectorVTInfo _DstRC, SDNode OpNode,
4930 let Predicates = [HasAVX512] in {
4931 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4932 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4933 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4934 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4935 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4937 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4938 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4939 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4942 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4943 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4944 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4945 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4946 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4947 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4948 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4949 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4950 (i32 FROUND_NO_EXC)))]>,
4951 EVEX,VEX_LIG , EVEX_B;
4953 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4954 (ins _SrcRC.MemOp:$src),
4955 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4958 } // isCodeGenOnly = 1, hasSideEffects = 0
4963 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4964 fp_to_sint,X86cvttss2IntRnd>,
4965 XS, EVEX_CD8<32, CD8VT1>;
4966 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4967 fp_to_sint,X86cvttss2IntRnd>,
4968 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4969 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4970 fp_to_sint,X86cvttsd2IntRnd>,
4971 XD, EVEX_CD8<64, CD8VT1>;
4972 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4973 fp_to_sint,X86cvttsd2IntRnd>,
4974 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4976 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4977 fp_to_uint,X86cvttss2UIntRnd>,
4978 XS, EVEX_CD8<32, CD8VT1>;
4979 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4980 fp_to_uint,X86cvttss2UIntRnd>,
4981 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4982 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4983 fp_to_uint,X86cvttsd2UIntRnd>,
4984 XD, EVEX_CD8<64, CD8VT1>;
4985 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4986 fp_to_uint,X86cvttsd2UIntRnd>,
4987 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4988 let Predicates = [HasAVX512] in {
4989 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4990 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4991 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4992 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4993 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4994 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4995 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4996 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4999 //===----------------------------------------------------------------------===//
5000 // AVX-512 Convert form float to double and back
5001 //===----------------------------------------------------------------------===//
5002 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5003 X86VectorVTInfo _Src, SDNode OpNode> {
5004 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5005 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5006 "$src2, $src1", "$src1, $src2",
5007 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5008 (_Src.VT _Src.RC:$src2)))>,
5009 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5010 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5011 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5012 "$src2, $src1", "$src1, $src2",
5013 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5014 (_Src.VT (scalar_to_vector
5015 (_Src.ScalarLdFrag addr:$src2)))))>,
5016 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5019 // Scalar Coversion with SAE - suppress all exceptions
5020 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5021 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5022 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5023 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5024 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5025 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5026 (_Src.VT _Src.RC:$src2),
5027 (i32 FROUND_NO_EXC)))>,
5028 EVEX_4V, VEX_LIG, EVEX_B;
5031 // Scalar Conversion with rounding control (RC)
5032 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5033 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5034 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5035 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5036 "$rc, $src2, $src1", "$src1, $src2, $rc",
5037 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5038 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5039 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5042 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5043 SDNode OpNodeRnd, X86VectorVTInfo _src,
5044 X86VectorVTInfo _dst> {
5045 let Predicates = [HasAVX512] in {
5046 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5047 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5048 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5053 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5054 SDNode OpNodeRnd, X86VectorVTInfo _src,
5055 X86VectorVTInfo _dst> {
5056 let Predicates = [HasAVX512] in {
5057 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5058 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5059 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5062 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5063 X86froundRnd, f64x_info, f32x_info>;
5064 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5065 X86fpextRnd,f32x_info, f64x_info >;
5067 def : Pat<(f64 (fextend FR32X:$src)),
5068 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5069 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5070 Requires<[HasAVX512]>;
5071 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5072 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5073 Requires<[HasAVX512]>;
5075 def : Pat<(f64 (extloadf32 addr:$src)),
5076 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5077 Requires<[HasAVX512, OptForSize]>;
5079 def : Pat<(f64 (extloadf32 addr:$src)),
5080 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5081 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5082 Requires<[HasAVX512, OptForSpeed]>;
5084 def : Pat<(f32 (fround FR64X:$src)),
5085 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5086 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5087 Requires<[HasAVX512]>;
5088 //===----------------------------------------------------------------------===//
5089 // AVX-512 Vector convert from signed/unsigned integer to float/double
5090 // and from float/double to signed/unsigned integer
5091 //===----------------------------------------------------------------------===//
5093 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5094 X86VectorVTInfo _Src, SDNode OpNode,
5095 string Broadcast = _.BroadcastStr,
5096 string Alias = ""> {
5098 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5099 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5100 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5102 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5103 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5104 (_.VT (OpNode (_Src.VT
5105 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5107 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5108 (ins _Src.MemOp:$src), OpcodeStr,
5109 "${src}"##Broadcast, "${src}"##Broadcast,
5110 (_.VT (OpNode (_Src.VT
5111 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5114 // Coversion with SAE - suppress all exceptions
5115 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5116 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5117 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5118 (ins _Src.RC:$src), OpcodeStr,
5119 "{sae}, $src", "$src, {sae}",
5120 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5121 (i32 FROUND_NO_EXC)))>,
5125 // Conversion with rounding control (RC)
5126 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5127 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5128 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5129 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5130 "$rc, $src", "$src, $rc",
5131 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5132 EVEX, EVEX_B, EVEX_RC;
5135 // Extend Float to Double
5136 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5137 let Predicates = [HasAVX512] in {
5138 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5139 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5140 X86vfpextRnd>, EVEX_V512;
5142 let Predicates = [HasVLX] in {
5143 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5144 X86vfpext, "{1to2}">, EVEX_V128;
5145 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5150 // Truncate Double to Float
5151 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5152 let Predicates = [HasAVX512] in {
5153 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5154 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5155 X86vfproundRnd>, EVEX_V512;
5157 let Predicates = [HasVLX] in {
5158 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5159 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5160 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5161 "{1to4}", "{y}">, EVEX_V256;
5165 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5166 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5167 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5168 PS, EVEX_CD8<32, CD8VH>;
5170 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5171 (VCVTPS2PDZrm addr:$src)>;
5173 let Predicates = [HasVLX] in {
5174 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5175 (VCVTPS2PDZ256rm addr:$src)>;
5178 // Convert Signed/Unsigned Doubleword to Double
5179 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5181 // No rounding in this op
5182 let Predicates = [HasAVX512] in
5183 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5186 let Predicates = [HasVLX] in {
5187 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5188 OpNode128, "{1to2}">, EVEX_V128;
5189 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5194 // Convert Signed/Unsigned Doubleword to Float
5195 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5197 let Predicates = [HasAVX512] in
5198 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5199 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5200 OpNodeRnd>, EVEX_V512;
5202 let Predicates = [HasVLX] in {
5203 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5205 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5210 // Convert Float to Signed/Unsigned Doubleword with truncation
5211 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5212 SDNode OpNode, SDNode OpNodeRnd> {
5213 let Predicates = [HasAVX512] in {
5214 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5215 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5216 OpNodeRnd>, EVEX_V512;
5218 let Predicates = [HasVLX] in {
5219 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5221 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5226 // Convert Float to Signed/Unsigned Doubleword
5227 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5228 SDNode OpNode, SDNode OpNodeRnd> {
5229 let Predicates = [HasAVX512] in {
5230 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5231 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5232 OpNodeRnd>, EVEX_V512;
5234 let Predicates = [HasVLX] in {
5235 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5237 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5242 // Convert Double to Signed/Unsigned Doubleword with truncation
5243 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5244 SDNode OpNode, SDNode OpNodeRnd> {
5245 let Predicates = [HasAVX512] in {
5246 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5247 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5248 OpNodeRnd>, EVEX_V512;
5250 let Predicates = [HasVLX] in {
5251 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5252 // memory forms of these instructions in Asm Parcer. They have the same
5253 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5254 // due to the same reason.
5255 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5256 "{1to2}", "{x}">, EVEX_V128;
5257 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5258 "{1to4}", "{y}">, EVEX_V256;
5262 // Convert Double to Signed/Unsigned Doubleword
5263 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5264 SDNode OpNode, SDNode OpNodeRnd> {
5265 let Predicates = [HasAVX512] in {
5266 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5267 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5268 OpNodeRnd>, EVEX_V512;
5270 let Predicates = [HasVLX] in {
5271 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5272 // memory forms of these instructions in Asm Parcer. They have the same
5273 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5274 // due to the same reason.
5275 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5276 "{1to2}", "{x}">, EVEX_V128;
5277 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5278 "{1to4}", "{y}">, EVEX_V256;
5282 // Convert Double to Signed/Unsigned Quardword
5283 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5284 SDNode OpNode, SDNode OpNodeRnd> {
5285 let Predicates = [HasDQI] in {
5286 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5287 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5288 OpNodeRnd>, EVEX_V512;
5290 let Predicates = [HasDQI, HasVLX] in {
5291 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5293 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5298 // Convert Double to Signed/Unsigned Quardword with truncation
5299 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5300 SDNode OpNode, SDNode OpNodeRnd> {
5301 let Predicates = [HasDQI] in {
5302 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5303 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5304 OpNodeRnd>, EVEX_V512;
5306 let Predicates = [HasDQI, HasVLX] in {
5307 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5309 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5314 // Convert Signed/Unsigned Quardword to Double
5315 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5316 SDNode OpNode, SDNode OpNodeRnd> {
5317 let Predicates = [HasDQI] in {
5318 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5319 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5320 OpNodeRnd>, EVEX_V512;
5322 let Predicates = [HasDQI, HasVLX] in {
5323 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5325 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5330 // Convert Float to Signed/Unsigned Quardword
5331 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5332 SDNode OpNode, SDNode OpNodeRnd> {
5333 let Predicates = [HasDQI] in {
5334 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5335 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5336 OpNodeRnd>, EVEX_V512;
5338 let Predicates = [HasDQI, HasVLX] in {
5339 // Explicitly specified broadcast string, since we take only 2 elements
5340 // from v4f32x_info source
5341 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5342 "{1to2}">, EVEX_V128;
5343 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5348 // Convert Float to Signed/Unsigned Quardword with truncation
5349 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5350 SDNode OpNode, SDNode OpNodeRnd> {
5351 let Predicates = [HasDQI] in {
5352 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5353 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5354 OpNodeRnd>, EVEX_V512;
5356 let Predicates = [HasDQI, HasVLX] in {
5357 // Explicitly specified broadcast string, since we take only 2 elements
5358 // from v4f32x_info source
5359 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5360 "{1to2}">, EVEX_V128;
5361 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5366 // Convert Signed/Unsigned Quardword to Float
5367 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5368 SDNode OpNode, SDNode OpNodeRnd> {
5369 let Predicates = [HasDQI] in {
5370 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5371 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5372 OpNodeRnd>, EVEX_V512;
5374 let Predicates = [HasDQI, HasVLX] in {
5375 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5376 // memory forms of these instructions in Asm Parcer. They have the same
5377 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5378 // due to the same reason.
5379 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5380 "{1to2}", "{x}">, EVEX_V128;
5381 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5382 "{1to4}", "{y}">, EVEX_V256;
5386 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5387 EVEX_CD8<32, CD8VH>;
5389 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5391 PS, EVEX_CD8<32, CD8VF>;
5393 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5395 XS, EVEX_CD8<32, CD8VF>;
5397 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5399 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5401 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5402 X86VFpToUintRnd>, PS,
5403 EVEX_CD8<32, CD8VF>;
5405 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5406 X86VFpToUintRnd>, PS, VEX_W,
5407 EVEX_CD8<64, CD8VF>;
5409 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5410 XS, EVEX_CD8<32, CD8VH>;
5412 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5413 X86VUintToFpRnd>, XD,
5414 EVEX_CD8<32, CD8VF>;
5416 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5417 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5419 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5420 X86cvtpd2IntRnd>, XD, VEX_W,
5421 EVEX_CD8<64, CD8VF>;
5423 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5425 PS, EVEX_CD8<32, CD8VF>;
5426 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5427 X86cvtpd2UIntRnd>, VEX_W,
5428 PS, EVEX_CD8<64, CD8VF>;
5430 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5431 X86cvtpd2IntRnd>, VEX_W,
5432 PD, EVEX_CD8<64, CD8VF>;
5434 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5435 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5437 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5438 X86cvtpd2UIntRnd>, VEX_W,
5439 PD, EVEX_CD8<64, CD8VF>;
5441 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5442 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5444 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5445 X86VFpToSlongRnd>, VEX_W,
5446 PD, EVEX_CD8<64, CD8VF>;
5448 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5449 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5451 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5452 X86VFpToUlongRnd>, VEX_W,
5453 PD, EVEX_CD8<64, CD8VF>;
5455 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5456 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5458 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5459 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5461 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5462 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5464 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5465 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5467 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5468 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5470 let Predicates = [NoVLX] in {
5471 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5472 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5473 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5475 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5476 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5477 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5479 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5480 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5481 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5483 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5484 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5485 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5487 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5488 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5489 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5492 let Predicates = [HasAVX512] in {
5493 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5494 (VCVTPD2PSZrm addr:$src)>;
5495 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5496 (VCVTPS2PDZrm addr:$src)>;
5499 //===----------------------------------------------------------------------===//
5500 // Half precision conversion instructions
5501 //===----------------------------------------------------------------------===//
5502 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5503 X86MemOperand x86memop, PatFrag ld_frag> {
5504 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5505 "vcvtph2ps", "$src", "$src",
5506 (X86cvtph2ps (_src.VT _src.RC:$src),
5507 (i32 FROUND_CURRENT))>, T8PD;
5508 let hasSideEffects = 0, mayLoad = 1 in {
5509 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5510 "vcvtph2ps", "$src", "$src",
5511 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5512 (i32 FROUND_CURRENT))>, T8PD;
5516 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5517 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5518 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5519 (X86cvtph2ps (_src.VT _src.RC:$src),
5520 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5524 let Predicates = [HasAVX512] in {
5525 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5526 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5527 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5528 let Predicates = [HasVLX] in {
5529 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5530 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5531 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5532 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5536 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5537 X86MemOperand x86memop> {
5538 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5539 (ins _src.RC:$src1, i32u8imm:$src2),
5540 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5541 (X86cvtps2ph (_src.VT _src.RC:$src1),
5543 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5544 let hasSideEffects = 0, mayStore = 1 in {
5545 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5546 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5547 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5548 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5549 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5551 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5552 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5553 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5557 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5558 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5559 (ins _src.RC:$src1, i32u8imm:$src2),
5560 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5561 (X86cvtps2ph (_src.VT _src.RC:$src1),
5563 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5565 let Predicates = [HasAVX512] in {
5566 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5567 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5568 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5569 let Predicates = [HasVLX] in {
5570 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5571 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5572 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5573 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5576 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5577 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5578 "ucomiss">, PS, EVEX, VEX_LIG,
5579 EVEX_CD8<32, CD8VT1>;
5580 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5581 "ucomisd">, PD, EVEX,
5582 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5583 let Pattern = []<dag> in {
5584 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5585 "comiss">, PS, EVEX, VEX_LIG,
5586 EVEX_CD8<32, CD8VT1>;
5587 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5588 "comisd">, PD, EVEX,
5589 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5591 let isCodeGenOnly = 1 in {
5592 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5593 load, "ucomiss">, PS, EVEX, VEX_LIG,
5594 EVEX_CD8<32, CD8VT1>;
5595 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5596 load, "ucomisd">, PD, EVEX,
5597 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5599 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5600 load, "comiss">, PS, EVEX, VEX_LIG,
5601 EVEX_CD8<32, CD8VT1>;
5602 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5603 load, "comisd">, PD, EVEX,
5604 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5608 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5609 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5610 X86VectorVTInfo _> {
5611 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5612 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5613 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5614 "$src2, $src1", "$src1, $src2",
5615 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5616 let mayLoad = 1 in {
5617 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5618 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5619 "$src2, $src1", "$src1, $src2",
5620 (OpNode (_.VT _.RC:$src1),
5621 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5626 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5627 EVEX_CD8<32, CD8VT1>, T8PD;
5628 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5629 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5630 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5631 EVEX_CD8<32, CD8VT1>, T8PD;
5632 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5633 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5635 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5636 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5637 X86VectorVTInfo _> {
5638 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5639 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5640 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5641 let mayLoad = 1 in {
5642 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5643 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5645 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5646 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5647 (ins _.ScalarMemOp:$src), OpcodeStr,
5648 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5650 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5655 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5656 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5657 EVEX_V512, EVEX_CD8<32, CD8VF>;
5658 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5659 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5661 // Define only if AVX512VL feature is present.
5662 let Predicates = [HasVLX] in {
5663 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5664 OpNode, v4f32x_info>,
5665 EVEX_V128, EVEX_CD8<32, CD8VF>;
5666 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5667 OpNode, v8f32x_info>,
5668 EVEX_V256, EVEX_CD8<32, CD8VF>;
5669 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5670 OpNode, v2f64x_info>,
5671 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5672 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5673 OpNode, v4f64x_info>,
5674 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5678 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5679 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5681 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5682 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5683 (VRSQRT14PSZr VR512:$src)>;
5684 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5685 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5686 (VRSQRT14PDZr VR512:$src)>;
5688 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5689 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5690 (VRCP14PSZr VR512:$src)>;
5691 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5692 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5693 (VRCP14PDZr VR512:$src)>;
5695 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5696 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5699 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5700 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5701 "$src2, $src1", "$src1, $src2",
5702 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5703 (i32 FROUND_CURRENT))>;
5705 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5706 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5707 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5708 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5709 (i32 FROUND_NO_EXC))>, EVEX_B;
5711 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5712 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5713 "$src2, $src1", "$src1, $src2",
5714 (OpNode (_.VT _.RC:$src1),
5715 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5716 (i32 FROUND_CURRENT))>;
5719 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5720 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5721 EVEX_CD8<32, CD8VT1>;
5722 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5723 EVEX_CD8<64, CD8VT1>, VEX_W;
5726 let hasSideEffects = 0, Predicates = [HasERI] in {
5727 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5728 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5731 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5732 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5734 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5737 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5738 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5739 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5741 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5742 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5744 (bitconvert (_.LdFrag addr:$src))),
5745 (i32 FROUND_CURRENT))>;
5747 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5748 (ins _.MemOp:$src), OpcodeStr,
5749 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5751 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5752 (i32 FROUND_CURRENT))>, EVEX_B;
5754 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5756 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5757 (ins _.RC:$src), OpcodeStr,
5758 "{sae}, $src", "$src, {sae}",
5759 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5762 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5763 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5764 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5765 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5766 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5767 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5768 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5771 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5773 // Define only if AVX512VL feature is present.
5774 let Predicates = [HasVLX] in {
5775 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5776 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5777 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5778 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5779 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5780 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5781 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5782 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5785 let Predicates = [HasERI], hasSideEffects = 0 in {
5787 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5788 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5789 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5791 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5792 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5794 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5795 SDNode OpNodeRnd, X86VectorVTInfo _>{
5796 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5797 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5798 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5799 EVEX, EVEX_B, EVEX_RC;
5802 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5803 SDNode OpNode, X86VectorVTInfo _>{
5804 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5805 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5806 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5807 let mayLoad = 1 in {
5808 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5809 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5811 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5813 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5814 (ins _.ScalarMemOp:$src), OpcodeStr,
5815 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5817 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5822 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5824 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5826 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5827 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5829 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5830 // Define only if AVX512VL feature is present.
5831 let Predicates = [HasVLX] in {
5832 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5833 OpNode, v4f32x_info>,
5834 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5835 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5836 OpNode, v8f32x_info>,
5837 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5838 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5839 OpNode, v2f64x_info>,
5840 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5841 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5842 OpNode, v4f64x_info>,
5843 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5847 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5849 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5850 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5851 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5852 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5855 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5856 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5858 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5859 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5860 "$src2, $src1", "$src1, $src2",
5861 (OpNodeRnd (_.VT _.RC:$src1),
5863 (i32 FROUND_CURRENT))>;
5865 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5866 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5867 "$src2, $src1", "$src1, $src2",
5868 (OpNodeRnd (_.VT _.RC:$src1),
5869 (_.VT (scalar_to_vector
5870 (_.ScalarLdFrag addr:$src2))),
5871 (i32 FROUND_CURRENT))>;
5873 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5874 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5875 "$rc, $src2, $src1", "$src1, $src2, $rc",
5876 (OpNodeRnd (_.VT _.RC:$src1),
5881 let isCodeGenOnly = 1 in {
5882 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5883 (ins _.FRC:$src1, _.FRC:$src2),
5884 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5887 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5888 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5889 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5892 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5893 (!cast<Instruction>(NAME#SUFF#Zr)
5894 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5896 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5897 (!cast<Instruction>(NAME#SUFF#Zm)
5898 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5901 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5902 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5903 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5904 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5905 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5908 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5909 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5911 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5913 let Predicates = [HasAVX512] in {
5914 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5915 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5916 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5917 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5918 Requires<[OptForSize]>;
5919 def : Pat<(f32 (X86frcp FR32X:$src)),
5920 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5921 def : Pat<(f32 (X86frcp (load addr:$src))),
5922 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5923 Requires<[OptForSize]>;
5927 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5929 let ExeDomain = _.ExeDomain in {
5930 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5931 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5932 "$src3, $src2, $src1", "$src1, $src2, $src3",
5933 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5934 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5936 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5937 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5938 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5939 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5940 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5943 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5944 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5945 "$src3, $src2, $src1", "$src1, $src2, $src3",
5946 (_.VT (X86RndScales (_.VT _.RC:$src1),
5947 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5948 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5950 let Predicates = [HasAVX512] in {
5951 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5952 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5953 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5954 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5955 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5956 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5957 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5958 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5959 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5960 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5961 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5962 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5963 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5964 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5965 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5967 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5968 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5969 addr:$src, (i32 0x1))), _.FRC)>;
5970 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5971 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5972 addr:$src, (i32 0x2))), _.FRC)>;
5973 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5974 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5975 addr:$src, (i32 0x3))), _.FRC)>;
5976 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5977 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5978 addr:$src, (i32 0x4))), _.FRC)>;
5979 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5980 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5981 addr:$src, (i32 0xc))), _.FRC)>;
5985 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5986 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5988 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5989 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5991 //-------------------------------------------------
5992 // Integer truncate and extend operations
5993 //-------------------------------------------------
5995 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5996 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5997 X86MemOperand x86memop> {
5999 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6000 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6001 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6004 // for intrinsic patter match
6005 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6006 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6008 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6011 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6012 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6013 DestInfo.ImmAllZerosV)),
6014 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6017 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6018 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6019 DestInfo.RC:$src0)),
6020 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6021 DestInfo.KRCWM:$mask ,
6024 let mayStore = 1 in {
6025 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6026 (ins x86memop:$dst, SrcInfo.RC:$src),
6027 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6030 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6031 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6032 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6037 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6038 X86VectorVTInfo DestInfo,
6039 PatFrag truncFrag, PatFrag mtruncFrag > {
6041 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6042 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6043 addr:$dst, SrcInfo.RC:$src)>;
6045 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6046 (SrcInfo.VT SrcInfo.RC:$src)),
6047 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6048 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6051 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6052 X86VectorVTInfo DestInfo, string sat > {
6054 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6055 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6056 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6057 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6058 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6059 (SrcInfo.VT SrcInfo.RC:$src))>;
6061 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6062 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6063 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6064 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6065 (SrcInfo.VT SrcInfo.RC:$src))>;
6068 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6069 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6070 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6071 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6072 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6073 Predicate prd = HasAVX512>{
6075 let Predicates = [HasVLX, prd] in {
6076 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6077 DestInfoZ128, x86memopZ128>,
6078 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6079 truncFrag, mtruncFrag>, EVEX_V128;
6081 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6082 DestInfoZ256, x86memopZ256>,
6083 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6084 truncFrag, mtruncFrag>, EVEX_V256;
6086 let Predicates = [prd] in
6087 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6088 DestInfoZ, x86memopZ>,
6089 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6090 truncFrag, mtruncFrag>, EVEX_V512;
6093 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6094 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6095 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6096 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6097 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6099 let Predicates = [HasVLX, prd] in {
6100 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6101 DestInfoZ128, x86memopZ128>,
6102 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6105 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6106 DestInfoZ256, x86memopZ256>,
6107 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6110 let Predicates = [prd] in
6111 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6112 DestInfoZ, x86memopZ>,
6113 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6117 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6118 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6119 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6120 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6122 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6123 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6124 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6125 sat>, EVEX_CD8<8, CD8VO>;
6128 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6129 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6130 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6131 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6133 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6134 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6135 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6136 sat>, EVEX_CD8<16, CD8VQ>;
6139 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6140 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6141 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6142 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6144 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6145 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6146 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6147 sat>, EVEX_CD8<32, CD8VH>;
6150 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6151 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6152 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6153 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6155 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6156 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6157 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6158 sat>, EVEX_CD8<8, CD8VQ>;
6161 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6162 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6163 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6164 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6166 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6167 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6168 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6169 sat>, EVEX_CD8<16, CD8VH>;
6172 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6173 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6174 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6175 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6177 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6178 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6179 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6180 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6183 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6184 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6185 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6187 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6188 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6189 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6191 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6192 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6193 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6195 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6196 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6197 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6199 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6200 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6201 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6203 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6204 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6205 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6207 let Predicates = [HasAVX512, NoVLX] in {
6208 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6209 (v8i16 (EXTRACT_SUBREG
6210 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6211 VR256X:$src, sub_ymm)))), sub_xmm))>;
6212 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6213 (v4i32 (EXTRACT_SUBREG
6214 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6215 VR256X:$src, sub_ymm)))), sub_xmm))>;
6218 let Predicates = [HasBWI, NoVLX] in {
6219 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6220 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6221 VR256X:$src, sub_ymm))), sub_xmm))>;
6224 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6225 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6226 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6228 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6229 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6230 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6233 let mayLoad = 1 in {
6234 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6235 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6236 (DestInfo.VT (LdFrag addr:$src))>,
6241 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6242 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6243 let Predicates = [HasVLX, HasBWI] in {
6244 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6245 v16i8x_info, i64mem, LdFrag, OpNode>,
6246 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6248 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6249 v16i8x_info, i128mem, LdFrag, OpNode>,
6250 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6252 let Predicates = [HasBWI] in {
6253 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6254 v32i8x_info, i256mem, LdFrag, OpNode>,
6255 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6259 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6260 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6261 let Predicates = [HasVLX, HasAVX512] in {
6262 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6263 v16i8x_info, i32mem, LdFrag, OpNode>,
6264 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6266 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6267 v16i8x_info, i64mem, LdFrag, OpNode>,
6268 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6270 let Predicates = [HasAVX512] in {
6271 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6272 v16i8x_info, i128mem, LdFrag, OpNode>,
6273 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6277 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6278 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6279 let Predicates = [HasVLX, HasAVX512] in {
6280 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6281 v16i8x_info, i16mem, LdFrag, OpNode>,
6282 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6284 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6285 v16i8x_info, i32mem, LdFrag, OpNode>,
6286 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6288 let Predicates = [HasAVX512] in {
6289 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6290 v16i8x_info, i64mem, LdFrag, OpNode>,
6291 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6295 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6296 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6297 let Predicates = [HasVLX, HasAVX512] in {
6298 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6299 v8i16x_info, i64mem, LdFrag, OpNode>,
6300 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6302 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6303 v8i16x_info, i128mem, LdFrag, OpNode>,
6304 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6306 let Predicates = [HasAVX512] in {
6307 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6308 v16i16x_info, i256mem, LdFrag, OpNode>,
6309 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6313 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6314 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6315 let Predicates = [HasVLX, HasAVX512] in {
6316 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6317 v8i16x_info, i32mem, LdFrag, OpNode>,
6318 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6320 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6321 v8i16x_info, i64mem, LdFrag, OpNode>,
6322 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6324 let Predicates = [HasAVX512] in {
6325 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6326 v8i16x_info, i128mem, LdFrag, OpNode>,
6327 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6331 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6332 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6334 let Predicates = [HasVLX, HasAVX512] in {
6335 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6336 v4i32x_info, i64mem, LdFrag, OpNode>,
6337 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6339 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6340 v4i32x_info, i128mem, LdFrag, OpNode>,
6341 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6343 let Predicates = [HasAVX512] in {
6344 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6345 v8i32x_info, i256mem, LdFrag, OpNode>,
6346 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6350 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6351 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6352 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6353 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6354 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6355 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6358 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6359 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6360 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6361 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6362 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6363 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6365 //===----------------------------------------------------------------------===//
6366 // GATHER - SCATTER Operations
6368 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6369 X86MemOperand memop, PatFrag GatherNode> {
6370 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6371 ExeDomain = _.ExeDomain in
6372 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6373 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6374 !strconcat(OpcodeStr#_.Suffix,
6375 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6376 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6377 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6378 vectoraddr:$src2))]>, EVEX, EVEX_K,
6379 EVEX_CD8<_.EltSize, CD8VT1>;
6382 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6383 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6384 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6385 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6386 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6387 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6388 let Predicates = [HasVLX] in {
6389 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6390 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6391 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6392 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6393 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6394 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6395 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6396 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6400 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6401 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6402 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6403 mgatherv16i32>, EVEX_V512;
6404 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6405 mgatherv8i64>, EVEX_V512;
6406 let Predicates = [HasVLX] in {
6407 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6408 vy32xmem, mgatherv8i32>, EVEX_V256;
6409 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6410 vy64xmem, mgatherv4i64>, EVEX_V256;
6411 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6412 vx32xmem, mgatherv4i32>, EVEX_V128;
6413 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6414 vx64xmem, mgatherv2i64>, EVEX_V128;
6419 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6420 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6422 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6423 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6425 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6426 X86MemOperand memop, PatFrag ScatterNode> {
6428 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6430 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6431 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6432 !strconcat(OpcodeStr#_.Suffix,
6433 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6434 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6435 _.KRCWM:$mask, vectoraddr:$dst))]>,
6436 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6439 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6440 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6441 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6442 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6443 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6444 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6445 let Predicates = [HasVLX] in {
6446 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6447 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6448 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6449 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6450 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6451 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6452 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6453 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6457 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6458 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6459 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6460 mscatterv16i32>, EVEX_V512;
6461 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6462 mscatterv8i64>, EVEX_V512;
6463 let Predicates = [HasVLX] in {
6464 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6465 vy32xmem, mscatterv8i32>, EVEX_V256;
6466 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6467 vy64xmem, mscatterv4i64>, EVEX_V256;
6468 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6469 vx32xmem, mscatterv4i32>, EVEX_V128;
6470 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6471 vx64xmem, mscatterv2i64>, EVEX_V128;
6475 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6476 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6478 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6479 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6482 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6483 RegisterClass KRC, X86MemOperand memop> {
6484 let Predicates = [HasPFI], hasSideEffects = 1 in
6485 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6486 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6490 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6491 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6493 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6494 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6496 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6497 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6499 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6500 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6502 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6503 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6505 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6506 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6508 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6509 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6511 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6512 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6514 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6515 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6517 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6518 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6520 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6521 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6523 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6524 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6526 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6527 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6529 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6530 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6532 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6533 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6535 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6536 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6538 // Helper fragments to match sext vXi1 to vXiY.
6539 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6540 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6542 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6543 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6544 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6546 def : Pat<(store VK1:$src, addr:$dst),
6548 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6549 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6551 def : Pat<(store VK8:$src, addr:$dst),
6553 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6554 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6556 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6557 (truncstore node:$val, node:$ptr), [{
6558 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6561 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6562 (MOV8mr addr:$dst, GR8:$src)>;
6564 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6565 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6566 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6567 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6570 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6571 string OpcodeStr, Predicate prd> {
6572 let Predicates = [prd] in
6573 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6575 let Predicates = [prd, HasVLX] in {
6576 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6577 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6581 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6582 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6584 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6586 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6588 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6592 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6594 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6595 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6597 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6600 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6601 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6602 let Predicates = [prd] in
6603 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6606 let Predicates = [prd, HasVLX] in {
6607 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6609 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6614 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6615 avx512vl_i8_info, HasBWI>;
6616 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6617 avx512vl_i16_info, HasBWI>, VEX_W;
6618 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6619 avx512vl_i32_info, HasDQI>;
6620 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6621 avx512vl_i64_info, HasDQI>, VEX_W;
6623 //===----------------------------------------------------------------------===//
6624 // AVX-512 - COMPRESS and EXPAND
6627 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6629 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6630 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6631 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6633 let mayStore = 1 in {
6634 def mr : AVX5128I<opc, MRMDestMem, (outs),
6635 (ins _.MemOp:$dst, _.RC:$src),
6636 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6637 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6639 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6640 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6641 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6642 [(store (_.VT (vselect _.KRCWM:$mask,
6643 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6645 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6649 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6650 AVX512VLVectorVTInfo VTInfo> {
6651 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6653 let Predicates = [HasVLX] in {
6654 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6655 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6659 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6661 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6663 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6665 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6669 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6671 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6672 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6673 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6676 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6677 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6678 (_.VT (X86expand (_.VT (bitconvert
6679 (_.LdFrag addr:$src1)))))>,
6680 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6683 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6684 AVX512VLVectorVTInfo VTInfo> {
6685 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6687 let Predicates = [HasVLX] in {
6688 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6689 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6693 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6695 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6697 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6699 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6702 //handle instruction reg_vec1 = op(reg_vec,imm)
6704 // op(broadcast(eltVt),imm)
6705 //all instruction created with FROUND_CURRENT
6706 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6708 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6709 (ins _.RC:$src1, i32u8imm:$src2),
6710 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6711 (OpNode (_.VT _.RC:$src1),
6713 (i32 FROUND_CURRENT))>;
6714 let mayLoad = 1 in {
6715 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6716 (ins _.MemOp:$src1, i32u8imm:$src2),
6717 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6718 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6720 (i32 FROUND_CURRENT))>;
6721 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6722 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6723 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6724 "${src1}"##_.BroadcastStr##", $src2",
6725 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6727 (i32 FROUND_CURRENT))>, EVEX_B;
6731 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6732 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6733 SDNode OpNode, X86VectorVTInfo _>{
6734 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6735 (ins _.RC:$src1, i32u8imm:$src2),
6736 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6737 "$src1, {sae}, $src2",
6738 (OpNode (_.VT _.RC:$src1),
6740 (i32 FROUND_NO_EXC))>, EVEX_B;
6743 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6744 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6745 let Predicates = [prd] in {
6746 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6747 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6750 let Predicates = [prd, HasVLX] in {
6751 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6753 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6758 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6759 // op(reg_vec2,mem_vec,imm)
6760 // op(reg_vec2,broadcast(eltVt),imm)
6761 //all instruction created with FROUND_CURRENT
6762 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6764 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6765 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6766 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6767 (OpNode (_.VT _.RC:$src1),
6770 (i32 FROUND_CURRENT))>;
6771 let mayLoad = 1 in {
6772 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6773 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6774 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6775 (OpNode (_.VT _.RC:$src1),
6776 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6778 (i32 FROUND_CURRENT))>;
6779 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6780 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6781 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6782 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6783 (OpNode (_.VT _.RC:$src1),
6784 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6786 (i32 FROUND_CURRENT))>, EVEX_B;
6790 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6791 // op(reg_vec2,mem_vec,imm)
6792 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6793 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6795 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6796 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6797 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6798 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6799 (SrcInfo.VT SrcInfo.RC:$src2),
6802 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6803 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6804 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6805 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6806 (SrcInfo.VT (bitconvert
6807 (SrcInfo.LdFrag addr:$src2))),
6811 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6812 // op(reg_vec2,mem_vec,imm)
6813 // op(reg_vec2,broadcast(eltVt),imm)
6814 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6816 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6819 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6820 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6821 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6822 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6823 (OpNode (_.VT _.RC:$src1),
6824 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6825 (i8 imm:$src3))>, EVEX_B;
6828 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6829 // op(reg_vec2,mem_scalar,imm)
6830 //all instruction created with FROUND_CURRENT
6831 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6832 X86VectorVTInfo _> {
6834 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6835 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6836 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6837 (OpNode (_.VT _.RC:$src1),
6840 (i32 FROUND_CURRENT))>;
6841 let mayLoad = 1 in {
6842 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6843 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6844 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6845 (OpNode (_.VT _.RC:$src1),
6846 (_.VT (scalar_to_vector
6847 (_.ScalarLdFrag addr:$src2))),
6849 (i32 FROUND_CURRENT))>;
6851 let isAsmParserOnly = 1 in {
6852 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6853 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6854 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6860 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6861 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6862 SDNode OpNode, X86VectorVTInfo _>{
6863 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6864 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6865 OpcodeStr, "$src3,{sae}, $src2, $src1",
6866 "$src1, $src2,{sae}, $src3",
6867 (OpNode (_.VT _.RC:$src1),
6870 (i32 FROUND_NO_EXC))>, EVEX_B;
6872 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6873 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6874 SDNode OpNode, X86VectorVTInfo _> {
6875 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6876 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6877 OpcodeStr, "$src3,{sae}, $src2, $src1",
6878 "$src1, $src2,{sae}, $src3",
6879 (OpNode (_.VT _.RC:$src1),
6882 (i32 FROUND_NO_EXC))>, EVEX_B;
6885 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6886 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6887 let Predicates = [prd] in {
6888 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6889 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6893 let Predicates = [prd, HasVLX] in {
6894 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6896 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6901 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6902 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6903 let Predicates = [HasBWI] in {
6904 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6905 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6907 let Predicates = [HasBWI, HasVLX] in {
6908 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6909 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6910 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6911 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6915 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6916 bits<8> opc, SDNode OpNode>{
6917 let Predicates = [HasAVX512] in {
6918 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6920 let Predicates = [HasAVX512, HasVLX] in {
6921 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6922 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6926 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6927 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6928 let Predicates = [prd] in {
6929 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6930 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6934 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6935 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6936 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6937 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6938 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6939 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6942 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6943 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6944 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6945 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6946 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6947 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6949 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6950 0x55, X86VFixupimm, HasAVX512>,
6951 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6952 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6953 0x55, X86VFixupimm, HasAVX512>,
6954 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6956 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6957 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6958 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6959 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6960 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6961 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6964 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6965 0x50, X86VRange, HasDQI>,
6966 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6967 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6968 0x50, X86VRange, HasDQI>,
6969 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6971 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6972 0x51, X86VRange, HasDQI>,
6973 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6974 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6975 0x51, X86VRange, HasDQI>,
6976 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6978 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6979 0x57, X86Reduces, HasDQI>,
6980 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6981 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6982 0x57, X86Reduces, HasDQI>,
6983 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6985 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6986 0x27, X86GetMants, HasAVX512>,
6987 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6988 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6989 0x27, X86GetMants, HasAVX512>,
6990 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6992 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6993 bits<8> opc, SDNode OpNode = X86Shuf128>{
6994 let Predicates = [HasAVX512] in {
6995 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6998 let Predicates = [HasAVX512, HasVLX] in {
6999 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7002 let Predicates = [HasAVX512] in {
7003 def : Pat<(v16f32 (ffloor VR512:$src)),
7004 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7005 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7006 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7007 def : Pat<(v16f32 (fceil VR512:$src)),
7008 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7009 def : Pat<(v16f32 (frint VR512:$src)),
7010 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7011 def : Pat<(v16f32 (ftrunc VR512:$src)),
7012 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7014 def : Pat<(v8f64 (ffloor VR512:$src)),
7015 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7016 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7017 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7018 def : Pat<(v8f64 (fceil VR512:$src)),
7019 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7020 def : Pat<(v8f64 (frint VR512:$src)),
7021 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7022 def : Pat<(v8f64 (ftrunc VR512:$src)),
7023 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7026 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7027 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7028 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7029 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7030 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7031 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7032 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7033 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7035 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7036 AVX512VLVectorVTInfo VTInfo_FP>{
7037 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7038 AVX512AIi8Base, EVEX_4V;
7039 let isCodeGenOnly = 1 in {
7040 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
7041 AVX512AIi8Base, EVEX_4V;
7045 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
7046 EVEX_CD8<32, CD8VF>;
7047 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
7048 EVEX_CD8<64, CD8VF>, VEX_W;
7050 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7051 let Predicates = p in
7052 def NAME#_.VTName#rri:
7053 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7054 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7055 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7058 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7059 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7060 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7061 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7063 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7064 avx512vl_i8_info, avx512vl_i8_info>,
7065 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7066 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7067 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7068 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7069 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7072 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7073 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7075 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7076 X86VectorVTInfo _> {
7077 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7078 (ins _.RC:$src1), OpcodeStr,
7080 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7083 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7084 (ins _.MemOp:$src1), OpcodeStr,
7086 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7087 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7090 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7091 X86VectorVTInfo _> :
7092 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7094 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7095 (ins _.ScalarMemOp:$src1), OpcodeStr,
7096 "${src1}"##_.BroadcastStr,
7097 "${src1}"##_.BroadcastStr,
7098 (_.VT (OpNode (X86VBroadcast
7099 (_.ScalarLdFrag addr:$src1))))>,
7100 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7103 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7104 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7105 let Predicates = [prd] in
7106 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7108 let Predicates = [prd, HasVLX] in {
7109 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7111 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7116 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7117 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7118 let Predicates = [prd] in
7119 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7122 let Predicates = [prd, HasVLX] in {
7123 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7125 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7130 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7131 SDNode OpNode, Predicate prd> {
7132 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7134 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7138 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7139 SDNode OpNode, Predicate prd> {
7140 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7141 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7144 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7145 bits<8> opc_d, bits<8> opc_q,
7146 string OpcodeStr, SDNode OpNode> {
7147 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7149 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7153 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7156 (bc_v16i32 (v16i1sextv16i32)),
7157 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7158 (VPABSDZrr VR512:$src)>;
7160 (bc_v8i64 (v8i1sextv8i64)),
7161 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7162 (VPABSQZrr VR512:$src)>;
7164 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7166 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7167 let isCodeGenOnly = 1 in
7168 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7169 ctlz_zero_undef, prd>;
7172 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7173 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7175 //===---------------------------------------------------------------------===//
7176 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7177 //===---------------------------------------------------------------------===//
7178 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7179 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7181 let isCodeGenOnly = 1 in
7182 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7186 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7187 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7189 //===----------------------------------------------------------------------===//
7190 // AVX-512 - MOVDDUP
7191 //===----------------------------------------------------------------------===//
7193 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7194 X86VectorVTInfo _> {
7195 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7196 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7197 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7199 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7200 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7201 (_.VT (OpNode (_.VT (scalar_to_vector
7202 (_.ScalarLdFrag addr:$src)))))>,
7203 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7206 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7207 AVX512VLVectorVTInfo VTInfo> {
7209 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7211 let Predicates = [HasAVX512, HasVLX] in {
7212 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7214 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7219 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7220 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7221 avx512vl_f64_info>, XD, VEX_W;
7222 let isCodeGenOnly = 1 in
7223 defm NAME#_I: avx512_movddup_common<opc, OpcodeStr, OpNode,
7227 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7229 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7230 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7231 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7232 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7234 //===----------------------------------------------------------------------===//
7235 // AVX-512 - Unpack Instructions
7236 //===----------------------------------------------------------------------===//
7237 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7238 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7240 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7241 SSE_INTALU_ITINS_P, HasBWI>;
7242 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7243 SSE_INTALU_ITINS_P, HasBWI>;
7244 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7245 SSE_INTALU_ITINS_P, HasBWI>;
7246 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7247 SSE_INTALU_ITINS_P, HasBWI>;
7249 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7250 SSE_INTALU_ITINS_P, HasAVX512>;
7251 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7252 SSE_INTALU_ITINS_P, HasAVX512>;
7253 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7254 SSE_INTALU_ITINS_P, HasAVX512>;
7255 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7256 SSE_INTALU_ITINS_P, HasAVX512>;
7258 //===----------------------------------------------------------------------===//
7259 // AVX-512 - Extract & Insert Integer Instructions
7260 //===----------------------------------------------------------------------===//
7262 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7263 X86VectorVTInfo _> {
7265 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7266 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7267 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7268 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7271 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7274 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7275 let Predicates = [HasBWI] in {
7276 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7277 (ins _.RC:$src1, u8imm:$src2),
7278 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7279 [(set GR32orGR64:$dst,
7280 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7283 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7287 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7288 let Predicates = [HasBWI] in {
7289 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7290 (ins _.RC:$src1, u8imm:$src2),
7291 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7292 [(set GR32orGR64:$dst,
7293 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7296 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7297 (ins _.RC:$src1, u8imm:$src2),
7298 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7301 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7305 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7306 RegisterClass GRC> {
7307 let Predicates = [HasDQI] in {
7308 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7309 (ins _.RC:$src1, u8imm:$src2),
7310 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7312 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7316 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7317 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7318 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7319 [(store (extractelt (_.VT _.RC:$src1),
7320 imm:$src2),addr:$dst)]>,
7321 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7325 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7326 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7327 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7328 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7330 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7331 X86VectorVTInfo _, PatFrag LdFrag> {
7332 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7333 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7334 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7336 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7337 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7340 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7341 X86VectorVTInfo _, PatFrag LdFrag> {
7342 let Predicates = [HasBWI] in {
7343 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7344 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7345 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7347 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7349 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7353 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7354 X86VectorVTInfo _, RegisterClass GRC> {
7355 let Predicates = [HasDQI] in {
7356 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7357 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7358 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7360 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7363 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7364 _.ScalarLdFrag>, TAPD;
7368 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7370 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7372 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7373 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7374 //===----------------------------------------------------------------------===//
7375 // VSHUFPS - VSHUFPD Operations
7376 //===----------------------------------------------------------------------===//
7377 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7378 AVX512VLVectorVTInfo VTInfo_FP>{
7379 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7380 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7381 AVX512AIi8Base, EVEX_4V;
7382 let isCodeGenOnly = 1 in {
7383 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7384 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7385 AVX512AIi8Base, EVEX_4V;
7389 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7390 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7391 //===----------------------------------------------------------------------===//
7392 // AVX-512 - Byte shift Left/Right
7393 //===----------------------------------------------------------------------===//
7395 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7396 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7397 def rr : AVX512<opc, MRMr,
7398 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7400 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7402 def rm : AVX512<opc, MRMm,
7403 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7405 [(set _.RC:$dst,(_.VT (OpNode
7406 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7409 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7410 Format MRMm, string OpcodeStr, Predicate prd>{
7411 let Predicates = [prd] in
7412 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7413 OpcodeStr, v8i64_info>, EVEX_V512;
7414 let Predicates = [prd, HasVLX] in {
7415 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7416 OpcodeStr, v4i64x_info>, EVEX_V256;
7417 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7418 OpcodeStr, v2i64x_info>, EVEX_V128;
7421 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7422 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7423 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7424 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7427 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7428 string OpcodeStr, X86VectorVTInfo _dst,
7429 X86VectorVTInfo _src>{
7430 def rr : AVX512BI<opc, MRMSrcReg,
7431 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7433 [(set _dst.RC:$dst,(_dst.VT
7434 (OpNode (_src.VT _src.RC:$src1),
7435 (_src.VT _src.RC:$src2))))]>;
7437 def rm : AVX512BI<opc, MRMSrcMem,
7438 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7439 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7440 [(set _dst.RC:$dst,(_dst.VT
7441 (OpNode (_src.VT _src.RC:$src1),
7442 (_src.VT (bitconvert
7443 (_src.LdFrag addr:$src2))))))]>;
7446 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7447 string OpcodeStr, Predicate prd> {
7448 let Predicates = [prd] in
7449 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7450 v64i8_info>, EVEX_V512;
7451 let Predicates = [prd, HasVLX] in {
7452 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7453 v32i8x_info>, EVEX_V256;
7454 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7455 v16i8x_info>, EVEX_V128;
7459 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7462 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7464 let Constraints = "$src1 = $dst" in {
7465 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7466 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7467 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7468 (OpNode (_.VT _.RC:$src1),
7471 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7472 let mayLoad = 1 in {
7473 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7474 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7475 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7476 (OpNode (_.VT _.RC:$src1),
7478 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7480 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7481 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7482 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7483 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7484 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7485 (OpNode (_.VT _.RC:$src1),
7487 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7488 (i8 imm:$src4))>, EVEX_B,
7489 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7491 }// Constraints = "$src1 = $dst"
7494 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7495 let Predicates = [HasAVX512] in
7496 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7497 let Predicates = [HasAVX512, HasVLX] in {
7498 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7499 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7503 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7504 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;