1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let hasSideEffects = 0 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let hasSideEffects = 0 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let hasSideEffects = 0 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
622 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
623 (ins KRC:$mask, RC:$src1, x86memop:$src2),
624 !strconcat(OpcodeStr,
625 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
626 []>, EVEX_4V, EVEX_K;
629 let ExeDomain = SSEPackedSingle in
630 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
631 VK16WM, VR512, f512mem,
632 memopv16f32, vselect, v16f32>,
633 EVEX_CD8<32, CD8VF>, EVEX_V512;
634 let ExeDomain = SSEPackedDouble in
635 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
636 VK8WM, VR512, f512mem,
637 memopv8f64, vselect, v8f64>,
638 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
640 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
641 (v16f32 VR512:$src2), (i16 GR16:$mask))),
642 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
643 VR512:$src1, VR512:$src2)>;
645 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
646 (v8f64 VR512:$src2), (i8 GR8:$mask))),
647 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
648 VR512:$src1, VR512:$src2)>;
650 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
651 VK16WM, VR512, f512mem,
652 memopv16i32, vselect, v16i32>,
653 EVEX_CD8<32, CD8VF>, EVEX_V512;
655 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
656 VK8WM, VR512, f512mem,
657 memopv8i64, vselect, v8i64>,
658 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
660 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
661 (v16i32 VR512:$src2), (i16 GR16:$mask))),
662 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
663 VR512:$src1, VR512:$src2)>;
665 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
666 (v8i64 VR512:$src2), (i8 GR8:$mask))),
667 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
668 VR512:$src1, VR512:$src2)>;
670 let Predicates = [HasAVX512] in {
671 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
672 (v8f32 VR256X:$src2))),
674 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
675 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
678 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
679 (v8i32 VR256X:$src2))),
681 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
682 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
685 //===----------------------------------------------------------------------===//
686 // Compare Instructions
687 //===----------------------------------------------------------------------===//
689 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
690 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
691 Operand CC, SDNode OpNode, ValueType VT,
692 PatFrag ld_frag, string asm, string asm_alt> {
693 def rr : AVX512Ii8<0xC2, MRMSrcReg,
694 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
695 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
696 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
697 def rm : AVX512Ii8<0xC2, MRMSrcMem,
698 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
699 [(set VK1:$dst, (OpNode (VT RC:$src1),
700 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
701 let isAsmParserOnly = 1, hasSideEffects = 0 in {
702 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
703 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
704 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
705 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
706 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
707 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
711 let Predicates = [HasAVX512] in {
712 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
713 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
714 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
716 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
717 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
722 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
723 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
724 SDNode OpNode, ValueType vt> {
725 def rr : AVX512BI<opc, MRMSrcReg,
726 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
727 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
728 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
729 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
730 def rm : AVX512BI<opc, MRMSrcMem,
731 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
732 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
733 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
734 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
737 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
738 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
739 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
740 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
742 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
743 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
744 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
745 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
747 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
748 (COPY_TO_REGCLASS (VPCMPGTDZrr
749 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
752 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
753 (COPY_TO_REGCLASS (VPCMPEQDZrr
754 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
757 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
758 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
759 SDNode OpNode, ValueType vt, Operand CC, string asm,
761 def rri : AVX512AIi8<opc, MRMSrcReg,
762 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
763 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
764 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
765 def rmi : AVX512AIi8<opc, MRMSrcMem,
766 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
767 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
768 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
769 // Accept explicit immediate argument form instead of comparison code.
770 let isAsmParserOnly = 1, hasSideEffects = 0 in {
771 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
772 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
773 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
774 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
775 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
776 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
780 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
781 X86cmpm, v16i32, AVXCC,
782 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
783 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
784 EVEX_V512, EVEX_CD8<32, CD8VF>;
785 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
786 X86cmpmu, v16i32, AVXCC,
787 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
788 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
789 EVEX_V512, EVEX_CD8<32, CD8VF>;
791 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
792 X86cmpm, v8i64, AVXCC,
793 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
794 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
795 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
796 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
797 X86cmpmu, v8i64, AVXCC,
798 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
802 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
803 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
804 X86MemOperand x86memop, ValueType vt,
805 string suffix, Domain d> {
806 def rri : AVX512PIi8<0xC2, MRMSrcReg,
807 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
808 !strconcat("vcmp${cc}", suffix,
809 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
812 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc, i32imm:$sae),
813 !strconcat("vcmp${cc}", suffix,
814 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
816 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
817 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
818 !strconcat("vcmp", suffix,
819 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
821 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
823 // Accept explicit immediate argument form instead of comparison code.
824 let isAsmParserOnly = 1, hasSideEffects = 0 in {
825 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
826 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
827 !strconcat("vcmp", suffix,
828 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
829 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
830 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
831 !strconcat("vcmp", suffix,
832 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
836 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
837 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
838 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
839 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
842 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VCMPPSZrri
844 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
852 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
853 (COPY_TO_REGCLASS (VPCMPUDZrri
854 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
855 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
858 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
859 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
861 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
862 (I8Imm imm:$cc), (i32 0)), GR16)>;
864 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
865 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
867 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
868 (I8Imm imm:$cc), (i32 0)), GR8)>;
870 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
871 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
873 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
874 (I8Imm imm:$cc)), GR16)>;
876 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
877 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
879 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
880 (I8Imm imm:$cc)), GR8)>;
882 // Mask register copy, including
883 // - copy between mask registers
884 // - load/store mask registers
885 // - copy from GPR to mask register and vice versa
887 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
888 string OpcodeStr, RegisterClass KRC,
889 ValueType vt, X86MemOperand x86memop> {
890 let hasSideEffects = 0 in {
891 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
892 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
894 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
896 [(set KRC:$dst, (vt (load addr:$src)))]>;
898 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
903 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
905 RegisterClass KRC, RegisterClass GRC> {
906 let hasSideEffects = 0 in {
907 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
908 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
909 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
910 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
914 let Predicates = [HasAVX512] in {
915 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
917 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
921 let Predicates = [HasAVX512] in {
922 // GR16 from/to 16-bit mask
923 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
924 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
925 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
926 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
928 // Store kreg in memory
929 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
930 (KMOVWmk addr:$dst, VK16:$src)>;
932 def : Pat<(store VK8:$src, addr:$dst),
933 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
935 def : Pat<(i1 (load addr:$src)),
936 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
938 def : Pat<(v8i1 (load addr:$src)),
939 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
941 def : Pat<(i1 (trunc (i32 GR32:$src))),
942 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
944 def : Pat<(i1 (trunc (i8 GR8:$src))),
946 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
948 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
949 def : Pat<(i8 (zext VK1:$src)),
951 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
953 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
954 let Predicates = [HasAVX512] in {
955 // GR from/to 8-bit mask without native support
956 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
958 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
960 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
962 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
965 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
966 (COPY_TO_REGCLASS VK16:$src, VK1)>;
967 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
968 (COPY_TO_REGCLASS VK8:$src, VK1)>;
972 // Mask unary operation
974 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
975 RegisterClass KRC, SDPatternOperator OpNode> {
976 let Predicates = [HasAVX512] in
977 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
978 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
979 [(set KRC:$dst, (OpNode KRC:$src))]>;
982 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
983 SDPatternOperator OpNode> {
984 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
988 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
990 multiclass avx512_mask_unop_int<string IntName, string InstName> {
991 let Predicates = [HasAVX512] in
992 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
994 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
995 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
997 defm : avx512_mask_unop_int<"knot", "KNOT">;
999 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1000 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1001 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1003 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1004 def : Pat<(not VK8:$src),
1006 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1008 // Mask binary operation
1009 // - KAND, KANDN, KOR, KXNOR, KXOR
1010 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1011 RegisterClass KRC, SDPatternOperator OpNode> {
1012 let Predicates = [HasAVX512] in
1013 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1014 !strconcat(OpcodeStr,
1015 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1016 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1019 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1020 SDPatternOperator OpNode> {
1021 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1025 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1026 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1028 let isCommutable = 1 in {
1029 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1030 let isCommutable = 0 in
1031 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1032 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1033 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1034 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1037 def : Pat<(xor VK1:$src1, VK1:$src2),
1038 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1039 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1041 def : Pat<(or VK1:$src1, VK1:$src2),
1042 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1043 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1045 def : Pat<(not VK1:$src),
1046 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1047 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1048 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1050 def : Pat<(and VK1:$src1, VK1:$src2),
1051 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1052 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1054 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1055 let Predicates = [HasAVX512] in
1056 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1057 (i16 GR16:$src1), (i16 GR16:$src2)),
1058 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1059 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1060 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1063 defm : avx512_mask_binop_int<"kand", "KAND">;
1064 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1065 defm : avx512_mask_binop_int<"kor", "KOR">;
1066 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1067 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1069 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1070 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1071 let Predicates = [HasAVX512] in
1072 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1074 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1075 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1078 defm : avx512_binop_pat<and, KANDWrr>;
1079 defm : avx512_binop_pat<andn, KANDNWrr>;
1080 defm : avx512_binop_pat<or, KORWrr>;
1081 defm : avx512_binop_pat<xnor, KXNORWrr>;
1082 defm : avx512_binop_pat<xor, KXORWrr>;
1085 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1086 RegisterClass KRC> {
1087 let Predicates = [HasAVX512] in
1088 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1089 !strconcat(OpcodeStr,
1090 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1093 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1094 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1095 VEX_4V, VEX_L, OpSize, TB;
1098 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1099 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1100 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1101 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1104 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1105 let Predicates = [HasAVX512] in
1106 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1107 (i16 GR16:$src1), (i16 GR16:$src2)),
1108 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1109 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1110 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1112 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1115 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1117 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1118 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1119 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1120 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1123 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1124 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1128 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1130 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1131 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1132 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1135 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1137 let Predicates = [HasAVX512] in
1138 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1139 !strconcat(OpcodeStr,
1140 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1141 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1144 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1146 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1147 VEX, OpSize, TA, VEX_W;
1150 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1151 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1153 // Mask setting all 0s or 1s
1154 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1155 let Predicates = [HasAVX512] in
1156 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1157 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1158 [(set KRC:$dst, (VT Val))]>;
1161 multiclass avx512_mask_setop_w<PatFrag Val> {
1162 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1163 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1166 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1167 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1169 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1170 let Predicates = [HasAVX512] in {
1171 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1172 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1174 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1175 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1177 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1178 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1180 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1181 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1183 //===----------------------------------------------------------------------===//
1184 // AVX-512 - Aligned and unaligned load and store
1187 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1188 X86MemOperand x86memop, PatFrag ld_frag,
1189 string asm, Domain d> {
1190 let hasSideEffects = 0 in
1191 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1192 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1194 let canFoldAsLoad = 1 in
1195 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1196 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1197 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1198 let Constraints = "$src1 = $dst" in {
1199 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1200 (ins RC:$src1, KRC:$mask, RC:$src2),
1202 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1204 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1205 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1207 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1208 [], d>, EVEX, EVEX_K;
1212 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1213 "vmovaps", SSEPackedSingle>,
1214 EVEX_V512, EVEX_CD8<32, CD8VF>;
1215 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1216 "vmovapd", SSEPackedDouble>,
1217 OpSize, EVEX_V512, VEX_W,
1218 EVEX_CD8<64, CD8VF>;
1219 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1220 "vmovups", SSEPackedSingle>,
1221 EVEX_V512, EVEX_CD8<32, CD8VF>;
1222 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1223 "vmovupd", SSEPackedDouble>,
1224 OpSize, EVEX_V512, VEX_W,
1225 EVEX_CD8<64, CD8VF>;
1226 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1227 "vmovaps\t{$src, $dst|$dst, $src}",
1228 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1229 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1230 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1231 "vmovapd\t{$src, $dst|$dst, $src}",
1232 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1233 SSEPackedDouble>, EVEX, EVEX_V512,
1234 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1235 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1236 "vmovups\t{$src, $dst|$dst, $src}",
1237 [(store (v16f32 VR512:$src), addr:$dst)],
1238 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1239 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1240 "vmovupd\t{$src, $dst|$dst, $src}",
1241 [(store (v8f64 VR512:$src), addr:$dst)],
1242 SSEPackedDouble>, EVEX, EVEX_V512,
1243 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1245 let hasSideEffects = 0 in {
1246 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1248 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1250 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1252 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1253 EVEX, EVEX_V512, VEX_W;
1254 let mayStore = 1 in {
1255 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1256 (ins i512mem:$dst, VR512:$src),
1257 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1258 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1259 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1260 (ins i512mem:$dst, VR512:$src),
1261 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1262 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1264 let mayLoad = 1 in {
1265 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1267 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1268 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1269 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1271 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1272 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1276 // 512-bit aligned load/store
1277 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1278 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1280 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1281 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1282 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1283 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1285 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1286 RegisterClass RC, RegisterClass KRC,
1287 PatFrag ld_frag, X86MemOperand x86memop> {
1288 let hasSideEffects = 0 in
1289 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1290 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1291 let canFoldAsLoad = 1 in
1292 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1293 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1294 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1296 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1297 (ins x86memop:$dst, VR512:$src),
1298 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1299 let Constraints = "$src1 = $dst" in {
1300 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1301 (ins RC:$src1, KRC:$mask, RC:$src2),
1303 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1305 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1306 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1308 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1313 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1314 memopv16i32, i512mem>,
1315 EVEX_V512, EVEX_CD8<32, CD8VF>;
1316 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1317 memopv8i64, i512mem>,
1318 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1320 // 512-bit unaligned load/store
1321 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1322 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1324 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1325 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1326 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1327 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1329 let AddedComplexity = 20 in {
1330 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1331 (v16f32 VR512:$src2))),
1332 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1333 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1334 (v8f64 VR512:$src2))),
1335 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1336 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1337 (v16i32 VR512:$src2))),
1338 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1339 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1340 (v8i64 VR512:$src2))),
1341 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1343 // Move Int Doubleword to Packed Double Int
1345 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1346 "vmovd\t{$src, $dst|$dst, $src}",
1348 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1350 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1351 "vmovd\t{$src, $dst|$dst, $src}",
1353 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1354 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1355 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1356 "vmovq\t{$src, $dst|$dst, $src}",
1358 (v2i64 (scalar_to_vector GR64:$src)))],
1359 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1360 let isCodeGenOnly = 1 in {
1361 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1362 "vmovq\t{$src, $dst|$dst, $src}",
1363 [(set FR64:$dst, (bitconvert GR64:$src))],
1364 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1365 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1366 "vmovq\t{$src, $dst|$dst, $src}",
1367 [(set GR64:$dst, (bitconvert FR64:$src))],
1368 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1370 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1371 "vmovq\t{$src, $dst|$dst, $src}",
1372 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1373 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1374 EVEX_CD8<64, CD8VT1>;
1376 // Move Int Doubleword to Single Scalar
1378 let isCodeGenOnly = 1 in {
1379 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1380 "vmovd\t{$src, $dst|$dst, $src}",
1381 [(set FR32X:$dst, (bitconvert GR32:$src))],
1382 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1384 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1385 "vmovd\t{$src, $dst|$dst, $src}",
1386 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1387 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1390 // Move Packed Doubleword Int to Packed Double Int
1392 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1393 "vmovd\t{$src, $dst|$dst, $src}",
1394 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1395 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1397 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1398 (ins i32mem:$dst, VR128X:$src),
1399 "vmovd\t{$src, $dst|$dst, $src}",
1400 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1401 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1402 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1404 // Move Packed Doubleword Int first element to Doubleword Int
1406 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1407 "vmovq\t{$src, $dst|$dst, $src}",
1408 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1410 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1411 Requires<[HasAVX512, In64BitMode]>;
1413 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1414 (ins i64mem:$dst, VR128X:$src),
1415 "vmovq\t{$src, $dst|$dst, $src}",
1416 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1417 addr:$dst)], IIC_SSE_MOVDQ>,
1418 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1419 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1421 // Move Scalar Single to Double Int
1423 let isCodeGenOnly = 1 in {
1424 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1426 "vmovd\t{$src, $dst|$dst, $src}",
1427 [(set GR32:$dst, (bitconvert FR32X:$src))],
1428 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1429 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1430 (ins i32mem:$dst, FR32X:$src),
1431 "vmovd\t{$src, $dst|$dst, $src}",
1432 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1433 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1436 // Move Quadword Int to Packed Quadword Int
1438 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1440 "vmovq\t{$src, $dst|$dst, $src}",
1442 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1443 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1445 //===----------------------------------------------------------------------===//
1446 // AVX-512 MOVSS, MOVSD
1447 //===----------------------------------------------------------------------===//
1449 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1450 SDNode OpNode, ValueType vt,
1451 X86MemOperand x86memop, PatFrag mem_pat> {
1452 let hasSideEffects = 0 in {
1453 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1454 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1455 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1456 (scalar_to_vector RC:$src2))))],
1457 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1458 let Constraints = "$src1 = $dst" in
1459 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1460 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1462 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1463 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1464 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1465 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1466 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1468 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1469 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1470 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1472 } //hasSideEffects = 0
1475 let ExeDomain = SSEPackedSingle in
1476 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1477 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1479 let ExeDomain = SSEPackedDouble in
1480 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1481 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1483 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1484 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1485 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1487 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1488 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1489 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1491 // For the disassembler
1492 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1493 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1494 (ins VR128X:$src1, FR32X:$src2),
1495 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1497 XS, EVEX_4V, VEX_LIG;
1498 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1499 (ins VR128X:$src1, FR64X:$src2),
1500 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1502 XD, EVEX_4V, VEX_LIG, VEX_W;
1505 let Predicates = [HasAVX512] in {
1506 let AddedComplexity = 15 in {
1507 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1508 // MOVS{S,D} to the lower bits.
1509 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1510 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1511 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1512 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1513 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1514 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1515 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1516 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1518 // Move low f32 and clear high bits.
1519 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1520 (SUBREG_TO_REG (i32 0),
1521 (VMOVSSZrr (v4f32 (V_SET0)),
1522 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1523 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1524 (SUBREG_TO_REG (i32 0),
1525 (VMOVSSZrr (v4i32 (V_SET0)),
1526 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1529 let AddedComplexity = 20 in {
1530 // MOVSSrm zeros the high parts of the register; represent this
1531 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1532 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1533 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1534 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1535 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1536 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1537 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1539 // MOVSDrm zeros the high parts of the register; represent this
1540 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1541 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1542 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1543 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1544 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1545 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1546 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1547 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1548 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1549 def : Pat<(v2f64 (X86vzload addr:$src)),
1550 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1552 // Represent the same patterns above but in the form they appear for
1554 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1555 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1556 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1557 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1558 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1559 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1560 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1561 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1562 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1564 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1565 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1566 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1567 FR32X:$src)), sub_xmm)>;
1568 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1569 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1570 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1571 FR64X:$src)), sub_xmm)>;
1572 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1573 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1574 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1576 // Move low f64 and clear high bits.
1577 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1578 (SUBREG_TO_REG (i32 0),
1579 (VMOVSDZrr (v2f64 (V_SET0)),
1580 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1582 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1583 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1584 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1586 // Extract and store.
1587 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1589 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1590 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1592 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1594 // Shuffle with VMOVSS
1595 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1596 (VMOVSSZrr (v4i32 VR128X:$src1),
1597 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1598 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1599 (VMOVSSZrr (v4f32 VR128X:$src1),
1600 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1603 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1604 (SUBREG_TO_REG (i32 0),
1605 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1606 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1608 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1609 (SUBREG_TO_REG (i32 0),
1610 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1611 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1614 // Shuffle with VMOVSD
1615 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1616 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1617 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1618 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1619 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1620 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1621 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1622 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1625 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1626 (SUBREG_TO_REG (i32 0),
1627 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1628 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1630 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1631 (SUBREG_TO_REG (i32 0),
1632 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1633 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1636 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1637 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1638 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1639 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1640 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1641 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1642 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1643 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1646 let AddedComplexity = 15 in
1647 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1649 "vmovq\t{$src, $dst|$dst, $src}",
1650 [(set VR128X:$dst, (v2i64 (X86vzmovl
1651 (v2i64 VR128X:$src))))],
1652 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1654 let AddedComplexity = 20 in
1655 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1657 "vmovq\t{$src, $dst|$dst, $src}",
1658 [(set VR128X:$dst, (v2i64 (X86vzmovl
1659 (loadv2i64 addr:$src))))],
1660 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1661 EVEX_CD8<8, CD8VT8>;
1663 let Predicates = [HasAVX512] in {
1664 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1665 let AddedComplexity = 20 in {
1666 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1667 (VMOVDI2PDIZrm addr:$src)>;
1668 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1669 (VMOV64toPQIZrr GR64:$src)>;
1670 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1671 (VMOVDI2PDIZrr GR32:$src)>;
1673 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1674 (VMOVDI2PDIZrm addr:$src)>;
1675 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1676 (VMOVDI2PDIZrm addr:$src)>;
1677 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1678 (VMOVZPQILo2PQIZrm addr:$src)>;
1679 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1680 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1681 def : Pat<(v2i64 (X86vzload addr:$src)),
1682 (VMOVZPQILo2PQIZrm addr:$src)>;
1685 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1686 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1687 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1688 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1689 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1690 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1691 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1694 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1695 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1697 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1698 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1700 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1701 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1703 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1704 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1706 //===----------------------------------------------------------------------===//
1707 // AVX-512 - Integer arithmetic
1709 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1710 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1711 X86MemOperand x86memop, PatFrag scalar_mfrag,
1712 X86MemOperand x86scalar_mop, string BrdcstStr,
1713 OpndItins itins, bit IsCommutable = 0> {
1714 let isCommutable = IsCommutable in
1715 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1716 (ins RC:$src1, RC:$src2),
1717 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1718 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1720 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1721 (ins RC:$src1, x86memop:$src2),
1722 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1723 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1725 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1726 (ins RC:$src1, x86scalar_mop:$src2),
1727 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1728 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1729 [(set RC:$dst, (OpNode RC:$src1,
1730 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1731 itins.rm>, EVEX_4V, EVEX_B;
1733 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1734 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1735 PatFrag memop_frag, X86MemOperand x86memop,
1737 bit IsCommutable = 0> {
1738 let isCommutable = IsCommutable in
1739 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1740 (ins RC:$src1, RC:$src2),
1741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1742 []>, EVEX_4V, VEX_W;
1743 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1744 (ins RC:$src1, x86memop:$src2),
1745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1746 []>, EVEX_4V, VEX_W;
1749 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1750 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1751 EVEX_V512, EVEX_CD8<32, CD8VF>;
1753 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1754 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1755 EVEX_V512, EVEX_CD8<32, CD8VF>;
1757 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1758 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1759 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1761 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1762 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1763 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1765 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1766 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1767 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1769 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1770 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1771 EVEX_V512, EVEX_CD8<64, CD8VF>;
1773 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1774 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1775 EVEX_CD8<64, CD8VF>;
1777 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1778 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1780 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1781 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1782 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1783 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1784 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1785 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1787 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1788 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1789 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1790 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1791 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1792 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1794 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1795 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1796 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1797 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1798 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1799 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1801 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1802 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1803 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1804 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1805 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1806 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1808 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1809 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1810 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1811 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1812 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1813 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1815 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1816 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1817 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1818 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1819 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1820 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1821 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1822 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1823 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1824 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1825 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1826 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1827 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1828 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1829 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1830 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1831 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1832 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1833 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1834 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1835 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1836 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1837 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1838 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1839 //===----------------------------------------------------------------------===//
1840 // AVX-512 - Unpack Instructions
1841 //===----------------------------------------------------------------------===//
1843 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1844 PatFrag mem_frag, RegisterClass RC,
1845 X86MemOperand x86memop, string asm,
1847 def rr : AVX512PI<opc, MRMSrcReg,
1848 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1850 (vt (OpNode RC:$src1, RC:$src2)))],
1852 def rm : AVX512PI<opc, MRMSrcMem,
1853 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1855 (vt (OpNode RC:$src1,
1856 (bitconvert (mem_frag addr:$src2)))))],
1860 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1861 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1862 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1863 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1864 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1865 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1866 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1867 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1868 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1869 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1870 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1871 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1873 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1874 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1875 X86MemOperand x86memop> {
1876 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1877 (ins RC:$src1, RC:$src2),
1878 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1879 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1880 IIC_SSE_UNPCK>, EVEX_4V;
1881 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1882 (ins RC:$src1, x86memop:$src2),
1883 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1884 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1885 (bitconvert (memop_frag addr:$src2)))))],
1886 IIC_SSE_UNPCK>, EVEX_4V;
1888 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1889 VR512, memopv16i32, i512mem>, EVEX_V512,
1890 EVEX_CD8<32, CD8VF>;
1891 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1892 VR512, memopv8i64, i512mem>, EVEX_V512,
1893 VEX_W, EVEX_CD8<64, CD8VF>;
1894 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1895 VR512, memopv16i32, i512mem>, EVEX_V512,
1896 EVEX_CD8<32, CD8VF>;
1897 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1898 VR512, memopv8i64, i512mem>, EVEX_V512,
1899 VEX_W, EVEX_CD8<64, CD8VF>;
1900 //===----------------------------------------------------------------------===//
1904 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1905 SDNode OpNode, PatFrag mem_frag,
1906 X86MemOperand x86memop, ValueType OpVT> {
1907 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1908 (ins RC:$src1, i8imm:$src2),
1909 !strconcat(OpcodeStr,
1910 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1912 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1914 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1915 (ins x86memop:$src1, i8imm:$src2),
1916 !strconcat(OpcodeStr,
1917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1919 (OpVT (OpNode (mem_frag addr:$src1),
1920 (i8 imm:$src2))))]>, EVEX;
1923 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1924 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1926 let ExeDomain = SSEPackedSingle in
1927 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1928 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1929 EVEX_CD8<32, CD8VF>;
1930 let ExeDomain = SSEPackedDouble in
1931 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1932 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1933 VEX_W, EVEX_CD8<32, CD8VF>;
1935 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1937 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1940 //===----------------------------------------------------------------------===//
1941 // AVX-512 Logical Instructions
1942 //===----------------------------------------------------------------------===//
1944 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1945 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1946 EVEX_V512, EVEX_CD8<32, CD8VF>;
1947 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1948 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1949 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1950 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1951 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1952 EVEX_V512, EVEX_CD8<32, CD8VF>;
1953 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1954 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1955 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1956 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1957 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1958 EVEX_V512, EVEX_CD8<32, CD8VF>;
1959 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1960 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1961 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1962 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1963 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1964 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1965 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1966 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1967 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1969 //===----------------------------------------------------------------------===//
1970 // AVX-512 FP arithmetic
1971 //===----------------------------------------------------------------------===//
1973 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1975 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1976 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1977 EVEX_CD8<32, CD8VT1>;
1978 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1979 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1980 EVEX_CD8<64, CD8VT1>;
1983 let isCommutable = 1 in {
1984 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1985 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1986 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1987 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1989 let isCommutable = 0 in {
1990 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1991 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1994 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1995 RegisterClass RC, ValueType vt,
1996 X86MemOperand x86memop, PatFrag mem_frag,
1997 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1999 Domain d, OpndItins itins, bit commutable> {
2000 let isCommutable = commutable in
2001 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2003 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2005 let mayLoad = 1 in {
2006 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2008 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2009 itins.rm, d>, EVEX_4V, TB;
2010 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2011 (ins RC:$src1, x86scalar_mop:$src2),
2012 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2013 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2014 [(set RC:$dst, (OpNode RC:$src1,
2015 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2016 itins.rm, d>, EVEX_4V, EVEX_B, TB;
2020 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2021 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2022 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2024 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2025 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2026 SSE_ALU_ITINS_P.d, 1>,
2027 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2029 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2030 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2031 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2032 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2033 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2034 SSE_ALU_ITINS_P.d, 1>,
2035 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2037 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2038 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2039 SSE_ALU_ITINS_P.s, 1>,
2040 EVEX_V512, EVEX_CD8<32, CD8VF>;
2041 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2042 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2043 SSE_ALU_ITINS_P.s, 1>,
2044 EVEX_V512, EVEX_CD8<32, CD8VF>;
2046 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2047 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2048 SSE_ALU_ITINS_P.d, 1>,
2049 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2050 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2051 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2052 SSE_ALU_ITINS_P.d, 1>,
2053 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2055 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2056 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2057 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2058 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2059 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2060 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2062 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2063 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2064 SSE_ALU_ITINS_P.d, 0>,
2065 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2066 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2067 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2068 SSE_ALU_ITINS_P.d, 0>,
2069 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2071 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2072 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2073 (i16 -1), FROUND_CURRENT)),
2074 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2076 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2077 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2078 (i8 -1), FROUND_CURRENT)),
2079 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2081 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2082 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2083 (i16 -1), FROUND_CURRENT)),
2084 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2086 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2087 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2088 (i8 -1), FROUND_CURRENT)),
2089 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2090 //===----------------------------------------------------------------------===//
2091 // AVX-512 VPTESTM instructions
2092 //===----------------------------------------------------------------------===//
2094 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2095 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2096 SDNode OpNode, ValueType vt> {
2097 def rr : AVX5128I<opc, MRMSrcReg,
2098 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2099 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2100 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2101 def rm : AVX5128I<opc, MRMSrcMem,
2102 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2104 [(set KRC:$dst, (OpNode (vt RC:$src1),
2105 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2108 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2109 memopv16i32, X86testm, v16i32>, EVEX_V512,
2110 EVEX_CD8<32, CD8VF>;
2111 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2112 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2113 EVEX_CD8<64, CD8VF>;
2115 //===----------------------------------------------------------------------===//
2116 // AVX-512 Shift instructions
2117 //===----------------------------------------------------------------------===//
2118 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2119 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2120 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2121 RegisterClass KRC> {
2122 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2123 (ins RC:$src1, i8imm:$src2),
2124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2125 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2126 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2127 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2128 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2129 !strconcat(OpcodeStr,
2130 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2131 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2132 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2133 (ins x86memop:$src1, i8imm:$src2),
2134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2135 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2136 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2137 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2138 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2139 !strconcat(OpcodeStr,
2140 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2141 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2144 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2145 RegisterClass RC, ValueType vt, ValueType SrcVT,
2146 PatFrag bc_frag, RegisterClass KRC> {
2147 // src2 is always 128-bit
2148 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2149 (ins RC:$src1, VR128X:$src2),
2150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2151 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2152 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2153 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2154 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2155 !strconcat(OpcodeStr,
2156 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2157 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2158 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2159 (ins RC:$src1, i128mem:$src2),
2160 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2161 [(set RC:$dst, (vt (OpNode RC:$src1,
2162 (bc_frag (memopv2i64 addr:$src2)))))],
2163 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2164 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2165 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2166 !strconcat(OpcodeStr,
2167 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2168 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2171 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2172 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2173 EVEX_V512, EVEX_CD8<32, CD8VF>;
2174 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2175 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2176 EVEX_CD8<32, CD8VQ>;
2178 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2179 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2180 EVEX_CD8<64, CD8VF>, VEX_W;
2181 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2182 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2183 EVEX_CD8<64, CD8VQ>, VEX_W;
2185 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2186 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2187 EVEX_CD8<32, CD8VF>;
2188 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2189 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2190 EVEX_CD8<32, CD8VQ>;
2192 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2193 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2194 EVEX_CD8<64, CD8VF>, VEX_W;
2195 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2196 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2197 EVEX_CD8<64, CD8VQ>, VEX_W;
2199 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2200 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2201 EVEX_V512, EVEX_CD8<32, CD8VF>;
2202 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2203 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2204 EVEX_CD8<32, CD8VQ>;
2206 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2207 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2208 EVEX_CD8<64, CD8VF>, VEX_W;
2209 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2210 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2211 EVEX_CD8<64, CD8VQ>, VEX_W;
2213 //===-------------------------------------------------------------------===//
2214 // Variable Bit Shifts
2215 //===-------------------------------------------------------------------===//
2216 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2217 RegisterClass RC, ValueType vt,
2218 X86MemOperand x86memop, PatFrag mem_frag> {
2219 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2220 (ins RC:$src1, RC:$src2),
2221 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2223 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2225 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2226 (ins RC:$src1, x86memop:$src2),
2227 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2229 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2233 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2234 i512mem, memopv16i32>, EVEX_V512,
2235 EVEX_CD8<32, CD8VF>;
2236 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2237 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2238 EVEX_CD8<64, CD8VF>;
2239 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2240 i512mem, memopv16i32>, EVEX_V512,
2241 EVEX_CD8<32, CD8VF>;
2242 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2243 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2244 EVEX_CD8<64, CD8VF>;
2245 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2246 i512mem, memopv16i32>, EVEX_V512,
2247 EVEX_CD8<32, CD8VF>;
2248 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2249 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2250 EVEX_CD8<64, CD8VF>;
2252 //===----------------------------------------------------------------------===//
2253 // AVX-512 - MOVDDUP
2254 //===----------------------------------------------------------------------===//
2256 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2257 X86MemOperand x86memop, PatFrag memop_frag> {
2258 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2259 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2260 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2261 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2262 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2264 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2267 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2268 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2269 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2270 (VMOVDDUPZrm addr:$src)>;
2272 //===---------------------------------------------------------------------===//
2273 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2274 //===---------------------------------------------------------------------===//
2275 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2276 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2277 X86MemOperand x86memop> {
2278 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2279 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2280 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2282 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2283 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2284 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2287 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2288 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2289 EVEX_CD8<32, CD8VF>;
2290 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2291 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2292 EVEX_CD8<32, CD8VF>;
2294 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2295 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2296 (VMOVSHDUPZrm addr:$src)>;
2297 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2298 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2299 (VMOVSLDUPZrm addr:$src)>;
2301 //===----------------------------------------------------------------------===//
2302 // Move Low to High and High to Low packed FP Instructions
2303 //===----------------------------------------------------------------------===//
2304 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2305 (ins VR128X:$src1, VR128X:$src2),
2306 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2307 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2308 IIC_SSE_MOV_LH>, EVEX_4V;
2309 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2310 (ins VR128X:$src1, VR128X:$src2),
2311 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2312 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2313 IIC_SSE_MOV_LH>, EVEX_4V;
2315 let Predicates = [HasAVX512] in {
2317 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2318 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2319 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2320 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2323 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2324 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2327 //===----------------------------------------------------------------------===//
2328 // FMA - Fused Multiply Operations
2330 let Constraints = "$src1 = $dst" in {
2331 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2332 RegisterClass RC, X86MemOperand x86memop,
2333 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2334 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2335 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2336 (ins RC:$src1, RC:$src2, RC:$src3),
2337 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2338 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2341 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2342 (ins RC:$src1, RC:$src2, x86memop:$src3),
2343 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2344 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2345 (mem_frag addr:$src3))))]>;
2346 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2347 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2348 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2349 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2350 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2351 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2353 } // Constraints = "$src1 = $dst"
2355 let ExeDomain = SSEPackedSingle in {
2356 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2357 memopv16f32, f32mem, loadf32, "{1to16}",
2358 X86Fmadd, v16f32>, EVEX_V512,
2359 EVEX_CD8<32, CD8VF>;
2360 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2361 memopv16f32, f32mem, loadf32, "{1to16}",
2362 X86Fmsub, v16f32>, EVEX_V512,
2363 EVEX_CD8<32, CD8VF>;
2364 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2365 memopv16f32, f32mem, loadf32, "{1to16}",
2366 X86Fmaddsub, v16f32>,
2367 EVEX_V512, EVEX_CD8<32, CD8VF>;
2368 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2369 memopv16f32, f32mem, loadf32, "{1to16}",
2370 X86Fmsubadd, v16f32>,
2371 EVEX_V512, EVEX_CD8<32, CD8VF>;
2372 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2373 memopv16f32, f32mem, loadf32, "{1to16}",
2374 X86Fnmadd, v16f32>, EVEX_V512,
2375 EVEX_CD8<32, CD8VF>;
2376 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2377 memopv16f32, f32mem, loadf32, "{1to16}",
2378 X86Fnmsub, v16f32>, EVEX_V512,
2379 EVEX_CD8<32, CD8VF>;
2381 let ExeDomain = SSEPackedDouble in {
2382 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2383 memopv8f64, f64mem, loadf64, "{1to8}",
2384 X86Fmadd, v8f64>, EVEX_V512,
2385 VEX_W, EVEX_CD8<64, CD8VF>;
2386 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2387 memopv8f64, f64mem, loadf64, "{1to8}",
2388 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2389 EVEX_CD8<64, CD8VF>;
2390 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2391 memopv8f64, f64mem, loadf64, "{1to8}",
2392 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2393 EVEX_CD8<64, CD8VF>;
2394 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2395 memopv8f64, f64mem, loadf64, "{1to8}",
2396 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2397 EVEX_CD8<64, CD8VF>;
2398 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2399 memopv8f64, f64mem, loadf64, "{1to8}",
2400 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2401 EVEX_CD8<64, CD8VF>;
2402 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2403 memopv8f64, f64mem, loadf64, "{1to8}",
2404 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2405 EVEX_CD8<64, CD8VF>;
2408 let Constraints = "$src1 = $dst" in {
2409 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2410 RegisterClass RC, X86MemOperand x86memop,
2411 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2412 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2414 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2415 (ins RC:$src1, RC:$src3, x86memop:$src2),
2416 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2417 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2418 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2419 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2420 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2421 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2422 [(set RC:$dst, (OpNode RC:$src1,
2423 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2425 } // Constraints = "$src1 = $dst"
2428 let ExeDomain = SSEPackedSingle in {
2429 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2430 memopv16f32, f32mem, loadf32, "{1to16}",
2431 X86Fmadd, v16f32>, EVEX_V512,
2432 EVEX_CD8<32, CD8VF>;
2433 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2434 memopv16f32, f32mem, loadf32, "{1to16}",
2435 X86Fmsub, v16f32>, EVEX_V512,
2436 EVEX_CD8<32, CD8VF>;
2437 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2438 memopv16f32, f32mem, loadf32, "{1to16}",
2439 X86Fmaddsub, v16f32>,
2440 EVEX_V512, EVEX_CD8<32, CD8VF>;
2441 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2442 memopv16f32, f32mem, loadf32, "{1to16}",
2443 X86Fmsubadd, v16f32>,
2444 EVEX_V512, EVEX_CD8<32, CD8VF>;
2445 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2446 memopv16f32, f32mem, loadf32, "{1to16}",
2447 X86Fnmadd, v16f32>, EVEX_V512,
2448 EVEX_CD8<32, CD8VF>;
2449 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2450 memopv16f32, f32mem, loadf32, "{1to16}",
2451 X86Fnmsub, v16f32>, EVEX_V512,
2452 EVEX_CD8<32, CD8VF>;
2454 let ExeDomain = SSEPackedDouble in {
2455 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2456 memopv8f64, f64mem, loadf64, "{1to8}",
2457 X86Fmadd, v8f64>, EVEX_V512,
2458 VEX_W, EVEX_CD8<64, CD8VF>;
2459 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2460 memopv8f64, f64mem, loadf64, "{1to8}",
2461 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2462 EVEX_CD8<64, CD8VF>;
2463 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2464 memopv8f64, f64mem, loadf64, "{1to8}",
2465 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2466 EVEX_CD8<64, CD8VF>;
2467 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2468 memopv8f64, f64mem, loadf64, "{1to8}",
2469 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2470 EVEX_CD8<64, CD8VF>;
2471 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2472 memopv8f64, f64mem, loadf64, "{1to8}",
2473 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2474 EVEX_CD8<64, CD8VF>;
2475 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2476 memopv8f64, f64mem, loadf64, "{1to8}",
2477 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2478 EVEX_CD8<64, CD8VF>;
2482 let Constraints = "$src1 = $dst" in {
2483 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2484 RegisterClass RC, ValueType OpVT,
2485 X86MemOperand x86memop, Operand memop,
2487 let isCommutable = 1 in
2488 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2489 (ins RC:$src1, RC:$src2, RC:$src3),
2490 !strconcat(OpcodeStr,
2491 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2493 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2495 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2496 (ins RC:$src1, RC:$src2, f128mem:$src3),
2497 !strconcat(OpcodeStr,
2498 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2500 (OpVT (OpNode RC:$src2, RC:$src1,
2501 (mem_frag addr:$src3))))]>;
2504 } // Constraints = "$src1 = $dst"
2506 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2507 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2508 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2509 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2510 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2511 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2512 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2513 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2514 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2515 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2516 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2517 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2518 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2519 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2520 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2521 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2523 //===----------------------------------------------------------------------===//
2524 // AVX-512 Scalar convert from sign integer to float/double
2525 //===----------------------------------------------------------------------===//
2527 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2528 X86MemOperand x86memop, string asm> {
2529 let hasSideEffects = 0 in {
2530 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2531 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2534 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2535 (ins DstRC:$src1, x86memop:$src),
2536 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2538 } // hasSideEffects = 0
2540 let Predicates = [HasAVX512] in {
2541 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2542 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2543 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2544 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2545 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2546 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2547 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2548 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2550 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2551 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2552 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2553 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2554 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2555 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2556 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2557 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2559 def : Pat<(f32 (sint_to_fp GR32:$src)),
2560 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2561 def : Pat<(f32 (sint_to_fp GR64:$src)),
2562 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2563 def : Pat<(f64 (sint_to_fp GR32:$src)),
2564 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2565 def : Pat<(f64 (sint_to_fp GR64:$src)),
2566 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2568 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2569 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2570 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2571 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2572 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2573 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2574 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2575 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2577 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2578 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2579 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2580 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2581 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2582 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2583 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2584 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2586 def : Pat<(f32 (uint_to_fp GR32:$src)),
2587 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2588 def : Pat<(f32 (uint_to_fp GR64:$src)),
2589 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2590 def : Pat<(f64 (uint_to_fp GR32:$src)),
2591 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2592 def : Pat<(f64 (uint_to_fp GR64:$src)),
2593 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2596 //===----------------------------------------------------------------------===//
2597 // AVX-512 Scalar convert from float/double to integer
2598 //===----------------------------------------------------------------------===//
2599 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2600 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2602 let hasSideEffects = 0 in {
2603 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2604 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2605 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2606 Requires<[HasAVX512]>;
2608 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2609 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2610 Requires<[HasAVX512]>;
2611 } // hasSideEffects = 0
2613 let Predicates = [HasAVX512] in {
2614 // Convert float/double to signed/unsigned int 32/64
2615 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2616 ssmem, sse_load_f32, "cvtss2si">,
2617 XS, EVEX_CD8<32, CD8VT1>;
2618 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2619 ssmem, sse_load_f32, "cvtss2si">,
2620 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2621 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2622 ssmem, sse_load_f32, "cvtss2usi">,
2623 XS, EVEX_CD8<32, CD8VT1>;
2624 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2625 int_x86_avx512_cvtss2usi64, ssmem,
2626 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2627 EVEX_CD8<32, CD8VT1>;
2628 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2629 sdmem, sse_load_f64, "cvtsd2si">,
2630 XD, EVEX_CD8<64, CD8VT1>;
2631 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2632 sdmem, sse_load_f64, "cvtsd2si">,
2633 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2634 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2635 sdmem, sse_load_f64, "cvtsd2usi">,
2636 XD, EVEX_CD8<64, CD8VT1>;
2637 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2638 int_x86_avx512_cvtsd2usi64, sdmem,
2639 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2640 EVEX_CD8<64, CD8VT1>;
2642 let isCodeGenOnly = 1 in {
2643 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2644 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2645 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2646 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2647 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2648 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2649 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2650 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2651 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2652 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2653 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2654 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2656 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2657 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2658 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2659 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2660 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2661 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2662 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2663 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2664 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2665 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2666 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2667 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2668 } // isCodeGenOnly = 1
2670 // Convert float/double to signed/unsigned int 32/64 with truncation
2671 let isCodeGenOnly = 1 in {
2672 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2673 ssmem, sse_load_f32, "cvttss2si">,
2674 XS, EVEX_CD8<32, CD8VT1>;
2675 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2676 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2677 "cvttss2si">, XS, VEX_W,
2678 EVEX_CD8<32, CD8VT1>;
2679 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2680 sdmem, sse_load_f64, "cvttsd2si">, XD,
2681 EVEX_CD8<64, CD8VT1>;
2682 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2683 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2684 "cvttsd2si">, XD, VEX_W,
2685 EVEX_CD8<64, CD8VT1>;
2686 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2687 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2688 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2689 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2690 int_x86_avx512_cvttss2usi64, ssmem,
2691 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2692 EVEX_CD8<32, CD8VT1>;
2693 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2694 int_x86_avx512_cvttsd2usi,
2695 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2696 EVEX_CD8<64, CD8VT1>;
2697 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2698 int_x86_avx512_cvttsd2usi64, sdmem,
2699 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2700 EVEX_CD8<64, CD8VT1>;
2701 } // isCodeGenOnly = 1
2703 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2704 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2706 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2707 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2708 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2709 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2710 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2711 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2714 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2715 loadf32, "cvttss2si">, XS,
2716 EVEX_CD8<32, CD8VT1>;
2717 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2718 loadf32, "cvttss2usi">, XS,
2719 EVEX_CD8<32, CD8VT1>;
2720 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2721 loadf32, "cvttss2si">, XS, VEX_W,
2722 EVEX_CD8<32, CD8VT1>;
2723 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2724 loadf32, "cvttss2usi">, XS, VEX_W,
2725 EVEX_CD8<32, CD8VT1>;
2726 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2727 loadf64, "cvttsd2si">, XD,
2728 EVEX_CD8<64, CD8VT1>;
2729 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2730 loadf64, "cvttsd2usi">, XD,
2731 EVEX_CD8<64, CD8VT1>;
2732 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2733 loadf64, "cvttsd2si">, XD, VEX_W,
2734 EVEX_CD8<64, CD8VT1>;
2735 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2736 loadf64, "cvttsd2usi">, XD, VEX_W,
2737 EVEX_CD8<64, CD8VT1>;
2739 //===----------------------------------------------------------------------===//
2740 // AVX-512 Convert form float to double and back
2741 //===----------------------------------------------------------------------===//
2742 let hasSideEffects = 0 in {
2743 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2744 (ins FR32X:$src1, FR32X:$src2),
2745 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2746 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2748 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2749 (ins FR32X:$src1, f32mem:$src2),
2750 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2751 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2752 EVEX_CD8<32, CD8VT1>;
2754 // Convert scalar double to scalar single
2755 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2756 (ins FR64X:$src1, FR64X:$src2),
2757 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2758 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2760 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2761 (ins FR64X:$src1, f64mem:$src2),
2762 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2763 []>, EVEX_4V, VEX_LIG, VEX_W,
2764 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2767 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2768 Requires<[HasAVX512]>;
2769 def : Pat<(fextend (loadf32 addr:$src)),
2770 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2772 def : Pat<(extloadf32 addr:$src),
2773 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2774 Requires<[HasAVX512, OptForSize]>;
2776 def : Pat<(extloadf32 addr:$src),
2777 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2778 Requires<[HasAVX512, OptForSpeed]>;
2780 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2781 Requires<[HasAVX512]>;
2783 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2784 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2785 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2787 let hasSideEffects = 0 in {
2788 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2789 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2791 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2792 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2793 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2794 [], d>, EVEX, EVEX_B;
2796 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2797 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2799 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2800 } // hasSideEffects = 0
2803 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2804 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2805 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2807 let hasSideEffects = 0 in {
2808 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2809 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2811 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2813 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2814 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2816 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2817 } // hasSideEffects = 0
2820 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2821 memopv8f64, f512mem, v8f32, v8f64,
2822 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2823 EVEX_CD8<64, CD8VF>;
2825 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2826 memopv4f64, f256mem, v8f64, v8f32,
2827 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2828 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2829 (VCVTPS2PDZrm addr:$src)>;
2831 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2832 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2833 (VCVTPD2PSZrr VR512:$src)>;
2835 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2836 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2837 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2839 //===----------------------------------------------------------------------===//
2840 // AVX-512 Vector convert from sign integer to float/double
2841 //===----------------------------------------------------------------------===//
2843 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2844 memopv8i64, i512mem, v16f32, v16i32,
2845 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2847 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2848 memopv4i64, i256mem, v8f64, v8i32,
2849 SSEPackedDouble>, EVEX_V512, XS,
2850 EVEX_CD8<32, CD8VH>;
2852 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2853 memopv16f32, f512mem, v16i32, v16f32,
2854 SSEPackedSingle>, EVEX_V512, XS,
2855 EVEX_CD8<32, CD8VF>;
2857 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2858 memopv8f64, f512mem, v8i32, v8f64,
2859 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2860 EVEX_CD8<64, CD8VF>;
2862 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2863 memopv16f32, f512mem, v16i32, v16f32,
2864 SSEPackedSingle>, EVEX_V512,
2865 EVEX_CD8<32, CD8VF>;
2867 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2868 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2869 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2870 (VCVTTPS2UDQZrr VR512:$src)>;
2872 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2873 memopv8f64, f512mem, v8i32, v8f64,
2874 SSEPackedDouble>, EVEX_V512, VEX_W,
2875 EVEX_CD8<64, CD8VF>;
2877 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2878 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2879 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2880 (VCVTTPD2UDQZrr VR512:$src)>;
2882 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2883 memopv4i64, f256mem, v8f64, v8i32,
2884 SSEPackedDouble>, EVEX_V512, XS,
2885 EVEX_CD8<32, CD8VH>;
2887 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2888 memopv16i32, f512mem, v16f32, v16i32,
2889 SSEPackedSingle>, EVEX_V512, XD,
2890 EVEX_CD8<32, CD8VF>;
2892 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2893 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2894 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2897 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2898 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2899 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2900 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2901 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2902 (VCVTDQ2PDZrr VR256X:$src)>;
2903 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2904 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2905 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2906 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2907 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2908 (VCVTUDQ2PDZrr VR256X:$src)>;
2910 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2911 RegisterClass DstRC, PatFrag mem_frag,
2912 X86MemOperand x86memop, Domain d> {
2913 let hasSideEffects = 0 in {
2914 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2915 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2917 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2918 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2919 [], d>, EVEX, EVEX_B;
2921 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2922 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2924 } // hasSideEffects = 0
2927 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2928 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2929 EVEX_V512, EVEX_CD8<32, CD8VF>;
2930 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2931 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2932 EVEX_V512, EVEX_CD8<64, CD8VF>;
2934 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2935 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2936 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2938 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2939 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2940 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2942 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2943 memopv16f32, f512mem, SSEPackedSingle>,
2944 EVEX_V512, EVEX_CD8<32, CD8VF>;
2945 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2946 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2947 EVEX_V512, EVEX_CD8<64, CD8VF>;
2949 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2950 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2951 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2953 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2954 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2955 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2957 let Predicates = [HasAVX512] in {
2958 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2959 (VCVTPD2PSZrm addr:$src)>;
2960 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2961 (VCVTPS2PDZrm addr:$src)>;
2964 //===----------------------------------------------------------------------===//
2965 // Half precision conversion instructions
2966 //===----------------------------------------------------------------------===//
2967 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2968 X86MemOperand x86memop, Intrinsic Int> {
2969 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2970 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2971 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2972 let hasSideEffects = 0, mayLoad = 1 in
2973 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2974 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2977 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2978 X86MemOperand x86memop, Intrinsic Int> {
2979 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2980 (ins srcRC:$src1, i32i8imm:$src2),
2981 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2982 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2983 let hasSideEffects = 0, mayStore = 1 in
2984 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2985 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2986 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2989 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2990 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2991 EVEX_CD8<32, CD8VH>;
2992 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2993 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2994 EVEX_CD8<32, CD8VH>;
2996 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2997 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2998 "ucomiss">, TB, EVEX, VEX_LIG,
2999 EVEX_CD8<32, CD8VT1>;
3000 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3001 "ucomisd">, TB, OpSize, EVEX,
3002 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3003 let Pattern = []<dag> in {
3004 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3005 "comiss">, TB, EVEX, VEX_LIG,
3006 EVEX_CD8<32, CD8VT1>;
3007 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3008 "comisd">, TB, OpSize, EVEX,
3009 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3011 let isCodeGenOnly = 1 in {
3012 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3013 load, "ucomiss">, TB, EVEX, VEX_LIG,
3014 EVEX_CD8<32, CD8VT1>;
3015 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3016 load, "ucomisd">, TB, OpSize, EVEX,
3017 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3019 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3020 load, "comiss">, TB, EVEX, VEX_LIG,
3021 EVEX_CD8<32, CD8VT1>;
3022 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3023 load, "comisd">, TB, OpSize, EVEX,
3024 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3028 /// avx512_unop_p - AVX-512 unops in packed form.
3029 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3030 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3031 !strconcat(OpcodeStr,
3032 "ps\t{$src, $dst|$dst, $src}"),
3033 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
3035 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
3036 !strconcat(OpcodeStr,
3037 "ps\t{$src, $dst|$dst, $src}"),
3038 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
3039 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3040 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3041 !strconcat(OpcodeStr,
3042 "pd\t{$src, $dst|$dst, $src}"),
3043 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
3044 EVEX, EVEX_V512, VEX_W;
3045 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3046 !strconcat(OpcodeStr,
3047 "pd\t{$src, $dst|$dst, $src}"),
3048 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
3049 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3052 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
3053 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3054 Intrinsic V16F32Int, Intrinsic V8F64Int> {
3055 let isCodeGenOnly = 1 in {
3056 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3057 !strconcat(OpcodeStr,
3058 "ps\t{$src, $dst|$dst, $src}"),
3059 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3061 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3062 !strconcat(OpcodeStr,
3063 "ps\t{$src, $dst|$dst, $src}"),
3065 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3066 EVEX_V512, EVEX_CD8<32, CD8VF>;
3067 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3068 !strconcat(OpcodeStr,
3069 "pd\t{$src, $dst|$dst, $src}"),
3070 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3071 EVEX, EVEX_V512, VEX_W;
3072 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3073 !strconcat(OpcodeStr,
3074 "pd\t{$src, $dst|$dst, $src}"),
3076 (V8F64Int (memopv8f64 addr:$src)))]>,
3077 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3078 } // isCodeGenOnly = 1
3081 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
3082 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
3083 let hasSideEffects = 0 in {
3084 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
3085 (ins FR32X:$src1, FR32X:$src2),
3086 !strconcat(OpcodeStr,
3087 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 let mayLoad = 1 in {
3090 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
3091 (ins FR32X:$src1, f32mem:$src2),
3092 !strconcat(OpcodeStr,
3093 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3094 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3095 let isCodeGenOnly = 1 in
3096 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3097 (ins VR128X:$src1, ssmem:$src2),
3098 !strconcat(OpcodeStr,
3099 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3100 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3102 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
3103 (ins FR64X:$src1, FR64X:$src2),
3104 !strconcat(OpcodeStr,
3105 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3107 let mayLoad = 1 in {
3108 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
3109 (ins FR64X:$src1, f64mem:$src2),
3110 !strconcat(OpcodeStr,
3111 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3112 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3113 let isCodeGenOnly = 1 in
3114 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3115 (ins VR128X:$src1, sdmem:$src2),
3116 !strconcat(OpcodeStr,
3117 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3118 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3123 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
3124 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
3125 avx512_fp_unop_p_int<0x4C, "vrcp14",
3126 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
3128 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
3129 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
3130 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
3131 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
3133 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
3134 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
3135 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3137 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
3138 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3140 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
3141 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
3142 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3144 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
3145 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3147 let AddedComplexity = 20, Predicates = [HasERI] in {
3148 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
3149 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
3150 avx512_fp_unop_p_int<0xCA, "vrcp28",
3151 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
3153 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
3154 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
3155 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
3156 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
3159 let Predicates = [HasERI] in {
3160 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
3161 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
3162 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3164 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
3165 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3167 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
3168 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
3169 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3171 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
3172 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3174 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3175 Intrinsic V16F32Int, Intrinsic V8F64Int,
3176 OpndItins itins_s, OpndItins itins_d> {
3177 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3179 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3183 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3184 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3186 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3187 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3189 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3190 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3191 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3195 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3196 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3197 [(set VR512:$dst, (OpNode
3198 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3199 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3201 let isCodeGenOnly = 1 in {
3202 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3203 !strconcat(OpcodeStr,
3204 "ps\t{$src, $dst|$dst, $src}"),
3205 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3207 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3208 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3210 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3211 EVEX_V512, EVEX_CD8<32, CD8VF>;
3212 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3213 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3214 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3215 EVEX, EVEX_V512, VEX_W;
3216 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3217 !strconcat(OpcodeStr,
3218 "pd\t{$src, $dst|$dst, $src}"),
3219 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3220 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3221 } // isCodeGenOnly = 1
3224 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3225 Intrinsic F32Int, Intrinsic F64Int,
3226 OpndItins itins_s, OpndItins itins_d> {
3227 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3228 (ins FR32X:$src1, FR32X:$src2),
3229 !strconcat(OpcodeStr,
3230 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3231 [], itins_s.rr>, XS, EVEX_4V;
3232 let isCodeGenOnly = 1 in
3233 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3234 (ins VR128X:$src1, VR128X:$src2),
3235 !strconcat(OpcodeStr,
3236 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3238 (F32Int VR128X:$src1, VR128X:$src2))],
3239 itins_s.rr>, XS, EVEX_4V;
3240 let mayLoad = 1 in {
3241 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3242 (ins FR32X:$src1, f32mem:$src2),
3243 !strconcat(OpcodeStr,
3244 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3245 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3246 let isCodeGenOnly = 1 in
3247 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3248 (ins VR128X:$src1, ssmem:$src2),
3249 !strconcat(OpcodeStr,
3250 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3252 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3253 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3255 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3256 (ins FR64X:$src1, FR64X:$src2),
3257 !strconcat(OpcodeStr,
3258 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3260 let isCodeGenOnly = 1 in
3261 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3262 (ins VR128X:$src1, VR128X:$src2),
3263 !strconcat(OpcodeStr,
3264 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3266 (F64Int VR128X:$src1, VR128X:$src2))],
3267 itins_s.rr>, XD, EVEX_4V, VEX_W;
3268 let mayLoad = 1 in {
3269 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3270 (ins FR64X:$src1, f64mem:$src2),
3271 !strconcat(OpcodeStr,
3272 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3273 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3274 let isCodeGenOnly = 1 in
3275 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3276 (ins VR128X:$src1, sdmem:$src2),
3277 !strconcat(OpcodeStr,
3278 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3280 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3281 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3286 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3287 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3288 SSE_SQRTSS, SSE_SQRTSD>,
3289 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3290 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3291 SSE_SQRTPS, SSE_SQRTPD>;
3293 let Predicates = [HasAVX512] in {
3294 def : Pat<(f32 (fsqrt FR32X:$src)),
3295 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3296 def : Pat<(f32 (fsqrt (load addr:$src))),
3297 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3298 Requires<[OptForSize]>;
3299 def : Pat<(f64 (fsqrt FR64X:$src)),
3300 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3301 def : Pat<(f64 (fsqrt (load addr:$src))),
3302 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3303 Requires<[OptForSize]>;
3305 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3306 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3307 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3308 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3309 Requires<[OptForSize]>;
3311 def : Pat<(f32 (X86frcp FR32X:$src)),
3312 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3313 def : Pat<(f32 (X86frcp (load addr:$src))),
3314 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3315 Requires<[OptForSize]>;
3317 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3318 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3319 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3321 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3322 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3324 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3325 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3326 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3328 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3329 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3333 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3334 X86MemOperand x86memop, RegisterClass RC,
3335 PatFrag mem_frag32, PatFrag mem_frag64,
3336 Intrinsic V4F32Int, Intrinsic V2F64Int,
3338 let ExeDomain = SSEPackedSingle in {
3339 // Intrinsic operation, reg.
3340 // Vector intrinsic operation, reg
3341 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3342 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3343 !strconcat(OpcodeStr,
3344 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3345 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3347 // Vector intrinsic operation, mem
3348 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3349 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3350 !strconcat(OpcodeStr,
3351 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3353 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3354 EVEX_CD8<32, VForm>;
3355 } // ExeDomain = SSEPackedSingle
3357 let ExeDomain = SSEPackedDouble in {
3358 // Vector intrinsic operation, reg
3359 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3360 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3361 !strconcat(OpcodeStr,
3362 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3363 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3365 // Vector intrinsic operation, mem
3366 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3367 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3368 !strconcat(OpcodeStr,
3369 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3371 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3372 EVEX_CD8<64, VForm>;
3373 } // ExeDomain = SSEPackedDouble
3376 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3380 let ExeDomain = GenericDomain in {
3382 let hasSideEffects = 0 in
3383 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3384 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3385 !strconcat(OpcodeStr,
3386 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3389 // Intrinsic operation, reg.
3390 let isCodeGenOnly = 1 in
3391 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3392 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3393 !strconcat(OpcodeStr,
3394 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3395 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3397 // Intrinsic operation, mem.
3398 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3399 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3400 !strconcat(OpcodeStr,
3401 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3402 [(set VR128X:$dst, (F32Int VR128X:$src1,
3403 sse_load_f32:$src2, imm:$src3))]>,
3404 EVEX_CD8<32, CD8VT1>;
3407 let hasSideEffects = 0 in
3408 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3409 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3410 !strconcat(OpcodeStr,
3411 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3414 // Intrinsic operation, reg.
3415 let isCodeGenOnly = 1 in
3416 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3417 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3418 !strconcat(OpcodeStr,
3419 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3420 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3423 // Intrinsic operation, mem.
3424 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3425 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3426 !strconcat(OpcodeStr,
3427 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3429 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3430 VEX_W, EVEX_CD8<64, CD8VT1>;
3431 } // ExeDomain = GenericDomain
3434 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3435 X86MemOperand x86memop, RegisterClass RC,
3436 PatFrag mem_frag, Domain d> {
3437 let ExeDomain = d in {
3438 // Intrinsic operation, reg.
3439 // Vector intrinsic operation, reg
3440 def r : AVX512AIi8<opc, MRMSrcReg,
3441 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3442 !strconcat(OpcodeStr,
3443 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3446 // Vector intrinsic operation, mem
3447 def m : AVX512AIi8<opc, MRMSrcMem,
3448 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3449 !strconcat(OpcodeStr,
3450 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3456 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3457 memopv16f32, SSEPackedSingle>, EVEX_V512,
3458 EVEX_CD8<32, CD8VF>;
3460 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3461 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3463 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3466 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3467 memopv8f64, SSEPackedDouble>, EVEX_V512,
3468 VEX_W, EVEX_CD8<64, CD8VF>;
3470 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3471 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3473 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3475 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3476 Operand x86memop, RegisterClass RC, Domain d> {
3477 let ExeDomain = d in {
3478 def r : AVX512AIi8<opc, MRMSrcReg,
3479 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3480 !strconcat(OpcodeStr,
3481 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3484 def m : AVX512AIi8<opc, MRMSrcMem,
3485 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3486 !strconcat(OpcodeStr,
3487 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3492 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3493 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3495 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3496 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3498 def : Pat<(ffloor FR32X:$src),
3499 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3500 def : Pat<(f64 (ffloor FR64X:$src)),
3501 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3502 def : Pat<(f32 (fnearbyint FR32X:$src)),
3503 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3504 def : Pat<(f64 (fnearbyint FR64X:$src)),
3505 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3506 def : Pat<(f32 (fceil FR32X:$src)),
3507 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3508 def : Pat<(f64 (fceil FR64X:$src)),
3509 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3510 def : Pat<(f32 (frint FR32X:$src)),
3511 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3512 def : Pat<(f64 (frint FR64X:$src)),
3513 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3514 def : Pat<(f32 (ftrunc FR32X:$src)),
3515 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3516 def : Pat<(f64 (ftrunc FR64X:$src)),
3517 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3519 def : Pat<(v16f32 (ffloor VR512:$src)),
3520 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3521 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3522 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3523 def : Pat<(v16f32 (fceil VR512:$src)),
3524 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3525 def : Pat<(v16f32 (frint VR512:$src)),
3526 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3527 def : Pat<(v16f32 (ftrunc VR512:$src)),
3528 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3530 def : Pat<(v8f64 (ffloor VR512:$src)),
3531 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3532 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3533 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3534 def : Pat<(v8f64 (fceil VR512:$src)),
3535 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3536 def : Pat<(v8f64 (frint VR512:$src)),
3537 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3538 def : Pat<(v8f64 (ftrunc VR512:$src)),
3539 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3541 //-------------------------------------------------
3542 // Integer truncate and extend operations
3543 //-------------------------------------------------
3545 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3546 RegisterClass dstRC, RegisterClass srcRC,
3547 RegisterClass KRC, X86MemOperand x86memop> {
3548 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3550 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3553 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3554 (ins KRC:$mask, srcRC:$src),
3555 !strconcat(OpcodeStr,
3556 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3559 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3563 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3564 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3565 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3566 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3567 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3568 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3569 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3570 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3571 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3572 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3573 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3574 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3575 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3576 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3577 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3578 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3579 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3580 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3581 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3582 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3583 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3584 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3585 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3586 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3587 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3588 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3589 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3590 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3591 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3592 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3594 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3595 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3596 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3597 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3598 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3600 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3601 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3602 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3603 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3604 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3605 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3606 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3607 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3610 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3611 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3612 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3614 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3617 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3618 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3619 (ins x86memop:$src),
3620 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3622 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3626 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3627 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3629 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3630 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3632 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3633 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3634 EVEX_CD8<16, CD8VH>;
3635 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3636 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3637 EVEX_CD8<16, CD8VQ>;
3638 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3639 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3640 EVEX_CD8<32, CD8VH>;
3642 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3643 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3645 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3646 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3648 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3649 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3650 EVEX_CD8<16, CD8VH>;
3651 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3652 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3653 EVEX_CD8<16, CD8VQ>;
3654 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3655 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3656 EVEX_CD8<32, CD8VH>;
3658 //===----------------------------------------------------------------------===//
3659 // GATHER - SCATTER Operations
3661 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3662 RegisterClass RC, X86MemOperand memop> {
3664 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3665 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3666 (ins RC:$src1, KRC:$mask, memop:$src2),
3667 !strconcat(OpcodeStr,
3668 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3671 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3672 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3673 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3674 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3676 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3677 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3678 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3679 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3681 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3682 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3683 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3684 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3686 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3687 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3688 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3689 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3691 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3692 RegisterClass RC, X86MemOperand memop> {
3693 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3694 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3695 (ins memop:$dst, KRC:$mask, RC:$src2),
3696 !strconcat(OpcodeStr,
3697 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3701 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3703 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3704 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3706 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3707 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3708 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3709 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3711 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3712 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3713 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3714 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3716 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3717 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3718 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3719 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3721 //===----------------------------------------------------------------------===//
3722 // VSHUFPS - VSHUFPD Operations
3724 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3725 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3727 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3728 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3729 !strconcat(OpcodeStr,
3730 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3731 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3732 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3733 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3734 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3735 (ins RC:$src1, RC:$src2, i8imm:$src3),
3736 !strconcat(OpcodeStr,
3737 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3738 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3739 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3740 EVEX_4V, Sched<[WriteShuffle]>;
3743 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3744 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3745 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3746 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3748 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3749 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3750 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3751 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3752 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3754 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3755 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3756 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3757 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3758 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3760 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3761 X86MemOperand x86memop> {
3762 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3763 (ins RC:$src1, RC:$src2, i8imm:$src3),
3764 !strconcat(OpcodeStr,
3765 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3768 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3769 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3770 !strconcat(OpcodeStr,
3771 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3774 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3775 EVEX_V512, EVEX_CD8<32, CD8VF>;
3776 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3777 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3779 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3780 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3781 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3782 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3783 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3784 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3785 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3786 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3788 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3789 X86MemOperand x86memop> {
3790 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3793 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3794 (ins x86memop:$src),
3795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3799 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3800 EVEX_CD8<32, CD8VF>;
3801 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3802 EVEX_CD8<64, CD8VF>;
3804 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3805 (v16i32 immAllZerosV), (i16 -1))),
3806 (VPABSDrr VR512:$src)>;
3807 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3808 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3809 (VPABSQrr VR512:$src)>;
3811 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3812 RegisterClass RC, RegisterClass KRC,
3813 X86MemOperand x86memop,
3814 X86MemOperand x86scalar_mop, string BrdcstStr> {
3815 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3817 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3819 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3820 (ins x86memop:$src),
3821 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3823 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3824 (ins x86scalar_mop:$src),
3825 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3826 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3828 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3829 (ins KRC:$mask, RC:$src),
3830 !strconcat(OpcodeStr,
3831 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3833 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3834 (ins KRC:$mask, x86memop:$src),
3835 !strconcat(OpcodeStr,
3836 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3838 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3839 (ins KRC:$mask, x86scalar_mop:$src),
3840 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3841 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3843 []>, EVEX, EVEX_KZ, EVEX_B;
3845 let Constraints = "$src1 = $dst" in {
3846 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3847 (ins RC:$src1, KRC:$mask, RC:$src2),
3848 !strconcat(OpcodeStr,
3849 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3851 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3852 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3853 !strconcat(OpcodeStr,
3854 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3856 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3857 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3858 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3859 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3860 []>, EVEX, EVEX_K, EVEX_B;
3864 let Predicates = [HasCDI] in {
3865 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3866 i512mem, i32mem, "{1to16}">,
3867 EVEX_V512, EVEX_CD8<32, CD8VF>;
3870 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3871 i512mem, i64mem, "{1to8}">,
3872 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3876 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3878 (VPCONFLICTDrrk VR512:$src1,
3879 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3881 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3883 (VPCONFLICTQrrk VR512:$src1,
3884 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;