1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
108 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
109 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
110 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
111 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
113 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
114 X86VectorVTInfo i128> {
115 X86VectorVTInfo info512 = i512;
116 X86VectorVTInfo info256 = i256;
117 X86VectorVTInfo info128 = i128;
120 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
122 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
124 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
126 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
129 // This multiclass generates the masking variants from the non-masking
130 // variant. It only provides the assembly pieces for the masking variants.
131 // It assumes custom ISel patterns for masking which can be provided as
132 // template arguments.
133 multiclass AVX512_maskable_custom<bits<8> O, Format F,
135 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
137 string AttSrcAsm, string IntelSrcAsm,
139 list<dag> MaskingPattern,
140 list<dag> ZeroMaskingPattern,
141 string MaskingConstraint = "",
142 InstrItinClass itin = NoItinerary,
143 bit IsCommutable = 0> {
144 let isCommutable = IsCommutable in
145 def NAME: AVX512<O, F, Outs, Ins,
146 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
147 "$dst, "#IntelSrcAsm#"}",
150 // Prefer over VMOV*rrk Pat<>
151 let AddedComplexity = 20 in
152 def NAME#k: AVX512<O, F, Outs, MaskingIns,
153 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
154 "$dst {${mask}}, "#IntelSrcAsm#"}",
155 MaskingPattern, itin>,
157 // In case of the 3src subclass this is overridden with a let.
158 string Constraints = MaskingConstraint;
160 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
161 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
163 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
170 // Common base class of AVX512_maskable and AVX512_maskable_3src.
171 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
173 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
175 string AttSrcAsm, string IntelSrcAsm,
176 dag RHS, dag MaskingRHS,
177 string MaskingConstraint = "",
178 InstrItinClass itin = NoItinerary,
179 bit IsCommutable = 0> :
180 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
181 AttSrcAsm, IntelSrcAsm,
182 [(set _.RC:$dst, RHS)],
183 [(set _.RC:$dst, MaskingRHS)],
185 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
186 MaskingConstraint, NoItinerary, IsCommutable>;
188 // This multiclass generates the unconditional/non-masking, the masking and
189 // the zero-masking variant of the instruction. In the masking case, the
190 // perserved vector elements come from a new dummy input operand tied to $dst.
191 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Outs, dag Ins, string OpcodeStr,
193 string AttSrcAsm, string IntelSrcAsm,
194 dag RHS, InstrItinClass itin = NoItinerary,
195 bit IsCommutable = 0> :
196 AVX512_maskable_common<O, F, _, Outs, Ins,
197 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
198 !con((ins _.KRCWM:$mask), Ins),
199 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
200 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
201 "$src0 = $dst", itin, IsCommutable>;
203 // Similar to AVX512_maskable but in this case one of the source operands
204 // ($src1) is already tied to $dst so we just use that for the preserved
205 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
207 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
208 dag Outs, dag NonTiedIns, string OpcodeStr,
209 string AttSrcAsm, string IntelSrcAsm,
211 AVX512_maskable_common<O, F, _, Outs,
212 !con((ins _.RC:$src1), NonTiedIns),
213 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
214 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
215 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
216 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
219 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
222 string AttSrcAsm, string IntelSrcAsm,
224 AVX512_maskable_custom<O, F, Outs, Ins,
225 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
226 !con((ins _.KRCWM:$mask), Ins),
227 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
230 // Bitcasts between 512-bit vector types. Return the original type since
231 // no instruction is needed for the conversion
232 let Predicates = [HasAVX512] in {
233 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
234 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
235 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
236 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
237 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
238 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
239 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
240 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
241 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
242 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
243 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
244 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
245 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
246 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
247 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
248 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
249 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
250 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
251 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
252 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
253 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
254 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
255 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
256 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
257 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
258 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
259 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
260 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
261 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
262 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
263 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
265 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
266 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
267 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
268 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
269 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
270 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
271 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
272 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
273 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
274 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
275 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
276 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
277 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
278 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
279 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
280 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
281 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
282 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
283 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
284 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
285 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
286 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
287 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
288 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
289 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
290 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
291 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
292 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
293 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
294 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
296 // Bitcasts between 256-bit vector types. Return the original type since
297 // no instruction is needed for the conversion
298 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
299 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
300 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
301 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
302 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
303 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
304 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
305 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
306 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
307 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
308 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
309 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
310 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
311 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
312 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
313 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
314 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
315 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
316 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
317 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
318 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
319 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
320 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
321 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
322 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
323 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
324 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
325 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
326 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
327 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
331 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
334 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
335 isPseudo = 1, Predicates = [HasAVX512] in {
336 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
337 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
340 let Predicates = [HasAVX512] in {
341 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
342 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
343 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
346 //===----------------------------------------------------------------------===//
347 // AVX-512 - VECTOR INSERT
350 multiclass vinsert_for_size_no_alt<int Opcode,
351 X86VectorVTInfo From, X86VectorVTInfo To,
352 PatFrag vinsert_insert,
353 SDNodeXForm INSERT_get_vinsert_imm> {
354 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
355 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
356 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
357 "vinsert" # From.EltTypeName # "x" # From.NumElts #
358 "\t{$src3, $src2, $src1, $dst|"
359 "$dst, $src1, $src2, $src3}",
360 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
361 (From.VT From.RC:$src2),
366 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
367 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
372 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
376 multiclass vinsert_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vinsert_insert,
380 SDNodeXForm INSERT_get_vinsert_imm> :
381 vinsert_for_size_no_alt<Opcode, From, To,
382 vinsert_insert, INSERT_get_vinsert_imm> {
383 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
384 // vinserti32x4. Only add this if 64x2 and friends are not supported
385 // natively via AVX512DQ.
386 let Predicates = [NoDQI] in
387 def : Pat<(vinsert_insert:$ins
388 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
389 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
390 VR512:$src1, From.RC:$src2,
391 (INSERT_get_vinsert_imm VR512:$ins)))>;
394 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
395 ValueType EltVT64, int Opcode256> {
396 defm NAME # "32x4" : vinsert_for_size<Opcode128,
397 X86VectorVTInfo< 4, EltVT32, VR128X>,
398 X86VectorVTInfo<16, EltVT32, VR512>,
399 X86VectorVTInfo< 2, EltVT64, VR128X>,
400 X86VectorVTInfo< 8, EltVT64, VR512>,
402 INSERT_get_vinsert128_imm>;
403 let Predicates = [HasDQI] in
404 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
405 X86VectorVTInfo< 2, EltVT64, VR128X>,
406 X86VectorVTInfo< 8, EltVT64, VR512>,
408 INSERT_get_vinsert128_imm>, VEX_W;
409 defm NAME # "64x4" : vinsert_for_size<Opcode256,
410 X86VectorVTInfo< 4, EltVT64, VR256X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
412 X86VectorVTInfo< 8, EltVT32, VR256>,
413 X86VectorVTInfo<16, EltVT32, VR512>,
415 INSERT_get_vinsert256_imm>, VEX_W;
416 let Predicates = [HasDQI] in
417 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
418 X86VectorVTInfo< 8, EltVT32, VR256X>,
419 X86VectorVTInfo<16, EltVT32, VR512>,
421 INSERT_get_vinsert256_imm>;
424 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
425 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
427 // vinsertps - insert f32 to XMM
428 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
429 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
430 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
431 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
433 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
434 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
435 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
436 [(set VR128X:$dst, (X86insertps VR128X:$src1,
437 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
438 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
440 //===----------------------------------------------------------------------===//
441 // AVX-512 VECTOR EXTRACT
444 multiclass vextract_for_size<int Opcode,
445 X86VectorVTInfo From, X86VectorVTInfo To,
446 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
447 PatFrag vextract_extract,
448 SDNodeXForm EXTRACT_get_vextract_imm> {
449 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
450 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
451 (ins VR512:$src1, i8imm:$idx),
452 "vextract" # To.EltTypeName # "x4",
453 "$idx, $src1", "$src1, $idx",
454 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
456 AVX512AIi8Base, EVEX, EVEX_V512;
458 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
459 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
460 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
461 "$dst, $src1, $src2}",
462 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
465 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
467 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
468 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
470 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
472 // A 128/256-bit subvector extract from the first 512-bit vector position is
473 // a subregister copy that needs no instruction.
474 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
476 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
478 // And for the alternative types.
479 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
481 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
483 // Intrinsic call with masking.
484 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
486 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
487 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
488 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
489 VR512:$src1, imm:$idx)>;
491 // Intrinsic call with zero-masking.
492 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
494 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
495 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
496 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
497 VR512:$src1, imm:$idx)>;
499 // Intrinsic call without masking.
500 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
502 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
503 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
504 VR512:$src1, imm:$idx)>;
507 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
508 ValueType EltVT64, int Opcode64> {
509 defm NAME # "32x4" : vextract_for_size<Opcode32,
510 X86VectorVTInfo<16, EltVT32, VR512>,
511 X86VectorVTInfo< 4, EltVT32, VR128X>,
512 X86VectorVTInfo< 8, EltVT64, VR512>,
513 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 EXTRACT_get_vextract128_imm>;
516 defm NAME # "64x4" : vextract_for_size<Opcode64,
517 X86VectorVTInfo< 8, EltVT64, VR512>,
518 X86VectorVTInfo< 4, EltVT64, VR256X>,
519 X86VectorVTInfo<16, EltVT32, VR512>,
520 X86VectorVTInfo< 8, EltVT32, VR256>,
522 EXTRACT_get_vextract256_imm>, VEX_W;
525 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
526 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
528 // A 128-bit subvector insert to the first 512-bit vector position
529 // is a subregister copy that needs no instruction.
530 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
531 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
532 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
534 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
535 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
536 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
538 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
542 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
547 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
548 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
549 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
551 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
552 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
553 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
556 // vextractps - extract 32 bits from XMM
557 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
558 (ins VR128X:$src1, i32i8imm:$src2),
559 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
560 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
563 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
564 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
565 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
566 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
567 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
569 //===---------------------------------------------------------------------===//
572 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
573 RegisterClass DestRC,
574 RegisterClass SrcRC, X86MemOperand x86memop> {
575 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
578 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
581 let ExeDomain = SSEPackedSingle in {
582 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
584 EVEX_V512, EVEX_CD8<32, CD8VT1>;
587 let ExeDomain = SSEPackedDouble in {
588 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
593 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
594 (VBROADCASTSSZrm addr:$src)>;
595 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
596 (VBROADCASTSDZrm addr:$src)>;
598 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
599 (VBROADCASTSSZrm addr:$src)>;
600 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
601 (VBROADCASTSDZrm addr:$src)>;
603 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
604 RegisterClass SrcRC, RegisterClass KRC> {
605 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
606 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
607 []>, EVEX, EVEX_V512;
608 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
609 (ins KRC:$mask, SrcRC:$src),
610 !strconcat(OpcodeStr,
611 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
612 []>, EVEX, EVEX_V512, EVEX_KZ;
615 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
616 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
619 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
620 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
622 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
623 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
625 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
626 (VPBROADCASTDrZrr GR32:$src)>;
627 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
628 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
629 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
630 (VPBROADCASTQrZrr GR64:$src)>;
631 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
632 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
634 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
635 (VPBROADCASTDrZrr GR32:$src)>;
636 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
637 (VPBROADCASTQrZrr GR64:$src)>;
639 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
640 (v16i32 immAllZerosV), (i16 GR16:$mask))),
641 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
642 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
643 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
644 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
646 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
647 X86MemOperand x86memop, PatFrag ld_frag,
648 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
650 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
651 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
653 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
654 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
656 !strconcat(OpcodeStr,
657 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
659 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
663 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
665 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
666 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
668 !strconcat(OpcodeStr,
669 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
670 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
671 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
675 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
676 loadi32, VR512, v16i32, v4i32, VK16WM>,
677 EVEX_V512, EVEX_CD8<32, CD8VT1>;
678 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
679 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
680 EVEX_CD8<64, CD8VT1>;
682 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
683 X86MemOperand x86memop, PatFrag ld_frag,
686 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
689 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
691 !strconcat(OpcodeStr,
692 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
697 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
698 i128mem, loadv2i64, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
701 i256mem, loadv4i64, VK16WM>, VEX_W,
702 EVEX_V512, EVEX_CD8<64, CD8VT4>;
704 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
705 (VPBROADCASTDZrr VR128X:$src)>;
706 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
707 (VPBROADCASTQZrr VR128X:$src)>;
709 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
710 (VBROADCASTSSZrr VR128X:$src)>;
711 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
712 (VBROADCASTSDZrr VR128X:$src)>;
714 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
715 (VBROADCASTSSZrr VR128X:$src)>;
716 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
717 (VBROADCASTSDZrr VR128X:$src)>;
719 // Provide fallback in case the load node that is used in the patterns above
720 // is used by additional users, which prevents the pattern selection.
721 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
722 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
723 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
724 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
727 let Predicates = [HasAVX512] in {
728 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
730 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
731 addr:$src)), sub_ymm)>;
733 //===----------------------------------------------------------------------===//
734 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
737 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
739 let Predicates = [HasCDI] in
740 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
741 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
742 []>, EVEX, EVEX_V512;
744 let Predicates = [HasCDI, HasVLX] in {
745 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
746 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
747 []>, EVEX, EVEX_V128;
748 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
749 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
750 []>, EVEX, EVEX_V256;
754 let Predicates = [HasCDI] in {
755 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
757 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
761 //===----------------------------------------------------------------------===//
764 // -- immediate form --
765 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
766 SDNode OpNode, PatFrag mem_frag,
767 X86MemOperand x86memop, ValueType OpVT> {
768 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
769 (ins RC:$src1, i8imm:$src2),
770 !strconcat(OpcodeStr,
771 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
773 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
775 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
776 (ins x86memop:$src1, i8imm:$src2),
777 !strconcat(OpcodeStr,
778 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
780 (OpVT (OpNode (mem_frag addr:$src1),
781 (i8 imm:$src2))))]>, EVEX;
784 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
785 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
786 let ExeDomain = SSEPackedDouble in
787 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
788 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
790 // -- VPERM - register form --
791 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
792 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
794 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
795 (ins RC:$src1, RC:$src2),
796 !strconcat(OpcodeStr,
797 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
799 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
801 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
802 (ins RC:$src1, x86memop:$src2),
803 !strconcat(OpcodeStr,
804 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
806 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
810 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
811 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
812 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
813 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
814 let ExeDomain = SSEPackedSingle in
815 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
816 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
817 let ExeDomain = SSEPackedDouble in
818 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
819 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
821 // -- VPERM2I - 3 source operands form --
822 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
823 PatFrag mem_frag, X86MemOperand x86memop,
824 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
825 let Constraints = "$src1 = $dst" in {
826 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
827 (ins RC:$src1, RC:$src2, RC:$src3),
828 !strconcat(OpcodeStr,
829 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
831 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
834 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
835 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
836 !strconcat(OpcodeStr,
837 " \t{$src3, $src2, $dst {${mask}}|"
838 "$dst {${mask}}, $src2, $src3}"),
839 [(set RC:$dst, (OpVT (vselect KRC:$mask,
840 (OpNode RC:$src1, RC:$src2,
845 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
846 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
847 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
848 !strconcat(OpcodeStr,
849 " \t{$src3, $src2, $dst {${mask}} {z} |",
850 "$dst {${mask}} {z}, $src2, $src3}"),
851 [(set RC:$dst, (OpVT (vselect KRC:$mask,
852 (OpNode RC:$src1, RC:$src2,
855 (v16i32 immAllZerosV))))))]>,
858 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
859 (ins RC:$src1, RC:$src2, x86memop:$src3),
860 !strconcat(OpcodeStr,
861 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
863 (OpVT (OpNode RC:$src1, RC:$src2,
864 (mem_frag addr:$src3))))]>, EVEX_4V;
866 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
867 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
868 !strconcat(OpcodeStr,
869 " \t{$src3, $src2, $dst {${mask}}|"
870 "$dst {${mask}}, $src2, $src3}"),
872 (OpVT (vselect KRC:$mask,
873 (OpNode RC:$src1, RC:$src2,
874 (mem_frag addr:$src3)),
878 let AddedComplexity = 10 in // Prefer over the rrkz variant
879 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
880 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
881 !strconcat(OpcodeStr,
882 " \t{$src3, $src2, $dst {${mask}} {z}|"
883 "$dst {${mask}} {z}, $src2, $src3}"),
885 (OpVT (vselect KRC:$mask,
886 (OpNode RC:$src1, RC:$src2,
887 (mem_frag addr:$src3)),
889 (v16i32 immAllZerosV))))))]>,
893 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
894 i512mem, X86VPermiv3, v16i32, VK16WM>,
895 EVEX_V512, EVEX_CD8<32, CD8VF>;
896 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
897 i512mem, X86VPermiv3, v8i64, VK8WM>,
898 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
899 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
900 i512mem, X86VPermiv3, v16f32, VK16WM>,
901 EVEX_V512, EVEX_CD8<32, CD8VF>;
902 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
903 i512mem, X86VPermiv3, v8f64, VK8WM>,
904 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
906 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
907 PatFrag mem_frag, X86MemOperand x86memop,
908 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
909 ValueType MaskVT, RegisterClass MRC> :
910 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
912 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
913 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
914 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
916 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
917 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
918 (!cast<Instruction>(NAME#rrk) VR512:$src1,
919 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
922 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
923 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
924 EVEX_V512, EVEX_CD8<32, CD8VF>;
925 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
926 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
927 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
928 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
929 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
930 EVEX_V512, EVEX_CD8<32, CD8VF>;
931 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
932 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
933 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
935 //===----------------------------------------------------------------------===//
936 // AVX-512 - BLEND using mask
938 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
939 RegisterClass KRC, RegisterClass RC,
940 X86MemOperand x86memop, PatFrag mem_frag,
941 SDNode OpNode, ValueType vt> {
942 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
943 (ins KRC:$mask, RC:$src1, RC:$src2),
944 !strconcat(OpcodeStr,
945 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
946 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
947 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
949 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
950 (ins KRC:$mask, RC:$src1, x86memop:$src2),
951 !strconcat(OpcodeStr,
952 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
953 []>, EVEX_4V, EVEX_K;
956 let ExeDomain = SSEPackedSingle in
957 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
958 VK16WM, VR512, f512mem,
959 memopv16f32, vselect, v16f32>,
960 EVEX_CD8<32, CD8VF>, EVEX_V512;
961 let ExeDomain = SSEPackedDouble in
962 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
963 VK8WM, VR512, f512mem,
964 memopv8f64, vselect, v8f64>,
965 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
967 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
968 (v16f32 VR512:$src2), (i16 GR16:$mask))),
969 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
970 VR512:$src1, VR512:$src2)>;
972 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
973 (v8f64 VR512:$src2), (i8 GR8:$mask))),
974 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
975 VR512:$src1, VR512:$src2)>;
977 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
978 VK16WM, VR512, f512mem,
979 memopv16i32, vselect, v16i32>,
980 EVEX_CD8<32, CD8VF>, EVEX_V512;
982 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
983 VK8WM, VR512, f512mem,
984 memopv8i64, vselect, v8i64>,
985 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
987 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
988 (v16i32 VR512:$src2), (i16 GR16:$mask))),
989 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
990 VR512:$src1, VR512:$src2)>;
992 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
993 (v8i64 VR512:$src2), (i8 GR8:$mask))),
994 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
995 VR512:$src1, VR512:$src2)>;
997 let Predicates = [HasAVX512] in {
998 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
999 (v8f32 VR256X:$src2))),
1001 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1002 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1003 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1005 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1006 (v8i32 VR256X:$src2))),
1008 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1009 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1010 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1012 //===----------------------------------------------------------------------===//
1013 // Compare Instructions
1014 //===----------------------------------------------------------------------===//
1016 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1017 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1018 Operand CC, SDNode OpNode, ValueType VT,
1019 PatFrag ld_frag, string asm, string asm_alt> {
1020 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1021 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1022 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1023 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1024 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1025 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1026 [(set VK1:$dst, (OpNode (VT RC:$src1),
1027 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1028 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1029 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1030 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1031 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1032 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1033 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1034 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1038 let Predicates = [HasAVX512] in {
1039 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1040 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1041 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1043 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1044 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1045 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1049 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1050 X86VectorVTInfo _> {
1051 def rr : AVX512BI<opc, MRMSrcReg,
1052 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1054 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1055 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1057 def rm : AVX512BI<opc, MRMSrcMem,
1058 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1060 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1061 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1062 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1063 def rrk : AVX512BI<opc, MRMSrcReg,
1064 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1066 "$dst {${mask}}, $src1, $src2}"),
1067 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1068 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1069 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1071 def rmk : AVX512BI<opc, MRMSrcMem,
1072 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1073 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1074 "$dst {${mask}}, $src1, $src2}"),
1075 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1076 (OpNode (_.VT _.RC:$src1),
1078 (_.LdFrag addr:$src2))))))],
1079 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1082 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1083 X86VectorVTInfo _> :
1084 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1085 let mayLoad = 1 in {
1086 def rmb : AVX512BI<opc, MRMSrcMem,
1087 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1088 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1089 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1090 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1091 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1092 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1093 def rmbk : AVX512BI<opc, MRMSrcMem,
1094 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1095 _.ScalarMemOp:$src2),
1096 !strconcat(OpcodeStr,
1097 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1098 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1099 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1100 (OpNode (_.VT _.RC:$src1),
1102 (_.ScalarLdFrag addr:$src2)))))],
1103 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1107 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1108 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1109 let Predicates = [prd] in
1110 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1113 let Predicates = [prd, HasVLX] in {
1114 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1116 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1121 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1122 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1124 let Predicates = [prd] in
1125 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1128 let Predicates = [prd, HasVLX] in {
1129 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1131 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1136 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1137 avx512vl_i8_info, HasBWI>,
1140 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1141 avx512vl_i16_info, HasBWI>,
1142 EVEX_CD8<16, CD8VF>;
1144 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1145 avx512vl_i32_info, HasAVX512>,
1146 EVEX_CD8<32, CD8VF>;
1148 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1149 avx512vl_i64_info, HasAVX512>,
1150 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1152 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1153 avx512vl_i8_info, HasBWI>,
1156 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1157 avx512vl_i16_info, HasBWI>,
1158 EVEX_CD8<16, CD8VF>;
1160 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1161 avx512vl_i32_info, HasAVX512>,
1162 EVEX_CD8<32, CD8VF>;
1164 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1165 avx512vl_i64_info, HasAVX512>,
1166 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1168 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1169 (COPY_TO_REGCLASS (VPCMPGTDZrr
1170 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1171 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1173 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1174 (COPY_TO_REGCLASS (VPCMPEQDZrr
1175 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1176 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1178 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1179 X86VectorVTInfo _> {
1180 def rri : AVX512AIi8<opc, MRMSrcReg,
1181 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1182 !strconcat("vpcmp${cc}", Suffix,
1183 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1184 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1186 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1188 def rmi : AVX512AIi8<opc, MRMSrcMem,
1189 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1190 !strconcat("vpcmp${cc}", Suffix,
1191 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1192 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1193 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1195 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1196 def rrik : AVX512AIi8<opc, MRMSrcReg,
1197 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1199 !strconcat("vpcmp${cc}", Suffix,
1200 "\t{$src2, $src1, $dst {${mask}}|",
1201 "$dst {${mask}}, $src1, $src2}"),
1202 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1203 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1205 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1207 def rmik : AVX512AIi8<opc, MRMSrcMem,
1208 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1210 !strconcat("vpcmp${cc}", Suffix,
1211 "\t{$src2, $src1, $dst {${mask}}|",
1212 "$dst {${mask}}, $src1, $src2}"),
1213 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1214 (OpNode (_.VT _.RC:$src1),
1215 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1217 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1219 // Accept explicit immediate argument form instead of comparison code.
1220 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1221 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1222 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1223 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1224 "$dst, $src1, $src2, $cc}"),
1225 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1226 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1227 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1228 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1229 "$dst, $src1, $src2, $cc}"),
1230 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1231 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1232 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1234 !strconcat("vpcmp", Suffix,
1235 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1236 "$dst {${mask}}, $src1, $src2, $cc}"),
1237 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1238 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1239 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1241 !strconcat("vpcmp", Suffix,
1242 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1243 "$dst {${mask}}, $src1, $src2, $cc}"),
1244 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1248 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1249 X86VectorVTInfo _> :
1250 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1251 let mayLoad = 1 in {
1252 def rmib : AVX512AIi8<opc, MRMSrcMem,
1253 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1255 !strconcat("vpcmp${cc}", Suffix,
1256 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1257 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1258 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1259 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1261 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1262 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1263 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1264 _.ScalarMemOp:$src2, AVXCC:$cc),
1265 !strconcat("vpcmp${cc}", Suffix,
1266 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1267 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1268 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1269 (OpNode (_.VT _.RC:$src1),
1270 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1272 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1275 // Accept explicit immediate argument form instead of comparison code.
1276 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1277 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1278 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1280 !strconcat("vpcmp", Suffix,
1281 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1282 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1283 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1284 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1285 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1286 _.ScalarMemOp:$src2, i8imm:$cc),
1287 !strconcat("vpcmp", Suffix,
1288 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1289 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1290 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1294 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1295 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1296 let Predicates = [prd] in
1297 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1299 let Predicates = [prd, HasVLX] in {
1300 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1301 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1305 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1306 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1307 let Predicates = [prd] in
1308 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1311 let Predicates = [prd, HasVLX] in {
1312 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1314 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1319 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1320 HasBWI>, EVEX_CD8<8, CD8VF>;
1321 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1322 HasBWI>, EVEX_CD8<8, CD8VF>;
1324 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1325 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1326 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1327 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1329 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1330 HasAVX512>, EVEX_CD8<32, CD8VF>;
1331 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1332 HasAVX512>, EVEX_CD8<32, CD8VF>;
1334 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1335 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1336 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1337 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1339 // avx512_cmp_packed - compare packed instructions
1340 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1341 X86MemOperand x86memop, ValueType vt,
1342 string suffix, Domain d> {
1343 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1344 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1345 !strconcat("vcmp${cc}", suffix,
1346 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1347 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1348 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1349 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1350 !strconcat("vcmp${cc}", suffix,
1351 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1353 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1354 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1355 !strconcat("vcmp${cc}", suffix,
1356 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1358 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1360 // Accept explicit immediate argument form instead of comparison code.
1361 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1362 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1363 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1364 !strconcat("vcmp", suffix,
1365 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1366 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1367 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1368 !strconcat("vcmp", suffix,
1369 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1373 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1374 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1375 EVEX_CD8<32, CD8VF>;
1376 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1377 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1378 EVEX_CD8<64, CD8VF>;
1380 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1381 (COPY_TO_REGCLASS (VCMPPSZrri
1382 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1383 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1385 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1386 (COPY_TO_REGCLASS (VPCMPDZrri
1387 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1388 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1390 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1391 (COPY_TO_REGCLASS (VPCMPUDZrri
1392 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1393 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1396 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1397 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1399 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1400 (I8Imm imm:$cc)), GR16)>;
1402 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1403 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1405 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1406 (I8Imm imm:$cc)), GR8)>;
1408 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1409 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1411 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1412 (I8Imm imm:$cc)), GR16)>;
1414 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1415 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1417 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1418 (I8Imm imm:$cc)), GR8)>;
1420 // Mask register copy, including
1421 // - copy between mask registers
1422 // - load/store mask registers
1423 // - copy from GPR to mask register and vice versa
1425 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1426 string OpcodeStr, RegisterClass KRC,
1427 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1428 let hasSideEffects = 0 in {
1429 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1430 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1432 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1433 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1434 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1436 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1437 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1441 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1443 RegisterClass KRC, RegisterClass GRC> {
1444 let hasSideEffects = 0 in {
1445 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1446 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1447 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1452 let Predicates = [HasDQI] in
1453 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1455 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1458 let Predicates = [HasAVX512] in
1459 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1461 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1464 let Predicates = [HasBWI] in {
1465 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1466 i32mem>, VEX, PD, VEX_W;
1467 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1471 let Predicates = [HasBWI] in {
1472 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1473 i64mem>, VEX, PS, VEX_W;
1474 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1478 // GR from/to mask register
1479 let Predicates = [HasDQI] in {
1480 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1481 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1482 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1483 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1485 let Predicates = [HasAVX512] in {
1486 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1487 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1488 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1489 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1491 let Predicates = [HasBWI] in {
1492 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1493 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1495 let Predicates = [HasBWI] in {
1496 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1497 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1501 let Predicates = [HasDQI] in {
1502 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1503 (KMOVBmk addr:$dst, VK8:$src)>;
1505 let Predicates = [HasAVX512] in {
1506 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1507 (KMOVWmk addr:$dst, VK16:$src)>;
1508 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1509 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1510 def : Pat<(i1 (load addr:$src)),
1511 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1512 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1513 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1515 let Predicates = [HasBWI] in {
1516 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1517 (KMOVDmk addr:$dst, VK32:$src)>;
1519 let Predicates = [HasBWI] in {
1520 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1521 (KMOVQmk addr:$dst, VK64:$src)>;
1524 let Predicates = [HasAVX512] in {
1525 def : Pat<(i1 (trunc (i64 GR64:$src))),
1526 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1529 def : Pat<(i1 (trunc (i32 GR32:$src))),
1530 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1532 def : Pat<(i1 (trunc (i8 GR8:$src))),
1534 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1536 def : Pat<(i1 (trunc (i16 GR16:$src))),
1538 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1541 def : Pat<(i32 (zext VK1:$src)),
1542 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1543 def : Pat<(i8 (zext VK1:$src)),
1546 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1547 def : Pat<(i64 (zext VK1:$src)),
1548 (AND64ri8 (SUBREG_TO_REG (i64 0),
1549 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1550 def : Pat<(i16 (zext VK1:$src)),
1552 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1554 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1555 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1556 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1557 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1559 let Predicates = [HasBWI] in {
1560 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1561 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1562 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1563 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1567 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1568 let Predicates = [HasAVX512] in {
1569 // GR from/to 8-bit mask without native support
1570 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1572 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1574 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1576 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1579 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1580 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1581 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1582 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1584 let Predicates = [HasBWI] in {
1585 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1586 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1587 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1588 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1591 // Mask unary operation
1593 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1594 RegisterClass KRC, SDPatternOperator OpNode,
1596 let Predicates = [prd] in
1597 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1598 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1599 [(set KRC:$dst, (OpNode KRC:$src))]>;
1602 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1603 SDPatternOperator OpNode> {
1604 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1606 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1607 HasAVX512>, VEX, PS;
1608 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1609 HasBWI>, VEX, PD, VEX_W;
1610 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1611 HasBWI>, VEX, PS, VEX_W;
1614 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1616 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1617 let Predicates = [HasAVX512] in
1618 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1620 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1621 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1623 defm : avx512_mask_unop_int<"knot", "KNOT">;
1625 let Predicates = [HasDQI] in
1626 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1627 let Predicates = [HasAVX512] in
1628 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1629 let Predicates = [HasBWI] in
1630 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1631 let Predicates = [HasBWI] in
1632 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1634 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1635 let Predicates = [HasAVX512] in {
1636 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1637 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1639 def : Pat<(not VK8:$src),
1641 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1644 // Mask binary operation
1645 // - KAND, KANDN, KOR, KXNOR, KXOR
1646 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1647 RegisterClass KRC, SDPatternOperator OpNode,
1649 let Predicates = [prd] in
1650 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1651 !strconcat(OpcodeStr,
1652 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1653 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1656 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1657 SDPatternOperator OpNode> {
1658 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1659 HasDQI>, VEX_4V, VEX_L, PD;
1660 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1661 HasAVX512>, VEX_4V, VEX_L, PS;
1662 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1663 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1664 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1665 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1668 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1669 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1671 let isCommutable = 1 in {
1672 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1673 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1674 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1675 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1677 let isCommutable = 0 in
1678 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1680 def : Pat<(xor VK1:$src1, VK1:$src2),
1681 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1682 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1684 def : Pat<(or VK1:$src1, VK1:$src2),
1685 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1686 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1688 def : Pat<(and VK1:$src1, VK1:$src2),
1689 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1690 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1692 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1693 let Predicates = [HasAVX512] in
1694 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1695 (i16 GR16:$src1), (i16 GR16:$src2)),
1696 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1697 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1698 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1701 defm : avx512_mask_binop_int<"kand", "KAND">;
1702 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1703 defm : avx512_mask_binop_int<"kor", "KOR">;
1704 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1705 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1707 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1708 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1709 let Predicates = [HasAVX512] in
1710 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1712 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1713 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1716 defm : avx512_binop_pat<and, KANDWrr>;
1717 defm : avx512_binop_pat<andn, KANDNWrr>;
1718 defm : avx512_binop_pat<or, KORWrr>;
1719 defm : avx512_binop_pat<xnor, KXNORWrr>;
1720 defm : avx512_binop_pat<xor, KXORWrr>;
1723 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1724 RegisterClass KRC> {
1725 let Predicates = [HasAVX512] in
1726 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1727 !strconcat(OpcodeStr,
1728 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1731 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1732 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1736 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1737 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1738 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1739 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1742 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1743 let Predicates = [HasAVX512] in
1744 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1745 (i16 GR16:$src1), (i16 GR16:$src2)),
1746 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1747 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1748 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1750 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1753 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1755 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1756 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1757 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1758 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1761 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1762 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1766 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1768 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1769 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1770 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1773 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1775 let Predicates = [HasAVX512] in
1776 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1777 !strconcat(OpcodeStr,
1778 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1779 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1782 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1784 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1788 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1789 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1791 // Mask setting all 0s or 1s
1792 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1793 let Predicates = [HasAVX512] in
1794 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1795 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1796 [(set KRC:$dst, (VT Val))]>;
1799 multiclass avx512_mask_setop_w<PatFrag Val> {
1800 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1801 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1804 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1805 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1807 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1808 let Predicates = [HasAVX512] in {
1809 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1810 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1811 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1812 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1813 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1815 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1816 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1818 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1819 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1821 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1822 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1824 let Predicates = [HasVLX] in {
1825 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1826 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1827 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1828 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1829 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1830 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1831 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1832 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1835 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1836 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1838 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1839 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1840 //===----------------------------------------------------------------------===//
1841 // AVX-512 - Aligned and unaligned load and store
1844 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1845 RegisterClass KRC, RegisterClass RC,
1846 ValueType vt, ValueType zvt, X86MemOperand memop,
1847 Domain d, bit IsReMaterializable = 1> {
1848 let hasSideEffects = 0 in {
1849 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1850 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1852 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1853 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1854 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1856 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1857 SchedRW = [WriteLoad] in
1858 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1859 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1860 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1863 let AddedComplexity = 20 in {
1864 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1865 let hasSideEffects = 0 in
1866 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1867 (ins RC:$src0, KRC:$mask, RC:$src1),
1868 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1869 "${dst} {${mask}}, $src1}"),
1870 [(set RC:$dst, (vt (vselect KRC:$mask,
1874 let mayLoad = 1, SchedRW = [WriteLoad] in
1875 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1876 (ins RC:$src0, KRC:$mask, memop:$src1),
1877 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1878 "${dst} {${mask}}, $src1}"),
1881 (vt (bitconvert (ld_frag addr:$src1))),
1885 let mayLoad = 1, SchedRW = [WriteLoad] in
1886 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1887 (ins KRC:$mask, memop:$src),
1888 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1889 "${dst} {${mask}} {z}, $src}"),
1892 (vt (bitconvert (ld_frag addr:$src))),
1893 (vt (bitconvert (zvt immAllZerosV))))))],
1898 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1899 string elty, string elsz, string vsz512,
1900 string vsz256, string vsz128, Domain d,
1901 Predicate prd, bit IsReMaterializable = 1> {
1902 let Predicates = [prd] in
1903 defm Z : avx512_load<opc, OpcodeStr,
1904 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1905 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1906 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1907 !cast<X86MemOperand>(elty##"512mem"), d,
1908 IsReMaterializable>, EVEX_V512;
1910 let Predicates = [prd, HasVLX] in {
1911 defm Z256 : avx512_load<opc, OpcodeStr,
1912 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1913 "v"##vsz256##elty##elsz, "v4i64")),
1914 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1915 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1916 !cast<X86MemOperand>(elty##"256mem"), d,
1917 IsReMaterializable>, EVEX_V256;
1919 defm Z128 : avx512_load<opc, OpcodeStr,
1920 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1921 "v"##vsz128##elty##elsz, "v2i64")),
1922 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1923 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1924 !cast<X86MemOperand>(elty##"128mem"), d,
1925 IsReMaterializable>, EVEX_V128;
1930 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1931 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1932 X86MemOperand memop, Domain d> {
1933 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1934 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1935 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1937 let Constraints = "$src1 = $dst" in
1938 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1939 (ins RC:$src1, KRC:$mask, RC:$src2),
1940 !strconcat(OpcodeStr,
1941 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1943 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1944 (ins KRC:$mask, RC:$src),
1945 !strconcat(OpcodeStr,
1946 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1947 [], d>, EVEX, EVEX_KZ;
1949 let mayStore = 1 in {
1950 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1952 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1953 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1954 (ins memop:$dst, KRC:$mask, RC:$src),
1955 !strconcat(OpcodeStr,
1956 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1957 [], d>, EVEX, EVEX_K;
1962 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1963 string st_suff_512, string st_suff_256,
1964 string st_suff_128, string elty, string elsz,
1965 string vsz512, string vsz256, string vsz128,
1966 Domain d, Predicate prd> {
1967 let Predicates = [prd] in
1968 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1969 !cast<ValueType>("v"##vsz512##elty##elsz),
1970 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1971 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1973 let Predicates = [prd, HasVLX] in {
1974 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1975 !cast<ValueType>("v"##vsz256##elty##elsz),
1976 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1977 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1979 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1980 !cast<ValueType>("v"##vsz128##elty##elsz),
1981 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1982 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1986 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1987 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1988 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1989 "512", "256", "", "f", "32", "16", "8", "4",
1990 SSEPackedSingle, HasAVX512>,
1991 PS, EVEX_CD8<32, CD8VF>;
1993 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1994 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1995 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1996 "512", "256", "", "f", "64", "8", "4", "2",
1997 SSEPackedDouble, HasAVX512>,
1998 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2000 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2001 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2002 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2003 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2004 PS, EVEX_CD8<32, CD8VF>;
2006 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2007 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2008 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2009 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2010 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2012 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2013 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2014 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2016 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2017 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2018 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2020 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2022 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2024 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2026 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2029 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2030 "16", "8", "4", SSEPackedInt, HasAVX512>,
2031 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2032 "512", "256", "", "i", "32", "16", "8", "4",
2033 SSEPackedInt, HasAVX512>,
2034 PD, EVEX_CD8<32, CD8VF>;
2036 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2037 "8", "4", "2", SSEPackedInt, HasAVX512>,
2038 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2039 "512", "256", "", "i", "64", "8", "4", "2",
2040 SSEPackedInt, HasAVX512>,
2041 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2043 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2044 "64", "32", "16", SSEPackedInt, HasBWI>,
2045 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2046 "i", "8", "64", "32", "16", SSEPackedInt,
2047 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2049 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2050 "32", "16", "8", SSEPackedInt, HasBWI>,
2051 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2052 "i", "16", "32", "16", "8", SSEPackedInt,
2053 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2055 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2056 "16", "8", "4", SSEPackedInt, HasAVX512>,
2057 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2058 "i", "32", "16", "8", "4", SSEPackedInt,
2059 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2061 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2062 "8", "4", "2", SSEPackedInt, HasAVX512>,
2063 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2064 "i", "64", "8", "4", "2", SSEPackedInt,
2065 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2067 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2068 (v16i32 immAllZerosV), GR16:$mask)),
2069 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2071 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2072 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2073 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2075 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2077 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2079 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2081 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2084 let AddedComplexity = 20 in {
2085 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2086 (bc_v8i64 (v16i32 immAllZerosV)))),
2087 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2089 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2090 (v8i64 VR512:$src))),
2091 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2094 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2095 (v16i32 immAllZerosV))),
2096 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2098 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2099 (v16i32 VR512:$src))),
2100 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2103 // Move Int Doubleword to Packed Double Int
2105 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2106 "vmovd\t{$src, $dst|$dst, $src}",
2108 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2110 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2111 "vmovd\t{$src, $dst|$dst, $src}",
2113 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2114 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2115 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2116 "vmovq\t{$src, $dst|$dst, $src}",
2118 (v2i64 (scalar_to_vector GR64:$src)))],
2119 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2120 let isCodeGenOnly = 1 in {
2121 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2122 "vmovq\t{$src, $dst|$dst, $src}",
2123 [(set FR64:$dst, (bitconvert GR64:$src))],
2124 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2125 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2126 "vmovq\t{$src, $dst|$dst, $src}",
2127 [(set GR64:$dst, (bitconvert FR64:$src))],
2128 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2130 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2131 "vmovq\t{$src, $dst|$dst, $src}",
2132 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2133 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2134 EVEX_CD8<64, CD8VT1>;
2136 // Move Int Doubleword to Single Scalar
2138 let isCodeGenOnly = 1 in {
2139 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2140 "vmovd\t{$src, $dst|$dst, $src}",
2141 [(set FR32X:$dst, (bitconvert GR32:$src))],
2142 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2144 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2145 "vmovd\t{$src, $dst|$dst, $src}",
2146 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2147 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2150 // Move doubleword from xmm register to r/m32
2152 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2153 "vmovd\t{$src, $dst|$dst, $src}",
2154 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2155 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2157 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2158 (ins i32mem:$dst, VR128X:$src),
2159 "vmovd\t{$src, $dst|$dst, $src}",
2160 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2161 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2162 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2164 // Move quadword from xmm1 register to r/m64
2166 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2167 "vmovq\t{$src, $dst|$dst, $src}",
2168 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2170 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2171 Requires<[HasAVX512, In64BitMode]>;
2173 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2174 (ins i64mem:$dst, VR128X:$src),
2175 "vmovq\t{$src, $dst|$dst, $src}",
2176 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2177 addr:$dst)], IIC_SSE_MOVDQ>,
2178 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2179 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2181 // Move Scalar Single to Double Int
2183 let isCodeGenOnly = 1 in {
2184 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2186 "vmovd\t{$src, $dst|$dst, $src}",
2187 [(set GR32:$dst, (bitconvert FR32X:$src))],
2188 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2189 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2190 (ins i32mem:$dst, FR32X:$src),
2191 "vmovd\t{$src, $dst|$dst, $src}",
2192 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2193 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2196 // Move Quadword Int to Packed Quadword Int
2198 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2200 "vmovq\t{$src, $dst|$dst, $src}",
2202 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2203 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2205 //===----------------------------------------------------------------------===//
2206 // AVX-512 MOVSS, MOVSD
2207 //===----------------------------------------------------------------------===//
2209 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2210 SDNode OpNode, ValueType vt,
2211 X86MemOperand x86memop, PatFrag mem_pat> {
2212 let hasSideEffects = 0 in {
2213 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2214 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2215 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2216 (scalar_to_vector RC:$src2))))],
2217 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2218 let Constraints = "$src1 = $dst" in
2219 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2220 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2222 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2223 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2224 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2225 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2226 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2228 let mayStore = 1 in {
2229 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2230 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2231 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2233 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2234 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2235 [], IIC_SSE_MOV_S_MR>,
2236 EVEX, VEX_LIG, EVEX_K;
2238 } //hasSideEffects = 0
2241 let ExeDomain = SSEPackedSingle in
2242 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2243 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2245 let ExeDomain = SSEPackedDouble in
2246 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2247 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2249 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2250 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2251 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2253 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2254 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2255 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2257 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2258 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2259 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2261 // For the disassembler
2262 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2263 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2264 (ins VR128X:$src1, FR32X:$src2),
2265 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2267 XS, EVEX_4V, VEX_LIG;
2268 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2269 (ins VR128X:$src1, FR64X:$src2),
2270 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2272 XD, EVEX_4V, VEX_LIG, VEX_W;
2275 let Predicates = [HasAVX512] in {
2276 let AddedComplexity = 15 in {
2277 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2278 // MOVS{S,D} to the lower bits.
2279 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2280 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2281 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2282 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2283 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2284 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2285 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2286 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2288 // Move low f32 and clear high bits.
2289 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2290 (SUBREG_TO_REG (i32 0),
2291 (VMOVSSZrr (v4f32 (V_SET0)),
2292 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2293 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2294 (SUBREG_TO_REG (i32 0),
2295 (VMOVSSZrr (v4i32 (V_SET0)),
2296 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2299 let AddedComplexity = 20 in {
2300 // MOVSSrm zeros the high parts of the register; represent this
2301 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2302 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2303 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2304 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2305 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2306 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2307 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2309 // MOVSDrm zeros the high parts of the register; represent this
2310 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2311 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2312 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2313 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2314 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2315 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2316 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2317 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2318 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2319 def : Pat<(v2f64 (X86vzload addr:$src)),
2320 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2322 // Represent the same patterns above but in the form they appear for
2324 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2325 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2326 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2327 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2328 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2329 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2330 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2331 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2332 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2334 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2335 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2336 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2337 FR32X:$src)), sub_xmm)>;
2338 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2339 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2340 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2341 FR64X:$src)), sub_xmm)>;
2342 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2343 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2344 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2346 // Move low f64 and clear high bits.
2347 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2348 (SUBREG_TO_REG (i32 0),
2349 (VMOVSDZrr (v2f64 (V_SET0)),
2350 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2352 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2353 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2354 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2356 // Extract and store.
2357 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2359 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2360 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2362 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2364 // Shuffle with VMOVSS
2365 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2366 (VMOVSSZrr (v4i32 VR128X:$src1),
2367 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2368 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2369 (VMOVSSZrr (v4f32 VR128X:$src1),
2370 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2373 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2374 (SUBREG_TO_REG (i32 0),
2375 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2376 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2378 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2379 (SUBREG_TO_REG (i32 0),
2380 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2381 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2384 // Shuffle with VMOVSD
2385 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2386 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2387 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2388 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2389 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2390 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2391 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2392 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2395 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2396 (SUBREG_TO_REG (i32 0),
2397 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2398 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2400 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2401 (SUBREG_TO_REG (i32 0),
2402 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2403 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2406 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2407 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2408 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2409 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2410 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2411 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2412 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2413 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2416 let AddedComplexity = 15 in
2417 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2419 "vmovq\t{$src, $dst|$dst, $src}",
2420 [(set VR128X:$dst, (v2i64 (X86vzmovl
2421 (v2i64 VR128X:$src))))],
2422 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2424 let AddedComplexity = 20 in
2425 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2427 "vmovq\t{$src, $dst|$dst, $src}",
2428 [(set VR128X:$dst, (v2i64 (X86vzmovl
2429 (loadv2i64 addr:$src))))],
2430 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2431 EVEX_CD8<8, CD8VT8>;
2433 let Predicates = [HasAVX512] in {
2434 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2435 let AddedComplexity = 20 in {
2436 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2437 (VMOVDI2PDIZrm addr:$src)>;
2438 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2439 (VMOV64toPQIZrr GR64:$src)>;
2440 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2441 (VMOVDI2PDIZrr GR32:$src)>;
2443 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2444 (VMOVDI2PDIZrm addr:$src)>;
2445 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2446 (VMOVDI2PDIZrm addr:$src)>;
2447 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2448 (VMOVZPQILo2PQIZrm addr:$src)>;
2449 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2450 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2451 def : Pat<(v2i64 (X86vzload addr:$src)),
2452 (VMOVZPQILo2PQIZrm addr:$src)>;
2455 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2456 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2457 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2458 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2459 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2460 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2461 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2464 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2465 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2467 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2468 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2470 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2471 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2473 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2474 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2476 //===----------------------------------------------------------------------===//
2477 // AVX-512 - Non-temporals
2478 //===----------------------------------------------------------------------===//
2479 let SchedRW = [WriteLoad] in {
2480 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2481 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2482 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2483 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2484 EVEX_CD8<64, CD8VF>;
2486 let Predicates = [HasAVX512, HasVLX] in {
2487 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2489 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2490 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2491 EVEX_CD8<64, CD8VF>;
2493 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2495 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2496 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2497 EVEX_CD8<64, CD8VF>;
2501 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2502 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2503 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2504 let SchedRW = [WriteStore], mayStore = 1,
2505 AddedComplexity = 400 in
2506 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2507 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2508 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2511 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2512 string elty, string elsz, string vsz512,
2513 string vsz256, string vsz128, Domain d,
2514 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2515 let Predicates = [prd] in
2516 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2517 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2518 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2521 let Predicates = [prd, HasVLX] in {
2522 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2523 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2524 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2527 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2528 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2529 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2534 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2535 "i", "64", "8", "4", "2", SSEPackedInt,
2536 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2538 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2539 "f", "64", "8", "4", "2", SSEPackedDouble,
2540 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2542 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2543 "f", "32", "16", "8", "4", SSEPackedSingle,
2544 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2546 //===----------------------------------------------------------------------===//
2547 // AVX-512 - Integer arithmetic
2549 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2550 X86VectorVTInfo _, OpndItins itins,
2551 bit IsCommutable = 0> {
2552 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2553 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2554 "$src2, $src1", "$src1, $src2",
2555 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2556 itins.rr, IsCommutable>,
2557 AVX512BIBase, EVEX_4V;
2560 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2561 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2562 "$src2, $src1", "$src1, $src2",
2563 (_.VT (OpNode _.RC:$src1,
2564 (bitconvert (_.LdFrag addr:$src2)))),
2566 AVX512BIBase, EVEX_4V;
2569 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2570 X86VectorVTInfo _, OpndItins itins,
2571 bit IsCommutable = 0> :
2572 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2574 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2575 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2576 "${src2}"##_.BroadcastStr##", $src1",
2577 "$src1, ${src2}"##_.BroadcastStr,
2578 (_.VT (OpNode _.RC:$src1,
2580 (_.ScalarLdFrag addr:$src2)))),
2582 AVX512BIBase, EVEX_4V, EVEX_B;
2585 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2586 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2587 Predicate prd, bit IsCommutable = 0> {
2588 let Predicates = [prd] in
2589 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2590 IsCommutable>, EVEX_V512;
2592 let Predicates = [prd, HasVLX] in {
2593 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2594 IsCommutable>, EVEX_V256;
2595 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2596 IsCommutable>, EVEX_V128;
2600 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2601 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2602 Predicate prd, bit IsCommutable = 0> {
2603 let Predicates = [prd] in
2604 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2605 IsCommutable>, EVEX_V512;
2607 let Predicates = [prd, HasVLX] in {
2608 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2609 IsCommutable>, EVEX_V256;
2610 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2611 IsCommutable>, EVEX_V128;
2615 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2616 OpndItins itins, Predicate prd,
2617 bit IsCommutable = 0> {
2618 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2619 itins, prd, IsCommutable>,
2620 VEX_W, EVEX_CD8<64, CD8VF>;
2623 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2624 OpndItins itins, Predicate prd,
2625 bit IsCommutable = 0> {
2626 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2627 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2630 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2631 OpndItins itins, Predicate prd,
2632 bit IsCommutable = 0> {
2633 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2634 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2637 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2638 OpndItins itins, Predicate prd,
2639 bit IsCommutable = 0> {
2640 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2641 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2644 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2645 SDNode OpNode, OpndItins itins, Predicate prd,
2646 bit IsCommutable = 0> {
2647 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2650 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2654 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2655 SDNode OpNode, OpndItins itins, Predicate prd,
2656 bit IsCommutable = 0> {
2657 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2660 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2664 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2665 bits<8> opc_d, bits<8> opc_q,
2666 string OpcodeStr, SDNode OpNode,
2667 OpndItins itins, bit IsCommutable = 0> {
2668 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2669 itins, HasAVX512, IsCommutable>,
2670 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2671 itins, HasBWI, IsCommutable>;
2674 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2675 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2676 PatFrag memop_frag, X86MemOperand x86memop,
2677 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2678 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2679 let isCommutable = IsCommutable in
2681 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2682 (ins RC:$src1, RC:$src2),
2683 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2685 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2686 (ins KRC:$mask, RC:$src1, RC:$src2),
2687 !strconcat(OpcodeStr,
2688 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2689 [], itins.rr>, EVEX_4V, EVEX_K;
2690 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2691 (ins KRC:$mask, RC:$src1, RC:$src2),
2692 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2693 "|$dst {${mask}} {z}, $src1, $src2}"),
2694 [], itins.rr>, EVEX_4V, EVEX_KZ;
2696 let mayLoad = 1 in {
2697 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2698 (ins RC:$src1, x86memop:$src2),
2699 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2701 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2702 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2703 !strconcat(OpcodeStr,
2704 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2705 [], itins.rm>, EVEX_4V, EVEX_K;
2706 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2707 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2708 !strconcat(OpcodeStr,
2709 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2710 [], itins.rm>, EVEX_4V, EVEX_KZ;
2711 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2712 (ins RC:$src1, x86scalar_mop:$src2),
2713 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2714 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2715 [], itins.rm>, EVEX_4V, EVEX_B;
2716 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2717 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2718 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2719 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2721 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2722 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2723 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2724 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2725 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2727 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2731 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2732 SSE_INTALU_ITINS_P, 1>;
2733 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2734 SSE_INTALU_ITINS_P, 0>;
2735 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2736 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2737 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2738 SSE_INTALU_ITINS_P, HasBWI, 1>;
2739 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2740 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2742 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2743 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2744 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2745 EVEX_CD8<64, CD8VF>, VEX_W;
2747 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2748 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2749 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2751 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2752 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2754 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2755 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2756 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2757 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2758 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2759 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2761 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2762 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2763 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2764 SSE_INTALU_ITINS_P, HasBWI, 1>;
2765 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2766 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2768 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2769 SSE_INTALU_ITINS_P, HasBWI, 1>;
2770 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2771 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2772 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2773 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2775 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2776 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2777 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2778 SSE_INTALU_ITINS_P, HasBWI, 1>;
2779 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2780 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2782 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2783 SSE_INTALU_ITINS_P, HasBWI, 1>;
2784 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2785 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2786 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2787 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2789 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2790 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2791 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2792 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2793 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2794 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2795 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2796 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2797 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2798 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2799 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2800 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2801 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2802 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2803 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2804 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2805 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2806 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2807 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2808 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2809 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2810 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2811 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2812 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2813 //===----------------------------------------------------------------------===//
2814 // AVX-512 - Unpack Instructions
2815 //===----------------------------------------------------------------------===//
2817 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2818 PatFrag mem_frag, RegisterClass RC,
2819 X86MemOperand x86memop, string asm,
2821 def rr : AVX512PI<opc, MRMSrcReg,
2822 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2824 (vt (OpNode RC:$src1, RC:$src2)))],
2826 def rm : AVX512PI<opc, MRMSrcMem,
2827 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2829 (vt (OpNode RC:$src1,
2830 (bitconvert (mem_frag addr:$src2)))))],
2834 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2835 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2836 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2837 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2838 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2839 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2840 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2841 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2842 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2843 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2844 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2845 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2847 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2848 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2849 X86MemOperand x86memop> {
2850 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2851 (ins RC:$src1, RC:$src2),
2852 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2853 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2854 IIC_SSE_UNPCK>, EVEX_4V;
2855 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2856 (ins RC:$src1, x86memop:$src2),
2857 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2858 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2859 (bitconvert (memop_frag addr:$src2)))))],
2860 IIC_SSE_UNPCK>, EVEX_4V;
2862 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2863 VR512, memopv16i32, i512mem>, EVEX_V512,
2864 EVEX_CD8<32, CD8VF>;
2865 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2866 VR512, memopv8i64, i512mem>, EVEX_V512,
2867 VEX_W, EVEX_CD8<64, CD8VF>;
2868 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2869 VR512, memopv16i32, i512mem>, EVEX_V512,
2870 EVEX_CD8<32, CD8VF>;
2871 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2872 VR512, memopv8i64, i512mem>, EVEX_V512,
2873 VEX_W, EVEX_CD8<64, CD8VF>;
2874 //===----------------------------------------------------------------------===//
2878 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2879 SDNode OpNode, PatFrag mem_frag,
2880 X86MemOperand x86memop, ValueType OpVT> {
2881 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2882 (ins RC:$src1, i8imm:$src2),
2883 !strconcat(OpcodeStr,
2884 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2886 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2888 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2889 (ins x86memop:$src1, i8imm:$src2),
2890 !strconcat(OpcodeStr,
2891 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2893 (OpVT (OpNode (mem_frag addr:$src1),
2894 (i8 imm:$src2))))]>, EVEX;
2897 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2898 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2900 let ExeDomain = SSEPackedSingle in
2901 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2902 memopv16f32, f512mem, v16f32>, TAPD, EVEX_V512,
2903 EVEX_CD8<32, CD8VF>;
2904 let ExeDomain = SSEPackedDouble in
2905 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2906 memopv8f64, f512mem, v8f64>, TAPD, EVEX_V512,
2907 VEX_W, EVEX_CD8<64, CD8VF>;
2909 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2910 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2911 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2912 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2914 //===----------------------------------------------------------------------===//
2915 // AVX-512 Logical Instructions
2916 //===----------------------------------------------------------------------===//
2918 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2919 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2920 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2921 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2922 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2923 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2924 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2925 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2927 //===----------------------------------------------------------------------===//
2928 // AVX-512 FP arithmetic
2929 //===----------------------------------------------------------------------===//
2931 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2933 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2934 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2935 EVEX_CD8<32, CD8VT1>;
2936 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2937 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2938 EVEX_CD8<64, CD8VT1>;
2941 let isCommutable = 1 in {
2942 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2943 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2944 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2945 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2947 let isCommutable = 0 in {
2948 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2949 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2952 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2954 RegisterClass RC, ValueType vt,
2955 X86MemOperand x86memop, PatFrag mem_frag,
2956 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2958 Domain d, OpndItins itins, bit commutable> {
2959 let isCommutable = commutable in {
2960 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2961 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2962 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2965 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2966 !strconcat(OpcodeStr,
2967 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2968 [], itins.rr, d>, EVEX_4V, EVEX_K;
2970 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2971 !strconcat(OpcodeStr,
2972 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2973 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2976 let mayLoad = 1 in {
2977 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2978 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2979 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2980 itins.rm, d>, EVEX_4V;
2982 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2983 (ins RC:$src1, x86scalar_mop:$src2),
2984 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2985 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2986 [(set RC:$dst, (OpNode RC:$src1,
2987 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2988 itins.rm, d>, EVEX_4V, EVEX_B;
2990 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2991 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2992 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2993 [], itins.rm, d>, EVEX_4V, EVEX_K;
2995 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2996 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2997 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2998 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
3000 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
3001 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3002 " \t{${src2}", BrdcstStr,
3003 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
3004 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
3006 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
3007 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3008 " \t{${src2}", BrdcstStr,
3009 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3011 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
3015 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
3016 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3017 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3019 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
3020 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3021 SSE_ALU_ITINS_P.d, 1>,
3022 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3024 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
3025 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3026 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3027 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
3028 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3029 SSE_ALU_ITINS_P.d, 1>,
3030 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3032 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
3033 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3034 SSE_ALU_ITINS_P.s, 1>,
3035 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3036 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
3037 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3038 SSE_ALU_ITINS_P.s, 1>,
3039 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3041 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
3042 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3043 SSE_ALU_ITINS_P.d, 1>,
3044 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3045 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
3046 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3047 SSE_ALU_ITINS_P.d, 1>,
3048 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3050 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
3051 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3052 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3053 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
3054 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3055 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3057 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
3058 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3059 SSE_ALU_ITINS_P.d, 0>,
3060 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3061 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
3062 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3063 SSE_ALU_ITINS_P.d, 0>,
3064 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3066 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3067 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3068 (i16 -1), FROUND_CURRENT)),
3069 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3071 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3072 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3073 (i8 -1), FROUND_CURRENT)),
3074 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3076 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3077 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3078 (i16 -1), FROUND_CURRENT)),
3079 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3081 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3082 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3083 (i8 -1), FROUND_CURRENT)),
3084 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3085 //===----------------------------------------------------------------------===//
3086 // AVX-512 VPTESTM instructions
3087 //===----------------------------------------------------------------------===//
3089 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3090 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3091 SDNode OpNode, ValueType vt> {
3092 def rr : AVX512PI<opc, MRMSrcReg,
3093 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3094 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3095 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3096 SSEPackedInt>, EVEX_4V;
3097 def rm : AVX512PI<opc, MRMSrcMem,
3098 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3099 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3100 [(set KRC:$dst, (OpNode (vt RC:$src1),
3101 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3104 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3105 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3106 EVEX_CD8<32, CD8VF>;
3107 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3108 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3109 EVEX_CD8<64, CD8VF>;
3111 let Predicates = [HasCDI] in {
3112 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3113 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3114 EVEX_CD8<32, CD8VF>;
3115 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3116 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3117 EVEX_CD8<64, CD8VF>;
3120 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3121 (v16i32 VR512:$src2), (i16 -1))),
3122 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3124 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3125 (v8i64 VR512:$src2), (i8 -1))),
3126 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3127 //===----------------------------------------------------------------------===//
3128 // AVX-512 Shift instructions
3129 //===----------------------------------------------------------------------===//
3130 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3131 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3132 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3133 RegisterClass KRC> {
3134 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3135 (ins RC:$src1, i8imm:$src2),
3136 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3137 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
3138 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3139 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3140 (ins KRC:$mask, RC:$src1, i8imm:$src2),
3141 !strconcat(OpcodeStr,
3142 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3143 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3144 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3145 (ins x86memop:$src1, i8imm:$src2),
3146 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3147 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
3148 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3149 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3150 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
3151 !strconcat(OpcodeStr,
3152 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3153 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3156 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3157 RegisterClass RC, ValueType vt, ValueType SrcVT,
3158 PatFrag bc_frag, RegisterClass KRC> {
3159 // src2 is always 128-bit
3160 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3161 (ins RC:$src1, VR128X:$src2),
3162 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3163 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3164 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3165 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3166 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3167 !strconcat(OpcodeStr,
3168 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3169 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3170 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3171 (ins RC:$src1, i128mem:$src2),
3172 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3173 [(set RC:$dst, (vt (OpNode RC:$src1,
3174 (bc_frag (memopv2i64 addr:$src2)))))],
3175 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3176 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3177 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3178 !strconcat(OpcodeStr,
3179 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3180 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3183 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3184 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3185 EVEX_V512, EVEX_CD8<32, CD8VF>;
3186 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3187 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3188 EVEX_CD8<32, CD8VQ>;
3190 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3191 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3192 EVEX_CD8<64, CD8VF>, VEX_W;
3193 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3194 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3195 EVEX_CD8<64, CD8VQ>, VEX_W;
3197 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3198 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3199 EVEX_CD8<32, CD8VF>;
3200 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3201 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3202 EVEX_CD8<32, CD8VQ>;
3204 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3205 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3206 EVEX_CD8<64, CD8VF>, VEX_W;
3207 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3208 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3209 EVEX_CD8<64, CD8VQ>, VEX_W;
3211 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3212 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3213 EVEX_V512, EVEX_CD8<32, CD8VF>;
3214 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3215 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3216 EVEX_CD8<32, CD8VQ>;
3218 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3219 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3220 EVEX_CD8<64, CD8VF>, VEX_W;
3221 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3222 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3223 EVEX_CD8<64, CD8VQ>, VEX_W;
3225 //===-------------------------------------------------------------------===//
3226 // Variable Bit Shifts
3227 //===-------------------------------------------------------------------===//
3228 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3229 RegisterClass RC, ValueType vt,
3230 X86MemOperand x86memop, PatFrag mem_frag> {
3231 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3232 (ins RC:$src1, RC:$src2),
3233 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3235 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3237 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3238 (ins RC:$src1, x86memop:$src2),
3239 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3241 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3245 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3246 i512mem, memopv16i32>, EVEX_V512,
3247 EVEX_CD8<32, CD8VF>;
3248 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3249 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3250 EVEX_CD8<64, CD8VF>;
3251 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3252 i512mem, memopv16i32>, EVEX_V512,
3253 EVEX_CD8<32, CD8VF>;
3254 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3255 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3256 EVEX_CD8<64, CD8VF>;
3257 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3258 i512mem, memopv16i32>, EVEX_V512,
3259 EVEX_CD8<32, CD8VF>;
3260 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3261 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3262 EVEX_CD8<64, CD8VF>;
3264 //===----------------------------------------------------------------------===//
3265 // AVX-512 - MOVDDUP
3266 //===----------------------------------------------------------------------===//
3268 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3269 X86MemOperand x86memop, PatFrag memop_frag> {
3270 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3271 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3272 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3273 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3274 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3276 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3279 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3280 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3281 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3282 (VMOVDDUPZrm addr:$src)>;
3284 //===---------------------------------------------------------------------===//
3285 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3286 //===---------------------------------------------------------------------===//
3287 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3288 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3289 X86MemOperand x86memop> {
3290 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3291 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3292 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3294 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3295 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3296 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3299 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3300 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3301 EVEX_CD8<32, CD8VF>;
3302 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3303 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3304 EVEX_CD8<32, CD8VF>;
3306 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3307 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3308 (VMOVSHDUPZrm addr:$src)>;
3309 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3310 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3311 (VMOVSLDUPZrm addr:$src)>;
3313 //===----------------------------------------------------------------------===//
3314 // Move Low to High and High to Low packed FP Instructions
3315 //===----------------------------------------------------------------------===//
3316 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3317 (ins VR128X:$src1, VR128X:$src2),
3318 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3319 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3320 IIC_SSE_MOV_LH>, EVEX_4V;
3321 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3322 (ins VR128X:$src1, VR128X:$src2),
3323 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3324 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3325 IIC_SSE_MOV_LH>, EVEX_4V;
3327 let Predicates = [HasAVX512] in {
3329 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3330 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3331 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3332 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3335 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3336 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3339 //===----------------------------------------------------------------------===//
3340 // FMA - Fused Multiply Operations
3343 let Constraints = "$src1 = $dst" in {
3344 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3345 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3346 SDPatternOperator OpNode = null_frag> {
3347 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3348 (ins _.RC:$src2, _.RC:$src3),
3349 OpcodeStr, "$src3, $src2", "$src2, $src3",
3350 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3354 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3355 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3356 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3357 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3358 (_.MemOpFrag addr:$src3))))]>;
3359 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3360 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3361 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3362 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3363 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3364 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3366 } // Constraints = "$src1 = $dst"
3368 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3369 string OpcodeStr, X86VectorVTInfo VTI,
3370 SDPatternOperator OpNode> {
3371 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3373 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3375 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3377 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3380 let ExeDomain = SSEPackedSingle in {
3381 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3382 v16f32_info, X86Fmadd>;
3383 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3384 v16f32_info, X86Fmsub>;
3385 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3386 v16f32_info, X86Fmaddsub>;
3387 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3388 v16f32_info, X86Fmsubadd>;
3389 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3390 v16f32_info, X86Fnmadd>;
3391 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3392 v16f32_info, X86Fnmsub>;
3394 let ExeDomain = SSEPackedDouble in {
3395 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3396 v8f64_info, X86Fmadd>, VEX_W;
3397 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3398 v8f64_info, X86Fmsub>, VEX_W;
3399 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3400 v8f64_info, X86Fmaddsub>, VEX_W;
3401 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3402 v8f64_info, X86Fmsubadd>, VEX_W;
3403 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3404 v8f64_info, X86Fnmadd>, VEX_W;
3405 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3406 v8f64_info, X86Fnmsub>, VEX_W;
3409 let Constraints = "$src1 = $dst" in {
3410 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3411 X86VectorVTInfo _> {
3413 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3414 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3415 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3416 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3418 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3419 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3420 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3421 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3423 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3424 (_.ScalarLdFrag addr:$src2))),
3425 _.RC:$src3))]>, EVEX_B;
3427 } // Constraints = "$src1 = $dst"
3430 let ExeDomain = SSEPackedSingle in {
3431 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3433 EVEX_V512, EVEX_CD8<32, CD8VF>;
3434 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3436 EVEX_V512, EVEX_CD8<32, CD8VF>;
3437 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3439 EVEX_V512, EVEX_CD8<32, CD8VF>;
3440 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3442 EVEX_V512, EVEX_CD8<32, CD8VF>;
3443 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3445 EVEX_V512, EVEX_CD8<32, CD8VF>;
3446 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3448 EVEX_V512, EVEX_CD8<32, CD8VF>;
3450 let ExeDomain = SSEPackedDouble in {
3451 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3453 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3454 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3456 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3457 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3459 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3460 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3462 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3463 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3465 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3466 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3468 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3472 let Constraints = "$src1 = $dst" in {
3473 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3474 RegisterClass RC, ValueType OpVT,
3475 X86MemOperand x86memop, Operand memop,
3477 let isCommutable = 1 in
3478 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3479 (ins RC:$src1, RC:$src2, RC:$src3),
3480 !strconcat(OpcodeStr,
3481 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3483 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3485 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3486 (ins RC:$src1, RC:$src2, f128mem:$src3),
3487 !strconcat(OpcodeStr,
3488 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3490 (OpVT (OpNode RC:$src2, RC:$src1,
3491 (mem_frag addr:$src3))))]>;
3494 } // Constraints = "$src1 = $dst"
3496 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3497 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3498 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3499 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3500 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3501 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3502 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3503 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3504 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3505 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3506 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3507 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3508 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3509 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3510 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3511 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3513 //===----------------------------------------------------------------------===//
3514 // AVX-512 Scalar convert from sign integer to float/double
3515 //===----------------------------------------------------------------------===//
3517 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3518 X86MemOperand x86memop, string asm> {
3519 let hasSideEffects = 0 in {
3520 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3521 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3524 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3525 (ins DstRC:$src1, x86memop:$src),
3526 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3528 } // hasSideEffects = 0
3530 let Predicates = [HasAVX512] in {
3531 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3532 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3533 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3534 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3535 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3536 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3537 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3538 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3540 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3541 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3542 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3543 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3544 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3545 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3546 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3547 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3549 def : Pat<(f32 (sint_to_fp GR32:$src)),
3550 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3551 def : Pat<(f32 (sint_to_fp GR64:$src)),
3552 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3553 def : Pat<(f64 (sint_to_fp GR32:$src)),
3554 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3555 def : Pat<(f64 (sint_to_fp GR64:$src)),
3556 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3558 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3559 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3560 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3561 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3562 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3563 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3564 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3565 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3567 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3568 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3569 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3570 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3571 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3572 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3573 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3574 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3576 def : Pat<(f32 (uint_to_fp GR32:$src)),
3577 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3578 def : Pat<(f32 (uint_to_fp GR64:$src)),
3579 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3580 def : Pat<(f64 (uint_to_fp GR32:$src)),
3581 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3582 def : Pat<(f64 (uint_to_fp GR64:$src)),
3583 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3586 //===----------------------------------------------------------------------===//
3587 // AVX-512 Scalar convert from float/double to integer
3588 //===----------------------------------------------------------------------===//
3589 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3590 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3592 let hasSideEffects = 0 in {
3593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3594 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3595 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3596 Requires<[HasAVX512]>;
3598 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3599 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3600 Requires<[HasAVX512]>;
3601 } // hasSideEffects = 0
3603 let Predicates = [HasAVX512] in {
3604 // Convert float/double to signed/unsigned int 32/64
3605 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3606 ssmem, sse_load_f32, "cvtss2si">,
3607 XS, EVEX_CD8<32, CD8VT1>;
3608 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3609 ssmem, sse_load_f32, "cvtss2si">,
3610 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3611 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3612 ssmem, sse_load_f32, "cvtss2usi">,
3613 XS, EVEX_CD8<32, CD8VT1>;
3614 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3615 int_x86_avx512_cvtss2usi64, ssmem,
3616 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3617 EVEX_CD8<32, CD8VT1>;
3618 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3619 sdmem, sse_load_f64, "cvtsd2si">,
3620 XD, EVEX_CD8<64, CD8VT1>;
3621 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3622 sdmem, sse_load_f64, "cvtsd2si">,
3623 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3624 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3625 sdmem, sse_load_f64, "cvtsd2usi">,
3626 XD, EVEX_CD8<64, CD8VT1>;
3627 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3628 int_x86_avx512_cvtsd2usi64, sdmem,
3629 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3630 EVEX_CD8<64, CD8VT1>;
3632 let isCodeGenOnly = 1 in {
3633 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3634 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3635 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3636 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3637 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3638 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3639 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3640 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3641 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3642 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3643 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3644 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3646 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3647 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3648 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3649 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3650 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3651 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3652 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3653 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3654 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3655 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3656 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3657 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3658 } // isCodeGenOnly = 1
3660 // Convert float/double to signed/unsigned int 32/64 with truncation
3661 let isCodeGenOnly = 1 in {
3662 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3663 ssmem, sse_load_f32, "cvttss2si">,
3664 XS, EVEX_CD8<32, CD8VT1>;
3665 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3666 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3667 "cvttss2si">, XS, VEX_W,
3668 EVEX_CD8<32, CD8VT1>;
3669 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3670 sdmem, sse_load_f64, "cvttsd2si">, XD,
3671 EVEX_CD8<64, CD8VT1>;
3672 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3673 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3674 "cvttsd2si">, XD, VEX_W,
3675 EVEX_CD8<64, CD8VT1>;
3676 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3677 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3678 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3679 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3680 int_x86_avx512_cvttss2usi64, ssmem,
3681 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3682 EVEX_CD8<32, CD8VT1>;
3683 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3684 int_x86_avx512_cvttsd2usi,
3685 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3686 EVEX_CD8<64, CD8VT1>;
3687 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3688 int_x86_avx512_cvttsd2usi64, sdmem,
3689 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3690 EVEX_CD8<64, CD8VT1>;
3691 } // isCodeGenOnly = 1
3693 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3694 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3696 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3697 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3698 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3699 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3700 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3701 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3704 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3705 loadf32, "cvttss2si">, XS,
3706 EVEX_CD8<32, CD8VT1>;
3707 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3708 loadf32, "cvttss2usi">, XS,
3709 EVEX_CD8<32, CD8VT1>;
3710 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3711 loadf32, "cvttss2si">, XS, VEX_W,
3712 EVEX_CD8<32, CD8VT1>;
3713 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3714 loadf32, "cvttss2usi">, XS, VEX_W,
3715 EVEX_CD8<32, CD8VT1>;
3716 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3717 loadf64, "cvttsd2si">, XD,
3718 EVEX_CD8<64, CD8VT1>;
3719 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3720 loadf64, "cvttsd2usi">, XD,
3721 EVEX_CD8<64, CD8VT1>;
3722 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3723 loadf64, "cvttsd2si">, XD, VEX_W,
3724 EVEX_CD8<64, CD8VT1>;
3725 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3726 loadf64, "cvttsd2usi">, XD, VEX_W,
3727 EVEX_CD8<64, CD8VT1>;
3729 //===----------------------------------------------------------------------===//
3730 // AVX-512 Convert form float to double and back
3731 //===----------------------------------------------------------------------===//
3732 let hasSideEffects = 0 in {
3733 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3734 (ins FR32X:$src1, FR32X:$src2),
3735 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3736 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3738 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3739 (ins FR32X:$src1, f32mem:$src2),
3740 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3741 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3742 EVEX_CD8<32, CD8VT1>;
3744 // Convert scalar double to scalar single
3745 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3746 (ins FR64X:$src1, FR64X:$src2),
3747 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3748 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3750 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3751 (ins FR64X:$src1, f64mem:$src2),
3752 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3753 []>, EVEX_4V, VEX_LIG, VEX_W,
3754 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3757 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3758 Requires<[HasAVX512]>;
3759 def : Pat<(fextend (loadf32 addr:$src)),
3760 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3762 def : Pat<(extloadf32 addr:$src),
3763 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3764 Requires<[HasAVX512, OptForSize]>;
3766 def : Pat<(extloadf32 addr:$src),
3767 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3768 Requires<[HasAVX512, OptForSpeed]>;
3770 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3771 Requires<[HasAVX512]>;
3773 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3774 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3775 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3777 let hasSideEffects = 0 in {
3778 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3779 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3781 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3782 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3783 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3784 [], d>, EVEX, EVEX_B, EVEX_RC;
3786 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3787 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3789 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3790 } // hasSideEffects = 0
3793 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3794 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3795 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3797 let hasSideEffects = 0 in {
3798 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3799 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3801 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3803 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3804 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3806 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3807 } // hasSideEffects = 0
3810 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3811 memopv8f64, f512mem, v8f32, v8f64,
3812 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3813 EVEX_CD8<64, CD8VF>;
3815 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3816 memopv4f64, f256mem, v8f64, v8f32,
3817 SSEPackedDouble>, EVEX_V512, PS,
3818 EVEX_CD8<32, CD8VH>;
3819 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3820 (VCVTPS2PDZrm addr:$src)>;
3822 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3823 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3824 (VCVTPD2PSZrr VR512:$src)>;
3826 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3827 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3828 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3830 //===----------------------------------------------------------------------===//
3831 // AVX-512 Vector convert from sign integer to float/double
3832 //===----------------------------------------------------------------------===//
3834 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3835 memopv8i64, i512mem, v16f32, v16i32,
3836 SSEPackedSingle>, EVEX_V512, PS,
3837 EVEX_CD8<32, CD8VF>;
3839 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3840 memopv4i64, i256mem, v8f64, v8i32,
3841 SSEPackedDouble>, EVEX_V512, XS,
3842 EVEX_CD8<32, CD8VH>;
3844 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3845 memopv16f32, f512mem, v16i32, v16f32,
3846 SSEPackedSingle>, EVEX_V512, XS,
3847 EVEX_CD8<32, CD8VF>;
3849 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3850 memopv8f64, f512mem, v8i32, v8f64,
3851 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3852 EVEX_CD8<64, CD8VF>;
3854 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3855 memopv16f32, f512mem, v16i32, v16f32,
3856 SSEPackedSingle>, EVEX_V512, PS,
3857 EVEX_CD8<32, CD8VF>;
3859 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3860 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3861 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3862 (VCVTTPS2UDQZrr VR512:$src)>;
3864 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3865 memopv8f64, f512mem, v8i32, v8f64,
3866 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3867 EVEX_CD8<64, CD8VF>;
3869 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3870 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3871 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3872 (VCVTTPD2UDQZrr VR512:$src)>;
3874 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3875 memopv4i64, f256mem, v8f64, v8i32,
3876 SSEPackedDouble>, EVEX_V512, XS,
3877 EVEX_CD8<32, CD8VH>;
3879 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3880 memopv16i32, f512mem, v16f32, v16i32,
3881 SSEPackedSingle>, EVEX_V512, XD,
3882 EVEX_CD8<32, CD8VF>;
3884 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3885 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3886 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3888 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3889 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3890 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3892 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3893 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3894 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3896 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3897 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3898 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3900 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3901 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3902 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3904 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3905 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3906 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3907 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3908 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3909 (VCVTDQ2PDZrr VR256X:$src)>;
3910 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3911 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3912 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3913 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3914 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3915 (VCVTUDQ2PDZrr VR256X:$src)>;
3917 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3918 RegisterClass DstRC, PatFrag mem_frag,
3919 X86MemOperand x86memop, Domain d> {
3920 let hasSideEffects = 0 in {
3921 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3922 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3924 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3925 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3926 [], d>, EVEX, EVEX_B, EVEX_RC;
3928 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3929 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3931 } // hasSideEffects = 0
3934 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3935 memopv16f32, f512mem, SSEPackedSingle>, PD,
3936 EVEX_V512, EVEX_CD8<32, CD8VF>;
3937 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3938 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3939 EVEX_V512, EVEX_CD8<64, CD8VF>;
3941 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3942 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3943 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3945 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3946 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3947 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3949 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3950 memopv16f32, f512mem, SSEPackedSingle>,
3951 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3952 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3953 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3954 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3956 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3957 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3958 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3960 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3961 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3962 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3964 let Predicates = [HasAVX512] in {
3965 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3966 (VCVTPD2PSZrm addr:$src)>;
3967 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3968 (VCVTPS2PDZrm addr:$src)>;
3971 //===----------------------------------------------------------------------===//
3972 // Half precision conversion instructions
3973 //===----------------------------------------------------------------------===//
3974 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3975 X86MemOperand x86memop> {
3976 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3977 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3979 let hasSideEffects = 0, mayLoad = 1 in
3980 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3981 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3984 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3985 X86MemOperand x86memop> {
3986 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3987 (ins srcRC:$src1, i32i8imm:$src2),
3988 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3990 let hasSideEffects = 0, mayStore = 1 in
3991 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3992 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3993 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3996 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3997 EVEX_CD8<32, CD8VH>;
3998 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3999 EVEX_CD8<32, CD8VH>;
4001 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4002 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4003 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4005 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4006 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4007 (VCVTPH2PSZrr VR256X:$src)>;
4009 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4010 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4011 "ucomiss">, PS, EVEX, VEX_LIG,
4012 EVEX_CD8<32, CD8VT1>;
4013 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4014 "ucomisd">, PD, EVEX,
4015 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4016 let Pattern = []<dag> in {
4017 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4018 "comiss">, PS, EVEX, VEX_LIG,
4019 EVEX_CD8<32, CD8VT1>;
4020 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4021 "comisd">, PD, EVEX,
4022 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4024 let isCodeGenOnly = 1 in {
4025 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4026 load, "ucomiss">, PS, EVEX, VEX_LIG,
4027 EVEX_CD8<32, CD8VT1>;
4028 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4029 load, "ucomisd">, PD, EVEX,
4030 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4032 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4033 load, "comiss">, PS, EVEX, VEX_LIG,
4034 EVEX_CD8<32, CD8VT1>;
4035 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4036 load, "comisd">, PD, EVEX,
4037 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4041 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4042 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4043 X86MemOperand x86memop> {
4044 let hasSideEffects = 0 in {
4045 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4046 (ins RC:$src1, RC:$src2),
4047 !strconcat(OpcodeStr,
4048 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4049 let mayLoad = 1 in {
4050 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4051 (ins RC:$src1, x86memop:$src2),
4052 !strconcat(OpcodeStr,
4053 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4058 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4059 EVEX_CD8<32, CD8VT1>;
4060 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4061 VEX_W, EVEX_CD8<64, CD8VT1>;
4062 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4063 EVEX_CD8<32, CD8VT1>;
4064 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4065 VEX_W, EVEX_CD8<64, CD8VT1>;
4067 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4068 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4069 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4070 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4072 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4073 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4074 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4075 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4077 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4078 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4079 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4080 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4082 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4083 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4084 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4085 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4087 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4088 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4089 RegisterClass RC, X86MemOperand x86memop,
4090 PatFrag mem_frag, ValueType OpVt> {
4091 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4092 !strconcat(OpcodeStr,
4093 " \t{$src, $dst|$dst, $src}"),
4094 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
4096 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4097 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4098 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
4101 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4102 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4103 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4104 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4105 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4106 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4107 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4108 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4110 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4111 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4112 (VRSQRT14PSZr VR512:$src)>;
4113 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4114 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4115 (VRSQRT14PDZr VR512:$src)>;
4117 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4118 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4119 (VRCP14PSZr VR512:$src)>;
4120 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4121 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4122 (VRCP14PDZr VR512:$src)>;
4124 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4125 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4126 X86MemOperand x86memop> {
4127 let hasSideEffects = 0, Predicates = [HasERI] in {
4128 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4129 (ins RC:$src1, RC:$src2),
4130 !strconcat(OpcodeStr,
4131 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4132 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4133 (ins RC:$src1, RC:$src2),
4134 !strconcat(OpcodeStr,
4135 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4136 []>, EVEX_4V, EVEX_B;
4137 let mayLoad = 1 in {
4138 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4139 (ins RC:$src1, x86memop:$src2),
4140 !strconcat(OpcodeStr,
4141 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4146 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4147 EVEX_CD8<32, CD8VT1>;
4148 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4149 VEX_W, EVEX_CD8<64, CD8VT1>;
4150 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4151 EVEX_CD8<32, CD8VT1>;
4152 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4153 VEX_W, EVEX_CD8<64, CD8VT1>;
4155 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4156 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4158 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4159 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4161 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4162 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4164 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4165 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4167 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4168 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4170 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4171 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4173 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4174 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4176 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4177 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4179 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4180 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4181 RegisterClass RC, X86MemOperand x86memop> {
4182 let hasSideEffects = 0, Predicates = [HasERI] in {
4183 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4184 !strconcat(OpcodeStr,
4185 " \t{$src, $dst|$dst, $src}"),
4187 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4188 !strconcat(OpcodeStr,
4189 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4191 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4192 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4196 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4197 EVEX_V512, EVEX_CD8<32, CD8VF>;
4198 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4199 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4200 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4201 EVEX_V512, EVEX_CD8<32, CD8VF>;
4202 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4203 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4205 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4206 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4207 (VRSQRT28PSZrb VR512:$src)>;
4208 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4209 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4210 (VRSQRT28PDZrb VR512:$src)>;
4212 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4213 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4214 (VRCP28PSZrb VR512:$src)>;
4215 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4216 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4217 (VRCP28PDZrb VR512:$src)>;
4219 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4220 OpndItins itins_s, OpndItins itins_d> {
4221 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4222 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4223 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4227 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4228 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4230 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4231 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4233 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4234 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4235 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4239 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4240 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4241 [(set VR512:$dst, (OpNode
4242 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4243 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4247 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4248 Intrinsic F32Int, Intrinsic F64Int,
4249 OpndItins itins_s, OpndItins itins_d> {
4250 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4251 (ins FR32X:$src1, FR32X:$src2),
4252 !strconcat(OpcodeStr,
4253 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4254 [], itins_s.rr>, XS, EVEX_4V;
4255 let isCodeGenOnly = 1 in
4256 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4257 (ins VR128X:$src1, VR128X:$src2),
4258 !strconcat(OpcodeStr,
4259 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4261 (F32Int VR128X:$src1, VR128X:$src2))],
4262 itins_s.rr>, XS, EVEX_4V;
4263 let mayLoad = 1 in {
4264 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4265 (ins FR32X:$src1, f32mem:$src2),
4266 !strconcat(OpcodeStr,
4267 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4268 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4269 let isCodeGenOnly = 1 in
4270 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4271 (ins VR128X:$src1, ssmem:$src2),
4272 !strconcat(OpcodeStr,
4273 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4275 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4276 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4278 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4279 (ins FR64X:$src1, FR64X:$src2),
4280 !strconcat(OpcodeStr,
4281 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4283 let isCodeGenOnly = 1 in
4284 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4285 (ins VR128X:$src1, VR128X:$src2),
4286 !strconcat(OpcodeStr,
4287 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4289 (F64Int VR128X:$src1, VR128X:$src2))],
4290 itins_s.rr>, XD, EVEX_4V, VEX_W;
4291 let mayLoad = 1 in {
4292 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4293 (ins FR64X:$src1, f64mem:$src2),
4294 !strconcat(OpcodeStr,
4295 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4296 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4297 let isCodeGenOnly = 1 in
4298 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4299 (ins VR128X:$src1, sdmem:$src2),
4300 !strconcat(OpcodeStr,
4301 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4303 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4304 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4309 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4310 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4311 SSE_SQRTSS, SSE_SQRTSD>,
4312 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4313 SSE_SQRTPS, SSE_SQRTPD>;
4315 let Predicates = [HasAVX512] in {
4316 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4317 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4318 (VSQRTPSZrr VR512:$src1)>;
4319 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4320 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4321 (VSQRTPDZrr VR512:$src1)>;
4323 def : Pat<(f32 (fsqrt FR32X:$src)),
4324 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4325 def : Pat<(f32 (fsqrt (load addr:$src))),
4326 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4327 Requires<[OptForSize]>;
4328 def : Pat<(f64 (fsqrt FR64X:$src)),
4329 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4330 def : Pat<(f64 (fsqrt (load addr:$src))),
4331 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4332 Requires<[OptForSize]>;
4334 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4335 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4336 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4337 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4338 Requires<[OptForSize]>;
4340 def : Pat<(f32 (X86frcp FR32X:$src)),
4341 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4342 def : Pat<(f32 (X86frcp (load addr:$src))),
4343 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4344 Requires<[OptForSize]>;
4346 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4347 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4348 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4350 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4351 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4353 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4354 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4355 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4357 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4358 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4362 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4363 X86MemOperand x86memop, RegisterClass RC,
4364 PatFrag mem_frag32, PatFrag mem_frag64,
4365 Intrinsic V4F32Int, Intrinsic V2F64Int,
4367 let ExeDomain = SSEPackedSingle in {
4368 // Intrinsic operation, reg.
4369 // Vector intrinsic operation, reg
4370 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4371 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4372 !strconcat(OpcodeStr,
4373 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4376 // Vector intrinsic operation, mem
4377 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4378 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4379 !strconcat(OpcodeStr,
4380 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4382 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4383 EVEX_CD8<32, VForm>;
4384 } // ExeDomain = SSEPackedSingle
4386 let ExeDomain = SSEPackedDouble in {
4387 // Vector intrinsic operation, reg
4388 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4389 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4390 !strconcat(OpcodeStr,
4391 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4392 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4394 // Vector intrinsic operation, mem
4395 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4396 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4397 !strconcat(OpcodeStr,
4398 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4400 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4401 EVEX_CD8<64, VForm>;
4402 } // ExeDomain = SSEPackedDouble
4405 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4409 let ExeDomain = GenericDomain in {
4411 let hasSideEffects = 0 in
4412 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4413 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4414 !strconcat(OpcodeStr,
4415 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4418 // Intrinsic operation, reg.
4419 let isCodeGenOnly = 1 in
4420 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4421 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4422 !strconcat(OpcodeStr,
4423 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4424 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4426 // Intrinsic operation, mem.
4427 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4428 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4429 !strconcat(OpcodeStr,
4430 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4431 [(set VR128X:$dst, (F32Int VR128X:$src1,
4432 sse_load_f32:$src2, imm:$src3))]>,
4433 EVEX_CD8<32, CD8VT1>;
4436 let hasSideEffects = 0 in
4437 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4438 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4439 !strconcat(OpcodeStr,
4440 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4443 // Intrinsic operation, reg.
4444 let isCodeGenOnly = 1 in
4445 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4446 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4447 !strconcat(OpcodeStr,
4448 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4449 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4452 // Intrinsic operation, mem.
4453 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4454 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4455 !strconcat(OpcodeStr,
4456 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4458 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4459 VEX_W, EVEX_CD8<64, CD8VT1>;
4460 } // ExeDomain = GenericDomain
4463 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4464 X86MemOperand x86memop, RegisterClass RC,
4465 PatFrag mem_frag, Domain d> {
4466 let ExeDomain = d in {
4467 // Intrinsic operation, reg.
4468 // Vector intrinsic operation, reg
4469 def r : AVX512AIi8<opc, MRMSrcReg,
4470 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4471 !strconcat(OpcodeStr,
4472 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4475 // Vector intrinsic operation, mem
4476 def m : AVX512AIi8<opc, MRMSrcMem,
4477 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4478 !strconcat(OpcodeStr,
4479 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4485 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4486 memopv16f32, SSEPackedSingle>, EVEX_V512,
4487 EVEX_CD8<32, CD8VF>;
4489 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4490 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4492 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4495 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4496 memopv8f64, SSEPackedDouble>, EVEX_V512,
4497 VEX_W, EVEX_CD8<64, CD8VF>;
4499 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4500 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4502 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4504 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4505 Operand x86memop, RegisterClass RC, Domain d> {
4506 let ExeDomain = d in {
4507 def r : AVX512AIi8<opc, MRMSrcReg,
4508 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4509 !strconcat(OpcodeStr,
4510 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4513 def m : AVX512AIi8<opc, MRMSrcMem,
4514 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4515 !strconcat(OpcodeStr,
4516 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4521 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4522 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4524 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4525 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4527 def : Pat<(ffloor FR32X:$src),
4528 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4529 def : Pat<(f64 (ffloor FR64X:$src)),
4530 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4531 def : Pat<(f32 (fnearbyint FR32X:$src)),
4532 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4533 def : Pat<(f64 (fnearbyint FR64X:$src)),
4534 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4535 def : Pat<(f32 (fceil FR32X:$src)),
4536 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4537 def : Pat<(f64 (fceil FR64X:$src)),
4538 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4539 def : Pat<(f32 (frint FR32X:$src)),
4540 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4541 def : Pat<(f64 (frint FR64X:$src)),
4542 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4543 def : Pat<(f32 (ftrunc FR32X:$src)),
4544 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4545 def : Pat<(f64 (ftrunc FR64X:$src)),
4546 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4548 def : Pat<(v16f32 (ffloor VR512:$src)),
4549 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4550 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4551 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4552 def : Pat<(v16f32 (fceil VR512:$src)),
4553 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4554 def : Pat<(v16f32 (frint VR512:$src)),
4555 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4556 def : Pat<(v16f32 (ftrunc VR512:$src)),
4557 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4559 def : Pat<(v8f64 (ffloor VR512:$src)),
4560 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4561 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4562 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4563 def : Pat<(v8f64 (fceil VR512:$src)),
4564 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4565 def : Pat<(v8f64 (frint VR512:$src)),
4566 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4567 def : Pat<(v8f64 (ftrunc VR512:$src)),
4568 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4570 //-------------------------------------------------
4571 // Integer truncate and extend operations
4572 //-------------------------------------------------
4574 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4575 RegisterClass dstRC, RegisterClass srcRC,
4576 RegisterClass KRC, X86MemOperand x86memop> {
4577 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4579 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4582 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4583 (ins KRC:$mask, srcRC:$src),
4584 !strconcat(OpcodeStr,
4585 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4588 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4589 (ins KRC:$mask, srcRC:$src),
4590 !strconcat(OpcodeStr,
4591 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4594 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4595 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4598 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4599 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4600 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4604 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4605 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4606 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4607 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4608 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4609 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4610 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4611 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4612 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4613 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4614 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4615 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4616 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4617 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4618 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4619 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4620 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4621 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4622 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4623 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4624 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4625 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4626 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4627 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4628 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4629 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4630 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4631 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4632 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4633 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4635 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4636 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4637 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4638 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4639 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4641 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4642 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4643 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4644 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4645 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4646 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4647 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4648 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4651 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4652 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4653 PatFrag mem_frag, X86MemOperand x86memop,
4654 ValueType OpVT, ValueType InVT> {
4656 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4658 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4659 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4661 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4662 (ins KRC:$mask, SrcRC:$src),
4663 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4666 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4667 (ins KRC:$mask, SrcRC:$src),
4668 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4671 let mayLoad = 1 in {
4672 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4673 (ins x86memop:$src),
4674 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4676 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4679 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4680 (ins KRC:$mask, x86memop:$src),
4681 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4685 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4686 (ins KRC:$mask, x86memop:$src),
4687 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4693 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4694 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4696 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4697 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4699 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4700 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4701 EVEX_CD8<16, CD8VH>;
4702 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4703 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4704 EVEX_CD8<16, CD8VQ>;
4705 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4706 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4707 EVEX_CD8<32, CD8VH>;
4709 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4710 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4712 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4713 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4715 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4716 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4717 EVEX_CD8<16, CD8VH>;
4718 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4719 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4720 EVEX_CD8<16, CD8VQ>;
4721 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4722 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4723 EVEX_CD8<32, CD8VH>;
4725 //===----------------------------------------------------------------------===//
4726 // GATHER - SCATTER Operations
4728 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4729 RegisterClass RC, X86MemOperand memop> {
4731 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4732 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4733 (ins RC:$src1, KRC:$mask, memop:$src2),
4734 !strconcat(OpcodeStr,
4735 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4739 let ExeDomain = SSEPackedDouble in {
4740 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4741 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4742 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4743 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4746 let ExeDomain = SSEPackedSingle in {
4747 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4748 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4749 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4750 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4753 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4754 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4755 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4756 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4758 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4759 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4760 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4761 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4763 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4764 RegisterClass RC, X86MemOperand memop> {
4765 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4766 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4767 (ins memop:$dst, KRC:$mask, RC:$src2),
4768 !strconcat(OpcodeStr,
4769 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4773 let ExeDomain = SSEPackedDouble in {
4774 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4775 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4776 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4777 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4780 let ExeDomain = SSEPackedSingle in {
4781 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4782 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4783 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4784 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4787 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4788 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4789 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4790 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4792 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4793 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4794 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4795 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4798 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4799 RegisterClass KRC, X86MemOperand memop> {
4800 let Predicates = [HasPFI], hasSideEffects = 1 in
4801 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4802 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4806 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4807 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4809 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4810 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4812 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4813 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4815 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4816 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4818 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4819 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4821 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4822 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4824 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4825 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4827 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4828 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4830 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4831 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4833 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4834 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4836 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4837 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4839 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4840 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4842 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4843 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4845 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4846 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4848 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4849 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4851 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4852 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4853 //===----------------------------------------------------------------------===//
4854 // VSHUFPS - VSHUFPD Operations
4856 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4857 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4859 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4860 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4861 !strconcat(OpcodeStr,
4862 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4863 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4864 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4865 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4866 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4867 (ins RC:$src1, RC:$src2, i8imm:$src3),
4868 !strconcat(OpcodeStr,
4869 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4870 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4871 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4872 EVEX_4V, Sched<[WriteShuffle]>;
4875 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4876 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4877 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4878 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4880 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4881 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4882 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4883 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4884 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4886 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4887 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4888 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4889 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4890 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4892 multiclass avx512_valign<X86VectorVTInfo _> {
4893 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4894 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4896 "$src3, $src2, $src1", "$src1, $src2, $src3",
4897 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4899 AVX512AIi8Base, EVEX_4V;
4901 // Also match valign of packed floats.
4902 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4903 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4906 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4907 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4908 !strconcat("valign"##_.Suffix,
4909 " \t{$src3, $src2, $src1, $dst|"
4910 "$dst, $src1, $src2, $src3}"),
4913 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4914 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4916 // Helper fragments to match sext vXi1 to vXiY.
4917 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4918 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4920 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4921 RegisterClass KRC, RegisterClass RC,
4922 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4924 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4927 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4928 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4930 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4931 !strconcat(OpcodeStr,
4932 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4934 let mayLoad = 1 in {
4935 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4936 (ins x86memop:$src),
4937 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4939 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4940 (ins KRC:$mask, x86memop:$src),
4941 !strconcat(OpcodeStr,
4942 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4944 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4945 (ins KRC:$mask, x86memop:$src),
4946 !strconcat(OpcodeStr,
4947 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4949 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4950 (ins x86scalar_mop:$src),
4951 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4952 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4954 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4955 (ins KRC:$mask, x86scalar_mop:$src),
4956 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4957 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4958 []>, EVEX, EVEX_B, EVEX_K;
4959 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4960 (ins KRC:$mask, x86scalar_mop:$src),
4961 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4962 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4964 []>, EVEX, EVEX_B, EVEX_KZ;
4968 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4969 i512mem, i32mem, "{1to16}">, EVEX_V512,
4970 EVEX_CD8<32, CD8VF>;
4971 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4972 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4973 EVEX_CD8<64, CD8VF>;
4976 (bc_v16i32 (v16i1sextv16i32)),
4977 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4978 (VPABSDZrr VR512:$src)>;
4980 (bc_v8i64 (v8i1sextv8i64)),
4981 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4982 (VPABSQZrr VR512:$src)>;
4984 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4985 (v16i32 immAllZerosV), (i16 -1))),
4986 (VPABSDZrr VR512:$src)>;
4987 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4988 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4989 (VPABSQZrr VR512:$src)>;
4991 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4992 RegisterClass RC, RegisterClass KRC,
4993 X86MemOperand x86memop,
4994 X86MemOperand x86scalar_mop, string BrdcstStr> {
4995 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4997 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4999 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5000 (ins x86memop:$src),
5001 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
5003 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5004 (ins x86scalar_mop:$src),
5005 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5006 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5008 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5009 (ins KRC:$mask, RC:$src),
5010 !strconcat(OpcodeStr,
5011 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5013 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5014 (ins KRC:$mask, x86memop:$src),
5015 !strconcat(OpcodeStr,
5016 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5018 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5019 (ins KRC:$mask, x86scalar_mop:$src),
5020 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5021 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5023 []>, EVEX, EVEX_KZ, EVEX_B;
5025 let Constraints = "$src1 = $dst" in {
5026 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5027 (ins RC:$src1, KRC:$mask, RC:$src2),
5028 !strconcat(OpcodeStr,
5029 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5031 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5032 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5033 !strconcat(OpcodeStr,
5034 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5036 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5037 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5038 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5039 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5040 []>, EVEX, EVEX_K, EVEX_B;
5044 let Predicates = [HasCDI] in {
5045 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5046 i512mem, i32mem, "{1to16}">,
5047 EVEX_V512, EVEX_CD8<32, CD8VF>;
5050 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5051 i512mem, i64mem, "{1to8}">,
5052 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5056 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5058 (VPCONFLICTDrrk VR512:$src1,
5059 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5061 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5063 (VPCONFLICTQrrk VR512:$src1,
5064 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5066 let Predicates = [HasCDI] in {
5067 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5068 i512mem, i32mem, "{1to16}">,
5069 EVEX_V512, EVEX_CD8<32, CD8VF>;
5072 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5073 i512mem, i64mem, "{1to8}">,
5074 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5078 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5080 (VPLZCNTDrrk VR512:$src1,
5081 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5083 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5085 (VPLZCNTQrrk VR512:$src1,
5086 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5088 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5089 (VPLZCNTDrm addr:$src)>;
5090 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5091 (VPLZCNTDrr VR512:$src)>;
5092 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5093 (VPLZCNTQrm addr:$src)>;
5094 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5095 (VPLZCNTQrr VR512:$src)>;
5097 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5098 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5099 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5101 def : Pat<(store VK1:$src, addr:$dst),
5102 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5104 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5105 (truncstore node:$val, node:$ptr), [{
5106 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5109 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5110 (MOV8mr addr:$dst, GR8:$src)>;
5112 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5113 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5114 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5115 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5118 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5119 string OpcodeStr, Predicate prd> {
5120 let Predicates = [prd] in
5121 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5123 let Predicates = [prd, HasVLX] in {
5124 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5125 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5129 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5130 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5132 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5134 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5136 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5140 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;