1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
108 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
109 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
110 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
111 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
113 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
114 X86VectorVTInfo i128> {
115 X86VectorVTInfo info512 = i512;
116 X86VectorVTInfo info256 = i256;
117 X86VectorVTInfo info128 = i128;
120 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
122 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
124 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
126 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
129 // This multiclass generates the masking variants from the non-masking
130 // variant. It only provides the assembly pieces for the masking variants.
131 // It assumes custom ISel patterns for masking which can be provided as
132 // template arguments.
133 multiclass AVX512_maskable_custom<bits<8> O, Format F,
135 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
137 string AttSrcAsm, string IntelSrcAsm,
139 list<dag> MaskingPattern,
140 list<dag> ZeroMaskingPattern,
141 string MaskingConstraint = "",
142 InstrItinClass itin = NoItinerary,
143 bit IsCommutable = 0> {
144 let isCommutable = IsCommutable in
145 def NAME: AVX512<O, F, Outs, Ins,
146 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
147 "$dst, "#IntelSrcAsm#"}",
150 // Prefer over VMOV*rrk Pat<>
151 let AddedComplexity = 20 in
152 def NAME#k: AVX512<O, F, Outs, MaskingIns,
153 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
154 "$dst {${mask}}, "#IntelSrcAsm#"}",
155 MaskingPattern, itin>,
157 // In case of the 3src subclass this is overridden with a let.
158 string Constraints = MaskingConstraint;
160 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
161 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
163 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
170 // Common base class of AVX512_maskable and AVX512_maskable_3src.
171 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
173 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
175 string AttSrcAsm, string IntelSrcAsm,
176 dag RHS, dag MaskingRHS,
177 string MaskingConstraint = "",
178 InstrItinClass itin = NoItinerary,
179 bit IsCommutable = 0> :
180 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
181 AttSrcAsm, IntelSrcAsm,
182 [(set _.RC:$dst, RHS)],
183 [(set _.RC:$dst, MaskingRHS)],
185 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
186 MaskingConstraint, NoItinerary, IsCommutable>;
188 // This multiclass generates the unconditional/non-masking, the masking and
189 // the zero-masking variant of the instruction. In the masking case, the
190 // perserved vector elements come from a new dummy input operand tied to $dst.
191 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Outs, dag Ins, string OpcodeStr,
193 string AttSrcAsm, string IntelSrcAsm,
194 dag RHS, InstrItinClass itin = NoItinerary,
195 bit IsCommutable = 0> :
196 AVX512_maskable_common<O, F, _, Outs, Ins,
197 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
198 !con((ins _.KRCWM:$mask), Ins),
199 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
200 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
201 "$src0 = $dst", itin, IsCommutable>;
203 // Similar to AVX512_maskable but in this case one of the source operands
204 // ($src1) is already tied to $dst so we just use that for the preserved
205 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
207 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
208 dag Outs, dag NonTiedIns, string OpcodeStr,
209 string AttSrcAsm, string IntelSrcAsm,
211 AVX512_maskable_common<O, F, _, Outs,
212 !con((ins _.RC:$src1), NonTiedIns),
213 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
214 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
215 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
216 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
219 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
222 string AttSrcAsm, string IntelSrcAsm,
224 AVX512_maskable_custom<O, F, Outs, Ins,
225 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
226 !con((ins _.KRCWM:$mask), Ins),
227 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
230 // Bitcasts between 512-bit vector types. Return the original type since
231 // no instruction is needed for the conversion
232 let Predicates = [HasAVX512] in {
233 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
234 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
235 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
236 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
237 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
238 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
239 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
240 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
241 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
242 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
243 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
244 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
245 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
246 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
247 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
248 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
249 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
250 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
251 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
252 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
253 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
254 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
255 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
256 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
257 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
258 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
259 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
260 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
261 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
262 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
263 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
265 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
266 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
267 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
268 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
269 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
270 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
271 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
272 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
273 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
274 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
275 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
276 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
277 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
278 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
279 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
280 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
281 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
282 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
283 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
284 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
285 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
286 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
287 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
288 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
289 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
290 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
291 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
292 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
293 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
294 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
296 // Bitcasts between 256-bit vector types. Return the original type since
297 // no instruction is needed for the conversion
298 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
299 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
300 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
301 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
302 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
303 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
304 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
305 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
306 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
307 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
308 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
309 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
310 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
311 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
312 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
313 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
314 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
315 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
316 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
317 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
318 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
319 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
320 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
321 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
322 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
323 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
324 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
325 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
326 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
327 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
331 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
334 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
335 isPseudo = 1, Predicates = [HasAVX512] in {
336 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
337 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
340 let Predicates = [HasAVX512] in {
341 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
342 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
343 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
346 //===----------------------------------------------------------------------===//
347 // AVX-512 - VECTOR INSERT
350 multiclass vinsert_for_size_no_alt<int Opcode,
351 X86VectorVTInfo From, X86VectorVTInfo To,
352 PatFrag vinsert_insert,
353 SDNodeXForm INSERT_get_vinsert_imm> {
354 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
355 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
356 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
357 "vinsert" # From.EltTypeName # "x" # From.NumElts #
358 "\t{$src3, $src2, $src1, $dst|"
359 "$dst, $src1, $src2, $src3}",
360 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
361 (From.VT From.RC:$src2),
366 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
367 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
372 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
376 multiclass vinsert_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vinsert_insert,
380 SDNodeXForm INSERT_get_vinsert_imm> :
381 vinsert_for_size_no_alt<Opcode, From, To,
382 vinsert_insert, INSERT_get_vinsert_imm> {
383 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
384 // vinserti32x4. Only add this if 64x2 and friends are not supported
385 // natively via AVX512DQ.
386 let Predicates = [NoDQI] in
387 def : Pat<(vinsert_insert:$ins
388 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
389 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
390 VR512:$src1, From.RC:$src2,
391 (INSERT_get_vinsert_imm VR512:$ins)))>;
394 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
395 ValueType EltVT64, int Opcode256> {
396 defm NAME # "32x4" : vinsert_for_size<Opcode128,
397 X86VectorVTInfo< 4, EltVT32, VR128X>,
398 X86VectorVTInfo<16, EltVT32, VR512>,
399 X86VectorVTInfo< 2, EltVT64, VR128X>,
400 X86VectorVTInfo< 8, EltVT64, VR512>,
402 INSERT_get_vinsert128_imm>;
403 let Predicates = [HasDQI] in
404 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
405 X86VectorVTInfo< 2, EltVT64, VR128X>,
406 X86VectorVTInfo< 8, EltVT64, VR512>,
408 INSERT_get_vinsert128_imm>, VEX_W;
409 defm NAME # "64x4" : vinsert_for_size<Opcode256,
410 X86VectorVTInfo< 4, EltVT64, VR256X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
412 X86VectorVTInfo< 8, EltVT32, VR256>,
413 X86VectorVTInfo<16, EltVT32, VR512>,
415 INSERT_get_vinsert256_imm>, VEX_W;
416 let Predicates = [HasDQI] in
417 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
418 X86VectorVTInfo< 8, EltVT32, VR256X>,
419 X86VectorVTInfo<16, EltVT32, VR512>,
421 INSERT_get_vinsert256_imm>;
424 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
425 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
427 // vinsertps - insert f32 to XMM
428 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
429 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
430 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
431 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
433 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
434 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
435 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
436 [(set VR128X:$dst, (X86insertps VR128X:$src1,
437 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
438 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
440 //===----------------------------------------------------------------------===//
441 // AVX-512 VECTOR EXTRACT
444 multiclass vextract_for_size<int Opcode,
445 X86VectorVTInfo From, X86VectorVTInfo To,
446 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
447 PatFrag vextract_extract,
448 SDNodeXForm EXTRACT_get_vextract_imm> {
449 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
450 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
451 (ins VR512:$src1, i8imm:$idx),
452 "vextract" # To.EltTypeName # "x4",
453 "$idx, $src1", "$src1, $idx",
454 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
456 AVX512AIi8Base, EVEX, EVEX_V512;
458 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
459 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
460 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
461 "$dst, $src1, $src2}",
462 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
465 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
467 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
468 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
470 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
472 // A 128/256-bit subvector extract from the first 512-bit vector position is
473 // a subregister copy that needs no instruction.
474 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
476 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
478 // And for the alternative types.
479 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
481 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
483 // Intrinsic call with masking.
484 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
486 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
487 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
488 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
489 VR512:$src1, imm:$idx)>;
491 // Intrinsic call with zero-masking.
492 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
494 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
495 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
496 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
497 VR512:$src1, imm:$idx)>;
499 // Intrinsic call without masking.
500 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
502 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
503 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
504 VR512:$src1, imm:$idx)>;
507 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
508 ValueType EltVT64, int Opcode64> {
509 defm NAME # "32x4" : vextract_for_size<Opcode32,
510 X86VectorVTInfo<16, EltVT32, VR512>,
511 X86VectorVTInfo< 4, EltVT32, VR128X>,
512 X86VectorVTInfo< 8, EltVT64, VR512>,
513 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 EXTRACT_get_vextract128_imm>;
516 defm NAME # "64x4" : vextract_for_size<Opcode64,
517 X86VectorVTInfo< 8, EltVT64, VR512>,
518 X86VectorVTInfo< 4, EltVT64, VR256X>,
519 X86VectorVTInfo<16, EltVT32, VR512>,
520 X86VectorVTInfo< 8, EltVT32, VR256>,
522 EXTRACT_get_vextract256_imm>, VEX_W;
525 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
526 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
528 // A 128-bit subvector insert to the first 512-bit vector position
529 // is a subregister copy that needs no instruction.
530 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
531 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
532 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
534 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
535 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
536 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
538 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
542 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
547 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
548 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
549 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
551 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
552 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
553 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
556 // vextractps - extract 32 bits from XMM
557 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
558 (ins VR128X:$src1, i32i8imm:$src2),
559 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
560 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
563 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
564 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
565 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
566 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
567 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
569 //===---------------------------------------------------------------------===//
572 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
573 RegisterClass DestRC,
574 RegisterClass SrcRC, X86MemOperand x86memop> {
575 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
578 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
581 let ExeDomain = SSEPackedSingle in {
582 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
584 EVEX_V512, EVEX_CD8<32, CD8VT1>;
587 let ExeDomain = SSEPackedDouble in {
588 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
593 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
594 (VBROADCASTSSZrm addr:$src)>;
595 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
596 (VBROADCASTSDZrm addr:$src)>;
598 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
599 (VBROADCASTSSZrm addr:$src)>;
600 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
601 (VBROADCASTSDZrm addr:$src)>;
603 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
604 RegisterClass SrcRC, RegisterClass KRC> {
605 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
606 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
607 []>, EVEX, EVEX_V512;
608 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
609 (ins KRC:$mask, SrcRC:$src),
610 !strconcat(OpcodeStr,
611 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
612 []>, EVEX, EVEX_V512, EVEX_KZ;
615 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
616 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
619 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
620 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
622 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
623 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
625 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
626 (VPBROADCASTDrZrr GR32:$src)>;
627 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
628 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
629 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
630 (VPBROADCASTQrZrr GR64:$src)>;
631 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
632 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
634 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
635 (VPBROADCASTDrZrr GR32:$src)>;
636 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
637 (VPBROADCASTQrZrr GR64:$src)>;
639 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
640 (v16i32 immAllZerosV), (i16 GR16:$mask))),
641 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
642 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
643 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
644 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
646 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
647 X86MemOperand x86memop, PatFrag ld_frag,
648 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
650 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
651 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
653 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
654 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
656 !strconcat(OpcodeStr,
657 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
659 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
663 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
665 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
666 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
668 !strconcat(OpcodeStr,
669 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
670 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
671 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
675 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
676 loadi32, VR512, v16i32, v4i32, VK16WM>,
677 EVEX_V512, EVEX_CD8<32, CD8VT1>;
678 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
679 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
680 EVEX_CD8<64, CD8VT1>;
682 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
683 X86MemOperand x86memop, PatFrag ld_frag,
686 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
689 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
691 !strconcat(OpcodeStr,
692 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
697 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
698 i128mem, loadv2i64, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
701 i256mem, loadv4i64, VK16WM>, VEX_W,
702 EVEX_V512, EVEX_CD8<64, CD8VT4>;
704 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
705 (VPBROADCASTDZrr VR128X:$src)>;
706 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
707 (VPBROADCASTQZrr VR128X:$src)>;
709 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
710 (VBROADCASTSSZrr VR128X:$src)>;
711 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
712 (VBROADCASTSDZrr VR128X:$src)>;
714 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
715 (VBROADCASTSSZrr VR128X:$src)>;
716 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
717 (VBROADCASTSDZrr VR128X:$src)>;
719 // Provide fallback in case the load node that is used in the patterns above
720 // is used by additional users, which prevents the pattern selection.
721 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
722 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
723 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
724 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
727 let Predicates = [HasAVX512] in {
728 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
730 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
731 addr:$src)), sub_ymm)>;
733 //===----------------------------------------------------------------------===//
734 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
737 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
738 RegisterClass DstRC, RegisterClass KRC,
739 ValueType OpVT, ValueType SrcVT> {
740 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
741 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
745 let Predicates = [HasCDI] in {
746 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
747 VK16, v16i32, v16i1>, EVEX_V512;
748 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
749 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
752 //===----------------------------------------------------------------------===//
755 // -- immediate form --
756 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
757 SDNode OpNode, PatFrag mem_frag,
758 X86MemOperand x86memop, ValueType OpVT> {
759 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
760 (ins RC:$src1, i8imm:$src2),
761 !strconcat(OpcodeStr,
762 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
764 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
766 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
767 (ins x86memop:$src1, i8imm:$src2),
768 !strconcat(OpcodeStr,
769 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
771 (OpVT (OpNode (mem_frag addr:$src1),
772 (i8 imm:$src2))))]>, EVEX;
775 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
776 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
777 let ExeDomain = SSEPackedDouble in
778 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
779 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
781 // -- VPERM - register form --
782 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
783 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
785 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
786 (ins RC:$src1, RC:$src2),
787 !strconcat(OpcodeStr,
788 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
790 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
792 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
793 (ins RC:$src1, x86memop:$src2),
794 !strconcat(OpcodeStr,
795 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
797 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
801 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
802 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
803 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
804 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
805 let ExeDomain = SSEPackedSingle in
806 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
807 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
808 let ExeDomain = SSEPackedDouble in
809 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
810 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
812 // -- VPERM2I - 3 source operands form --
813 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
814 PatFrag mem_frag, X86MemOperand x86memop,
815 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
816 let Constraints = "$src1 = $dst" in {
817 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
818 (ins RC:$src1, RC:$src2, RC:$src3),
819 !strconcat(OpcodeStr,
820 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
822 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
825 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
826 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
827 !strconcat(OpcodeStr,
828 " \t{$src3, $src2, $dst {${mask}}|"
829 "$dst {${mask}}, $src2, $src3}"),
830 [(set RC:$dst, (OpVT (vselect KRC:$mask,
831 (OpNode RC:$src1, RC:$src2,
836 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
837 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
838 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
839 !strconcat(OpcodeStr,
840 " \t{$src3, $src2, $dst {${mask}} {z} |",
841 "$dst {${mask}} {z}, $src2, $src3}"),
842 [(set RC:$dst, (OpVT (vselect KRC:$mask,
843 (OpNode RC:$src1, RC:$src2,
846 (v16i32 immAllZerosV))))))]>,
849 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
850 (ins RC:$src1, RC:$src2, x86memop:$src3),
851 !strconcat(OpcodeStr,
852 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
854 (OpVT (OpNode RC:$src1, RC:$src2,
855 (mem_frag addr:$src3))))]>, EVEX_4V;
857 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
858 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
859 !strconcat(OpcodeStr,
860 " \t{$src3, $src2, $dst {${mask}}|"
861 "$dst {${mask}}, $src2, $src3}"),
863 (OpVT (vselect KRC:$mask,
864 (OpNode RC:$src1, RC:$src2,
865 (mem_frag addr:$src3)),
869 let AddedComplexity = 10 in // Prefer over the rrkz variant
870 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
871 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
872 !strconcat(OpcodeStr,
873 " \t{$src3, $src2, $dst {${mask}} {z}|"
874 "$dst {${mask}} {z}, $src2, $src3}"),
876 (OpVT (vselect KRC:$mask,
877 (OpNode RC:$src1, RC:$src2,
878 (mem_frag addr:$src3)),
880 (v16i32 immAllZerosV))))))]>,
884 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
885 i512mem, X86VPermiv3, v16i32, VK16WM>,
886 EVEX_V512, EVEX_CD8<32, CD8VF>;
887 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
888 i512mem, X86VPermiv3, v8i64, VK8WM>,
889 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
890 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
891 i512mem, X86VPermiv3, v16f32, VK16WM>,
892 EVEX_V512, EVEX_CD8<32, CD8VF>;
893 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
894 i512mem, X86VPermiv3, v8f64, VK8WM>,
895 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
897 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
898 PatFrag mem_frag, X86MemOperand x86memop,
899 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
900 ValueType MaskVT, RegisterClass MRC> :
901 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
903 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
904 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
905 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
907 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
908 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
909 (!cast<Instruction>(NAME#rrk) VR512:$src1,
910 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
913 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
914 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
915 EVEX_V512, EVEX_CD8<32, CD8VF>;
916 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
917 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
918 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
919 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
920 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
921 EVEX_V512, EVEX_CD8<32, CD8VF>;
922 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
923 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
924 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
926 //===----------------------------------------------------------------------===//
927 // AVX-512 - BLEND using mask
929 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
930 RegisterClass KRC, RegisterClass RC,
931 X86MemOperand x86memop, PatFrag mem_frag,
932 SDNode OpNode, ValueType vt> {
933 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
934 (ins KRC:$mask, RC:$src1, RC:$src2),
935 !strconcat(OpcodeStr,
936 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
937 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
938 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
940 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
941 (ins KRC:$mask, RC:$src1, x86memop:$src2),
942 !strconcat(OpcodeStr,
943 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
944 []>, EVEX_4V, EVEX_K;
947 let ExeDomain = SSEPackedSingle in
948 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
949 VK16WM, VR512, f512mem,
950 memopv16f32, vselect, v16f32>,
951 EVEX_CD8<32, CD8VF>, EVEX_V512;
952 let ExeDomain = SSEPackedDouble in
953 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
954 VK8WM, VR512, f512mem,
955 memopv8f64, vselect, v8f64>,
956 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
958 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
959 (v16f32 VR512:$src2), (i16 GR16:$mask))),
960 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
961 VR512:$src1, VR512:$src2)>;
963 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
964 (v8f64 VR512:$src2), (i8 GR8:$mask))),
965 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
966 VR512:$src1, VR512:$src2)>;
968 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
969 VK16WM, VR512, f512mem,
970 memopv16i32, vselect, v16i32>,
971 EVEX_CD8<32, CD8VF>, EVEX_V512;
973 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
974 VK8WM, VR512, f512mem,
975 memopv8i64, vselect, v8i64>,
976 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
978 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
979 (v16i32 VR512:$src2), (i16 GR16:$mask))),
980 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
981 VR512:$src1, VR512:$src2)>;
983 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
984 (v8i64 VR512:$src2), (i8 GR8:$mask))),
985 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
986 VR512:$src1, VR512:$src2)>;
988 let Predicates = [HasAVX512] in {
989 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
990 (v8f32 VR256X:$src2))),
992 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
993 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
994 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
996 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
997 (v8i32 VR256X:$src2))),
999 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1000 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1001 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1003 //===----------------------------------------------------------------------===//
1004 // Compare Instructions
1005 //===----------------------------------------------------------------------===//
1007 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1008 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1009 Operand CC, SDNode OpNode, ValueType VT,
1010 PatFrag ld_frag, string asm, string asm_alt> {
1011 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1012 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1013 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1014 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1015 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1016 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1017 [(set VK1:$dst, (OpNode (VT RC:$src1),
1018 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1019 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1020 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1021 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1022 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1023 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1024 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1025 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1029 let Predicates = [HasAVX512] in {
1030 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1031 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1032 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1034 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1035 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1036 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1040 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1041 X86VectorVTInfo _> {
1042 def rr : AVX512BI<opc, MRMSrcReg,
1043 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1046 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1048 def rm : AVX512BI<opc, MRMSrcMem,
1049 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1051 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1052 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1053 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1054 def rrk : AVX512BI<opc, MRMSrcReg,
1055 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1056 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1057 "$dst {${mask}}, $src1, $src2}"),
1058 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1059 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1060 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1062 def rmk : AVX512BI<opc, MRMSrcMem,
1063 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1064 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1065 "$dst {${mask}}, $src1, $src2}"),
1066 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1067 (OpNode (_.VT _.RC:$src1),
1069 (_.LdFrag addr:$src2))))))],
1070 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1073 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1074 X86VectorVTInfo _> :
1075 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1076 let mayLoad = 1 in {
1077 def rmb : AVX512BI<opc, MRMSrcMem,
1078 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1079 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1080 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1081 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1082 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1083 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1084 def rmbk : AVX512BI<opc, MRMSrcMem,
1085 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1086 _.ScalarMemOp:$src2),
1087 !strconcat(OpcodeStr,
1088 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1089 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1090 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1091 (OpNode (_.VT _.RC:$src1),
1093 (_.ScalarLdFrag addr:$src2)))))],
1094 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1098 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1099 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1100 let Predicates = [prd] in
1101 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1104 let Predicates = [prd, HasVLX] in {
1105 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1107 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1112 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1113 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1115 let Predicates = [prd] in
1116 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1119 let Predicates = [prd, HasVLX] in {
1120 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1122 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1127 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1128 avx512vl_i8_info, HasBWI>,
1131 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1132 avx512vl_i16_info, HasBWI>,
1133 EVEX_CD8<16, CD8VF>;
1135 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1136 avx512vl_i32_info, HasAVX512>,
1137 EVEX_CD8<32, CD8VF>;
1139 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1140 avx512vl_i64_info, HasAVX512>,
1141 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1143 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1144 avx512vl_i8_info, HasBWI>,
1147 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1148 avx512vl_i16_info, HasBWI>,
1149 EVEX_CD8<16, CD8VF>;
1151 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1152 avx512vl_i32_info, HasAVX512>,
1153 EVEX_CD8<32, CD8VF>;
1155 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1156 avx512vl_i64_info, HasAVX512>,
1157 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1159 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1160 (COPY_TO_REGCLASS (VPCMPGTDZrr
1161 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1162 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1164 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1165 (COPY_TO_REGCLASS (VPCMPEQDZrr
1166 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1167 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1169 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1170 X86VectorVTInfo _> {
1171 def rri : AVX512AIi8<opc, MRMSrcReg,
1172 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1173 !strconcat("vpcmp${cc}", Suffix,
1174 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1175 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1177 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1179 def rmi : AVX512AIi8<opc, MRMSrcMem,
1180 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1181 !strconcat("vpcmp${cc}", Suffix,
1182 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1183 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1184 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1186 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1187 def rrik : AVX512AIi8<opc, MRMSrcReg,
1188 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1190 !strconcat("vpcmp${cc}", Suffix,
1191 "\t{$src2, $src1, $dst {${mask}}|",
1192 "$dst {${mask}}, $src1, $src2}"),
1193 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1194 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1196 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1198 def rmik : AVX512AIi8<opc, MRMSrcMem,
1199 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1201 !strconcat("vpcmp${cc}", Suffix,
1202 "\t{$src2, $src1, $dst {${mask}}|",
1203 "$dst {${mask}}, $src1, $src2}"),
1204 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1205 (OpNode (_.VT _.RC:$src1),
1206 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1208 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1210 // Accept explicit immediate argument form instead of comparison code.
1211 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1212 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1213 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1214 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1215 "$dst, $src1, $src2, $cc}"),
1216 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1217 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1218 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1219 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1220 "$dst, $src1, $src2, $cc}"),
1221 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1222 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1223 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1225 !strconcat("vpcmp", Suffix,
1226 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1227 "$dst {${mask}}, $src1, $src2, $cc}"),
1228 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1229 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1230 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1232 !strconcat("vpcmp", Suffix,
1233 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1234 "$dst {${mask}}, $src1, $src2, $cc}"),
1235 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1239 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1240 X86VectorVTInfo _> :
1241 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1242 let mayLoad = 1 in {
1243 def rmib : AVX512AIi8<opc, MRMSrcMem,
1244 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1246 !strconcat("vpcmp${cc}", Suffix,
1247 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1248 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1249 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1250 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1252 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1253 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1254 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1255 _.ScalarMemOp:$src2, AVXCC:$cc),
1256 !strconcat("vpcmp${cc}", Suffix,
1257 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1258 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1259 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1260 (OpNode (_.VT _.RC:$src1),
1261 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1263 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1266 // Accept explicit immediate argument form instead of comparison code.
1267 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1268 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1269 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1271 !strconcat("vpcmp", Suffix,
1272 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1273 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1274 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1275 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1276 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1277 _.ScalarMemOp:$src2, i8imm:$cc),
1278 !strconcat("vpcmp", Suffix,
1279 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1280 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1281 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1285 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1286 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1287 let Predicates = [prd] in
1288 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1290 let Predicates = [prd, HasVLX] in {
1291 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1296 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1297 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1298 let Predicates = [prd] in
1299 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1302 let Predicates = [prd, HasVLX] in {
1303 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1305 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1310 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1311 HasBWI>, EVEX_CD8<8, CD8VF>;
1312 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1313 HasBWI>, EVEX_CD8<8, CD8VF>;
1315 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1316 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1317 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1318 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1320 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1321 HasAVX512>, EVEX_CD8<32, CD8VF>;
1322 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1323 HasAVX512>, EVEX_CD8<32, CD8VF>;
1325 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1326 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1327 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1328 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1330 // avx512_cmp_packed - compare packed instructions
1331 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1332 X86MemOperand x86memop, ValueType vt,
1333 string suffix, Domain d> {
1334 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1335 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1336 !strconcat("vcmp${cc}", suffix,
1337 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1338 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1339 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1340 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1341 !strconcat("vcmp${cc}", suffix,
1342 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1344 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1345 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1346 !strconcat("vcmp${cc}", suffix,
1347 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1349 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1351 // Accept explicit immediate argument form instead of comparison code.
1352 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1353 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1354 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1355 !strconcat("vcmp", suffix,
1356 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1357 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1358 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1359 !strconcat("vcmp", suffix,
1360 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1364 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1365 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1366 EVEX_CD8<32, CD8VF>;
1367 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1368 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1369 EVEX_CD8<64, CD8VF>;
1371 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1372 (COPY_TO_REGCLASS (VCMPPSZrri
1373 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1374 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1376 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1377 (COPY_TO_REGCLASS (VPCMPDZrri
1378 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1379 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1381 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1382 (COPY_TO_REGCLASS (VPCMPUDZrri
1383 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1384 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1387 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1388 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1390 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1391 (I8Imm imm:$cc)), GR16)>;
1393 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1394 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1396 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1397 (I8Imm imm:$cc)), GR8)>;
1399 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1400 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1402 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1403 (I8Imm imm:$cc)), GR16)>;
1405 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1406 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1408 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1409 (I8Imm imm:$cc)), GR8)>;
1411 // Mask register copy, including
1412 // - copy between mask registers
1413 // - load/store mask registers
1414 // - copy from GPR to mask register and vice versa
1416 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1417 string OpcodeStr, RegisterClass KRC,
1418 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1419 let hasSideEffects = 0 in {
1420 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1421 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1423 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1424 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1425 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1427 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1428 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1432 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1434 RegisterClass KRC, RegisterClass GRC> {
1435 let hasSideEffects = 0 in {
1436 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1437 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1438 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1439 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1443 let Predicates = [HasDQI] in
1444 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1446 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1449 let Predicates = [HasAVX512] in
1450 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1452 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1455 let Predicates = [HasBWI] in {
1456 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1457 i32mem>, VEX, PD, VEX_W;
1458 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1462 let Predicates = [HasBWI] in {
1463 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1464 i64mem>, VEX, PS, VEX_W;
1465 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1469 // GR from/to mask register
1470 let Predicates = [HasDQI] in {
1471 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1472 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1473 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1474 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1476 let Predicates = [HasAVX512] in {
1477 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1478 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1479 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1480 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1482 let Predicates = [HasBWI] in {
1483 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1484 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1486 let Predicates = [HasBWI] in {
1487 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1488 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1492 let Predicates = [HasDQI] in {
1493 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1494 (KMOVBmk addr:$dst, VK8:$src)>;
1496 let Predicates = [HasAVX512] in {
1497 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1498 (KMOVWmk addr:$dst, VK16:$src)>;
1499 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1500 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1501 def : Pat<(i1 (load addr:$src)),
1502 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1503 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1504 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1506 let Predicates = [HasBWI] in {
1507 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1508 (KMOVDmk addr:$dst, VK32:$src)>;
1510 let Predicates = [HasBWI] in {
1511 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1512 (KMOVQmk addr:$dst, VK64:$src)>;
1515 let Predicates = [HasAVX512] in {
1516 def : Pat<(i1 (trunc (i64 GR64:$src))),
1517 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1520 def : Pat<(i1 (trunc (i32 GR32:$src))),
1521 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1523 def : Pat<(i1 (trunc (i8 GR8:$src))),
1525 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1527 def : Pat<(i1 (trunc (i16 GR16:$src))),
1529 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1532 def : Pat<(i32 (zext VK1:$src)),
1533 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1534 def : Pat<(i8 (zext VK1:$src)),
1537 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1538 def : Pat<(i64 (zext VK1:$src)),
1539 (AND64ri8 (SUBREG_TO_REG (i64 0),
1540 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1541 def : Pat<(i16 (zext VK1:$src)),
1543 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1545 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1546 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1547 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1548 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1550 let Predicates = [HasBWI] in {
1551 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1552 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1553 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1554 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1558 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1559 let Predicates = [HasAVX512] in {
1560 // GR from/to 8-bit mask without native support
1561 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1563 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1565 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1567 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1570 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1571 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1572 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1573 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1575 let Predicates = [HasBWI] in {
1576 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1577 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1578 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1579 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1582 // Mask unary operation
1584 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1585 RegisterClass KRC, SDPatternOperator OpNode,
1587 let Predicates = [prd] in
1588 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1589 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1590 [(set KRC:$dst, (OpNode KRC:$src))]>;
1593 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1594 SDPatternOperator OpNode> {
1595 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1597 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1598 HasAVX512>, VEX, PS;
1599 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1600 HasBWI>, VEX, PD, VEX_W;
1601 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1602 HasBWI>, VEX, PS, VEX_W;
1605 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1607 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1608 let Predicates = [HasAVX512] in
1609 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1611 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1612 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1614 defm : avx512_mask_unop_int<"knot", "KNOT">;
1616 let Predicates = [HasDQI] in
1617 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1618 let Predicates = [HasAVX512] in
1619 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1620 let Predicates = [HasBWI] in
1621 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1622 let Predicates = [HasBWI] in
1623 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1625 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1626 let Predicates = [HasAVX512] in {
1627 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1628 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1630 def : Pat<(not VK8:$src),
1632 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1635 // Mask binary operation
1636 // - KAND, KANDN, KOR, KXNOR, KXOR
1637 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1638 RegisterClass KRC, SDPatternOperator OpNode,
1640 let Predicates = [prd] in
1641 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1642 !strconcat(OpcodeStr,
1643 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1644 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1647 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1648 SDPatternOperator OpNode> {
1649 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1650 HasDQI>, VEX_4V, VEX_L, PD;
1651 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1652 HasAVX512>, VEX_4V, VEX_L, PS;
1653 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1654 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1655 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1656 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1659 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1660 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1662 let isCommutable = 1 in {
1663 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1664 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1665 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1666 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1668 let isCommutable = 0 in
1669 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1671 def : Pat<(xor VK1:$src1, VK1:$src2),
1672 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1673 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1675 def : Pat<(or VK1:$src1, VK1:$src2),
1676 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1677 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1679 def : Pat<(and VK1:$src1, VK1:$src2),
1680 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1681 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1683 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1684 let Predicates = [HasAVX512] in
1685 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1686 (i16 GR16:$src1), (i16 GR16:$src2)),
1687 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1688 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1689 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1692 defm : avx512_mask_binop_int<"kand", "KAND">;
1693 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1694 defm : avx512_mask_binop_int<"kor", "KOR">;
1695 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1696 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1698 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1699 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1700 let Predicates = [HasAVX512] in
1701 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1703 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1704 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1707 defm : avx512_binop_pat<and, KANDWrr>;
1708 defm : avx512_binop_pat<andn, KANDNWrr>;
1709 defm : avx512_binop_pat<or, KORWrr>;
1710 defm : avx512_binop_pat<xnor, KXNORWrr>;
1711 defm : avx512_binop_pat<xor, KXORWrr>;
1714 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1715 RegisterClass KRC> {
1716 let Predicates = [HasAVX512] in
1717 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1718 !strconcat(OpcodeStr,
1719 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1722 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1723 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1727 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1728 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1729 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1730 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1733 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1734 let Predicates = [HasAVX512] in
1735 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1736 (i16 GR16:$src1), (i16 GR16:$src2)),
1737 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1738 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1739 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1741 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1744 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1746 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1747 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1748 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1749 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1752 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1753 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1757 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1759 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1760 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1761 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1764 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1766 let Predicates = [HasAVX512] in
1767 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1768 !strconcat(OpcodeStr,
1769 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1770 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1773 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1775 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1779 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1780 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1782 // Mask setting all 0s or 1s
1783 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1784 let Predicates = [HasAVX512] in
1785 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1786 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1787 [(set KRC:$dst, (VT Val))]>;
1790 multiclass avx512_mask_setop_w<PatFrag Val> {
1791 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1792 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1795 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1796 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1798 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1799 let Predicates = [HasAVX512] in {
1800 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1801 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1802 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1803 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1804 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1806 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1807 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1809 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1810 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1812 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1813 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1815 let Predicates = [HasVLX] in {
1816 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1817 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1818 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1819 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1820 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1821 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1822 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1823 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1826 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1827 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1829 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1830 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1831 //===----------------------------------------------------------------------===//
1832 // AVX-512 - Aligned and unaligned load and store
1835 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1836 RegisterClass KRC, RegisterClass RC,
1837 ValueType vt, ValueType zvt, X86MemOperand memop,
1838 Domain d, bit IsReMaterializable = 1> {
1839 let hasSideEffects = 0 in {
1840 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1841 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1843 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1844 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1845 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1847 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1848 SchedRW = [WriteLoad] in
1849 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1850 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1851 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1854 let AddedComplexity = 20 in {
1855 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1856 let hasSideEffects = 0 in
1857 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1858 (ins RC:$src0, KRC:$mask, RC:$src1),
1859 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1860 "${dst} {${mask}}, $src1}"),
1861 [(set RC:$dst, (vt (vselect KRC:$mask,
1865 let mayLoad = 1, SchedRW = [WriteLoad] in
1866 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1867 (ins RC:$src0, KRC:$mask, memop:$src1),
1868 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1869 "${dst} {${mask}}, $src1}"),
1872 (vt (bitconvert (ld_frag addr:$src1))),
1876 let mayLoad = 1, SchedRW = [WriteLoad] in
1877 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1878 (ins KRC:$mask, memop:$src),
1879 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1880 "${dst} {${mask}} {z}, $src}"),
1883 (vt (bitconvert (ld_frag addr:$src))),
1884 (vt (bitconvert (zvt immAllZerosV))))))],
1889 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1890 string elty, string elsz, string vsz512,
1891 string vsz256, string vsz128, Domain d,
1892 Predicate prd, bit IsReMaterializable = 1> {
1893 let Predicates = [prd] in
1894 defm Z : avx512_load<opc, OpcodeStr,
1895 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1896 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1897 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1898 !cast<X86MemOperand>(elty##"512mem"), d,
1899 IsReMaterializable>, EVEX_V512;
1901 let Predicates = [prd, HasVLX] in {
1902 defm Z256 : avx512_load<opc, OpcodeStr,
1903 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1904 "v"##vsz256##elty##elsz, "v4i64")),
1905 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1906 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1907 !cast<X86MemOperand>(elty##"256mem"), d,
1908 IsReMaterializable>, EVEX_V256;
1910 defm Z128 : avx512_load<opc, OpcodeStr,
1911 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1912 "v"##vsz128##elty##elsz, "v2i64")),
1913 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1914 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1915 !cast<X86MemOperand>(elty##"128mem"), d,
1916 IsReMaterializable>, EVEX_V128;
1921 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1922 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1923 X86MemOperand memop, Domain d> {
1924 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1925 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1926 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1928 let Constraints = "$src1 = $dst" in
1929 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1930 (ins RC:$src1, KRC:$mask, RC:$src2),
1931 !strconcat(OpcodeStr,
1932 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1934 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1935 (ins KRC:$mask, RC:$src),
1936 !strconcat(OpcodeStr,
1937 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1938 [], d>, EVEX, EVEX_KZ;
1940 let mayStore = 1 in {
1941 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1943 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1944 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1945 (ins memop:$dst, KRC:$mask, RC:$src),
1946 !strconcat(OpcodeStr,
1947 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1948 [], d>, EVEX, EVEX_K;
1953 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1954 string st_suff_512, string st_suff_256,
1955 string st_suff_128, string elty, string elsz,
1956 string vsz512, string vsz256, string vsz128,
1957 Domain d, Predicate prd> {
1958 let Predicates = [prd] in
1959 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1960 !cast<ValueType>("v"##vsz512##elty##elsz),
1961 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1962 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1964 let Predicates = [prd, HasVLX] in {
1965 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1966 !cast<ValueType>("v"##vsz256##elty##elsz),
1967 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1968 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1970 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1971 !cast<ValueType>("v"##vsz128##elty##elsz),
1972 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1973 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1977 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1978 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1979 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1980 "512", "256", "", "f", "32", "16", "8", "4",
1981 SSEPackedSingle, HasAVX512>,
1982 PS, EVEX_CD8<32, CD8VF>;
1984 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1985 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1986 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1987 "512", "256", "", "f", "64", "8", "4", "2",
1988 SSEPackedDouble, HasAVX512>,
1989 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1991 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1992 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1993 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1994 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1995 PS, EVEX_CD8<32, CD8VF>;
1997 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1998 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1999 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2000 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2001 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2003 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2004 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2005 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2007 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2008 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2009 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2011 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2013 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2015 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2017 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2020 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2021 "16", "8", "4", SSEPackedInt, HasAVX512>,
2022 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2023 "512", "256", "", "i", "32", "16", "8", "4",
2024 SSEPackedInt, HasAVX512>,
2025 PD, EVEX_CD8<32, CD8VF>;
2027 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2028 "8", "4", "2", SSEPackedInt, HasAVX512>,
2029 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2030 "512", "256", "", "i", "64", "8", "4", "2",
2031 SSEPackedInt, HasAVX512>,
2032 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2034 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2035 "64", "32", "16", SSEPackedInt, HasBWI>,
2036 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2037 "i", "8", "64", "32", "16", SSEPackedInt,
2038 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2040 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2041 "32", "16", "8", SSEPackedInt, HasBWI>,
2042 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2043 "i", "16", "32", "16", "8", SSEPackedInt,
2044 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2046 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2047 "16", "8", "4", SSEPackedInt, HasAVX512>,
2048 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2049 "i", "32", "16", "8", "4", SSEPackedInt,
2050 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2052 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2053 "8", "4", "2", SSEPackedInt, HasAVX512>,
2054 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2055 "i", "64", "8", "4", "2", SSEPackedInt,
2056 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2058 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2059 (v16i32 immAllZerosV), GR16:$mask)),
2060 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2062 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2063 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2064 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2066 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2068 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2070 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2072 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2075 let AddedComplexity = 20 in {
2076 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2077 (bc_v8i64 (v16i32 immAllZerosV)))),
2078 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2080 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2081 (v8i64 VR512:$src))),
2082 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2085 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2086 (v16i32 immAllZerosV))),
2087 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2089 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2090 (v16i32 VR512:$src))),
2091 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2094 // Move Int Doubleword to Packed Double Int
2096 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2097 "vmovd\t{$src, $dst|$dst, $src}",
2099 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2101 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2102 "vmovd\t{$src, $dst|$dst, $src}",
2104 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2105 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2106 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2107 "vmovq\t{$src, $dst|$dst, $src}",
2109 (v2i64 (scalar_to_vector GR64:$src)))],
2110 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2111 let isCodeGenOnly = 1 in {
2112 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2113 "vmovq\t{$src, $dst|$dst, $src}",
2114 [(set FR64:$dst, (bitconvert GR64:$src))],
2115 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2116 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2117 "vmovq\t{$src, $dst|$dst, $src}",
2118 [(set GR64:$dst, (bitconvert FR64:$src))],
2119 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2121 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2122 "vmovq\t{$src, $dst|$dst, $src}",
2123 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2124 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2125 EVEX_CD8<64, CD8VT1>;
2127 // Move Int Doubleword to Single Scalar
2129 let isCodeGenOnly = 1 in {
2130 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2131 "vmovd\t{$src, $dst|$dst, $src}",
2132 [(set FR32X:$dst, (bitconvert GR32:$src))],
2133 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2135 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2136 "vmovd\t{$src, $dst|$dst, $src}",
2137 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2138 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2141 // Move doubleword from xmm register to r/m32
2143 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2144 "vmovd\t{$src, $dst|$dst, $src}",
2145 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2146 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2148 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2149 (ins i32mem:$dst, VR128X:$src),
2150 "vmovd\t{$src, $dst|$dst, $src}",
2151 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2152 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2153 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2155 // Move quadword from xmm1 register to r/m64
2157 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2158 "vmovq\t{$src, $dst|$dst, $src}",
2159 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2161 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2162 Requires<[HasAVX512, In64BitMode]>;
2164 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2165 (ins i64mem:$dst, VR128X:$src),
2166 "vmovq\t{$src, $dst|$dst, $src}",
2167 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2168 addr:$dst)], IIC_SSE_MOVDQ>,
2169 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2170 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2172 // Move Scalar Single to Double Int
2174 let isCodeGenOnly = 1 in {
2175 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2177 "vmovd\t{$src, $dst|$dst, $src}",
2178 [(set GR32:$dst, (bitconvert FR32X:$src))],
2179 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2180 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2181 (ins i32mem:$dst, FR32X:$src),
2182 "vmovd\t{$src, $dst|$dst, $src}",
2183 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2184 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2187 // Move Quadword Int to Packed Quadword Int
2189 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2191 "vmovq\t{$src, $dst|$dst, $src}",
2193 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2194 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2196 //===----------------------------------------------------------------------===//
2197 // AVX-512 MOVSS, MOVSD
2198 //===----------------------------------------------------------------------===//
2200 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2201 SDNode OpNode, ValueType vt,
2202 X86MemOperand x86memop, PatFrag mem_pat> {
2203 let hasSideEffects = 0 in {
2204 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2205 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2206 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2207 (scalar_to_vector RC:$src2))))],
2208 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2209 let Constraints = "$src1 = $dst" in
2210 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2211 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2213 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2214 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2215 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2216 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2217 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2219 let mayStore = 1 in {
2220 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2221 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2222 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2224 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2225 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2226 [], IIC_SSE_MOV_S_MR>,
2227 EVEX, VEX_LIG, EVEX_K;
2229 } //hasSideEffects = 0
2232 let ExeDomain = SSEPackedSingle in
2233 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2234 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2236 let ExeDomain = SSEPackedDouble in
2237 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2238 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2240 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2241 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2242 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2244 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2245 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2246 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2248 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2249 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2250 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2252 // For the disassembler
2253 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2254 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2255 (ins VR128X:$src1, FR32X:$src2),
2256 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2258 XS, EVEX_4V, VEX_LIG;
2259 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2260 (ins VR128X:$src1, FR64X:$src2),
2261 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2263 XD, EVEX_4V, VEX_LIG, VEX_W;
2266 let Predicates = [HasAVX512] in {
2267 let AddedComplexity = 15 in {
2268 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2269 // MOVS{S,D} to the lower bits.
2270 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2271 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2272 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2273 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2274 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2275 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2276 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2277 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2279 // Move low f32 and clear high bits.
2280 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2281 (SUBREG_TO_REG (i32 0),
2282 (VMOVSSZrr (v4f32 (V_SET0)),
2283 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2284 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2285 (SUBREG_TO_REG (i32 0),
2286 (VMOVSSZrr (v4i32 (V_SET0)),
2287 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2290 let AddedComplexity = 20 in {
2291 // MOVSSrm zeros the high parts of the register; represent this
2292 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2293 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2294 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2295 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2296 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2297 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2298 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2300 // MOVSDrm zeros the high parts of the register; represent this
2301 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2302 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2303 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2304 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2305 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2306 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2307 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2308 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2309 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2310 def : Pat<(v2f64 (X86vzload addr:$src)),
2311 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2313 // Represent the same patterns above but in the form they appear for
2315 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2316 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2317 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2318 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2319 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2320 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2321 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2322 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2323 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2325 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2326 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2327 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2328 FR32X:$src)), sub_xmm)>;
2329 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2330 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2331 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2332 FR64X:$src)), sub_xmm)>;
2333 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2334 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2335 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2337 // Move low f64 and clear high bits.
2338 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2339 (SUBREG_TO_REG (i32 0),
2340 (VMOVSDZrr (v2f64 (V_SET0)),
2341 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2343 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2344 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2345 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2347 // Extract and store.
2348 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2350 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2351 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2353 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2355 // Shuffle with VMOVSS
2356 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2357 (VMOVSSZrr (v4i32 VR128X:$src1),
2358 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2359 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2360 (VMOVSSZrr (v4f32 VR128X:$src1),
2361 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2364 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2365 (SUBREG_TO_REG (i32 0),
2366 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2367 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2369 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2370 (SUBREG_TO_REG (i32 0),
2371 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2372 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2375 // Shuffle with VMOVSD
2376 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2377 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2378 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2379 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2380 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2381 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2382 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2383 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2386 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2387 (SUBREG_TO_REG (i32 0),
2388 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2389 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2391 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2392 (SUBREG_TO_REG (i32 0),
2393 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2394 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2397 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2398 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2399 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2400 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2401 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2402 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2403 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2404 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2407 let AddedComplexity = 15 in
2408 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2410 "vmovq\t{$src, $dst|$dst, $src}",
2411 [(set VR128X:$dst, (v2i64 (X86vzmovl
2412 (v2i64 VR128X:$src))))],
2413 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2415 let AddedComplexity = 20 in
2416 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2418 "vmovq\t{$src, $dst|$dst, $src}",
2419 [(set VR128X:$dst, (v2i64 (X86vzmovl
2420 (loadv2i64 addr:$src))))],
2421 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2422 EVEX_CD8<8, CD8VT8>;
2424 let Predicates = [HasAVX512] in {
2425 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2426 let AddedComplexity = 20 in {
2427 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2428 (VMOVDI2PDIZrm addr:$src)>;
2429 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2430 (VMOV64toPQIZrr GR64:$src)>;
2431 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2432 (VMOVDI2PDIZrr GR32:$src)>;
2434 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2435 (VMOVDI2PDIZrm addr:$src)>;
2436 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2437 (VMOVDI2PDIZrm addr:$src)>;
2438 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2439 (VMOVZPQILo2PQIZrm addr:$src)>;
2440 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2441 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2442 def : Pat<(v2i64 (X86vzload addr:$src)),
2443 (VMOVZPQILo2PQIZrm addr:$src)>;
2446 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2447 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2448 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2449 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2450 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2451 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2452 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2455 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2456 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2458 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2459 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2461 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2462 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2464 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2465 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2467 //===----------------------------------------------------------------------===//
2468 // AVX-512 - Non-temporals
2469 //===----------------------------------------------------------------------===//
2470 let SchedRW = [WriteLoad] in {
2471 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2472 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2473 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2474 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2475 EVEX_CD8<64, CD8VF>;
2477 let Predicates = [HasAVX512, HasVLX] in {
2478 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2480 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2481 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2482 EVEX_CD8<64, CD8VF>;
2484 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2486 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2487 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2488 EVEX_CD8<64, CD8VF>;
2492 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2493 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2494 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2495 let SchedRW = [WriteStore], mayStore = 1,
2496 AddedComplexity = 400 in
2497 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2498 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2499 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2502 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2503 string elty, string elsz, string vsz512,
2504 string vsz256, string vsz128, Domain d,
2505 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2506 let Predicates = [prd] in
2507 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2508 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2509 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2512 let Predicates = [prd, HasVLX] in {
2513 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2514 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2515 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2518 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2519 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2520 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2525 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2526 "i", "64", "8", "4", "2", SSEPackedInt,
2527 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2529 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2530 "f", "64", "8", "4", "2", SSEPackedDouble,
2531 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2533 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2534 "f", "32", "16", "8", "4", SSEPackedSingle,
2535 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2537 //===----------------------------------------------------------------------===//
2538 // AVX-512 - Integer arithmetic
2540 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2541 X86VectorVTInfo _, OpndItins itins,
2542 bit IsCommutable = 0> {
2543 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2544 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2545 "$src2, $src1", "$src1, $src2",
2546 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2547 itins.rr, IsCommutable>,
2548 AVX512BIBase, EVEX_4V;
2551 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2552 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2553 "$src2, $src1", "$src1, $src2",
2554 (_.VT (OpNode _.RC:$src1,
2555 (bitconvert (_.LdFrag addr:$src2)))),
2557 AVX512BIBase, EVEX_4V;
2560 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2561 X86VectorVTInfo _, OpndItins itins,
2562 bit IsCommutable = 0> :
2563 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2565 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2566 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2567 "${src2}"##_.BroadcastStr##", $src1",
2568 "$src1, ${src2}"##_.BroadcastStr,
2569 (_.VT (OpNode _.RC:$src1,
2571 (_.ScalarLdFrag addr:$src2)))),
2573 AVX512BIBase, EVEX_4V, EVEX_B;
2576 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2577 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2578 Predicate prd, bit IsCommutable = 0> {
2579 let Predicates = [prd] in
2580 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2581 IsCommutable>, EVEX_V512;
2583 let Predicates = [prd, HasVLX] in {
2584 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2585 IsCommutable>, EVEX_V256;
2586 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2587 IsCommutable>, EVEX_V128;
2591 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2592 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2593 Predicate prd, bit IsCommutable = 0> {
2594 let Predicates = [prd] in
2595 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2596 IsCommutable>, EVEX_V512;
2598 let Predicates = [prd, HasVLX] in {
2599 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2600 IsCommutable>, EVEX_V256;
2601 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2602 IsCommutable>, EVEX_V128;
2606 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2607 OpndItins itins, Predicate prd,
2608 bit IsCommutable = 0> {
2609 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2610 itins, prd, IsCommutable>,
2611 VEX_W, EVEX_CD8<64, CD8VF>;
2614 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2615 OpndItins itins, Predicate prd,
2616 bit IsCommutable = 0> {
2617 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2618 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2621 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2622 OpndItins itins, Predicate prd,
2623 bit IsCommutable = 0> {
2624 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2625 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2628 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2629 OpndItins itins, Predicate prd,
2630 bit IsCommutable = 0> {
2631 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2632 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2635 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2636 SDNode OpNode, OpndItins itins, Predicate prd,
2637 bit IsCommutable = 0> {
2638 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2641 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2645 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2646 SDNode OpNode, OpndItins itins, Predicate prd,
2647 bit IsCommutable = 0> {
2648 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2651 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2655 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2656 bits<8> opc_d, bits<8> opc_q,
2657 string OpcodeStr, SDNode OpNode,
2658 OpndItins itins, bit IsCommutable = 0> {
2659 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2660 itins, HasAVX512, IsCommutable>,
2661 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2662 itins, HasBWI, IsCommutable>;
2665 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2666 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2667 PatFrag memop_frag, X86MemOperand x86memop,
2668 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2669 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2670 let isCommutable = IsCommutable in
2672 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2673 (ins RC:$src1, RC:$src2),
2674 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2676 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2677 (ins KRC:$mask, RC:$src1, RC:$src2),
2678 !strconcat(OpcodeStr,
2679 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2680 [], itins.rr>, EVEX_4V, EVEX_K;
2681 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2682 (ins KRC:$mask, RC:$src1, RC:$src2),
2683 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2684 "|$dst {${mask}} {z}, $src1, $src2}"),
2685 [], itins.rr>, EVEX_4V, EVEX_KZ;
2687 let mayLoad = 1 in {
2688 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2689 (ins RC:$src1, x86memop:$src2),
2690 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2692 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2693 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2694 !strconcat(OpcodeStr,
2695 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2696 [], itins.rm>, EVEX_4V, EVEX_K;
2697 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2698 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2699 !strconcat(OpcodeStr,
2700 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2701 [], itins.rm>, EVEX_4V, EVEX_KZ;
2702 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2703 (ins RC:$src1, x86scalar_mop:$src2),
2704 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2705 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2706 [], itins.rm>, EVEX_4V, EVEX_B;
2707 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2708 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2709 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2710 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2712 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2713 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2714 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2715 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2716 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2718 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2722 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2723 SSE_INTALU_ITINS_P, 1>;
2724 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2725 SSE_INTALU_ITINS_P, 0>;
2726 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2727 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2728 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2729 SSE_INTALU_ITINS_P, HasBWI, 1>;
2730 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2731 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2733 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2734 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2735 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2736 EVEX_CD8<64, CD8VF>, VEX_W;
2738 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2739 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2740 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2742 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2743 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2745 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2746 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2747 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2748 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2749 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2750 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2752 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2753 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2754 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2755 SSE_INTALU_ITINS_P, HasBWI, 1>;
2756 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2757 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2759 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2760 SSE_INTALU_ITINS_P, HasBWI, 1>;
2761 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2762 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2763 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2764 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2766 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2767 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2768 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2769 SSE_INTALU_ITINS_P, HasBWI, 1>;
2770 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2771 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2773 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2774 SSE_INTALU_ITINS_P, HasBWI, 1>;
2775 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2776 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2777 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2778 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2780 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2781 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2782 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2783 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2784 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2785 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2786 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2787 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2788 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2789 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2790 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2791 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2792 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2793 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2794 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2795 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2796 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2797 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2798 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2799 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2800 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2801 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2802 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2803 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2804 //===----------------------------------------------------------------------===//
2805 // AVX-512 - Unpack Instructions
2806 //===----------------------------------------------------------------------===//
2808 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2809 PatFrag mem_frag, RegisterClass RC,
2810 X86MemOperand x86memop, string asm,
2812 def rr : AVX512PI<opc, MRMSrcReg,
2813 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2815 (vt (OpNode RC:$src1, RC:$src2)))],
2817 def rm : AVX512PI<opc, MRMSrcMem,
2818 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2820 (vt (OpNode RC:$src1,
2821 (bitconvert (mem_frag addr:$src2)))))],
2825 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2826 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2827 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2828 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2829 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2830 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2831 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2832 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2833 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2834 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2835 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2836 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2838 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2839 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2840 X86MemOperand x86memop> {
2841 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2842 (ins RC:$src1, RC:$src2),
2843 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2844 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2845 IIC_SSE_UNPCK>, EVEX_4V;
2846 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2847 (ins RC:$src1, x86memop:$src2),
2848 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2849 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2850 (bitconvert (memop_frag addr:$src2)))))],
2851 IIC_SSE_UNPCK>, EVEX_4V;
2853 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2854 VR512, memopv16i32, i512mem>, EVEX_V512,
2855 EVEX_CD8<32, CD8VF>;
2856 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2857 VR512, memopv8i64, i512mem>, EVEX_V512,
2858 VEX_W, EVEX_CD8<64, CD8VF>;
2859 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2860 VR512, memopv16i32, i512mem>, EVEX_V512,
2861 EVEX_CD8<32, CD8VF>;
2862 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2863 VR512, memopv8i64, i512mem>, EVEX_V512,
2864 VEX_W, EVEX_CD8<64, CD8VF>;
2865 //===----------------------------------------------------------------------===//
2869 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2870 SDNode OpNode, PatFrag mem_frag,
2871 X86MemOperand x86memop, ValueType OpVT> {
2872 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2873 (ins RC:$src1, i8imm:$src2),
2874 !strconcat(OpcodeStr,
2875 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2877 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2879 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2880 (ins x86memop:$src1, i8imm:$src2),
2881 !strconcat(OpcodeStr,
2882 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2884 (OpVT (OpNode (mem_frag addr:$src1),
2885 (i8 imm:$src2))))]>, EVEX;
2888 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2889 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2891 let ExeDomain = SSEPackedSingle in
2892 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2893 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2894 EVEX_CD8<32, CD8VF>;
2895 let ExeDomain = SSEPackedDouble in
2896 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2897 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2898 VEX_W, EVEX_CD8<32, CD8VF>;
2900 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2901 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2902 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2903 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2905 //===----------------------------------------------------------------------===//
2906 // AVX-512 Logical Instructions
2907 //===----------------------------------------------------------------------===//
2909 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2910 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2911 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2912 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2913 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2914 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2915 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2916 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2918 //===----------------------------------------------------------------------===//
2919 // AVX-512 FP arithmetic
2920 //===----------------------------------------------------------------------===//
2922 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2924 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2925 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2926 EVEX_CD8<32, CD8VT1>;
2927 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2928 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2929 EVEX_CD8<64, CD8VT1>;
2932 let isCommutable = 1 in {
2933 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2934 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2935 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2936 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2938 let isCommutable = 0 in {
2939 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2940 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2943 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2945 RegisterClass RC, ValueType vt,
2946 X86MemOperand x86memop, PatFrag mem_frag,
2947 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2949 Domain d, OpndItins itins, bit commutable> {
2950 let isCommutable = commutable in {
2951 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2952 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2953 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2956 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2957 !strconcat(OpcodeStr,
2958 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2959 [], itins.rr, d>, EVEX_4V, EVEX_K;
2961 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2962 !strconcat(OpcodeStr,
2963 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2964 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2967 let mayLoad = 1 in {
2968 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2969 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2970 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2971 itins.rm, d>, EVEX_4V;
2973 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2974 (ins RC:$src1, x86scalar_mop:$src2),
2975 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2976 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2977 [(set RC:$dst, (OpNode RC:$src1,
2978 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2979 itins.rm, d>, EVEX_4V, EVEX_B;
2981 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2982 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2983 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2984 [], itins.rm, d>, EVEX_4V, EVEX_K;
2986 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2987 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2988 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2989 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2991 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2992 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2993 " \t{${src2}", BrdcstStr,
2994 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2995 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2997 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2998 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2999 " \t{${src2}", BrdcstStr,
3000 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3002 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
3006 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
3007 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3008 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3010 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
3011 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3012 SSE_ALU_ITINS_P.d, 1>,
3013 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3015 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
3016 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3017 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3018 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
3019 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3020 SSE_ALU_ITINS_P.d, 1>,
3021 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3023 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
3024 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3025 SSE_ALU_ITINS_P.s, 1>,
3026 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3027 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
3028 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3029 SSE_ALU_ITINS_P.s, 1>,
3030 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3032 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
3033 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3034 SSE_ALU_ITINS_P.d, 1>,
3035 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3036 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
3037 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3038 SSE_ALU_ITINS_P.d, 1>,
3039 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3041 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
3042 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3043 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3044 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
3045 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3046 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3048 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
3049 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3050 SSE_ALU_ITINS_P.d, 0>,
3051 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3052 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
3053 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3054 SSE_ALU_ITINS_P.d, 0>,
3055 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3057 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3058 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3059 (i16 -1), FROUND_CURRENT)),
3060 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3062 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3063 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3064 (i8 -1), FROUND_CURRENT)),
3065 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3067 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3068 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3069 (i16 -1), FROUND_CURRENT)),
3070 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3072 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3073 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3074 (i8 -1), FROUND_CURRENT)),
3075 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3076 //===----------------------------------------------------------------------===//
3077 // AVX-512 VPTESTM instructions
3078 //===----------------------------------------------------------------------===//
3080 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3081 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3082 SDNode OpNode, ValueType vt> {
3083 def rr : AVX512PI<opc, MRMSrcReg,
3084 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3085 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3086 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3087 SSEPackedInt>, EVEX_4V;
3088 def rm : AVX512PI<opc, MRMSrcMem,
3089 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3090 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3091 [(set KRC:$dst, (OpNode (vt RC:$src1),
3092 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3095 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3096 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3097 EVEX_CD8<32, CD8VF>;
3098 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3099 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3100 EVEX_CD8<64, CD8VF>;
3102 let Predicates = [HasCDI] in {
3103 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3104 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3105 EVEX_CD8<32, CD8VF>;
3106 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3107 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3108 EVEX_CD8<64, CD8VF>;
3111 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3112 (v16i32 VR512:$src2), (i16 -1))),
3113 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3115 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3116 (v8i64 VR512:$src2), (i8 -1))),
3117 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3118 //===----------------------------------------------------------------------===//
3119 // AVX-512 Shift instructions
3120 //===----------------------------------------------------------------------===//
3121 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3122 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3123 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3124 RegisterClass KRC> {
3125 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3126 (ins RC:$src1, i8imm:$src2),
3127 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3128 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
3129 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3130 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
3131 (ins KRC:$mask, RC:$src1, i8imm:$src2),
3132 !strconcat(OpcodeStr,
3133 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3134 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3135 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3136 (ins x86memop:$src1, i8imm:$src2),
3137 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3138 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
3139 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3140 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
3141 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
3142 !strconcat(OpcodeStr,
3143 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3144 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3147 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3148 RegisterClass RC, ValueType vt, ValueType SrcVT,
3149 PatFrag bc_frag, RegisterClass KRC> {
3150 // src2 is always 128-bit
3151 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3152 (ins RC:$src1, VR128X:$src2),
3153 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3154 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3155 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3156 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3157 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3158 !strconcat(OpcodeStr,
3159 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3160 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3161 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3162 (ins RC:$src1, i128mem:$src2),
3163 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 [(set RC:$dst, (vt (OpNode RC:$src1,
3165 (bc_frag (memopv2i64 addr:$src2)))))],
3166 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3167 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3168 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3169 !strconcat(OpcodeStr,
3170 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3171 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3174 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3175 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3176 EVEX_V512, EVEX_CD8<32, CD8VF>;
3177 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3178 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3179 EVEX_CD8<32, CD8VQ>;
3181 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3182 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3183 EVEX_CD8<64, CD8VF>, VEX_W;
3184 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3185 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3186 EVEX_CD8<64, CD8VQ>, VEX_W;
3188 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3189 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3190 EVEX_CD8<32, CD8VF>;
3191 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3192 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3193 EVEX_CD8<32, CD8VQ>;
3195 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3196 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3197 EVEX_CD8<64, CD8VF>, VEX_W;
3198 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3199 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3200 EVEX_CD8<64, CD8VQ>, VEX_W;
3202 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3203 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3204 EVEX_V512, EVEX_CD8<32, CD8VF>;
3205 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3206 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3207 EVEX_CD8<32, CD8VQ>;
3209 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3210 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3211 EVEX_CD8<64, CD8VF>, VEX_W;
3212 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3213 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3214 EVEX_CD8<64, CD8VQ>, VEX_W;
3216 //===-------------------------------------------------------------------===//
3217 // Variable Bit Shifts
3218 //===-------------------------------------------------------------------===//
3219 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3220 RegisterClass RC, ValueType vt,
3221 X86MemOperand x86memop, PatFrag mem_frag> {
3222 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3223 (ins RC:$src1, RC:$src2),
3224 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3226 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3228 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3229 (ins RC:$src1, x86memop:$src2),
3230 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3232 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3236 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3237 i512mem, memopv16i32>, EVEX_V512,
3238 EVEX_CD8<32, CD8VF>;
3239 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3240 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3241 EVEX_CD8<64, CD8VF>;
3242 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3243 i512mem, memopv16i32>, EVEX_V512,
3244 EVEX_CD8<32, CD8VF>;
3245 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3246 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3247 EVEX_CD8<64, CD8VF>;
3248 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3249 i512mem, memopv16i32>, EVEX_V512,
3250 EVEX_CD8<32, CD8VF>;
3251 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3252 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3253 EVEX_CD8<64, CD8VF>;
3255 //===----------------------------------------------------------------------===//
3256 // AVX-512 - MOVDDUP
3257 //===----------------------------------------------------------------------===//
3259 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3260 X86MemOperand x86memop, PatFrag memop_frag> {
3261 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3262 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3263 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3264 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3265 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3267 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3270 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3271 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3272 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3273 (VMOVDDUPZrm addr:$src)>;
3275 //===---------------------------------------------------------------------===//
3276 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3277 //===---------------------------------------------------------------------===//
3278 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3279 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3280 X86MemOperand x86memop> {
3281 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3282 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3283 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3285 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3286 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3287 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3290 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3291 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3292 EVEX_CD8<32, CD8VF>;
3293 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3294 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3295 EVEX_CD8<32, CD8VF>;
3297 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3298 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3299 (VMOVSHDUPZrm addr:$src)>;
3300 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3301 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3302 (VMOVSLDUPZrm addr:$src)>;
3304 //===----------------------------------------------------------------------===//
3305 // Move Low to High and High to Low packed FP Instructions
3306 //===----------------------------------------------------------------------===//
3307 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3308 (ins VR128X:$src1, VR128X:$src2),
3309 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3310 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3311 IIC_SSE_MOV_LH>, EVEX_4V;
3312 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3313 (ins VR128X:$src1, VR128X:$src2),
3314 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3315 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3316 IIC_SSE_MOV_LH>, EVEX_4V;
3318 let Predicates = [HasAVX512] in {
3320 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3321 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3322 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3323 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3326 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3327 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3330 //===----------------------------------------------------------------------===//
3331 // FMA - Fused Multiply Operations
3334 let Constraints = "$src1 = $dst" in {
3335 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3336 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3337 SDPatternOperator OpNode = null_frag> {
3338 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3339 (ins _.RC:$src2, _.RC:$src3),
3340 OpcodeStr, "$src3, $src2", "$src2, $src3",
3341 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3345 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3346 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3347 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3348 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3349 (_.MemOpFrag addr:$src3))))]>;
3350 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3351 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3352 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3353 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3354 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3355 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3357 } // Constraints = "$src1 = $dst"
3359 multiclass avx512_fma3p_forms<bits<8> opc213,
3360 string OpcodeStr, X86VectorVTInfo VTI,
3361 SDPatternOperator OpNode> {
3362 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3364 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3367 let ExeDomain = SSEPackedSingle in {
3368 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, "vfmadd",
3369 v16f32_info, X86Fmadd>;
3370 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, "vfmsub",
3371 v16f32_info, X86Fmsub>;
3372 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, "vfmaddsub",
3373 v16f32_info, X86Fmaddsub>;
3374 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, "vfmsubadd",
3375 v16f32_info, X86Fmsubadd>;
3376 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, "vfnmadd",
3377 v16f32_info, X86Fnmadd>;
3378 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, "vfnmsub",
3379 v16f32_info, X86Fnmsub>;
3381 let ExeDomain = SSEPackedDouble in {
3382 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, "vfmadd",
3383 v8f64_info, X86Fmadd>, VEX_W;
3384 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, "vfmsub",
3385 v8f64_info, X86Fmsub>, VEX_W;
3386 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, "vfmaddsub",
3387 v8f64_info, X86Fmaddsub>, VEX_W;
3388 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, "vfmsubadd",
3389 v8f64_info, X86Fmsubadd>, VEX_W;
3390 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, "vfnmadd",
3391 v8f64_info, X86Fnmadd>, VEX_W;
3392 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, "vfnmsub",
3393 v8f64_info, X86Fnmsub>, VEX_W;
3396 let Constraints = "$src1 = $dst" in {
3397 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3398 X86VectorVTInfo _> {
3400 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3401 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3402 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3403 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3405 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3406 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3407 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3408 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3410 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3411 (_.ScalarLdFrag addr:$src2))),
3412 _.RC:$src3))]>, EVEX_B;
3414 } // Constraints = "$src1 = $dst"
3417 let ExeDomain = SSEPackedSingle in {
3418 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3420 EVEX_V512, EVEX_CD8<32, CD8VF>;
3421 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3423 EVEX_V512, EVEX_CD8<32, CD8VF>;
3424 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3426 EVEX_V512, EVEX_CD8<32, CD8VF>;
3427 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3429 EVEX_V512, EVEX_CD8<32, CD8VF>;
3430 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3432 EVEX_V512, EVEX_CD8<32, CD8VF>;
3433 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3435 EVEX_V512, EVEX_CD8<32, CD8VF>;
3437 let ExeDomain = SSEPackedDouble in {
3438 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3440 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3441 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3443 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3444 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3446 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3447 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3449 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3450 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3452 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3453 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3455 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3459 let Constraints = "$src1 = $dst" in {
3460 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3461 RegisterClass RC, ValueType OpVT,
3462 X86MemOperand x86memop, Operand memop,
3464 let isCommutable = 1 in
3465 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3466 (ins RC:$src1, RC:$src2, RC:$src3),
3467 !strconcat(OpcodeStr,
3468 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3470 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3472 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3473 (ins RC:$src1, RC:$src2, f128mem:$src3),
3474 !strconcat(OpcodeStr,
3475 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3477 (OpVT (OpNode RC:$src2, RC:$src1,
3478 (mem_frag addr:$src3))))]>;
3481 } // Constraints = "$src1 = $dst"
3483 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3484 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3485 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3486 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3487 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3488 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3489 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3490 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3491 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3492 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3493 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3494 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3495 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3496 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3497 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3498 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3500 //===----------------------------------------------------------------------===//
3501 // AVX-512 Scalar convert from sign integer to float/double
3502 //===----------------------------------------------------------------------===//
3504 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3505 X86MemOperand x86memop, string asm> {
3506 let hasSideEffects = 0 in {
3507 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3508 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3511 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3512 (ins DstRC:$src1, x86memop:$src),
3513 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3515 } // hasSideEffects = 0
3517 let Predicates = [HasAVX512] in {
3518 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3519 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3520 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3521 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3522 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3523 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3524 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3525 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3527 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3528 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3529 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3530 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3531 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3532 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3533 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3534 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3536 def : Pat<(f32 (sint_to_fp GR32:$src)),
3537 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3538 def : Pat<(f32 (sint_to_fp GR64:$src)),
3539 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3540 def : Pat<(f64 (sint_to_fp GR32:$src)),
3541 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3542 def : Pat<(f64 (sint_to_fp GR64:$src)),
3543 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3545 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3546 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3547 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3548 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3549 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3550 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3551 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3552 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3554 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3555 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3556 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3557 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3558 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3559 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3560 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3561 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3563 def : Pat<(f32 (uint_to_fp GR32:$src)),
3564 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3565 def : Pat<(f32 (uint_to_fp GR64:$src)),
3566 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3567 def : Pat<(f64 (uint_to_fp GR32:$src)),
3568 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3569 def : Pat<(f64 (uint_to_fp GR64:$src)),
3570 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3573 //===----------------------------------------------------------------------===//
3574 // AVX-512 Scalar convert from float/double to integer
3575 //===----------------------------------------------------------------------===//
3576 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3577 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3579 let hasSideEffects = 0 in {
3580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3581 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3582 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3583 Requires<[HasAVX512]>;
3585 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3586 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3587 Requires<[HasAVX512]>;
3588 } // hasSideEffects = 0
3590 let Predicates = [HasAVX512] in {
3591 // Convert float/double to signed/unsigned int 32/64
3592 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3593 ssmem, sse_load_f32, "cvtss2si">,
3594 XS, EVEX_CD8<32, CD8VT1>;
3595 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3596 ssmem, sse_load_f32, "cvtss2si">,
3597 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3598 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3599 ssmem, sse_load_f32, "cvtss2usi">,
3600 XS, EVEX_CD8<32, CD8VT1>;
3601 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3602 int_x86_avx512_cvtss2usi64, ssmem,
3603 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3604 EVEX_CD8<32, CD8VT1>;
3605 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3606 sdmem, sse_load_f64, "cvtsd2si">,
3607 XD, EVEX_CD8<64, CD8VT1>;
3608 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3609 sdmem, sse_load_f64, "cvtsd2si">,
3610 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3611 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3612 sdmem, sse_load_f64, "cvtsd2usi">,
3613 XD, EVEX_CD8<64, CD8VT1>;
3614 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3615 int_x86_avx512_cvtsd2usi64, sdmem,
3616 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3617 EVEX_CD8<64, CD8VT1>;
3619 let isCodeGenOnly = 1 in {
3620 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3621 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3622 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3623 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3624 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3625 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3626 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3627 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3628 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3629 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3630 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3631 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3633 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3634 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3635 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3636 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3637 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3638 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3639 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3640 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3641 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3642 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3643 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3644 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3645 } // isCodeGenOnly = 1
3647 // Convert float/double to signed/unsigned int 32/64 with truncation
3648 let isCodeGenOnly = 1 in {
3649 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3650 ssmem, sse_load_f32, "cvttss2si">,
3651 XS, EVEX_CD8<32, CD8VT1>;
3652 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3653 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3654 "cvttss2si">, XS, VEX_W,
3655 EVEX_CD8<32, CD8VT1>;
3656 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3657 sdmem, sse_load_f64, "cvttsd2si">, XD,
3658 EVEX_CD8<64, CD8VT1>;
3659 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3660 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3661 "cvttsd2si">, XD, VEX_W,
3662 EVEX_CD8<64, CD8VT1>;
3663 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3664 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3665 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3666 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3667 int_x86_avx512_cvttss2usi64, ssmem,
3668 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3669 EVEX_CD8<32, CD8VT1>;
3670 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3671 int_x86_avx512_cvttsd2usi,
3672 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3673 EVEX_CD8<64, CD8VT1>;
3674 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3675 int_x86_avx512_cvttsd2usi64, sdmem,
3676 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3677 EVEX_CD8<64, CD8VT1>;
3678 } // isCodeGenOnly = 1
3680 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3681 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3683 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3684 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3685 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3686 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3687 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3688 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3691 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3692 loadf32, "cvttss2si">, XS,
3693 EVEX_CD8<32, CD8VT1>;
3694 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3695 loadf32, "cvttss2usi">, XS,
3696 EVEX_CD8<32, CD8VT1>;
3697 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3698 loadf32, "cvttss2si">, XS, VEX_W,
3699 EVEX_CD8<32, CD8VT1>;
3700 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3701 loadf32, "cvttss2usi">, XS, VEX_W,
3702 EVEX_CD8<32, CD8VT1>;
3703 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3704 loadf64, "cvttsd2si">, XD,
3705 EVEX_CD8<64, CD8VT1>;
3706 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3707 loadf64, "cvttsd2usi">, XD,
3708 EVEX_CD8<64, CD8VT1>;
3709 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3710 loadf64, "cvttsd2si">, XD, VEX_W,
3711 EVEX_CD8<64, CD8VT1>;
3712 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3713 loadf64, "cvttsd2usi">, XD, VEX_W,
3714 EVEX_CD8<64, CD8VT1>;
3716 //===----------------------------------------------------------------------===//
3717 // AVX-512 Convert form float to double and back
3718 //===----------------------------------------------------------------------===//
3719 let hasSideEffects = 0 in {
3720 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3721 (ins FR32X:$src1, FR32X:$src2),
3722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3723 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3725 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3726 (ins FR32X:$src1, f32mem:$src2),
3727 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3728 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3729 EVEX_CD8<32, CD8VT1>;
3731 // Convert scalar double to scalar single
3732 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3733 (ins FR64X:$src1, FR64X:$src2),
3734 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3735 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3737 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3738 (ins FR64X:$src1, f64mem:$src2),
3739 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3740 []>, EVEX_4V, VEX_LIG, VEX_W,
3741 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3744 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3745 Requires<[HasAVX512]>;
3746 def : Pat<(fextend (loadf32 addr:$src)),
3747 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3749 def : Pat<(extloadf32 addr:$src),
3750 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3751 Requires<[HasAVX512, OptForSize]>;
3753 def : Pat<(extloadf32 addr:$src),
3754 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3755 Requires<[HasAVX512, OptForSpeed]>;
3757 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3758 Requires<[HasAVX512]>;
3760 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3761 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3762 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3764 let hasSideEffects = 0 in {
3765 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3766 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3768 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3769 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3770 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3771 [], d>, EVEX, EVEX_B, EVEX_RC;
3773 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3774 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3776 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3777 } // hasSideEffects = 0
3780 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3781 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3782 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3784 let hasSideEffects = 0 in {
3785 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3786 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3788 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3790 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3791 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3793 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3794 } // hasSideEffects = 0
3797 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3798 memopv8f64, f512mem, v8f32, v8f64,
3799 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3800 EVEX_CD8<64, CD8VF>;
3802 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3803 memopv4f64, f256mem, v8f64, v8f32,
3804 SSEPackedDouble>, EVEX_V512, PS,
3805 EVEX_CD8<32, CD8VH>;
3806 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3807 (VCVTPS2PDZrm addr:$src)>;
3809 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3810 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3811 (VCVTPD2PSZrr VR512:$src)>;
3813 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3814 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3815 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3817 //===----------------------------------------------------------------------===//
3818 // AVX-512 Vector convert from sign integer to float/double
3819 //===----------------------------------------------------------------------===//
3821 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3822 memopv8i64, i512mem, v16f32, v16i32,
3823 SSEPackedSingle>, EVEX_V512, PS,
3824 EVEX_CD8<32, CD8VF>;
3826 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3827 memopv4i64, i256mem, v8f64, v8i32,
3828 SSEPackedDouble>, EVEX_V512, XS,
3829 EVEX_CD8<32, CD8VH>;
3831 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3832 memopv16f32, f512mem, v16i32, v16f32,
3833 SSEPackedSingle>, EVEX_V512, XS,
3834 EVEX_CD8<32, CD8VF>;
3836 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3837 memopv8f64, f512mem, v8i32, v8f64,
3838 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3839 EVEX_CD8<64, CD8VF>;
3841 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3842 memopv16f32, f512mem, v16i32, v16f32,
3843 SSEPackedSingle>, EVEX_V512, PS,
3844 EVEX_CD8<32, CD8VF>;
3846 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3847 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3848 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3849 (VCVTTPS2UDQZrr VR512:$src)>;
3851 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3852 memopv8f64, f512mem, v8i32, v8f64,
3853 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3854 EVEX_CD8<64, CD8VF>;
3856 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3857 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3858 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3859 (VCVTTPD2UDQZrr VR512:$src)>;
3861 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3862 memopv4i64, f256mem, v8f64, v8i32,
3863 SSEPackedDouble>, EVEX_V512, XS,
3864 EVEX_CD8<32, CD8VH>;
3866 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3867 memopv16i32, f512mem, v16f32, v16i32,
3868 SSEPackedSingle>, EVEX_V512, XD,
3869 EVEX_CD8<32, CD8VF>;
3871 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3872 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3873 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3875 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3876 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3877 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3879 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3880 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3881 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3883 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3884 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3885 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3887 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3888 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3889 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3891 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3892 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3893 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3894 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3895 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3896 (VCVTDQ2PDZrr VR256X:$src)>;
3897 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3898 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3899 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3900 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3901 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3902 (VCVTUDQ2PDZrr VR256X:$src)>;
3904 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3905 RegisterClass DstRC, PatFrag mem_frag,
3906 X86MemOperand x86memop, Domain d> {
3907 let hasSideEffects = 0 in {
3908 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3909 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3911 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3912 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3913 [], d>, EVEX, EVEX_B, EVEX_RC;
3915 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3916 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3918 } // hasSideEffects = 0
3921 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3922 memopv16f32, f512mem, SSEPackedSingle>, PD,
3923 EVEX_V512, EVEX_CD8<32, CD8VF>;
3924 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3925 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3926 EVEX_V512, EVEX_CD8<64, CD8VF>;
3928 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3929 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3930 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3932 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3933 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3934 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3936 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3937 memopv16f32, f512mem, SSEPackedSingle>,
3938 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3939 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3940 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3941 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3943 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3944 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3945 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3947 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3948 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3949 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3951 let Predicates = [HasAVX512] in {
3952 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3953 (VCVTPD2PSZrm addr:$src)>;
3954 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3955 (VCVTPS2PDZrm addr:$src)>;
3958 //===----------------------------------------------------------------------===//
3959 // Half precision conversion instructions
3960 //===----------------------------------------------------------------------===//
3961 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3962 X86MemOperand x86memop> {
3963 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3964 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3966 let hasSideEffects = 0, mayLoad = 1 in
3967 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3968 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3971 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3972 X86MemOperand x86memop> {
3973 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3974 (ins srcRC:$src1, i32i8imm:$src2),
3975 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3977 let hasSideEffects = 0, mayStore = 1 in
3978 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3979 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3980 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3983 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3984 EVEX_CD8<32, CD8VH>;
3985 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3986 EVEX_CD8<32, CD8VH>;
3988 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3989 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3990 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3992 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3993 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3994 (VCVTPH2PSZrr VR256X:$src)>;
3996 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3997 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3998 "ucomiss">, PS, EVEX, VEX_LIG,
3999 EVEX_CD8<32, CD8VT1>;
4000 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4001 "ucomisd">, PD, EVEX,
4002 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4003 let Pattern = []<dag> in {
4004 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4005 "comiss">, PS, EVEX, VEX_LIG,
4006 EVEX_CD8<32, CD8VT1>;
4007 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4008 "comisd">, PD, EVEX,
4009 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4011 let isCodeGenOnly = 1 in {
4012 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4013 load, "ucomiss">, PS, EVEX, VEX_LIG,
4014 EVEX_CD8<32, CD8VT1>;
4015 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4016 load, "ucomisd">, PD, EVEX,
4017 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4019 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4020 load, "comiss">, PS, EVEX, VEX_LIG,
4021 EVEX_CD8<32, CD8VT1>;
4022 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4023 load, "comisd">, PD, EVEX,
4024 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4028 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4029 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4030 X86MemOperand x86memop> {
4031 let hasSideEffects = 0 in {
4032 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4033 (ins RC:$src1, RC:$src2),
4034 !strconcat(OpcodeStr,
4035 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4036 let mayLoad = 1 in {
4037 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4038 (ins RC:$src1, x86memop:$src2),
4039 !strconcat(OpcodeStr,
4040 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4045 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4046 EVEX_CD8<32, CD8VT1>;
4047 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4048 VEX_W, EVEX_CD8<64, CD8VT1>;
4049 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4050 EVEX_CD8<32, CD8VT1>;
4051 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4052 VEX_W, EVEX_CD8<64, CD8VT1>;
4054 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4055 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4056 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4057 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4059 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4060 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4061 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4062 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4064 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4065 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4066 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4067 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4069 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4070 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4071 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4072 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4074 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4075 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4076 RegisterClass RC, X86MemOperand x86memop,
4077 PatFrag mem_frag, ValueType OpVt> {
4078 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4079 !strconcat(OpcodeStr,
4080 " \t{$src, $dst|$dst, $src}"),
4081 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
4083 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4084 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4085 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
4088 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4089 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4090 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4091 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4092 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4093 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4094 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4095 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4097 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4098 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4099 (VRSQRT14PSZr VR512:$src)>;
4100 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4101 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4102 (VRSQRT14PDZr VR512:$src)>;
4104 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4105 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4106 (VRCP14PSZr VR512:$src)>;
4107 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4108 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4109 (VRCP14PDZr VR512:$src)>;
4111 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4112 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4113 X86MemOperand x86memop> {
4114 let hasSideEffects = 0, Predicates = [HasERI] in {
4115 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4116 (ins RC:$src1, RC:$src2),
4117 !strconcat(OpcodeStr,
4118 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4119 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4120 (ins RC:$src1, RC:$src2),
4121 !strconcat(OpcodeStr,
4122 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4123 []>, EVEX_4V, EVEX_B;
4124 let mayLoad = 1 in {
4125 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4126 (ins RC:$src1, x86memop:$src2),
4127 !strconcat(OpcodeStr,
4128 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4133 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4134 EVEX_CD8<32, CD8VT1>;
4135 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4136 VEX_W, EVEX_CD8<64, CD8VT1>;
4137 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4138 EVEX_CD8<32, CD8VT1>;
4139 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4140 VEX_W, EVEX_CD8<64, CD8VT1>;
4142 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4143 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4145 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4146 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4148 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4149 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4151 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4152 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4154 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4155 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4157 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4158 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4160 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4161 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4163 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4164 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4166 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4167 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4168 RegisterClass RC, X86MemOperand x86memop> {
4169 let hasSideEffects = 0, Predicates = [HasERI] in {
4170 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4171 !strconcat(OpcodeStr,
4172 " \t{$src, $dst|$dst, $src}"),
4174 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4175 !strconcat(OpcodeStr,
4176 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4178 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4179 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4183 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4184 EVEX_V512, EVEX_CD8<32, CD8VF>;
4185 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4186 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4187 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4188 EVEX_V512, EVEX_CD8<32, CD8VF>;
4189 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4190 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4192 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4193 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4194 (VRSQRT28PSZrb VR512:$src)>;
4195 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4196 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4197 (VRSQRT28PDZrb VR512:$src)>;
4199 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4200 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4201 (VRCP28PSZrb VR512:$src)>;
4202 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4203 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4204 (VRCP28PDZrb VR512:$src)>;
4206 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4207 OpndItins itins_s, OpndItins itins_d> {
4208 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4209 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4210 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4214 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4215 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4217 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4218 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4220 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4221 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4222 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4226 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4227 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4228 [(set VR512:$dst, (OpNode
4229 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4230 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4234 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4235 Intrinsic F32Int, Intrinsic F64Int,
4236 OpndItins itins_s, OpndItins itins_d> {
4237 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4238 (ins FR32X:$src1, FR32X:$src2),
4239 !strconcat(OpcodeStr,
4240 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4241 [], itins_s.rr>, XS, EVEX_4V;
4242 let isCodeGenOnly = 1 in
4243 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4244 (ins VR128X:$src1, VR128X:$src2),
4245 !strconcat(OpcodeStr,
4246 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4248 (F32Int VR128X:$src1, VR128X:$src2))],
4249 itins_s.rr>, XS, EVEX_4V;
4250 let mayLoad = 1 in {
4251 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4252 (ins FR32X:$src1, f32mem:$src2),
4253 !strconcat(OpcodeStr,
4254 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4255 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4256 let isCodeGenOnly = 1 in
4257 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4258 (ins VR128X:$src1, ssmem:$src2),
4259 !strconcat(OpcodeStr,
4260 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4262 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4263 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4265 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4266 (ins FR64X:$src1, FR64X:$src2),
4267 !strconcat(OpcodeStr,
4268 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4270 let isCodeGenOnly = 1 in
4271 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4272 (ins VR128X:$src1, VR128X:$src2),
4273 !strconcat(OpcodeStr,
4274 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4276 (F64Int VR128X:$src1, VR128X:$src2))],
4277 itins_s.rr>, XD, EVEX_4V, VEX_W;
4278 let mayLoad = 1 in {
4279 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4280 (ins FR64X:$src1, f64mem:$src2),
4281 !strconcat(OpcodeStr,
4282 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4283 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4284 let isCodeGenOnly = 1 in
4285 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4286 (ins VR128X:$src1, sdmem:$src2),
4287 !strconcat(OpcodeStr,
4288 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4290 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4291 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4296 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4297 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4298 SSE_SQRTSS, SSE_SQRTSD>,
4299 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4300 SSE_SQRTPS, SSE_SQRTPD>;
4302 let Predicates = [HasAVX512] in {
4303 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4304 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4305 (VSQRTPSZrr VR512:$src1)>;
4306 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4307 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4308 (VSQRTPDZrr VR512:$src1)>;
4310 def : Pat<(f32 (fsqrt FR32X:$src)),
4311 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4312 def : Pat<(f32 (fsqrt (load addr:$src))),
4313 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4314 Requires<[OptForSize]>;
4315 def : Pat<(f64 (fsqrt FR64X:$src)),
4316 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4317 def : Pat<(f64 (fsqrt (load addr:$src))),
4318 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4319 Requires<[OptForSize]>;
4321 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4322 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4323 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4324 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4325 Requires<[OptForSize]>;
4327 def : Pat<(f32 (X86frcp FR32X:$src)),
4328 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4329 def : Pat<(f32 (X86frcp (load addr:$src))),
4330 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4331 Requires<[OptForSize]>;
4333 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4334 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4335 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4337 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4338 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4340 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4341 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4342 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4344 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4345 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4349 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4350 X86MemOperand x86memop, RegisterClass RC,
4351 PatFrag mem_frag32, PatFrag mem_frag64,
4352 Intrinsic V4F32Int, Intrinsic V2F64Int,
4354 let ExeDomain = SSEPackedSingle in {
4355 // Intrinsic operation, reg.
4356 // Vector intrinsic operation, reg
4357 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4358 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4359 !strconcat(OpcodeStr,
4360 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4361 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4363 // Vector intrinsic operation, mem
4364 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4365 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4366 !strconcat(OpcodeStr,
4367 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4369 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4370 EVEX_CD8<32, VForm>;
4371 } // ExeDomain = SSEPackedSingle
4373 let ExeDomain = SSEPackedDouble in {
4374 // Vector intrinsic operation, reg
4375 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4376 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4377 !strconcat(OpcodeStr,
4378 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4379 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4381 // Vector intrinsic operation, mem
4382 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4383 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4384 !strconcat(OpcodeStr,
4385 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4387 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4388 EVEX_CD8<64, VForm>;
4389 } // ExeDomain = SSEPackedDouble
4392 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4396 let ExeDomain = GenericDomain in {
4398 let hasSideEffects = 0 in
4399 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4400 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4401 !strconcat(OpcodeStr,
4402 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4405 // Intrinsic operation, reg.
4406 let isCodeGenOnly = 1 in
4407 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4408 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4409 !strconcat(OpcodeStr,
4410 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4411 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4413 // Intrinsic operation, mem.
4414 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4415 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4416 !strconcat(OpcodeStr,
4417 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4418 [(set VR128X:$dst, (F32Int VR128X:$src1,
4419 sse_load_f32:$src2, imm:$src3))]>,
4420 EVEX_CD8<32, CD8VT1>;
4423 let hasSideEffects = 0 in
4424 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4425 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4426 !strconcat(OpcodeStr,
4427 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4430 // Intrinsic operation, reg.
4431 let isCodeGenOnly = 1 in
4432 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4433 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4434 !strconcat(OpcodeStr,
4435 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4436 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4439 // Intrinsic operation, mem.
4440 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4441 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4442 !strconcat(OpcodeStr,
4443 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4445 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4446 VEX_W, EVEX_CD8<64, CD8VT1>;
4447 } // ExeDomain = GenericDomain
4450 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4451 X86MemOperand x86memop, RegisterClass RC,
4452 PatFrag mem_frag, Domain d> {
4453 let ExeDomain = d in {
4454 // Intrinsic operation, reg.
4455 // Vector intrinsic operation, reg
4456 def r : AVX512AIi8<opc, MRMSrcReg,
4457 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4458 !strconcat(OpcodeStr,
4459 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4462 // Vector intrinsic operation, mem
4463 def m : AVX512AIi8<opc, MRMSrcMem,
4464 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4465 !strconcat(OpcodeStr,
4466 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4472 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4473 memopv16f32, SSEPackedSingle>, EVEX_V512,
4474 EVEX_CD8<32, CD8VF>;
4476 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4477 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4479 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4482 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4483 memopv8f64, SSEPackedDouble>, EVEX_V512,
4484 VEX_W, EVEX_CD8<64, CD8VF>;
4486 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4487 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4489 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4491 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4492 Operand x86memop, RegisterClass RC, Domain d> {
4493 let ExeDomain = d in {
4494 def r : AVX512AIi8<opc, MRMSrcReg,
4495 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4496 !strconcat(OpcodeStr,
4497 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4500 def m : AVX512AIi8<opc, MRMSrcMem,
4501 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4502 !strconcat(OpcodeStr,
4503 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4508 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4509 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4511 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4512 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4514 def : Pat<(ffloor FR32X:$src),
4515 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4516 def : Pat<(f64 (ffloor FR64X:$src)),
4517 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4518 def : Pat<(f32 (fnearbyint FR32X:$src)),
4519 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4520 def : Pat<(f64 (fnearbyint FR64X:$src)),
4521 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4522 def : Pat<(f32 (fceil FR32X:$src)),
4523 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4524 def : Pat<(f64 (fceil FR64X:$src)),
4525 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4526 def : Pat<(f32 (frint FR32X:$src)),
4527 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4528 def : Pat<(f64 (frint FR64X:$src)),
4529 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4530 def : Pat<(f32 (ftrunc FR32X:$src)),
4531 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4532 def : Pat<(f64 (ftrunc FR64X:$src)),
4533 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4535 def : Pat<(v16f32 (ffloor VR512:$src)),
4536 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4537 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4538 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4539 def : Pat<(v16f32 (fceil VR512:$src)),
4540 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4541 def : Pat<(v16f32 (frint VR512:$src)),
4542 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4543 def : Pat<(v16f32 (ftrunc VR512:$src)),
4544 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4546 def : Pat<(v8f64 (ffloor VR512:$src)),
4547 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4548 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4549 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4550 def : Pat<(v8f64 (fceil VR512:$src)),
4551 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4552 def : Pat<(v8f64 (frint VR512:$src)),
4553 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4554 def : Pat<(v8f64 (ftrunc VR512:$src)),
4555 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4557 //-------------------------------------------------
4558 // Integer truncate and extend operations
4559 //-------------------------------------------------
4561 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4562 RegisterClass dstRC, RegisterClass srcRC,
4563 RegisterClass KRC, X86MemOperand x86memop> {
4564 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4566 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4569 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4570 (ins KRC:$mask, srcRC:$src),
4571 !strconcat(OpcodeStr,
4572 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4575 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4576 (ins KRC:$mask, srcRC:$src),
4577 !strconcat(OpcodeStr,
4578 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4581 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4582 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4585 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4586 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4587 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4591 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4592 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4593 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4594 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4595 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4596 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4597 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4598 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4599 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4600 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4601 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4602 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4603 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4604 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4605 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4606 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4607 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4608 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4609 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4610 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4611 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4612 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4613 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4614 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4615 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4616 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4617 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4618 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4619 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4620 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4622 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4623 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4624 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4625 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4626 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4628 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4629 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4630 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4631 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4632 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4633 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4634 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4635 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4638 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4639 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4640 PatFrag mem_frag, X86MemOperand x86memop,
4641 ValueType OpVT, ValueType InVT> {
4643 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4645 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4646 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4648 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4649 (ins KRC:$mask, SrcRC:$src),
4650 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4653 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4654 (ins KRC:$mask, SrcRC:$src),
4655 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4658 let mayLoad = 1 in {
4659 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4660 (ins x86memop:$src),
4661 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4663 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4666 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4667 (ins KRC:$mask, x86memop:$src),
4668 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4672 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4673 (ins KRC:$mask, x86memop:$src),
4674 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4680 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4681 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4683 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4684 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4686 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4687 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4688 EVEX_CD8<16, CD8VH>;
4689 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4690 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4691 EVEX_CD8<16, CD8VQ>;
4692 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4693 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4694 EVEX_CD8<32, CD8VH>;
4696 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4697 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4699 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4700 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4702 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4703 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4704 EVEX_CD8<16, CD8VH>;
4705 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4706 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4707 EVEX_CD8<16, CD8VQ>;
4708 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4709 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4710 EVEX_CD8<32, CD8VH>;
4712 //===----------------------------------------------------------------------===//
4713 // GATHER - SCATTER Operations
4715 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4716 RegisterClass RC, X86MemOperand memop> {
4718 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4719 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4720 (ins RC:$src1, KRC:$mask, memop:$src2),
4721 !strconcat(OpcodeStr,
4722 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4726 let ExeDomain = SSEPackedDouble in {
4727 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4728 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4729 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4730 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4733 let ExeDomain = SSEPackedSingle in {
4734 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4735 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4736 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4737 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4740 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4741 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4742 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4743 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4745 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4746 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4747 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4748 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4750 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4751 RegisterClass RC, X86MemOperand memop> {
4752 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4753 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4754 (ins memop:$dst, KRC:$mask, RC:$src2),
4755 !strconcat(OpcodeStr,
4756 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4760 let ExeDomain = SSEPackedDouble in {
4761 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4762 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4763 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4764 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4767 let ExeDomain = SSEPackedSingle in {
4768 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4769 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4770 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4771 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4774 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4775 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4776 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4777 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4779 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4780 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4781 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4782 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4785 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4786 RegisterClass KRC, X86MemOperand memop> {
4787 let Predicates = [HasPFI], hasSideEffects = 1 in
4788 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4789 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4793 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4794 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4796 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4797 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4799 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4800 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4802 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4803 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4805 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4806 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4808 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4809 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4811 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4812 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4814 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4815 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4817 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4818 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4820 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4821 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4823 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4824 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4826 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4827 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4829 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4830 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4832 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4833 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4835 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4836 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4838 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4839 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4840 //===----------------------------------------------------------------------===//
4841 // VSHUFPS - VSHUFPD Operations
4843 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4844 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4846 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4847 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4848 !strconcat(OpcodeStr,
4849 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4850 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4851 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4852 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4853 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4854 (ins RC:$src1, RC:$src2, i8imm:$src3),
4855 !strconcat(OpcodeStr,
4856 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4857 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4858 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4859 EVEX_4V, Sched<[WriteShuffle]>;
4862 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4863 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4864 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4865 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4867 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4868 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4869 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4870 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4871 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4873 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4874 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4875 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4876 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4877 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4879 multiclass avx512_valign<X86VectorVTInfo _> {
4880 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4881 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4883 "$src3, $src2, $src1", "$src1, $src2, $src3",
4884 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4886 AVX512AIi8Base, EVEX_4V;
4888 // Also match valign of packed floats.
4889 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4890 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4893 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4894 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4895 !strconcat("valign"##_.Suffix,
4896 " \t{$src3, $src2, $src1, $dst|"
4897 "$dst, $src1, $src2, $src3}"),
4900 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4901 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4903 // Helper fragments to match sext vXi1 to vXiY.
4904 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4905 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4907 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4908 RegisterClass KRC, RegisterClass RC,
4909 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4911 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4914 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4915 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4917 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4918 !strconcat(OpcodeStr,
4919 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4921 let mayLoad = 1 in {
4922 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4923 (ins x86memop:$src),
4924 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4926 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4927 (ins KRC:$mask, x86memop:$src),
4928 !strconcat(OpcodeStr,
4929 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4931 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4932 (ins KRC:$mask, x86memop:$src),
4933 !strconcat(OpcodeStr,
4934 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4936 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4937 (ins x86scalar_mop:$src),
4938 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4939 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4941 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4942 (ins KRC:$mask, x86scalar_mop:$src),
4943 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4944 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4945 []>, EVEX, EVEX_B, EVEX_K;
4946 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4947 (ins KRC:$mask, x86scalar_mop:$src),
4948 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4949 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4951 []>, EVEX, EVEX_B, EVEX_KZ;
4955 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4956 i512mem, i32mem, "{1to16}">, EVEX_V512,
4957 EVEX_CD8<32, CD8VF>;
4958 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4959 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4960 EVEX_CD8<64, CD8VF>;
4963 (bc_v16i32 (v16i1sextv16i32)),
4964 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4965 (VPABSDZrr VR512:$src)>;
4967 (bc_v8i64 (v8i1sextv8i64)),
4968 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4969 (VPABSQZrr VR512:$src)>;
4971 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4972 (v16i32 immAllZerosV), (i16 -1))),
4973 (VPABSDZrr VR512:$src)>;
4974 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4975 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4976 (VPABSQZrr VR512:$src)>;
4978 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4979 RegisterClass RC, RegisterClass KRC,
4980 X86MemOperand x86memop,
4981 X86MemOperand x86scalar_mop, string BrdcstStr> {
4982 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4984 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4986 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4987 (ins x86memop:$src),
4988 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4990 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4991 (ins x86scalar_mop:$src),
4992 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4993 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4995 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4996 (ins KRC:$mask, RC:$src),
4997 !strconcat(OpcodeStr,
4998 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5000 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5001 (ins KRC:$mask, x86memop:$src),
5002 !strconcat(OpcodeStr,
5003 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5005 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5006 (ins KRC:$mask, x86scalar_mop:$src),
5007 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5008 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5010 []>, EVEX, EVEX_KZ, EVEX_B;
5012 let Constraints = "$src1 = $dst" in {
5013 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5014 (ins RC:$src1, KRC:$mask, RC:$src2),
5015 !strconcat(OpcodeStr,
5016 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5018 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5019 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5020 !strconcat(OpcodeStr,
5021 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5023 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5024 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5025 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5026 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5027 []>, EVEX, EVEX_K, EVEX_B;
5031 let Predicates = [HasCDI] in {
5032 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5033 i512mem, i32mem, "{1to16}">,
5034 EVEX_V512, EVEX_CD8<32, CD8VF>;
5037 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5038 i512mem, i64mem, "{1to8}">,
5039 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5043 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5045 (VPCONFLICTDrrk VR512:$src1,
5046 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5048 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5050 (VPCONFLICTQrrk VR512:$src1,
5051 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5053 let Predicates = [HasCDI] in {
5054 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5055 i512mem, i32mem, "{1to16}">,
5056 EVEX_V512, EVEX_CD8<32, CD8VF>;
5059 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5060 i512mem, i64mem, "{1to8}">,
5061 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5065 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5067 (VPLZCNTDrrk VR512:$src1,
5068 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5070 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5072 (VPLZCNTQrrk VR512:$src1,
5073 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5075 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5076 (VPLZCNTDrm addr:$src)>;
5077 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5078 (VPLZCNTDrr VR512:$src)>;
5079 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5080 (VPLZCNTQrm addr:$src)>;
5081 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5082 (VPLZCNTQrr VR512:$src)>;
5084 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5085 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5086 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5088 def : Pat<(store VK1:$src, addr:$dst),
5089 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5091 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5092 (truncstore node:$val, node:$ptr), [{
5093 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5096 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5097 (MOV8mr addr:$dst, GR8:$src)>;
5099 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5100 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5101 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5102 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5105 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5106 string OpcodeStr, Predicate prd> {
5107 let Predicates = [prd] in
5108 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5110 let Predicates = [prd, HasVLX] in {
5111 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5112 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5116 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5117 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5119 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5121 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5123 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5127 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;