1 multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
3 string AttSrcAsm, string IntelSrcAsm,
4 dag RHS, ValueType OpVT,
5 RegisterClass RC, RegisterClass KRC> {
6 def NAME: AVX512<O, F, Outs, Ins,
7 OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
8 "$dst, "#IntelSrcAsm#"}",
11 // Prefer over VMOV*rrk Pat<>
12 let Constraints = "$src0 = $dst", AddedComplexity = 20 in
13 def NAME#k: AVX512<O, F, Outs,
14 !con((ins RC:$src0, KRC:$mask), Ins),
15 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
16 "$dst {${mask}}, "#IntelSrcAsm#"}",
18 (vselect KRC:$mask, RHS, RC:$src0))]>,
20 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
21 def NAME#kz: AVX512<O, F, Outs,
22 !con((ins KRC:$mask), Ins),
23 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
24 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
26 (vselect KRC:$mask, RHS,
28 (v16i32 immAllZerosV)))))]>,
32 // Bitcasts between 512-bit vector types. Return the original type since
33 // no instruction is needed for the conversion
34 let Predicates = [HasAVX512] in {
35 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
36 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
37 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
38 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
39 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
40 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
41 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
42 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
43 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
44 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
45 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
46 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
47 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
48 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
49 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
50 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
51 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
52 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
53 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
54 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
55 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
56 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
57 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
58 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
59 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
60 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
61 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
62 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
63 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
64 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
65 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
67 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
68 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
69 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
70 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
71 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
72 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
73 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
74 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
75 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
76 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
77 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
78 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
79 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
80 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
81 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
82 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
83 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
84 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
85 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
86 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
87 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
88 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
89 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
90 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
91 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
92 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
93 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
94 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
95 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
96 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
98 // Bitcasts between 256-bit vector types. Return the original type since
99 // no instruction is needed for the conversion
100 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
101 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
102 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
103 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
104 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
105 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
106 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
107 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
108 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
109 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
110 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
111 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
112 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
113 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
114 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
115 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
116 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
117 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
118 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
119 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
120 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
121 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
122 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
123 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
124 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
125 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
126 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
127 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
128 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
129 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
133 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
136 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
137 isPseudo = 1, Predicates = [HasAVX512] in {
138 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
139 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
142 let Predicates = [HasAVX512] in {
143 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
144 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
145 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
148 //===----------------------------------------------------------------------===//
149 // AVX-512 - VECTOR INSERT
152 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
153 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
154 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
155 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
156 []>, EVEX_4V, EVEX_V512;
158 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
159 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
160 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
161 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
164 // -- 64x4 fp form --
165 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
166 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
167 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
168 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
169 []>, EVEX_4V, EVEX_V512, VEX_W;
171 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
172 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
173 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
174 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
176 // -- 32x4 integer form --
177 let hasSideEffects = 0 in {
178 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
179 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
180 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
181 []>, EVEX_4V, EVEX_V512;
183 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
184 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
185 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
186 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
189 let hasSideEffects = 0 in {
191 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
192 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
193 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
194 []>, EVEX_4V, EVEX_V512, VEX_W;
196 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
197 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
198 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
199 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
202 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
203 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
204 (INSERT_get_vinsert128_imm VR512:$ins))>;
205 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
206 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
207 (INSERT_get_vinsert128_imm VR512:$ins))>;
208 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
209 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
210 (INSERT_get_vinsert128_imm VR512:$ins))>;
211 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
212 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
213 (INSERT_get_vinsert128_imm VR512:$ins))>;
215 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
216 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
217 (INSERT_get_vinsert128_imm VR512:$ins))>;
218 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
219 (bc_v4i32 (loadv2i64 addr:$src2)),
220 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
221 (INSERT_get_vinsert128_imm VR512:$ins))>;
222 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
223 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
224 (INSERT_get_vinsert128_imm VR512:$ins))>;
225 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
226 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
227 (INSERT_get_vinsert128_imm VR512:$ins))>;
229 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
230 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
231 (INSERT_get_vinsert256_imm VR512:$ins))>;
232 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
233 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
234 (INSERT_get_vinsert256_imm VR512:$ins))>;
235 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
236 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
237 (INSERT_get_vinsert256_imm VR512:$ins))>;
238 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
239 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
240 (INSERT_get_vinsert256_imm VR512:$ins))>;
242 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
243 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
244 (INSERT_get_vinsert256_imm VR512:$ins))>;
245 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
246 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
247 (INSERT_get_vinsert256_imm VR512:$ins))>;
248 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
249 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
250 (INSERT_get_vinsert256_imm VR512:$ins))>;
251 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
252 (bc_v8i32 (loadv4i64 addr:$src2)),
253 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
254 (INSERT_get_vinsert256_imm VR512:$ins))>;
256 // vinsertps - insert f32 to XMM
257 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
258 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
259 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
260 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
262 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
263 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
264 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
265 [(set VR128X:$dst, (X86insertps VR128X:$src1,
266 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
267 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
269 //===----------------------------------------------------------------------===//
270 // AVX-512 VECTOR EXTRACT
272 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
274 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
275 (ins VR512:$src1, i8imm:$src2),
276 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
277 []>, EVEX, EVEX_V512;
278 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
279 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
280 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
281 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
284 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
285 (ins VR512:$src1, i8imm:$src2),
286 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
287 []>, EVEX, EVEX_V512, VEX_W;
289 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
290 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
291 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
292 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
295 let hasSideEffects = 0 in {
297 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
298 (ins VR512:$src1, i8imm:$src2),
299 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
300 []>, EVEX, EVEX_V512;
301 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
302 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
303 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
304 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
307 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
308 (ins VR512:$src1, i8imm:$src2),
309 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
310 []>, EVEX, EVEX_V512, VEX_W;
312 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
313 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
314 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
315 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
318 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
319 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
320 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
322 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
323 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
324 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
326 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
327 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
328 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
330 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
331 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
332 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
335 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
336 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
337 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
339 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
340 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
341 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
343 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
344 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
345 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
347 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
348 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
349 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
351 // A 256-bit subvector extract from the first 512-bit vector position
352 // is a subregister copy that needs no instruction.
353 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
354 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
355 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
356 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
357 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
358 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
359 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
360 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
363 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
364 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
365 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
366 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
367 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
368 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
369 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
370 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
373 // A 128-bit subvector insert to the first 512-bit vector position
374 // is a subregister copy that needs no instruction.
375 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
376 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
377 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
379 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
380 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
381 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
383 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
384 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
385 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
387 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
388 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
389 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
392 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
393 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
394 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
395 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
396 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
397 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
398 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
399 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
401 // vextractps - extract 32 bits from XMM
402 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
403 (ins VR128X:$src1, u32u8imm:$src2),
404 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
405 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
408 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
409 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
410 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
411 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
412 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
414 //===---------------------------------------------------------------------===//
417 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
418 RegisterClass DestRC,
419 RegisterClass SrcRC, X86MemOperand x86memop> {
420 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
421 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
423 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
424 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
426 let ExeDomain = SSEPackedSingle in {
427 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
429 EVEX_V512, EVEX_CD8<32, CD8VT1>;
432 let ExeDomain = SSEPackedDouble in {
433 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
435 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
438 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
439 (VBROADCASTSSZrm addr:$src)>;
440 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
441 (VBROADCASTSDZrm addr:$src)>;
443 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
444 (VBROADCASTSSZrm addr:$src)>;
445 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
446 (VBROADCASTSDZrm addr:$src)>;
448 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
449 RegisterClass SrcRC, RegisterClass KRC> {
450 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
451 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
452 []>, EVEX, EVEX_V512;
453 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
454 (ins KRC:$mask, SrcRC:$src),
455 !strconcat(OpcodeStr,
456 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
457 []>, EVEX, EVEX_V512, EVEX_KZ;
460 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
461 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
464 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
465 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
467 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
468 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
470 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
471 (VPBROADCASTDrZrr GR32:$src)>;
472 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
473 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
474 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
475 (VPBROADCASTQrZrr GR64:$src)>;
476 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
477 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
480 (VPBROADCASTDrZrr GR32:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
482 (VPBROADCASTQrZrr GR64:$src)>;
484 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
485 (v16i32 immAllZerosV), (i16 GR16:$mask))),
486 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
487 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
488 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
489 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
491 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
492 X86MemOperand x86memop, PatFrag ld_frag,
493 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
495 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
496 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
498 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
499 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
501 !strconcat(OpcodeStr,
502 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
504 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
507 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
508 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
510 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
511 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
513 !strconcat(OpcodeStr,
514 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
515 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
516 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
520 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
521 loadi32, VR512, v16i32, v4i32, VK16WM>,
522 EVEX_V512, EVEX_CD8<32, CD8VT1>;
523 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
524 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
525 EVEX_CD8<64, CD8VT1>;
527 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
528 X86MemOperand x86memop, PatFrag ld_frag,
531 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
532 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
534 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
536 !strconcat(OpcodeStr,
537 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
542 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
543 i128mem, loadv2i64, VK16WM>,
544 EVEX_V512, EVEX_CD8<32, CD8VT4>;
545 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
546 i256mem, loadv4i64, VK16WM>, VEX_W,
547 EVEX_V512, EVEX_CD8<64, CD8VT4>;
549 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
550 (VPBROADCASTDZrr VR128X:$src)>;
551 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
552 (VPBROADCASTQZrr VR128X:$src)>;
554 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
555 (VBROADCASTSSZrr VR128X:$src)>;
556 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
557 (VBROADCASTSDZrr VR128X:$src)>;
559 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
560 (VBROADCASTSSZrr VR128X:$src)>;
561 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
562 (VBROADCASTSDZrr VR128X:$src)>;
564 // Provide fallback in case the load node that is used in the patterns above
565 // is used by additional users, which prevents the pattern selection.
566 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
567 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
568 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
569 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
572 let Predicates = [HasAVX512] in {
573 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
575 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
576 addr:$src)), sub_ymm)>;
578 //===----------------------------------------------------------------------===//
579 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
582 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
583 RegisterClass DstRC, RegisterClass KRC,
584 ValueType OpVT, ValueType SrcVT> {
585 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
586 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
590 let Predicates = [HasCDI] in {
591 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
592 VK16, v16i32, v16i1>, EVEX_V512;
593 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
594 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
597 //===----------------------------------------------------------------------===//
600 // -- immediate form --
601 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
602 SDNode OpNode, PatFrag mem_frag,
603 X86MemOperand x86memop, ValueType OpVT> {
604 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
605 (ins RC:$src1, i8imm:$src2),
606 !strconcat(OpcodeStr,
607 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
609 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
611 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
612 (ins x86memop:$src1, i8imm:$src2),
613 !strconcat(OpcodeStr,
614 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
616 (OpVT (OpNode (mem_frag addr:$src1),
617 (i8 imm:$src2))))]>, EVEX;
620 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
621 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
622 let ExeDomain = SSEPackedDouble in
623 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
624 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
626 // -- VPERM - register form --
627 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
628 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins RC:$src1, RC:$src2),
632 !strconcat(OpcodeStr,
633 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
635 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
637 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
638 (ins RC:$src1, x86memop:$src2),
639 !strconcat(OpcodeStr,
640 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
642 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
646 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
647 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
648 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
649 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
650 let ExeDomain = SSEPackedSingle in
651 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
652 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
653 let ExeDomain = SSEPackedDouble in
654 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
655 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
657 // -- VPERM2I - 3 source operands form --
658 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
659 PatFrag mem_frag, X86MemOperand x86memop,
660 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
661 let Constraints = "$src1 = $dst" in {
662 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
663 (ins RC:$src1, RC:$src2, RC:$src3),
664 !strconcat(OpcodeStr,
665 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
667 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
670 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}}|"
674 "$dst {${mask}}, $src2, $src3}"),
675 [(set RC:$dst, (OpVT (vselect KRC:$mask,
676 (OpNode RC:$src1, RC:$src2,
681 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
682 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
683 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
684 !strconcat(OpcodeStr,
685 " \t{$src3, $src2, $dst {${mask}} {z} |",
686 "$dst {${mask}} {z}, $src2, $src3}"),
687 [(set RC:$dst, (OpVT (vselect KRC:$mask,
688 (OpNode RC:$src1, RC:$src2,
691 (v16i32 immAllZerosV))))))]>,
694 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
695 (ins RC:$src1, RC:$src2, x86memop:$src3),
696 !strconcat(OpcodeStr,
697 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
699 (OpVT (OpNode RC:$src1, RC:$src2,
700 (mem_frag addr:$src3))))]>, EVEX_4V;
702 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
703 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
704 !strconcat(OpcodeStr,
705 " \t{$src3, $src2, $dst {${mask}}|"
706 "$dst {${mask}}, $src2, $src3}"),
708 (OpVT (vselect KRC:$mask,
709 (OpNode RC:$src1, RC:$src2,
710 (mem_frag addr:$src3)),
714 let AddedComplexity = 10 in // Prefer over the rrkz variant
715 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
716 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
717 !strconcat(OpcodeStr,
718 " \t{$src3, $src2, $dst {${mask}} {z}|"
719 "$dst {${mask}} {z}, $src2, $src3}"),
721 (OpVT (vselect KRC:$mask,
722 (OpNode RC:$src1, RC:$src2,
723 (mem_frag addr:$src3)),
725 (v16i32 immAllZerosV))))))]>,
729 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
730 i512mem, X86VPermiv3, v16i32, VK16WM>,
731 EVEX_V512, EVEX_CD8<32, CD8VF>;
732 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
733 i512mem, X86VPermiv3, v8i64, VK8WM>,
734 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
735 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
736 i512mem, X86VPermiv3, v16f32, VK16WM>,
737 EVEX_V512, EVEX_CD8<32, CD8VF>;
738 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
739 i512mem, X86VPermiv3, v8f64, VK8WM>,
740 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
742 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
743 PatFrag mem_frag, X86MemOperand x86memop,
744 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
745 ValueType MaskVT, RegisterClass MRC> :
746 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
748 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
749 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
750 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
752 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
753 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
754 (!cast<Instruction>(NAME#rrk) VR512:$src1,
755 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
758 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
759 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
760 EVEX_V512, EVEX_CD8<32, CD8VF>;
761 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
762 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
763 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
764 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
765 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
766 EVEX_V512, EVEX_CD8<32, CD8VF>;
767 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
768 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
769 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
771 //===----------------------------------------------------------------------===//
772 // AVX-512 - BLEND using mask
774 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
775 RegisterClass KRC, RegisterClass RC,
776 X86MemOperand x86memop, PatFrag mem_frag,
777 SDNode OpNode, ValueType vt> {
778 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
779 (ins KRC:$mask, RC:$src1, RC:$src2),
780 !strconcat(OpcodeStr,
781 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
782 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
783 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
785 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
786 (ins KRC:$mask, RC:$src1, x86memop:$src2),
787 !strconcat(OpcodeStr,
788 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
789 []>, EVEX_4V, EVEX_K;
792 let ExeDomain = SSEPackedSingle in
793 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
794 VK16WM, VR512, f512mem,
795 memopv16f32, vselect, v16f32>,
796 EVEX_CD8<32, CD8VF>, EVEX_V512;
797 let ExeDomain = SSEPackedDouble in
798 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
799 VK8WM, VR512, f512mem,
800 memopv8f64, vselect, v8f64>,
801 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
803 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
804 (v16f32 VR512:$src2), (i16 GR16:$mask))),
805 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
806 VR512:$src1, VR512:$src2)>;
808 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
809 (v8f64 VR512:$src2), (i8 GR8:$mask))),
810 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
811 VR512:$src1, VR512:$src2)>;
813 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
814 VK16WM, VR512, f512mem,
815 memopv16i32, vselect, v16i32>,
816 EVEX_CD8<32, CD8VF>, EVEX_V512;
818 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
819 VK8WM, VR512, f512mem,
820 memopv8i64, vselect, v8i64>,
821 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
823 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
824 (v16i32 VR512:$src2), (i16 GR16:$mask))),
825 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
826 VR512:$src1, VR512:$src2)>;
828 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
829 (v8i64 VR512:$src2), (i8 GR8:$mask))),
830 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
831 VR512:$src1, VR512:$src2)>;
833 let Predicates = [HasAVX512] in {
834 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
835 (v8f32 VR256X:$src2))),
837 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
838 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
841 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
842 (v8i32 VR256X:$src2))),
844 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
846 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
848 //===----------------------------------------------------------------------===//
849 // Compare Instructions
850 //===----------------------------------------------------------------------===//
852 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
853 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
854 Operand CC, SDNode OpNode, ValueType VT,
855 PatFrag ld_frag, string asm, string asm_alt> {
856 def rr : AVX512Ii8<0xC2, MRMSrcReg,
857 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
858 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
859 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
860 def rm : AVX512Ii8<0xC2, MRMSrcMem,
861 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
862 [(set VK1:$dst, (OpNode (VT RC:$src1),
863 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
864 let isAsmParserOnly = 1, hasSideEffects = 0 in {
865 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
866 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
867 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
868 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
869 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
870 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
874 let Predicates = [HasAVX512] in {
875 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
876 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
877 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
879 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
880 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
881 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
885 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
886 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
887 SDNode OpNode, ValueType vt> {
888 def rr : AVX512BI<opc, MRMSrcReg,
889 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
890 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
891 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
892 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
893 def rm : AVX512BI<opc, MRMSrcMem,
894 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
895 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
897 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
900 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
901 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
903 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
904 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
905 VEX_W, EVEX_CD8<64, CD8VF>;
907 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
908 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
910 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
911 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
912 VEX_W, EVEX_CD8<64, CD8VF>;
914 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
915 (COPY_TO_REGCLASS (VPCMPGTDZrr
916 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
917 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
919 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
920 (COPY_TO_REGCLASS (VPCMPEQDZrr
921 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
922 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
924 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
925 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
926 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
927 def rri : AVX512AIi8<opc, MRMSrcReg,
928 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
929 !strconcat("vpcmp${cc}", Suffix,
930 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
931 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
932 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
933 def rmi : AVX512AIi8<opc, MRMSrcMem,
934 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
935 !strconcat("vpcmp${cc}", Suffix,
936 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
937 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
938 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
939 // Accept explicit immediate argument form instead of comparison code.
940 let isAsmParserOnly = 1, hasSideEffects = 0 in {
941 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
942 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
943 !strconcat("vpcmp", Suffix,
944 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
945 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
946 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
947 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
948 !strconcat("vpcmp", Suffix,
949 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
950 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
951 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
952 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
953 !strconcat("vpcmp", Suffix,
954 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
955 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
956 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
957 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
958 !strconcat("vpcmp", Suffix,
959 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
960 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
964 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
965 X86cmpm, v16i32, AVXCC, "d">,
966 EVEX_V512, EVEX_CD8<32, CD8VF>;
967 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
968 X86cmpmu, v16i32, AVXCC, "ud">,
969 EVEX_V512, EVEX_CD8<32, CD8VF>;
971 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
972 X86cmpm, v8i64, AVXCC, "q">,
973 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
974 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
975 X86cmpmu, v8i64, AVXCC, "uq">,
976 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
978 // avx512_cmp_packed - compare packed instructions
979 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
980 X86MemOperand x86memop, ValueType vt,
981 string suffix, Domain d> {
982 def rri : AVX512PIi8<0xC2, MRMSrcReg,
983 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
984 !strconcat("vcmp${cc}", suffix,
985 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
986 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
987 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
988 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
989 !strconcat("vcmp${cc}", suffix,
990 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
992 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
993 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
994 !strconcat("vcmp${cc}", suffix,
995 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
997 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
999 // Accept explicit immediate argument form instead of comparison code.
1000 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1001 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1002 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1003 !strconcat("vcmp", suffix,
1004 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1005 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1006 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1007 !strconcat("vcmp", suffix,
1008 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1012 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1013 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1014 EVEX_CD8<32, CD8VF>;
1015 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1016 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1017 EVEX_CD8<64, CD8VF>;
1019 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1020 (COPY_TO_REGCLASS (VCMPPSZrri
1021 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1022 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1024 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1025 (COPY_TO_REGCLASS (VPCMPDZrri
1026 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1027 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1029 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1030 (COPY_TO_REGCLASS (VPCMPUDZrri
1031 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1032 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1035 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1036 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1038 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1039 (I8Imm imm:$cc)), GR16)>;
1041 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1042 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1044 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1045 (I8Imm imm:$cc)), GR8)>;
1047 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1048 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1050 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1051 (I8Imm imm:$cc)), GR16)>;
1053 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1054 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1056 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1057 (I8Imm imm:$cc)), GR8)>;
1059 // Mask register copy, including
1060 // - copy between mask registers
1061 // - load/store mask registers
1062 // - copy from GPR to mask register and vice versa
1064 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1065 string OpcodeStr, RegisterClass KRC,
1066 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1067 let hasSideEffects = 0 in {
1068 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1069 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1071 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1072 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1073 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1075 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1076 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1080 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1082 RegisterClass KRC, RegisterClass GRC> {
1083 let hasSideEffects = 0 in {
1084 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1085 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1086 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1087 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1091 let Predicates = [HasDQI] in
1092 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1094 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1097 let Predicates = [HasAVX512] in
1098 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1100 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1103 let Predicates = [HasBWI] in {
1104 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1105 i32mem>, VEX, PD, VEX_W;
1106 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1110 let Predicates = [HasBWI] in {
1111 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1112 i64mem>, VEX, PS, VEX_W;
1113 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1117 // GR from/to mask register
1118 let Predicates = [HasDQI] in {
1119 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1120 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1121 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1122 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1124 let Predicates = [HasAVX512] in {
1125 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1126 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1127 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1128 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1130 let Predicates = [HasBWI] in {
1131 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1132 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1134 let Predicates = [HasBWI] in {
1135 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1136 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1140 let Predicates = [HasDQI] in {
1141 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1142 (KMOVBmk addr:$dst, VK8:$src)>;
1144 let Predicates = [HasAVX512] in {
1145 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1146 (KMOVWmk addr:$dst, VK16:$src)>;
1147 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1148 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1149 def : Pat<(i1 (load addr:$src)),
1150 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1151 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1152 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1154 let Predicates = [HasBWI] in {
1155 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1156 (KMOVDmk addr:$dst, VK32:$src)>;
1158 let Predicates = [HasBWI] in {
1159 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1160 (KMOVQmk addr:$dst, VK64:$src)>;
1163 let Predicates = [HasAVX512] in {
1164 def : Pat<(i1 (trunc (i32 GR32:$src))),
1165 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1167 def : Pat<(i1 (trunc (i8 GR8:$src))),
1169 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1171 def : Pat<(i1 (trunc (i16 GR16:$src))),
1173 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1176 def : Pat<(i32 (zext VK1:$src)),
1177 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1178 def : Pat<(i8 (zext VK1:$src)),
1181 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1182 def : Pat<(i64 (zext VK1:$src)),
1183 (AND64ri8 (SUBREG_TO_REG (i64 0),
1184 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1185 def : Pat<(i16 (zext VK1:$src)),
1187 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1189 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1190 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1191 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1192 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1194 let Predicates = [HasBWI] in {
1195 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1196 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1197 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1198 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1202 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1203 let Predicates = [HasAVX512] in {
1204 // GR from/to 8-bit mask without native support
1205 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1207 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1209 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1211 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1214 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1215 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1216 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1217 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1219 let Predicates = [HasBWI] in {
1220 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1221 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1222 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1223 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1226 // Mask unary operation
1228 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1229 RegisterClass KRC, SDPatternOperator OpNode,
1231 let Predicates = [prd] in
1232 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1233 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1234 [(set KRC:$dst, (OpNode KRC:$src))]>;
1237 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1238 SDPatternOperator OpNode> {
1239 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1241 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1242 HasAVX512>, VEX, PS;
1243 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1244 HasBWI>, VEX, PD, VEX_W;
1245 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1246 HasBWI>, VEX, PS, VEX_W;
1249 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1251 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1252 let Predicates = [HasAVX512] in
1253 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1255 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1256 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1258 defm : avx512_mask_unop_int<"knot", "KNOT">;
1260 let Predicates = [HasDQI] in
1261 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1262 let Predicates = [HasAVX512] in
1263 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1264 let Predicates = [HasBWI] in
1265 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1266 let Predicates = [HasBWI] in
1267 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1269 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1270 let Predicates = [HasAVX512] in {
1271 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1272 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1274 def : Pat<(not VK8:$src),
1276 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1279 // Mask binary operation
1280 // - KAND, KANDN, KOR, KXNOR, KXOR
1281 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1282 RegisterClass KRC, SDPatternOperator OpNode,
1284 let Predicates = [prd] in
1285 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1286 !strconcat(OpcodeStr,
1287 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1288 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1291 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1292 SDPatternOperator OpNode> {
1293 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1294 HasDQI>, VEX_4V, VEX_L, PD;
1295 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1296 HasAVX512>, VEX_4V, VEX_L, PS;
1297 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1298 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1299 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1300 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1303 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1304 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1306 let isCommutable = 1 in {
1307 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1308 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1309 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1310 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1312 let isCommutable = 0 in
1313 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1315 def : Pat<(xor VK1:$src1, VK1:$src2),
1316 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1317 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1319 def : Pat<(or VK1:$src1, VK1:$src2),
1320 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1321 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1323 def : Pat<(and VK1:$src1, VK1:$src2),
1324 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1325 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1327 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1328 let Predicates = [HasAVX512] in
1329 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1330 (i16 GR16:$src1), (i16 GR16:$src2)),
1331 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1332 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1333 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1336 defm : avx512_mask_binop_int<"kand", "KAND">;
1337 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1338 defm : avx512_mask_binop_int<"kor", "KOR">;
1339 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1340 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1342 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1343 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1344 let Predicates = [HasAVX512] in
1345 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1347 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1348 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1351 defm : avx512_binop_pat<and, KANDWrr>;
1352 defm : avx512_binop_pat<andn, KANDNWrr>;
1353 defm : avx512_binop_pat<or, KORWrr>;
1354 defm : avx512_binop_pat<xnor, KXNORWrr>;
1355 defm : avx512_binop_pat<xor, KXORWrr>;
1358 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1359 RegisterClass KRC> {
1360 let Predicates = [HasAVX512] in
1361 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1362 !strconcat(OpcodeStr,
1363 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1366 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1367 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1371 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1372 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1373 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1374 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1377 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1378 let Predicates = [HasAVX512] in
1379 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1380 (i16 GR16:$src1), (i16 GR16:$src2)),
1381 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1382 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1383 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1385 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1388 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1390 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1391 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1392 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1393 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1396 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1397 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1401 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1403 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1404 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1405 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1408 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1410 let Predicates = [HasAVX512] in
1411 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1412 !strconcat(OpcodeStr,
1413 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1414 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1417 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1419 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1423 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1424 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1426 // Mask setting all 0s or 1s
1427 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1428 let Predicates = [HasAVX512] in
1429 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1430 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1431 [(set KRC:$dst, (VT Val))]>;
1434 multiclass avx512_mask_setop_w<PatFrag Val> {
1435 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1436 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1439 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1440 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1442 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1443 let Predicates = [HasAVX512] in {
1444 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1445 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1446 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1447 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1448 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1450 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1451 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1453 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1454 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1456 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1457 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1459 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1460 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1462 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1463 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1464 //===----------------------------------------------------------------------===//
1465 // AVX-512 - Aligned and unaligned load and store
1468 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1469 RegisterClass KRC, RegisterClass RC,
1470 ValueType vt, ValueType zvt, X86MemOperand memop,
1471 Domain d, bit IsReMaterializable = 1> {
1472 let hasSideEffects = 0 in {
1473 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1474 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1476 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1477 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1478 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1480 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1481 SchedRW = [WriteLoad] in
1482 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1483 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1484 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1487 let AddedComplexity = 20 in {
1488 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1489 let hasSideEffects = 0 in
1490 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1491 (ins RC:$src0, KRC:$mask, RC:$src1),
1492 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1493 "${dst} {${mask}}, $src1}"),
1494 [(set RC:$dst, (vt (vselect KRC:$mask,
1498 let mayLoad = 1, SchedRW = [WriteLoad] in
1499 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1500 (ins RC:$src0, KRC:$mask, memop:$src1),
1501 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1502 "${dst} {${mask}}, $src1}"),
1505 (vt (bitconvert (ld_frag addr:$src1))),
1509 let mayLoad = 1, SchedRW = [WriteLoad] in
1510 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1511 (ins KRC:$mask, memop:$src),
1512 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1513 "${dst} {${mask}} {z}, $src}"),
1516 (vt (bitconvert (ld_frag addr:$src))),
1517 (vt (bitconvert (zvt immAllZerosV))))))],
1522 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1523 string elty, string elsz, string vsz512,
1524 string vsz256, string vsz128, Domain d,
1525 Predicate prd, bit IsReMaterializable = 1> {
1526 let Predicates = [prd] in
1527 defm Z : avx512_load<opc, OpcodeStr,
1528 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1529 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1530 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1531 !cast<X86MemOperand>(elty##"512mem"), d,
1532 IsReMaterializable>, EVEX_V512;
1534 let Predicates = [prd, HasVLX] in {
1535 defm Z256 : avx512_load<opc, OpcodeStr,
1536 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1537 "v"##vsz256##elty##elsz, "v4i64")),
1538 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1539 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1540 !cast<X86MemOperand>(elty##"256mem"), d,
1541 IsReMaterializable>, EVEX_V256;
1543 defm Z128 : avx512_load<opc, OpcodeStr,
1544 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1545 "v"##vsz128##elty##elsz, "v2i64")),
1546 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1547 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1548 !cast<X86MemOperand>(elty##"128mem"), d,
1549 IsReMaterializable>, EVEX_V128;
1554 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1555 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1556 X86MemOperand memop, Domain d> {
1557 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1558 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1561 let Constraints = "$src1 = $dst" in
1562 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1563 (ins RC:$src1, KRC:$mask, RC:$src2),
1564 !strconcat(OpcodeStr,
1565 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1567 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1568 (ins KRC:$mask, RC:$src),
1569 !strconcat(OpcodeStr,
1570 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1571 [], d>, EVEX, EVEX_KZ;
1573 let mayStore = 1 in {
1574 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1576 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1577 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1578 (ins memop:$dst, KRC:$mask, RC:$src),
1579 !strconcat(OpcodeStr,
1580 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1581 [], d>, EVEX, EVEX_K;
1586 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1587 string st_suff_512, string st_suff_256,
1588 string st_suff_128, string elty, string elsz,
1589 string vsz512, string vsz256, string vsz128,
1590 Domain d, Predicate prd> {
1591 let Predicates = [prd] in
1592 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1593 !cast<ValueType>("v"##vsz512##elty##elsz),
1594 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1595 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1597 let Predicates = [prd, HasVLX] in {
1598 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1599 !cast<ValueType>("v"##vsz256##elty##elsz),
1600 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1601 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1603 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1604 !cast<ValueType>("v"##vsz128##elty##elsz),
1605 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1606 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1610 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1611 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1612 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1613 "512", "256", "", "f", "32", "16", "8", "4",
1614 SSEPackedSingle, HasAVX512>,
1615 PS, EVEX_CD8<32, CD8VF>;
1617 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1618 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1619 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1620 "512", "256", "", "f", "64", "8", "4", "2",
1621 SSEPackedDouble, HasAVX512>,
1622 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1624 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1625 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1626 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1627 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1628 PS, EVEX_CD8<32, CD8VF>;
1630 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1631 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1632 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1633 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1634 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1636 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1637 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1638 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1640 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1641 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1642 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1644 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1646 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1648 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1650 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1653 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1654 "16", "8", "4", SSEPackedInt, HasAVX512>,
1655 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1656 "512", "256", "", "i", "32", "16", "8", "4",
1657 SSEPackedInt, HasAVX512>,
1658 PD, EVEX_CD8<32, CD8VF>;
1660 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1661 "8", "4", "2", SSEPackedInt, HasAVX512>,
1662 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1663 "512", "256", "", "i", "64", "8", "4", "2",
1664 SSEPackedInt, HasAVX512>,
1665 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1667 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1668 "64", "32", "16", SSEPackedInt, HasBWI>,
1669 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1670 "i", "8", "64", "32", "16", SSEPackedInt,
1671 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1673 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1674 "32", "16", "8", SSEPackedInt, HasBWI>,
1675 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1676 "i", "16", "32", "16", "8", SSEPackedInt,
1677 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1679 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1680 "16", "8", "4", SSEPackedInt, HasAVX512>,
1681 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1682 "i", "32", "16", "8", "4", SSEPackedInt,
1683 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1685 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1686 "8", "4", "2", SSEPackedInt, HasAVX512>,
1687 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1688 "i", "64", "8", "4", "2", SSEPackedInt,
1689 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1691 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1692 (v16i32 immAllZerosV), GR16:$mask)),
1693 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1695 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1696 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1697 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1699 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1701 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1703 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1705 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1708 let AddedComplexity = 20 in {
1709 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1710 (bc_v8i64 (v16i32 immAllZerosV)))),
1711 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1713 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1714 (v8i64 VR512:$src))),
1715 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1718 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1719 (v16i32 immAllZerosV))),
1720 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1722 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1723 (v16i32 VR512:$src))),
1724 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1727 // Move Int Doubleword to Packed Double Int
1729 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1730 "vmovd\t{$src, $dst|$dst, $src}",
1732 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1734 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1735 "vmovd\t{$src, $dst|$dst, $src}",
1737 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1738 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1739 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1740 "vmovq\t{$src, $dst|$dst, $src}",
1742 (v2i64 (scalar_to_vector GR64:$src)))],
1743 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1744 let isCodeGenOnly = 1 in {
1745 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1746 "vmovq\t{$src, $dst|$dst, $src}",
1747 [(set FR64:$dst, (bitconvert GR64:$src))],
1748 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1749 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1750 "vmovq\t{$src, $dst|$dst, $src}",
1751 [(set GR64:$dst, (bitconvert FR64:$src))],
1752 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1754 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1755 "vmovq\t{$src, $dst|$dst, $src}",
1756 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1757 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1758 EVEX_CD8<64, CD8VT1>;
1760 // Move Int Doubleword to Single Scalar
1762 let isCodeGenOnly = 1 in {
1763 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1764 "vmovd\t{$src, $dst|$dst, $src}",
1765 [(set FR32X:$dst, (bitconvert GR32:$src))],
1766 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1768 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1769 "vmovd\t{$src, $dst|$dst, $src}",
1770 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1771 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1774 // Move doubleword from xmm register to r/m32
1776 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1777 "vmovd\t{$src, $dst|$dst, $src}",
1778 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1779 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1781 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1782 (ins i32mem:$dst, VR128X:$src),
1783 "vmovd\t{$src, $dst|$dst, $src}",
1784 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1785 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1786 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1788 // Move quadword from xmm1 register to r/m64
1790 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1791 "vmovq\t{$src, $dst|$dst, $src}",
1792 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1794 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1795 Requires<[HasAVX512, In64BitMode]>;
1797 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1798 (ins i64mem:$dst, VR128X:$src),
1799 "vmovq\t{$src, $dst|$dst, $src}",
1800 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1801 addr:$dst)], IIC_SSE_MOVDQ>,
1802 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1803 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1805 // Move Scalar Single to Double Int
1807 let isCodeGenOnly = 1 in {
1808 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1810 "vmovd\t{$src, $dst|$dst, $src}",
1811 [(set GR32:$dst, (bitconvert FR32X:$src))],
1812 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1813 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1814 (ins i32mem:$dst, FR32X:$src),
1815 "vmovd\t{$src, $dst|$dst, $src}",
1816 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1817 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1820 // Move Quadword Int to Packed Quadword Int
1822 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1824 "vmovq\t{$src, $dst|$dst, $src}",
1826 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1827 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1829 //===----------------------------------------------------------------------===//
1830 // AVX-512 MOVSS, MOVSD
1831 //===----------------------------------------------------------------------===//
1833 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1834 SDNode OpNode, ValueType vt,
1835 X86MemOperand x86memop, PatFrag mem_pat> {
1836 let hasSideEffects = 0 in {
1837 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1838 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1839 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1840 (scalar_to_vector RC:$src2))))],
1841 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1842 let Constraints = "$src1 = $dst" in
1843 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1844 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1846 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1847 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1848 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1849 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1850 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1852 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1853 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1854 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1856 } //hasSideEffects = 0
1859 let ExeDomain = SSEPackedSingle in
1860 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1861 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1863 let ExeDomain = SSEPackedDouble in
1864 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1865 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1867 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1868 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1869 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1871 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1872 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1873 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1875 // For the disassembler
1876 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1877 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1878 (ins VR128X:$src1, FR32X:$src2),
1879 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1881 XS, EVEX_4V, VEX_LIG;
1882 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1883 (ins VR128X:$src1, FR64X:$src2),
1884 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1886 XD, EVEX_4V, VEX_LIG, VEX_W;
1889 let Predicates = [HasAVX512] in {
1890 let AddedComplexity = 15 in {
1891 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1892 // MOVS{S,D} to the lower bits.
1893 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1894 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1895 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1896 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1897 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1898 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1899 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1900 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1902 // Move low f32 and clear high bits.
1903 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1904 (SUBREG_TO_REG (i32 0),
1905 (VMOVSSZrr (v4f32 (V_SET0)),
1906 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1907 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1908 (SUBREG_TO_REG (i32 0),
1909 (VMOVSSZrr (v4i32 (V_SET0)),
1910 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1913 let AddedComplexity = 20 in {
1914 // MOVSSrm zeros the high parts of the register; represent this
1915 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1916 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1917 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1918 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1919 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1920 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1921 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1923 // MOVSDrm zeros the high parts of the register; represent this
1924 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1925 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1926 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1927 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1928 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1929 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1930 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1931 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1932 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1933 def : Pat<(v2f64 (X86vzload addr:$src)),
1934 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1936 // Represent the same patterns above but in the form they appear for
1938 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1939 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1940 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1941 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1942 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1943 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1944 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1945 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1946 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1948 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1949 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1950 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1951 FR32X:$src)), sub_xmm)>;
1952 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1953 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1954 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1955 FR64X:$src)), sub_xmm)>;
1956 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1957 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1958 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1960 // Move low f64 and clear high bits.
1961 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1962 (SUBREG_TO_REG (i32 0),
1963 (VMOVSDZrr (v2f64 (V_SET0)),
1964 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1966 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1967 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1968 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1970 // Extract and store.
1971 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1973 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1974 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1976 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1978 // Shuffle with VMOVSS
1979 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1980 (VMOVSSZrr (v4i32 VR128X:$src1),
1981 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1982 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1983 (VMOVSSZrr (v4f32 VR128X:$src1),
1984 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1987 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1988 (SUBREG_TO_REG (i32 0),
1989 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1990 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1992 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1993 (SUBREG_TO_REG (i32 0),
1994 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1995 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1998 // Shuffle with VMOVSD
1999 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2000 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2001 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2002 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2003 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2004 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2005 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2006 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2009 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2010 (SUBREG_TO_REG (i32 0),
2011 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2012 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2014 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2015 (SUBREG_TO_REG (i32 0),
2016 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2017 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2020 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2021 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2022 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2023 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2024 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2025 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2026 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2027 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2030 let AddedComplexity = 15 in
2031 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2033 "vmovq\t{$src, $dst|$dst, $src}",
2034 [(set VR128X:$dst, (v2i64 (X86vzmovl
2035 (v2i64 VR128X:$src))))],
2036 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2038 let AddedComplexity = 20 in
2039 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2041 "vmovq\t{$src, $dst|$dst, $src}",
2042 [(set VR128X:$dst, (v2i64 (X86vzmovl
2043 (loadv2i64 addr:$src))))],
2044 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2045 EVEX_CD8<8, CD8VT8>;
2047 let Predicates = [HasAVX512] in {
2048 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2049 let AddedComplexity = 20 in {
2050 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2051 (VMOVDI2PDIZrm addr:$src)>;
2052 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2053 (VMOV64toPQIZrr GR64:$src)>;
2054 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2055 (VMOVDI2PDIZrr GR32:$src)>;
2057 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2058 (VMOVDI2PDIZrm addr:$src)>;
2059 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2060 (VMOVDI2PDIZrm addr:$src)>;
2061 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2062 (VMOVZPQILo2PQIZrm addr:$src)>;
2063 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2064 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2065 def : Pat<(v2i64 (X86vzload addr:$src)),
2066 (VMOVZPQILo2PQIZrm addr:$src)>;
2069 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2070 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2071 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2072 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2073 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2074 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2075 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2078 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2079 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2081 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2082 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2084 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2085 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2087 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2088 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2090 //===----------------------------------------------------------------------===//
2091 // AVX-512 - Non-temporals
2092 //===----------------------------------------------------------------------===//
2093 let SchedRW = [WriteLoad] in {
2094 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2095 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2096 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2097 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2098 EVEX_CD8<64, CD8VF>;
2100 let Predicates = [HasAVX512, HasVLX] in {
2101 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2103 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2104 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2105 EVEX_CD8<64, CD8VF>;
2107 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2109 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2110 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2111 EVEX_CD8<64, CD8VF>;
2115 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2116 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2117 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2118 let SchedRW = [WriteStore], mayStore = 1,
2119 AddedComplexity = 400 in
2120 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2121 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2122 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2125 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2126 string elty, string elsz, string vsz512,
2127 string vsz256, string vsz128, Domain d,
2128 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2129 let Predicates = [prd] in
2130 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2131 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2132 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2135 let Predicates = [prd, HasVLX] in {
2136 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2137 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2138 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2141 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2142 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2143 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2148 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2149 "i", "64", "8", "4", "2", SSEPackedInt,
2150 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2152 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2153 "f", "64", "8", "4", "2", SSEPackedDouble,
2154 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2156 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2157 "f", "32", "16", "8", "4", SSEPackedSingle,
2158 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2160 //===----------------------------------------------------------------------===//
2161 // AVX-512 - Integer arithmetic
2163 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2164 ValueType OpVT, RegisterClass KRC,
2165 RegisterClass RC, PatFrag memop_frag,
2166 X86MemOperand x86memop, PatFrag scalar_mfrag,
2167 X86MemOperand x86scalar_mop, string BrdcstStr,
2168 OpndItins itins, bit IsCommutable = 0> {
2169 let isCommutable = IsCommutable in
2170 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2171 (ins RC:$src1, RC:$src2),
2172 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2173 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2175 let AddedComplexity = 30 in {
2176 let Constraints = "$src0 = $dst" in
2177 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2178 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2179 !strconcat(OpcodeStr,
2180 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2181 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2182 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2184 itins.rr>, EVEX_4V, EVEX_K;
2185 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2186 (ins KRC:$mask, RC:$src1, RC:$src2),
2187 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2188 "|$dst {${mask}} {z}, $src1, $src2}"),
2189 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2190 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2191 (OpVT immAllZerosV))))],
2192 itins.rr>, EVEX_4V, EVEX_KZ;
2195 let mayLoad = 1 in {
2196 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2197 (ins RC:$src1, x86memop:$src2),
2198 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2201 let AddedComplexity = 30 in {
2202 let Constraints = "$src0 = $dst" in
2203 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2204 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2205 !strconcat(OpcodeStr,
2206 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2207 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2208 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2210 itins.rm>, EVEX_4V, EVEX_K;
2211 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2212 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2213 !strconcat(OpcodeStr,
2214 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2215 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2216 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2217 (OpVT immAllZerosV))))],
2218 itins.rm>, EVEX_4V, EVEX_KZ;
2220 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2221 (ins RC:$src1, x86scalar_mop:$src2),
2222 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2223 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2224 [(set RC:$dst, (OpNode RC:$src1,
2225 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2226 itins.rm>, EVEX_4V, EVEX_B;
2227 let AddedComplexity = 30 in {
2228 let Constraints = "$src0 = $dst" in
2229 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2230 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2231 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2232 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2234 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2235 (OpNode (OpVT RC:$src1),
2236 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2238 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2239 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2240 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2241 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2242 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2244 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2245 (OpNode (OpVT RC:$src1),
2246 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2247 (OpVT immAllZerosV))))],
2248 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2253 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2254 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2255 PatFrag memop_frag, X86MemOperand x86memop,
2256 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2257 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2258 let isCommutable = IsCommutable in
2260 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2261 (ins RC:$src1, RC:$src2),
2262 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2264 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2265 (ins KRC:$mask, RC:$src1, RC:$src2),
2266 !strconcat(OpcodeStr,
2267 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2268 [], itins.rr>, EVEX_4V, EVEX_K;
2269 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2270 (ins KRC:$mask, RC:$src1, RC:$src2),
2271 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2272 "|$dst {${mask}} {z}, $src1, $src2}"),
2273 [], itins.rr>, EVEX_4V, EVEX_KZ;
2275 let mayLoad = 1 in {
2276 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2277 (ins RC:$src1, x86memop:$src2),
2278 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2280 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2281 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2282 !strconcat(OpcodeStr,
2283 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2284 [], itins.rm>, EVEX_4V, EVEX_K;
2285 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2286 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2287 !strconcat(OpcodeStr,
2288 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2289 [], itins.rm>, EVEX_4V, EVEX_KZ;
2290 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2291 (ins RC:$src1, x86scalar_mop:$src2),
2292 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2293 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2294 [], itins.rm>, EVEX_4V, EVEX_B;
2295 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2296 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2297 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2298 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2300 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2301 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2302 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2303 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2304 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2306 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2310 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2311 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2312 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2314 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2315 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2316 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2318 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2319 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2320 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2322 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2323 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2324 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2326 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2327 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2328 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2330 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2331 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2332 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2333 EVEX_CD8<64, CD8VF>, VEX_W;
2335 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2336 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2337 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2339 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2340 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2342 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2343 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2344 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2345 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2346 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2347 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2349 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2350 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2351 SSE_INTALU_ITINS_P, 1>,
2352 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2353 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2354 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2355 SSE_INTALU_ITINS_P, 0>,
2356 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2358 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2359 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2360 SSE_INTALU_ITINS_P, 1>,
2361 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2362 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2363 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2364 SSE_INTALU_ITINS_P, 0>,
2365 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2367 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2368 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2369 SSE_INTALU_ITINS_P, 1>,
2370 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2371 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2372 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2373 SSE_INTALU_ITINS_P, 0>,
2374 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2376 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2377 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2378 SSE_INTALU_ITINS_P, 1>,
2379 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2380 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2381 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2382 SSE_INTALU_ITINS_P, 0>,
2383 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2385 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2386 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2387 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2388 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2389 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2390 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2391 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2392 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2393 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2394 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2395 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2396 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2397 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2398 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2399 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2400 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2401 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2402 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2403 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2404 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2405 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2406 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2407 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2408 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2409 //===----------------------------------------------------------------------===//
2410 // AVX-512 - Unpack Instructions
2411 //===----------------------------------------------------------------------===//
2413 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2414 PatFrag mem_frag, RegisterClass RC,
2415 X86MemOperand x86memop, string asm,
2417 def rr : AVX512PI<opc, MRMSrcReg,
2418 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2420 (vt (OpNode RC:$src1, RC:$src2)))],
2422 def rm : AVX512PI<opc, MRMSrcMem,
2423 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2425 (vt (OpNode RC:$src1,
2426 (bitconvert (mem_frag addr:$src2)))))],
2430 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2431 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2432 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2433 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2434 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2435 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2436 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2437 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2438 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2439 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2440 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2441 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2443 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2444 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2445 X86MemOperand x86memop> {
2446 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2447 (ins RC:$src1, RC:$src2),
2448 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2449 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2450 IIC_SSE_UNPCK>, EVEX_4V;
2451 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2452 (ins RC:$src1, x86memop:$src2),
2453 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2454 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2455 (bitconvert (memop_frag addr:$src2)))))],
2456 IIC_SSE_UNPCK>, EVEX_4V;
2458 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2459 VR512, memopv16i32, i512mem>, EVEX_V512,
2460 EVEX_CD8<32, CD8VF>;
2461 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2462 VR512, memopv8i64, i512mem>, EVEX_V512,
2463 VEX_W, EVEX_CD8<64, CD8VF>;
2464 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2465 VR512, memopv16i32, i512mem>, EVEX_V512,
2466 EVEX_CD8<32, CD8VF>;
2467 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2468 VR512, memopv8i64, i512mem>, EVEX_V512,
2469 VEX_W, EVEX_CD8<64, CD8VF>;
2470 //===----------------------------------------------------------------------===//
2474 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2475 SDNode OpNode, PatFrag mem_frag,
2476 X86MemOperand x86memop, ValueType OpVT> {
2477 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2478 (ins RC:$src1, i8imm:$src2),
2479 !strconcat(OpcodeStr,
2480 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2482 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2484 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2485 (ins x86memop:$src1, i8imm:$src2),
2486 !strconcat(OpcodeStr,
2487 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2489 (OpVT (OpNode (mem_frag addr:$src1),
2490 (i8 imm:$src2))))]>, EVEX;
2493 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2494 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2496 let ExeDomain = SSEPackedSingle in
2497 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2498 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2499 EVEX_CD8<32, CD8VF>;
2500 let ExeDomain = SSEPackedDouble in
2501 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2502 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2503 VEX_W, EVEX_CD8<32, CD8VF>;
2505 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2506 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2507 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2508 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2510 //===----------------------------------------------------------------------===//
2511 // AVX-512 Logical Instructions
2512 //===----------------------------------------------------------------------===//
2514 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2515 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2516 EVEX_V512, EVEX_CD8<32, CD8VF>;
2517 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2518 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2519 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2520 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2521 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2522 EVEX_V512, EVEX_CD8<32, CD8VF>;
2523 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2524 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2525 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2526 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2527 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2528 EVEX_V512, EVEX_CD8<32, CD8VF>;
2529 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2530 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2531 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2532 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2533 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2534 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2535 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2536 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2537 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2539 //===----------------------------------------------------------------------===//
2540 // AVX-512 FP arithmetic
2541 //===----------------------------------------------------------------------===//
2543 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2545 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2546 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2547 EVEX_CD8<32, CD8VT1>;
2548 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2549 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2550 EVEX_CD8<64, CD8VT1>;
2553 let isCommutable = 1 in {
2554 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2555 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2556 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2557 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2559 let isCommutable = 0 in {
2560 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2561 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2564 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2566 RegisterClass RC, ValueType vt,
2567 X86MemOperand x86memop, PatFrag mem_frag,
2568 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2570 Domain d, OpndItins itins, bit commutable> {
2571 let isCommutable = commutable in {
2572 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2573 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2574 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2577 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2578 !strconcat(OpcodeStr,
2579 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2580 [], itins.rr, d>, EVEX_4V, EVEX_K;
2582 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2583 !strconcat(OpcodeStr,
2584 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2585 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2588 let mayLoad = 1 in {
2589 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2590 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2591 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2592 itins.rm, d>, EVEX_4V;
2594 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2595 (ins RC:$src1, x86scalar_mop:$src2),
2596 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2597 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2598 [(set RC:$dst, (OpNode RC:$src1,
2599 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2600 itins.rm, d>, EVEX_4V, EVEX_B;
2602 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2603 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2604 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2605 [], itins.rm, d>, EVEX_4V, EVEX_K;
2607 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2608 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2609 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2610 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2612 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2613 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2614 " \t{${src2}", BrdcstStr,
2615 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2616 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2618 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2619 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2620 " \t{${src2}", BrdcstStr,
2621 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2623 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2627 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2628 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2629 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2631 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2632 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2633 SSE_ALU_ITINS_P.d, 1>,
2634 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2636 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2637 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2638 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2639 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2640 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2641 SSE_ALU_ITINS_P.d, 1>,
2642 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2644 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2645 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2646 SSE_ALU_ITINS_P.s, 1>,
2647 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2648 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2649 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2650 SSE_ALU_ITINS_P.s, 1>,
2651 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2653 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2654 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2655 SSE_ALU_ITINS_P.d, 1>,
2656 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2657 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2658 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2659 SSE_ALU_ITINS_P.d, 1>,
2660 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2662 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2663 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2664 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2665 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2666 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2667 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2669 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2670 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2671 SSE_ALU_ITINS_P.d, 0>,
2672 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2673 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2674 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2675 SSE_ALU_ITINS_P.d, 0>,
2676 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2678 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2679 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2680 (i16 -1), FROUND_CURRENT)),
2681 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2683 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2684 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2685 (i8 -1), FROUND_CURRENT)),
2686 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2688 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2689 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2690 (i16 -1), FROUND_CURRENT)),
2691 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2693 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2694 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2695 (i8 -1), FROUND_CURRENT)),
2696 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2697 //===----------------------------------------------------------------------===//
2698 // AVX-512 VPTESTM instructions
2699 //===----------------------------------------------------------------------===//
2701 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2702 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2703 SDNode OpNode, ValueType vt> {
2704 def rr : AVX512PI<opc, MRMSrcReg,
2705 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2706 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2707 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2708 SSEPackedInt>, EVEX_4V;
2709 def rm : AVX512PI<opc, MRMSrcMem,
2710 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2711 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2712 [(set KRC:$dst, (OpNode (vt RC:$src1),
2713 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2716 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2717 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2718 EVEX_CD8<32, CD8VF>;
2719 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2720 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2721 EVEX_CD8<64, CD8VF>;
2723 let Predicates = [HasCDI] in {
2724 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2725 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2726 EVEX_CD8<32, CD8VF>;
2727 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2728 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2729 EVEX_CD8<64, CD8VF>;
2732 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2733 (v16i32 VR512:$src2), (i16 -1))),
2734 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2736 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2737 (v8i64 VR512:$src2), (i8 -1))),
2738 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2739 //===----------------------------------------------------------------------===//
2740 // AVX-512 Shift instructions
2741 //===----------------------------------------------------------------------===//
2742 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2743 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2744 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2745 RegisterClass KRC> {
2746 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2747 (ins RC:$src1, i8imm:$src2),
2748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2749 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2750 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2751 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2752 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2753 !strconcat(OpcodeStr,
2754 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2755 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2756 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2757 (ins x86memop:$src1, i8imm:$src2),
2758 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2759 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2760 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2761 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2762 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2763 !strconcat(OpcodeStr,
2764 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2765 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2768 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2769 RegisterClass RC, ValueType vt, ValueType SrcVT,
2770 PatFrag bc_frag, RegisterClass KRC> {
2771 // src2 is always 128-bit
2772 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2773 (ins RC:$src1, VR128X:$src2),
2774 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2775 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2776 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2777 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2778 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2779 !strconcat(OpcodeStr,
2780 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2781 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2782 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2783 (ins RC:$src1, i128mem:$src2),
2784 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2785 [(set RC:$dst, (vt (OpNode RC:$src1,
2786 (bc_frag (memopv2i64 addr:$src2)))))],
2787 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2788 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2789 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2790 !strconcat(OpcodeStr,
2791 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2792 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2795 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2796 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2797 EVEX_V512, EVEX_CD8<32, CD8VF>;
2798 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2799 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2800 EVEX_CD8<32, CD8VQ>;
2802 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2803 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2804 EVEX_CD8<64, CD8VF>, VEX_W;
2805 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2806 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2807 EVEX_CD8<64, CD8VQ>, VEX_W;
2809 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2810 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2811 EVEX_CD8<32, CD8VF>;
2812 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2813 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2814 EVEX_CD8<32, CD8VQ>;
2816 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2817 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2818 EVEX_CD8<64, CD8VF>, VEX_W;
2819 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2820 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2821 EVEX_CD8<64, CD8VQ>, VEX_W;
2823 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2824 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2825 EVEX_V512, EVEX_CD8<32, CD8VF>;
2826 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2827 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2828 EVEX_CD8<32, CD8VQ>;
2830 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2831 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2832 EVEX_CD8<64, CD8VF>, VEX_W;
2833 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2834 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2835 EVEX_CD8<64, CD8VQ>, VEX_W;
2837 //===-------------------------------------------------------------------===//
2838 // Variable Bit Shifts
2839 //===-------------------------------------------------------------------===//
2840 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2841 RegisterClass RC, ValueType vt,
2842 X86MemOperand x86memop, PatFrag mem_frag> {
2843 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2844 (ins RC:$src1, RC:$src2),
2845 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2847 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2849 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2850 (ins RC:$src1, x86memop:$src2),
2851 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2853 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2857 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2858 i512mem, memopv16i32>, EVEX_V512,
2859 EVEX_CD8<32, CD8VF>;
2860 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2861 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2862 EVEX_CD8<64, CD8VF>;
2863 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2864 i512mem, memopv16i32>, EVEX_V512,
2865 EVEX_CD8<32, CD8VF>;
2866 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2867 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2868 EVEX_CD8<64, CD8VF>;
2869 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2870 i512mem, memopv16i32>, EVEX_V512,
2871 EVEX_CD8<32, CD8VF>;
2872 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2873 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2874 EVEX_CD8<64, CD8VF>;
2876 //===----------------------------------------------------------------------===//
2877 // AVX-512 - MOVDDUP
2878 //===----------------------------------------------------------------------===//
2880 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2881 X86MemOperand x86memop, PatFrag memop_frag> {
2882 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2883 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2884 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2885 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2886 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2888 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2891 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2892 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2893 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2894 (VMOVDDUPZrm addr:$src)>;
2896 //===---------------------------------------------------------------------===//
2897 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2898 //===---------------------------------------------------------------------===//
2899 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2900 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2901 X86MemOperand x86memop> {
2902 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2903 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2904 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2906 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2907 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2908 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2911 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2912 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2913 EVEX_CD8<32, CD8VF>;
2914 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2915 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2916 EVEX_CD8<32, CD8VF>;
2918 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2919 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2920 (VMOVSHDUPZrm addr:$src)>;
2921 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2922 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2923 (VMOVSLDUPZrm addr:$src)>;
2925 //===----------------------------------------------------------------------===//
2926 // Move Low to High and High to Low packed FP Instructions
2927 //===----------------------------------------------------------------------===//
2928 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2929 (ins VR128X:$src1, VR128X:$src2),
2930 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2931 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2932 IIC_SSE_MOV_LH>, EVEX_4V;
2933 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2934 (ins VR128X:$src1, VR128X:$src2),
2935 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2936 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2937 IIC_SSE_MOV_LH>, EVEX_4V;
2939 let Predicates = [HasAVX512] in {
2941 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2942 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2943 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2944 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2947 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2948 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2951 //===----------------------------------------------------------------------===//
2952 // FMA - Fused Multiply Operations
2954 let Constraints = "$src1 = $dst" in {
2955 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2956 RegisterClass RC, X86MemOperand x86memop,
2957 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2958 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2959 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2960 (ins RC:$src1, RC:$src2, RC:$src3),
2961 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2962 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2965 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2966 (ins RC:$src1, RC:$src2, x86memop:$src3),
2967 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2968 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2969 (mem_frag addr:$src3))))]>;
2970 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2971 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2972 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2973 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2974 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2975 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2977 } // Constraints = "$src1 = $dst"
2979 let ExeDomain = SSEPackedSingle in {
2980 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2981 memopv16f32, f32mem, loadf32, "{1to16}",
2982 X86Fmadd, v16f32>, EVEX_V512,
2983 EVEX_CD8<32, CD8VF>;
2984 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2985 memopv16f32, f32mem, loadf32, "{1to16}",
2986 X86Fmsub, v16f32>, EVEX_V512,
2987 EVEX_CD8<32, CD8VF>;
2988 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2989 memopv16f32, f32mem, loadf32, "{1to16}",
2990 X86Fmaddsub, v16f32>,
2991 EVEX_V512, EVEX_CD8<32, CD8VF>;
2992 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2993 memopv16f32, f32mem, loadf32, "{1to16}",
2994 X86Fmsubadd, v16f32>,
2995 EVEX_V512, EVEX_CD8<32, CD8VF>;
2996 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2997 memopv16f32, f32mem, loadf32, "{1to16}",
2998 X86Fnmadd, v16f32>, EVEX_V512,
2999 EVEX_CD8<32, CD8VF>;
3000 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
3001 memopv16f32, f32mem, loadf32, "{1to16}",
3002 X86Fnmsub, v16f32>, EVEX_V512,
3003 EVEX_CD8<32, CD8VF>;
3005 let ExeDomain = SSEPackedDouble in {
3006 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
3007 memopv8f64, f64mem, loadf64, "{1to8}",
3008 X86Fmadd, v8f64>, EVEX_V512,
3009 VEX_W, EVEX_CD8<64, CD8VF>;
3010 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
3011 memopv8f64, f64mem, loadf64, "{1to8}",
3012 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3013 EVEX_CD8<64, CD8VF>;
3014 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
3015 memopv8f64, f64mem, loadf64, "{1to8}",
3016 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3017 EVEX_CD8<64, CD8VF>;
3018 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
3019 memopv8f64, f64mem, loadf64, "{1to8}",
3020 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3021 EVEX_CD8<64, CD8VF>;
3022 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
3023 memopv8f64, f64mem, loadf64, "{1to8}",
3024 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3025 EVEX_CD8<64, CD8VF>;
3026 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
3027 memopv8f64, f64mem, loadf64, "{1to8}",
3028 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3029 EVEX_CD8<64, CD8VF>;
3032 let Constraints = "$src1 = $dst" in {
3033 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
3034 RegisterClass RC, X86MemOperand x86memop,
3035 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
3036 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
3038 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3039 (ins RC:$src1, RC:$src3, x86memop:$src2),
3040 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3041 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
3042 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3043 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
3044 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3045 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
3046 [(set RC:$dst, (OpNode RC:$src1,
3047 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
3049 } // Constraints = "$src1 = $dst"
3052 let ExeDomain = SSEPackedSingle in {
3053 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
3054 memopv16f32, f32mem, loadf32, "{1to16}",
3055 X86Fmadd, v16f32>, EVEX_V512,
3056 EVEX_CD8<32, CD8VF>;
3057 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
3058 memopv16f32, f32mem, loadf32, "{1to16}",
3059 X86Fmsub, v16f32>, EVEX_V512,
3060 EVEX_CD8<32, CD8VF>;
3061 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
3062 memopv16f32, f32mem, loadf32, "{1to16}",
3063 X86Fmaddsub, v16f32>,
3064 EVEX_V512, EVEX_CD8<32, CD8VF>;
3065 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
3066 memopv16f32, f32mem, loadf32, "{1to16}",
3067 X86Fmsubadd, v16f32>,
3068 EVEX_V512, EVEX_CD8<32, CD8VF>;
3069 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
3070 memopv16f32, f32mem, loadf32, "{1to16}",
3071 X86Fnmadd, v16f32>, EVEX_V512,
3072 EVEX_CD8<32, CD8VF>;
3073 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
3074 memopv16f32, f32mem, loadf32, "{1to16}",
3075 X86Fnmsub, v16f32>, EVEX_V512,
3076 EVEX_CD8<32, CD8VF>;
3078 let ExeDomain = SSEPackedDouble in {
3079 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
3080 memopv8f64, f64mem, loadf64, "{1to8}",
3081 X86Fmadd, v8f64>, EVEX_V512,
3082 VEX_W, EVEX_CD8<64, CD8VF>;
3083 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
3084 memopv8f64, f64mem, loadf64, "{1to8}",
3085 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3086 EVEX_CD8<64, CD8VF>;
3087 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
3088 memopv8f64, f64mem, loadf64, "{1to8}",
3089 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3090 EVEX_CD8<64, CD8VF>;
3091 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
3092 memopv8f64, f64mem, loadf64, "{1to8}",
3093 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3094 EVEX_CD8<64, CD8VF>;
3095 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
3096 memopv8f64, f64mem, loadf64, "{1to8}",
3097 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3098 EVEX_CD8<64, CD8VF>;
3099 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
3100 memopv8f64, f64mem, loadf64, "{1to8}",
3101 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3102 EVEX_CD8<64, CD8VF>;
3106 let Constraints = "$src1 = $dst" in {
3107 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3108 RegisterClass RC, ValueType OpVT,
3109 X86MemOperand x86memop, Operand memop,
3111 let isCommutable = 1 in
3112 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3113 (ins RC:$src1, RC:$src2, RC:$src3),
3114 !strconcat(OpcodeStr,
3115 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3117 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3119 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3120 (ins RC:$src1, RC:$src2, f128mem:$src3),
3121 !strconcat(OpcodeStr,
3122 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3124 (OpVT (OpNode RC:$src2, RC:$src1,
3125 (mem_frag addr:$src3))))]>;
3128 } // Constraints = "$src1 = $dst"
3130 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3131 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3132 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3133 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3134 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3135 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3136 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3137 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3138 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3139 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3140 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3141 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3142 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3143 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3144 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3145 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3147 //===----------------------------------------------------------------------===//
3148 // AVX-512 Scalar convert from sign integer to float/double
3149 //===----------------------------------------------------------------------===//
3151 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3152 X86MemOperand x86memop, string asm> {
3153 let hasSideEffects = 0 in {
3154 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3155 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3158 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3159 (ins DstRC:$src1, x86memop:$src),
3160 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3162 } // hasSideEffects = 0
3164 let Predicates = [HasAVX512] in {
3165 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3166 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3167 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3168 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3169 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3170 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3171 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3172 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3174 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3175 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3176 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3177 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3178 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3179 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3180 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3181 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3183 def : Pat<(f32 (sint_to_fp GR32:$src)),
3184 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3185 def : Pat<(f32 (sint_to_fp GR64:$src)),
3186 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3187 def : Pat<(f64 (sint_to_fp GR32:$src)),
3188 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3189 def : Pat<(f64 (sint_to_fp GR64:$src)),
3190 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3192 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3193 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3194 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3195 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3196 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3197 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3198 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3199 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3201 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3202 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3203 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3204 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3205 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3206 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3207 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3208 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3210 def : Pat<(f32 (uint_to_fp GR32:$src)),
3211 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3212 def : Pat<(f32 (uint_to_fp GR64:$src)),
3213 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3214 def : Pat<(f64 (uint_to_fp GR32:$src)),
3215 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3216 def : Pat<(f64 (uint_to_fp GR64:$src)),
3217 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3220 //===----------------------------------------------------------------------===//
3221 // AVX-512 Scalar convert from float/double to integer
3222 //===----------------------------------------------------------------------===//
3223 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3224 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3226 let hasSideEffects = 0 in {
3227 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3228 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3229 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3230 Requires<[HasAVX512]>;
3232 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3233 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3234 Requires<[HasAVX512]>;
3235 } // hasSideEffects = 0
3237 let Predicates = [HasAVX512] in {
3238 // Convert float/double to signed/unsigned int 32/64
3239 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3240 ssmem, sse_load_f32, "cvtss2si">,
3241 XS, EVEX_CD8<32, CD8VT1>;
3242 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3243 ssmem, sse_load_f32, "cvtss2si">,
3244 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3245 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3246 ssmem, sse_load_f32, "cvtss2usi">,
3247 XS, EVEX_CD8<32, CD8VT1>;
3248 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3249 int_x86_avx512_cvtss2usi64, ssmem,
3250 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3251 EVEX_CD8<32, CD8VT1>;
3252 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3253 sdmem, sse_load_f64, "cvtsd2si">,
3254 XD, EVEX_CD8<64, CD8VT1>;
3255 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3256 sdmem, sse_load_f64, "cvtsd2si">,
3257 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3258 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3259 sdmem, sse_load_f64, "cvtsd2usi">,
3260 XD, EVEX_CD8<64, CD8VT1>;
3261 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3262 int_x86_avx512_cvtsd2usi64, sdmem,
3263 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3264 EVEX_CD8<64, CD8VT1>;
3266 let isCodeGenOnly = 1 in {
3267 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3268 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3269 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3270 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3271 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3272 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3273 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3274 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3275 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3276 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3277 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3278 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3280 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3281 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3282 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3283 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3284 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3285 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3286 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3287 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3288 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3289 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3290 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3291 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3292 } // isCodeGenOnly = 1
3294 // Convert float/double to signed/unsigned int 32/64 with truncation
3295 let isCodeGenOnly = 1 in {
3296 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3297 ssmem, sse_load_f32, "cvttss2si">,
3298 XS, EVEX_CD8<32, CD8VT1>;
3299 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3300 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3301 "cvttss2si">, XS, VEX_W,
3302 EVEX_CD8<32, CD8VT1>;
3303 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3304 sdmem, sse_load_f64, "cvttsd2si">, XD,
3305 EVEX_CD8<64, CD8VT1>;
3306 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3307 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3308 "cvttsd2si">, XD, VEX_W,
3309 EVEX_CD8<64, CD8VT1>;
3310 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3311 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3312 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3313 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3314 int_x86_avx512_cvttss2usi64, ssmem,
3315 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3316 EVEX_CD8<32, CD8VT1>;
3317 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3318 int_x86_avx512_cvttsd2usi,
3319 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3320 EVEX_CD8<64, CD8VT1>;
3321 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3322 int_x86_avx512_cvttsd2usi64, sdmem,
3323 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3324 EVEX_CD8<64, CD8VT1>;
3325 } // isCodeGenOnly = 1
3327 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3328 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3330 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3331 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3332 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3333 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3334 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3335 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3338 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3339 loadf32, "cvttss2si">, XS,
3340 EVEX_CD8<32, CD8VT1>;
3341 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3342 loadf32, "cvttss2usi">, XS,
3343 EVEX_CD8<32, CD8VT1>;
3344 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3345 loadf32, "cvttss2si">, XS, VEX_W,
3346 EVEX_CD8<32, CD8VT1>;
3347 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3348 loadf32, "cvttss2usi">, XS, VEX_W,
3349 EVEX_CD8<32, CD8VT1>;
3350 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3351 loadf64, "cvttsd2si">, XD,
3352 EVEX_CD8<64, CD8VT1>;
3353 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3354 loadf64, "cvttsd2usi">, XD,
3355 EVEX_CD8<64, CD8VT1>;
3356 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3357 loadf64, "cvttsd2si">, XD, VEX_W,
3358 EVEX_CD8<64, CD8VT1>;
3359 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3360 loadf64, "cvttsd2usi">, XD, VEX_W,
3361 EVEX_CD8<64, CD8VT1>;
3363 //===----------------------------------------------------------------------===//
3364 // AVX-512 Convert form float to double and back
3365 //===----------------------------------------------------------------------===//
3366 let hasSideEffects = 0 in {
3367 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3368 (ins FR32X:$src1, FR32X:$src2),
3369 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3370 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3372 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3373 (ins FR32X:$src1, f32mem:$src2),
3374 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3375 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3376 EVEX_CD8<32, CD8VT1>;
3378 // Convert scalar double to scalar single
3379 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3380 (ins FR64X:$src1, FR64X:$src2),
3381 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3382 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3384 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3385 (ins FR64X:$src1, f64mem:$src2),
3386 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3387 []>, EVEX_4V, VEX_LIG, VEX_W,
3388 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3391 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3392 Requires<[HasAVX512]>;
3393 def : Pat<(fextend (loadf32 addr:$src)),
3394 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3396 def : Pat<(extloadf32 addr:$src),
3397 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3398 Requires<[HasAVX512, OptForSize]>;
3400 def : Pat<(extloadf32 addr:$src),
3401 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3402 Requires<[HasAVX512, OptForSpeed]>;
3404 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3405 Requires<[HasAVX512]>;
3407 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3408 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3409 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3411 let hasSideEffects = 0 in {
3412 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3413 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3415 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3416 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3417 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3418 [], d>, EVEX, EVEX_B, EVEX_RC;
3420 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3421 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3423 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3424 } // hasSideEffects = 0
3427 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3428 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3429 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3431 let hasSideEffects = 0 in {
3432 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3433 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3435 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3437 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3438 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3440 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3441 } // hasSideEffects = 0
3444 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3445 memopv8f64, f512mem, v8f32, v8f64,
3446 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3447 EVEX_CD8<64, CD8VF>;
3449 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3450 memopv4f64, f256mem, v8f64, v8f32,
3451 SSEPackedDouble>, EVEX_V512, PS,
3452 EVEX_CD8<32, CD8VH>;
3453 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3454 (VCVTPS2PDZrm addr:$src)>;
3456 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3457 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3458 (VCVTPD2PSZrr VR512:$src)>;
3460 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3461 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3462 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3464 //===----------------------------------------------------------------------===//
3465 // AVX-512 Vector convert from sign integer to float/double
3466 //===----------------------------------------------------------------------===//
3468 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3469 memopv8i64, i512mem, v16f32, v16i32,
3470 SSEPackedSingle>, EVEX_V512, PS,
3471 EVEX_CD8<32, CD8VF>;
3473 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3474 memopv4i64, i256mem, v8f64, v8i32,
3475 SSEPackedDouble>, EVEX_V512, XS,
3476 EVEX_CD8<32, CD8VH>;
3478 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3479 memopv16f32, f512mem, v16i32, v16f32,
3480 SSEPackedSingle>, EVEX_V512, XS,
3481 EVEX_CD8<32, CD8VF>;
3483 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3484 memopv8f64, f512mem, v8i32, v8f64,
3485 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3486 EVEX_CD8<64, CD8VF>;
3488 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3489 memopv16f32, f512mem, v16i32, v16f32,
3490 SSEPackedSingle>, EVEX_V512, PS,
3491 EVEX_CD8<32, CD8VF>;
3493 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3494 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3495 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3496 (VCVTTPS2UDQZrr VR512:$src)>;
3498 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3499 memopv8f64, f512mem, v8i32, v8f64,
3500 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3501 EVEX_CD8<64, CD8VF>;
3503 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3504 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3505 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3506 (VCVTTPD2UDQZrr VR512:$src)>;
3508 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3509 memopv4i64, f256mem, v8f64, v8i32,
3510 SSEPackedDouble>, EVEX_V512, XS,
3511 EVEX_CD8<32, CD8VH>;
3513 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3514 memopv16i32, f512mem, v16f32, v16i32,
3515 SSEPackedSingle>, EVEX_V512, XD,
3516 EVEX_CD8<32, CD8VF>;
3518 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3519 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3520 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3522 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3523 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3524 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3526 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3527 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3528 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3530 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3531 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3532 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3534 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3535 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3536 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3538 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3539 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3540 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3541 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3542 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3543 (VCVTDQ2PDZrr VR256X:$src)>;
3544 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3545 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3546 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3547 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3548 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3549 (VCVTUDQ2PDZrr VR256X:$src)>;
3551 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3552 RegisterClass DstRC, PatFrag mem_frag,
3553 X86MemOperand x86memop, Domain d> {
3554 let hasSideEffects = 0 in {
3555 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3556 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3558 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3559 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3560 [], d>, EVEX, EVEX_B, EVEX_RC;
3562 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3563 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3565 } // hasSideEffects = 0
3568 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3569 memopv16f32, f512mem, SSEPackedSingle>, PD,
3570 EVEX_V512, EVEX_CD8<32, CD8VF>;
3571 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3572 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3573 EVEX_V512, EVEX_CD8<64, CD8VF>;
3575 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3576 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3577 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3579 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3580 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3581 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3583 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3584 memopv16f32, f512mem, SSEPackedSingle>,
3585 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3586 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3587 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3588 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3590 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3591 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3592 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3594 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3595 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3596 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3598 let Predicates = [HasAVX512] in {
3599 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3600 (VCVTPD2PSZrm addr:$src)>;
3601 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3602 (VCVTPS2PDZrm addr:$src)>;
3605 //===----------------------------------------------------------------------===//
3606 // Half precision conversion instructions
3607 //===----------------------------------------------------------------------===//
3608 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3609 X86MemOperand x86memop> {
3610 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3611 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3613 let hasSideEffects = 0, mayLoad = 1 in
3614 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3615 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3618 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3619 X86MemOperand x86memop> {
3620 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3621 (ins srcRC:$src1, i32i8imm:$src2),
3622 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3624 let hasSideEffects = 0, mayStore = 1 in
3625 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3626 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3627 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3630 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3631 EVEX_CD8<32, CD8VH>;
3632 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3633 EVEX_CD8<32, CD8VH>;
3635 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3636 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3637 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3639 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3640 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3641 (VCVTPH2PSZrr VR256X:$src)>;
3643 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3644 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3645 "ucomiss">, PS, EVEX, VEX_LIG,
3646 EVEX_CD8<32, CD8VT1>;
3647 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3648 "ucomisd">, PD, EVEX,
3649 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3650 let Pattern = []<dag> in {
3651 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3652 "comiss">, PS, EVEX, VEX_LIG,
3653 EVEX_CD8<32, CD8VT1>;
3654 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3655 "comisd">, PD, EVEX,
3656 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3658 let isCodeGenOnly = 1 in {
3659 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3660 load, "ucomiss">, PS, EVEX, VEX_LIG,
3661 EVEX_CD8<32, CD8VT1>;
3662 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3663 load, "ucomisd">, PD, EVEX,
3664 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3666 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3667 load, "comiss">, PS, EVEX, VEX_LIG,
3668 EVEX_CD8<32, CD8VT1>;
3669 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3670 load, "comisd">, PD, EVEX,
3671 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3675 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3676 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3677 X86MemOperand x86memop> {
3678 let hasSideEffects = 0 in {
3679 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3680 (ins RC:$src1, RC:$src2),
3681 !strconcat(OpcodeStr,
3682 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3683 let mayLoad = 1 in {
3684 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3685 (ins RC:$src1, x86memop:$src2),
3686 !strconcat(OpcodeStr,
3687 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3692 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3693 EVEX_CD8<32, CD8VT1>;
3694 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3695 VEX_W, EVEX_CD8<64, CD8VT1>;
3696 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3697 EVEX_CD8<32, CD8VT1>;
3698 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3699 VEX_W, EVEX_CD8<64, CD8VT1>;
3701 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3702 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3703 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3704 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3706 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3707 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3708 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3709 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3711 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3712 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3713 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3714 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3716 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3717 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3718 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3719 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3721 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3722 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3723 RegisterClass RC, X86MemOperand x86memop,
3724 PatFrag mem_frag, ValueType OpVt> {
3725 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3726 !strconcat(OpcodeStr,
3727 " \t{$src, $dst|$dst, $src}"),
3728 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3730 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3731 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3732 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3735 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3736 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3737 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3738 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3739 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3740 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3741 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3742 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3744 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3745 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3746 (VRSQRT14PSZr VR512:$src)>;
3747 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3748 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3749 (VRSQRT14PDZr VR512:$src)>;
3751 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3752 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3753 (VRCP14PSZr VR512:$src)>;
3754 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3755 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3756 (VRCP14PDZr VR512:$src)>;
3758 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3759 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3760 X86MemOperand x86memop> {
3761 let hasSideEffects = 0, Predicates = [HasERI] in {
3762 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3763 (ins RC:$src1, RC:$src2),
3764 !strconcat(OpcodeStr,
3765 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3766 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3767 (ins RC:$src1, RC:$src2),
3768 !strconcat(OpcodeStr,
3769 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3770 []>, EVEX_4V, EVEX_B;
3771 let mayLoad = 1 in {
3772 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3773 (ins RC:$src1, x86memop:$src2),
3774 !strconcat(OpcodeStr,
3775 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3780 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3781 EVEX_CD8<32, CD8VT1>;
3782 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3783 VEX_W, EVEX_CD8<64, CD8VT1>;
3784 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3785 EVEX_CD8<32, CD8VT1>;
3786 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3787 VEX_W, EVEX_CD8<64, CD8VT1>;
3789 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3790 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3792 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3793 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3795 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3796 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3798 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3799 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3801 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3802 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3804 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3805 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3807 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3808 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3810 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3811 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3813 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3814 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3815 RegisterClass RC, X86MemOperand x86memop> {
3816 let hasSideEffects = 0, Predicates = [HasERI] in {
3817 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3818 !strconcat(OpcodeStr,
3819 " \t{$src, $dst|$dst, $src}"),
3821 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3822 !strconcat(OpcodeStr,
3823 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3825 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3826 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3830 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3831 EVEX_V512, EVEX_CD8<32, CD8VF>;
3832 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3833 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3834 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3835 EVEX_V512, EVEX_CD8<32, CD8VF>;
3836 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3837 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3839 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3840 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3841 (VRSQRT28PSZrb VR512:$src)>;
3842 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3843 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3844 (VRSQRT28PDZrb VR512:$src)>;
3846 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3847 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3848 (VRCP28PSZrb VR512:$src)>;
3849 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3850 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3851 (VRCP28PDZrb VR512:$src)>;
3853 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3854 OpndItins itins_s, OpndItins itins_d> {
3855 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3856 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3857 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3861 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3862 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3864 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3865 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3867 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3868 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3869 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3873 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3874 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3875 [(set VR512:$dst, (OpNode
3876 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3877 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3881 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3882 Intrinsic F32Int, Intrinsic F64Int,
3883 OpndItins itins_s, OpndItins itins_d> {
3884 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3885 (ins FR32X:$src1, FR32X:$src2),
3886 !strconcat(OpcodeStr,
3887 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3888 [], itins_s.rr>, XS, EVEX_4V;
3889 let isCodeGenOnly = 1 in
3890 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3891 (ins VR128X:$src1, VR128X:$src2),
3892 !strconcat(OpcodeStr,
3893 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3895 (F32Int VR128X:$src1, VR128X:$src2))],
3896 itins_s.rr>, XS, EVEX_4V;
3897 let mayLoad = 1 in {
3898 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3899 (ins FR32X:$src1, f32mem:$src2),
3900 !strconcat(OpcodeStr,
3901 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3902 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3903 let isCodeGenOnly = 1 in
3904 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3905 (ins VR128X:$src1, ssmem:$src2),
3906 !strconcat(OpcodeStr,
3907 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3909 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3910 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3912 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3913 (ins FR64X:$src1, FR64X:$src2),
3914 !strconcat(OpcodeStr,
3915 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3917 let isCodeGenOnly = 1 in
3918 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3919 (ins VR128X:$src1, VR128X:$src2),
3920 !strconcat(OpcodeStr,
3921 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3923 (F64Int VR128X:$src1, VR128X:$src2))],
3924 itins_s.rr>, XD, EVEX_4V, VEX_W;
3925 let mayLoad = 1 in {
3926 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3927 (ins FR64X:$src1, f64mem:$src2),
3928 !strconcat(OpcodeStr,
3929 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3930 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3931 let isCodeGenOnly = 1 in
3932 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3933 (ins VR128X:$src1, sdmem:$src2),
3934 !strconcat(OpcodeStr,
3935 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3937 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3938 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3943 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3944 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3945 SSE_SQRTSS, SSE_SQRTSD>,
3946 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3947 SSE_SQRTPS, SSE_SQRTPD>;
3949 let Predicates = [HasAVX512] in {
3950 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3951 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3952 (VSQRTPSZrr VR512:$src1)>;
3953 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3954 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3955 (VSQRTPDZrr VR512:$src1)>;
3957 def : Pat<(f32 (fsqrt FR32X:$src)),
3958 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3959 def : Pat<(f32 (fsqrt (load addr:$src))),
3960 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3961 Requires<[OptForSize]>;
3962 def : Pat<(f64 (fsqrt FR64X:$src)),
3963 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3964 def : Pat<(f64 (fsqrt (load addr:$src))),
3965 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3966 Requires<[OptForSize]>;
3968 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3969 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3970 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3971 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3972 Requires<[OptForSize]>;
3974 def : Pat<(f32 (X86frcp FR32X:$src)),
3975 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3976 def : Pat<(f32 (X86frcp (load addr:$src))),
3977 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3978 Requires<[OptForSize]>;
3980 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3981 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3982 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3984 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3985 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3987 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3988 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3989 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3991 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3992 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3996 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3997 X86MemOperand x86memop, RegisterClass RC,
3998 PatFrag mem_frag32, PatFrag mem_frag64,
3999 Intrinsic V4F32Int, Intrinsic V2F64Int,
4001 let ExeDomain = SSEPackedSingle in {
4002 // Intrinsic operation, reg.
4003 // Vector intrinsic operation, reg
4004 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4005 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4006 !strconcat(OpcodeStr,
4007 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4008 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4010 // Vector intrinsic operation, mem
4011 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4012 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4013 !strconcat(OpcodeStr,
4014 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4016 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4017 EVEX_CD8<32, VForm>;
4018 } // ExeDomain = SSEPackedSingle
4020 let ExeDomain = SSEPackedDouble in {
4021 // Vector intrinsic operation, reg
4022 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4023 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4024 !strconcat(OpcodeStr,
4025 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4026 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4028 // Vector intrinsic operation, mem
4029 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4030 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4031 !strconcat(OpcodeStr,
4032 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4034 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4035 EVEX_CD8<64, VForm>;
4036 } // ExeDomain = SSEPackedDouble
4039 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4043 let ExeDomain = GenericDomain in {
4045 let hasSideEffects = 0 in
4046 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4047 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4048 !strconcat(OpcodeStr,
4049 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4052 // Intrinsic operation, reg.
4053 let isCodeGenOnly = 1 in
4054 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4055 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4056 !strconcat(OpcodeStr,
4057 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4058 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4060 // Intrinsic operation, mem.
4061 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4062 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4063 !strconcat(OpcodeStr,
4064 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4065 [(set VR128X:$dst, (F32Int VR128X:$src1,
4066 sse_load_f32:$src2, imm:$src3))]>,
4067 EVEX_CD8<32, CD8VT1>;
4070 let hasSideEffects = 0 in
4071 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4072 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4073 !strconcat(OpcodeStr,
4074 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4077 // Intrinsic operation, reg.
4078 let isCodeGenOnly = 1 in
4079 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4080 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4081 !strconcat(OpcodeStr,
4082 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4083 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4086 // Intrinsic operation, mem.
4087 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4088 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4089 !strconcat(OpcodeStr,
4090 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4092 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4093 VEX_W, EVEX_CD8<64, CD8VT1>;
4094 } // ExeDomain = GenericDomain
4097 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4098 X86MemOperand x86memop, RegisterClass RC,
4099 PatFrag mem_frag, Domain d> {
4100 let ExeDomain = d in {
4101 // Intrinsic operation, reg.
4102 // Vector intrinsic operation, reg
4103 def r : AVX512AIi8<opc, MRMSrcReg,
4104 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4105 !strconcat(OpcodeStr,
4106 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 // Vector intrinsic operation, mem
4110 def m : AVX512AIi8<opc, MRMSrcMem,
4111 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4112 !strconcat(OpcodeStr,
4113 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4119 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4120 memopv16f32, SSEPackedSingle>, EVEX_V512,
4121 EVEX_CD8<32, CD8VF>;
4123 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4124 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4126 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4129 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4130 memopv8f64, SSEPackedDouble>, EVEX_V512,
4131 VEX_W, EVEX_CD8<64, CD8VF>;
4133 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4134 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4136 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4138 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4139 Operand x86memop, RegisterClass RC, Domain d> {
4140 let ExeDomain = d in {
4141 def r : AVX512AIi8<opc, MRMSrcReg,
4142 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4143 !strconcat(OpcodeStr,
4144 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4147 def m : AVX512AIi8<opc, MRMSrcMem,
4148 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4149 !strconcat(OpcodeStr,
4150 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4155 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4156 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4158 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4159 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4161 def : Pat<(ffloor FR32X:$src),
4162 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4163 def : Pat<(f64 (ffloor FR64X:$src)),
4164 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4165 def : Pat<(f32 (fnearbyint FR32X:$src)),
4166 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4167 def : Pat<(f64 (fnearbyint FR64X:$src)),
4168 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4169 def : Pat<(f32 (fceil FR32X:$src)),
4170 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4171 def : Pat<(f64 (fceil FR64X:$src)),
4172 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4173 def : Pat<(f32 (frint FR32X:$src)),
4174 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4175 def : Pat<(f64 (frint FR64X:$src)),
4176 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4177 def : Pat<(f32 (ftrunc FR32X:$src)),
4178 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4179 def : Pat<(f64 (ftrunc FR64X:$src)),
4180 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4182 def : Pat<(v16f32 (ffloor VR512:$src)),
4183 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4184 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4185 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4186 def : Pat<(v16f32 (fceil VR512:$src)),
4187 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4188 def : Pat<(v16f32 (frint VR512:$src)),
4189 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4190 def : Pat<(v16f32 (ftrunc VR512:$src)),
4191 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4193 def : Pat<(v8f64 (ffloor VR512:$src)),
4194 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4195 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4196 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4197 def : Pat<(v8f64 (fceil VR512:$src)),
4198 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4199 def : Pat<(v8f64 (frint VR512:$src)),
4200 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4201 def : Pat<(v8f64 (ftrunc VR512:$src)),
4202 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4204 //-------------------------------------------------
4205 // Integer truncate and extend operations
4206 //-------------------------------------------------
4208 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4209 RegisterClass dstRC, RegisterClass srcRC,
4210 RegisterClass KRC, X86MemOperand x86memop> {
4211 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4213 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4216 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4217 (ins KRC:$mask, srcRC:$src),
4218 !strconcat(OpcodeStr,
4219 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4222 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4223 (ins KRC:$mask, srcRC:$src),
4224 !strconcat(OpcodeStr,
4225 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4228 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4229 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4232 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4233 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4234 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4238 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4239 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4240 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4241 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4242 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4243 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4244 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4245 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4246 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4247 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4248 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4249 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4250 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4251 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4252 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4253 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4254 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4255 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4256 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4257 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4258 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4259 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4260 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4261 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4262 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4263 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4264 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4265 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4266 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4267 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4269 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4270 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4271 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4272 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4273 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4275 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4276 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4277 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4278 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4279 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4280 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4281 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4282 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4285 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4286 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4287 PatFrag mem_frag, X86MemOperand x86memop,
4288 ValueType OpVT, ValueType InVT> {
4290 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4292 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4293 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4295 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4296 (ins KRC:$mask, SrcRC:$src),
4297 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4300 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4301 (ins KRC:$mask, SrcRC:$src),
4302 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4305 let mayLoad = 1 in {
4306 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4307 (ins x86memop:$src),
4308 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4310 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4313 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4314 (ins KRC:$mask, x86memop:$src),
4315 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4319 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4320 (ins KRC:$mask, x86memop:$src),
4321 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4327 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4328 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4330 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4331 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4333 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4334 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4335 EVEX_CD8<16, CD8VH>;
4336 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4337 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4338 EVEX_CD8<16, CD8VQ>;
4339 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4340 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4341 EVEX_CD8<32, CD8VH>;
4343 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4344 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4346 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4347 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4349 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4350 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4351 EVEX_CD8<16, CD8VH>;
4352 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4353 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4354 EVEX_CD8<16, CD8VQ>;
4355 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4356 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4357 EVEX_CD8<32, CD8VH>;
4359 //===----------------------------------------------------------------------===//
4360 // GATHER - SCATTER Operations
4362 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4363 RegisterClass RC, X86MemOperand memop> {
4365 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4366 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4367 (ins RC:$src1, KRC:$mask, memop:$src2),
4368 !strconcat(OpcodeStr,
4369 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4373 let ExeDomain = SSEPackedDouble in {
4374 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4375 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4376 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4377 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4380 let ExeDomain = SSEPackedSingle in {
4381 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4382 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4383 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4384 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4387 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4388 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4389 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4390 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4392 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4393 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4394 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4395 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4397 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4398 RegisterClass RC, X86MemOperand memop> {
4399 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4400 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4401 (ins memop:$dst, KRC:$mask, RC:$src2),
4402 !strconcat(OpcodeStr,
4403 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4407 let ExeDomain = SSEPackedDouble in {
4408 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4409 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4410 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4411 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4414 let ExeDomain = SSEPackedSingle in {
4415 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4416 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4417 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4418 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4421 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4422 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4423 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4424 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4426 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4427 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4428 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4429 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4432 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4433 RegisterClass KRC, X86MemOperand memop> {
4434 let Predicates = [HasPFI], hasSideEffects = 1 in
4435 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4436 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4440 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4441 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4443 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4444 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4446 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4447 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4449 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4450 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4452 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4453 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4455 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4456 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4458 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4459 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4461 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4462 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4464 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4465 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4467 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4468 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4470 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4471 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4473 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4474 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4476 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4477 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4479 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4480 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4482 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4483 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4485 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4486 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4487 //===----------------------------------------------------------------------===//
4488 // VSHUFPS - VSHUFPD Operations
4490 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4491 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4493 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4494 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4495 !strconcat(OpcodeStr,
4496 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4497 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4498 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4499 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4500 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4501 (ins RC:$src1, RC:$src2, i8imm:$src3),
4502 !strconcat(OpcodeStr,
4503 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4504 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4505 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4506 EVEX_4V, Sched<[WriteShuffle]>;
4509 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4510 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4511 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4512 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4514 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4515 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4516 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4517 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4518 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4520 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4521 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4522 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4523 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4524 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4526 multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC,
4527 RegisterClass MRC, X86MemOperand x86memop,
4528 ValueType IntVT, ValueType FloatVT> {
4529 defm rri : AVX512_masking<0x03, MRMSrcReg, (outs RC:$dst),
4530 (ins RC:$src1, RC:$src2, i8imm:$src3),
4532 "$src3, $src2, $src1", "$src1, $src2, $src3",
4533 (IntVT (X86VAlign RC:$src2, RC:$src1,
4536 AVX512AIi8Base, EVEX_4V;
4538 // Also match valign of packed floats.
4539 def : Pat<(FloatVT (X86VAlign RC:$src1, RC:$src2, (i8 imm:$imm))),
4540 (!cast<Instruction>(NAME##rri) RC:$src2, RC:$src1, imm:$imm)>;
4543 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4544 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4545 !strconcat("valign"##Suffix,
4546 " \t{$src3, $src2, $src1, $dst|"
4547 "$dst, $src1, $src2, $src3}"),
4550 defm VALIGND : avx512_valign<"d", VR512, VK16WM, GR16, i512mem, v16i32, v16f32>,
4551 EVEX_V512, EVEX_CD8<32, CD8VF>;
4552 defm VALIGNQ : avx512_valign<"q", VR512, VK8WM, GR8, i512mem, v8i64, v8f64>,
4553 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4555 // Helper fragments to match sext vXi1 to vXiY.
4556 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4557 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4559 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4560 RegisterClass KRC, RegisterClass RC,
4561 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4563 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4564 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4566 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4567 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4569 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4570 !strconcat(OpcodeStr,
4571 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4573 let mayLoad = 1 in {
4574 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4575 (ins x86memop:$src),
4576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4578 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4579 (ins KRC:$mask, x86memop:$src),
4580 !strconcat(OpcodeStr,
4581 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4583 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4584 (ins KRC:$mask, x86memop:$src),
4585 !strconcat(OpcodeStr,
4586 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4588 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4589 (ins x86scalar_mop:$src),
4590 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4591 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4593 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4594 (ins KRC:$mask, x86scalar_mop:$src),
4595 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4596 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4597 []>, EVEX, EVEX_B, EVEX_K;
4598 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4599 (ins KRC:$mask, x86scalar_mop:$src),
4600 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4601 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4603 []>, EVEX, EVEX_B, EVEX_KZ;
4607 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4608 i512mem, i32mem, "{1to16}">, EVEX_V512,
4609 EVEX_CD8<32, CD8VF>;
4610 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4611 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4612 EVEX_CD8<64, CD8VF>;
4615 (bc_v16i32 (v16i1sextv16i32)),
4616 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4617 (VPABSDZrr VR512:$src)>;
4619 (bc_v8i64 (v8i1sextv8i64)),
4620 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4621 (VPABSQZrr VR512:$src)>;
4623 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4624 (v16i32 immAllZerosV), (i16 -1))),
4625 (VPABSDZrr VR512:$src)>;
4626 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4627 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4628 (VPABSQZrr VR512:$src)>;
4630 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4631 RegisterClass RC, RegisterClass KRC,
4632 X86MemOperand x86memop,
4633 X86MemOperand x86scalar_mop, string BrdcstStr> {
4634 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4636 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4639 (ins x86memop:$src),
4640 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4642 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4643 (ins x86scalar_mop:$src),
4644 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4645 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4647 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4648 (ins KRC:$mask, RC:$src),
4649 !strconcat(OpcodeStr,
4650 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4652 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4653 (ins KRC:$mask, x86memop:$src),
4654 !strconcat(OpcodeStr,
4655 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4657 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4658 (ins KRC:$mask, x86scalar_mop:$src),
4659 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4660 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4662 []>, EVEX, EVEX_KZ, EVEX_B;
4664 let Constraints = "$src1 = $dst" in {
4665 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4666 (ins RC:$src1, KRC:$mask, RC:$src2),
4667 !strconcat(OpcodeStr,
4668 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4670 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4671 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4672 !strconcat(OpcodeStr,
4673 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4675 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4676 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4677 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4678 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4679 []>, EVEX, EVEX_K, EVEX_B;
4683 let Predicates = [HasCDI] in {
4684 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4685 i512mem, i32mem, "{1to16}">,
4686 EVEX_V512, EVEX_CD8<32, CD8VF>;
4689 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4690 i512mem, i64mem, "{1to8}">,
4691 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4695 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4697 (VPCONFLICTDrrk VR512:$src1,
4698 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4700 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4702 (VPCONFLICTQrrk VR512:$src1,
4703 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4705 let Predicates = [HasCDI] in {
4706 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4707 i512mem, i32mem, "{1to16}">,
4708 EVEX_V512, EVEX_CD8<32, CD8VF>;
4711 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4712 i512mem, i64mem, "{1to8}">,
4713 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4717 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4719 (VPLZCNTDrrk VR512:$src1,
4720 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4722 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4724 (VPLZCNTQrrk VR512:$src1,
4725 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4727 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4728 (VPLZCNTDrm addr:$src)>;
4729 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4730 (VPLZCNTDrr VR512:$src)>;
4731 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4732 (VPLZCNTQrm addr:$src)>;
4733 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4734 (VPLZCNTQrr VR512:$src)>;
4736 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4737 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4738 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4740 def : Pat<(store VK1:$src, addr:$dst),
4741 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4743 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4744 (truncstore node:$val, node:$ptr), [{
4745 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4748 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4749 (MOV8mr addr:$dst, GR8:$src)>;