1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7187 // 2013 will allow us to use it as a non-type template parameter.
7190 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7192 /// See its documentation for details.
7193 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7194 if (Mask.size() != Args.size())
7196 for (int i = 0, e = Mask.size(); i < e; ++i) {
7197 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7198 if (Mask[i] != -1 && Mask[i] != *Args[i])
7206 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7209 /// This is a fast way to test a shuffle mask against a fixed pattern:
7211 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7213 /// It returns true if the mask is exactly as wide as the argument list, and
7214 /// each element of the mask is either -1 (signifying undef) or the value given
7215 /// in the argument.
7216 static const VariadicFunction1<
7217 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7219 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7221 /// This helper function produces an 8-bit shuffle immediate corresponding to
7222 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7223 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7226 /// NB: We rely heavily on "undef" masks preserving the input lane.
7227 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7228 SelectionDAG &DAG) {
7229 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7230 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7231 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7232 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7233 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7236 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7237 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7238 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7239 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7240 return DAG.getConstant(Imm, MVT::i8);
7243 /// \brief Try to emit a blend instruction for a shuffle.
7245 /// This doesn't do any checks for the availability of instructions for blending
7246 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7247 /// be matched in the backend with the type given. What it does check for is
7248 /// that the shuffle mask is in fact a blend.
7249 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7250 SDValue V2, ArrayRef<int> Mask,
7251 const X86Subtarget *Subtarget,
7252 SelectionDAG &DAG) {
7254 unsigned BlendMask = 0;
7255 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7256 if (Mask[i] >= Size) {
7257 if (Mask[i] != i + Size)
7258 return SDValue(); // Shuffled V2 input!
7259 BlendMask |= 1u << i;
7262 if (Mask[i] >= 0 && Mask[i] != i)
7263 return SDValue(); // Shuffled V1 input!
7265 switch (VT.SimpleTy) {
7270 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7271 DAG.getConstant(BlendMask, MVT::i8));
7275 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7279 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7280 // that instruction.
7281 if (Subtarget->hasAVX2()) {
7282 // Scale the blend by the number of 32-bit dwords per element.
7283 int Scale = VT.getScalarSizeInBits() / 32;
7285 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7286 if (Mask[i] >= Size)
7287 for (int j = 0; j < Scale; ++j)
7288 BlendMask |= 1u << (i * Scale + j);
7290 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7291 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7292 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7293 return DAG.getNode(ISD::BITCAST, DL, VT,
7294 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7295 DAG.getConstant(BlendMask, MVT::i8)));
7299 // For integer shuffles we need to expand the mask and cast the inputs to
7300 // v8i16s prior to blending.
7301 int Scale = 8 / VT.getVectorNumElements();
7303 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7304 if (Mask[i] >= Size)
7305 for (int j = 0; j < Scale; ++j)
7306 BlendMask |= 1u << (i * Scale + j);
7308 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7309 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7310 return DAG.getNode(ISD::BITCAST, DL, VT,
7311 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7312 DAG.getConstant(BlendMask, MVT::i8)));
7316 llvm_unreachable("Not a supported integer vector type!");
7320 /// \brief Try to lower a vector shuffle as a byte rotation.
7322 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7323 /// byte-rotation of a the concatentation of two vectors. This routine will
7324 /// try to generically lower a vector shuffle through such an instruction. It
7325 /// does not check for the availability of PALIGNR-based lowerings, only the
7326 /// applicability of this strategy to the given mask. This matches shuffle
7327 /// vectors that look like:
7329 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7331 /// Essentially it concatenates V1 and V2, shifts right by some number of
7332 /// elements, and takes the low elements as the result. Note that while this is
7333 /// specified as a *right shift* because x86 is little-endian, it is a *left
7334 /// rotate* of the vector lanes.
7336 /// Note that this only handles 128-bit vector widths currently.
7337 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7340 SelectionDAG &DAG) {
7341 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7343 // We need to detect various ways of spelling a rotation:
7344 // [11, 12, 13, 14, 15, 0, 1, 2]
7345 // [-1, 12, 13, 14, -1, -1, 1, -1]
7346 // [-1, -1, -1, -1, -1, -1, 1, 2]
7347 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7348 // [-1, 4, 5, 6, -1, -1, 9, -1]
7349 // [-1, 4, 5, 6, -1, -1, -1, -1]
7352 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7355 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7357 // Based on the mod-Size value of this mask element determine where
7358 // a rotated vector would have started.
7359 int StartIdx = i - (Mask[i] % Size);
7361 // The identity rotation isn't interesting, stop.
7364 // If we found the tail of a vector the rotation must be the missing
7365 // front. If we found the head of a vector, it must be how much of the head.
7366 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7369 Rotation = CandidateRotation;
7370 else if (Rotation != CandidateRotation)
7371 // The rotations don't match, so we can't match this mask.
7374 // Compute which value this mask is pointing at.
7375 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7377 // Compute which of the two target values this index should be assigned to.
7378 // This reflects whether the high elements are remaining or the low elements
7380 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7382 // Either set up this value if we've not encountered it before, or check
7383 // that it remains consistent.
7386 else if (TargetV != MaskV)
7387 // This may be a rotation, but it pulls from the inputs in some
7388 // unsupported interleaving.
7392 // Check that we successfully analyzed the mask, and normalize the results.
7393 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7394 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7400 // Cast the inputs to v16i8 to match PALIGNR.
7401 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7402 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7404 assert(VT.getSizeInBits() == 128 &&
7405 "Rotate-based lowering only supports 128-bit lowering!");
7406 assert(Mask.size() <= 16 &&
7407 "Can shuffle at most 16 bytes in a 128-bit vector!");
7408 // The actual rotate instruction rotates bytes, so we need to scale the
7409 // rotation based on how many bytes are in the vector.
7410 int Scale = 16 / Mask.size();
7412 return DAG.getNode(ISD::BITCAST, DL, VT,
7413 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7414 DAG.getConstant(Rotation * Scale, MVT::i8)));
7417 /// \brief Compute whether each element of a shuffle is zeroable.
7419 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7420 /// Either it is an undef element in the shuffle mask, the element of the input
7421 /// referenced is undef, or the element of the input referenced is known to be
7422 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7423 /// as many lanes with this technique as possible to simplify the remaining
7425 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7426 SDValue V1, SDValue V2) {
7427 SmallBitVector Zeroable(Mask.size(), false);
7429 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7430 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7432 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7434 // Handle the easy cases.
7435 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7440 // If this is an index into a build_vector node, dig out the input value and
7442 SDValue V = M < Size ? V1 : V2;
7443 if (V.getOpcode() != ISD::BUILD_VECTOR)
7446 SDValue Input = V.getOperand(M % Size);
7447 // The UNDEF opcode check really should be dead code here, but not quite
7448 // worth asserting on (it isn't invalid, just unexpected).
7449 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7456 /// \brief Lower a vector shuffle as a zero or any extension.
7458 /// Given a specific number of elements, element bit width, and extension
7459 /// stride, produce either a zero or any extension based on the available
7460 /// features of the subtarget.
7461 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7462 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7463 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7464 assert(Scale > 1 && "Need a scale to extend.");
7465 int EltBits = VT.getSizeInBits() / NumElements;
7466 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7467 "Only 8, 16, and 32 bit elements can be extended.");
7468 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7470 // Found a valid zext mask! Try various lowering strategies based on the
7471 // input type and available ISA extensions.
7472 if (Subtarget->hasSSE41()) {
7473 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7474 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7475 NumElements / Scale);
7476 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7477 return DAG.getNode(ISD::BITCAST, DL, VT,
7478 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7481 // For any extends we can cheat for larger element sizes and use shuffle
7482 // instructions that can fold with a load and/or copy.
7483 if (AnyExt && EltBits == 32) {
7484 int PSHUFDMask[4] = {0, -1, 1, -1};
7486 ISD::BITCAST, DL, VT,
7487 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7488 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7489 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7491 if (AnyExt && EltBits == 16 && Scale > 2) {
7492 int PSHUFDMask[4] = {0, -1, 0, -1};
7493 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7494 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7495 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7496 int PSHUFHWMask[4] = {1, -1, -1, -1};
7498 ISD::BITCAST, DL, VT,
7499 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7500 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7501 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7504 // If this would require more than 2 unpack instructions to expand, use
7505 // pshufb when available. We can only use more than 2 unpack instructions
7506 // when zero extending i8 elements which also makes it easier to use pshufb.
7507 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7508 assert(NumElements == 16 && "Unexpected byte vector width!");
7509 SDValue PSHUFBMask[16];
7510 for (int i = 0; i < 16; ++i)
7512 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7513 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7514 return DAG.getNode(ISD::BITCAST, DL, VT,
7515 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7516 DAG.getNode(ISD::BUILD_VECTOR, DL,
7517 MVT::v16i8, PSHUFBMask)));
7520 // Otherwise emit a sequence of unpacks.
7522 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7523 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7524 : getZeroVector(InputVT, Subtarget, DAG, DL);
7525 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7526 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7530 } while (Scale > 1);
7531 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7534 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7536 /// This routine will try to do everything in its power to cleverly lower
7537 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7538 /// check for the profitability of this lowering, it tries to aggressively
7539 /// match this pattern. It will use all of the micro-architectural details it
7540 /// can to emit an efficient lowering. It handles both blends with all-zero
7541 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7542 /// masking out later).
7544 /// The reason we have dedicated lowering for zext-style shuffles is that they
7545 /// are both incredibly common and often quite performance sensitive.
7546 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7547 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7548 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7549 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7551 int Bits = VT.getSizeInBits();
7552 int NumElements = Mask.size();
7554 // Define a helper function to check a particular ext-scale and lower to it if
7556 auto Lower = [&](int Scale) -> SDValue {
7559 for (int i = 0; i < NumElements; ++i) {
7561 continue; // Valid anywhere but doesn't tell us anything.
7562 if (i % Scale != 0) {
7563 // Each of the extend elements needs to be zeroable.
7567 // We no lorger are in the anyext case.
7572 // Each of the base elements needs to be consecutive indices into the
7573 // same input vector.
7574 SDValue V = Mask[i] < NumElements ? V1 : V2;
7577 else if (InputV != V)
7578 return SDValue(); // Flip-flopping inputs.
7580 if (Mask[i] % NumElements != i / Scale)
7581 return SDValue(); // Non-consecutive strided elemenst.
7584 // If we fail to find an input, we have a zero-shuffle which should always
7585 // have already been handled.
7586 // FIXME: Maybe handle this here in case during blending we end up with one?
7590 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7594 // The widest scale possible for extending is to a 64-bit integer.
7595 assert(Bits % 64 == 0 &&
7596 "The number of bits in a vector must be divisible by 64 on x86!");
7597 int NumExtElements = Bits / 64;
7599 // Each iteration, try extending the elements half as much, but into twice as
7601 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7602 assert(NumElements % NumExtElements == 0 &&
7603 "The input vector size must be divisble by the extended size.");
7604 if (SDValue V = Lower(NumElements / NumExtElements))
7608 // No viable ext lowering found.
7612 /// \brief Try to lower insertion of a single element into a zero vector.
7614 /// This is a common pattern that we have especially efficient patterns to lower
7615 /// across all subtarget feature sets.
7616 static SDValue lowerVectorShuffleAsElementInsertion(
7617 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7618 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7619 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7621 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7622 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7624 if (Mask.size() == 2) {
7625 if (!Zeroable[V2Index ^ 1]) {
7626 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7627 // with 2 to flip from {2,3} to {0,1} and vice versa.
7628 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7629 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7630 if (Zeroable[V2Index])
7631 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7637 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7638 if (i != V2Index && !Zeroable[i])
7639 return SDValue(); // Not inserting into a zero vector.
7642 // Step over any bitcasts on either input so we can scan the actual
7643 // BUILD_VECTOR nodes.
7644 while (V1.getOpcode() == ISD::BITCAST)
7645 V1 = V1.getOperand(0);
7646 while (V2.getOpcode() == ISD::BITCAST)
7647 V2 = V2.getOperand(0);
7649 // Check for a single input from a SCALAR_TO_VECTOR node.
7650 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7651 // all the smarts here sunk into that routine. However, the current
7652 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7653 // vector shuffle lowering is dead.
7654 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7655 Mask[V2Index] == (int)Mask.size()) ||
7656 V2.getOpcode() == ISD::BUILD_VECTOR))
7659 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7661 // First, we need to zext the scalar if it is smaller than an i32.
7663 MVT EltVT = VT.getVectorElementType();
7664 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7665 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7666 // Zero-extend directly to i32.
7668 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7671 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7672 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7674 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7677 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7678 // the desired position. Otherwise it is more efficient to do a vector
7679 // shift left. We know that we can do a vector shift left because all
7680 // the inputs are zero.
7681 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7682 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7683 V2Shuffle[V2Index] = 0;
7684 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7686 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7688 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7690 V2Index * EltVT.getSizeInBits(),
7691 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7692 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7698 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7700 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7701 /// support for floating point shuffles but not integer shuffles. These
7702 /// instructions will incur a domain crossing penalty on some chips though so
7703 /// it is better to avoid lowering through this for integer vectors where
7705 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7706 const X86Subtarget *Subtarget,
7707 SelectionDAG &DAG) {
7709 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7710 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7711 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7713 ArrayRef<int> Mask = SVOp->getMask();
7714 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7716 if (isSingleInputShuffleMask(Mask)) {
7717 // Straight shuffle of a single input vector. Simulate this by using the
7718 // single input as both of the "inputs" to this instruction..
7719 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7721 if (Subtarget->hasAVX()) {
7722 // If we have AVX, we can use VPERMILPS which will allow folding a load
7723 // into the shuffle.
7724 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7725 DAG.getConstant(SHUFPDMask, MVT::i8));
7728 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7729 DAG.getConstant(SHUFPDMask, MVT::i8));
7731 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7732 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7734 // Use dedicated unpack instructions for masks that match their pattern.
7735 if (isShuffleEquivalent(Mask, 0, 2))
7736 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7737 if (isShuffleEquivalent(Mask, 1, 3))
7738 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7740 // If we have a single input, insert that into V1 if we can do so cheaply.
7741 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7742 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7743 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7746 if (Subtarget->hasSSE41())
7747 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7751 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7752 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7753 DAG.getConstant(SHUFPDMask, MVT::i8));
7756 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7758 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7759 /// the integer unit to minimize domain crossing penalties. However, for blends
7760 /// it falls back to the floating point shuffle operation with appropriate bit
7762 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7763 const X86Subtarget *Subtarget,
7764 SelectionDAG &DAG) {
7766 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7767 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7768 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7770 ArrayRef<int> Mask = SVOp->getMask();
7771 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7773 if (isSingleInputShuffleMask(Mask)) {
7774 // Straight shuffle of a single input vector. For everything from SSE2
7775 // onward this has a single fast instruction with no scary immediates.
7776 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7777 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7778 int WidenedMask[4] = {
7779 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7780 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7782 ISD::BITCAST, DL, MVT::v2i64,
7783 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7784 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7787 // Use dedicated unpack instructions for masks that match their pattern.
7788 if (isShuffleEquivalent(Mask, 0, 2))
7789 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7790 if (isShuffleEquivalent(Mask, 1, 3))
7791 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7793 // If we have a single input from V2 insert that into V1 if we can do so
7795 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7796 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7797 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7800 if (Subtarget->hasSSE41())
7801 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7805 // Try to use rotation instructions if available.
7806 if (Subtarget->hasSSSE3())
7807 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7808 DL, MVT::v2i64, V1, V2, Mask, DAG))
7811 // We implement this with SHUFPD which is pretty lame because it will likely
7812 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7813 // However, all the alternatives are still more cycles and newer chips don't
7814 // have this problem. It would be really nice if x86 had better shuffles here.
7815 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7816 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7817 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7818 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7821 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7823 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7824 /// It makes no assumptions about whether this is the *best* lowering, it simply
7826 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7827 ArrayRef<int> Mask, SDValue V1,
7828 SDValue V2, SelectionDAG &DAG) {
7829 SDValue LowV = V1, HighV = V2;
7830 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7833 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7835 if (NumV2Elements == 1) {
7837 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7840 // Compute the index adjacent to V2Index and in the same half by toggling
7842 int V2AdjIndex = V2Index ^ 1;
7844 if (Mask[V2AdjIndex] == -1) {
7845 // Handles all the cases where we have a single V2 element and an undef.
7846 // This will only ever happen in the high lanes because we commute the
7847 // vector otherwise.
7849 std::swap(LowV, HighV);
7850 NewMask[V2Index] -= 4;
7852 // Handle the case where the V2 element ends up adjacent to a V1 element.
7853 // To make this work, blend them together as the first step.
7854 int V1Index = V2AdjIndex;
7855 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7856 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7857 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7859 // Now proceed to reconstruct the final blend as we have the necessary
7860 // high or low half formed.
7867 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7868 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7870 } else if (NumV2Elements == 2) {
7871 if (Mask[0] < 4 && Mask[1] < 4) {
7872 // Handle the easy case where we have V1 in the low lanes and V2 in the
7873 // high lanes. We never see this reversed because we sort the shuffle.
7877 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7878 // trying to place elements directly, just blend them and set up the final
7879 // shuffle to place them.
7881 // The first two blend mask elements are for V1, the second two are for
7883 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7884 Mask[2] < 4 ? Mask[2] : Mask[3],
7885 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7886 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7887 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7888 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7890 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7893 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7894 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7895 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7896 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7899 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7900 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7903 /// \brief Lower 4-lane 32-bit floating point shuffles.
7905 /// Uses instructions exclusively from the floating point unit to minimize
7906 /// domain crossing penalties, as these are sufficient to implement all v4f32
7908 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7909 const X86Subtarget *Subtarget,
7910 SelectionDAG &DAG) {
7912 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7913 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7914 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7915 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7916 ArrayRef<int> Mask = SVOp->getMask();
7917 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7920 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7922 if (NumV2Elements == 0) {
7923 if (Subtarget->hasAVX()) {
7924 // If we have AVX, we can use VPERMILPS which will allow folding a load
7925 // into the shuffle.
7926 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7927 getV4X86ShuffleImm8ForMask(Mask, DAG));
7930 // Otherwise, use a straight shuffle of a single input vector. We pass the
7931 // input vector to both operands to simulate this with a SHUFPS.
7932 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7933 getV4X86ShuffleImm8ForMask(Mask, DAG));
7936 // Use dedicated unpack instructions for masks that match their pattern.
7937 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7938 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7939 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7940 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7942 // There are special ways we can lower some single-element blends. However, we
7943 // have custom ways we can lower more complex single-element blends below that
7944 // we defer to if both this and BLENDPS fail to match, so restrict this to
7945 // when the V2 input is targeting element 0 of the mask -- that is the fast
7947 if (NumV2Elements == 1 && Mask[0] >= 4)
7948 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7949 Mask, Subtarget, DAG))
7952 if (Subtarget->hasSSE41())
7953 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7957 // Check for whether we can use INSERTPS to perform the blend. We only use
7958 // INSERTPS when the V1 elements are already in the correct locations
7959 // because otherwise we can just always use two SHUFPS instructions which
7960 // are much smaller to encode than a SHUFPS and an INSERTPS.
7961 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7963 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7966 // When using INSERTPS we can zero any lane of the destination. Collect
7967 // the zero inputs into a mask and drop them from the lanes of V1 which
7968 // actually need to be present as inputs to the INSERTPS.
7969 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7971 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7972 bool InsertNeedsShuffle = false;
7974 for (int i = 0; i < 4; ++i)
7978 } else if (Mask[i] != i) {
7979 InsertNeedsShuffle = true;
7984 // We don't want to use INSERTPS or other insertion techniques if it will
7985 // require shuffling anyways.
7986 if (!InsertNeedsShuffle) {
7987 // If all of V1 is zeroable, replace it with undef.
7988 if ((ZMask | 1 << V2Index) == 0xF)
7989 V1 = DAG.getUNDEF(MVT::v4f32);
7991 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7992 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7994 // Insert the V2 element into the desired position.
7995 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7996 DAG.getConstant(InsertPSMask, MVT::i8));
8000 // Otherwise fall back to a SHUFPS lowering strategy.
8001 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8004 /// \brief Lower 4-lane i32 vector shuffles.
8006 /// We try to handle these with integer-domain shuffles where we can, but for
8007 /// blends we use the floating point domain blend instructions.
8008 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8009 const X86Subtarget *Subtarget,
8010 SelectionDAG &DAG) {
8012 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8013 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8014 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8015 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8016 ArrayRef<int> Mask = SVOp->getMask();
8017 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8020 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8022 if (NumV2Elements == 0) {
8023 // Straight shuffle of a single input vector. For everything from SSE2
8024 // onward this has a single fast instruction with no scary immediates.
8025 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8026 // but we aren't actually going to use the UNPCK instruction because doing
8027 // so prevents folding a load into this instruction or making a copy.
8028 const int UnpackLoMask[] = {0, 0, 1, 1};
8029 const int UnpackHiMask[] = {2, 2, 3, 3};
8030 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8031 Mask = UnpackLoMask;
8032 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8033 Mask = UnpackHiMask;
8035 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8036 getV4X86ShuffleImm8ForMask(Mask, DAG));
8039 // Whenever we can lower this as a zext, that instruction is strictly faster
8040 // than any alternative.
8041 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8042 Mask, Subtarget, DAG))
8045 // Use dedicated unpack instructions for masks that match their pattern.
8046 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8047 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8048 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8049 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8051 // There are special ways we can lower some single-element blends.
8052 if (NumV2Elements == 1)
8053 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8054 Mask, Subtarget, DAG))
8057 if (Subtarget->hasSSE41())
8058 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8062 // Try to use rotation instructions if available.
8063 if (Subtarget->hasSSSE3())
8064 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8065 DL, MVT::v4i32, V1, V2, Mask, DAG))
8068 // We implement this with SHUFPS because it can blend from two vectors.
8069 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8070 // up the inputs, bypassing domain shift penalties that we would encur if we
8071 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8073 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8074 DAG.getVectorShuffle(
8076 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8077 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8080 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8081 /// shuffle lowering, and the most complex part.
8083 /// The lowering strategy is to try to form pairs of input lanes which are
8084 /// targeted at the same half of the final vector, and then use a dword shuffle
8085 /// to place them onto the right half, and finally unpack the paired lanes into
8086 /// their final position.
8088 /// The exact breakdown of how to form these dword pairs and align them on the
8089 /// correct sides is really tricky. See the comments within the function for
8090 /// more of the details.
8091 static SDValue lowerV8I16SingleInputVectorShuffle(
8092 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8093 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8094 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8095 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8096 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8098 SmallVector<int, 4> LoInputs;
8099 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8100 [](int M) { return M >= 0; });
8101 std::sort(LoInputs.begin(), LoInputs.end());
8102 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8103 SmallVector<int, 4> HiInputs;
8104 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8105 [](int M) { return M >= 0; });
8106 std::sort(HiInputs.begin(), HiInputs.end());
8107 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8109 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8110 int NumHToL = LoInputs.size() - NumLToL;
8112 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8113 int NumHToH = HiInputs.size() - NumLToH;
8114 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8115 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8116 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8117 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8119 // Use dedicated unpack instructions for masks that match their pattern.
8120 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8121 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8122 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8123 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8125 // Try to use rotation instructions if available.
8126 if (Subtarget->hasSSSE3())
8127 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8128 DL, MVT::v8i16, V, V, Mask, DAG))
8131 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8132 // such inputs we can swap two of the dwords across the half mark and end up
8133 // with <=2 inputs to each half in each half. Once there, we can fall through
8134 // to the generic code below. For example:
8136 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8137 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8139 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8140 // and an existing 2-into-2 on the other half. In this case we may have to
8141 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8142 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8143 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8144 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8145 // half than the one we target for fixing) will be fixed when we re-enter this
8146 // path. We will also combine away any sequence of PSHUFD instructions that
8147 // result into a single instruction. Here is an example of the tricky case:
8149 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8150 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8152 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8154 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8155 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8157 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8158 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8160 // The result is fine to be handled by the generic logic.
8161 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8162 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8163 int AOffset, int BOffset) {
8164 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8165 "Must call this with A having 3 or 1 inputs from the A half.");
8166 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8167 "Must call this with B having 1 or 3 inputs from the B half.");
8168 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8169 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8171 // Compute the index of dword with only one word among the three inputs in
8172 // a half by taking the sum of the half with three inputs and subtracting
8173 // the sum of the actual three inputs. The difference is the remaining
8176 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8177 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8178 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8179 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8180 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8181 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8182 int TripleNonInputIdx =
8183 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8184 TripleDWord = TripleNonInputIdx / 2;
8186 // We use xor with one to compute the adjacent DWord to whichever one the
8188 OneInputDWord = (OneInput / 2) ^ 1;
8190 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8191 // and BToA inputs. If there is also such a problem with the BToB and AToB
8192 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8193 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8194 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8195 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8196 // Compute how many inputs will be flipped by swapping these DWords. We
8198 // to balance this to ensure we don't form a 3-1 shuffle in the other
8200 int NumFlippedAToBInputs =
8201 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8202 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8203 int NumFlippedBToBInputs =
8204 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8205 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8206 if ((NumFlippedAToBInputs == 1 &&
8207 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8208 (NumFlippedBToBInputs == 1 &&
8209 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8210 // We choose whether to fix the A half or B half based on whether that
8211 // half has zero flipped inputs. At zero, we may not be able to fix it
8212 // with that half. We also bias towards fixing the B half because that
8213 // will more commonly be the high half, and we have to bias one way.
8214 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8215 ArrayRef<int> Inputs) {
8216 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8217 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8218 PinnedIdx ^ 1) != Inputs.end();
8219 // Determine whether the free index is in the flipped dword or the
8220 // unflipped dword based on where the pinned index is. We use this bit
8221 // in an xor to conditionally select the adjacent dword.
8222 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8223 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8224 FixFreeIdx) != Inputs.end();
8225 if (IsFixIdxInput == IsFixFreeIdxInput)
8227 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8228 FixFreeIdx) != Inputs.end();
8229 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8230 "We need to be changing the number of flipped inputs!");
8231 int PSHUFHalfMask[] = {0, 1, 2, 3};
8232 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8233 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8235 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8238 if (M != -1 && M == FixIdx)
8240 else if (M != -1 && M == FixFreeIdx)
8243 if (NumFlippedBToBInputs != 0) {
8245 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8246 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8248 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8250 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8251 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8256 int PSHUFDMask[] = {0, 1, 2, 3};
8257 PSHUFDMask[ADWord] = BDWord;
8258 PSHUFDMask[BDWord] = ADWord;
8259 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8260 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8261 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8262 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8264 // Adjust the mask to match the new locations of A and B.
8266 if (M != -1 && M/2 == ADWord)
8267 M = 2 * BDWord + M % 2;
8268 else if (M != -1 && M/2 == BDWord)
8269 M = 2 * ADWord + M % 2;
8271 // Recurse back into this routine to re-compute state now that this isn't
8272 // a 3 and 1 problem.
8273 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8276 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8277 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8278 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8279 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8281 // At this point there are at most two inputs to the low and high halves from
8282 // each half. That means the inputs can always be grouped into dwords and
8283 // those dwords can then be moved to the correct half with a dword shuffle.
8284 // We use at most one low and one high word shuffle to collect these paired
8285 // inputs into dwords, and finally a dword shuffle to place them.
8286 int PSHUFLMask[4] = {-1, -1, -1, -1};
8287 int PSHUFHMask[4] = {-1, -1, -1, -1};
8288 int PSHUFDMask[4] = {-1, -1, -1, -1};
8290 // First fix the masks for all the inputs that are staying in their
8291 // original halves. This will then dictate the targets of the cross-half
8293 auto fixInPlaceInputs =
8294 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8295 MutableArrayRef<int> SourceHalfMask,
8296 MutableArrayRef<int> HalfMask, int HalfOffset) {
8297 if (InPlaceInputs.empty())
8299 if (InPlaceInputs.size() == 1) {
8300 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8301 InPlaceInputs[0] - HalfOffset;
8302 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8305 if (IncomingInputs.empty()) {
8306 // Just fix all of the in place inputs.
8307 for (int Input : InPlaceInputs) {
8308 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8309 PSHUFDMask[Input / 2] = Input / 2;
8314 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8315 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8316 InPlaceInputs[0] - HalfOffset;
8317 // Put the second input next to the first so that they are packed into
8318 // a dword. We find the adjacent index by toggling the low bit.
8319 int AdjIndex = InPlaceInputs[0] ^ 1;
8320 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8321 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8322 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8324 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8325 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8327 // Now gather the cross-half inputs and place them into a free dword of
8328 // their target half.
8329 // FIXME: This operation could almost certainly be simplified dramatically to
8330 // look more like the 3-1 fixing operation.
8331 auto moveInputsToRightHalf = [&PSHUFDMask](
8332 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8333 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8334 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8336 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8337 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8339 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8341 int LowWord = Word & ~1;
8342 int HighWord = Word | 1;
8343 return isWordClobbered(SourceHalfMask, LowWord) ||
8344 isWordClobbered(SourceHalfMask, HighWord);
8347 if (IncomingInputs.empty())
8350 if (ExistingInputs.empty()) {
8351 // Map any dwords with inputs from them into the right half.
8352 for (int Input : IncomingInputs) {
8353 // If the source half mask maps over the inputs, turn those into
8354 // swaps and use the swapped lane.
8355 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8356 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8357 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8358 Input - SourceOffset;
8359 // We have to swap the uses in our half mask in one sweep.
8360 for (int &M : HalfMask)
8361 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8363 else if (M == Input)
8364 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8366 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8367 Input - SourceOffset &&
8368 "Previous placement doesn't match!");
8370 // Note that this correctly re-maps both when we do a swap and when
8371 // we observe the other side of the swap above. We rely on that to
8372 // avoid swapping the members of the input list directly.
8373 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8376 // Map the input's dword into the correct half.
8377 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8378 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8380 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8382 "Previous placement doesn't match!");
8385 // And just directly shift any other-half mask elements to be same-half
8386 // as we will have mirrored the dword containing the element into the
8387 // same position within that half.
8388 for (int &M : HalfMask)
8389 if (M >= SourceOffset && M < SourceOffset + 4) {
8390 M = M - SourceOffset + DestOffset;
8391 assert(M >= 0 && "This should never wrap below zero!");
8396 // Ensure we have the input in a viable dword of its current half. This
8397 // is particularly tricky because the original position may be clobbered
8398 // by inputs being moved and *staying* in that half.
8399 if (IncomingInputs.size() == 1) {
8400 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8401 int InputFixed = std::find(std::begin(SourceHalfMask),
8402 std::end(SourceHalfMask), -1) -
8403 std::begin(SourceHalfMask) + SourceOffset;
8404 SourceHalfMask[InputFixed - SourceOffset] =
8405 IncomingInputs[0] - SourceOffset;
8406 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8408 IncomingInputs[0] = InputFixed;
8410 } else if (IncomingInputs.size() == 2) {
8411 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8412 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8413 // We have two non-adjacent or clobbered inputs we need to extract from
8414 // the source half. To do this, we need to map them into some adjacent
8415 // dword slot in the source mask.
8416 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8417 IncomingInputs[1] - SourceOffset};
8419 // If there is a free slot in the source half mask adjacent to one of
8420 // the inputs, place the other input in it. We use (Index XOR 1) to
8421 // compute an adjacent index.
8422 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8423 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8424 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8425 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8426 InputsFixed[1] = InputsFixed[0] ^ 1;
8427 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8428 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8429 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8430 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8431 InputsFixed[0] = InputsFixed[1] ^ 1;
8432 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8433 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8434 // The two inputs are in the same DWord but it is clobbered and the
8435 // adjacent DWord isn't used at all. Move both inputs to the free
8437 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8438 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8439 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8440 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8442 // The only way we hit this point is if there is no clobbering
8443 // (because there are no off-half inputs to this half) and there is no
8444 // free slot adjacent to one of the inputs. In this case, we have to
8445 // swap an input with a non-input.
8446 for (int i = 0; i < 4; ++i)
8447 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8448 "We can't handle any clobbers here!");
8449 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8450 "Cannot have adjacent inputs here!");
8452 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8453 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8455 // We also have to update the final source mask in this case because
8456 // it may need to undo the above swap.
8457 for (int &M : FinalSourceHalfMask)
8458 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8459 M = InputsFixed[1] + SourceOffset;
8460 else if (M == InputsFixed[1] + SourceOffset)
8461 M = (InputsFixed[0] ^ 1) + SourceOffset;
8463 InputsFixed[1] = InputsFixed[0] ^ 1;
8466 // Point everything at the fixed inputs.
8467 for (int &M : HalfMask)
8468 if (M == IncomingInputs[0])
8469 M = InputsFixed[0] + SourceOffset;
8470 else if (M == IncomingInputs[1])
8471 M = InputsFixed[1] + SourceOffset;
8473 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8474 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8477 llvm_unreachable("Unhandled input size!");
8480 // Now hoist the DWord down to the right half.
8481 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8482 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8483 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8484 for (int &M : HalfMask)
8485 for (int Input : IncomingInputs)
8487 M = FreeDWord * 2 + Input % 2;
8489 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8490 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8491 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8492 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8494 // Now enact all the shuffles we've computed to move the inputs into their
8496 if (!isNoopShuffleMask(PSHUFLMask))
8497 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8498 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8499 if (!isNoopShuffleMask(PSHUFHMask))
8500 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8501 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8502 if (!isNoopShuffleMask(PSHUFDMask))
8503 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8504 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8505 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8506 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8508 // At this point, each half should contain all its inputs, and we can then
8509 // just shuffle them into their final position.
8510 assert(std::count_if(LoMask.begin(), LoMask.end(),
8511 [](int M) { return M >= 4; }) == 0 &&
8512 "Failed to lift all the high half inputs to the low mask!");
8513 assert(std::count_if(HiMask.begin(), HiMask.end(),
8514 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8515 "Failed to lift all the low half inputs to the high mask!");
8517 // Do a half shuffle for the low mask.
8518 if (!isNoopShuffleMask(LoMask))
8519 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8520 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8522 // Do a half shuffle with the high mask after shifting its values down.
8523 for (int &M : HiMask)
8526 if (!isNoopShuffleMask(HiMask))
8527 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8528 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8533 /// \brief Detect whether the mask pattern should be lowered through
8536 /// This essentially tests whether viewing the mask as an interleaving of two
8537 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8538 /// lowering it through interleaving is a significantly better strategy.
8539 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8540 int NumEvenInputs[2] = {0, 0};
8541 int NumOddInputs[2] = {0, 0};
8542 int NumLoInputs[2] = {0, 0};
8543 int NumHiInputs[2] = {0, 0};
8544 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8548 int InputIdx = Mask[i] >= Size;
8551 ++NumLoInputs[InputIdx];
8553 ++NumHiInputs[InputIdx];
8556 ++NumEvenInputs[InputIdx];
8558 ++NumOddInputs[InputIdx];
8561 // The minimum number of cross-input results for both the interleaved and
8562 // split cases. If interleaving results in fewer cross-input results, return
8564 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8565 NumEvenInputs[0] + NumOddInputs[1]);
8566 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8567 NumLoInputs[0] + NumHiInputs[1]);
8568 return InterleavedCrosses < SplitCrosses;
8571 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8573 /// This strategy only works when the inputs from each vector fit into a single
8574 /// half of that vector, and generally there are not so many inputs as to leave
8575 /// the in-place shuffles required highly constrained (and thus expensive). It
8576 /// shifts all the inputs into a single side of both input vectors and then
8577 /// uses an unpack to interleave these inputs in a single vector. At that
8578 /// point, we will fall back on the generic single input shuffle lowering.
8579 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8581 MutableArrayRef<int> Mask,
8582 const X86Subtarget *Subtarget,
8583 SelectionDAG &DAG) {
8584 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8585 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8586 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8587 for (int i = 0; i < 8; ++i)
8588 if (Mask[i] >= 0 && Mask[i] < 4)
8589 LoV1Inputs.push_back(i);
8590 else if (Mask[i] >= 4 && Mask[i] < 8)
8591 HiV1Inputs.push_back(i);
8592 else if (Mask[i] >= 8 && Mask[i] < 12)
8593 LoV2Inputs.push_back(i);
8594 else if (Mask[i] >= 12)
8595 HiV2Inputs.push_back(i);
8597 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8598 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8601 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8602 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8603 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8605 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8606 HiV1Inputs.size() + HiV2Inputs.size();
8608 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8609 ArrayRef<int> HiInputs, bool MoveToLo,
8611 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8612 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8613 if (BadInputs.empty())
8616 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8617 int MoveOffset = MoveToLo ? 0 : 4;
8619 if (GoodInputs.empty()) {
8620 for (int BadInput : BadInputs) {
8621 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8622 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8625 if (GoodInputs.size() == 2) {
8626 // If the low inputs are spread across two dwords, pack them into
8628 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8629 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8630 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8631 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8633 // Otherwise pin the good inputs.
8634 for (int GoodInput : GoodInputs)
8635 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8638 if (BadInputs.size() == 2) {
8639 // If we have two bad inputs then there may be either one or two good
8640 // inputs fixed in place. Find a fixed input, and then find the *other*
8641 // two adjacent indices by using modular arithmetic.
8643 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8644 [](int M) { return M >= 0; }) -
8645 std::begin(MoveMask);
8647 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8648 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8649 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8650 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8651 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8652 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8653 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8655 assert(BadInputs.size() == 1 && "All sizes handled");
8656 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8657 std::end(MoveMask), -1) -
8658 std::begin(MoveMask);
8659 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8660 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8664 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8667 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8669 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8672 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8673 // cross-half traffic in the final shuffle.
8675 // Munge the mask to be a single-input mask after the unpack merges the
8679 M = 2 * (M % 4) + (M / 8);
8681 return DAG.getVectorShuffle(
8682 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8683 DL, MVT::v8i16, V1, V2),
8684 DAG.getUNDEF(MVT::v8i16), Mask);
8687 /// \brief Generic lowering of 8-lane i16 shuffles.
8689 /// This handles both single-input shuffles and combined shuffle/blends with
8690 /// two inputs. The single input shuffles are immediately delegated to
8691 /// a dedicated lowering routine.
8693 /// The blends are lowered in one of three fundamental ways. If there are few
8694 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8695 /// of the input is significantly cheaper when lowered as an interleaving of
8696 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8697 /// halves of the inputs separately (making them have relatively few inputs)
8698 /// and then concatenate them.
8699 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8700 const X86Subtarget *Subtarget,
8701 SelectionDAG &DAG) {
8703 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8704 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8705 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8707 ArrayRef<int> OrigMask = SVOp->getMask();
8708 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8709 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8710 MutableArrayRef<int> Mask(MaskStorage);
8712 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8714 // Whenever we can lower this as a zext, that instruction is strictly faster
8715 // than any alternative.
8716 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8717 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8720 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8721 auto isV2 = [](int M) { return M >= 8; };
8723 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8724 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8726 if (NumV2Inputs == 0)
8727 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8729 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8730 "to be V1-input shuffles.");
8732 // There are special ways we can lower some single-element blends.
8733 if (NumV2Inputs == 1)
8734 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8735 Mask, Subtarget, DAG))
8738 if (Subtarget->hasSSE41())
8739 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8743 // Try to use rotation instructions if available.
8744 if (Subtarget->hasSSSE3())
8745 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8748 if (NumV1Inputs + NumV2Inputs <= 4)
8749 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8751 // Check whether an interleaving lowering is likely to be more efficient.
8752 // This isn't perfect but it is a strong heuristic that tends to work well on
8753 // the kinds of shuffles that show up in practice.
8755 // FIXME: Handle 1x, 2x, and 4x interleaving.
8756 if (shouldLowerAsInterleaving(Mask)) {
8757 // FIXME: Figure out whether we should pack these into the low or high
8760 int EMask[8], OMask[8];
8761 for (int i = 0; i < 4; ++i) {
8762 EMask[i] = Mask[2*i];
8763 OMask[i] = Mask[2*i + 1];
8768 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8769 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8771 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8774 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8775 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8777 for (int i = 0; i < 4; ++i) {
8778 LoBlendMask[i] = Mask[i];
8779 HiBlendMask[i] = Mask[i + 4];
8782 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8783 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8784 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8785 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8787 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8788 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8791 /// \brief Check whether a compaction lowering can be done by dropping even
8792 /// elements and compute how many times even elements must be dropped.
8794 /// This handles shuffles which take every Nth element where N is a power of
8795 /// two. Example shuffle masks:
8797 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8798 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8799 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8800 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8801 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8802 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8804 /// Any of these lanes can of course be undef.
8806 /// This routine only supports N <= 3.
8807 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8810 /// \returns N above, or the number of times even elements must be dropped if
8811 /// there is such a number. Otherwise returns zero.
8812 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8813 // Figure out whether we're looping over two inputs or just one.
8814 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8816 // The modulus for the shuffle vector entries is based on whether this is
8817 // a single input or not.
8818 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8819 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8820 "We should only be called with masks with a power-of-2 size!");
8822 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8824 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8825 // and 2^3 simultaneously. This is because we may have ambiguity with
8826 // partially undef inputs.
8827 bool ViableForN[3] = {true, true, true};
8829 for (int i = 0, e = Mask.size(); i < e; ++i) {
8830 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8835 bool IsAnyViable = false;
8836 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8837 if (ViableForN[j]) {
8840 // The shuffle mask must be equal to (i * 2^N) % M.
8841 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8844 ViableForN[j] = false;
8846 // Early exit if we exhaust the possible powers of two.
8851 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8855 // Return 0 as there is no viable power of two.
8859 /// \brief Generic lowering of v16i8 shuffles.
8861 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8862 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8863 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8864 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8866 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8867 const X86Subtarget *Subtarget,
8868 SelectionDAG &DAG) {
8870 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8871 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8872 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8874 ArrayRef<int> OrigMask = SVOp->getMask();
8875 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8877 // Try to use rotation instructions if available.
8878 if (Subtarget->hasSSSE3())
8879 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8883 // Try to use a zext lowering.
8884 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8885 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8888 int MaskStorage[16] = {
8889 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8890 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8891 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8892 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8893 MutableArrayRef<int> Mask(MaskStorage);
8894 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8895 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8898 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8900 // For single-input shuffles, there are some nicer lowering tricks we can use.
8901 if (NumV2Elements == 0) {
8902 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8903 // Notably, this handles splat and partial-splat shuffles more efficiently.
8904 // However, it only makes sense if the pre-duplication shuffle simplifies
8905 // things significantly. Currently, this means we need to be able to
8906 // express the pre-duplication shuffle as an i16 shuffle.
8908 // FIXME: We should check for other patterns which can be widened into an
8909 // i16 shuffle as well.
8910 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8911 for (int i = 0; i < 16; i += 2)
8912 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8917 auto tryToWidenViaDuplication = [&]() -> SDValue {
8918 if (!canWidenViaDuplication(Mask))
8920 SmallVector<int, 4> LoInputs;
8921 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8922 [](int M) { return M >= 0 && M < 8; });
8923 std::sort(LoInputs.begin(), LoInputs.end());
8924 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8926 SmallVector<int, 4> HiInputs;
8927 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8928 [](int M) { return M >= 8; });
8929 std::sort(HiInputs.begin(), HiInputs.end());
8930 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8933 bool TargetLo = LoInputs.size() >= HiInputs.size();
8934 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8935 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8937 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8938 SmallDenseMap<int, int, 8> LaneMap;
8939 for (int I : InPlaceInputs) {
8940 PreDupI16Shuffle[I/2] = I/2;
8943 int j = TargetLo ? 0 : 4, je = j + 4;
8944 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8945 // Check if j is already a shuffle of this input. This happens when
8946 // there are two adjacent bytes after we move the low one.
8947 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8948 // If we haven't yet mapped the input, search for a slot into which
8950 while (j < je && PreDupI16Shuffle[j] != -1)
8954 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8957 // Map this input with the i16 shuffle.
8958 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8961 // Update the lane map based on the mapping we ended up with.
8962 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8965 ISD::BITCAST, DL, MVT::v16i8,
8966 DAG.getVectorShuffle(MVT::v8i16, DL,
8967 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8968 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8970 // Unpack the bytes to form the i16s that will be shuffled into place.
8971 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8972 MVT::v16i8, V1, V1);
8974 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8975 for (int i = 0; i < 16; i += 2) {
8977 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8978 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8981 ISD::BITCAST, DL, MVT::v16i8,
8982 DAG.getVectorShuffle(MVT::v8i16, DL,
8983 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8984 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8986 if (SDValue V = tryToWidenViaDuplication())
8990 // Check whether an interleaving lowering is likely to be more efficient.
8991 // This isn't perfect but it is a strong heuristic that tends to work well on
8992 // the kinds of shuffles that show up in practice.
8994 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8995 if (shouldLowerAsInterleaving(Mask)) {
8996 // FIXME: Figure out whether we should pack these into the low or high
8999 int EMask[16], OMask[16];
9000 for (int i = 0; i < 8; ++i) {
9001 EMask[i] = Mask[2*i];
9002 OMask[i] = Mask[2*i + 1];
9007 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9008 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9010 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9013 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9014 // with PSHUFB. It is important to do this before we attempt to generate any
9015 // blends but after all of the single-input lowerings. If the single input
9016 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9017 // want to preserve that and we can DAG combine any longer sequences into
9018 // a PSHUFB in the end. But once we start blending from multiple inputs,
9019 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9020 // and there are *very* few patterns that would actually be faster than the
9021 // PSHUFB approach because of its ability to zero lanes.
9023 // FIXME: The only exceptions to the above are blends which are exact
9024 // interleavings with direct instructions supporting them. We currently don't
9025 // handle those well here.
9026 if (Subtarget->hasSSSE3()) {
9029 for (int i = 0; i < 16; ++i)
9030 if (Mask[i] == -1) {
9031 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9033 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9035 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9037 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9038 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9039 if (isSingleInputShuffleMask(Mask))
9040 return V1; // Single inputs are easy.
9042 // Otherwise, blend the two.
9043 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9044 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9045 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9048 // There are special ways we can lower some single-element blends.
9049 if (NumV2Elements == 1)
9050 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9051 Mask, Subtarget, DAG))
9054 // Check whether a compaction lowering can be done. This handles shuffles
9055 // which take every Nth element for some even N. See the helper function for
9058 // We special case these as they can be particularly efficiently handled with
9059 // the PACKUSB instruction on x86 and they show up in common patterns of
9060 // rearranging bytes to truncate wide elements.
9061 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9062 // NumEvenDrops is the power of two stride of the elements. Another way of
9063 // thinking about it is that we need to drop the even elements this many
9064 // times to get the original input.
9065 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9067 // First we need to zero all the dropped bytes.
9068 assert(NumEvenDrops <= 3 &&
9069 "No support for dropping even elements more than 3 times.");
9070 // We use the mask type to pick which bytes are preserved based on how many
9071 // elements are dropped.
9072 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9073 SDValue ByteClearMask =
9074 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9075 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9076 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9078 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9080 // Now pack things back together.
9081 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9082 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9083 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9084 for (int i = 1; i < NumEvenDrops; ++i) {
9085 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9086 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9092 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9093 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9094 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9095 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9097 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9098 MutableArrayRef<int> V1HalfBlendMask,
9099 MutableArrayRef<int> V2HalfBlendMask) {
9100 for (int i = 0; i < 8; ++i)
9101 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9102 V1HalfBlendMask[i] = HalfMask[i];
9104 } else if (HalfMask[i] >= 16) {
9105 V2HalfBlendMask[i] = HalfMask[i] - 16;
9106 HalfMask[i] = i + 8;
9109 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9110 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9112 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9114 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9115 MutableArrayRef<int> HiBlendMask) {
9117 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9118 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9120 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9121 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9122 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9123 [](int M) { return M >= 0 && M % 2 == 1; })) {
9124 // Use a mask to drop the high bytes.
9125 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9126 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9127 DAG.getConstant(0x00FF, MVT::v8i16));
9129 // This will be a single vector shuffle instead of a blend so nuke V2.
9130 V2 = DAG.getUNDEF(MVT::v8i16);
9132 // Squash the masks to point directly into V1.
9133 for (int &M : LoBlendMask)
9136 for (int &M : HiBlendMask)
9140 // Otherwise just unpack the low half of V into V1 and the high half into
9141 // V2 so that we can blend them as i16s.
9142 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9143 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9144 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9145 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9148 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9149 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9150 return std::make_pair(BlendedLo, BlendedHi);
9152 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9153 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9154 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9156 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9157 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9159 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9162 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9164 /// This routine breaks down the specific type of 128-bit shuffle and
9165 /// dispatches to the lowering routines accordingly.
9166 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9167 MVT VT, const X86Subtarget *Subtarget,
9168 SelectionDAG &DAG) {
9169 switch (VT.SimpleTy) {
9171 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9173 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9175 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9177 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9179 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9181 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9184 llvm_unreachable("Unimplemented!");
9188 /// \brief Test whether there are elements crossing 128-bit lanes in this
9191 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9192 /// and we routinely test for these.
9193 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9194 int LaneSize = 128 / VT.getScalarSizeInBits();
9195 int Size = Mask.size();
9196 for (int i = 0; i < Size; ++i)
9197 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9202 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9204 /// This checks a shuffle mask to see if it is performing the same
9205 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9206 /// that it is also not lane-crossing. It may however involve a blend from the
9207 /// same lane of a second vector.
9209 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
9210 /// non-trivial to compute in the face of undef lanes. The representation is
9211 /// *not* suitable for use with existing 128-bit shuffles as it will contain
9212 /// entries from both V1 and V2 inputs to the wider mask.
9214 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
9215 SmallVectorImpl<int> &RepeatedMask) {
9216 int LaneSize = 128 / VT.getScalarSizeInBits();
9217 RepeatedMask.resize(LaneSize, -1);
9218 int Size = Mask.size();
9219 for (int i = 0; i < Size; ++i) {
9222 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
9223 // This entry crosses lanes, so there is no way to model this shuffle.
9226 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
9227 if (RepeatedMask[i % LaneSize] == -1)
9228 // This is the first non-undef entry in this slot of a 128-bit lane.
9229 RepeatedMask[i % LaneSize] =
9230 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
9231 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
9232 // Found a mismatch with the repeated mask.
9238 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9241 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9242 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9243 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9244 /// we encode the logic here for specific shuffle lowering routines to bail to
9245 /// when they exhaust the features avaible to more directly handle the shuffle.
9246 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9248 const X86Subtarget *Subtarget,
9249 SelectionDAG &DAG) {
9251 MVT VT = Op.getSimpleValueType();
9252 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9253 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9254 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9256 ArrayRef<int> Mask = SVOp->getMask();
9258 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9259 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9261 int NumElements = VT.getVectorNumElements();
9262 int SplitNumElements = NumElements / 2;
9263 MVT ScalarVT = VT.getScalarType();
9264 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9266 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9267 DAG.getIntPtrConstant(0));
9268 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9269 DAG.getIntPtrConstant(SplitNumElements));
9270 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9271 DAG.getIntPtrConstant(0));
9272 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9273 DAG.getIntPtrConstant(SplitNumElements));
9275 // Now create two 4-way blends of these half-width vectors.
9276 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9277 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9278 for (int i = 0; i < SplitNumElements; ++i) {
9279 int M = HalfMask[i];
9280 if (M >= NumElements) {
9281 V2BlendMask.push_back(M - NumElements);
9282 V1BlendMask.push_back(-1);
9283 BlendMask.push_back(SplitNumElements + i);
9284 } else if (M >= 0) {
9285 V2BlendMask.push_back(-1);
9286 V1BlendMask.push_back(M);
9287 BlendMask.push_back(i);
9289 V2BlendMask.push_back(-1);
9290 V1BlendMask.push_back(-1);
9291 BlendMask.push_back(-1);
9294 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9295 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9296 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9298 SDValue Lo = HalfBlend(LoMask);
9299 SDValue Hi = HalfBlend(HiMask);
9300 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9303 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9305 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9306 /// isn't available.
9307 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9308 const X86Subtarget *Subtarget,
9309 SelectionDAG &DAG) {
9311 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9312 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9314 ArrayRef<int> Mask = SVOp->getMask();
9315 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9317 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9318 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9320 if (isSingleInputShuffleMask(Mask)) {
9321 // Non-half-crossing single input shuffles can be lowerid with an
9322 // interleaved permutation.
9323 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9324 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9325 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9326 DAG.getConstant(VPERMILPMask, MVT::i8));
9329 // X86 has dedicated unpack instructions that can handle specific blend
9330 // operations: UNPCKH and UNPCKL.
9331 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9332 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9333 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9334 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9336 // If we have a single input to the zero element, insert that into V1 if we
9337 // can do so cheaply.
9339 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9340 if (NumV2Elements == 1 && Mask[0] >= 4)
9341 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9342 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9345 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9349 // Check if the blend happens to exactly fit that of SHUFPD.
9350 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9351 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9352 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9353 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9354 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9355 DAG.getConstant(SHUFPDMask, MVT::i8));
9357 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9358 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9359 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9360 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9361 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9362 DAG.getConstant(SHUFPDMask, MVT::i8));
9365 // Shuffle the input elements into the desired positions in V1 and V2 and
9366 // blend them together.
9367 int V1Mask[] = {-1, -1, -1, -1};
9368 int V2Mask[] = {-1, -1, -1, -1};
9369 for (int i = 0; i < 4; ++i)
9370 if (Mask[i] >= 0 && Mask[i] < 4)
9371 V1Mask[i] = Mask[i];
9372 else if (Mask[i] >= 4)
9373 V2Mask[i] = Mask[i] - 4;
9375 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9376 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9378 unsigned BlendMask = 0;
9379 for (int i = 0; i < 4; ++i)
9381 BlendMask |= 1 << i;
9383 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9384 DAG.getConstant(BlendMask, MVT::i8));
9387 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9389 /// This routine is only called when we have AVX2 and thus a reasonable
9390 /// instruction set for v4i64 shuffling..
9391 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9392 const X86Subtarget *Subtarget,
9393 SelectionDAG &DAG) {
9395 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9396 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9397 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9398 ArrayRef<int> Mask = SVOp->getMask();
9399 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9400 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9402 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9406 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9407 // use lower latency instructions that will operate on both 128-bit lanes.
9408 SmallVector<int, 2> RepeatedMask;
9409 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9410 if (isSingleInputShuffleMask(Mask)) {
9411 int PSHUFDMask[] = {-1, -1, -1, -1};
9412 for (int i = 0; i < 2; ++i)
9413 if (RepeatedMask[i] >= 0) {
9414 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9415 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9418 ISD::BITCAST, DL, MVT::v4i64,
9419 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9420 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9421 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9424 // Use dedicated unpack instructions for masks that match their pattern.
9425 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9426 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9427 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9428 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9431 // AVX2 provides a direct instruction for permuting a single input across
9433 if (isSingleInputShuffleMask(Mask))
9434 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9435 getV4X86ShuffleImm8ForMask(Mask, DAG));
9437 // Shuffle the input elements into the desired positions in V1 and V2 and
9438 // blend them together.
9439 int V1Mask[] = {-1, -1, -1, -1};
9440 int V2Mask[] = {-1, -1, -1, -1};
9441 int BlendMask[] = {-1, -1, -1, -1};
9442 for (int i = 0; i < 4; ++i)
9443 if (Mask[i] >= 0 && Mask[i] < 4) {
9444 V1Mask[i] = Mask[i];
9446 } else if (Mask[i] >= 4) {
9447 V2Mask[i] = Mask[i] - 4;
9448 BlendMask[i] = i + 4;
9451 V1 = DAG.getVectorShuffle(MVT::v4i64, DL, V1, DAG.getUNDEF(MVT::v4i64), V1Mask);
9452 V2 = DAG.getVectorShuffle(MVT::v4i64, DL, V2, DAG.getUNDEF(MVT::v4i64), V2Mask);
9453 return DAG.getVectorShuffle(MVT::v4i64, DL, V1, V2, BlendMask);
9456 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9458 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9459 /// isn't available.
9460 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9461 const X86Subtarget *Subtarget,
9462 SelectionDAG &DAG) {
9464 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9465 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9466 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9467 ArrayRef<int> Mask = SVOp->getMask();
9468 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9470 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9471 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9477 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9478 // options to efficiently lower the shuffle.
9479 SmallVector<int, 2> RepeatedMask;
9480 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9481 if (isSingleInputShuffleMask(Mask))
9482 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9483 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9485 // Use dedicated unpack instructions for masks that match their pattern.
9486 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9487 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9488 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9489 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9491 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9492 // have already handled any direct blends.
9493 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9494 for (int &M : SHUFPSMask)
9497 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9500 // If we have a single input shuffle with different shuffle patterns in the
9501 // two 128-bit lanes use the variable mask to VPERMILPS.
9502 if (isSingleInputShuffleMask(Mask)) {
9503 SDValue VPermMask[8];
9504 for (int i = 0; i < 8; ++i)
9505 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9506 : DAG.getConstant(Mask[i], MVT::i32);
9508 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9509 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9512 // Shuffle the input elements into the desired positions in V1 and V2 and
9513 // blend them together.
9514 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9515 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9516 unsigned BlendMask = 0;
9517 for (int i = 0; i < 8; ++i)
9518 if (Mask[i] >= 0 && Mask[i] < 8) {
9519 V1Mask[i] = Mask[i];
9520 } else if (Mask[i] >= 8) {
9521 V2Mask[i] = Mask[i] - 8;
9522 BlendMask |= 1 << i;
9525 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9526 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9528 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9529 DAG.getConstant(BlendMask, MVT::i8));
9532 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9534 /// This routine is only called when we have AVX2 and thus a reasonable
9535 /// instruction set for v8i32 shuffling..
9536 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9537 const X86Subtarget *Subtarget,
9538 SelectionDAG &DAG) {
9540 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9541 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9543 ArrayRef<int> Mask = SVOp->getMask();
9544 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9545 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9547 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9551 // If the shuffle mask is repeated in each 128-bit lane we can use more
9552 // efficient instructions that mirror the shuffles across the two 128-bit
9554 SmallVector<int, 4> RepeatedMask;
9555 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9556 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9557 if (isSingleInputShuffleMask(Mask))
9558 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9559 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9561 // Use dedicated unpack instructions for masks that match their pattern.
9562 if (isShuffleEquivalent(Mask, 0, 8, 1, 9))
9563 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9564 if (isShuffleEquivalent(Mask, 2, 10, 3, 11))
9565 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9568 // If the shuffle patterns aren't repeated but it is a single input, directly
9569 // generate a cross-lane VPERMD instruction.
9570 if (isSingleInputShuffleMask(Mask)) {
9571 SDValue VPermMask[8];
9572 for (int i = 0; i < 8; ++i)
9573 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9574 : DAG.getConstant(Mask[i], MVT::i32);
9576 X86ISD::VPERMV, DL, MVT::v8i32,
9577 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9580 // Shuffle the input elements into the desired positions in V1 and V2 and
9581 // blend them together.
9582 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9583 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9584 int BlendMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9585 for (int i = 0; i < 8; ++i)
9586 if (Mask[i] >= 0 && Mask[i] < 8) {
9587 V1Mask[i] = Mask[i];
9589 } else if (Mask[i] >= 8) {
9590 V2Mask[i] = Mask[i] - 8;
9591 BlendMask[i] = i + 8;
9594 V1 = DAG.getVectorShuffle(MVT::v8i32, DL, V1, DAG.getUNDEF(MVT::v8i32), V1Mask);
9595 V2 = DAG.getVectorShuffle(MVT::v8i32, DL, V2, DAG.getUNDEF(MVT::v8i32), V2Mask);
9596 return DAG.getVectorShuffle(MVT::v8i32, DL, V1, V2, BlendMask);
9599 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9601 /// This routine is only called when we have AVX2 and thus a reasonable
9602 /// instruction set for v16i16 shuffling..
9603 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9604 const X86Subtarget *Subtarget,
9605 SelectionDAG &DAG) {
9607 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9608 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9610 ArrayRef<int> Mask = SVOp->getMask();
9611 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9612 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9614 // FIXME: Actually implement this using AVX2!!!
9616 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9619 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9621 /// This routine is only called when we have AVX2 and thus a reasonable
9622 /// instruction set for v32i8 shuffling..
9623 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9624 const X86Subtarget *Subtarget,
9625 SelectionDAG &DAG) {
9627 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9628 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9629 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9630 ArrayRef<int> Mask = SVOp->getMask();
9631 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9632 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9634 // FIXME: Actually implement this using AVX2!!!
9636 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9639 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9641 /// This routine either breaks down the specific type of a 256-bit x86 vector
9642 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9643 /// together based on the available instructions.
9644 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9645 MVT VT, const X86Subtarget *Subtarget,
9646 SelectionDAG &DAG) {
9648 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9649 ArrayRef<int> Mask = SVOp->getMask();
9651 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9652 // check for those subtargets here and avoid much of the subtarget querying in
9653 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9654 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9655 // floating point types there eventually, just immediately cast everything to
9656 // a float and operate entirely in that domain.
9657 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9658 int ElementBits = VT.getScalarSizeInBits();
9659 if (ElementBits < 32)
9660 // No floating point type available, decompose into 128-bit vectors.
9661 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9663 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9664 VT.getVectorNumElements());
9665 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9666 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9667 return DAG.getNode(ISD::BITCAST, DL, VT,
9668 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9671 switch (VT.SimpleTy) {
9673 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9675 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9677 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9679 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9683 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9686 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9690 /// \brief Tiny helper function to test whether a shuffle mask could be
9691 /// simplified by widening the elements being shuffled.
9692 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9693 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9694 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9695 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9696 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9702 /// \brief Top-level lowering for x86 vector shuffles.
9704 /// This handles decomposition, canonicalization, and lowering of all x86
9705 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9706 /// above in helper routines. The canonicalization attempts to widen shuffles
9707 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9708 /// s.t. only one of the two inputs needs to be tested, etc.
9709 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9710 SelectionDAG &DAG) {
9711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9712 ArrayRef<int> Mask = SVOp->getMask();
9713 SDValue V1 = Op.getOperand(0);
9714 SDValue V2 = Op.getOperand(1);
9715 MVT VT = Op.getSimpleValueType();
9716 int NumElements = VT.getVectorNumElements();
9719 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9721 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9722 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9723 if (V1IsUndef && V2IsUndef)
9724 return DAG.getUNDEF(VT);
9726 // When we create a shuffle node we put the UNDEF node to second operand,
9727 // but in some cases the first operand may be transformed to UNDEF.
9728 // In this case we should just commute the node.
9730 return DAG.getCommutedVectorShuffle(*SVOp);
9732 // Check for non-undef masks pointing at an undef vector and make the masks
9733 // undef as well. This makes it easier to match the shuffle based solely on
9737 if (M >= NumElements) {
9738 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9739 for (int &M : NewMask)
9740 if (M >= NumElements)
9742 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9745 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9746 // lanes but wider integers. We cap this to not form integers larger than i64
9747 // but it might be interesting to form i128 integers to handle flipping the
9748 // low and high halves of AVX 256-bit vectors.
9749 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9750 canWidenShuffleElements(Mask)) {
9751 SmallVector<int, 8> NewMask;
9752 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9753 NewMask.push_back(Mask[i] != -1
9755 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9757 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9758 VT.getVectorNumElements() / 2);
9759 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9760 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9761 return DAG.getNode(ISD::BITCAST, dl, VT,
9762 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9765 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9766 for (int M : SVOp->getMask())
9769 else if (M < NumElements)
9774 // Commute the shuffle as needed such that more elements come from V1 than
9775 // V2. This allows us to match the shuffle pattern strictly on how many
9776 // elements come from V1 without handling the symmetric cases.
9777 if (NumV2Elements > NumV1Elements)
9778 return DAG.getCommutedVectorShuffle(*SVOp);
9780 // When the number of V1 and V2 elements are the same, try to minimize the
9781 // number of uses of V2 in the low half of the vector. When that is tied,
9782 // ensure that the sum of indices for V1 is equal to or lower than the sum
9784 if (NumV1Elements == NumV2Elements) {
9785 int LowV1Elements = 0, LowV2Elements = 0;
9786 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9787 if (M >= NumElements)
9791 if (LowV2Elements > LowV1Elements)
9792 return DAG.getCommutedVectorShuffle(*SVOp);
9794 int SumV1Indices = 0, SumV2Indices = 0;
9795 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9796 if (SVOp->getMask()[i] >= NumElements)
9798 else if (SVOp->getMask()[i] >= 0)
9800 if (SumV2Indices < SumV1Indices)
9801 return DAG.getCommutedVectorShuffle(*SVOp);
9804 // For each vector width, delegate to a specialized lowering routine.
9805 if (VT.getSizeInBits() == 128)
9806 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9808 if (VT.getSizeInBits() == 256)
9809 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9811 llvm_unreachable("Unimplemented!");
9815 //===----------------------------------------------------------------------===//
9816 // Legacy vector shuffle lowering
9818 // This code is the legacy code handling vector shuffles until the above
9819 // replaces its functionality and performance.
9820 //===----------------------------------------------------------------------===//
9822 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9823 bool hasInt256, unsigned *MaskOut = nullptr) {
9824 MVT EltVT = VT.getVectorElementType();
9826 // There is no blend with immediate in AVX-512.
9827 if (VT.is512BitVector())
9830 if (!hasSSE41 || EltVT == MVT::i8)
9832 if (!hasInt256 && VT == MVT::v16i16)
9835 unsigned MaskValue = 0;
9836 unsigned NumElems = VT.getVectorNumElements();
9837 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9838 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9839 unsigned NumElemsInLane = NumElems / NumLanes;
9841 // Blend for v16i16 should be symetric for the both lanes.
9842 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9844 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9845 int EltIdx = MaskVals[i];
9847 if ((EltIdx < 0 || EltIdx == (int)i) &&
9848 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9851 if (((unsigned)EltIdx == (i + NumElems)) &&
9852 (SndLaneEltIdx < 0 ||
9853 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9854 MaskValue |= (1 << i);
9860 *MaskOut = MaskValue;
9864 // Try to lower a shuffle node into a simple blend instruction.
9865 // This function assumes isBlendMask returns true for this
9866 // SuffleVectorSDNode
9867 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9869 const X86Subtarget *Subtarget,
9870 SelectionDAG &DAG) {
9871 MVT VT = SVOp->getSimpleValueType(0);
9872 MVT EltVT = VT.getVectorElementType();
9873 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9874 Subtarget->hasInt256() && "Trying to lower a "
9875 "VECTOR_SHUFFLE to a Blend but "
9876 "with the wrong mask"));
9877 SDValue V1 = SVOp->getOperand(0);
9878 SDValue V2 = SVOp->getOperand(1);
9880 unsigned NumElems = VT.getVectorNumElements();
9882 // Convert i32 vectors to floating point if it is not AVX2.
9883 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9885 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9886 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9888 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9889 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9892 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9893 DAG.getConstant(MaskValue, MVT::i32));
9894 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9897 /// In vector type \p VT, return true if the element at index \p InputIdx
9898 /// falls on a different 128-bit lane than \p OutputIdx.
9899 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9900 unsigned OutputIdx) {
9901 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9902 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9905 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9906 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9907 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9908 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9910 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9911 SelectionDAG &DAG) {
9912 MVT VT = V1.getSimpleValueType();
9913 assert(VT.is128BitVector() || VT.is256BitVector());
9915 MVT EltVT = VT.getVectorElementType();
9916 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9917 unsigned NumElts = VT.getVectorNumElements();
9919 SmallVector<SDValue, 32> PshufbMask;
9920 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9921 int InputIdx = MaskVals[OutputIdx];
9922 unsigned InputByteIdx;
9924 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9925 InputByteIdx = 0x80;
9927 // Cross lane is not allowed.
9928 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9930 InputByteIdx = InputIdx * EltSizeInBytes;
9931 // Index is an byte offset within the 128-bit lane.
9932 InputByteIdx &= 0xf;
9935 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9936 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9937 if (InputByteIdx != 0x80)
9942 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9944 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9945 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9946 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9949 // v8i16 shuffles - Prefer shuffles in the following order:
9950 // 1. [all] pshuflw, pshufhw, optional move
9951 // 2. [ssse3] 1 x pshufb
9952 // 3. [ssse3] 2 x pshufb + 1 x por
9953 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9955 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9956 SelectionDAG &DAG) {
9957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9958 SDValue V1 = SVOp->getOperand(0);
9959 SDValue V2 = SVOp->getOperand(1);
9961 SmallVector<int, 8> MaskVals;
9963 // Determine if more than 1 of the words in each of the low and high quadwords
9964 // of the result come from the same quadword of one of the two inputs. Undef
9965 // mask values count as coming from any quadword, for better codegen.
9967 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9968 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9969 unsigned LoQuad[] = { 0, 0, 0, 0 };
9970 unsigned HiQuad[] = { 0, 0, 0, 0 };
9971 // Indices of quads used.
9972 std::bitset<4> InputQuads;
9973 for (unsigned i = 0; i < 8; ++i) {
9974 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9975 int EltIdx = SVOp->getMaskElt(i);
9976 MaskVals.push_back(EltIdx);
9985 InputQuads.set(EltIdx / 4);
9988 int BestLoQuad = -1;
9989 unsigned MaxQuad = 1;
9990 for (unsigned i = 0; i < 4; ++i) {
9991 if (LoQuad[i] > MaxQuad) {
9993 MaxQuad = LoQuad[i];
9997 int BestHiQuad = -1;
9999 for (unsigned i = 0; i < 4; ++i) {
10000 if (HiQuad[i] > MaxQuad) {
10002 MaxQuad = HiQuad[i];
10006 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10007 // of the two input vectors, shuffle them into one input vector so only a
10008 // single pshufb instruction is necessary. If there are more than 2 input
10009 // quads, disable the next transformation since it does not help SSSE3.
10010 bool V1Used = InputQuads[0] || InputQuads[1];
10011 bool V2Used = InputQuads[2] || InputQuads[3];
10012 if (Subtarget->hasSSSE3()) {
10013 if (InputQuads.count() == 2 && V1Used && V2Used) {
10014 BestLoQuad = InputQuads[0] ? 0 : 1;
10015 BestHiQuad = InputQuads[2] ? 2 : 3;
10017 if (InputQuads.count() > 2) {
10023 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10024 // the shuffle mask. If a quad is scored as -1, that means that it contains
10025 // words from all 4 input quadwords.
10027 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10029 BestLoQuad < 0 ? 0 : BestLoQuad,
10030 BestHiQuad < 0 ? 1 : BestHiQuad
10032 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10033 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10034 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10035 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10037 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10038 // source words for the shuffle, to aid later transformations.
10039 bool AllWordsInNewV = true;
10040 bool InOrder[2] = { true, true };
10041 for (unsigned i = 0; i != 8; ++i) {
10042 int idx = MaskVals[i];
10044 InOrder[i/4] = false;
10045 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10047 AllWordsInNewV = false;
10051 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10052 if (AllWordsInNewV) {
10053 for (int i = 0; i != 8; ++i) {
10054 int idx = MaskVals[i];
10057 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10058 if ((idx != i) && idx < 4)
10060 if ((idx != i) && idx > 3)
10069 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10070 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10071 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10072 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10073 unsigned TargetMask = 0;
10074 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10075 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10076 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10077 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10078 getShufflePSHUFLWImmediate(SVOp);
10079 V1 = NewV.getOperand(0);
10080 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10084 // Promote splats to a larger type which usually leads to more efficient code.
10085 // FIXME: Is this true if pshufb is available?
10086 if (SVOp->isSplat())
10087 return PromoteSplat(SVOp, DAG);
10089 // If we have SSSE3, and all words of the result are from 1 input vector,
10090 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10091 // is present, fall back to case 4.
10092 if (Subtarget->hasSSSE3()) {
10093 SmallVector<SDValue,16> pshufbMask;
10095 // If we have elements from both input vectors, set the high bit of the
10096 // shuffle mask element to zero out elements that come from V2 in the V1
10097 // mask, and elements that come from V1 in the V2 mask, so that the two
10098 // results can be OR'd together.
10099 bool TwoInputs = V1Used && V2Used;
10100 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10102 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10104 // Calculate the shuffle mask for the second input, shuffle it, and
10105 // OR it with the first shuffled input.
10106 CommuteVectorShuffleMask(MaskVals, 8);
10107 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10108 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10109 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10112 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10113 // and update MaskVals with new element order.
10114 std::bitset<8> InOrder;
10115 if (BestLoQuad >= 0) {
10116 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10117 for (int i = 0; i != 4; ++i) {
10118 int idx = MaskVals[i];
10121 } else if ((idx / 4) == BestLoQuad) {
10122 MaskV[i] = idx & 3;
10126 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10129 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10131 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10132 NewV.getOperand(0),
10133 getShufflePSHUFLWImmediate(SVOp), DAG);
10137 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10138 // and update MaskVals with the new element order.
10139 if (BestHiQuad >= 0) {
10140 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10141 for (unsigned i = 4; i != 8; ++i) {
10142 int idx = MaskVals[i];
10145 } else if ((idx / 4) == BestHiQuad) {
10146 MaskV[i] = (idx & 3) + 4;
10150 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10153 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10154 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10155 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10156 NewV.getOperand(0),
10157 getShufflePSHUFHWImmediate(SVOp), DAG);
10161 // In case BestHi & BestLo were both -1, which means each quadword has a word
10162 // from each of the four input quadwords, calculate the InOrder bitvector now
10163 // before falling through to the insert/extract cleanup.
10164 if (BestLoQuad == -1 && BestHiQuad == -1) {
10166 for (int i = 0; i != 8; ++i)
10167 if (MaskVals[i] < 0 || MaskVals[i] == i)
10171 // The other elements are put in the right place using pextrw and pinsrw.
10172 for (unsigned i = 0; i != 8; ++i) {
10175 int EltIdx = MaskVals[i];
10178 SDValue ExtOp = (EltIdx < 8) ?
10179 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10180 DAG.getIntPtrConstant(EltIdx)) :
10181 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10182 DAG.getIntPtrConstant(EltIdx - 8));
10183 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10184 DAG.getIntPtrConstant(i));
10189 /// \brief v16i16 shuffles
10191 /// FIXME: We only support generation of a single pshufb currently. We can
10192 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10193 /// well (e.g 2 x pshufb + 1 x por).
10195 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10197 SDValue V1 = SVOp->getOperand(0);
10198 SDValue V2 = SVOp->getOperand(1);
10201 if (V2.getOpcode() != ISD::UNDEF)
10204 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10205 return getPSHUFB(MaskVals, V1, dl, DAG);
10208 // v16i8 shuffles - Prefer shuffles in the following order:
10209 // 1. [ssse3] 1 x pshufb
10210 // 2. [ssse3] 2 x pshufb + 1 x por
10211 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10212 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10213 const X86Subtarget* Subtarget,
10214 SelectionDAG &DAG) {
10215 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10216 SDValue V1 = SVOp->getOperand(0);
10217 SDValue V2 = SVOp->getOperand(1);
10219 ArrayRef<int> MaskVals = SVOp->getMask();
10221 // Promote splats to a larger type which usually leads to more efficient code.
10222 // FIXME: Is this true if pshufb is available?
10223 if (SVOp->isSplat())
10224 return PromoteSplat(SVOp, DAG);
10226 // If we have SSSE3, case 1 is generated when all result bytes come from
10227 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10228 // present, fall back to case 3.
10230 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10231 if (Subtarget->hasSSSE3()) {
10232 SmallVector<SDValue,16> pshufbMask;
10234 // If all result elements are from one input vector, then only translate
10235 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10237 // Otherwise, we have elements from both input vectors, and must zero out
10238 // elements that come from V2 in the first mask, and V1 in the second mask
10239 // so that we can OR them together.
10240 for (unsigned i = 0; i != 16; ++i) {
10241 int EltIdx = MaskVals[i];
10242 if (EltIdx < 0 || EltIdx >= 16)
10244 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10246 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10247 DAG.getNode(ISD::BUILD_VECTOR, dl,
10248 MVT::v16i8, pshufbMask));
10250 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10251 // the 2nd operand if it's undefined or zero.
10252 if (V2.getOpcode() == ISD::UNDEF ||
10253 ISD::isBuildVectorAllZeros(V2.getNode()))
10256 // Calculate the shuffle mask for the second input, shuffle it, and
10257 // OR it with the first shuffled input.
10258 pshufbMask.clear();
10259 for (unsigned i = 0; i != 16; ++i) {
10260 int EltIdx = MaskVals[i];
10261 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10262 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10264 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10265 DAG.getNode(ISD::BUILD_VECTOR, dl,
10266 MVT::v16i8, pshufbMask));
10267 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10270 // No SSSE3 - Calculate in place words and then fix all out of place words
10271 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10272 // the 16 different words that comprise the two doublequadword input vectors.
10273 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10274 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10276 for (int i = 0; i != 8; ++i) {
10277 int Elt0 = MaskVals[i*2];
10278 int Elt1 = MaskVals[i*2+1];
10280 // This word of the result is all undef, skip it.
10281 if (Elt0 < 0 && Elt1 < 0)
10284 // This word of the result is already in the correct place, skip it.
10285 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10288 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10289 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10292 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10293 // using a single extract together, load it and store it.
10294 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10295 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10296 DAG.getIntPtrConstant(Elt1 / 2));
10297 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10298 DAG.getIntPtrConstant(i));
10302 // If Elt1 is defined, extract it from the appropriate source. If the
10303 // source byte is not also odd, shift the extracted word left 8 bits
10304 // otherwise clear the bottom 8 bits if we need to do an or.
10306 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10307 DAG.getIntPtrConstant(Elt1 / 2));
10308 if ((Elt1 & 1) == 0)
10309 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10311 TLI.getShiftAmountTy(InsElt.getValueType())));
10312 else if (Elt0 >= 0)
10313 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10314 DAG.getConstant(0xFF00, MVT::i16));
10316 // If Elt0 is defined, extract it from the appropriate source. If the
10317 // source byte is not also even, shift the extracted word right 8 bits. If
10318 // Elt1 was also defined, OR the extracted values together before
10319 // inserting them in the result.
10321 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10322 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10323 if ((Elt0 & 1) != 0)
10324 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10326 TLI.getShiftAmountTy(InsElt0.getValueType())));
10327 else if (Elt1 >= 0)
10328 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10329 DAG.getConstant(0x00FF, MVT::i16));
10330 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10333 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10334 DAG.getIntPtrConstant(i));
10336 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10339 // v32i8 shuffles - Translate to VPSHUFB if possible.
10341 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10342 const X86Subtarget *Subtarget,
10343 SelectionDAG &DAG) {
10344 MVT VT = SVOp->getSimpleValueType(0);
10345 SDValue V1 = SVOp->getOperand(0);
10346 SDValue V2 = SVOp->getOperand(1);
10348 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10350 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10351 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10352 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10354 // VPSHUFB may be generated if
10355 // (1) one of input vector is undefined or zeroinitializer.
10356 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10357 // And (2) the mask indexes don't cross the 128-bit lane.
10358 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10359 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10362 if (V1IsAllZero && !V2IsAllZero) {
10363 CommuteVectorShuffleMask(MaskVals, 32);
10366 return getPSHUFB(MaskVals, V1, dl, DAG);
10369 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10370 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10371 /// done when every pair / quad of shuffle mask elements point to elements in
10372 /// the right sequence. e.g.
10373 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10375 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10376 SelectionDAG &DAG) {
10377 MVT VT = SVOp->getSimpleValueType(0);
10379 unsigned NumElems = VT.getVectorNumElements();
10382 switch (VT.SimpleTy) {
10383 default: llvm_unreachable("Unexpected!");
10386 return SDValue(SVOp, 0);
10387 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10388 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10389 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10390 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10391 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10392 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10395 SmallVector<int, 8> MaskVec;
10396 for (unsigned i = 0; i != NumElems; i += Scale) {
10398 for (unsigned j = 0; j != Scale; ++j) {
10399 int EltIdx = SVOp->getMaskElt(i+j);
10403 StartIdx = (EltIdx / Scale);
10404 if (EltIdx != (int)(StartIdx*Scale + j))
10407 MaskVec.push_back(StartIdx);
10410 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10411 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10412 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10415 /// getVZextMovL - Return a zero-extending vector move low node.
10417 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10418 SDValue SrcOp, SelectionDAG &DAG,
10419 const X86Subtarget *Subtarget, SDLoc dl) {
10420 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10421 LoadSDNode *LD = nullptr;
10422 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10423 LD = dyn_cast<LoadSDNode>(SrcOp);
10425 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10427 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10428 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10429 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10430 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10431 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10433 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10434 return DAG.getNode(ISD::BITCAST, dl, VT,
10435 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10436 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10438 SrcOp.getOperand(0)
10444 return DAG.getNode(ISD::BITCAST, dl, VT,
10445 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10446 DAG.getNode(ISD::BITCAST, dl,
10450 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10451 /// which could not be matched by any known target speficic shuffle
10453 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10455 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10456 if (NewOp.getNode())
10459 MVT VT = SVOp->getSimpleValueType(0);
10461 unsigned NumElems = VT.getVectorNumElements();
10462 unsigned NumLaneElems = NumElems / 2;
10465 MVT EltVT = VT.getVectorElementType();
10466 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10469 SmallVector<int, 16> Mask;
10470 for (unsigned l = 0; l < 2; ++l) {
10471 // Build a shuffle mask for the output, discovering on the fly which
10472 // input vectors to use as shuffle operands (recorded in InputUsed).
10473 // If building a suitable shuffle vector proves too hard, then bail
10474 // out with UseBuildVector set.
10475 bool UseBuildVector = false;
10476 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10477 unsigned LaneStart = l * NumLaneElems;
10478 for (unsigned i = 0; i != NumLaneElems; ++i) {
10479 // The mask element. This indexes into the input.
10480 int Idx = SVOp->getMaskElt(i+LaneStart);
10482 // the mask element does not index into any input vector.
10483 Mask.push_back(-1);
10487 // The input vector this mask element indexes into.
10488 int Input = Idx / NumLaneElems;
10490 // Turn the index into an offset from the start of the input vector.
10491 Idx -= Input * NumLaneElems;
10493 // Find or create a shuffle vector operand to hold this input.
10495 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10496 if (InputUsed[OpNo] == Input)
10497 // This input vector is already an operand.
10499 if (InputUsed[OpNo] < 0) {
10500 // Create a new operand for this input vector.
10501 InputUsed[OpNo] = Input;
10506 if (OpNo >= array_lengthof(InputUsed)) {
10507 // More than two input vectors used! Give up on trying to create a
10508 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10509 UseBuildVector = true;
10513 // Add the mask index for the new shuffle vector.
10514 Mask.push_back(Idx + OpNo * NumLaneElems);
10517 if (UseBuildVector) {
10518 SmallVector<SDValue, 16> SVOps;
10519 for (unsigned i = 0; i != NumLaneElems; ++i) {
10520 // The mask element. This indexes into the input.
10521 int Idx = SVOp->getMaskElt(i+LaneStart);
10523 SVOps.push_back(DAG.getUNDEF(EltVT));
10527 // The input vector this mask element indexes into.
10528 int Input = Idx / NumElems;
10530 // Turn the index into an offset from the start of the input vector.
10531 Idx -= Input * NumElems;
10533 // Extract the vector element by hand.
10534 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10535 SVOp->getOperand(Input),
10536 DAG.getIntPtrConstant(Idx)));
10539 // Construct the output using a BUILD_VECTOR.
10540 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10541 } else if (InputUsed[0] < 0) {
10542 // No input vectors were used! The result is undefined.
10543 Output[l] = DAG.getUNDEF(NVT);
10545 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10546 (InputUsed[0] % 2) * NumLaneElems,
10548 // If only one input was used, use an undefined vector for the other.
10549 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10550 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10551 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10552 // At least one input vector was used. Create a new shuffle vector.
10553 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10559 // Concatenate the result back
10560 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10563 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10564 /// 4 elements, and match them with several different shuffle types.
10566 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10567 SDValue V1 = SVOp->getOperand(0);
10568 SDValue V2 = SVOp->getOperand(1);
10570 MVT VT = SVOp->getSimpleValueType(0);
10572 assert(VT.is128BitVector() && "Unsupported vector size");
10574 std::pair<int, int> Locs[4];
10575 int Mask1[] = { -1, -1, -1, -1 };
10576 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10578 unsigned NumHi = 0;
10579 unsigned NumLo = 0;
10580 for (unsigned i = 0; i != 4; ++i) {
10581 int Idx = PermMask[i];
10583 Locs[i] = std::make_pair(-1, -1);
10585 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10587 Locs[i] = std::make_pair(0, NumLo);
10588 Mask1[NumLo] = Idx;
10591 Locs[i] = std::make_pair(1, NumHi);
10593 Mask1[2+NumHi] = Idx;
10599 if (NumLo <= 2 && NumHi <= 2) {
10600 // If no more than two elements come from either vector. This can be
10601 // implemented with two shuffles. First shuffle gather the elements.
10602 // The second shuffle, which takes the first shuffle as both of its
10603 // vector operands, put the elements into the right order.
10604 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10606 int Mask2[] = { -1, -1, -1, -1 };
10608 for (unsigned i = 0; i != 4; ++i)
10609 if (Locs[i].first != -1) {
10610 unsigned Idx = (i < 2) ? 0 : 4;
10611 Idx += Locs[i].first * 2 + Locs[i].second;
10615 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10618 if (NumLo == 3 || NumHi == 3) {
10619 // Otherwise, we must have three elements from one vector, call it X, and
10620 // one element from the other, call it Y. First, use a shufps to build an
10621 // intermediate vector with the one element from Y and the element from X
10622 // that will be in the same half in the final destination (the indexes don't
10623 // matter). Then, use a shufps to build the final vector, taking the half
10624 // containing the element from Y from the intermediate, and the other half
10627 // Normalize it so the 3 elements come from V1.
10628 CommuteVectorShuffleMask(PermMask, 4);
10632 // Find the element from V2.
10634 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10635 int Val = PermMask[HiIndex];
10642 Mask1[0] = PermMask[HiIndex];
10644 Mask1[2] = PermMask[HiIndex^1];
10646 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10648 if (HiIndex >= 2) {
10649 Mask1[0] = PermMask[0];
10650 Mask1[1] = PermMask[1];
10651 Mask1[2] = HiIndex & 1 ? 6 : 4;
10652 Mask1[3] = HiIndex & 1 ? 4 : 6;
10653 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10656 Mask1[0] = HiIndex & 1 ? 2 : 0;
10657 Mask1[1] = HiIndex & 1 ? 0 : 2;
10658 Mask1[2] = PermMask[2];
10659 Mask1[3] = PermMask[3];
10664 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10667 // Break it into (shuffle shuffle_hi, shuffle_lo).
10668 int LoMask[] = { -1, -1, -1, -1 };
10669 int HiMask[] = { -1, -1, -1, -1 };
10671 int *MaskPtr = LoMask;
10672 unsigned MaskIdx = 0;
10673 unsigned LoIdx = 0;
10674 unsigned HiIdx = 2;
10675 for (unsigned i = 0; i != 4; ++i) {
10682 int Idx = PermMask[i];
10684 Locs[i] = std::make_pair(-1, -1);
10685 } else if (Idx < 4) {
10686 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10687 MaskPtr[LoIdx] = Idx;
10690 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10691 MaskPtr[HiIdx] = Idx;
10696 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10697 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10698 int MaskOps[] = { -1, -1, -1, -1 };
10699 for (unsigned i = 0; i != 4; ++i)
10700 if (Locs[i].first != -1)
10701 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10702 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10705 static bool MayFoldVectorLoad(SDValue V) {
10706 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10707 V = V.getOperand(0);
10709 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10710 V = V.getOperand(0);
10711 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10712 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10713 // BUILD_VECTOR (load), undef
10714 V = V.getOperand(0);
10716 return MayFoldLoad(V);
10720 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10721 MVT VT = Op.getSimpleValueType();
10723 // Canonizalize to v2f64.
10724 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10725 return DAG.getNode(ISD::BITCAST, dl, VT,
10726 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10731 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10733 SDValue V1 = Op.getOperand(0);
10734 SDValue V2 = Op.getOperand(1);
10735 MVT VT = Op.getSimpleValueType();
10737 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10739 if (HasSSE2 && VT == MVT::v2f64)
10740 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10742 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10743 return DAG.getNode(ISD::BITCAST, dl, VT,
10744 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10745 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10746 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10750 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10751 SDValue V1 = Op.getOperand(0);
10752 SDValue V2 = Op.getOperand(1);
10753 MVT VT = Op.getSimpleValueType();
10755 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10756 "unsupported shuffle type");
10758 if (V2.getOpcode() == ISD::UNDEF)
10762 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10766 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10767 SDValue V1 = Op.getOperand(0);
10768 SDValue V2 = Op.getOperand(1);
10769 MVT VT = Op.getSimpleValueType();
10770 unsigned NumElems = VT.getVectorNumElements();
10772 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10773 // operand of these instructions is only memory, so check if there's a
10774 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10776 bool CanFoldLoad = false;
10778 // Trivial case, when V2 comes from a load.
10779 if (MayFoldVectorLoad(V2))
10780 CanFoldLoad = true;
10782 // When V1 is a load, it can be folded later into a store in isel, example:
10783 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10785 // (MOVLPSmr addr:$src1, VR128:$src2)
10786 // So, recognize this potential and also use MOVLPS or MOVLPD
10787 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10788 CanFoldLoad = true;
10790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10792 if (HasSSE2 && NumElems == 2)
10793 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10796 // If we don't care about the second element, proceed to use movss.
10797 if (SVOp->getMaskElt(1) != -1)
10798 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10801 // movl and movlp will both match v2i64, but v2i64 is never matched by
10802 // movl earlier because we make it strict to avoid messing with the movlp load
10803 // folding logic (see the code above getMOVLP call). Match it here then,
10804 // this is horrible, but will stay like this until we move all shuffle
10805 // matching to x86 specific nodes. Note that for the 1st condition all
10806 // types are matched with movsd.
10808 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10809 // as to remove this logic from here, as much as possible
10810 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10811 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10812 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10815 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10817 // Invert the operand order and use SHUFPS to match it.
10818 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10819 getShuffleSHUFImmediate(SVOp), DAG);
10822 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10823 SelectionDAG &DAG) {
10825 MVT VT = Load->getSimpleValueType(0);
10826 MVT EVT = VT.getVectorElementType();
10827 SDValue Addr = Load->getOperand(1);
10828 SDValue NewAddr = DAG.getNode(
10829 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10830 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10833 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10834 DAG.getMachineFunction().getMachineMemOperand(
10835 Load->getMemOperand(), 0, EVT.getStoreSize()));
10839 // It is only safe to call this function if isINSERTPSMask is true for
10840 // this shufflevector mask.
10841 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10842 SelectionDAG &DAG) {
10843 // Generate an insertps instruction when inserting an f32 from memory onto a
10844 // v4f32 or when copying a member from one v4f32 to another.
10845 // We also use it for transferring i32 from one register to another,
10846 // since it simply copies the same bits.
10847 // If we're transferring an i32 from memory to a specific element in a
10848 // register, we output a generic DAG that will match the PINSRD
10850 MVT VT = SVOp->getSimpleValueType(0);
10851 MVT EVT = VT.getVectorElementType();
10852 SDValue V1 = SVOp->getOperand(0);
10853 SDValue V2 = SVOp->getOperand(1);
10854 auto Mask = SVOp->getMask();
10855 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10856 "unsupported vector type for insertps/pinsrd");
10858 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10859 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10860 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10864 unsigned DestIndex;
10868 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10871 // If we have 1 element from each vector, we have to check if we're
10872 // changing V1's element's place. If so, we're done. Otherwise, we
10873 // should assume we're changing V2's element's place and behave
10875 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10876 assert(DestIndex <= INT32_MAX && "truncated destination index");
10877 if (FromV1 == FromV2 &&
10878 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10882 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10885 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10886 "More than one element from V1 and from V2, or no elements from one "
10887 "of the vectors. This case should not have returned true from "
10892 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10895 // Get an index into the source vector in the range [0,4) (the mask is
10896 // in the range [0,8) because it can address V1 and V2)
10897 unsigned SrcIndex = Mask[DestIndex] % 4;
10898 if (MayFoldLoad(From)) {
10899 // Trivial case, when From comes from a load and is only used by the
10900 // shuffle. Make it use insertps from the vector that we need from that
10903 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10904 if (!NewLoad.getNode())
10907 if (EVT == MVT::f32) {
10908 // Create this as a scalar to vector to match the instruction pattern.
10909 SDValue LoadScalarToVector =
10910 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10911 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10912 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10914 } else { // EVT == MVT::i32
10915 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10916 // instruction, to match the PINSRD instruction, which loads an i32 to a
10917 // certain vector element.
10918 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10919 DAG.getConstant(DestIndex, MVT::i32));
10923 // Vector-element-to-vector
10924 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10925 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10928 // Reduce a vector shuffle to zext.
10929 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10930 SelectionDAG &DAG) {
10931 // PMOVZX is only available from SSE41.
10932 if (!Subtarget->hasSSE41())
10935 MVT VT = Op.getSimpleValueType();
10937 // Only AVX2 support 256-bit vector integer extending.
10938 if (!Subtarget->hasInt256() && VT.is256BitVector())
10941 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10943 SDValue V1 = Op.getOperand(0);
10944 SDValue V2 = Op.getOperand(1);
10945 unsigned NumElems = VT.getVectorNumElements();
10947 // Extending is an unary operation and the element type of the source vector
10948 // won't be equal to or larger than i64.
10949 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10950 VT.getVectorElementType() == MVT::i64)
10953 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10954 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10955 while ((1U << Shift) < NumElems) {
10956 if (SVOp->getMaskElt(1U << Shift) == 1)
10959 // The maximal ratio is 8, i.e. from i8 to i64.
10964 // Check the shuffle mask.
10965 unsigned Mask = (1U << Shift) - 1;
10966 for (unsigned i = 0; i != NumElems; ++i) {
10967 int EltIdx = SVOp->getMaskElt(i);
10968 if ((i & Mask) != 0 && EltIdx != -1)
10970 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10974 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10975 MVT NeVT = MVT::getIntegerVT(NBits);
10976 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10978 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10981 // Simplify the operand as it's prepared to be fed into shuffle.
10982 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10983 if (V1.getOpcode() == ISD::BITCAST &&
10984 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10985 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10986 V1.getOperand(0).getOperand(0)
10987 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10988 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10989 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10990 ConstantSDNode *CIdx =
10991 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10992 // If it's foldable, i.e. normal load with single use, we will let code
10993 // selection to fold it. Otherwise, we will short the conversion sequence.
10994 if (CIdx && CIdx->getZExtValue() == 0 &&
10995 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10996 MVT FullVT = V.getSimpleValueType();
10997 MVT V1VT = V1.getSimpleValueType();
10998 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10999 // The "ext_vec_elt" node is wider than the result node.
11000 // In this case we should extract subvector from V.
11001 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11002 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11003 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11004 FullVT.getVectorNumElements()/Ratio);
11005 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11006 DAG.getIntPtrConstant(0));
11008 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11012 return DAG.getNode(ISD::BITCAST, DL, VT,
11013 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11016 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11017 SelectionDAG &DAG) {
11018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11019 MVT VT = Op.getSimpleValueType();
11021 SDValue V1 = Op.getOperand(0);
11022 SDValue V2 = Op.getOperand(1);
11024 if (isZeroShuffle(SVOp))
11025 return getZeroVector(VT, Subtarget, DAG, dl);
11027 // Handle splat operations
11028 if (SVOp->isSplat()) {
11029 // Use vbroadcast whenever the splat comes from a foldable load
11030 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11031 if (Broadcast.getNode())
11035 // Check integer expanding shuffles.
11036 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11037 if (NewOp.getNode())
11040 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11042 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11043 VT == MVT::v32i8) {
11044 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11045 if (NewOp.getNode())
11046 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11047 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11048 // FIXME: Figure out a cleaner way to do this.
11049 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11050 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11051 if (NewOp.getNode()) {
11052 MVT NewVT = NewOp.getSimpleValueType();
11053 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11054 NewVT, true, false))
11055 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11058 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11059 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11060 if (NewOp.getNode()) {
11061 MVT NewVT = NewOp.getSimpleValueType();
11062 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11063 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11072 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11074 SDValue V1 = Op.getOperand(0);
11075 SDValue V2 = Op.getOperand(1);
11076 MVT VT = Op.getSimpleValueType();
11078 unsigned NumElems = VT.getVectorNumElements();
11079 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11080 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11081 bool V1IsSplat = false;
11082 bool V2IsSplat = false;
11083 bool HasSSE2 = Subtarget->hasSSE2();
11084 bool HasFp256 = Subtarget->hasFp256();
11085 bool HasInt256 = Subtarget->hasInt256();
11086 MachineFunction &MF = DAG.getMachineFunction();
11087 bool OptForSize = MF.getFunction()->getAttributes().
11088 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11090 // Check if we should use the experimental vector shuffle lowering. If so,
11091 // delegate completely to that code path.
11092 if (ExperimentalVectorShuffleLowering)
11093 return lowerVectorShuffle(Op, Subtarget, DAG);
11095 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11097 if (V1IsUndef && V2IsUndef)
11098 return DAG.getUNDEF(VT);
11100 // When we create a shuffle node we put the UNDEF node to second operand,
11101 // but in some cases the first operand may be transformed to UNDEF.
11102 // In this case we should just commute the node.
11104 return DAG.getCommutedVectorShuffle(*SVOp);
11106 // Vector shuffle lowering takes 3 steps:
11108 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11109 // narrowing and commutation of operands should be handled.
11110 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11112 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11113 // so the shuffle can be broken into other shuffles and the legalizer can
11114 // try the lowering again.
11116 // The general idea is that no vector_shuffle operation should be left to
11117 // be matched during isel, all of them must be converted to a target specific
11120 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11121 // narrowing and commutation of operands should be handled. The actual code
11122 // doesn't include all of those, work in progress...
11123 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11124 if (NewOp.getNode())
11127 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11129 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11130 // unpckh_undef). Only use pshufd if speed is more important than size.
11131 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11132 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11133 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11134 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11136 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11137 V2IsUndef && MayFoldVectorLoad(V1))
11138 return getMOVDDup(Op, dl, V1, DAG);
11140 if (isMOVHLPS_v_undef_Mask(M, VT))
11141 return getMOVHighToLow(Op, dl, DAG);
11143 // Use to match splats
11144 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11145 (VT == MVT::v2f64 || VT == MVT::v2i64))
11146 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11148 if (isPSHUFDMask(M, VT)) {
11149 // The actual implementation will match the mask in the if above and then
11150 // during isel it can match several different instructions, not only pshufd
11151 // as its name says, sad but true, emulate the behavior for now...
11152 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11153 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11155 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11157 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11158 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11160 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11161 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11164 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11168 if (isPALIGNRMask(M, VT, Subtarget))
11169 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11170 getShufflePALIGNRImmediate(SVOp),
11173 if (isVALIGNMask(M, VT, Subtarget))
11174 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11175 getShuffleVALIGNImmediate(SVOp),
11178 // Check if this can be converted into a logical shift.
11179 bool isLeft = false;
11180 unsigned ShAmt = 0;
11182 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11183 if (isShift && ShVal.hasOneUse()) {
11184 // If the shifted value has multiple uses, it may be cheaper to use
11185 // v_set0 + movlhps or movhlps, etc.
11186 MVT EltVT = VT.getVectorElementType();
11187 ShAmt *= EltVT.getSizeInBits();
11188 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11191 if (isMOVLMask(M, VT)) {
11192 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11193 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11194 if (!isMOVLPMask(M, VT)) {
11195 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11196 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11198 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11199 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11203 // FIXME: fold these into legal mask.
11204 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11205 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11207 if (isMOVHLPSMask(M, VT))
11208 return getMOVHighToLow(Op, dl, DAG);
11210 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11211 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11213 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11214 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11216 if (isMOVLPMask(M, VT))
11217 return getMOVLP(Op, dl, DAG, HasSSE2);
11219 if (ShouldXformToMOVHLPS(M, VT) ||
11220 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11221 return DAG.getCommutedVectorShuffle(*SVOp);
11224 // No better options. Use a vshldq / vsrldq.
11225 MVT EltVT = VT.getVectorElementType();
11226 ShAmt *= EltVT.getSizeInBits();
11227 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11230 bool Commuted = false;
11231 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11232 // 1,1,1,1 -> v8i16 though.
11233 BitVector UndefElements;
11234 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11235 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11237 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11238 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11241 // Canonicalize the splat or undef, if present, to be on the RHS.
11242 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11243 CommuteVectorShuffleMask(M, NumElems);
11245 std::swap(V1IsSplat, V2IsSplat);
11249 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11250 // Shuffling low element of v1 into undef, just return v1.
11253 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11254 // the instruction selector will not match, so get a canonical MOVL with
11255 // swapped operands to undo the commute.
11256 return getMOVL(DAG, dl, VT, V2, V1);
11259 if (isUNPCKLMask(M, VT, HasInt256))
11260 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11262 if (isUNPCKHMask(M, VT, HasInt256))
11263 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11266 // Normalize mask so all entries that point to V2 points to its first
11267 // element then try to match unpck{h|l} again. If match, return a
11268 // new vector_shuffle with the corrected mask.p
11269 SmallVector<int, 8> NewMask(M.begin(), M.end());
11270 NormalizeMask(NewMask, NumElems);
11271 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11272 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11273 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11274 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11278 // Commute is back and try unpck* again.
11279 // FIXME: this seems wrong.
11280 CommuteVectorShuffleMask(M, NumElems);
11282 std::swap(V1IsSplat, V2IsSplat);
11284 if (isUNPCKLMask(M, VT, HasInt256))
11285 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11287 if (isUNPCKHMask(M, VT, HasInt256))
11288 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11291 // Normalize the node to match x86 shuffle ops if needed
11292 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11293 return DAG.getCommutedVectorShuffle(*SVOp);
11295 // The checks below are all present in isShuffleMaskLegal, but they are
11296 // inlined here right now to enable us to directly emit target specific
11297 // nodes, and remove one by one until they don't return Op anymore.
11299 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11300 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11301 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11302 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11305 if (isPSHUFHWMask(M, VT, HasInt256))
11306 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11307 getShufflePSHUFHWImmediate(SVOp),
11310 if (isPSHUFLWMask(M, VT, HasInt256))
11311 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11312 getShufflePSHUFLWImmediate(SVOp),
11315 unsigned MaskValue;
11316 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11318 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11320 if (isSHUFPMask(M, VT))
11321 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11322 getShuffleSHUFImmediate(SVOp), DAG);
11324 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11325 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11326 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11327 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11329 //===--------------------------------------------------------------------===//
11330 // Generate target specific nodes for 128 or 256-bit shuffles only
11331 // supported in the AVX instruction set.
11334 // Handle VMOVDDUPY permutations
11335 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11336 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11338 // Handle VPERMILPS/D* permutations
11339 if (isVPERMILPMask(M, VT)) {
11340 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11341 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11342 getShuffleSHUFImmediate(SVOp), DAG);
11343 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11344 getShuffleSHUFImmediate(SVOp), DAG);
11348 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11349 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11350 Idx*(NumElems/2), DAG, dl);
11352 // Handle VPERM2F128/VPERM2I128 permutations
11353 if (isVPERM2X128Mask(M, VT, HasFp256))
11354 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11355 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11357 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11358 return getINSERTPS(SVOp, dl, DAG);
11361 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11362 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11364 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11365 VT.is512BitVector()) {
11366 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11367 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11368 SmallVector<SDValue, 16> permclMask;
11369 for (unsigned i = 0; i != NumElems; ++i) {
11370 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11373 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11375 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11376 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11377 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11378 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11379 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11382 //===--------------------------------------------------------------------===//
11383 // Since no target specific shuffle was selected for this generic one,
11384 // lower it into other known shuffles. FIXME: this isn't true yet, but
11385 // this is the plan.
11388 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11389 if (VT == MVT::v8i16) {
11390 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11391 if (NewOp.getNode())
11395 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11396 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11397 if (NewOp.getNode())
11401 if (VT == MVT::v16i8) {
11402 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11403 if (NewOp.getNode())
11407 if (VT == MVT::v32i8) {
11408 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11409 if (NewOp.getNode())
11413 // Handle all 128-bit wide vectors with 4 elements, and match them with
11414 // several different shuffle types.
11415 if (NumElems == 4 && VT.is128BitVector())
11416 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11418 // Handle general 256-bit shuffles
11419 if (VT.is256BitVector())
11420 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11425 // This function assumes its argument is a BUILD_VECTOR of constants or
11426 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11428 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11429 unsigned &MaskValue) {
11431 unsigned NumElems = BuildVector->getNumOperands();
11432 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11433 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11434 unsigned NumElemsInLane = NumElems / NumLanes;
11436 // Blend for v16i16 should be symetric for the both lanes.
11437 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11438 SDValue EltCond = BuildVector->getOperand(i);
11439 SDValue SndLaneEltCond =
11440 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11442 int Lane1Cond = -1, Lane2Cond = -1;
11443 if (isa<ConstantSDNode>(EltCond))
11444 Lane1Cond = !isZero(EltCond);
11445 if (isa<ConstantSDNode>(SndLaneEltCond))
11446 Lane2Cond = !isZero(SndLaneEltCond);
11448 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11449 // Lane1Cond != 0, means we want the first argument.
11450 // Lane1Cond == 0, means we want the second argument.
11451 // The encoding of this argument is 0 for the first argument, 1
11452 // for the second. Therefore, invert the condition.
11453 MaskValue |= !Lane1Cond << i;
11454 else if (Lane1Cond < 0)
11455 MaskValue |= !Lane2Cond << i;
11462 // Try to lower a vselect node into a simple blend instruction.
11463 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11464 SelectionDAG &DAG) {
11465 SDValue Cond = Op.getOperand(0);
11466 SDValue LHS = Op.getOperand(1);
11467 SDValue RHS = Op.getOperand(2);
11469 MVT VT = Op.getSimpleValueType();
11470 MVT EltVT = VT.getVectorElementType();
11471 unsigned NumElems = VT.getVectorNumElements();
11473 // There is no blend with immediate in AVX-512.
11474 if (VT.is512BitVector())
11477 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11479 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11482 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11485 // Check the mask for BLEND and build the value.
11486 unsigned MaskValue = 0;
11487 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11490 // Convert i32 vectors to floating point if it is not AVX2.
11491 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11493 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11494 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11496 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11497 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11500 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11501 DAG.getConstant(MaskValue, MVT::i32));
11502 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11505 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11506 // A vselect where all conditions and data are constants can be optimized into
11507 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11508 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11509 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11510 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11513 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11514 if (BlendOp.getNode())
11517 // Some types for vselect were previously set to Expand, not Legal or
11518 // Custom. Return an empty SDValue so we fall-through to Expand, after
11519 // the Custom lowering phase.
11520 MVT VT = Op.getSimpleValueType();
11521 switch (VT.SimpleTy) {
11526 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11531 // We couldn't create a "Blend with immediate" node.
11532 // This node should still be legal, but we'll have to emit a blendv*
11537 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11538 MVT VT = Op.getSimpleValueType();
11541 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11544 if (VT.getSizeInBits() == 8) {
11545 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11546 Op.getOperand(0), Op.getOperand(1));
11547 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11548 DAG.getValueType(VT));
11549 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11552 if (VT.getSizeInBits() == 16) {
11553 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11554 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11556 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11557 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11558 DAG.getNode(ISD::BITCAST, dl,
11561 Op.getOperand(1)));
11562 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11563 Op.getOperand(0), Op.getOperand(1));
11564 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11565 DAG.getValueType(VT));
11566 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11569 if (VT == MVT::f32) {
11570 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11571 // the result back to FR32 register. It's only worth matching if the
11572 // result has a single use which is a store or a bitcast to i32. And in
11573 // the case of a store, it's not worth it if the index is a constant 0,
11574 // because a MOVSSmr can be used instead, which is smaller and faster.
11575 if (!Op.hasOneUse())
11577 SDNode *User = *Op.getNode()->use_begin();
11578 if ((User->getOpcode() != ISD::STORE ||
11579 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11580 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11581 (User->getOpcode() != ISD::BITCAST ||
11582 User->getValueType(0) != MVT::i32))
11584 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11585 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11588 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11591 if (VT == MVT::i32 || VT == MVT::i64) {
11592 // ExtractPS/pextrq works with constant index.
11593 if (isa<ConstantSDNode>(Op.getOperand(1)))
11599 /// Extract one bit from mask vector, like v16i1 or v8i1.
11600 /// AVX-512 feature.
11602 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11603 SDValue Vec = Op.getOperand(0);
11605 MVT VecVT = Vec.getSimpleValueType();
11606 SDValue Idx = Op.getOperand(1);
11607 MVT EltVT = Op.getSimpleValueType();
11609 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11611 // variable index can't be handled in mask registers,
11612 // extend vector to VR512
11613 if (!isa<ConstantSDNode>(Idx)) {
11614 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11615 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11616 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11617 ExtVT.getVectorElementType(), Ext, Idx);
11618 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11621 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11622 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11623 unsigned MaxSift = rc->getSize()*8 - 1;
11624 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11625 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11626 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11627 DAG.getConstant(MaxSift, MVT::i8));
11628 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11629 DAG.getIntPtrConstant(0));
11633 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11634 SelectionDAG &DAG) const {
11636 SDValue Vec = Op.getOperand(0);
11637 MVT VecVT = Vec.getSimpleValueType();
11638 SDValue Idx = Op.getOperand(1);
11640 if (Op.getSimpleValueType() == MVT::i1)
11641 return ExtractBitFromMaskVector(Op, DAG);
11643 if (!isa<ConstantSDNode>(Idx)) {
11644 if (VecVT.is512BitVector() ||
11645 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11646 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11649 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11650 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11651 MaskEltVT.getSizeInBits());
11653 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11654 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11655 getZeroVector(MaskVT, Subtarget, DAG, dl),
11656 Idx, DAG.getConstant(0, getPointerTy()));
11657 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11658 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11659 Perm, DAG.getConstant(0, getPointerTy()));
11664 // If this is a 256-bit vector result, first extract the 128-bit vector and
11665 // then extract the element from the 128-bit vector.
11666 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11668 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11669 // Get the 128-bit vector.
11670 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11671 MVT EltVT = VecVT.getVectorElementType();
11673 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11675 //if (IdxVal >= NumElems/2)
11676 // IdxVal -= NumElems/2;
11677 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11678 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11679 DAG.getConstant(IdxVal, MVT::i32));
11682 assert(VecVT.is128BitVector() && "Unexpected vector length");
11684 if (Subtarget->hasSSE41()) {
11685 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11690 MVT VT = Op.getSimpleValueType();
11691 // TODO: handle v16i8.
11692 if (VT.getSizeInBits() == 16) {
11693 SDValue Vec = Op.getOperand(0);
11694 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11696 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11697 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11698 DAG.getNode(ISD::BITCAST, dl,
11700 Op.getOperand(1)));
11701 // Transform it so it match pextrw which produces a 32-bit result.
11702 MVT EltVT = MVT::i32;
11703 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11704 Op.getOperand(0), Op.getOperand(1));
11705 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11706 DAG.getValueType(VT));
11707 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11710 if (VT.getSizeInBits() == 32) {
11711 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11715 // SHUFPS the element to the lowest double word, then movss.
11716 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11717 MVT VVT = Op.getOperand(0).getSimpleValueType();
11718 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11719 DAG.getUNDEF(VVT), Mask);
11720 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11721 DAG.getIntPtrConstant(0));
11724 if (VT.getSizeInBits() == 64) {
11725 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11726 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11727 // to match extract_elt for f64.
11728 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11732 // UNPCKHPD the element to the lowest double word, then movsd.
11733 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11734 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11735 int Mask[2] = { 1, -1 };
11736 MVT VVT = Op.getOperand(0).getSimpleValueType();
11737 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11738 DAG.getUNDEF(VVT), Mask);
11739 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11740 DAG.getIntPtrConstant(0));
11746 /// Insert one bit to mask vector, like v16i1 or v8i1.
11747 /// AVX-512 feature.
11749 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11751 SDValue Vec = Op.getOperand(0);
11752 SDValue Elt = Op.getOperand(1);
11753 SDValue Idx = Op.getOperand(2);
11754 MVT VecVT = Vec.getSimpleValueType();
11756 if (!isa<ConstantSDNode>(Idx)) {
11757 // Non constant index. Extend source and destination,
11758 // insert element and then truncate the result.
11759 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11760 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11761 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11762 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11763 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11764 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11767 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11768 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11769 if (Vec.getOpcode() == ISD::UNDEF)
11770 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11771 DAG.getConstant(IdxVal, MVT::i8));
11772 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11773 unsigned MaxSift = rc->getSize()*8 - 1;
11774 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11775 DAG.getConstant(MaxSift, MVT::i8));
11776 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11777 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11778 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11781 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11782 SelectionDAG &DAG) const {
11783 MVT VT = Op.getSimpleValueType();
11784 MVT EltVT = VT.getVectorElementType();
11786 if (EltVT == MVT::i1)
11787 return InsertBitToMaskVector(Op, DAG);
11790 SDValue N0 = Op.getOperand(0);
11791 SDValue N1 = Op.getOperand(1);
11792 SDValue N2 = Op.getOperand(2);
11793 if (!isa<ConstantSDNode>(N2))
11795 auto *N2C = cast<ConstantSDNode>(N2);
11796 unsigned IdxVal = N2C->getZExtValue();
11798 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11799 // into that, and then insert the subvector back into the result.
11800 if (VT.is256BitVector() || VT.is512BitVector()) {
11801 // Get the desired 128-bit vector half.
11802 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11804 // Insert the element into the desired half.
11805 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11806 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11808 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11809 DAG.getConstant(IdxIn128, MVT::i32));
11811 // Insert the changed part back to the 256-bit vector
11812 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11814 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11816 if (Subtarget->hasSSE41()) {
11817 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11819 if (VT == MVT::v8i16) {
11820 Opc = X86ISD::PINSRW;
11822 assert(VT == MVT::v16i8);
11823 Opc = X86ISD::PINSRB;
11826 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11828 if (N1.getValueType() != MVT::i32)
11829 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11830 if (N2.getValueType() != MVT::i32)
11831 N2 = DAG.getIntPtrConstant(IdxVal);
11832 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11835 if (EltVT == MVT::f32) {
11836 // Bits [7:6] of the constant are the source select. This will always be
11837 // zero here. The DAG Combiner may combine an extract_elt index into
11839 // bits. For example (insert (extract, 3), 2) could be matched by
11841 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11842 // Bits [5:4] of the constant are the destination select. This is the
11843 // value of the incoming immediate.
11844 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11845 // combine either bitwise AND or insert of float 0.0 to set these bits.
11846 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11847 // Create this as a scalar to vector..
11848 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11849 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11852 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11853 // PINSR* works with constant index.
11858 if (EltVT == MVT::i8)
11861 if (EltVT.getSizeInBits() == 16) {
11862 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11863 // as its second argument.
11864 if (N1.getValueType() != MVT::i32)
11865 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11866 if (N2.getValueType() != MVT::i32)
11867 N2 = DAG.getIntPtrConstant(IdxVal);
11868 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11873 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11875 MVT OpVT = Op.getSimpleValueType();
11877 // If this is a 256-bit vector result, first insert into a 128-bit
11878 // vector and then insert into the 256-bit vector.
11879 if (!OpVT.is128BitVector()) {
11880 // Insert into a 128-bit vector.
11881 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11882 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11883 OpVT.getVectorNumElements() / SizeFactor);
11885 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11887 // Insert the 128-bit vector.
11888 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11891 if (OpVT == MVT::v1i64 &&
11892 Op.getOperand(0).getValueType() == MVT::i64)
11893 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11895 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11896 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11897 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11901 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11902 // a simple subregister reference or explicit instructions to grab
11903 // upper bits of a vector.
11904 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11905 SelectionDAG &DAG) {
11907 SDValue In = Op.getOperand(0);
11908 SDValue Idx = Op.getOperand(1);
11909 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11910 MVT ResVT = Op.getSimpleValueType();
11911 MVT InVT = In.getSimpleValueType();
11913 if (Subtarget->hasFp256()) {
11914 if (ResVT.is128BitVector() &&
11915 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11916 isa<ConstantSDNode>(Idx)) {
11917 return Extract128BitVector(In, IdxVal, DAG, dl);
11919 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11920 isa<ConstantSDNode>(Idx)) {
11921 return Extract256BitVector(In, IdxVal, DAG, dl);
11927 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11928 // simple superregister reference or explicit instructions to insert
11929 // the upper bits of a vector.
11930 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11931 SelectionDAG &DAG) {
11932 if (Subtarget->hasFp256()) {
11933 SDLoc dl(Op.getNode());
11934 SDValue Vec = Op.getNode()->getOperand(0);
11935 SDValue SubVec = Op.getNode()->getOperand(1);
11936 SDValue Idx = Op.getNode()->getOperand(2);
11938 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11939 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11940 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11941 isa<ConstantSDNode>(Idx)) {
11942 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11943 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11946 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11947 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11948 isa<ConstantSDNode>(Idx)) {
11949 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11950 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11956 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11957 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11958 // one of the above mentioned nodes. It has to be wrapped because otherwise
11959 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11960 // be used to form addressing mode. These wrapped nodes will be selected
11963 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11964 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11966 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11967 // global base reg.
11968 unsigned char OpFlag = 0;
11969 unsigned WrapperKind = X86ISD::Wrapper;
11970 CodeModel::Model M = DAG.getTarget().getCodeModel();
11972 if (Subtarget->isPICStyleRIPRel() &&
11973 (M == CodeModel::Small || M == CodeModel::Kernel))
11974 WrapperKind = X86ISD::WrapperRIP;
11975 else if (Subtarget->isPICStyleGOT())
11976 OpFlag = X86II::MO_GOTOFF;
11977 else if (Subtarget->isPICStyleStubPIC())
11978 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11980 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11981 CP->getAlignment(),
11982 CP->getOffset(), OpFlag);
11984 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11985 // With PIC, the address is actually $g + Offset.
11987 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11988 DAG.getNode(X86ISD::GlobalBaseReg,
11989 SDLoc(), getPointerTy()),
11996 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11997 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11999 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12000 // global base reg.
12001 unsigned char OpFlag = 0;
12002 unsigned WrapperKind = X86ISD::Wrapper;
12003 CodeModel::Model M = DAG.getTarget().getCodeModel();
12005 if (Subtarget->isPICStyleRIPRel() &&
12006 (M == CodeModel::Small || M == CodeModel::Kernel))
12007 WrapperKind = X86ISD::WrapperRIP;
12008 else if (Subtarget->isPICStyleGOT())
12009 OpFlag = X86II::MO_GOTOFF;
12010 else if (Subtarget->isPICStyleStubPIC())
12011 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12013 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12016 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12018 // With PIC, the address is actually $g + Offset.
12020 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12021 DAG.getNode(X86ISD::GlobalBaseReg,
12022 SDLoc(), getPointerTy()),
12029 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12030 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12032 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12033 // global base reg.
12034 unsigned char OpFlag = 0;
12035 unsigned WrapperKind = X86ISD::Wrapper;
12036 CodeModel::Model M = DAG.getTarget().getCodeModel();
12038 if (Subtarget->isPICStyleRIPRel() &&
12039 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12040 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12041 OpFlag = X86II::MO_GOTPCREL;
12042 WrapperKind = X86ISD::WrapperRIP;
12043 } else if (Subtarget->isPICStyleGOT()) {
12044 OpFlag = X86II::MO_GOT;
12045 } else if (Subtarget->isPICStyleStubPIC()) {
12046 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12047 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12048 OpFlag = X86II::MO_DARWIN_NONLAZY;
12051 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12054 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12056 // With PIC, the address is actually $g + Offset.
12057 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12058 !Subtarget->is64Bit()) {
12059 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12060 DAG.getNode(X86ISD::GlobalBaseReg,
12061 SDLoc(), getPointerTy()),
12065 // For symbols that require a load from a stub to get the address, emit the
12067 if (isGlobalStubReference(OpFlag))
12068 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12069 MachinePointerInfo::getGOT(), false, false, false, 0);
12075 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12076 // Create the TargetBlockAddressAddress node.
12077 unsigned char OpFlags =
12078 Subtarget->ClassifyBlockAddressReference();
12079 CodeModel::Model M = DAG.getTarget().getCodeModel();
12080 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12081 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12083 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12086 if (Subtarget->isPICStyleRIPRel() &&
12087 (M == CodeModel::Small || M == CodeModel::Kernel))
12088 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12090 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12092 // With PIC, the address is actually $g + Offset.
12093 if (isGlobalRelativeToPICBase(OpFlags)) {
12094 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12095 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12103 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12104 int64_t Offset, SelectionDAG &DAG) const {
12105 // Create the TargetGlobalAddress node, folding in the constant
12106 // offset if it is legal.
12107 unsigned char OpFlags =
12108 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12109 CodeModel::Model M = DAG.getTarget().getCodeModel();
12111 if (OpFlags == X86II::MO_NO_FLAG &&
12112 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12113 // A direct static reference to a global.
12114 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12117 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12120 if (Subtarget->isPICStyleRIPRel() &&
12121 (M == CodeModel::Small || M == CodeModel::Kernel))
12122 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12124 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12126 // With PIC, the address is actually $g + Offset.
12127 if (isGlobalRelativeToPICBase(OpFlags)) {
12128 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12129 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12133 // For globals that require a load from a stub to get the address, emit the
12135 if (isGlobalStubReference(OpFlags))
12136 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12137 MachinePointerInfo::getGOT(), false, false, false, 0);
12139 // If there was a non-zero offset that we didn't fold, create an explicit
12140 // addition for it.
12142 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12143 DAG.getConstant(Offset, getPointerTy()));
12149 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12150 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12151 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12152 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12156 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12157 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12158 unsigned char OperandFlags, bool LocalDynamic = false) {
12159 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12160 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12162 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12163 GA->getValueType(0),
12167 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12171 SDValue Ops[] = { Chain, TGA, *InFlag };
12172 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12174 SDValue Ops[] = { Chain, TGA };
12175 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12178 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12179 MFI->setAdjustsStack(true);
12181 SDValue Flag = Chain.getValue(1);
12182 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12185 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12187 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12190 SDLoc dl(GA); // ? function entry point might be better
12191 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12192 DAG.getNode(X86ISD::GlobalBaseReg,
12193 SDLoc(), PtrVT), InFlag);
12194 InFlag = Chain.getValue(1);
12196 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12199 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12201 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12203 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12204 X86::RAX, X86II::MO_TLSGD);
12207 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12213 // Get the start address of the TLS block for this module.
12214 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12215 .getInfo<X86MachineFunctionInfo>();
12216 MFI->incNumLocalDynamicTLSAccesses();
12220 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12221 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12224 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12225 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12226 InFlag = Chain.getValue(1);
12227 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12228 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12231 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12235 unsigned char OperandFlags = X86II::MO_DTPOFF;
12236 unsigned WrapperKind = X86ISD::Wrapper;
12237 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12238 GA->getValueType(0),
12239 GA->getOffset(), OperandFlags);
12240 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12242 // Add x@dtpoff with the base.
12243 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12246 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12247 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12248 const EVT PtrVT, TLSModel::Model model,
12249 bool is64Bit, bool isPIC) {
12252 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12253 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12254 is64Bit ? 257 : 256));
12256 SDValue ThreadPointer =
12257 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12258 MachinePointerInfo(Ptr), false, false, false, 0);
12260 unsigned char OperandFlags = 0;
12261 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12263 unsigned WrapperKind = X86ISD::Wrapper;
12264 if (model == TLSModel::LocalExec) {
12265 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12266 } else if (model == TLSModel::InitialExec) {
12268 OperandFlags = X86II::MO_GOTTPOFF;
12269 WrapperKind = X86ISD::WrapperRIP;
12271 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12274 llvm_unreachable("Unexpected model");
12277 // emit "addl x@ntpoff,%eax" (local exec)
12278 // or "addl x@indntpoff,%eax" (initial exec)
12279 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12281 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12282 GA->getOffset(), OperandFlags);
12283 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12285 if (model == TLSModel::InitialExec) {
12286 if (isPIC && !is64Bit) {
12287 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12288 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12292 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12293 MachinePointerInfo::getGOT(), false, false, false, 0);
12296 // The address of the thread local variable is the add of the thread
12297 // pointer with the offset of the variable.
12298 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12302 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12304 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12305 const GlobalValue *GV = GA->getGlobal();
12307 if (Subtarget->isTargetELF()) {
12308 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12311 case TLSModel::GeneralDynamic:
12312 if (Subtarget->is64Bit())
12313 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12314 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12315 case TLSModel::LocalDynamic:
12316 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12317 Subtarget->is64Bit());
12318 case TLSModel::InitialExec:
12319 case TLSModel::LocalExec:
12320 return LowerToTLSExecModel(
12321 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12322 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12324 llvm_unreachable("Unknown TLS model.");
12327 if (Subtarget->isTargetDarwin()) {
12328 // Darwin only has one model of TLS. Lower to that.
12329 unsigned char OpFlag = 0;
12330 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12331 X86ISD::WrapperRIP : X86ISD::Wrapper;
12333 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12334 // global base reg.
12335 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12336 !Subtarget->is64Bit();
12338 OpFlag = X86II::MO_TLVP_PIC_BASE;
12340 OpFlag = X86II::MO_TLVP;
12342 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12343 GA->getValueType(0),
12344 GA->getOffset(), OpFlag);
12345 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12347 // With PIC32, the address is actually $g + Offset.
12349 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12350 DAG.getNode(X86ISD::GlobalBaseReg,
12351 SDLoc(), getPointerTy()),
12354 // Lowering the machine isd will make sure everything is in the right
12356 SDValue Chain = DAG.getEntryNode();
12357 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12358 SDValue Args[] = { Chain, Offset };
12359 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12361 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12362 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12363 MFI->setAdjustsStack(true);
12365 // And our return value (tls address) is in the standard call return value
12367 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12368 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12369 Chain.getValue(1));
12372 if (Subtarget->isTargetKnownWindowsMSVC() ||
12373 Subtarget->isTargetWindowsGNU()) {
12374 // Just use the implicit TLS architecture
12375 // Need to generate someting similar to:
12376 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12378 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12379 // mov rcx, qword [rdx+rcx*8]
12380 // mov eax, .tls$:tlsvar
12381 // [rax+rcx] contains the address
12382 // Windows 64bit: gs:0x58
12383 // Windows 32bit: fs:__tls_array
12386 SDValue Chain = DAG.getEntryNode();
12388 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12389 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12390 // use its literal value of 0x2C.
12391 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12392 ? Type::getInt8PtrTy(*DAG.getContext(),
12394 : Type::getInt32PtrTy(*DAG.getContext(),
12398 Subtarget->is64Bit()
12399 ? DAG.getIntPtrConstant(0x58)
12400 : (Subtarget->isTargetWindowsGNU()
12401 ? DAG.getIntPtrConstant(0x2C)
12402 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12404 SDValue ThreadPointer =
12405 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12406 MachinePointerInfo(Ptr), false, false, false, 0);
12408 // Load the _tls_index variable
12409 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12410 if (Subtarget->is64Bit())
12411 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12412 IDX, MachinePointerInfo(), MVT::i32,
12413 false, false, false, 0);
12415 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12416 false, false, false, 0);
12418 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12420 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12422 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12423 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12424 false, false, false, 0);
12426 // Get the offset of start of .tls section
12427 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12428 GA->getValueType(0),
12429 GA->getOffset(), X86II::MO_SECREL);
12430 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12432 // The address of the thread local variable is the add of the thread
12433 // pointer with the offset of the variable.
12434 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12437 llvm_unreachable("TLS not implemented for this target.");
12440 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12441 /// and take a 2 x i32 value to shift plus a shift amount.
12442 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12443 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12444 MVT VT = Op.getSimpleValueType();
12445 unsigned VTBits = VT.getSizeInBits();
12447 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12448 SDValue ShOpLo = Op.getOperand(0);
12449 SDValue ShOpHi = Op.getOperand(1);
12450 SDValue ShAmt = Op.getOperand(2);
12451 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12452 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12454 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12455 DAG.getConstant(VTBits - 1, MVT::i8));
12456 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12457 DAG.getConstant(VTBits - 1, MVT::i8))
12458 : DAG.getConstant(0, VT);
12460 SDValue Tmp2, Tmp3;
12461 if (Op.getOpcode() == ISD::SHL_PARTS) {
12462 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12463 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12465 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12466 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12469 // If the shift amount is larger or equal than the width of a part we can't
12470 // rely on the results of shld/shrd. Insert a test and select the appropriate
12471 // values for large shift amounts.
12472 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12473 DAG.getConstant(VTBits, MVT::i8));
12474 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12475 AndNode, DAG.getConstant(0, MVT::i8));
12478 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12479 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12480 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12482 if (Op.getOpcode() == ISD::SHL_PARTS) {
12483 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12484 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12486 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12487 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12490 SDValue Ops[2] = { Lo, Hi };
12491 return DAG.getMergeValues(Ops, dl);
12494 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12495 SelectionDAG &DAG) const {
12496 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12498 if (SrcVT.isVector())
12501 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12502 "Unknown SINT_TO_FP to lower!");
12504 // These are really Legal; return the operand so the caller accepts it as
12506 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12508 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12509 Subtarget->is64Bit()) {
12514 unsigned Size = SrcVT.getSizeInBits()/8;
12515 MachineFunction &MF = DAG.getMachineFunction();
12516 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12517 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12518 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12520 MachinePointerInfo::getFixedStack(SSFI),
12522 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12525 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12527 SelectionDAG &DAG) const {
12531 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12533 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12535 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12537 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12539 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12540 MachineMemOperand *MMO;
12542 int SSFI = FI->getIndex();
12544 DAG.getMachineFunction()
12545 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12546 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12548 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12549 StackSlot = StackSlot.getOperand(1);
12551 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12552 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12554 Tys, Ops, SrcVT, MMO);
12557 Chain = Result.getValue(1);
12558 SDValue InFlag = Result.getValue(2);
12560 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12561 // shouldn't be necessary except that RFP cannot be live across
12562 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12563 MachineFunction &MF = DAG.getMachineFunction();
12564 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12565 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12566 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12567 Tys = DAG.getVTList(MVT::Other);
12569 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12571 MachineMemOperand *MMO =
12572 DAG.getMachineFunction()
12573 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12574 MachineMemOperand::MOStore, SSFISize, SSFISize);
12576 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12577 Ops, Op.getValueType(), MMO);
12578 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12579 MachinePointerInfo::getFixedStack(SSFI),
12580 false, false, false, 0);
12586 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12587 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12588 SelectionDAG &DAG) const {
12589 // This algorithm is not obvious. Here it is what we're trying to output:
12592 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12593 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12595 haddpd %xmm0, %xmm0
12597 pshufd $0x4e, %xmm0, %xmm1
12603 LLVMContext *Context = DAG.getContext();
12605 // Build some magic constants.
12606 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12607 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12608 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12610 SmallVector<Constant*,2> CV1;
12612 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12613 APInt(64, 0x4330000000000000ULL))));
12615 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12616 APInt(64, 0x4530000000000000ULL))));
12617 Constant *C1 = ConstantVector::get(CV1);
12618 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12620 // Load the 64-bit value into an XMM register.
12621 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12623 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12624 MachinePointerInfo::getConstantPool(),
12625 false, false, false, 16);
12626 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12627 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12630 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12631 MachinePointerInfo::getConstantPool(),
12632 false, false, false, 16);
12633 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12634 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12637 if (Subtarget->hasSSE3()) {
12638 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12639 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12641 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12642 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12644 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12645 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12649 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12650 DAG.getIntPtrConstant(0));
12653 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12654 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12655 SelectionDAG &DAG) const {
12657 // FP constant to bias correct the final result.
12658 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12661 // Load the 32-bit value into an XMM register.
12662 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12665 // Zero out the upper parts of the register.
12666 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12668 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12669 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12670 DAG.getIntPtrConstant(0));
12672 // Or the load with the bias.
12673 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12675 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12676 MVT::v2f64, Load)),
12677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12678 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12679 MVT::v2f64, Bias)));
12680 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12681 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12682 DAG.getIntPtrConstant(0));
12684 // Subtract the bias.
12685 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12687 // Handle final rounding.
12688 EVT DestVT = Op.getValueType();
12690 if (DestVT.bitsLT(MVT::f64))
12691 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12692 DAG.getIntPtrConstant(0));
12693 if (DestVT.bitsGT(MVT::f64))
12694 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12696 // Handle final rounding.
12700 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12701 SelectionDAG &DAG) const {
12702 SDValue N0 = Op.getOperand(0);
12703 MVT SVT = N0.getSimpleValueType();
12706 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12707 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12708 "Custom UINT_TO_FP is not supported!");
12710 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12711 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12712 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12715 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12716 SelectionDAG &DAG) const {
12717 SDValue N0 = Op.getOperand(0);
12720 if (Op.getValueType().isVector())
12721 return lowerUINT_TO_FP_vec(Op, DAG);
12723 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12724 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12725 // the optimization here.
12726 if (DAG.SignBitIsZero(N0))
12727 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12729 MVT SrcVT = N0.getSimpleValueType();
12730 MVT DstVT = Op.getSimpleValueType();
12731 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12732 return LowerUINT_TO_FP_i64(Op, DAG);
12733 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12734 return LowerUINT_TO_FP_i32(Op, DAG);
12735 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12738 // Make a 64-bit buffer, and use it to build an FILD.
12739 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12740 if (SrcVT == MVT::i32) {
12741 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12742 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12743 getPointerTy(), StackSlot, WordOff);
12744 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12745 StackSlot, MachinePointerInfo(),
12747 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12748 OffsetSlot, MachinePointerInfo(),
12750 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12754 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12755 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12756 StackSlot, MachinePointerInfo(),
12758 // For i64 source, we need to add the appropriate power of 2 if the input
12759 // was negative. This is the same as the optimization in
12760 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12761 // we must be careful to do the computation in x87 extended precision, not
12762 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12763 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12764 MachineMemOperand *MMO =
12765 DAG.getMachineFunction()
12766 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12767 MachineMemOperand::MOLoad, 8, 8);
12769 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12770 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12771 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12774 APInt FF(32, 0x5F800000ULL);
12776 // Check whether the sign bit is set.
12777 SDValue SignSet = DAG.getSetCC(dl,
12778 getSetCCResultType(*DAG.getContext(), MVT::i64),
12779 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12782 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12783 SDValue FudgePtr = DAG.getConstantPool(
12784 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12787 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12788 SDValue Zero = DAG.getIntPtrConstant(0);
12789 SDValue Four = DAG.getIntPtrConstant(4);
12790 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12792 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12794 // Load the value out, extending it from f32 to f80.
12795 // FIXME: Avoid the extend by constructing the right constant pool?
12796 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12797 FudgePtr, MachinePointerInfo::getConstantPool(),
12798 MVT::f32, false, false, false, 4);
12799 // Extend everything to 80 bits to force it to be done on x87.
12800 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12801 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12804 std::pair<SDValue,SDValue>
12805 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12806 bool IsSigned, bool IsReplace) const {
12809 EVT DstTy = Op.getValueType();
12811 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12812 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12816 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12817 DstTy.getSimpleVT() >= MVT::i16 &&
12818 "Unknown FP_TO_INT to lower!");
12820 // These are really Legal.
12821 if (DstTy == MVT::i32 &&
12822 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12823 return std::make_pair(SDValue(), SDValue());
12824 if (Subtarget->is64Bit() &&
12825 DstTy == MVT::i64 &&
12826 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12827 return std::make_pair(SDValue(), SDValue());
12829 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12830 // stack slot, or into the FTOL runtime function.
12831 MachineFunction &MF = DAG.getMachineFunction();
12832 unsigned MemSize = DstTy.getSizeInBits()/8;
12833 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12834 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12837 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12838 Opc = X86ISD::WIN_FTOL;
12840 switch (DstTy.getSimpleVT().SimpleTy) {
12841 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12842 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12843 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12844 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12847 SDValue Chain = DAG.getEntryNode();
12848 SDValue Value = Op.getOperand(0);
12849 EVT TheVT = Op.getOperand(0).getValueType();
12850 // FIXME This causes a redundant load/store if the SSE-class value is already
12851 // in memory, such as if it is on the callstack.
12852 if (isScalarFPTypeInSSEReg(TheVT)) {
12853 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12854 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12855 MachinePointerInfo::getFixedStack(SSFI),
12857 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12859 Chain, StackSlot, DAG.getValueType(TheVT)
12862 MachineMemOperand *MMO =
12863 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12864 MachineMemOperand::MOLoad, MemSize, MemSize);
12865 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12866 Chain = Value.getValue(1);
12867 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12868 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12871 MachineMemOperand *MMO =
12872 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12873 MachineMemOperand::MOStore, MemSize, MemSize);
12875 if (Opc != X86ISD::WIN_FTOL) {
12876 // Build the FP_TO_INT*_IN_MEM
12877 SDValue Ops[] = { Chain, Value, StackSlot };
12878 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12880 return std::make_pair(FIST, StackSlot);
12882 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12883 DAG.getVTList(MVT::Other, MVT::Glue),
12885 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12886 MVT::i32, ftol.getValue(1));
12887 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12888 MVT::i32, eax.getValue(2));
12889 SDValue Ops[] = { eax, edx };
12890 SDValue pair = IsReplace
12891 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12892 : DAG.getMergeValues(Ops, DL);
12893 return std::make_pair(pair, SDValue());
12897 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12898 const X86Subtarget *Subtarget) {
12899 MVT VT = Op->getSimpleValueType(0);
12900 SDValue In = Op->getOperand(0);
12901 MVT InVT = In.getSimpleValueType();
12904 // Optimize vectors in AVX mode:
12907 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12908 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12909 // Concat upper and lower parts.
12912 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12913 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12914 // Concat upper and lower parts.
12917 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12918 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12919 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12922 if (Subtarget->hasInt256())
12923 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12925 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12926 SDValue Undef = DAG.getUNDEF(InVT);
12927 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12928 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12929 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12931 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12932 VT.getVectorNumElements()/2);
12934 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12935 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12937 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12940 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12941 SelectionDAG &DAG) {
12942 MVT VT = Op->getSimpleValueType(0);
12943 SDValue In = Op->getOperand(0);
12944 MVT InVT = In.getSimpleValueType();
12946 unsigned int NumElts = VT.getVectorNumElements();
12947 if (NumElts != 8 && NumElts != 16)
12950 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12951 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12953 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12955 // Now we have only mask extension
12956 assert(InVT.getVectorElementType() == MVT::i1);
12957 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12958 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12959 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12960 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12961 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12962 MachinePointerInfo::getConstantPool(),
12963 false, false, false, Alignment);
12965 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12966 if (VT.is512BitVector())
12968 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12971 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12972 SelectionDAG &DAG) {
12973 if (Subtarget->hasFp256()) {
12974 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12982 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12983 SelectionDAG &DAG) {
12985 MVT VT = Op.getSimpleValueType();
12986 SDValue In = Op.getOperand(0);
12987 MVT SVT = In.getSimpleValueType();
12989 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12990 return LowerZERO_EXTEND_AVX512(Op, DAG);
12992 if (Subtarget->hasFp256()) {
12993 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12998 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12999 VT.getVectorNumElements() != SVT.getVectorNumElements());
13003 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13005 MVT VT = Op.getSimpleValueType();
13006 SDValue In = Op.getOperand(0);
13007 MVT InVT = In.getSimpleValueType();
13009 if (VT == MVT::i1) {
13010 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13011 "Invalid scalar TRUNCATE operation");
13012 if (InVT.getSizeInBits() >= 32)
13014 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13015 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13017 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13018 "Invalid TRUNCATE operation");
13020 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13021 if (VT.getVectorElementType().getSizeInBits() >=8)
13022 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13024 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13025 unsigned NumElts = InVT.getVectorNumElements();
13026 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13027 if (InVT.getSizeInBits() < 512) {
13028 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13029 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13033 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13034 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13035 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13036 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13037 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13038 MachinePointerInfo::getConstantPool(),
13039 false, false, false, Alignment);
13040 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13041 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13042 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13045 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13046 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13047 if (Subtarget->hasInt256()) {
13048 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13049 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13050 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13052 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13053 DAG.getIntPtrConstant(0));
13056 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13057 DAG.getIntPtrConstant(0));
13058 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13059 DAG.getIntPtrConstant(2));
13060 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13061 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13062 static const int ShufMask[] = {0, 2, 4, 6};
13063 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13066 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13067 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13068 if (Subtarget->hasInt256()) {
13069 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13071 SmallVector<SDValue,32> pshufbMask;
13072 for (unsigned i = 0; i < 2; ++i) {
13073 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13074 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13075 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13076 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13077 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13078 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13079 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13080 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13081 for (unsigned j = 0; j < 8; ++j)
13082 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13084 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13085 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13086 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13088 static const int ShufMask[] = {0, 2, -1, -1};
13089 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13091 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13092 DAG.getIntPtrConstant(0));
13093 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13096 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13097 DAG.getIntPtrConstant(0));
13099 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13100 DAG.getIntPtrConstant(4));
13102 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13103 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13105 // The PSHUFB mask:
13106 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13107 -1, -1, -1, -1, -1, -1, -1, -1};
13109 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13110 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13111 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13113 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13114 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13116 // The MOVLHPS Mask:
13117 static const int ShufMask2[] = {0, 1, 4, 5};
13118 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13119 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13122 // Handle truncation of V256 to V128 using shuffles.
13123 if (!VT.is128BitVector() || !InVT.is256BitVector())
13126 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13128 unsigned NumElems = VT.getVectorNumElements();
13129 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13131 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13132 // Prepare truncation shuffle mask
13133 for (unsigned i = 0; i != NumElems; ++i)
13134 MaskVec[i] = i * 2;
13135 SDValue V = DAG.getVectorShuffle(NVT, DL,
13136 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13137 DAG.getUNDEF(NVT), &MaskVec[0]);
13138 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13139 DAG.getIntPtrConstant(0));
13142 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13143 SelectionDAG &DAG) const {
13144 assert(!Op.getSimpleValueType().isVector());
13146 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13147 /*IsSigned=*/ true, /*IsReplace=*/ false);
13148 SDValue FIST = Vals.first, StackSlot = Vals.second;
13149 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13150 if (!FIST.getNode()) return Op;
13152 if (StackSlot.getNode())
13153 // Load the result.
13154 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13155 FIST, StackSlot, MachinePointerInfo(),
13156 false, false, false, 0);
13158 // The node is the result.
13162 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13163 SelectionDAG &DAG) const {
13164 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13165 /*IsSigned=*/ false, /*IsReplace=*/ false);
13166 SDValue FIST = Vals.first, StackSlot = Vals.second;
13167 assert(FIST.getNode() && "Unexpected failure");
13169 if (StackSlot.getNode())
13170 // Load the result.
13171 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13172 FIST, StackSlot, MachinePointerInfo(),
13173 false, false, false, 0);
13175 // The node is the result.
13179 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13181 MVT VT = Op.getSimpleValueType();
13182 SDValue In = Op.getOperand(0);
13183 MVT SVT = In.getSimpleValueType();
13185 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13187 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13188 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13189 In, DAG.getUNDEF(SVT)));
13192 // The only differences between FABS and FNEG are the mask and the logic op.
13193 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13194 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13195 "Wrong opcode for lowering FABS or FNEG.");
13197 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13199 MVT VT = Op.getSimpleValueType();
13200 // Assume scalar op for initialization; update for vector if needed.
13201 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13202 // generate a 16-byte vector constant and logic op even for the scalar case.
13203 // Using a 16-byte mask allows folding the load of the mask with
13204 // the logic op, so it can save (~4 bytes) on code size.
13206 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13207 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13208 // decide if we should generate a 16-byte constant mask when we only need 4 or
13209 // 8 bytes for the scalar case.
13210 if (VT.isVector()) {
13211 EltVT = VT.getVectorElementType();
13212 NumElts = VT.getVectorNumElements();
13215 unsigned EltBits = EltVT.getSizeInBits();
13216 LLVMContext *Context = DAG.getContext();
13217 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13219 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13220 Constant *C = ConstantInt::get(*Context, MaskElt);
13221 C = ConstantVector::getSplat(NumElts, C);
13222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13223 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13224 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13225 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13226 MachinePointerInfo::getConstantPool(),
13227 false, false, false, Alignment);
13229 if (VT.isVector()) {
13230 // For a vector, cast operands to a vector type, perform the logic op,
13231 // and cast the result back to the original value type.
13232 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13233 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13234 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13235 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13236 return DAG.getNode(ISD::BITCAST, dl, VT,
13237 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13239 // If not vector, then scalar.
13240 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13241 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13244 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13246 LLVMContext *Context = DAG.getContext();
13247 SDValue Op0 = Op.getOperand(0);
13248 SDValue Op1 = Op.getOperand(1);
13250 MVT VT = Op.getSimpleValueType();
13251 MVT SrcVT = Op1.getSimpleValueType();
13253 // If second operand is smaller, extend it first.
13254 if (SrcVT.bitsLT(VT)) {
13255 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13258 // And if it is bigger, shrink it first.
13259 if (SrcVT.bitsGT(VT)) {
13260 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13264 // At this point the operands and the result should have the same
13265 // type, and that won't be f80 since that is not custom lowered.
13267 // First get the sign bit of second operand.
13268 SmallVector<Constant*,4> CV;
13269 if (SrcVT == MVT::f64) {
13270 const fltSemantics &Sem = APFloat::IEEEdouble;
13271 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13272 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13274 const fltSemantics &Sem = APFloat::IEEEsingle;
13275 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13276 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13277 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13278 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13280 Constant *C = ConstantVector::get(CV);
13281 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13282 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13283 MachinePointerInfo::getConstantPool(),
13284 false, false, false, 16);
13285 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13287 // Shift sign bit right or left if the two operands have different types.
13288 if (SrcVT.bitsGT(VT)) {
13289 // Op0 is MVT::f32, Op1 is MVT::f64.
13290 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13291 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13292 DAG.getConstant(32, MVT::i32));
13293 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13294 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13295 DAG.getIntPtrConstant(0));
13298 // Clear first operand sign bit.
13300 if (VT == MVT::f64) {
13301 const fltSemantics &Sem = APFloat::IEEEdouble;
13302 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13303 APInt(64, ~(1ULL << 63)))));
13304 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13306 const fltSemantics &Sem = APFloat::IEEEsingle;
13307 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13308 APInt(32, ~(1U << 31)))));
13309 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13310 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13311 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13313 C = ConstantVector::get(CV);
13314 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13315 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13316 MachinePointerInfo::getConstantPool(),
13317 false, false, false, 16);
13318 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13320 // Or the value with the sign bit.
13321 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13324 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13325 SDValue N0 = Op.getOperand(0);
13327 MVT VT = Op.getSimpleValueType();
13329 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13330 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13331 DAG.getConstant(1, VT));
13332 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13335 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13337 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13338 SelectionDAG &DAG) {
13339 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13341 if (!Subtarget->hasSSE41())
13344 if (!Op->hasOneUse())
13347 SDNode *N = Op.getNode();
13350 SmallVector<SDValue, 8> Opnds;
13351 DenseMap<SDValue, unsigned> VecInMap;
13352 SmallVector<SDValue, 8> VecIns;
13353 EVT VT = MVT::Other;
13355 // Recognize a special case where a vector is casted into wide integer to
13357 Opnds.push_back(N->getOperand(0));
13358 Opnds.push_back(N->getOperand(1));
13360 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13361 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13362 // BFS traverse all OR'd operands.
13363 if (I->getOpcode() == ISD::OR) {
13364 Opnds.push_back(I->getOperand(0));
13365 Opnds.push_back(I->getOperand(1));
13366 // Re-evaluate the number of nodes to be traversed.
13367 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13371 // Quit if a non-EXTRACT_VECTOR_ELT
13372 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13375 // Quit if without a constant index.
13376 SDValue Idx = I->getOperand(1);
13377 if (!isa<ConstantSDNode>(Idx))
13380 SDValue ExtractedFromVec = I->getOperand(0);
13381 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13382 if (M == VecInMap.end()) {
13383 VT = ExtractedFromVec.getValueType();
13384 // Quit if not 128/256-bit vector.
13385 if (!VT.is128BitVector() && !VT.is256BitVector())
13387 // Quit if not the same type.
13388 if (VecInMap.begin() != VecInMap.end() &&
13389 VT != VecInMap.begin()->first.getValueType())
13391 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13392 VecIns.push_back(ExtractedFromVec);
13394 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13397 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13398 "Not extracted from 128-/256-bit vector.");
13400 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13402 for (DenseMap<SDValue, unsigned>::const_iterator
13403 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13404 // Quit if not all elements are used.
13405 if (I->second != FullMask)
13409 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13411 // Cast all vectors into TestVT for PTEST.
13412 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13413 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13415 // If more than one full vectors are evaluated, OR them first before PTEST.
13416 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13417 // Each iteration will OR 2 nodes and append the result until there is only
13418 // 1 node left, i.e. the final OR'd value of all vectors.
13419 SDValue LHS = VecIns[Slot];
13420 SDValue RHS = VecIns[Slot + 1];
13421 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13424 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13425 VecIns.back(), VecIns.back());
13428 /// \brief return true if \c Op has a use that doesn't just read flags.
13429 static bool hasNonFlagsUse(SDValue Op) {
13430 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13432 SDNode *User = *UI;
13433 unsigned UOpNo = UI.getOperandNo();
13434 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13435 // Look pass truncate.
13436 UOpNo = User->use_begin().getOperandNo();
13437 User = *User->use_begin();
13440 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13441 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13447 /// Emit nodes that will be selected as "test Op0,Op0", or something
13449 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13450 SelectionDAG &DAG) const {
13451 if (Op.getValueType() == MVT::i1)
13452 // KORTEST instruction should be selected
13453 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13454 DAG.getConstant(0, Op.getValueType()));
13456 // CF and OF aren't always set the way we want. Determine which
13457 // of these we need.
13458 bool NeedCF = false;
13459 bool NeedOF = false;
13462 case X86::COND_A: case X86::COND_AE:
13463 case X86::COND_B: case X86::COND_BE:
13466 case X86::COND_G: case X86::COND_GE:
13467 case X86::COND_L: case X86::COND_LE:
13468 case X86::COND_O: case X86::COND_NO: {
13469 // Check if we really need to set the
13470 // Overflow flag. If NoSignedWrap is present
13471 // that is not actually needed.
13472 switch (Op->getOpcode()) {
13477 const BinaryWithFlagsSDNode *BinNode =
13478 cast<BinaryWithFlagsSDNode>(Op.getNode());
13479 if (BinNode->hasNoSignedWrap())
13489 // See if we can use the EFLAGS value from the operand instead of
13490 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13491 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13492 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13493 // Emit a CMP with 0, which is the TEST pattern.
13494 //if (Op.getValueType() == MVT::i1)
13495 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13496 // DAG.getConstant(0, MVT::i1));
13497 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13498 DAG.getConstant(0, Op.getValueType()));
13500 unsigned Opcode = 0;
13501 unsigned NumOperands = 0;
13503 // Truncate operations may prevent the merge of the SETCC instruction
13504 // and the arithmetic instruction before it. Attempt to truncate the operands
13505 // of the arithmetic instruction and use a reduced bit-width instruction.
13506 bool NeedTruncation = false;
13507 SDValue ArithOp = Op;
13508 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13509 SDValue Arith = Op->getOperand(0);
13510 // Both the trunc and the arithmetic op need to have one user each.
13511 if (Arith->hasOneUse())
13512 switch (Arith.getOpcode()) {
13519 NeedTruncation = true;
13525 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13526 // which may be the result of a CAST. We use the variable 'Op', which is the
13527 // non-casted variable when we check for possible users.
13528 switch (ArithOp.getOpcode()) {
13530 // Due to an isel shortcoming, be conservative if this add is likely to be
13531 // selected as part of a load-modify-store instruction. When the root node
13532 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13533 // uses of other nodes in the match, such as the ADD in this case. This
13534 // leads to the ADD being left around and reselected, with the result being
13535 // two adds in the output. Alas, even if none our users are stores, that
13536 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13537 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13538 // climbing the DAG back to the root, and it doesn't seem to be worth the
13540 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13541 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13542 if (UI->getOpcode() != ISD::CopyToReg &&
13543 UI->getOpcode() != ISD::SETCC &&
13544 UI->getOpcode() != ISD::STORE)
13547 if (ConstantSDNode *C =
13548 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13549 // An add of one will be selected as an INC.
13550 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13551 Opcode = X86ISD::INC;
13556 // An add of negative one (subtract of one) will be selected as a DEC.
13557 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13558 Opcode = X86ISD::DEC;
13564 // Otherwise use a regular EFLAGS-setting add.
13565 Opcode = X86ISD::ADD;
13570 // If we have a constant logical shift that's only used in a comparison
13571 // against zero turn it into an equivalent AND. This allows turning it into
13572 // a TEST instruction later.
13573 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13574 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13575 EVT VT = Op.getValueType();
13576 unsigned BitWidth = VT.getSizeInBits();
13577 unsigned ShAmt = Op->getConstantOperandVal(1);
13578 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13580 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13581 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13582 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13583 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13585 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13586 DAG.getConstant(Mask, VT));
13587 DAG.ReplaceAllUsesWith(Op, New);
13593 // If the primary and result isn't used, don't bother using X86ISD::AND,
13594 // because a TEST instruction will be better.
13595 if (!hasNonFlagsUse(Op))
13601 // Due to the ISEL shortcoming noted above, be conservative if this op is
13602 // likely to be selected as part of a load-modify-store instruction.
13603 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13604 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13605 if (UI->getOpcode() == ISD::STORE)
13608 // Otherwise use a regular EFLAGS-setting instruction.
13609 switch (ArithOp.getOpcode()) {
13610 default: llvm_unreachable("unexpected operator!");
13611 case ISD::SUB: Opcode = X86ISD::SUB; break;
13612 case ISD::XOR: Opcode = X86ISD::XOR; break;
13613 case ISD::AND: Opcode = X86ISD::AND; break;
13615 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13616 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13617 if (EFLAGS.getNode())
13620 Opcode = X86ISD::OR;
13634 return SDValue(Op.getNode(), 1);
13640 // If we found that truncation is beneficial, perform the truncation and
13642 if (NeedTruncation) {
13643 EVT VT = Op.getValueType();
13644 SDValue WideVal = Op->getOperand(0);
13645 EVT WideVT = WideVal.getValueType();
13646 unsigned ConvertedOp = 0;
13647 // Use a target machine opcode to prevent further DAGCombine
13648 // optimizations that may separate the arithmetic operations
13649 // from the setcc node.
13650 switch (WideVal.getOpcode()) {
13652 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13653 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13654 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13655 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13656 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13661 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13662 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13663 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13664 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13670 // Emit a CMP with 0, which is the TEST pattern.
13671 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13672 DAG.getConstant(0, Op.getValueType()));
13674 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13675 SmallVector<SDValue, 4> Ops;
13676 for (unsigned i = 0; i != NumOperands; ++i)
13677 Ops.push_back(Op.getOperand(i));
13679 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13680 DAG.ReplaceAllUsesWith(Op, New);
13681 return SDValue(New.getNode(), 1);
13684 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13686 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13687 SDLoc dl, SelectionDAG &DAG) const {
13688 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13689 if (C->getAPIntValue() == 0)
13690 return EmitTest(Op0, X86CC, dl, DAG);
13692 if (Op0.getValueType() == MVT::i1)
13693 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13696 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13697 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13698 // Do the comparison at i32 if it's smaller, besides the Atom case.
13699 // This avoids subregister aliasing issues. Keep the smaller reference
13700 // if we're optimizing for size, however, as that'll allow better folding
13701 // of memory operations.
13702 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13703 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13704 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13705 !Subtarget->isAtom()) {
13706 unsigned ExtendOp =
13707 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13708 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13709 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13711 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13712 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13713 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13715 return SDValue(Sub.getNode(), 1);
13717 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13720 /// Convert a comparison if required by the subtarget.
13721 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13722 SelectionDAG &DAG) const {
13723 // If the subtarget does not support the FUCOMI instruction, floating-point
13724 // comparisons have to be converted.
13725 if (Subtarget->hasCMov() ||
13726 Cmp.getOpcode() != X86ISD::CMP ||
13727 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13728 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13731 // The instruction selector will select an FUCOM instruction instead of
13732 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13733 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13734 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13736 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13737 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13738 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13739 DAG.getConstant(8, MVT::i8));
13740 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13741 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13744 static bool isAllOnes(SDValue V) {
13745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13746 return C && C->isAllOnesValue();
13749 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13750 /// if it's possible.
13751 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13752 SDLoc dl, SelectionDAG &DAG) const {
13753 SDValue Op0 = And.getOperand(0);
13754 SDValue Op1 = And.getOperand(1);
13755 if (Op0.getOpcode() == ISD::TRUNCATE)
13756 Op0 = Op0.getOperand(0);
13757 if (Op1.getOpcode() == ISD::TRUNCATE)
13758 Op1 = Op1.getOperand(0);
13761 if (Op1.getOpcode() == ISD::SHL)
13762 std::swap(Op0, Op1);
13763 if (Op0.getOpcode() == ISD::SHL) {
13764 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13765 if (And00C->getZExtValue() == 1) {
13766 // If we looked past a truncate, check that it's only truncating away
13768 unsigned BitWidth = Op0.getValueSizeInBits();
13769 unsigned AndBitWidth = And.getValueSizeInBits();
13770 if (BitWidth > AndBitWidth) {
13772 DAG.computeKnownBits(Op0, Zeros, Ones);
13773 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13777 RHS = Op0.getOperand(1);
13779 } else if (Op1.getOpcode() == ISD::Constant) {
13780 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13781 uint64_t AndRHSVal = AndRHS->getZExtValue();
13782 SDValue AndLHS = Op0;
13784 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13785 LHS = AndLHS.getOperand(0);
13786 RHS = AndLHS.getOperand(1);
13789 // Use BT if the immediate can't be encoded in a TEST instruction.
13790 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13792 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13796 if (LHS.getNode()) {
13797 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13798 // instruction. Since the shift amount is in-range-or-undefined, we know
13799 // that doing a bittest on the i32 value is ok. We extend to i32 because
13800 // the encoding for the i16 version is larger than the i32 version.
13801 // Also promote i16 to i32 for performance / code size reason.
13802 if (LHS.getValueType() == MVT::i8 ||
13803 LHS.getValueType() == MVT::i16)
13804 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13806 // If the operand types disagree, extend the shift amount to match. Since
13807 // BT ignores high bits (like shifts) we can use anyextend.
13808 if (LHS.getValueType() != RHS.getValueType())
13809 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13811 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13812 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13813 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13814 DAG.getConstant(Cond, MVT::i8), BT);
13820 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13822 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13827 // SSE Condition code mapping:
13836 switch (SetCCOpcode) {
13837 default: llvm_unreachable("Unexpected SETCC condition");
13839 case ISD::SETEQ: SSECC = 0; break;
13841 case ISD::SETGT: Swap = true; // Fallthrough
13843 case ISD::SETOLT: SSECC = 1; break;
13845 case ISD::SETGE: Swap = true; // Fallthrough
13847 case ISD::SETOLE: SSECC = 2; break;
13848 case ISD::SETUO: SSECC = 3; break;
13850 case ISD::SETNE: SSECC = 4; break;
13851 case ISD::SETULE: Swap = true; // Fallthrough
13852 case ISD::SETUGE: SSECC = 5; break;
13853 case ISD::SETULT: Swap = true; // Fallthrough
13854 case ISD::SETUGT: SSECC = 6; break;
13855 case ISD::SETO: SSECC = 7; break;
13857 case ISD::SETONE: SSECC = 8; break;
13860 std::swap(Op0, Op1);
13865 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13866 // ones, and then concatenate the result back.
13867 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13868 MVT VT = Op.getSimpleValueType();
13870 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13871 "Unsupported value type for operation");
13873 unsigned NumElems = VT.getVectorNumElements();
13875 SDValue CC = Op.getOperand(2);
13877 // Extract the LHS vectors
13878 SDValue LHS = Op.getOperand(0);
13879 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13880 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13882 // Extract the RHS vectors
13883 SDValue RHS = Op.getOperand(1);
13884 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13885 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13887 // Issue the operation on the smaller types and concatenate the result back
13888 MVT EltVT = VT.getVectorElementType();
13889 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13890 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13891 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13892 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13895 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13896 const X86Subtarget *Subtarget) {
13897 SDValue Op0 = Op.getOperand(0);
13898 SDValue Op1 = Op.getOperand(1);
13899 SDValue CC = Op.getOperand(2);
13900 MVT VT = Op.getSimpleValueType();
13903 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13904 Op.getValueType().getScalarType() == MVT::i1 &&
13905 "Cannot set masked compare for this operation");
13907 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13909 bool Unsigned = false;
13912 switch (SetCCOpcode) {
13913 default: llvm_unreachable("Unexpected SETCC condition");
13914 case ISD::SETNE: SSECC = 4; break;
13915 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13916 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13917 case ISD::SETLT: Swap = true; //fall-through
13918 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13919 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13920 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13921 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13922 case ISD::SETULE: Unsigned = true; //fall-through
13923 case ISD::SETLE: SSECC = 2; break;
13927 std::swap(Op0, Op1);
13929 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13930 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13931 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13932 DAG.getConstant(SSECC, MVT::i8));
13935 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13936 /// operand \p Op1. If non-trivial (for example because it's not constant)
13937 /// return an empty value.
13938 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13940 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13944 MVT VT = Op1.getSimpleValueType();
13945 MVT EVT = VT.getVectorElementType();
13946 unsigned n = VT.getVectorNumElements();
13947 SmallVector<SDValue, 8> ULTOp1;
13949 for (unsigned i = 0; i < n; ++i) {
13950 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13951 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13954 // Avoid underflow.
13955 APInt Val = Elt->getAPIntValue();
13959 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13962 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13965 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13966 SelectionDAG &DAG) {
13967 SDValue Op0 = Op.getOperand(0);
13968 SDValue Op1 = Op.getOperand(1);
13969 SDValue CC = Op.getOperand(2);
13970 MVT VT = Op.getSimpleValueType();
13971 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13972 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13977 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13978 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13981 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13982 unsigned Opc = X86ISD::CMPP;
13983 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13984 assert(VT.getVectorNumElements() <= 16);
13985 Opc = X86ISD::CMPM;
13987 // In the two special cases we can't handle, emit two comparisons.
13990 unsigned CombineOpc;
13991 if (SetCCOpcode == ISD::SETUEQ) {
13992 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13994 assert(SetCCOpcode == ISD::SETONE);
13995 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13998 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13999 DAG.getConstant(CC0, MVT::i8));
14000 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14001 DAG.getConstant(CC1, MVT::i8));
14002 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14004 // Handle all other FP comparisons here.
14005 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14006 DAG.getConstant(SSECC, MVT::i8));
14009 // Break 256-bit integer vector compare into smaller ones.
14010 if (VT.is256BitVector() && !Subtarget->hasInt256())
14011 return Lower256IntVSETCC(Op, DAG);
14013 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14014 EVT OpVT = Op1.getValueType();
14015 if (Subtarget->hasAVX512()) {
14016 if (Op1.getValueType().is512BitVector() ||
14017 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14018 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14019 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14021 // In AVX-512 architecture setcc returns mask with i1 elements,
14022 // But there is no compare instruction for i8 and i16 elements in KNL.
14023 // We are not talking about 512-bit operands in this case, these
14024 // types are illegal.
14026 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14027 OpVT.getVectorElementType().getSizeInBits() >= 8))
14028 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14029 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14032 // We are handling one of the integer comparisons here. Since SSE only has
14033 // GT and EQ comparisons for integer, swapping operands and multiple
14034 // operations may be required for some comparisons.
14036 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14037 bool Subus = false;
14039 switch (SetCCOpcode) {
14040 default: llvm_unreachable("Unexpected SETCC condition");
14041 case ISD::SETNE: Invert = true;
14042 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14043 case ISD::SETLT: Swap = true;
14044 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14045 case ISD::SETGE: Swap = true;
14046 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14047 Invert = true; break;
14048 case ISD::SETULT: Swap = true;
14049 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14050 FlipSigns = true; break;
14051 case ISD::SETUGE: Swap = true;
14052 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14053 FlipSigns = true; Invert = true; break;
14056 // Special case: Use min/max operations for SETULE/SETUGE
14057 MVT VET = VT.getVectorElementType();
14059 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14060 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14063 switch (SetCCOpcode) {
14065 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14066 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14069 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14072 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14073 if (!MinMax && hasSubus) {
14074 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14076 // t = psubus Op0, Op1
14077 // pcmpeq t, <0..0>
14078 switch (SetCCOpcode) {
14080 case ISD::SETULT: {
14081 // If the comparison is against a constant we can turn this into a
14082 // setule. With psubus, setule does not require a swap. This is
14083 // beneficial because the constant in the register is no longer
14084 // destructed as the destination so it can be hoisted out of a loop.
14085 // Only do this pre-AVX since vpcmp* is no longer destructive.
14086 if (Subtarget->hasAVX())
14088 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14089 if (ULEOp1.getNode()) {
14091 Subus = true; Invert = false; Swap = false;
14095 // Psubus is better than flip-sign because it requires no inversion.
14096 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14097 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14101 Opc = X86ISD::SUBUS;
14107 std::swap(Op0, Op1);
14109 // Check that the operation in question is available (most are plain SSE2,
14110 // but PCMPGTQ and PCMPEQQ have different requirements).
14111 if (VT == MVT::v2i64) {
14112 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14113 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14115 // First cast everything to the right type.
14116 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14117 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14119 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14120 // bits of the inputs before performing those operations. The lower
14121 // compare is always unsigned.
14124 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14126 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14127 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14128 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14129 Sign, Zero, Sign, Zero);
14131 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14132 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14134 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14135 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14136 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14138 // Create masks for only the low parts/high parts of the 64 bit integers.
14139 static const int MaskHi[] = { 1, 1, 3, 3 };
14140 static const int MaskLo[] = { 0, 0, 2, 2 };
14141 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14142 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14143 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14145 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14146 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14149 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14151 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14154 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14155 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14156 // pcmpeqd + pshufd + pand.
14157 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14159 // First cast everything to the right type.
14160 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14161 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14164 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14166 // Make sure the lower and upper halves are both all-ones.
14167 static const int Mask[] = { 1, 0, 3, 2 };
14168 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14169 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14172 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14174 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14178 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14179 // bits of the inputs before performing those operations.
14181 EVT EltVT = VT.getVectorElementType();
14182 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14183 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14184 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14187 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14189 // If the logical-not of the result is required, perform that now.
14191 Result = DAG.getNOT(dl, Result, VT);
14194 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14197 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14198 getZeroVector(VT, Subtarget, DAG, dl));
14203 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14205 MVT VT = Op.getSimpleValueType();
14207 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14209 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14210 && "SetCC type must be 8-bit or 1-bit integer");
14211 SDValue Op0 = Op.getOperand(0);
14212 SDValue Op1 = Op.getOperand(1);
14214 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14216 // Optimize to BT if possible.
14217 // Lower (X & (1 << N)) == 0 to BT(X, N).
14218 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14219 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14220 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14221 Op1.getOpcode() == ISD::Constant &&
14222 cast<ConstantSDNode>(Op1)->isNullValue() &&
14223 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14224 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14225 if (NewSetCC.getNode())
14229 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14231 if (Op1.getOpcode() == ISD::Constant &&
14232 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14233 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14234 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14236 // If the input is a setcc, then reuse the input setcc or use a new one with
14237 // the inverted condition.
14238 if (Op0.getOpcode() == X86ISD::SETCC) {
14239 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14240 bool Invert = (CC == ISD::SETNE) ^
14241 cast<ConstantSDNode>(Op1)->isNullValue();
14245 CCode = X86::GetOppositeBranchCondition(CCode);
14246 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14247 DAG.getConstant(CCode, MVT::i8),
14248 Op0.getOperand(1));
14250 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14254 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14255 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14256 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14258 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14259 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14262 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14263 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14264 if (X86CC == X86::COND_INVALID)
14267 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14268 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14269 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14270 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14272 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14276 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14277 static bool isX86LogicalCmp(SDValue Op) {
14278 unsigned Opc = Op.getNode()->getOpcode();
14279 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14280 Opc == X86ISD::SAHF)
14282 if (Op.getResNo() == 1 &&
14283 (Opc == X86ISD::ADD ||
14284 Opc == X86ISD::SUB ||
14285 Opc == X86ISD::ADC ||
14286 Opc == X86ISD::SBB ||
14287 Opc == X86ISD::SMUL ||
14288 Opc == X86ISD::UMUL ||
14289 Opc == X86ISD::INC ||
14290 Opc == X86ISD::DEC ||
14291 Opc == X86ISD::OR ||
14292 Opc == X86ISD::XOR ||
14293 Opc == X86ISD::AND))
14296 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14302 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14303 if (V.getOpcode() != ISD::TRUNCATE)
14306 SDValue VOp0 = V.getOperand(0);
14307 unsigned InBits = VOp0.getValueSizeInBits();
14308 unsigned Bits = V.getValueSizeInBits();
14309 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14312 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14313 bool addTest = true;
14314 SDValue Cond = Op.getOperand(0);
14315 SDValue Op1 = Op.getOperand(1);
14316 SDValue Op2 = Op.getOperand(2);
14318 EVT VT = Op1.getValueType();
14321 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14322 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14323 // sequence later on.
14324 if (Cond.getOpcode() == ISD::SETCC &&
14325 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14326 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14327 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14328 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14329 int SSECC = translateX86FSETCC(
14330 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14333 if (Subtarget->hasAVX512()) {
14334 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14335 DAG.getConstant(SSECC, MVT::i8));
14336 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14338 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14339 DAG.getConstant(SSECC, MVT::i8));
14340 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14341 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14342 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14346 if (Cond.getOpcode() == ISD::SETCC) {
14347 SDValue NewCond = LowerSETCC(Cond, DAG);
14348 if (NewCond.getNode())
14352 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14353 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14354 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14355 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14356 if (Cond.getOpcode() == X86ISD::SETCC &&
14357 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14358 isZero(Cond.getOperand(1).getOperand(1))) {
14359 SDValue Cmp = Cond.getOperand(1);
14361 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14363 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14364 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14365 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14367 SDValue CmpOp0 = Cmp.getOperand(0);
14368 // Apply further optimizations for special cases
14369 // (select (x != 0), -1, 0) -> neg & sbb
14370 // (select (x == 0), 0, -1) -> neg & sbb
14371 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14372 if (YC->isNullValue() &&
14373 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14374 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14375 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14376 DAG.getConstant(0, CmpOp0.getValueType()),
14378 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14379 DAG.getConstant(X86::COND_B, MVT::i8),
14380 SDValue(Neg.getNode(), 1));
14384 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14385 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14386 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14388 SDValue Res = // Res = 0 or -1.
14389 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14390 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14392 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14393 Res = DAG.getNOT(DL, Res, Res.getValueType());
14395 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14396 if (!N2C || !N2C->isNullValue())
14397 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14402 // Look past (and (setcc_carry (cmp ...)), 1).
14403 if (Cond.getOpcode() == ISD::AND &&
14404 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14405 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14406 if (C && C->getAPIntValue() == 1)
14407 Cond = Cond.getOperand(0);
14410 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14411 // setting operand in place of the X86ISD::SETCC.
14412 unsigned CondOpcode = Cond.getOpcode();
14413 if (CondOpcode == X86ISD::SETCC ||
14414 CondOpcode == X86ISD::SETCC_CARRY) {
14415 CC = Cond.getOperand(0);
14417 SDValue Cmp = Cond.getOperand(1);
14418 unsigned Opc = Cmp.getOpcode();
14419 MVT VT = Op.getSimpleValueType();
14421 bool IllegalFPCMov = false;
14422 if (VT.isFloatingPoint() && !VT.isVector() &&
14423 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14424 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14426 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14427 Opc == X86ISD::BT) { // FIXME
14431 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14432 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14433 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14434 Cond.getOperand(0).getValueType() != MVT::i8)) {
14435 SDValue LHS = Cond.getOperand(0);
14436 SDValue RHS = Cond.getOperand(1);
14437 unsigned X86Opcode;
14440 switch (CondOpcode) {
14441 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14442 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14443 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14444 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14445 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14446 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14447 default: llvm_unreachable("unexpected overflowing operator");
14449 if (CondOpcode == ISD::UMULO)
14450 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14453 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14455 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14457 if (CondOpcode == ISD::UMULO)
14458 Cond = X86Op.getValue(2);
14460 Cond = X86Op.getValue(1);
14462 CC = DAG.getConstant(X86Cond, MVT::i8);
14467 // Look pass the truncate if the high bits are known zero.
14468 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14469 Cond = Cond.getOperand(0);
14471 // We know the result of AND is compared against zero. Try to match
14473 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14474 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14475 if (NewSetCC.getNode()) {
14476 CC = NewSetCC.getOperand(0);
14477 Cond = NewSetCC.getOperand(1);
14484 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14485 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14488 // a < b ? -1 : 0 -> RES = ~setcc_carry
14489 // a < b ? 0 : -1 -> RES = setcc_carry
14490 // a >= b ? -1 : 0 -> RES = setcc_carry
14491 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14492 if (Cond.getOpcode() == X86ISD::SUB) {
14493 Cond = ConvertCmpIfNecessary(Cond, DAG);
14494 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14496 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14497 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14498 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14499 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14500 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14501 return DAG.getNOT(DL, Res, Res.getValueType());
14506 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14507 // widen the cmov and push the truncate through. This avoids introducing a new
14508 // branch during isel and doesn't add any extensions.
14509 if (Op.getValueType() == MVT::i8 &&
14510 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14511 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14512 if (T1.getValueType() == T2.getValueType() &&
14513 // Blacklist CopyFromReg to avoid partial register stalls.
14514 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14515 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14516 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14517 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14521 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14522 // condition is true.
14523 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14524 SDValue Ops[] = { Op2, Op1, CC, Cond };
14525 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14528 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14529 MVT VT = Op->getSimpleValueType(0);
14530 SDValue In = Op->getOperand(0);
14531 MVT InVT = In.getSimpleValueType();
14534 unsigned int NumElts = VT.getVectorNumElements();
14535 if (NumElts != 8 && NumElts != 16)
14538 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14539 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14542 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14544 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14545 Constant *C = ConstantInt::get(*DAG.getContext(),
14546 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14548 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14549 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14550 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14551 MachinePointerInfo::getConstantPool(),
14552 false, false, false, Alignment);
14553 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14554 if (VT.is512BitVector())
14556 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14559 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14560 SelectionDAG &DAG) {
14561 MVT VT = Op->getSimpleValueType(0);
14562 SDValue In = Op->getOperand(0);
14563 MVT InVT = In.getSimpleValueType();
14566 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14567 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14569 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14570 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14571 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14574 if (Subtarget->hasInt256())
14575 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14577 // Optimize vectors in AVX mode
14578 // Sign extend v8i16 to v8i32 and
14581 // Divide input vector into two parts
14582 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14583 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14584 // concat the vectors to original VT
14586 unsigned NumElems = InVT.getVectorNumElements();
14587 SDValue Undef = DAG.getUNDEF(InVT);
14589 SmallVector<int,8> ShufMask1(NumElems, -1);
14590 for (unsigned i = 0; i != NumElems/2; ++i)
14593 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14595 SmallVector<int,8> ShufMask2(NumElems, -1);
14596 for (unsigned i = 0; i != NumElems/2; ++i)
14597 ShufMask2[i] = i + NumElems/2;
14599 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14601 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14602 VT.getVectorNumElements()/2);
14604 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14605 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14607 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14610 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14611 // may emit an illegal shuffle but the expansion is still better than scalar
14612 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14613 // we'll emit a shuffle and a arithmetic shift.
14614 // TODO: It is possible to support ZExt by zeroing the undef values during
14615 // the shuffle phase or after the shuffle.
14616 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14617 SelectionDAG &DAG) {
14618 MVT RegVT = Op.getSimpleValueType();
14619 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14620 assert(RegVT.isInteger() &&
14621 "We only custom lower integer vector sext loads.");
14623 // Nothing useful we can do without SSE2 shuffles.
14624 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14626 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14628 EVT MemVT = Ld->getMemoryVT();
14629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14630 unsigned RegSz = RegVT.getSizeInBits();
14632 ISD::LoadExtType Ext = Ld->getExtensionType();
14634 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14635 && "Only anyext and sext are currently implemented.");
14636 assert(MemVT != RegVT && "Cannot extend to the same type");
14637 assert(MemVT.isVector() && "Must load a vector from memory");
14639 unsigned NumElems = RegVT.getVectorNumElements();
14640 unsigned MemSz = MemVT.getSizeInBits();
14641 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14643 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14644 // The only way in which we have a legal 256-bit vector result but not the
14645 // integer 256-bit operations needed to directly lower a sextload is if we
14646 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14647 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14648 // correctly legalized. We do this late to allow the canonical form of
14649 // sextload to persist throughout the rest of the DAG combiner -- it wants
14650 // to fold together any extensions it can, and so will fuse a sign_extend
14651 // of an sextload into a sextload targeting a wider value.
14653 if (MemSz == 128) {
14654 // Just switch this to a normal load.
14655 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14656 "it must be a legal 128-bit vector "
14658 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14659 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14660 Ld->isInvariant(), Ld->getAlignment());
14662 assert(MemSz < 128 &&
14663 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14664 // Do an sext load to a 128-bit vector type. We want to use the same
14665 // number of elements, but elements half as wide. This will end up being
14666 // recursively lowered by this routine, but will succeed as we definitely
14667 // have all the necessary features if we're using AVX1.
14669 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14670 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14672 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14673 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14674 Ld->isNonTemporal(), Ld->isInvariant(),
14675 Ld->getAlignment());
14678 // Replace chain users with the new chain.
14679 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14680 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14682 // Finally, do a normal sign-extend to the desired register.
14683 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14686 // All sizes must be a power of two.
14687 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14688 "Non-power-of-two elements are not custom lowered!");
14690 // Attempt to load the original value using scalar loads.
14691 // Find the largest scalar type that divides the total loaded size.
14692 MVT SclrLoadTy = MVT::i8;
14693 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14694 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14695 MVT Tp = (MVT::SimpleValueType)tp;
14696 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14701 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14702 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14704 SclrLoadTy = MVT::f64;
14706 // Calculate the number of scalar loads that we need to perform
14707 // in order to load our vector from memory.
14708 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14710 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14711 "Can only lower sext loads with a single scalar load!");
14713 unsigned loadRegZize = RegSz;
14714 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14717 // Represent our vector as a sequence of elements which are the
14718 // largest scalar that we can load.
14719 EVT LoadUnitVecVT = EVT::getVectorVT(
14720 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14722 // Represent the data using the same element type that is stored in
14723 // memory. In practice, we ''widen'' MemVT.
14725 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14726 loadRegZize / MemVT.getScalarType().getSizeInBits());
14728 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14729 "Invalid vector type");
14731 // We can't shuffle using an illegal type.
14732 assert(TLI.isTypeLegal(WideVecVT) &&
14733 "We only lower types that form legal widened vector types");
14735 SmallVector<SDValue, 8> Chains;
14736 SDValue Ptr = Ld->getBasePtr();
14737 SDValue Increment =
14738 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14739 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14741 for (unsigned i = 0; i < NumLoads; ++i) {
14742 // Perform a single load.
14743 SDValue ScalarLoad =
14744 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14745 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14746 Ld->getAlignment());
14747 Chains.push_back(ScalarLoad.getValue(1));
14748 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14749 // another round of DAGCombining.
14751 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14753 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14754 ScalarLoad, DAG.getIntPtrConstant(i));
14756 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14759 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14761 // Bitcast the loaded value to a vector of the original element type, in
14762 // the size of the target vector type.
14763 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14764 unsigned SizeRatio = RegSz / MemSz;
14766 if (Ext == ISD::SEXTLOAD) {
14767 // If we have SSE4.1, we can directly emit a VSEXT node.
14768 if (Subtarget->hasSSE41()) {
14769 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14770 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14774 // Otherwise we'll shuffle the small elements in the high bits of the
14775 // larger type and perform an arithmetic shift. If the shift is not legal
14776 // it's better to scalarize.
14777 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14778 "We can't implement a sext load without an arithmetic right shift!");
14780 // Redistribute the loaded elements into the different locations.
14781 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14782 for (unsigned i = 0; i != NumElems; ++i)
14783 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14785 SDValue Shuff = DAG.getVectorShuffle(
14786 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14788 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14790 // Build the arithmetic shift.
14791 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14792 MemVT.getVectorElementType().getSizeInBits();
14794 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14796 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14800 // Redistribute the loaded elements into the different locations.
14801 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14802 for (unsigned i = 0; i != NumElems; ++i)
14803 ShuffleVec[i * SizeRatio] = i;
14805 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14806 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14808 // Bitcast to the requested type.
14809 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14810 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14814 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14815 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14816 // from the AND / OR.
14817 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14818 Opc = Op.getOpcode();
14819 if (Opc != ISD::OR && Opc != ISD::AND)
14821 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14822 Op.getOperand(0).hasOneUse() &&
14823 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14824 Op.getOperand(1).hasOneUse());
14827 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14828 // 1 and that the SETCC node has a single use.
14829 static bool isXor1OfSetCC(SDValue Op) {
14830 if (Op.getOpcode() != ISD::XOR)
14832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14833 if (N1C && N1C->getAPIntValue() == 1) {
14834 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14835 Op.getOperand(0).hasOneUse();
14840 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14841 bool addTest = true;
14842 SDValue Chain = Op.getOperand(0);
14843 SDValue Cond = Op.getOperand(1);
14844 SDValue Dest = Op.getOperand(2);
14847 bool Inverted = false;
14849 if (Cond.getOpcode() == ISD::SETCC) {
14850 // Check for setcc([su]{add,sub,mul}o == 0).
14851 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14852 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14853 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14854 Cond.getOperand(0).getResNo() == 1 &&
14855 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14856 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14857 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14858 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14859 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14860 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14862 Cond = Cond.getOperand(0);
14864 SDValue NewCond = LowerSETCC(Cond, DAG);
14865 if (NewCond.getNode())
14870 // FIXME: LowerXALUO doesn't handle these!!
14871 else if (Cond.getOpcode() == X86ISD::ADD ||
14872 Cond.getOpcode() == X86ISD::SUB ||
14873 Cond.getOpcode() == X86ISD::SMUL ||
14874 Cond.getOpcode() == X86ISD::UMUL)
14875 Cond = LowerXALUO(Cond, DAG);
14878 // Look pass (and (setcc_carry (cmp ...)), 1).
14879 if (Cond.getOpcode() == ISD::AND &&
14880 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14881 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14882 if (C && C->getAPIntValue() == 1)
14883 Cond = Cond.getOperand(0);
14886 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14887 // setting operand in place of the X86ISD::SETCC.
14888 unsigned CondOpcode = Cond.getOpcode();
14889 if (CondOpcode == X86ISD::SETCC ||
14890 CondOpcode == X86ISD::SETCC_CARRY) {
14891 CC = Cond.getOperand(0);
14893 SDValue Cmp = Cond.getOperand(1);
14894 unsigned Opc = Cmp.getOpcode();
14895 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14896 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14900 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14904 // These can only come from an arithmetic instruction with overflow,
14905 // e.g. SADDO, UADDO.
14906 Cond = Cond.getNode()->getOperand(1);
14912 CondOpcode = Cond.getOpcode();
14913 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14914 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14915 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14916 Cond.getOperand(0).getValueType() != MVT::i8)) {
14917 SDValue LHS = Cond.getOperand(0);
14918 SDValue RHS = Cond.getOperand(1);
14919 unsigned X86Opcode;
14922 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14923 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14925 switch (CondOpcode) {
14926 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14928 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14930 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14933 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14934 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14938 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14941 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14942 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14943 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14944 default: llvm_unreachable("unexpected overflowing operator");
14947 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14948 if (CondOpcode == ISD::UMULO)
14949 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14952 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14954 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14956 if (CondOpcode == ISD::UMULO)
14957 Cond = X86Op.getValue(2);
14959 Cond = X86Op.getValue(1);
14961 CC = DAG.getConstant(X86Cond, MVT::i8);
14965 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14966 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14967 if (CondOpc == ISD::OR) {
14968 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14969 // two branches instead of an explicit OR instruction with a
14971 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14972 isX86LogicalCmp(Cmp)) {
14973 CC = Cond.getOperand(0).getOperand(0);
14974 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14975 Chain, Dest, CC, Cmp);
14976 CC = Cond.getOperand(1).getOperand(0);
14980 } else { // ISD::AND
14981 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14982 // two branches instead of an explicit AND instruction with a
14983 // separate test. However, we only do this if this block doesn't
14984 // have a fall-through edge, because this requires an explicit
14985 // jmp when the condition is false.
14986 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14987 isX86LogicalCmp(Cmp) &&
14988 Op.getNode()->hasOneUse()) {
14989 X86::CondCode CCode =
14990 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14991 CCode = X86::GetOppositeBranchCondition(CCode);
14992 CC = DAG.getConstant(CCode, MVT::i8);
14993 SDNode *User = *Op.getNode()->use_begin();
14994 // Look for an unconditional branch following this conditional branch.
14995 // We need this because we need to reverse the successors in order
14996 // to implement FCMP_OEQ.
14997 if (User->getOpcode() == ISD::BR) {
14998 SDValue FalseBB = User->getOperand(1);
15000 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15001 assert(NewBR == User);
15005 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15006 Chain, Dest, CC, Cmp);
15007 X86::CondCode CCode =
15008 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15009 CCode = X86::GetOppositeBranchCondition(CCode);
15010 CC = DAG.getConstant(CCode, MVT::i8);
15016 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15017 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15018 // It should be transformed during dag combiner except when the condition
15019 // is set by a arithmetics with overflow node.
15020 X86::CondCode CCode =
15021 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15022 CCode = X86::GetOppositeBranchCondition(CCode);
15023 CC = DAG.getConstant(CCode, MVT::i8);
15024 Cond = Cond.getOperand(0).getOperand(1);
15026 } else if (Cond.getOpcode() == ISD::SETCC &&
15027 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15028 // For FCMP_OEQ, we can emit
15029 // two branches instead of an explicit AND instruction with a
15030 // separate test. However, we only do this if this block doesn't
15031 // have a fall-through edge, because this requires an explicit
15032 // jmp when the condition is false.
15033 if (Op.getNode()->hasOneUse()) {
15034 SDNode *User = *Op.getNode()->use_begin();
15035 // Look for an unconditional branch following this conditional branch.
15036 // We need this because we need to reverse the successors in order
15037 // to implement FCMP_OEQ.
15038 if (User->getOpcode() == ISD::BR) {
15039 SDValue FalseBB = User->getOperand(1);
15041 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15042 assert(NewBR == User);
15046 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15047 Cond.getOperand(0), Cond.getOperand(1));
15048 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15049 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15050 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15051 Chain, Dest, CC, Cmp);
15052 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15057 } else if (Cond.getOpcode() == ISD::SETCC &&
15058 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15059 // For FCMP_UNE, we can emit
15060 // two branches instead of an explicit AND instruction with a
15061 // separate test. However, we only do this if this block doesn't
15062 // have a fall-through edge, because this requires an explicit
15063 // jmp when the condition is false.
15064 if (Op.getNode()->hasOneUse()) {
15065 SDNode *User = *Op.getNode()->use_begin();
15066 // Look for an unconditional branch following this conditional branch.
15067 // We need this because we need to reverse the successors in order
15068 // to implement FCMP_UNE.
15069 if (User->getOpcode() == ISD::BR) {
15070 SDValue FalseBB = User->getOperand(1);
15072 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15073 assert(NewBR == User);
15076 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15077 Cond.getOperand(0), Cond.getOperand(1));
15078 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15079 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15080 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15081 Chain, Dest, CC, Cmp);
15082 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15092 // Look pass the truncate if the high bits are known zero.
15093 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15094 Cond = Cond.getOperand(0);
15096 // We know the result of AND is compared against zero. Try to match
15098 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15099 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15100 if (NewSetCC.getNode()) {
15101 CC = NewSetCC.getOperand(0);
15102 Cond = NewSetCC.getOperand(1);
15109 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15110 CC = DAG.getConstant(X86Cond, MVT::i8);
15111 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15113 Cond = ConvertCmpIfNecessary(Cond, DAG);
15114 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15115 Chain, Dest, CC, Cond);
15118 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15119 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15120 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15121 // that the guard pages used by the OS virtual memory manager are allocated in
15122 // correct sequence.
15124 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15125 SelectionDAG &DAG) const {
15126 MachineFunction &MF = DAG.getMachineFunction();
15127 bool SplitStack = MF.shouldSplitStack();
15128 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15134 SDNode* Node = Op.getNode();
15136 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15137 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15138 " not tell us which reg is the stack pointer!");
15139 EVT VT = Node->getValueType(0);
15140 SDValue Tmp1 = SDValue(Node, 0);
15141 SDValue Tmp2 = SDValue(Node, 1);
15142 SDValue Tmp3 = Node->getOperand(2);
15143 SDValue Chain = Tmp1.getOperand(0);
15145 // Chain the dynamic stack allocation so that it doesn't modify the stack
15146 // pointer when other instructions are using the stack.
15147 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15150 SDValue Size = Tmp2.getOperand(1);
15151 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15152 Chain = SP.getValue(1);
15153 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15154 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15155 unsigned StackAlign = TFI.getStackAlignment();
15156 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15157 if (Align > StackAlign)
15158 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15159 DAG.getConstant(-(uint64_t)Align, VT));
15160 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15162 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15163 DAG.getIntPtrConstant(0, true), SDValue(),
15166 SDValue Ops[2] = { Tmp1, Tmp2 };
15167 return DAG.getMergeValues(Ops, dl);
15171 SDValue Chain = Op.getOperand(0);
15172 SDValue Size = Op.getOperand(1);
15173 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15174 EVT VT = Op.getNode()->getValueType(0);
15176 bool Is64Bit = Subtarget->is64Bit();
15177 EVT SPTy = getPointerTy();
15180 MachineRegisterInfo &MRI = MF.getRegInfo();
15183 // The 64 bit implementation of segmented stacks needs to clobber both r10
15184 // r11. This makes it impossible to use it along with nested parameters.
15185 const Function *F = MF.getFunction();
15187 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15189 if (I->hasNestAttr())
15190 report_fatal_error("Cannot use segmented stacks with functions that "
15191 "have nested arguments.");
15194 const TargetRegisterClass *AddrRegClass =
15195 getRegClassFor(getPointerTy());
15196 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15197 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15198 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15199 DAG.getRegister(Vreg, SPTy));
15200 SDValue Ops1[2] = { Value, Chain };
15201 return DAG.getMergeValues(Ops1, dl);
15204 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15206 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15207 Flag = Chain.getValue(1);
15208 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15210 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15212 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15213 DAG.getSubtarget().getRegisterInfo());
15214 unsigned SPReg = RegInfo->getStackRegister();
15215 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15216 Chain = SP.getValue(1);
15219 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15220 DAG.getConstant(-(uint64_t)Align, VT));
15221 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15224 SDValue Ops1[2] = { SP, Chain };
15225 return DAG.getMergeValues(Ops1, dl);
15229 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15230 MachineFunction &MF = DAG.getMachineFunction();
15231 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15233 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15236 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15237 // vastart just stores the address of the VarArgsFrameIndex slot into the
15238 // memory location argument.
15239 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15241 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15242 MachinePointerInfo(SV), false, false, 0);
15246 // gp_offset (0 - 6 * 8)
15247 // fp_offset (48 - 48 + 8 * 16)
15248 // overflow_arg_area (point to parameters coming in memory).
15250 SmallVector<SDValue, 8> MemOps;
15251 SDValue FIN = Op.getOperand(1);
15253 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15254 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15256 FIN, MachinePointerInfo(SV), false, false, 0);
15257 MemOps.push_back(Store);
15260 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15261 FIN, DAG.getIntPtrConstant(4));
15262 Store = DAG.getStore(Op.getOperand(0), DL,
15263 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15265 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15266 MemOps.push_back(Store);
15268 // Store ptr to overflow_arg_area
15269 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15270 FIN, DAG.getIntPtrConstant(4));
15271 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15273 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15274 MachinePointerInfo(SV, 8),
15276 MemOps.push_back(Store);
15278 // Store ptr to reg_save_area.
15279 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15280 FIN, DAG.getIntPtrConstant(8));
15281 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15283 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15284 MachinePointerInfo(SV, 16), false, false, 0);
15285 MemOps.push_back(Store);
15286 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15289 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15290 assert(Subtarget->is64Bit() &&
15291 "LowerVAARG only handles 64-bit va_arg!");
15292 assert((Subtarget->isTargetLinux() ||
15293 Subtarget->isTargetDarwin()) &&
15294 "Unhandled target in LowerVAARG");
15295 assert(Op.getNode()->getNumOperands() == 4);
15296 SDValue Chain = Op.getOperand(0);
15297 SDValue SrcPtr = Op.getOperand(1);
15298 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15299 unsigned Align = Op.getConstantOperandVal(3);
15302 EVT ArgVT = Op.getNode()->getValueType(0);
15303 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15304 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15307 // Decide which area this value should be read from.
15308 // TODO: Implement the AMD64 ABI in its entirety. This simple
15309 // selection mechanism works only for the basic types.
15310 if (ArgVT == MVT::f80) {
15311 llvm_unreachable("va_arg for f80 not yet implemented");
15312 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15313 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15314 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15315 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15317 llvm_unreachable("Unhandled argument type in LowerVAARG");
15320 if (ArgMode == 2) {
15321 // Sanity Check: Make sure using fp_offset makes sense.
15322 assert(!DAG.getTarget().Options.UseSoftFloat &&
15323 !(DAG.getMachineFunction()
15324 .getFunction()->getAttributes()
15325 .hasAttribute(AttributeSet::FunctionIndex,
15326 Attribute::NoImplicitFloat)) &&
15327 Subtarget->hasSSE1());
15330 // Insert VAARG_64 node into the DAG
15331 // VAARG_64 returns two values: Variable Argument Address, Chain
15332 SmallVector<SDValue, 11> InstOps;
15333 InstOps.push_back(Chain);
15334 InstOps.push_back(SrcPtr);
15335 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15336 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15337 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15338 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15339 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15340 VTs, InstOps, MVT::i64,
15341 MachinePointerInfo(SV),
15343 /*Volatile=*/false,
15345 /*WriteMem=*/true);
15346 Chain = VAARG.getValue(1);
15348 // Load the next argument and return it
15349 return DAG.getLoad(ArgVT, dl,
15352 MachinePointerInfo(),
15353 false, false, false, 0);
15356 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15357 SelectionDAG &DAG) {
15358 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15359 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15360 SDValue Chain = Op.getOperand(0);
15361 SDValue DstPtr = Op.getOperand(1);
15362 SDValue SrcPtr = Op.getOperand(2);
15363 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15364 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15367 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15368 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15370 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15373 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15374 // amount is a constant. Takes immediate version of shift as input.
15375 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15376 SDValue SrcOp, uint64_t ShiftAmt,
15377 SelectionDAG &DAG) {
15378 MVT ElementType = VT.getVectorElementType();
15380 // Fold this packed shift into its first operand if ShiftAmt is 0.
15384 // Check for ShiftAmt >= element width
15385 if (ShiftAmt >= ElementType.getSizeInBits()) {
15386 if (Opc == X86ISD::VSRAI)
15387 ShiftAmt = ElementType.getSizeInBits() - 1;
15389 return DAG.getConstant(0, VT);
15392 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15393 && "Unknown target vector shift-by-constant node");
15395 // Fold this packed vector shift into a build vector if SrcOp is a
15396 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15397 if (VT == SrcOp.getSimpleValueType() &&
15398 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15399 SmallVector<SDValue, 8> Elts;
15400 unsigned NumElts = SrcOp->getNumOperands();
15401 ConstantSDNode *ND;
15404 default: llvm_unreachable(nullptr);
15405 case X86ISD::VSHLI:
15406 for (unsigned i=0; i!=NumElts; ++i) {
15407 SDValue CurrentOp = SrcOp->getOperand(i);
15408 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15409 Elts.push_back(CurrentOp);
15412 ND = cast<ConstantSDNode>(CurrentOp);
15413 const APInt &C = ND->getAPIntValue();
15414 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15417 case X86ISD::VSRLI:
15418 for (unsigned i=0; i!=NumElts; ++i) {
15419 SDValue CurrentOp = SrcOp->getOperand(i);
15420 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15421 Elts.push_back(CurrentOp);
15424 ND = cast<ConstantSDNode>(CurrentOp);
15425 const APInt &C = ND->getAPIntValue();
15426 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15429 case X86ISD::VSRAI:
15430 for (unsigned i=0; i!=NumElts; ++i) {
15431 SDValue CurrentOp = SrcOp->getOperand(i);
15432 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15433 Elts.push_back(CurrentOp);
15436 ND = cast<ConstantSDNode>(CurrentOp);
15437 const APInt &C = ND->getAPIntValue();
15438 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15443 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15446 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15449 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15450 // may or may not be a constant. Takes immediate version of shift as input.
15451 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15452 SDValue SrcOp, SDValue ShAmt,
15453 SelectionDAG &DAG) {
15454 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15456 // Catch shift-by-constant.
15457 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15458 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15459 CShAmt->getZExtValue(), DAG);
15461 // Change opcode to non-immediate version
15463 default: llvm_unreachable("Unknown target vector shift node");
15464 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15465 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15466 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15469 // Need to build a vector containing shift amount
15470 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15473 ShOps[1] = DAG.getConstant(0, MVT::i32);
15474 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15475 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15477 // The return type has to be a 128-bit type with the same element
15478 // type as the input type.
15479 MVT EltVT = VT.getVectorElementType();
15480 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15482 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15483 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15486 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15487 /// necessary casting for \p Mask when lowering masking intrinsics.
15488 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15489 SDValue PreservedSrc, SelectionDAG &DAG) {
15490 EVT VT = Op.getValueType();
15491 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15492 MVT::i1, VT.getVectorNumElements());
15495 assert(MaskVT.isSimple() && "invalid mask type");
15496 return DAG.getNode(ISD::VSELECT, dl, VT,
15497 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15501 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15503 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15504 case Intrinsic::x86_fma_vfmadd_ps:
15505 case Intrinsic::x86_fma_vfmadd_pd:
15506 case Intrinsic::x86_fma_vfmadd_ps_256:
15507 case Intrinsic::x86_fma_vfmadd_pd_256:
15508 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15509 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15510 return X86ISD::FMADD;
15511 case Intrinsic::x86_fma_vfmsub_ps:
15512 case Intrinsic::x86_fma_vfmsub_pd:
15513 case Intrinsic::x86_fma_vfmsub_ps_256:
15514 case Intrinsic::x86_fma_vfmsub_pd_256:
15515 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15516 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15517 return X86ISD::FMSUB;
15518 case Intrinsic::x86_fma_vfnmadd_ps:
15519 case Intrinsic::x86_fma_vfnmadd_pd:
15520 case Intrinsic::x86_fma_vfnmadd_ps_256:
15521 case Intrinsic::x86_fma_vfnmadd_pd_256:
15522 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15523 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15524 return X86ISD::FNMADD;
15525 case Intrinsic::x86_fma_vfnmsub_ps:
15526 case Intrinsic::x86_fma_vfnmsub_pd:
15527 case Intrinsic::x86_fma_vfnmsub_ps_256:
15528 case Intrinsic::x86_fma_vfnmsub_pd_256:
15529 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15530 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15531 return X86ISD::FNMSUB;
15532 case Intrinsic::x86_fma_vfmaddsub_ps:
15533 case Intrinsic::x86_fma_vfmaddsub_pd:
15534 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15535 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15536 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15537 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15538 return X86ISD::FMADDSUB;
15539 case Intrinsic::x86_fma_vfmsubadd_ps:
15540 case Intrinsic::x86_fma_vfmsubadd_pd:
15541 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15542 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15543 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15544 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15545 return X86ISD::FMSUBADD;
15549 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15551 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15553 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15555 switch(IntrData->Type) {
15556 case INTR_TYPE_1OP:
15557 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15558 case INTR_TYPE_2OP:
15559 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15561 case INTR_TYPE_3OP:
15562 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15563 Op.getOperand(2), Op.getOperand(3));
15564 case COMI: { // Comparison intrinsics
15565 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15566 SDValue LHS = Op.getOperand(1);
15567 SDValue RHS = Op.getOperand(2);
15568 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15569 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15570 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15571 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15572 DAG.getConstant(X86CC, MVT::i8), Cond);
15573 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15576 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15577 Op.getOperand(1), Op.getOperand(2), DAG);
15584 default: return SDValue(); // Don't custom lower most intrinsics.
15586 // Arithmetic intrinsics.
15587 case Intrinsic::x86_sse2_pmulu_dq:
15588 case Intrinsic::x86_avx2_pmulu_dq:
15589 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15590 Op.getOperand(1), Op.getOperand(2));
15592 case Intrinsic::x86_sse41_pmuldq:
15593 case Intrinsic::x86_avx2_pmul_dq:
15594 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15595 Op.getOperand(1), Op.getOperand(2));
15597 case Intrinsic::x86_sse2_pmulhu_w:
15598 case Intrinsic::x86_avx2_pmulhu_w:
15599 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15600 Op.getOperand(1), Op.getOperand(2));
15602 case Intrinsic::x86_sse2_pmulh_w:
15603 case Intrinsic::x86_avx2_pmulh_w:
15604 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15605 Op.getOperand(1), Op.getOperand(2));
15607 // SSE/SSE2/AVX floating point max/min intrinsics.
15608 case Intrinsic::x86_sse_max_ps:
15609 case Intrinsic::x86_sse2_max_pd:
15610 case Intrinsic::x86_avx_max_ps_256:
15611 case Intrinsic::x86_avx_max_pd_256:
15612 case Intrinsic::x86_sse_min_ps:
15613 case Intrinsic::x86_sse2_min_pd:
15614 case Intrinsic::x86_avx_min_ps_256:
15615 case Intrinsic::x86_avx_min_pd_256: {
15618 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15619 case Intrinsic::x86_sse_max_ps:
15620 case Intrinsic::x86_sse2_max_pd:
15621 case Intrinsic::x86_avx_max_ps_256:
15622 case Intrinsic::x86_avx_max_pd_256:
15623 Opcode = X86ISD::FMAX;
15625 case Intrinsic::x86_sse_min_ps:
15626 case Intrinsic::x86_sse2_min_pd:
15627 case Intrinsic::x86_avx_min_ps_256:
15628 case Intrinsic::x86_avx_min_pd_256:
15629 Opcode = X86ISD::FMIN;
15632 return DAG.getNode(Opcode, dl, Op.getValueType(),
15633 Op.getOperand(1), Op.getOperand(2));
15636 // AVX2 variable shift intrinsics
15637 case Intrinsic::x86_avx2_psllv_d:
15638 case Intrinsic::x86_avx2_psllv_q:
15639 case Intrinsic::x86_avx2_psllv_d_256:
15640 case Intrinsic::x86_avx2_psllv_q_256:
15641 case Intrinsic::x86_avx2_psrlv_d:
15642 case Intrinsic::x86_avx2_psrlv_q:
15643 case Intrinsic::x86_avx2_psrlv_d_256:
15644 case Intrinsic::x86_avx2_psrlv_q_256:
15645 case Intrinsic::x86_avx2_psrav_d:
15646 case Intrinsic::x86_avx2_psrav_d_256: {
15649 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15650 case Intrinsic::x86_avx2_psllv_d:
15651 case Intrinsic::x86_avx2_psllv_q:
15652 case Intrinsic::x86_avx2_psllv_d_256:
15653 case Intrinsic::x86_avx2_psllv_q_256:
15656 case Intrinsic::x86_avx2_psrlv_d:
15657 case Intrinsic::x86_avx2_psrlv_q:
15658 case Intrinsic::x86_avx2_psrlv_d_256:
15659 case Intrinsic::x86_avx2_psrlv_q_256:
15662 case Intrinsic::x86_avx2_psrav_d:
15663 case Intrinsic::x86_avx2_psrav_d_256:
15667 return DAG.getNode(Opcode, dl, Op.getValueType(),
15668 Op.getOperand(1), Op.getOperand(2));
15671 case Intrinsic::x86_sse2_packssdw_128:
15672 case Intrinsic::x86_sse2_packsswb_128:
15673 case Intrinsic::x86_avx2_packssdw:
15674 case Intrinsic::x86_avx2_packsswb:
15675 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15676 Op.getOperand(1), Op.getOperand(2));
15678 case Intrinsic::x86_sse2_packuswb_128:
15679 case Intrinsic::x86_sse41_packusdw:
15680 case Intrinsic::x86_avx2_packuswb:
15681 case Intrinsic::x86_avx2_packusdw:
15682 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15683 Op.getOperand(1), Op.getOperand(2));
15685 case Intrinsic::x86_ssse3_pshuf_b_128:
15686 case Intrinsic::x86_avx2_pshuf_b:
15687 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15688 Op.getOperand(1), Op.getOperand(2));
15690 case Intrinsic::x86_sse2_pshuf_d:
15691 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15692 Op.getOperand(1), Op.getOperand(2));
15694 case Intrinsic::x86_sse2_pshufl_w:
15695 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15696 Op.getOperand(1), Op.getOperand(2));
15698 case Intrinsic::x86_sse2_pshufh_w:
15699 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15700 Op.getOperand(1), Op.getOperand(2));
15702 case Intrinsic::x86_ssse3_psign_b_128:
15703 case Intrinsic::x86_ssse3_psign_w_128:
15704 case Intrinsic::x86_ssse3_psign_d_128:
15705 case Intrinsic::x86_avx2_psign_b:
15706 case Intrinsic::x86_avx2_psign_w:
15707 case Intrinsic::x86_avx2_psign_d:
15708 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15709 Op.getOperand(1), Op.getOperand(2));
15711 case Intrinsic::x86_avx2_permd:
15712 case Intrinsic::x86_avx2_permps:
15713 // Operands intentionally swapped. Mask is last operand to intrinsic,
15714 // but second operand for node/instruction.
15715 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15716 Op.getOperand(2), Op.getOperand(1));
15718 case Intrinsic::x86_avx512_mask_valign_q_512:
15719 case Intrinsic::x86_avx512_mask_valign_d_512:
15720 // Vector source operands are swapped.
15721 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15722 Op.getValueType(), Op.getOperand(2),
15725 Op.getOperand(5), Op.getOperand(4), DAG);
15727 // ptest and testp intrinsics. The intrinsic these come from are designed to
15728 // return an integer value, not just an instruction so lower it to the ptest
15729 // or testp pattern and a setcc for the result.
15730 case Intrinsic::x86_sse41_ptestz:
15731 case Intrinsic::x86_sse41_ptestc:
15732 case Intrinsic::x86_sse41_ptestnzc:
15733 case Intrinsic::x86_avx_ptestz_256:
15734 case Intrinsic::x86_avx_ptestc_256:
15735 case Intrinsic::x86_avx_ptestnzc_256:
15736 case Intrinsic::x86_avx_vtestz_ps:
15737 case Intrinsic::x86_avx_vtestc_ps:
15738 case Intrinsic::x86_avx_vtestnzc_ps:
15739 case Intrinsic::x86_avx_vtestz_pd:
15740 case Intrinsic::x86_avx_vtestc_pd:
15741 case Intrinsic::x86_avx_vtestnzc_pd:
15742 case Intrinsic::x86_avx_vtestz_ps_256:
15743 case Intrinsic::x86_avx_vtestc_ps_256:
15744 case Intrinsic::x86_avx_vtestnzc_ps_256:
15745 case Intrinsic::x86_avx_vtestz_pd_256:
15746 case Intrinsic::x86_avx_vtestc_pd_256:
15747 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15748 bool IsTestPacked = false;
15751 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15752 case Intrinsic::x86_avx_vtestz_ps:
15753 case Intrinsic::x86_avx_vtestz_pd:
15754 case Intrinsic::x86_avx_vtestz_ps_256:
15755 case Intrinsic::x86_avx_vtestz_pd_256:
15756 IsTestPacked = true; // Fallthrough
15757 case Intrinsic::x86_sse41_ptestz:
15758 case Intrinsic::x86_avx_ptestz_256:
15760 X86CC = X86::COND_E;
15762 case Intrinsic::x86_avx_vtestc_ps:
15763 case Intrinsic::x86_avx_vtestc_pd:
15764 case Intrinsic::x86_avx_vtestc_ps_256:
15765 case Intrinsic::x86_avx_vtestc_pd_256:
15766 IsTestPacked = true; // Fallthrough
15767 case Intrinsic::x86_sse41_ptestc:
15768 case Intrinsic::x86_avx_ptestc_256:
15770 X86CC = X86::COND_B;
15772 case Intrinsic::x86_avx_vtestnzc_ps:
15773 case Intrinsic::x86_avx_vtestnzc_pd:
15774 case Intrinsic::x86_avx_vtestnzc_ps_256:
15775 case Intrinsic::x86_avx_vtestnzc_pd_256:
15776 IsTestPacked = true; // Fallthrough
15777 case Intrinsic::x86_sse41_ptestnzc:
15778 case Intrinsic::x86_avx_ptestnzc_256:
15780 X86CC = X86::COND_A;
15784 SDValue LHS = Op.getOperand(1);
15785 SDValue RHS = Op.getOperand(2);
15786 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15787 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15788 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15789 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15790 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15792 case Intrinsic::x86_avx512_kortestz_w:
15793 case Intrinsic::x86_avx512_kortestc_w: {
15794 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15795 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15796 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15797 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15798 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15799 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15800 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15803 case Intrinsic::x86_sse42_pcmpistria128:
15804 case Intrinsic::x86_sse42_pcmpestria128:
15805 case Intrinsic::x86_sse42_pcmpistric128:
15806 case Intrinsic::x86_sse42_pcmpestric128:
15807 case Intrinsic::x86_sse42_pcmpistrio128:
15808 case Intrinsic::x86_sse42_pcmpestrio128:
15809 case Intrinsic::x86_sse42_pcmpistris128:
15810 case Intrinsic::x86_sse42_pcmpestris128:
15811 case Intrinsic::x86_sse42_pcmpistriz128:
15812 case Intrinsic::x86_sse42_pcmpestriz128: {
15816 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15817 case Intrinsic::x86_sse42_pcmpistria128:
15818 Opcode = X86ISD::PCMPISTRI;
15819 X86CC = X86::COND_A;
15821 case Intrinsic::x86_sse42_pcmpestria128:
15822 Opcode = X86ISD::PCMPESTRI;
15823 X86CC = X86::COND_A;
15825 case Intrinsic::x86_sse42_pcmpistric128:
15826 Opcode = X86ISD::PCMPISTRI;
15827 X86CC = X86::COND_B;
15829 case Intrinsic::x86_sse42_pcmpestric128:
15830 Opcode = X86ISD::PCMPESTRI;
15831 X86CC = X86::COND_B;
15833 case Intrinsic::x86_sse42_pcmpistrio128:
15834 Opcode = X86ISD::PCMPISTRI;
15835 X86CC = X86::COND_O;
15837 case Intrinsic::x86_sse42_pcmpestrio128:
15838 Opcode = X86ISD::PCMPESTRI;
15839 X86CC = X86::COND_O;
15841 case Intrinsic::x86_sse42_pcmpistris128:
15842 Opcode = X86ISD::PCMPISTRI;
15843 X86CC = X86::COND_S;
15845 case Intrinsic::x86_sse42_pcmpestris128:
15846 Opcode = X86ISD::PCMPESTRI;
15847 X86CC = X86::COND_S;
15849 case Intrinsic::x86_sse42_pcmpistriz128:
15850 Opcode = X86ISD::PCMPISTRI;
15851 X86CC = X86::COND_E;
15853 case Intrinsic::x86_sse42_pcmpestriz128:
15854 Opcode = X86ISD::PCMPESTRI;
15855 X86CC = X86::COND_E;
15858 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15859 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15860 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15861 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15862 DAG.getConstant(X86CC, MVT::i8),
15863 SDValue(PCMP.getNode(), 1));
15864 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15867 case Intrinsic::x86_sse42_pcmpistri128:
15868 case Intrinsic::x86_sse42_pcmpestri128: {
15870 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15871 Opcode = X86ISD::PCMPISTRI;
15873 Opcode = X86ISD::PCMPESTRI;
15875 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15876 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15877 return DAG.getNode(Opcode, dl, VTs, NewOps);
15880 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15881 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15882 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15883 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15884 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15885 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15886 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15887 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15888 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15889 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15890 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15891 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15892 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15893 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15894 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15895 dl, Op.getValueType(),
15899 Op.getOperand(4), Op.getOperand(1), DAG);
15904 case Intrinsic::x86_fma_vfmadd_ps:
15905 case Intrinsic::x86_fma_vfmadd_pd:
15906 case Intrinsic::x86_fma_vfmsub_ps:
15907 case Intrinsic::x86_fma_vfmsub_pd:
15908 case Intrinsic::x86_fma_vfnmadd_ps:
15909 case Intrinsic::x86_fma_vfnmadd_pd:
15910 case Intrinsic::x86_fma_vfnmsub_ps:
15911 case Intrinsic::x86_fma_vfnmsub_pd:
15912 case Intrinsic::x86_fma_vfmaddsub_ps:
15913 case Intrinsic::x86_fma_vfmaddsub_pd:
15914 case Intrinsic::x86_fma_vfmsubadd_ps:
15915 case Intrinsic::x86_fma_vfmsubadd_pd:
15916 case Intrinsic::x86_fma_vfmadd_ps_256:
15917 case Intrinsic::x86_fma_vfmadd_pd_256:
15918 case Intrinsic::x86_fma_vfmsub_ps_256:
15919 case Intrinsic::x86_fma_vfmsub_pd_256:
15920 case Intrinsic::x86_fma_vfnmadd_ps_256:
15921 case Intrinsic::x86_fma_vfnmadd_pd_256:
15922 case Intrinsic::x86_fma_vfnmsub_ps_256:
15923 case Intrinsic::x86_fma_vfnmsub_pd_256:
15924 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15925 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15926 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15927 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15928 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15929 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15933 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15934 SDValue Src, SDValue Mask, SDValue Base,
15935 SDValue Index, SDValue ScaleOp, SDValue Chain,
15936 const X86Subtarget * Subtarget) {
15938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15939 assert(C && "Invalid scale type");
15940 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15941 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15942 Index.getSimpleValueType().getVectorNumElements());
15944 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15946 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15948 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15949 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15950 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15951 SDValue Segment = DAG.getRegister(0, MVT::i32);
15952 if (Src.getOpcode() == ISD::UNDEF)
15953 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15954 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15955 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15956 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15957 return DAG.getMergeValues(RetOps, dl);
15960 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15961 SDValue Src, SDValue Mask, SDValue Base,
15962 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15964 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15965 assert(C && "Invalid scale type");
15966 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15967 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15968 SDValue Segment = DAG.getRegister(0, MVT::i32);
15969 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15970 Index.getSimpleValueType().getVectorNumElements());
15972 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15974 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15976 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15977 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15978 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15979 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15980 return SDValue(Res, 1);
15983 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15984 SDValue Mask, SDValue Base, SDValue Index,
15985 SDValue ScaleOp, SDValue Chain) {
15987 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15988 assert(C && "Invalid scale type");
15989 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15990 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15991 SDValue Segment = DAG.getRegister(0, MVT::i32);
15993 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15995 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15997 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15999 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16000 //SDVTList VTs = DAG.getVTList(MVT::Other);
16001 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16002 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16003 return SDValue(Res, 0);
16006 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16007 // read performance monitor counters (x86_rdpmc).
16008 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16009 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16010 SmallVectorImpl<SDValue> &Results) {
16011 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16012 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16015 // The ECX register is used to select the index of the performance counter
16017 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16019 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16021 // Reads the content of a 64-bit performance counter and returns it in the
16022 // registers EDX:EAX.
16023 if (Subtarget->is64Bit()) {
16024 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16025 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16028 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16029 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16032 Chain = HI.getValue(1);
16034 if (Subtarget->is64Bit()) {
16035 // The EAX register is loaded with the low-order 32 bits. The EDX register
16036 // is loaded with the supported high-order bits of the counter.
16037 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16038 DAG.getConstant(32, MVT::i8));
16039 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16040 Results.push_back(Chain);
16044 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16045 SDValue Ops[] = { LO, HI };
16046 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16047 Results.push_back(Pair);
16048 Results.push_back(Chain);
16051 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16052 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16053 // also used to custom lower READCYCLECOUNTER nodes.
16054 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16055 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16056 SmallVectorImpl<SDValue> &Results) {
16057 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16058 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16061 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16062 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16063 // and the EAX register is loaded with the low-order 32 bits.
16064 if (Subtarget->is64Bit()) {
16065 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16066 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16069 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16070 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16073 SDValue Chain = HI.getValue(1);
16075 if (Opcode == X86ISD::RDTSCP_DAG) {
16076 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16078 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16079 // the ECX register. Add 'ecx' explicitly to the chain.
16080 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16082 // Explicitly store the content of ECX at the location passed in input
16083 // to the 'rdtscp' intrinsic.
16084 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16085 MachinePointerInfo(), false, false, 0);
16088 if (Subtarget->is64Bit()) {
16089 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16090 // the EAX register is loaded with the low-order 32 bits.
16091 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16092 DAG.getConstant(32, MVT::i8));
16093 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16094 Results.push_back(Chain);
16098 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16099 SDValue Ops[] = { LO, HI };
16100 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16101 Results.push_back(Pair);
16102 Results.push_back(Chain);
16105 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16106 SelectionDAG &DAG) {
16107 SmallVector<SDValue, 2> Results;
16109 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16111 return DAG.getMergeValues(Results, DL);
16115 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16116 SelectionDAG &DAG) {
16117 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16119 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16124 switch(IntrData->Type) {
16126 llvm_unreachable("Unknown Intrinsic Type");
16130 // Emit the node with the right value type.
16131 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16132 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16134 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16135 // Otherwise return the value from Rand, which is always 0, casted to i32.
16136 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16137 DAG.getConstant(1, Op->getValueType(1)),
16138 DAG.getConstant(X86::COND_B, MVT::i32),
16139 SDValue(Result.getNode(), 1) };
16140 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16141 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16144 // Return { result, isValid, chain }.
16145 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16146 SDValue(Result.getNode(), 2));
16149 //gather(v1, mask, index, base, scale);
16150 SDValue Chain = Op.getOperand(0);
16151 SDValue Src = Op.getOperand(2);
16152 SDValue Base = Op.getOperand(3);
16153 SDValue Index = Op.getOperand(4);
16154 SDValue Mask = Op.getOperand(5);
16155 SDValue Scale = Op.getOperand(6);
16156 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16160 //scatter(base, mask, index, v1, scale);
16161 SDValue Chain = Op.getOperand(0);
16162 SDValue Base = Op.getOperand(2);
16163 SDValue Mask = Op.getOperand(3);
16164 SDValue Index = Op.getOperand(4);
16165 SDValue Src = Op.getOperand(5);
16166 SDValue Scale = Op.getOperand(6);
16167 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16170 SDValue Hint = Op.getOperand(6);
16172 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16173 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16174 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16175 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16176 SDValue Chain = Op.getOperand(0);
16177 SDValue Mask = Op.getOperand(2);
16178 SDValue Index = Op.getOperand(3);
16179 SDValue Base = Op.getOperand(4);
16180 SDValue Scale = Op.getOperand(5);
16181 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16183 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16185 SmallVector<SDValue, 2> Results;
16186 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16187 return DAG.getMergeValues(Results, dl);
16189 // Read Performance Monitoring Counters.
16191 SmallVector<SDValue, 2> Results;
16192 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16193 return DAG.getMergeValues(Results, dl);
16195 // XTEST intrinsics.
16197 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16198 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16199 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16200 DAG.getConstant(X86::COND_NE, MVT::i8),
16202 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16203 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16204 Ret, SDValue(InTrans.getNode(), 1));
16208 SmallVector<SDValue, 2> Results;
16209 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16210 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16211 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16212 DAG.getConstant(-1, MVT::i8));
16213 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16214 Op.getOperand(4), GenCF.getValue(1));
16215 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16216 Op.getOperand(5), MachinePointerInfo(),
16218 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16219 DAG.getConstant(X86::COND_B, MVT::i8),
16221 Results.push_back(SetCC);
16222 Results.push_back(Store);
16223 return DAG.getMergeValues(Results, dl);
16228 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16229 SelectionDAG &DAG) const {
16230 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16231 MFI->setReturnAddressIsTaken(true);
16233 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16236 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16238 EVT PtrVT = getPointerTy();
16241 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16242 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16243 DAG.getSubtarget().getRegisterInfo());
16244 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16245 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16246 DAG.getNode(ISD::ADD, dl, PtrVT,
16247 FrameAddr, Offset),
16248 MachinePointerInfo(), false, false, false, 0);
16251 // Just load the return address.
16252 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16253 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16254 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16257 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16258 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16259 MFI->setFrameAddressIsTaken(true);
16261 EVT VT = Op.getValueType();
16262 SDLoc dl(Op); // FIXME probably not meaningful
16263 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16264 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16265 DAG.getSubtarget().getRegisterInfo());
16266 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16267 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16268 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16269 "Invalid Frame Register!");
16270 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16272 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16273 MachinePointerInfo(),
16274 false, false, false, 0);
16278 // FIXME? Maybe this could be a TableGen attribute on some registers and
16279 // this table could be generated automatically from RegInfo.
16280 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16282 unsigned Reg = StringSwitch<unsigned>(RegName)
16283 .Case("esp", X86::ESP)
16284 .Case("rsp", X86::RSP)
16288 report_fatal_error("Invalid register name global variable");
16291 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16292 SelectionDAG &DAG) const {
16293 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16294 DAG.getSubtarget().getRegisterInfo());
16295 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16298 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16299 SDValue Chain = Op.getOperand(0);
16300 SDValue Offset = Op.getOperand(1);
16301 SDValue Handler = Op.getOperand(2);
16304 EVT PtrVT = getPointerTy();
16305 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16306 DAG.getSubtarget().getRegisterInfo());
16307 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16308 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16309 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16310 "Invalid Frame Register!");
16311 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16312 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16314 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16315 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16316 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16317 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16319 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16321 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16322 DAG.getRegister(StoreAddrReg, PtrVT));
16325 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16326 SelectionDAG &DAG) const {
16328 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16329 DAG.getVTList(MVT::i32, MVT::Other),
16330 Op.getOperand(0), Op.getOperand(1));
16333 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16334 SelectionDAG &DAG) const {
16336 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16337 Op.getOperand(0), Op.getOperand(1));
16340 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16341 return Op.getOperand(0);
16344 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16345 SelectionDAG &DAG) const {
16346 SDValue Root = Op.getOperand(0);
16347 SDValue Trmp = Op.getOperand(1); // trampoline
16348 SDValue FPtr = Op.getOperand(2); // nested function
16349 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16352 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16353 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16355 if (Subtarget->is64Bit()) {
16356 SDValue OutChains[6];
16358 // Large code-model.
16359 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16360 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16362 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16363 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16365 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16367 // Load the pointer to the nested function into R11.
16368 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16369 SDValue Addr = Trmp;
16370 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16371 Addr, MachinePointerInfo(TrmpAddr),
16374 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16375 DAG.getConstant(2, MVT::i64));
16376 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16377 MachinePointerInfo(TrmpAddr, 2),
16380 // Load the 'nest' parameter value into R10.
16381 // R10 is specified in X86CallingConv.td
16382 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16383 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16384 DAG.getConstant(10, MVT::i64));
16385 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16386 Addr, MachinePointerInfo(TrmpAddr, 10),
16389 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16390 DAG.getConstant(12, MVT::i64));
16391 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16392 MachinePointerInfo(TrmpAddr, 12),
16395 // Jump to the nested function.
16396 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16397 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16398 DAG.getConstant(20, MVT::i64));
16399 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16400 Addr, MachinePointerInfo(TrmpAddr, 20),
16403 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16404 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16405 DAG.getConstant(22, MVT::i64));
16406 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16407 MachinePointerInfo(TrmpAddr, 22),
16410 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16412 const Function *Func =
16413 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16414 CallingConv::ID CC = Func->getCallingConv();
16419 llvm_unreachable("Unsupported calling convention");
16420 case CallingConv::C:
16421 case CallingConv::X86_StdCall: {
16422 // Pass 'nest' parameter in ECX.
16423 // Must be kept in sync with X86CallingConv.td
16424 NestReg = X86::ECX;
16426 // Check that ECX wasn't needed by an 'inreg' parameter.
16427 FunctionType *FTy = Func->getFunctionType();
16428 const AttributeSet &Attrs = Func->getAttributes();
16430 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16431 unsigned InRegCount = 0;
16434 for (FunctionType::param_iterator I = FTy->param_begin(),
16435 E = FTy->param_end(); I != E; ++I, ++Idx)
16436 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16437 // FIXME: should only count parameters that are lowered to integers.
16438 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16440 if (InRegCount > 2) {
16441 report_fatal_error("Nest register in use - reduce number of inreg"
16447 case CallingConv::X86_FastCall:
16448 case CallingConv::X86_ThisCall:
16449 case CallingConv::Fast:
16450 // Pass 'nest' parameter in EAX.
16451 // Must be kept in sync with X86CallingConv.td
16452 NestReg = X86::EAX;
16456 SDValue OutChains[4];
16457 SDValue Addr, Disp;
16459 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16460 DAG.getConstant(10, MVT::i32));
16461 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16463 // This is storing the opcode for MOV32ri.
16464 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16465 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16466 OutChains[0] = DAG.getStore(Root, dl,
16467 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16468 Trmp, MachinePointerInfo(TrmpAddr),
16471 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16472 DAG.getConstant(1, MVT::i32));
16473 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16474 MachinePointerInfo(TrmpAddr, 1),
16477 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16478 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16479 DAG.getConstant(5, MVT::i32));
16480 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16481 MachinePointerInfo(TrmpAddr, 5),
16484 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16485 DAG.getConstant(6, MVT::i32));
16486 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16487 MachinePointerInfo(TrmpAddr, 6),
16490 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16494 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16495 SelectionDAG &DAG) const {
16497 The rounding mode is in bits 11:10 of FPSR, and has the following
16499 00 Round to nearest
16504 FLT_ROUNDS, on the other hand, expects the following:
16511 To perform the conversion, we do:
16512 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16515 MachineFunction &MF = DAG.getMachineFunction();
16516 const TargetMachine &TM = MF.getTarget();
16517 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16518 unsigned StackAlignment = TFI.getStackAlignment();
16519 MVT VT = Op.getSimpleValueType();
16522 // Save FP Control Word to stack slot
16523 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16524 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16526 MachineMemOperand *MMO =
16527 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16528 MachineMemOperand::MOStore, 2, 2);
16530 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16531 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16532 DAG.getVTList(MVT::Other),
16533 Ops, MVT::i16, MMO);
16535 // Load FP Control Word from stack slot
16536 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16537 MachinePointerInfo(), false, false, false, 0);
16539 // Transform as necessary
16541 DAG.getNode(ISD::SRL, DL, MVT::i16,
16542 DAG.getNode(ISD::AND, DL, MVT::i16,
16543 CWD, DAG.getConstant(0x800, MVT::i16)),
16544 DAG.getConstant(11, MVT::i8));
16546 DAG.getNode(ISD::SRL, DL, MVT::i16,
16547 DAG.getNode(ISD::AND, DL, MVT::i16,
16548 CWD, DAG.getConstant(0x400, MVT::i16)),
16549 DAG.getConstant(9, MVT::i8));
16552 DAG.getNode(ISD::AND, DL, MVT::i16,
16553 DAG.getNode(ISD::ADD, DL, MVT::i16,
16554 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16555 DAG.getConstant(1, MVT::i16)),
16556 DAG.getConstant(3, MVT::i16));
16558 return DAG.getNode((VT.getSizeInBits() < 16 ?
16559 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16562 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16563 MVT VT = Op.getSimpleValueType();
16565 unsigned NumBits = VT.getSizeInBits();
16568 Op = Op.getOperand(0);
16569 if (VT == MVT::i8) {
16570 // Zero extend to i32 since there is not an i8 bsr.
16572 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16575 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16576 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16577 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16579 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16582 DAG.getConstant(NumBits+NumBits-1, OpVT),
16583 DAG.getConstant(X86::COND_E, MVT::i8),
16586 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16588 // Finally xor with NumBits-1.
16589 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16592 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16596 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16597 MVT VT = Op.getSimpleValueType();
16599 unsigned NumBits = VT.getSizeInBits();
16602 Op = Op.getOperand(0);
16603 if (VT == MVT::i8) {
16604 // Zero extend to i32 since there is not an i8 bsr.
16606 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16609 // Issue a bsr (scan bits in reverse).
16610 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16611 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16613 // And xor with NumBits-1.
16614 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16617 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16621 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16622 MVT VT = Op.getSimpleValueType();
16623 unsigned NumBits = VT.getSizeInBits();
16625 Op = Op.getOperand(0);
16627 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16628 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16629 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16631 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16634 DAG.getConstant(NumBits, VT),
16635 DAG.getConstant(X86::COND_E, MVT::i8),
16638 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16641 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16642 // ones, and then concatenate the result back.
16643 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16644 MVT VT = Op.getSimpleValueType();
16646 assert(VT.is256BitVector() && VT.isInteger() &&
16647 "Unsupported value type for operation");
16649 unsigned NumElems = VT.getVectorNumElements();
16652 // Extract the LHS vectors
16653 SDValue LHS = Op.getOperand(0);
16654 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16655 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16657 // Extract the RHS vectors
16658 SDValue RHS = Op.getOperand(1);
16659 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16660 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16662 MVT EltVT = VT.getVectorElementType();
16663 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16665 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16666 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16667 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16670 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16671 assert(Op.getSimpleValueType().is256BitVector() &&
16672 Op.getSimpleValueType().isInteger() &&
16673 "Only handle AVX 256-bit vector integer operation");
16674 return Lower256IntArith(Op, DAG);
16677 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16678 assert(Op.getSimpleValueType().is256BitVector() &&
16679 Op.getSimpleValueType().isInteger() &&
16680 "Only handle AVX 256-bit vector integer operation");
16681 return Lower256IntArith(Op, DAG);
16684 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16685 SelectionDAG &DAG) {
16687 MVT VT = Op.getSimpleValueType();
16689 // Decompose 256-bit ops into smaller 128-bit ops.
16690 if (VT.is256BitVector() && !Subtarget->hasInt256())
16691 return Lower256IntArith(Op, DAG);
16693 SDValue A = Op.getOperand(0);
16694 SDValue B = Op.getOperand(1);
16696 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16697 if (VT == MVT::v4i32) {
16698 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16699 "Should not custom lower when pmuldq is available!");
16701 // Extract the odd parts.
16702 static const int UnpackMask[] = { 1, -1, 3, -1 };
16703 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16704 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16706 // Multiply the even parts.
16707 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16708 // Now multiply odd parts.
16709 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16711 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16712 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16714 // Merge the two vectors back together with a shuffle. This expands into 2
16716 static const int ShufMask[] = { 0, 4, 2, 6 };
16717 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16720 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16721 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16723 // Ahi = psrlqi(a, 32);
16724 // Bhi = psrlqi(b, 32);
16726 // AloBlo = pmuludq(a, b);
16727 // AloBhi = pmuludq(a, Bhi);
16728 // AhiBlo = pmuludq(Ahi, b);
16730 // AloBhi = psllqi(AloBhi, 32);
16731 // AhiBlo = psllqi(AhiBlo, 32);
16732 // return AloBlo + AloBhi + AhiBlo;
16734 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16735 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16737 // Bit cast to 32-bit vectors for MULUDQ
16738 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16739 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16740 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16741 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16742 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16743 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16745 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16746 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16747 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16749 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16750 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16752 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16753 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16756 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16757 assert(Subtarget->isTargetWin64() && "Unexpected target");
16758 EVT VT = Op.getValueType();
16759 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16760 "Unexpected return type for lowering");
16764 switch (Op->getOpcode()) {
16765 default: llvm_unreachable("Unexpected request for libcall!");
16766 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16767 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16768 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16769 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16770 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16771 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16775 SDValue InChain = DAG.getEntryNode();
16777 TargetLowering::ArgListTy Args;
16778 TargetLowering::ArgListEntry Entry;
16779 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16780 EVT ArgVT = Op->getOperand(i).getValueType();
16781 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16782 "Unexpected argument type for lowering");
16783 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16784 Entry.Node = StackPtr;
16785 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16787 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16788 Entry.Ty = PointerType::get(ArgTy,0);
16789 Entry.isSExt = false;
16790 Entry.isZExt = false;
16791 Args.push_back(Entry);
16794 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16797 TargetLowering::CallLoweringInfo CLI(DAG);
16798 CLI.setDebugLoc(dl).setChain(InChain)
16799 .setCallee(getLibcallCallingConv(LC),
16800 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16801 Callee, std::move(Args), 0)
16802 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16804 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16805 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16808 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16809 SelectionDAG &DAG) {
16810 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16811 EVT VT = Op0.getValueType();
16814 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16815 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16817 // PMULxD operations multiply each even value (starting at 0) of LHS with
16818 // the related value of RHS and produce a widen result.
16819 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16820 // => <2 x i64> <ae|cg>
16822 // In other word, to have all the results, we need to perform two PMULxD:
16823 // 1. one with the even values.
16824 // 2. one with the odd values.
16825 // To achieve #2, with need to place the odd values at an even position.
16827 // Place the odd value at an even position (basically, shift all values 1
16828 // step to the left):
16829 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16830 // <a|b|c|d> => <b|undef|d|undef>
16831 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16832 // <e|f|g|h> => <f|undef|h|undef>
16833 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16835 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16837 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16838 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16840 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16841 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16842 // => <2 x i64> <ae|cg>
16843 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16844 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16845 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16846 // => <2 x i64> <bf|dh>
16847 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16848 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16850 // Shuffle it back into the right order.
16851 SDValue Highs, Lows;
16852 if (VT == MVT::v8i32) {
16853 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16854 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16855 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16856 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16858 const int HighMask[] = {1, 5, 3, 7};
16859 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16860 const int LowMask[] = {0, 4, 2, 6};
16861 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16864 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16865 // unsigned multiply.
16866 if (IsSigned && !Subtarget->hasSSE41()) {
16868 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16869 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16870 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16871 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16872 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16874 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16875 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16878 // The first result of MUL_LOHI is actually the low value, followed by the
16880 SDValue Ops[] = {Lows, Highs};
16881 return DAG.getMergeValues(Ops, dl);
16884 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16885 const X86Subtarget *Subtarget) {
16886 MVT VT = Op.getSimpleValueType();
16888 SDValue R = Op.getOperand(0);
16889 SDValue Amt = Op.getOperand(1);
16891 // Optimize shl/srl/sra with constant shift amount.
16892 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16893 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16894 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16896 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16897 (Subtarget->hasInt256() &&
16898 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16899 (Subtarget->hasAVX512() &&
16900 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16901 if (Op.getOpcode() == ISD::SHL)
16902 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16904 if (Op.getOpcode() == ISD::SRL)
16905 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16907 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16908 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16912 if (VT == MVT::v16i8) {
16913 if (Op.getOpcode() == ISD::SHL) {
16914 // Make a large shift.
16915 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16916 MVT::v8i16, R, ShiftAmt,
16918 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16919 // Zero out the rightmost bits.
16920 SmallVector<SDValue, 16> V(16,
16921 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16923 return DAG.getNode(ISD::AND, dl, VT, SHL,
16924 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16926 if (Op.getOpcode() == ISD::SRL) {
16927 // Make a large shift.
16928 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16929 MVT::v8i16, R, ShiftAmt,
16931 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16932 // Zero out the leftmost bits.
16933 SmallVector<SDValue, 16> V(16,
16934 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16936 return DAG.getNode(ISD::AND, dl, VT, SRL,
16937 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16939 if (Op.getOpcode() == ISD::SRA) {
16940 if (ShiftAmt == 7) {
16941 // R s>> 7 === R s< 0
16942 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16943 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16946 // R s>> a === ((R u>> a) ^ m) - m
16947 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16948 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16950 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16951 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16952 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16955 llvm_unreachable("Unknown shift opcode.");
16958 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16959 if (Op.getOpcode() == ISD::SHL) {
16960 // Make a large shift.
16961 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16962 MVT::v16i16, R, ShiftAmt,
16964 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16965 // Zero out the rightmost bits.
16966 SmallVector<SDValue, 32> V(32,
16967 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16969 return DAG.getNode(ISD::AND, dl, VT, SHL,
16970 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16972 if (Op.getOpcode() == ISD::SRL) {
16973 // Make a large shift.
16974 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16975 MVT::v16i16, R, ShiftAmt,
16977 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16978 // Zero out the leftmost bits.
16979 SmallVector<SDValue, 32> V(32,
16980 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16982 return DAG.getNode(ISD::AND, dl, VT, SRL,
16983 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16985 if (Op.getOpcode() == ISD::SRA) {
16986 if (ShiftAmt == 7) {
16987 // R s>> 7 === R s< 0
16988 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16989 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16992 // R s>> a === ((R u>> a) ^ m) - m
16993 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16994 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16996 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16997 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16998 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17001 llvm_unreachable("Unknown shift opcode.");
17006 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17007 if (!Subtarget->is64Bit() &&
17008 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17009 Amt.getOpcode() == ISD::BITCAST &&
17010 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17011 Amt = Amt.getOperand(0);
17012 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17013 VT.getVectorNumElements();
17014 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17015 uint64_t ShiftAmt = 0;
17016 for (unsigned i = 0; i != Ratio; ++i) {
17017 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17021 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17023 // Check remaining shift amounts.
17024 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17025 uint64_t ShAmt = 0;
17026 for (unsigned j = 0; j != Ratio; ++j) {
17027 ConstantSDNode *C =
17028 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17032 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17034 if (ShAmt != ShiftAmt)
17037 switch (Op.getOpcode()) {
17039 llvm_unreachable("Unknown shift opcode!");
17041 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17044 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17047 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17055 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17056 const X86Subtarget* Subtarget) {
17057 MVT VT = Op.getSimpleValueType();
17059 SDValue R = Op.getOperand(0);
17060 SDValue Amt = Op.getOperand(1);
17062 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17063 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17064 (Subtarget->hasInt256() &&
17065 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17066 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17067 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17069 EVT EltVT = VT.getVectorElementType();
17071 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17072 unsigned NumElts = VT.getVectorNumElements();
17074 for (i = 0; i != NumElts; ++i) {
17075 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17079 for (j = i; j != NumElts; ++j) {
17080 SDValue Arg = Amt.getOperand(j);
17081 if (Arg.getOpcode() == ISD::UNDEF) continue;
17082 if (Arg != Amt.getOperand(i))
17085 if (i != NumElts && j == NumElts)
17086 BaseShAmt = Amt.getOperand(i);
17088 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17089 Amt = Amt.getOperand(0);
17090 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17091 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17092 SDValue InVec = Amt.getOperand(0);
17093 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17094 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17096 for (; i != NumElts; ++i) {
17097 SDValue Arg = InVec.getOperand(i);
17098 if (Arg.getOpcode() == ISD::UNDEF) continue;
17102 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17103 if (ConstantSDNode *C =
17104 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17105 unsigned SplatIdx =
17106 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17107 if (C->getZExtValue() == SplatIdx)
17108 BaseShAmt = InVec.getOperand(1);
17111 if (!BaseShAmt.getNode())
17112 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17113 DAG.getIntPtrConstant(0));
17117 if (BaseShAmt.getNode()) {
17118 if (EltVT.bitsGT(MVT::i32))
17119 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17120 else if (EltVT.bitsLT(MVT::i32))
17121 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17123 switch (Op.getOpcode()) {
17125 llvm_unreachable("Unknown shift opcode!");
17127 switch (VT.SimpleTy) {
17128 default: return SDValue();
17137 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17140 switch (VT.SimpleTy) {
17141 default: return SDValue();
17148 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17151 switch (VT.SimpleTy) {
17152 default: return SDValue();
17161 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17167 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17168 if (!Subtarget->is64Bit() &&
17169 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17170 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17171 Amt.getOpcode() == ISD::BITCAST &&
17172 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17173 Amt = Amt.getOperand(0);
17174 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17175 VT.getVectorNumElements();
17176 std::vector<SDValue> Vals(Ratio);
17177 for (unsigned i = 0; i != Ratio; ++i)
17178 Vals[i] = Amt.getOperand(i);
17179 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17180 for (unsigned j = 0; j != Ratio; ++j)
17181 if (Vals[j] != Amt.getOperand(i + j))
17184 switch (Op.getOpcode()) {
17186 llvm_unreachable("Unknown shift opcode!");
17188 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17190 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17192 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17199 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17200 SelectionDAG &DAG) {
17201 MVT VT = Op.getSimpleValueType();
17203 SDValue R = Op.getOperand(0);
17204 SDValue Amt = Op.getOperand(1);
17207 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17208 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17210 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17214 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17218 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17220 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17221 if (Subtarget->hasInt256()) {
17222 if (Op.getOpcode() == ISD::SRL &&
17223 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17224 VT == MVT::v4i64 || VT == MVT::v8i32))
17226 if (Op.getOpcode() == ISD::SHL &&
17227 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17228 VT == MVT::v4i64 || VT == MVT::v8i32))
17230 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17234 // If possible, lower this packed shift into a vector multiply instead of
17235 // expanding it into a sequence of scalar shifts.
17236 // Do this only if the vector shift count is a constant build_vector.
17237 if (Op.getOpcode() == ISD::SHL &&
17238 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17239 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17240 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17241 SmallVector<SDValue, 8> Elts;
17242 EVT SVT = VT.getScalarType();
17243 unsigned SVTBits = SVT.getSizeInBits();
17244 const APInt &One = APInt(SVTBits, 1);
17245 unsigned NumElems = VT.getVectorNumElements();
17247 for (unsigned i=0; i !=NumElems; ++i) {
17248 SDValue Op = Amt->getOperand(i);
17249 if (Op->getOpcode() == ISD::UNDEF) {
17250 Elts.push_back(Op);
17254 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17255 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17256 uint64_t ShAmt = C.getZExtValue();
17257 if (ShAmt >= SVTBits) {
17258 Elts.push_back(DAG.getUNDEF(SVT));
17261 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17263 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17264 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17267 // Lower SHL with variable shift amount.
17268 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17269 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17271 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17272 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17273 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17274 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17277 // If possible, lower this shift as a sequence of two shifts by
17278 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17280 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17282 // Could be rewritten as:
17283 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17285 // The advantage is that the two shifts from the example would be
17286 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17287 // the vector shift into four scalar shifts plus four pairs of vector
17289 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17290 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17291 unsigned TargetOpcode = X86ISD::MOVSS;
17292 bool CanBeSimplified;
17293 // The splat value for the first packed shift (the 'X' from the example).
17294 SDValue Amt1 = Amt->getOperand(0);
17295 // The splat value for the second packed shift (the 'Y' from the example).
17296 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17297 Amt->getOperand(2);
17299 // See if it is possible to replace this node with a sequence of
17300 // two shifts followed by a MOVSS/MOVSD
17301 if (VT == MVT::v4i32) {
17302 // Check if it is legal to use a MOVSS.
17303 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17304 Amt2 == Amt->getOperand(3);
17305 if (!CanBeSimplified) {
17306 // Otherwise, check if we can still simplify this node using a MOVSD.
17307 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17308 Amt->getOperand(2) == Amt->getOperand(3);
17309 TargetOpcode = X86ISD::MOVSD;
17310 Amt2 = Amt->getOperand(2);
17313 // Do similar checks for the case where the machine value type
17315 CanBeSimplified = Amt1 == Amt->getOperand(1);
17316 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17317 CanBeSimplified = Amt2 == Amt->getOperand(i);
17319 if (!CanBeSimplified) {
17320 TargetOpcode = X86ISD::MOVSD;
17321 CanBeSimplified = true;
17322 Amt2 = Amt->getOperand(4);
17323 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17324 CanBeSimplified = Amt1 == Amt->getOperand(i);
17325 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17326 CanBeSimplified = Amt2 == Amt->getOperand(j);
17330 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17331 isa<ConstantSDNode>(Amt2)) {
17332 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17333 EVT CastVT = MVT::v4i32;
17335 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17336 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17338 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17339 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17340 if (TargetOpcode == X86ISD::MOVSD)
17341 CastVT = MVT::v2i64;
17342 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17343 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17344 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17346 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17350 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17351 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17354 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17355 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17357 // Turn 'a' into a mask suitable for VSELECT
17358 SDValue VSelM = DAG.getConstant(0x80, VT);
17359 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17360 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17362 SDValue CM1 = DAG.getConstant(0x0f, VT);
17363 SDValue CM2 = DAG.getConstant(0x3f, VT);
17365 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17366 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17367 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17368 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17369 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17372 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17373 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17374 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17376 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17377 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17378 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17379 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17380 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17383 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17384 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17385 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17387 // return VSELECT(r, r+r, a);
17388 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17389 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17393 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17394 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17395 // solution better.
17396 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17397 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17399 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17400 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17401 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17402 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17403 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17406 // Decompose 256-bit shifts into smaller 128-bit shifts.
17407 if (VT.is256BitVector()) {
17408 unsigned NumElems = VT.getVectorNumElements();
17409 MVT EltVT = VT.getVectorElementType();
17410 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17412 // Extract the two vectors
17413 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17414 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17416 // Recreate the shift amount vectors
17417 SDValue Amt1, Amt2;
17418 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17419 // Constant shift amount
17420 SmallVector<SDValue, 4> Amt1Csts;
17421 SmallVector<SDValue, 4> Amt2Csts;
17422 for (unsigned i = 0; i != NumElems/2; ++i)
17423 Amt1Csts.push_back(Amt->getOperand(i));
17424 for (unsigned i = NumElems/2; i != NumElems; ++i)
17425 Amt2Csts.push_back(Amt->getOperand(i));
17427 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17428 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17430 // Variable shift amount
17431 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17432 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17435 // Issue new vector shifts for the smaller types
17436 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17437 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17439 // Concatenate the result back
17440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17446 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17447 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17448 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17449 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17450 // has only one use.
17451 SDNode *N = Op.getNode();
17452 SDValue LHS = N->getOperand(0);
17453 SDValue RHS = N->getOperand(1);
17454 unsigned BaseOp = 0;
17457 switch (Op.getOpcode()) {
17458 default: llvm_unreachable("Unknown ovf instruction!");
17460 // A subtract of one will be selected as a INC. Note that INC doesn't
17461 // set CF, so we can't do this for UADDO.
17462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17464 BaseOp = X86ISD::INC;
17465 Cond = X86::COND_O;
17468 BaseOp = X86ISD::ADD;
17469 Cond = X86::COND_O;
17472 BaseOp = X86ISD::ADD;
17473 Cond = X86::COND_B;
17476 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17477 // set CF, so we can't do this for USUBO.
17478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17480 BaseOp = X86ISD::DEC;
17481 Cond = X86::COND_O;
17484 BaseOp = X86ISD::SUB;
17485 Cond = X86::COND_O;
17488 BaseOp = X86ISD::SUB;
17489 Cond = X86::COND_B;
17492 BaseOp = X86ISD::SMUL;
17493 Cond = X86::COND_O;
17495 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17496 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17498 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17501 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17502 DAG.getConstant(X86::COND_O, MVT::i32),
17503 SDValue(Sum.getNode(), 2));
17505 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17509 // Also sets EFLAGS.
17510 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17511 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17514 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17515 DAG.getConstant(Cond, MVT::i32),
17516 SDValue(Sum.getNode(), 1));
17518 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17521 // Sign extension of the low part of vector elements. This may be used either
17522 // when sign extend instructions are not available or if the vector element
17523 // sizes already match the sign-extended size. If the vector elements are in
17524 // their pre-extended size and sign extend instructions are available, that will
17525 // be handled by LowerSIGN_EXTEND.
17526 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17527 SelectionDAG &DAG) const {
17529 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17530 MVT VT = Op.getSimpleValueType();
17532 if (!Subtarget->hasSSE2() || !VT.isVector())
17535 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17536 ExtraVT.getScalarType().getSizeInBits();
17538 switch (VT.SimpleTy) {
17539 default: return SDValue();
17542 if (!Subtarget->hasFp256())
17544 if (!Subtarget->hasInt256()) {
17545 // needs to be split
17546 unsigned NumElems = VT.getVectorNumElements();
17548 // Extract the LHS vectors
17549 SDValue LHS = Op.getOperand(0);
17550 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17551 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17553 MVT EltVT = VT.getVectorElementType();
17554 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17556 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17557 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17558 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17560 SDValue Extra = DAG.getValueType(ExtraVT);
17562 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17563 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17565 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17570 SDValue Op0 = Op.getOperand(0);
17572 // This is a sign extension of some low part of vector elements without
17573 // changing the size of the vector elements themselves:
17574 // Shift-Left + Shift-Right-Algebraic.
17575 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17577 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17583 /// Returns true if the operand type is exactly twice the native width, and
17584 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17585 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17586 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17587 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17588 const X86Subtarget &Subtarget =
17589 getTargetMachine().getSubtarget<X86Subtarget>();
17590 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17593 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17594 else if (OpWidth == 128)
17595 return Subtarget.hasCmpxchg16b();
17600 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17601 return needsCmpXchgNb(SI->getValueOperand()->getType());
17604 // Note: this turns large loads into lock cmpxchg8b/16b.
17605 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17606 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17607 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17608 return needsCmpXchgNb(PTy->getElementType());
17611 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17612 const X86Subtarget &Subtarget =
17613 getTargetMachine().getSubtarget<X86Subtarget>();
17614 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17615 const Type *MemType = AI->getType();
17617 // If the operand is too big, we must see if cmpxchg8/16b is available
17618 // and default to library calls otherwise.
17619 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17620 return needsCmpXchgNb(MemType);
17622 AtomicRMWInst::BinOp Op = AI->getOperation();
17625 llvm_unreachable("Unknown atomic operation");
17626 case AtomicRMWInst::Xchg:
17627 case AtomicRMWInst::Add:
17628 case AtomicRMWInst::Sub:
17629 // It's better to use xadd, xsub or xchg for these in all cases.
17631 case AtomicRMWInst::Or:
17632 case AtomicRMWInst::And:
17633 case AtomicRMWInst::Xor:
17634 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17635 // prefix to a normal instruction for these operations.
17636 return !AI->use_empty();
17637 case AtomicRMWInst::Nand:
17638 case AtomicRMWInst::Max:
17639 case AtomicRMWInst::Min:
17640 case AtomicRMWInst::UMax:
17641 case AtomicRMWInst::UMin:
17642 // These always require a non-trivial set of data operations on x86. We must
17643 // use a cmpxchg loop.
17648 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17649 SelectionDAG &DAG) {
17651 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17652 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17653 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17654 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17656 // The only fence that needs an instruction is a sequentially-consistent
17657 // cross-thread fence.
17658 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17659 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17660 // no-sse2). There isn't any reason to disable it if the target processor
17662 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17663 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17665 SDValue Chain = Op.getOperand(0);
17666 SDValue Zero = DAG.getConstant(0, MVT::i32);
17668 DAG.getRegister(X86::ESP, MVT::i32), // Base
17669 DAG.getTargetConstant(1, MVT::i8), // Scale
17670 DAG.getRegister(0, MVT::i32), // Index
17671 DAG.getTargetConstant(0, MVT::i32), // Disp
17672 DAG.getRegister(0, MVT::i32), // Segment.
17676 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17677 return SDValue(Res, 0);
17680 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17681 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17684 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17685 SelectionDAG &DAG) {
17686 MVT T = Op.getSimpleValueType();
17690 switch(T.SimpleTy) {
17691 default: llvm_unreachable("Invalid value type!");
17692 case MVT::i8: Reg = X86::AL; size = 1; break;
17693 case MVT::i16: Reg = X86::AX; size = 2; break;
17694 case MVT::i32: Reg = X86::EAX; size = 4; break;
17696 assert(Subtarget->is64Bit() && "Node not type legal!");
17697 Reg = X86::RAX; size = 8;
17700 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17701 Op.getOperand(2), SDValue());
17702 SDValue Ops[] = { cpIn.getValue(0),
17705 DAG.getTargetConstant(size, MVT::i8),
17706 cpIn.getValue(1) };
17707 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17708 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17709 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17713 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17714 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17715 MVT::i32, cpOut.getValue(2));
17716 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17717 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17719 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17720 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17721 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17725 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17726 SelectionDAG &DAG) {
17727 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17728 MVT DstVT = Op.getSimpleValueType();
17730 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17731 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17732 if (DstVT != MVT::f64)
17733 // This conversion needs to be expanded.
17736 SDValue InVec = Op->getOperand(0);
17738 unsigned NumElts = SrcVT.getVectorNumElements();
17739 EVT SVT = SrcVT.getVectorElementType();
17741 // Widen the vector in input in the case of MVT::v2i32.
17742 // Example: from MVT::v2i32 to MVT::v4i32.
17743 SmallVector<SDValue, 16> Elts;
17744 for (unsigned i = 0, e = NumElts; i != e; ++i)
17745 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17746 DAG.getIntPtrConstant(i)));
17748 // Explicitly mark the extra elements as Undef.
17749 SDValue Undef = DAG.getUNDEF(SVT);
17750 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17751 Elts.push_back(Undef);
17753 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17754 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17755 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17756 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17757 DAG.getIntPtrConstant(0));
17760 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17761 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17762 assert((DstVT == MVT::i64 ||
17763 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17764 "Unexpected custom BITCAST");
17765 // i64 <=> MMX conversions are Legal.
17766 if (SrcVT==MVT::i64 && DstVT.isVector())
17768 if (DstVT==MVT::i64 && SrcVT.isVector())
17770 // MMX <=> MMX conversions are Legal.
17771 if (SrcVT.isVector() && DstVT.isVector())
17773 // All other conversions need to be expanded.
17777 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17778 SDNode *Node = Op.getNode();
17780 EVT T = Node->getValueType(0);
17781 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17782 DAG.getConstant(0, T), Node->getOperand(2));
17783 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17784 cast<AtomicSDNode>(Node)->getMemoryVT(),
17785 Node->getOperand(0),
17786 Node->getOperand(1), negOp,
17787 cast<AtomicSDNode>(Node)->getMemOperand(),
17788 cast<AtomicSDNode>(Node)->getOrdering(),
17789 cast<AtomicSDNode>(Node)->getSynchScope());
17792 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17793 SDNode *Node = Op.getNode();
17795 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17797 // Convert seq_cst store -> xchg
17798 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17799 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17800 // (The only way to get a 16-byte store is cmpxchg16b)
17801 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17802 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17803 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17804 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17805 cast<AtomicSDNode>(Node)->getMemoryVT(),
17806 Node->getOperand(0),
17807 Node->getOperand(1), Node->getOperand(2),
17808 cast<AtomicSDNode>(Node)->getMemOperand(),
17809 cast<AtomicSDNode>(Node)->getOrdering(),
17810 cast<AtomicSDNode>(Node)->getSynchScope());
17811 return Swap.getValue(1);
17813 // Other atomic stores have a simple pattern.
17817 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17818 EVT VT = Op.getNode()->getSimpleValueType(0);
17820 // Let legalize expand this if it isn't a legal type yet.
17821 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17824 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17827 bool ExtraOp = false;
17828 switch (Op.getOpcode()) {
17829 default: llvm_unreachable("Invalid code");
17830 case ISD::ADDC: Opc = X86ISD::ADD; break;
17831 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17832 case ISD::SUBC: Opc = X86ISD::SUB; break;
17833 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17837 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17839 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17840 Op.getOperand(1), Op.getOperand(2));
17843 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17844 SelectionDAG &DAG) {
17845 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17847 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17848 // which returns the values as { float, float } (in XMM0) or
17849 // { double, double } (which is returned in XMM0, XMM1).
17851 SDValue Arg = Op.getOperand(0);
17852 EVT ArgVT = Arg.getValueType();
17853 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17855 TargetLowering::ArgListTy Args;
17856 TargetLowering::ArgListEntry Entry;
17860 Entry.isSExt = false;
17861 Entry.isZExt = false;
17862 Args.push_back(Entry);
17864 bool isF64 = ArgVT == MVT::f64;
17865 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17866 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17867 // the results are returned via SRet in memory.
17868 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17870 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17872 Type *RetTy = isF64
17873 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17874 : (Type*)VectorType::get(ArgTy, 4);
17876 TargetLowering::CallLoweringInfo CLI(DAG);
17877 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17878 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17880 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17883 // Returned in xmm0 and xmm1.
17884 return CallResult.first;
17886 // Returned in bits 0:31 and 32:64 xmm0.
17887 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17888 CallResult.first, DAG.getIntPtrConstant(0));
17889 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17890 CallResult.first, DAG.getIntPtrConstant(1));
17891 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17892 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17895 /// LowerOperation - Provide custom lowering hooks for some operations.
17897 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17898 switch (Op.getOpcode()) {
17899 default: llvm_unreachable("Should not custom lower this!");
17900 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17901 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17902 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17903 return LowerCMP_SWAP(Op, Subtarget, DAG);
17904 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17905 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17906 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17907 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17908 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17909 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17910 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17911 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17912 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17913 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17914 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17915 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17916 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17917 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17918 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17919 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17920 case ISD::SHL_PARTS:
17921 case ISD::SRA_PARTS:
17922 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17923 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17924 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17925 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17926 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17927 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17928 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17929 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17930 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17931 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17932 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17934 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17935 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17936 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17937 case ISD::SETCC: return LowerSETCC(Op, DAG);
17938 case ISD::SELECT: return LowerSELECT(Op, DAG);
17939 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17940 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17941 case ISD::VASTART: return LowerVASTART(Op, DAG);
17942 case ISD::VAARG: return LowerVAARG(Op, DAG);
17943 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17944 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17945 case ISD::INTRINSIC_VOID:
17946 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17947 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17948 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17949 case ISD::FRAME_TO_ARGS_OFFSET:
17950 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17951 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17952 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17953 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17954 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17955 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17956 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17957 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17958 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17959 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17960 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17961 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17962 case ISD::UMUL_LOHI:
17963 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17966 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17972 case ISD::UMULO: return LowerXALUO(Op, DAG);
17973 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17974 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17978 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17979 case ISD::ADD: return LowerADD(Op, DAG);
17980 case ISD::SUB: return LowerSUB(Op, DAG);
17981 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17985 /// ReplaceNodeResults - Replace a node with an illegal result type
17986 /// with a new node built out of custom code.
17987 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17988 SmallVectorImpl<SDValue>&Results,
17989 SelectionDAG &DAG) const {
17991 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17992 switch (N->getOpcode()) {
17994 llvm_unreachable("Do not know how to custom type legalize this operation!");
17995 case ISD::SIGN_EXTEND_INREG:
18000 // We don't want to expand or promote these.
18007 case ISD::UDIVREM: {
18008 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18009 Results.push_back(V);
18012 case ISD::FP_TO_SINT:
18013 case ISD::FP_TO_UINT: {
18014 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18016 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18019 std::pair<SDValue,SDValue> Vals =
18020 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18021 SDValue FIST = Vals.first, StackSlot = Vals.second;
18022 if (FIST.getNode()) {
18023 EVT VT = N->getValueType(0);
18024 // Return a load from the stack slot.
18025 if (StackSlot.getNode())
18026 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18027 MachinePointerInfo(),
18028 false, false, false, 0));
18030 Results.push_back(FIST);
18034 case ISD::UINT_TO_FP: {
18035 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18036 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18037 N->getValueType(0) != MVT::v2f32)
18039 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18041 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18043 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18044 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18045 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18046 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18047 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18048 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18051 case ISD::FP_ROUND: {
18052 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18054 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18055 Results.push_back(V);
18058 case ISD::INTRINSIC_W_CHAIN: {
18059 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18061 default : llvm_unreachable("Do not know how to custom type "
18062 "legalize this intrinsic operation!");
18063 case Intrinsic::x86_rdtsc:
18064 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18066 case Intrinsic::x86_rdtscp:
18067 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18069 case Intrinsic::x86_rdpmc:
18070 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18073 case ISD::READCYCLECOUNTER: {
18074 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18077 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18078 EVT T = N->getValueType(0);
18079 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18080 bool Regs64bit = T == MVT::i128;
18081 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18082 SDValue cpInL, cpInH;
18083 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18084 DAG.getConstant(0, HalfT));
18085 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18086 DAG.getConstant(1, HalfT));
18087 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18088 Regs64bit ? X86::RAX : X86::EAX,
18090 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18091 Regs64bit ? X86::RDX : X86::EDX,
18092 cpInH, cpInL.getValue(1));
18093 SDValue swapInL, swapInH;
18094 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18095 DAG.getConstant(0, HalfT));
18096 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18097 DAG.getConstant(1, HalfT));
18098 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18099 Regs64bit ? X86::RBX : X86::EBX,
18100 swapInL, cpInH.getValue(1));
18101 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18102 Regs64bit ? X86::RCX : X86::ECX,
18103 swapInH, swapInL.getValue(1));
18104 SDValue Ops[] = { swapInH.getValue(0),
18106 swapInH.getValue(1) };
18107 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18108 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18109 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18110 X86ISD::LCMPXCHG8_DAG;
18111 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18112 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18113 Regs64bit ? X86::RAX : X86::EAX,
18114 HalfT, Result.getValue(1));
18115 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18116 Regs64bit ? X86::RDX : X86::EDX,
18117 HalfT, cpOutL.getValue(2));
18118 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18120 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18121 MVT::i32, cpOutH.getValue(2));
18123 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18124 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18125 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18127 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18128 Results.push_back(Success);
18129 Results.push_back(EFLAGS.getValue(1));
18132 case ISD::ATOMIC_SWAP:
18133 case ISD::ATOMIC_LOAD_ADD:
18134 case ISD::ATOMIC_LOAD_SUB:
18135 case ISD::ATOMIC_LOAD_AND:
18136 case ISD::ATOMIC_LOAD_OR:
18137 case ISD::ATOMIC_LOAD_XOR:
18138 case ISD::ATOMIC_LOAD_NAND:
18139 case ISD::ATOMIC_LOAD_MIN:
18140 case ISD::ATOMIC_LOAD_MAX:
18141 case ISD::ATOMIC_LOAD_UMIN:
18142 case ISD::ATOMIC_LOAD_UMAX:
18143 case ISD::ATOMIC_LOAD: {
18144 // Delegate to generic TypeLegalization. Situations we can really handle
18145 // should have already been dealt with by AtomicExpandPass.cpp.
18148 case ISD::BITCAST: {
18149 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18150 EVT DstVT = N->getValueType(0);
18151 EVT SrcVT = N->getOperand(0)->getValueType(0);
18153 if (SrcVT != MVT::f64 ||
18154 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18157 unsigned NumElts = DstVT.getVectorNumElements();
18158 EVT SVT = DstVT.getVectorElementType();
18159 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18160 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18161 MVT::v2f64, N->getOperand(0));
18162 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18164 if (ExperimentalVectorWideningLegalization) {
18165 // If we are legalizing vectors by widening, we already have the desired
18166 // legal vector type, just return it.
18167 Results.push_back(ToVecInt);
18171 SmallVector<SDValue, 8> Elts;
18172 for (unsigned i = 0, e = NumElts; i != e; ++i)
18173 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18174 ToVecInt, DAG.getIntPtrConstant(i)));
18176 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18181 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18183 default: return nullptr;
18184 case X86ISD::BSF: return "X86ISD::BSF";
18185 case X86ISD::BSR: return "X86ISD::BSR";
18186 case X86ISD::SHLD: return "X86ISD::SHLD";
18187 case X86ISD::SHRD: return "X86ISD::SHRD";
18188 case X86ISD::FAND: return "X86ISD::FAND";
18189 case X86ISD::FANDN: return "X86ISD::FANDN";
18190 case X86ISD::FOR: return "X86ISD::FOR";
18191 case X86ISD::FXOR: return "X86ISD::FXOR";
18192 case X86ISD::FSRL: return "X86ISD::FSRL";
18193 case X86ISD::FILD: return "X86ISD::FILD";
18194 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18195 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18196 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18197 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18198 case X86ISD::FLD: return "X86ISD::FLD";
18199 case X86ISD::FST: return "X86ISD::FST";
18200 case X86ISD::CALL: return "X86ISD::CALL";
18201 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18202 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18203 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18204 case X86ISD::BT: return "X86ISD::BT";
18205 case X86ISD::CMP: return "X86ISD::CMP";
18206 case X86ISD::COMI: return "X86ISD::COMI";
18207 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18208 case X86ISD::CMPM: return "X86ISD::CMPM";
18209 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18210 case X86ISD::SETCC: return "X86ISD::SETCC";
18211 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18212 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18213 case X86ISD::CMOV: return "X86ISD::CMOV";
18214 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18215 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18216 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18217 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18218 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18219 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18220 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18221 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18222 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18223 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18224 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18225 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18226 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18227 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18228 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18229 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18230 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18231 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18232 case X86ISD::HADD: return "X86ISD::HADD";
18233 case X86ISD::HSUB: return "X86ISD::HSUB";
18234 case X86ISD::FHADD: return "X86ISD::FHADD";
18235 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18236 case X86ISD::UMAX: return "X86ISD::UMAX";
18237 case X86ISD::UMIN: return "X86ISD::UMIN";
18238 case X86ISD::SMAX: return "X86ISD::SMAX";
18239 case X86ISD::SMIN: return "X86ISD::SMIN";
18240 case X86ISD::FMAX: return "X86ISD::FMAX";
18241 case X86ISD::FMIN: return "X86ISD::FMIN";
18242 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18243 case X86ISD::FMINC: return "X86ISD::FMINC";
18244 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18245 case X86ISD::FRCP: return "X86ISD::FRCP";
18246 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18247 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18248 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18249 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18250 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18251 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18252 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18253 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18254 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18255 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18256 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18257 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18258 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18259 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18260 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18261 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18262 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18263 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18264 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18265 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18266 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18267 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18268 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18269 case X86ISD::VSHL: return "X86ISD::VSHL";
18270 case X86ISD::VSRL: return "X86ISD::VSRL";
18271 case X86ISD::VSRA: return "X86ISD::VSRA";
18272 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18273 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18274 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18275 case X86ISD::CMPP: return "X86ISD::CMPP";
18276 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18277 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18278 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18279 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18280 case X86ISD::ADD: return "X86ISD::ADD";
18281 case X86ISD::SUB: return "X86ISD::SUB";
18282 case X86ISD::ADC: return "X86ISD::ADC";
18283 case X86ISD::SBB: return "X86ISD::SBB";
18284 case X86ISD::SMUL: return "X86ISD::SMUL";
18285 case X86ISD::UMUL: return "X86ISD::UMUL";
18286 case X86ISD::INC: return "X86ISD::INC";
18287 case X86ISD::DEC: return "X86ISD::DEC";
18288 case X86ISD::OR: return "X86ISD::OR";
18289 case X86ISD::XOR: return "X86ISD::XOR";
18290 case X86ISD::AND: return "X86ISD::AND";
18291 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18292 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18293 case X86ISD::PTEST: return "X86ISD::PTEST";
18294 case X86ISD::TESTP: return "X86ISD::TESTP";
18295 case X86ISD::TESTM: return "X86ISD::TESTM";
18296 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18297 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18298 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18299 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18300 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18301 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18302 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18303 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18304 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18305 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18306 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18307 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18308 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18309 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18310 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18311 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18312 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18313 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18314 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18315 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18316 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18317 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18318 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18319 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18320 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18321 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18322 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18323 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18324 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18325 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18326 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18327 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18328 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18329 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18330 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18331 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18332 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18333 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18334 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18335 case X86ISD::SAHF: return "X86ISD::SAHF";
18336 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18337 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18338 case X86ISD::FMADD: return "X86ISD::FMADD";
18339 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18340 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18341 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18342 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18343 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18344 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18345 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18346 case X86ISD::XTEST: return "X86ISD::XTEST";
18350 // isLegalAddressingMode - Return true if the addressing mode represented
18351 // by AM is legal for this target, for a load/store of the specified type.
18352 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18354 // X86 supports extremely general addressing modes.
18355 CodeModel::Model M = getTargetMachine().getCodeModel();
18356 Reloc::Model R = getTargetMachine().getRelocationModel();
18358 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18359 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18364 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18366 // If a reference to this global requires an extra load, we can't fold it.
18367 if (isGlobalStubReference(GVFlags))
18370 // If BaseGV requires a register for the PIC base, we cannot also have a
18371 // BaseReg specified.
18372 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18375 // If lower 4G is not available, then we must use rip-relative addressing.
18376 if ((M != CodeModel::Small || R != Reloc::Static) &&
18377 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18381 switch (AM.Scale) {
18387 // These scales always work.
18392 // These scales are formed with basereg+scalereg. Only accept if there is
18397 default: // Other stuff never works.
18404 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18405 unsigned Bits = Ty->getScalarSizeInBits();
18407 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18408 // particularly cheaper than those without.
18412 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18413 // variable shifts just as cheap as scalar ones.
18414 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18417 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18418 // fully general vector.
18422 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18423 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18425 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18426 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18427 return NumBits1 > NumBits2;
18430 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18431 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18434 if (!isTypeLegal(EVT::getEVT(Ty1)))
18437 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18439 // Assuming the caller doesn't have a zeroext or signext return parameter,
18440 // truncation all the way down to i1 is valid.
18444 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18445 return isInt<32>(Imm);
18448 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18449 // Can also use sub to handle negated immediates.
18450 return isInt<32>(Imm);
18453 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18454 if (!VT1.isInteger() || !VT2.isInteger())
18456 unsigned NumBits1 = VT1.getSizeInBits();
18457 unsigned NumBits2 = VT2.getSizeInBits();
18458 return NumBits1 > NumBits2;
18461 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18462 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18463 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18466 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18467 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18468 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18471 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18472 EVT VT1 = Val.getValueType();
18473 if (isZExtFree(VT1, VT2))
18476 if (Val.getOpcode() != ISD::LOAD)
18479 if (!VT1.isSimple() || !VT1.isInteger() ||
18480 !VT2.isSimple() || !VT2.isInteger())
18483 switch (VT1.getSimpleVT().SimpleTy) {
18488 // X86 has 8, 16, and 32-bit zero-extending loads.
18496 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18497 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18500 VT = VT.getScalarType();
18502 if (!VT.isSimple())
18505 switch (VT.getSimpleVT().SimpleTy) {
18516 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18517 // i16 instructions are longer (0x66 prefix) and potentially slower.
18518 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18521 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18522 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18523 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18524 /// are assumed to be legal.
18526 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18528 if (!VT.isSimple())
18531 MVT SVT = VT.getSimpleVT();
18533 // Very little shuffling can be done for 64-bit vectors right now.
18534 if (VT.getSizeInBits() == 64)
18537 // If this is a single-input shuffle with no 128 bit lane crossings we can
18538 // lower it into pshufb.
18539 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18540 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18541 bool isLegal = true;
18542 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18543 if (M[I] >= (int)SVT.getVectorNumElements() ||
18544 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18553 // FIXME: blends, shifts.
18554 return (SVT.getVectorNumElements() == 2 ||
18555 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18556 isMOVLMask(M, SVT) ||
18557 isMOVHLPSMask(M, SVT) ||
18558 isSHUFPMask(M, SVT) ||
18559 isPSHUFDMask(M, SVT) ||
18560 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18561 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18562 isPALIGNRMask(M, SVT, Subtarget) ||
18563 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18564 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18565 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18566 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18567 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18571 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18573 if (!VT.isSimple())
18576 MVT SVT = VT.getSimpleVT();
18577 unsigned NumElts = SVT.getVectorNumElements();
18578 // FIXME: This collection of masks seems suspect.
18581 if (NumElts == 4 && SVT.is128BitVector()) {
18582 return (isMOVLMask(Mask, SVT) ||
18583 isCommutedMOVLMask(Mask, SVT, true) ||
18584 isSHUFPMask(Mask, SVT) ||
18585 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18590 //===----------------------------------------------------------------------===//
18591 // X86 Scheduler Hooks
18592 //===----------------------------------------------------------------------===//
18594 /// Utility function to emit xbegin specifying the start of an RTM region.
18595 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18596 const TargetInstrInfo *TII) {
18597 DebugLoc DL = MI->getDebugLoc();
18599 const BasicBlock *BB = MBB->getBasicBlock();
18600 MachineFunction::iterator I = MBB;
18603 // For the v = xbegin(), we generate
18614 MachineBasicBlock *thisMBB = MBB;
18615 MachineFunction *MF = MBB->getParent();
18616 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18617 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18618 MF->insert(I, mainMBB);
18619 MF->insert(I, sinkMBB);
18621 // Transfer the remainder of BB and its successor edges to sinkMBB.
18622 sinkMBB->splice(sinkMBB->begin(), MBB,
18623 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18624 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18628 // # fallthrough to mainMBB
18629 // # abortion to sinkMBB
18630 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18631 thisMBB->addSuccessor(mainMBB);
18632 thisMBB->addSuccessor(sinkMBB);
18636 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18637 mainMBB->addSuccessor(sinkMBB);
18640 // EAX is live into the sinkMBB
18641 sinkMBB->addLiveIn(X86::EAX);
18642 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18643 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18646 MI->eraseFromParent();
18650 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18651 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18652 // in the .td file.
18653 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18654 const TargetInstrInfo *TII) {
18656 switch (MI->getOpcode()) {
18657 default: llvm_unreachable("illegal opcode!");
18658 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18659 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18660 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18661 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18662 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18663 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18664 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18665 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18668 DebugLoc dl = MI->getDebugLoc();
18669 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18671 unsigned NumArgs = MI->getNumOperands();
18672 for (unsigned i = 1; i < NumArgs; ++i) {
18673 MachineOperand &Op = MI->getOperand(i);
18674 if (!(Op.isReg() && Op.isImplicit()))
18675 MIB.addOperand(Op);
18677 if (MI->hasOneMemOperand())
18678 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18680 BuildMI(*BB, MI, dl,
18681 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18682 .addReg(X86::XMM0);
18684 MI->eraseFromParent();
18688 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18689 // defs in an instruction pattern
18690 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18691 const TargetInstrInfo *TII) {
18693 switch (MI->getOpcode()) {
18694 default: llvm_unreachable("illegal opcode!");
18695 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18696 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18697 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18698 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18699 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18700 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18701 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18702 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18705 DebugLoc dl = MI->getDebugLoc();
18706 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18708 unsigned NumArgs = MI->getNumOperands(); // remove the results
18709 for (unsigned i = 1; i < NumArgs; ++i) {
18710 MachineOperand &Op = MI->getOperand(i);
18711 if (!(Op.isReg() && Op.isImplicit()))
18712 MIB.addOperand(Op);
18714 if (MI->hasOneMemOperand())
18715 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18717 BuildMI(*BB, MI, dl,
18718 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18721 MI->eraseFromParent();
18725 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18726 const TargetInstrInfo *TII,
18727 const X86Subtarget* Subtarget) {
18728 DebugLoc dl = MI->getDebugLoc();
18730 // Address into RAX/EAX, other two args into ECX, EDX.
18731 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18732 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18733 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18734 for (int i = 0; i < X86::AddrNumOperands; ++i)
18735 MIB.addOperand(MI->getOperand(i));
18737 unsigned ValOps = X86::AddrNumOperands;
18738 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18739 .addReg(MI->getOperand(ValOps).getReg());
18740 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18741 .addReg(MI->getOperand(ValOps+1).getReg());
18743 // The instruction doesn't actually take any operands though.
18744 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18746 MI->eraseFromParent(); // The pseudo is gone now.
18750 MachineBasicBlock *
18751 X86TargetLowering::EmitVAARG64WithCustomInserter(
18753 MachineBasicBlock *MBB) const {
18754 // Emit va_arg instruction on X86-64.
18756 // Operands to this pseudo-instruction:
18757 // 0 ) Output : destination address (reg)
18758 // 1-5) Input : va_list address (addr, i64mem)
18759 // 6 ) ArgSize : Size (in bytes) of vararg type
18760 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18761 // 8 ) Align : Alignment of type
18762 // 9 ) EFLAGS (implicit-def)
18764 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18765 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18767 unsigned DestReg = MI->getOperand(0).getReg();
18768 MachineOperand &Base = MI->getOperand(1);
18769 MachineOperand &Scale = MI->getOperand(2);
18770 MachineOperand &Index = MI->getOperand(3);
18771 MachineOperand &Disp = MI->getOperand(4);
18772 MachineOperand &Segment = MI->getOperand(5);
18773 unsigned ArgSize = MI->getOperand(6).getImm();
18774 unsigned ArgMode = MI->getOperand(7).getImm();
18775 unsigned Align = MI->getOperand(8).getImm();
18777 // Memory Reference
18778 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18779 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18780 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18782 // Machine Information
18783 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18784 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18785 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18786 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18787 DebugLoc DL = MI->getDebugLoc();
18789 // struct va_list {
18792 // i64 overflow_area (address)
18793 // i64 reg_save_area (address)
18795 // sizeof(va_list) = 24
18796 // alignment(va_list) = 8
18798 unsigned TotalNumIntRegs = 6;
18799 unsigned TotalNumXMMRegs = 8;
18800 bool UseGPOffset = (ArgMode == 1);
18801 bool UseFPOffset = (ArgMode == 2);
18802 unsigned MaxOffset = TotalNumIntRegs * 8 +
18803 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18805 /* Align ArgSize to a multiple of 8 */
18806 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18807 bool NeedsAlign = (Align > 8);
18809 MachineBasicBlock *thisMBB = MBB;
18810 MachineBasicBlock *overflowMBB;
18811 MachineBasicBlock *offsetMBB;
18812 MachineBasicBlock *endMBB;
18814 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18815 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18816 unsigned OffsetReg = 0;
18818 if (!UseGPOffset && !UseFPOffset) {
18819 // If we only pull from the overflow region, we don't create a branch.
18820 // We don't need to alter control flow.
18821 OffsetDestReg = 0; // unused
18822 OverflowDestReg = DestReg;
18824 offsetMBB = nullptr;
18825 overflowMBB = thisMBB;
18828 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18829 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18830 // If not, pull from overflow_area. (branch to overflowMBB)
18835 // offsetMBB overflowMBB
18840 // Registers for the PHI in endMBB
18841 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18842 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18844 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18845 MachineFunction *MF = MBB->getParent();
18846 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18847 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18848 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18850 MachineFunction::iterator MBBIter = MBB;
18853 // Insert the new basic blocks
18854 MF->insert(MBBIter, offsetMBB);
18855 MF->insert(MBBIter, overflowMBB);
18856 MF->insert(MBBIter, endMBB);
18858 // Transfer the remainder of MBB and its successor edges to endMBB.
18859 endMBB->splice(endMBB->begin(), thisMBB,
18860 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18861 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18863 // Make offsetMBB and overflowMBB successors of thisMBB
18864 thisMBB->addSuccessor(offsetMBB);
18865 thisMBB->addSuccessor(overflowMBB);
18867 // endMBB is a successor of both offsetMBB and overflowMBB
18868 offsetMBB->addSuccessor(endMBB);
18869 overflowMBB->addSuccessor(endMBB);
18871 // Load the offset value into a register
18872 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18873 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18877 .addDisp(Disp, UseFPOffset ? 4 : 0)
18878 .addOperand(Segment)
18879 .setMemRefs(MMOBegin, MMOEnd);
18881 // Check if there is enough room left to pull this argument.
18882 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18884 .addImm(MaxOffset + 8 - ArgSizeA8);
18886 // Branch to "overflowMBB" if offset >= max
18887 // Fall through to "offsetMBB" otherwise
18888 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18889 .addMBB(overflowMBB);
18892 // In offsetMBB, emit code to use the reg_save_area.
18894 assert(OffsetReg != 0);
18896 // Read the reg_save_area address.
18897 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18898 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18903 .addOperand(Segment)
18904 .setMemRefs(MMOBegin, MMOEnd);
18906 // Zero-extend the offset
18907 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18908 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18911 .addImm(X86::sub_32bit);
18913 // Add the offset to the reg_save_area to get the final address.
18914 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18915 .addReg(OffsetReg64)
18916 .addReg(RegSaveReg);
18918 // Compute the offset for the next argument
18919 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18920 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18922 .addImm(UseFPOffset ? 16 : 8);
18924 // Store it back into the va_list.
18925 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18929 .addDisp(Disp, UseFPOffset ? 4 : 0)
18930 .addOperand(Segment)
18931 .addReg(NextOffsetReg)
18932 .setMemRefs(MMOBegin, MMOEnd);
18935 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18940 // Emit code to use overflow area
18943 // Load the overflow_area address into a register.
18944 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18945 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18950 .addOperand(Segment)
18951 .setMemRefs(MMOBegin, MMOEnd);
18953 // If we need to align it, do so. Otherwise, just copy the address
18954 // to OverflowDestReg.
18956 // Align the overflow address
18957 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18958 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18960 // aligned_addr = (addr + (align-1)) & ~(align-1)
18961 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18962 .addReg(OverflowAddrReg)
18965 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18967 .addImm(~(uint64_t)(Align-1));
18969 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18970 .addReg(OverflowAddrReg);
18973 // Compute the next overflow address after this argument.
18974 // (the overflow address should be kept 8-byte aligned)
18975 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18976 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18977 .addReg(OverflowDestReg)
18978 .addImm(ArgSizeA8);
18980 // Store the new overflow address.
18981 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18986 .addOperand(Segment)
18987 .addReg(NextAddrReg)
18988 .setMemRefs(MMOBegin, MMOEnd);
18990 // If we branched, emit the PHI to the front of endMBB.
18992 BuildMI(*endMBB, endMBB->begin(), DL,
18993 TII->get(X86::PHI), DestReg)
18994 .addReg(OffsetDestReg).addMBB(offsetMBB)
18995 .addReg(OverflowDestReg).addMBB(overflowMBB);
18998 // Erase the pseudo instruction
18999 MI->eraseFromParent();
19004 MachineBasicBlock *
19005 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19007 MachineBasicBlock *MBB) const {
19008 // Emit code to save XMM registers to the stack. The ABI says that the
19009 // number of registers to save is given in %al, so it's theoretically
19010 // possible to do an indirect jump trick to avoid saving all of them,
19011 // however this code takes a simpler approach and just executes all
19012 // of the stores if %al is non-zero. It's less code, and it's probably
19013 // easier on the hardware branch predictor, and stores aren't all that
19014 // expensive anyway.
19016 // Create the new basic blocks. One block contains all the XMM stores,
19017 // and one block is the final destination regardless of whether any
19018 // stores were performed.
19019 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19020 MachineFunction *F = MBB->getParent();
19021 MachineFunction::iterator MBBIter = MBB;
19023 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19024 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19025 F->insert(MBBIter, XMMSaveMBB);
19026 F->insert(MBBIter, EndMBB);
19028 // Transfer the remainder of MBB and its successor edges to EndMBB.
19029 EndMBB->splice(EndMBB->begin(), MBB,
19030 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19031 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19033 // The original block will now fall through to the XMM save block.
19034 MBB->addSuccessor(XMMSaveMBB);
19035 // The XMMSaveMBB will fall through to the end block.
19036 XMMSaveMBB->addSuccessor(EndMBB);
19038 // Now add the instructions.
19039 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19040 DebugLoc DL = MI->getDebugLoc();
19042 unsigned CountReg = MI->getOperand(0).getReg();
19043 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19044 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19046 if (!Subtarget->isTargetWin64()) {
19047 // If %al is 0, branch around the XMM save block.
19048 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19049 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19050 MBB->addSuccessor(EndMBB);
19053 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19054 // that was just emitted, but clearly shouldn't be "saved".
19055 assert((MI->getNumOperands() <= 3 ||
19056 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19057 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19058 && "Expected last argument to be EFLAGS");
19059 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19060 // In the XMM save block, save all the XMM argument registers.
19061 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19062 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19063 MachineMemOperand *MMO =
19064 F->getMachineMemOperand(
19065 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19066 MachineMemOperand::MOStore,
19067 /*Size=*/16, /*Align=*/16);
19068 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19069 .addFrameIndex(RegSaveFrameIndex)
19070 .addImm(/*Scale=*/1)
19071 .addReg(/*IndexReg=*/0)
19072 .addImm(/*Disp=*/Offset)
19073 .addReg(/*Segment=*/0)
19074 .addReg(MI->getOperand(i).getReg())
19075 .addMemOperand(MMO);
19078 MI->eraseFromParent(); // The pseudo instruction is gone now.
19083 // The EFLAGS operand of SelectItr might be missing a kill marker
19084 // because there were multiple uses of EFLAGS, and ISel didn't know
19085 // which to mark. Figure out whether SelectItr should have had a
19086 // kill marker, and set it if it should. Returns the correct kill
19088 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19089 MachineBasicBlock* BB,
19090 const TargetRegisterInfo* TRI) {
19091 // Scan forward through BB for a use/def of EFLAGS.
19092 MachineBasicBlock::iterator miI(std::next(SelectItr));
19093 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19094 const MachineInstr& mi = *miI;
19095 if (mi.readsRegister(X86::EFLAGS))
19097 if (mi.definesRegister(X86::EFLAGS))
19098 break; // Should have kill-flag - update below.
19101 // If we hit the end of the block, check whether EFLAGS is live into a
19103 if (miI == BB->end()) {
19104 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19105 sEnd = BB->succ_end();
19106 sItr != sEnd; ++sItr) {
19107 MachineBasicBlock* succ = *sItr;
19108 if (succ->isLiveIn(X86::EFLAGS))
19113 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19114 // out. SelectMI should have a kill flag on EFLAGS.
19115 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19119 MachineBasicBlock *
19120 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19121 MachineBasicBlock *BB) const {
19122 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19123 DebugLoc DL = MI->getDebugLoc();
19125 // To "insert" a SELECT_CC instruction, we actually have to insert the
19126 // diamond control-flow pattern. The incoming instruction knows the
19127 // destination vreg to set, the condition code register to branch on, the
19128 // true/false values to select between, and a branch opcode to use.
19129 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19130 MachineFunction::iterator It = BB;
19136 // cmpTY ccX, r1, r2
19138 // fallthrough --> copy0MBB
19139 MachineBasicBlock *thisMBB = BB;
19140 MachineFunction *F = BB->getParent();
19141 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19142 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19143 F->insert(It, copy0MBB);
19144 F->insert(It, sinkMBB);
19146 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19147 // live into the sink and copy blocks.
19148 const TargetRegisterInfo *TRI =
19149 BB->getParent()->getSubtarget().getRegisterInfo();
19150 if (!MI->killsRegister(X86::EFLAGS) &&
19151 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19152 copy0MBB->addLiveIn(X86::EFLAGS);
19153 sinkMBB->addLiveIn(X86::EFLAGS);
19156 // Transfer the remainder of BB and its successor edges to sinkMBB.
19157 sinkMBB->splice(sinkMBB->begin(), BB,
19158 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19159 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19161 // Add the true and fallthrough blocks as its successors.
19162 BB->addSuccessor(copy0MBB);
19163 BB->addSuccessor(sinkMBB);
19165 // Create the conditional branch instruction.
19167 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19168 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19171 // %FalseValue = ...
19172 // # fallthrough to sinkMBB
19173 copy0MBB->addSuccessor(sinkMBB);
19176 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19178 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19179 TII->get(X86::PHI), MI->getOperand(0).getReg())
19180 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19181 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19183 MI->eraseFromParent(); // The pseudo instruction is gone now.
19187 MachineBasicBlock *
19188 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19189 MachineBasicBlock *BB) const {
19190 MachineFunction *MF = BB->getParent();
19191 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19192 DebugLoc DL = MI->getDebugLoc();
19193 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19195 assert(MF->shouldSplitStack());
19197 const bool Is64Bit = Subtarget->is64Bit();
19198 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19200 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19201 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19204 // ... [Till the alloca]
19205 // If stacklet is not large enough, jump to mallocMBB
19208 // Allocate by subtracting from RSP
19209 // Jump to continueMBB
19212 // Allocate by call to runtime
19216 // [rest of original BB]
19219 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19220 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19221 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19223 MachineRegisterInfo &MRI = MF->getRegInfo();
19224 const TargetRegisterClass *AddrRegClass =
19225 getRegClassFor(getPointerTy());
19227 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19228 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19229 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19230 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19231 sizeVReg = MI->getOperand(1).getReg(),
19232 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19234 MachineFunction::iterator MBBIter = BB;
19237 MF->insert(MBBIter, bumpMBB);
19238 MF->insert(MBBIter, mallocMBB);
19239 MF->insert(MBBIter, continueMBB);
19241 continueMBB->splice(continueMBB->begin(), BB,
19242 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19243 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19245 // Add code to the main basic block to check if the stack limit has been hit,
19246 // and if so, jump to mallocMBB otherwise to bumpMBB.
19247 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19248 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19249 .addReg(tmpSPVReg).addReg(sizeVReg);
19250 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19251 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19252 .addReg(SPLimitVReg);
19253 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19255 // bumpMBB simply decreases the stack pointer, since we know the current
19256 // stacklet has enough space.
19257 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19258 .addReg(SPLimitVReg);
19259 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19260 .addReg(SPLimitVReg);
19261 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19263 // Calls into a routine in libgcc to allocate more space from the heap.
19264 const uint32_t *RegMask = MF->getTarget()
19265 .getSubtargetImpl()
19266 ->getRegisterInfo()
19267 ->getCallPreservedMask(CallingConv::C);
19269 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19271 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19272 .addExternalSymbol("__morestack_allocate_stack_space")
19273 .addRegMask(RegMask)
19274 .addReg(X86::RDI, RegState::Implicit)
19275 .addReg(X86::RAX, RegState::ImplicitDefine);
19276 } else if (Is64Bit) {
19277 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19279 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19280 .addExternalSymbol("__morestack_allocate_stack_space")
19281 .addRegMask(RegMask)
19282 .addReg(X86::EDI, RegState::Implicit)
19283 .addReg(X86::EAX, RegState::ImplicitDefine);
19285 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19287 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19288 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19289 .addExternalSymbol("__morestack_allocate_stack_space")
19290 .addRegMask(RegMask)
19291 .addReg(X86::EAX, RegState::ImplicitDefine);
19295 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19298 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19299 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19300 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19302 // Set up the CFG correctly.
19303 BB->addSuccessor(bumpMBB);
19304 BB->addSuccessor(mallocMBB);
19305 mallocMBB->addSuccessor(continueMBB);
19306 bumpMBB->addSuccessor(continueMBB);
19308 // Take care of the PHI nodes.
19309 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19310 MI->getOperand(0).getReg())
19311 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19312 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19314 // Delete the original pseudo instruction.
19315 MI->eraseFromParent();
19318 return continueMBB;
19321 MachineBasicBlock *
19322 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19323 MachineBasicBlock *BB) const {
19324 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19325 DebugLoc DL = MI->getDebugLoc();
19327 assert(!Subtarget->isTargetMacho());
19329 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19330 // non-trivial part is impdef of ESP.
19332 if (Subtarget->isTargetWin64()) {
19333 if (Subtarget->isTargetCygMing()) {
19334 // ___chkstk(Mingw64):
19335 // Clobbers R10, R11, RAX and EFLAGS.
19337 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19338 .addExternalSymbol("___chkstk")
19339 .addReg(X86::RAX, RegState::Implicit)
19340 .addReg(X86::RSP, RegState::Implicit)
19341 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19342 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19343 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19345 // __chkstk(MSVCRT): does not update stack pointer.
19346 // Clobbers R10, R11 and EFLAGS.
19347 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19348 .addExternalSymbol("__chkstk")
19349 .addReg(X86::RAX, RegState::Implicit)
19350 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19351 // RAX has the offset to be subtracted from RSP.
19352 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19357 const char *StackProbeSymbol =
19358 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19360 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19361 .addExternalSymbol(StackProbeSymbol)
19362 .addReg(X86::EAX, RegState::Implicit)
19363 .addReg(X86::ESP, RegState::Implicit)
19364 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19365 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19366 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19369 MI->eraseFromParent(); // The pseudo instruction is gone now.
19373 MachineBasicBlock *
19374 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19375 MachineBasicBlock *BB) const {
19376 // This is pretty easy. We're taking the value that we received from
19377 // our load from the relocation, sticking it in either RDI (x86-64)
19378 // or EAX and doing an indirect call. The return value will then
19379 // be in the normal return register.
19380 MachineFunction *F = BB->getParent();
19381 const X86InstrInfo *TII =
19382 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19383 DebugLoc DL = MI->getDebugLoc();
19385 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19386 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19388 // Get a register mask for the lowered call.
19389 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19390 // proper register mask.
19391 const uint32_t *RegMask = F->getTarget()
19392 .getSubtargetImpl()
19393 ->getRegisterInfo()
19394 ->getCallPreservedMask(CallingConv::C);
19395 if (Subtarget->is64Bit()) {
19396 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19397 TII->get(X86::MOV64rm), X86::RDI)
19399 .addImm(0).addReg(0)
19400 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19401 MI->getOperand(3).getTargetFlags())
19403 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19404 addDirectMem(MIB, X86::RDI);
19405 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19406 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19407 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19408 TII->get(X86::MOV32rm), X86::EAX)
19410 .addImm(0).addReg(0)
19411 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19412 MI->getOperand(3).getTargetFlags())
19414 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19415 addDirectMem(MIB, X86::EAX);
19416 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19418 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19419 TII->get(X86::MOV32rm), X86::EAX)
19420 .addReg(TII->getGlobalBaseReg(F))
19421 .addImm(0).addReg(0)
19422 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19423 MI->getOperand(3).getTargetFlags())
19425 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19426 addDirectMem(MIB, X86::EAX);
19427 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19430 MI->eraseFromParent(); // The pseudo instruction is gone now.
19434 MachineBasicBlock *
19435 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19436 MachineBasicBlock *MBB) const {
19437 DebugLoc DL = MI->getDebugLoc();
19438 MachineFunction *MF = MBB->getParent();
19439 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19440 MachineRegisterInfo &MRI = MF->getRegInfo();
19442 const BasicBlock *BB = MBB->getBasicBlock();
19443 MachineFunction::iterator I = MBB;
19446 // Memory Reference
19447 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19448 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19451 unsigned MemOpndSlot = 0;
19453 unsigned CurOp = 0;
19455 DstReg = MI->getOperand(CurOp++).getReg();
19456 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19457 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19458 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19459 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19461 MemOpndSlot = CurOp;
19463 MVT PVT = getPointerTy();
19464 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19465 "Invalid Pointer Size!");
19467 // For v = setjmp(buf), we generate
19470 // buf[LabelOffset] = restoreMBB
19471 // SjLjSetup restoreMBB
19477 // v = phi(main, restore)
19482 MachineBasicBlock *thisMBB = MBB;
19483 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19484 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19485 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19486 MF->insert(I, mainMBB);
19487 MF->insert(I, sinkMBB);
19488 MF->push_back(restoreMBB);
19490 MachineInstrBuilder MIB;
19492 // Transfer the remainder of BB and its successor edges to sinkMBB.
19493 sinkMBB->splice(sinkMBB->begin(), MBB,
19494 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19495 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19498 unsigned PtrStoreOpc = 0;
19499 unsigned LabelReg = 0;
19500 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19501 Reloc::Model RM = MF->getTarget().getRelocationModel();
19502 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19503 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19505 // Prepare IP either in reg or imm.
19506 if (!UseImmLabel) {
19507 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19508 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19509 LabelReg = MRI.createVirtualRegister(PtrRC);
19510 if (Subtarget->is64Bit()) {
19511 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19515 .addMBB(restoreMBB)
19518 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19519 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19520 .addReg(XII->getGlobalBaseReg(MF))
19523 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19527 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19529 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19530 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19531 if (i == X86::AddrDisp)
19532 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19534 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19537 MIB.addReg(LabelReg);
19539 MIB.addMBB(restoreMBB);
19540 MIB.setMemRefs(MMOBegin, MMOEnd);
19542 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19543 .addMBB(restoreMBB);
19545 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19546 MF->getSubtarget().getRegisterInfo());
19547 MIB.addRegMask(RegInfo->getNoPreservedMask());
19548 thisMBB->addSuccessor(mainMBB);
19549 thisMBB->addSuccessor(restoreMBB);
19553 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19554 mainMBB->addSuccessor(sinkMBB);
19557 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19558 TII->get(X86::PHI), DstReg)
19559 .addReg(mainDstReg).addMBB(mainMBB)
19560 .addReg(restoreDstReg).addMBB(restoreMBB);
19563 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19564 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19565 restoreMBB->addSuccessor(sinkMBB);
19567 MI->eraseFromParent();
19571 MachineBasicBlock *
19572 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19573 MachineBasicBlock *MBB) const {
19574 DebugLoc DL = MI->getDebugLoc();
19575 MachineFunction *MF = MBB->getParent();
19576 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19577 MachineRegisterInfo &MRI = MF->getRegInfo();
19579 // Memory Reference
19580 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19581 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19583 MVT PVT = getPointerTy();
19584 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19585 "Invalid Pointer Size!");
19587 const TargetRegisterClass *RC =
19588 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19589 unsigned Tmp = MRI.createVirtualRegister(RC);
19590 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19591 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19592 MF->getSubtarget().getRegisterInfo());
19593 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19594 unsigned SP = RegInfo->getStackRegister();
19596 MachineInstrBuilder MIB;
19598 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19599 const int64_t SPOffset = 2 * PVT.getStoreSize();
19601 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19602 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19605 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19606 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19607 MIB.addOperand(MI->getOperand(i));
19608 MIB.setMemRefs(MMOBegin, MMOEnd);
19610 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19611 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19612 if (i == X86::AddrDisp)
19613 MIB.addDisp(MI->getOperand(i), LabelOffset);
19615 MIB.addOperand(MI->getOperand(i));
19617 MIB.setMemRefs(MMOBegin, MMOEnd);
19619 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19620 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19621 if (i == X86::AddrDisp)
19622 MIB.addDisp(MI->getOperand(i), SPOffset);
19624 MIB.addOperand(MI->getOperand(i));
19626 MIB.setMemRefs(MMOBegin, MMOEnd);
19628 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19630 MI->eraseFromParent();
19634 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19635 // accumulator loops. Writing back to the accumulator allows the coalescer
19636 // to remove extra copies in the loop.
19637 MachineBasicBlock *
19638 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19639 MachineBasicBlock *MBB) const {
19640 MachineOperand &AddendOp = MI->getOperand(3);
19642 // Bail out early if the addend isn't a register - we can't switch these.
19643 if (!AddendOp.isReg())
19646 MachineFunction &MF = *MBB->getParent();
19647 MachineRegisterInfo &MRI = MF.getRegInfo();
19649 // Check whether the addend is defined by a PHI:
19650 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19651 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19652 if (!AddendDef.isPHI())
19655 // Look for the following pattern:
19657 // %addend = phi [%entry, 0], [%loop, %result]
19659 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19663 // %addend = phi [%entry, 0], [%loop, %result]
19665 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19667 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19668 assert(AddendDef.getOperand(i).isReg());
19669 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19670 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19671 if (&PHISrcInst == MI) {
19672 // Found a matching instruction.
19673 unsigned NewFMAOpc = 0;
19674 switch (MI->getOpcode()) {
19675 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19676 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19677 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19678 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19679 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19680 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19681 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19682 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19683 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19684 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19685 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19686 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19687 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19688 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19689 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19690 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19691 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19692 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19693 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19694 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19695 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19696 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19697 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19698 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19699 default: llvm_unreachable("Unrecognized FMA variant.");
19702 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19703 MachineInstrBuilder MIB =
19704 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19705 .addOperand(MI->getOperand(0))
19706 .addOperand(MI->getOperand(3))
19707 .addOperand(MI->getOperand(2))
19708 .addOperand(MI->getOperand(1));
19709 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19710 MI->eraseFromParent();
19717 MachineBasicBlock *
19718 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19719 MachineBasicBlock *BB) const {
19720 switch (MI->getOpcode()) {
19721 default: llvm_unreachable("Unexpected instr type to insert");
19722 case X86::TAILJMPd64:
19723 case X86::TAILJMPr64:
19724 case X86::TAILJMPm64:
19725 llvm_unreachable("TAILJMP64 would not be touched here.");
19726 case X86::TCRETURNdi64:
19727 case X86::TCRETURNri64:
19728 case X86::TCRETURNmi64:
19730 case X86::WIN_ALLOCA:
19731 return EmitLoweredWinAlloca(MI, BB);
19732 case X86::SEG_ALLOCA_32:
19733 case X86::SEG_ALLOCA_64:
19734 return EmitLoweredSegAlloca(MI, BB);
19735 case X86::TLSCall_32:
19736 case X86::TLSCall_64:
19737 return EmitLoweredTLSCall(MI, BB);
19738 case X86::CMOV_GR8:
19739 case X86::CMOV_FR32:
19740 case X86::CMOV_FR64:
19741 case X86::CMOV_V4F32:
19742 case X86::CMOV_V2F64:
19743 case X86::CMOV_V2I64:
19744 case X86::CMOV_V8F32:
19745 case X86::CMOV_V4F64:
19746 case X86::CMOV_V4I64:
19747 case X86::CMOV_V16F32:
19748 case X86::CMOV_V8F64:
19749 case X86::CMOV_V8I64:
19750 case X86::CMOV_GR16:
19751 case X86::CMOV_GR32:
19752 case X86::CMOV_RFP32:
19753 case X86::CMOV_RFP64:
19754 case X86::CMOV_RFP80:
19755 return EmitLoweredSelect(MI, BB);
19757 case X86::FP32_TO_INT16_IN_MEM:
19758 case X86::FP32_TO_INT32_IN_MEM:
19759 case X86::FP32_TO_INT64_IN_MEM:
19760 case X86::FP64_TO_INT16_IN_MEM:
19761 case X86::FP64_TO_INT32_IN_MEM:
19762 case X86::FP64_TO_INT64_IN_MEM:
19763 case X86::FP80_TO_INT16_IN_MEM:
19764 case X86::FP80_TO_INT32_IN_MEM:
19765 case X86::FP80_TO_INT64_IN_MEM: {
19766 MachineFunction *F = BB->getParent();
19767 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19768 DebugLoc DL = MI->getDebugLoc();
19770 // Change the floating point control register to use "round towards zero"
19771 // mode when truncating to an integer value.
19772 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19773 addFrameReference(BuildMI(*BB, MI, DL,
19774 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19776 // Load the old value of the high byte of the control word...
19778 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19779 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19782 // Set the high part to be round to zero...
19783 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19786 // Reload the modified control word now...
19787 addFrameReference(BuildMI(*BB, MI, DL,
19788 TII->get(X86::FLDCW16m)), CWFrameIdx);
19790 // Restore the memory image of control word to original value
19791 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19794 // Get the X86 opcode to use.
19796 switch (MI->getOpcode()) {
19797 default: llvm_unreachable("illegal opcode!");
19798 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19799 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19800 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19801 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19802 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19803 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19804 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19805 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19806 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19810 MachineOperand &Op = MI->getOperand(0);
19812 AM.BaseType = X86AddressMode::RegBase;
19813 AM.Base.Reg = Op.getReg();
19815 AM.BaseType = X86AddressMode::FrameIndexBase;
19816 AM.Base.FrameIndex = Op.getIndex();
19818 Op = MI->getOperand(1);
19820 AM.Scale = Op.getImm();
19821 Op = MI->getOperand(2);
19823 AM.IndexReg = Op.getImm();
19824 Op = MI->getOperand(3);
19825 if (Op.isGlobal()) {
19826 AM.GV = Op.getGlobal();
19828 AM.Disp = Op.getImm();
19830 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19831 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19833 // Reload the original control word now.
19834 addFrameReference(BuildMI(*BB, MI, DL,
19835 TII->get(X86::FLDCW16m)), CWFrameIdx);
19837 MI->eraseFromParent(); // The pseudo instruction is gone now.
19840 // String/text processing lowering.
19841 case X86::PCMPISTRM128REG:
19842 case X86::VPCMPISTRM128REG:
19843 case X86::PCMPISTRM128MEM:
19844 case X86::VPCMPISTRM128MEM:
19845 case X86::PCMPESTRM128REG:
19846 case X86::VPCMPESTRM128REG:
19847 case X86::PCMPESTRM128MEM:
19848 case X86::VPCMPESTRM128MEM:
19849 assert(Subtarget->hasSSE42() &&
19850 "Target must have SSE4.2 or AVX features enabled");
19851 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19853 // String/text processing lowering.
19854 case X86::PCMPISTRIREG:
19855 case X86::VPCMPISTRIREG:
19856 case X86::PCMPISTRIMEM:
19857 case X86::VPCMPISTRIMEM:
19858 case X86::PCMPESTRIREG:
19859 case X86::VPCMPESTRIREG:
19860 case X86::PCMPESTRIMEM:
19861 case X86::VPCMPESTRIMEM:
19862 assert(Subtarget->hasSSE42() &&
19863 "Target must have SSE4.2 or AVX features enabled");
19864 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19866 // Thread synchronization.
19868 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19873 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19875 case X86::VASTART_SAVE_XMM_REGS:
19876 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19878 case X86::VAARG_64:
19879 return EmitVAARG64WithCustomInserter(MI, BB);
19881 case X86::EH_SjLj_SetJmp32:
19882 case X86::EH_SjLj_SetJmp64:
19883 return emitEHSjLjSetJmp(MI, BB);
19885 case X86::EH_SjLj_LongJmp32:
19886 case X86::EH_SjLj_LongJmp64:
19887 return emitEHSjLjLongJmp(MI, BB);
19889 case TargetOpcode::STACKMAP:
19890 case TargetOpcode::PATCHPOINT:
19891 return emitPatchPoint(MI, BB);
19893 case X86::VFMADDPDr213r:
19894 case X86::VFMADDPSr213r:
19895 case X86::VFMADDSDr213r:
19896 case X86::VFMADDSSr213r:
19897 case X86::VFMSUBPDr213r:
19898 case X86::VFMSUBPSr213r:
19899 case X86::VFMSUBSDr213r:
19900 case X86::VFMSUBSSr213r:
19901 case X86::VFNMADDPDr213r:
19902 case X86::VFNMADDPSr213r:
19903 case X86::VFNMADDSDr213r:
19904 case X86::VFNMADDSSr213r:
19905 case X86::VFNMSUBPDr213r:
19906 case X86::VFNMSUBPSr213r:
19907 case X86::VFNMSUBSDr213r:
19908 case X86::VFNMSUBSSr213r:
19909 case X86::VFMADDPDr213rY:
19910 case X86::VFMADDPSr213rY:
19911 case X86::VFMSUBPDr213rY:
19912 case X86::VFMSUBPSr213rY:
19913 case X86::VFNMADDPDr213rY:
19914 case X86::VFNMADDPSr213rY:
19915 case X86::VFNMSUBPDr213rY:
19916 case X86::VFNMSUBPSr213rY:
19917 return emitFMA3Instr(MI, BB);
19921 //===----------------------------------------------------------------------===//
19922 // X86 Optimization Hooks
19923 //===----------------------------------------------------------------------===//
19925 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19928 const SelectionDAG &DAG,
19929 unsigned Depth) const {
19930 unsigned BitWidth = KnownZero.getBitWidth();
19931 unsigned Opc = Op.getOpcode();
19932 assert((Opc >= ISD::BUILTIN_OP_END ||
19933 Opc == ISD::INTRINSIC_WO_CHAIN ||
19934 Opc == ISD::INTRINSIC_W_CHAIN ||
19935 Opc == ISD::INTRINSIC_VOID) &&
19936 "Should use MaskedValueIsZero if you don't know whether Op"
19937 " is a target node!");
19939 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19953 // These nodes' second result is a boolean.
19954 if (Op.getResNo() == 0)
19957 case X86ISD::SETCC:
19958 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19960 case ISD::INTRINSIC_WO_CHAIN: {
19961 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19962 unsigned NumLoBits = 0;
19965 case Intrinsic::x86_sse_movmsk_ps:
19966 case Intrinsic::x86_avx_movmsk_ps_256:
19967 case Intrinsic::x86_sse2_movmsk_pd:
19968 case Intrinsic::x86_avx_movmsk_pd_256:
19969 case Intrinsic::x86_mmx_pmovmskb:
19970 case Intrinsic::x86_sse2_pmovmskb_128:
19971 case Intrinsic::x86_avx2_pmovmskb: {
19972 // High bits of movmskp{s|d}, pmovmskb are known zero.
19974 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19975 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19976 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19977 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19978 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19979 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19980 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19981 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19983 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19992 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19994 const SelectionDAG &,
19995 unsigned Depth) const {
19996 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19997 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19998 return Op.getValueType().getScalarType().getSizeInBits();
20004 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20005 /// node is a GlobalAddress + offset.
20006 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20007 const GlobalValue* &GA,
20008 int64_t &Offset) const {
20009 if (N->getOpcode() == X86ISD::Wrapper) {
20010 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20011 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20012 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20016 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20019 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20020 /// same as extracting the high 128-bit part of 256-bit vector and then
20021 /// inserting the result into the low part of a new 256-bit vector
20022 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20023 EVT VT = SVOp->getValueType(0);
20024 unsigned NumElems = VT.getVectorNumElements();
20026 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20027 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20028 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20029 SVOp->getMaskElt(j) >= 0)
20035 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20036 /// same as extracting the low 128-bit part of 256-bit vector and then
20037 /// inserting the result into the high part of a new 256-bit vector
20038 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20039 EVT VT = SVOp->getValueType(0);
20040 unsigned NumElems = VT.getVectorNumElements();
20042 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20043 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20044 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20045 SVOp->getMaskElt(j) >= 0)
20051 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20052 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20053 TargetLowering::DAGCombinerInfo &DCI,
20054 const X86Subtarget* Subtarget) {
20056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20057 SDValue V1 = SVOp->getOperand(0);
20058 SDValue V2 = SVOp->getOperand(1);
20059 EVT VT = SVOp->getValueType(0);
20060 unsigned NumElems = VT.getVectorNumElements();
20062 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20063 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20067 // V UNDEF BUILD_VECTOR UNDEF
20069 // CONCAT_VECTOR CONCAT_VECTOR
20072 // RESULT: V + zero extended
20074 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20075 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20076 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20079 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20082 // To match the shuffle mask, the first half of the mask should
20083 // be exactly the first vector, and all the rest a splat with the
20084 // first element of the second one.
20085 for (unsigned i = 0; i != NumElems/2; ++i)
20086 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20087 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20090 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20091 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20092 if (Ld->hasNUsesOfValue(1, 0)) {
20093 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20094 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20096 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20098 Ld->getPointerInfo(),
20099 Ld->getAlignment(),
20100 false/*isVolatile*/, true/*ReadMem*/,
20101 false/*WriteMem*/);
20103 // Make sure the newly-created LOAD is in the same position as Ld in
20104 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20105 // and update uses of Ld's output chain to use the TokenFactor.
20106 if (Ld->hasAnyUseOfValue(1)) {
20107 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20108 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20109 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20110 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20111 SDValue(ResNode.getNode(), 1));
20114 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20118 // Emit a zeroed vector and insert the desired subvector on its
20120 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20121 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20122 return DCI.CombineTo(N, InsV);
20125 //===--------------------------------------------------------------------===//
20126 // Combine some shuffles into subvector extracts and inserts:
20129 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20130 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20131 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20132 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20133 return DCI.CombineTo(N, InsV);
20136 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20137 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20138 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20139 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20140 return DCI.CombineTo(N, InsV);
20146 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20149 /// This is the leaf of the recursive combinine below. When we have found some
20150 /// chain of single-use x86 shuffle instructions and accumulated the combined
20151 /// shuffle mask represented by them, this will try to pattern match that mask
20152 /// into either a single instruction if there is a special purpose instruction
20153 /// for this operation, or into a PSHUFB instruction which is a fully general
20154 /// instruction but should only be used to replace chains over a certain depth.
20155 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20156 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20157 TargetLowering::DAGCombinerInfo &DCI,
20158 const X86Subtarget *Subtarget) {
20159 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20161 // Find the operand that enters the chain. Note that multiple uses are OK
20162 // here, we're not going to remove the operand we find.
20163 SDValue Input = Op.getOperand(0);
20164 while (Input.getOpcode() == ISD::BITCAST)
20165 Input = Input.getOperand(0);
20167 MVT VT = Input.getSimpleValueType();
20168 MVT RootVT = Root.getSimpleValueType();
20171 // Just remove no-op shuffle masks.
20172 if (Mask.size() == 1) {
20173 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20178 // Use the float domain if the operand type is a floating point type.
20179 bool FloatDomain = VT.isFloatingPoint();
20181 // For floating point shuffles, we don't have free copies in the shuffle
20182 // instructions or the ability to load as part of the instruction, so
20183 // canonicalize their shuffles to UNPCK or MOV variants.
20185 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20186 // vectors because it can have a load folded into it that UNPCK cannot. This
20187 // doesn't preclude something switching to the shorter encoding post-RA.
20189 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20190 bool Lo = Mask.equals(0, 0);
20193 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20194 // is no slower than UNPCKLPD but has the option to fold the input operand
20195 // into even an unaligned memory load.
20196 if (Lo && Subtarget->hasSSE3()) {
20197 Shuffle = X86ISD::MOVDDUP;
20198 ShuffleVT = MVT::v2f64;
20200 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20201 // than the UNPCK variants.
20202 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20203 ShuffleVT = MVT::v4f32;
20205 if (Depth == 1 && Root->getOpcode() == Shuffle)
20206 return false; // Nothing to do!
20207 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20208 DCI.AddToWorklist(Op.getNode());
20209 if (Shuffle == X86ISD::MOVDDUP)
20210 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20212 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20213 DCI.AddToWorklist(Op.getNode());
20214 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20218 if (Subtarget->hasSSE3() &&
20219 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20220 bool Lo = Mask.equals(0, 0, 2, 2);
20221 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20222 MVT ShuffleVT = MVT::v4f32;
20223 if (Depth == 1 && Root->getOpcode() == Shuffle)
20224 return false; // Nothing to do!
20225 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20226 DCI.AddToWorklist(Op.getNode());
20227 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20228 DCI.AddToWorklist(Op.getNode());
20229 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20233 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20234 bool Lo = Mask.equals(0, 0, 1, 1);
20235 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20236 MVT ShuffleVT = MVT::v4f32;
20237 if (Depth == 1 && Root->getOpcode() == Shuffle)
20238 return false; // Nothing to do!
20239 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20240 DCI.AddToWorklist(Op.getNode());
20241 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20242 DCI.AddToWorklist(Op.getNode());
20243 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20249 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20250 // variants as none of these have single-instruction variants that are
20251 // superior to the UNPCK formulation.
20252 if (!FloatDomain &&
20253 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20254 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20255 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20256 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20258 bool Lo = Mask[0] == 0;
20259 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20260 if (Depth == 1 && Root->getOpcode() == Shuffle)
20261 return false; // Nothing to do!
20263 switch (Mask.size()) {
20265 ShuffleVT = MVT::v8i16;
20268 ShuffleVT = MVT::v16i8;
20271 llvm_unreachable("Impossible mask size!");
20273 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20274 DCI.AddToWorklist(Op.getNode());
20275 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20276 DCI.AddToWorklist(Op.getNode());
20277 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20282 // Don't try to re-form single instruction chains under any circumstances now
20283 // that we've done encoding canonicalization for them.
20287 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20288 // can replace them with a single PSHUFB instruction profitably. Intel's
20289 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20290 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20291 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20292 SmallVector<SDValue, 16> PSHUFBMask;
20293 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20294 int Ratio = 16 / Mask.size();
20295 for (unsigned i = 0; i < 16; ++i) {
20296 if (Mask[i / Ratio] == SM_SentinelUndef) {
20297 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20300 int M = Mask[i / Ratio] != SM_SentinelZero
20301 ? Ratio * Mask[i / Ratio] + i % Ratio
20303 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20305 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20306 DCI.AddToWorklist(Op.getNode());
20307 SDValue PSHUFBMaskOp =
20308 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20309 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20310 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20311 DCI.AddToWorklist(Op.getNode());
20312 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20317 // Failed to find any combines.
20321 /// \brief Fully generic combining of x86 shuffle instructions.
20323 /// This should be the last combine run over the x86 shuffle instructions. Once
20324 /// they have been fully optimized, this will recursively consider all chains
20325 /// of single-use shuffle instructions, build a generic model of the cumulative
20326 /// shuffle operation, and check for simpler instructions which implement this
20327 /// operation. We use this primarily for two purposes:
20329 /// 1) Collapse generic shuffles to specialized single instructions when
20330 /// equivalent. In most cases, this is just an encoding size win, but
20331 /// sometimes we will collapse multiple generic shuffles into a single
20332 /// special-purpose shuffle.
20333 /// 2) Look for sequences of shuffle instructions with 3 or more total
20334 /// instructions, and replace them with the slightly more expensive SSSE3
20335 /// PSHUFB instruction if available. We do this as the last combining step
20336 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20337 /// a suitable short sequence of other instructions. The PHUFB will either
20338 /// use a register or have to read from memory and so is slightly (but only
20339 /// slightly) more expensive than the other shuffle instructions.
20341 /// Because this is inherently a quadratic operation (for each shuffle in
20342 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20343 /// This should never be an issue in practice as the shuffle lowering doesn't
20344 /// produce sequences of more than 8 instructions.
20346 /// FIXME: We will currently miss some cases where the redundant shuffling
20347 /// would simplify under the threshold for PSHUFB formation because of
20348 /// combine-ordering. To fix this, we should do the redundant instruction
20349 /// combining in this recursive walk.
20350 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20351 ArrayRef<int> RootMask,
20352 int Depth, bool HasPSHUFB,
20354 TargetLowering::DAGCombinerInfo &DCI,
20355 const X86Subtarget *Subtarget) {
20356 // Bound the depth of our recursive combine because this is ultimately
20357 // quadratic in nature.
20361 // Directly rip through bitcasts to find the underlying operand.
20362 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20363 Op = Op.getOperand(0);
20365 MVT VT = Op.getSimpleValueType();
20366 if (!VT.isVector())
20367 return false; // Bail if we hit a non-vector.
20368 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20369 // version should be added.
20370 if (VT.getSizeInBits() != 128)
20373 assert(Root.getSimpleValueType().isVector() &&
20374 "Shuffles operate on vector types!");
20375 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20376 "Can only combine shuffles of the same vector register size.");
20378 if (!isTargetShuffle(Op.getOpcode()))
20380 SmallVector<int, 16> OpMask;
20382 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20383 // We only can combine unary shuffles which we can decode the mask for.
20384 if (!HaveMask || !IsUnary)
20387 assert(VT.getVectorNumElements() == OpMask.size() &&
20388 "Different mask size from vector size!");
20389 assert(((RootMask.size() > OpMask.size() &&
20390 RootMask.size() % OpMask.size() == 0) ||
20391 (OpMask.size() > RootMask.size() &&
20392 OpMask.size() % RootMask.size() == 0) ||
20393 OpMask.size() == RootMask.size()) &&
20394 "The smaller number of elements must divide the larger.");
20395 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20396 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20397 assert(((RootRatio == 1 && OpRatio == 1) ||
20398 (RootRatio == 1) != (OpRatio == 1)) &&
20399 "Must not have a ratio for both incoming and op masks!");
20401 SmallVector<int, 16> Mask;
20402 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20404 // Merge this shuffle operation's mask into our accumulated mask. Note that
20405 // this shuffle's mask will be the first applied to the input, followed by the
20406 // root mask to get us all the way to the root value arrangement. The reason
20407 // for this order is that we are recursing up the operation chain.
20408 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20409 int RootIdx = i / RootRatio;
20410 if (RootMask[RootIdx] < 0) {
20411 // This is a zero or undef lane, we're done.
20412 Mask.push_back(RootMask[RootIdx]);
20416 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20417 int OpIdx = RootMaskedIdx / OpRatio;
20418 if (OpMask[OpIdx] < 0) {
20419 // The incoming lanes are zero or undef, it doesn't matter which ones we
20421 Mask.push_back(OpMask[OpIdx]);
20425 // Ok, we have non-zero lanes, map them through.
20426 Mask.push_back(OpMask[OpIdx] * OpRatio +
20427 RootMaskedIdx % OpRatio);
20430 // See if we can recurse into the operand to combine more things.
20431 switch (Op.getOpcode()) {
20432 case X86ISD::PSHUFB:
20434 case X86ISD::PSHUFD:
20435 case X86ISD::PSHUFHW:
20436 case X86ISD::PSHUFLW:
20437 if (Op.getOperand(0).hasOneUse() &&
20438 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20439 HasPSHUFB, DAG, DCI, Subtarget))
20443 case X86ISD::UNPCKL:
20444 case X86ISD::UNPCKH:
20445 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20446 // We can't check for single use, we have to check that this shuffle is the only user.
20447 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20448 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20449 HasPSHUFB, DAG, DCI, Subtarget))
20454 // Minor canonicalization of the accumulated shuffle mask to make it easier
20455 // to match below. All this does is detect masks with squential pairs of
20456 // elements, and shrink them to the half-width mask. It does this in a loop
20457 // so it will reduce the size of the mask to the minimal width mask which
20458 // performs an equivalent shuffle.
20459 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20460 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20461 Mask[i] = Mask[2 * i] / 2;
20462 Mask.resize(Mask.size() / 2);
20465 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20469 /// \brief Get the PSHUF-style mask from PSHUF node.
20471 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20472 /// PSHUF-style masks that can be reused with such instructions.
20473 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20474 SmallVector<int, 4> Mask;
20476 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20480 switch (N.getOpcode()) {
20481 case X86ISD::PSHUFD:
20483 case X86ISD::PSHUFLW:
20486 case X86ISD::PSHUFHW:
20487 Mask.erase(Mask.begin(), Mask.begin() + 4);
20488 for (int &M : Mask)
20492 llvm_unreachable("No valid shuffle instruction found!");
20496 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20498 /// We walk up the chain and look for a combinable shuffle, skipping over
20499 /// shuffles that we could hoist this shuffle's transformation past without
20500 /// altering anything.
20502 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20504 TargetLowering::DAGCombinerInfo &DCI) {
20505 assert(N.getOpcode() == X86ISD::PSHUFD &&
20506 "Called with something other than an x86 128-bit half shuffle!");
20509 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20510 // of the shuffles in the chain so that we can form a fresh chain to replace
20512 SmallVector<SDValue, 8> Chain;
20513 SDValue V = N.getOperand(0);
20514 for (; V.hasOneUse(); V = V.getOperand(0)) {
20515 switch (V.getOpcode()) {
20517 return SDValue(); // Nothing combined!
20520 // Skip bitcasts as we always know the type for the target specific
20524 case X86ISD::PSHUFD:
20525 // Found another dword shuffle.
20528 case X86ISD::PSHUFLW:
20529 // Check that the low words (being shuffled) are the identity in the
20530 // dword shuffle, and the high words are self-contained.
20531 if (Mask[0] != 0 || Mask[1] != 1 ||
20532 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20535 Chain.push_back(V);
20538 case X86ISD::PSHUFHW:
20539 // Check that the high words (being shuffled) are the identity in the
20540 // dword shuffle, and the low words are self-contained.
20541 if (Mask[2] != 2 || Mask[3] != 3 ||
20542 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20545 Chain.push_back(V);
20548 case X86ISD::UNPCKL:
20549 case X86ISD::UNPCKH:
20550 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20551 // shuffle into a preceding word shuffle.
20552 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20555 // Search for a half-shuffle which we can combine with.
20556 unsigned CombineOp =
20557 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20558 if (V.getOperand(0) != V.getOperand(1) ||
20559 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20561 Chain.push_back(V);
20562 V = V.getOperand(0);
20564 switch (V.getOpcode()) {
20566 return SDValue(); // Nothing to combine.
20568 case X86ISD::PSHUFLW:
20569 case X86ISD::PSHUFHW:
20570 if (V.getOpcode() == CombineOp)
20573 Chain.push_back(V);
20577 V = V.getOperand(0);
20581 } while (V.hasOneUse());
20584 // Break out of the loop if we break out of the switch.
20588 if (!V.hasOneUse())
20589 // We fell out of the loop without finding a viable combining instruction.
20592 // Merge this node's mask and our incoming mask.
20593 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20594 for (int &M : Mask)
20596 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20597 getV4X86ShuffleImm8ForMask(Mask, DAG));
20599 // Rebuild the chain around this new shuffle.
20600 while (!Chain.empty()) {
20601 SDValue W = Chain.pop_back_val();
20603 if (V.getValueType() != W.getOperand(0).getValueType())
20604 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20606 switch (W.getOpcode()) {
20608 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20610 case X86ISD::UNPCKL:
20611 case X86ISD::UNPCKH:
20612 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20615 case X86ISD::PSHUFD:
20616 case X86ISD::PSHUFLW:
20617 case X86ISD::PSHUFHW:
20618 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20622 if (V.getValueType() != N.getValueType())
20623 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20625 // Return the new chain to replace N.
20629 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20631 /// We walk up the chain, skipping shuffles of the other half and looking
20632 /// through shuffles which switch halves trying to find a shuffle of the same
20633 /// pair of dwords.
20634 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20636 TargetLowering::DAGCombinerInfo &DCI) {
20638 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20639 "Called with something other than an x86 128-bit half shuffle!");
20641 unsigned CombineOpcode = N.getOpcode();
20643 // Walk up a single-use chain looking for a combinable shuffle.
20644 SDValue V = N.getOperand(0);
20645 for (; V.hasOneUse(); V = V.getOperand(0)) {
20646 switch (V.getOpcode()) {
20648 return false; // Nothing combined!
20651 // Skip bitcasts as we always know the type for the target specific
20655 case X86ISD::PSHUFLW:
20656 case X86ISD::PSHUFHW:
20657 if (V.getOpcode() == CombineOpcode)
20660 // Other-half shuffles are no-ops.
20663 // Break out of the loop if we break out of the switch.
20667 if (!V.hasOneUse())
20668 // We fell out of the loop without finding a viable combining instruction.
20671 // Combine away the bottom node as its shuffle will be accumulated into
20672 // a preceding shuffle.
20673 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20675 // Record the old value.
20678 // Merge this node's mask and our incoming mask (adjusted to account for all
20679 // the pshufd instructions encountered).
20680 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20681 for (int &M : Mask)
20683 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20684 getV4X86ShuffleImm8ForMask(Mask, DAG));
20686 // Check that the shuffles didn't cancel each other out. If not, we need to
20687 // combine to the new one.
20689 // Replace the combinable shuffle with the combined one, updating all users
20690 // so that we re-evaluate the chain here.
20691 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20696 /// \brief Try to combine x86 target specific shuffles.
20697 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20698 TargetLowering::DAGCombinerInfo &DCI,
20699 const X86Subtarget *Subtarget) {
20701 MVT VT = N.getSimpleValueType();
20702 SmallVector<int, 4> Mask;
20704 switch (N.getOpcode()) {
20705 case X86ISD::PSHUFD:
20706 case X86ISD::PSHUFLW:
20707 case X86ISD::PSHUFHW:
20708 Mask = getPSHUFShuffleMask(N);
20709 assert(Mask.size() == 4);
20715 // Nuke no-op shuffles that show up after combining.
20716 if (isNoopShuffleMask(Mask))
20717 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20719 // Look for simplifications involving one or two shuffle instructions.
20720 SDValue V = N.getOperand(0);
20721 switch (N.getOpcode()) {
20724 case X86ISD::PSHUFLW:
20725 case X86ISD::PSHUFHW:
20726 assert(VT == MVT::v8i16);
20729 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20730 return SDValue(); // We combined away this shuffle, so we're done.
20732 // See if this reduces to a PSHUFD which is no more expensive and can
20733 // combine with more operations.
20734 if (canWidenShuffleElements(Mask)) {
20735 int DMask[] = {-1, -1, -1, -1};
20736 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20737 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20738 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20739 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20740 DCI.AddToWorklist(V.getNode());
20741 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20742 getV4X86ShuffleImm8ForMask(DMask, DAG));
20743 DCI.AddToWorklist(V.getNode());
20744 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20747 // Look for shuffle patterns which can be implemented as a single unpack.
20748 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20749 // only works when we have a PSHUFD followed by two half-shuffles.
20750 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20751 (V.getOpcode() == X86ISD::PSHUFLW ||
20752 V.getOpcode() == X86ISD::PSHUFHW) &&
20753 V.getOpcode() != N.getOpcode() &&
20755 SDValue D = V.getOperand(0);
20756 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20757 D = D.getOperand(0);
20758 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20759 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20760 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20761 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20762 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20764 for (int i = 0; i < 4; ++i) {
20765 WordMask[i + NOffset] = Mask[i] + NOffset;
20766 WordMask[i + VOffset] = VMask[i] + VOffset;
20768 // Map the word mask through the DWord mask.
20770 for (int i = 0; i < 8; ++i)
20771 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20772 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20773 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20774 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20775 std::begin(UnpackLoMask)) ||
20776 std::equal(std::begin(MappedMask), std::end(MappedMask),
20777 std::begin(UnpackHiMask))) {
20778 // We can replace all three shuffles with an unpack.
20779 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20780 DCI.AddToWorklist(V.getNode());
20781 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20783 DL, MVT::v8i16, V, V);
20790 case X86ISD::PSHUFD:
20791 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20800 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20802 /// We combine this directly on the abstract vector shuffle nodes so it is
20803 /// easier to generically match. We also insert dummy vector shuffle nodes for
20804 /// the operands which explicitly discard the lanes which are unused by this
20805 /// operation to try to flow through the rest of the combiner the fact that
20806 /// they're unused.
20807 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20809 EVT VT = N->getValueType(0);
20811 // We only handle target-independent shuffles.
20812 // FIXME: It would be easy and harmless to use the target shuffle mask
20813 // extraction tool to support more.
20814 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20817 auto *SVN = cast<ShuffleVectorSDNode>(N);
20818 ArrayRef<int> Mask = SVN->getMask();
20819 SDValue V1 = N->getOperand(0);
20820 SDValue V2 = N->getOperand(1);
20822 // We require the first shuffle operand to be the SUB node, and the second to
20823 // be the ADD node.
20824 // FIXME: We should support the commuted patterns.
20825 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20828 // If there are other uses of these operations we can't fold them.
20829 if (!V1->hasOneUse() || !V2->hasOneUse())
20832 // Ensure that both operations have the same operands. Note that we can
20833 // commute the FADD operands.
20834 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20835 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20836 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20839 // We're looking for blends between FADD and FSUB nodes. We insist on these
20840 // nodes being lined up in a specific expected pattern.
20841 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20842 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20843 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20846 // Only specific types are legal at this point, assert so we notice if and
20847 // when these change.
20848 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20849 VT == MVT::v4f64) &&
20850 "Unknown vector type encountered!");
20852 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20855 /// PerformShuffleCombine - Performs several different shuffle combines.
20856 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20857 TargetLowering::DAGCombinerInfo &DCI,
20858 const X86Subtarget *Subtarget) {
20860 SDValue N0 = N->getOperand(0);
20861 SDValue N1 = N->getOperand(1);
20862 EVT VT = N->getValueType(0);
20864 // Don't create instructions with illegal types after legalize types has run.
20865 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20866 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20869 // If we have legalized the vector types, look for blends of FADD and FSUB
20870 // nodes that we can fuse into an ADDSUB node.
20871 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20872 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20875 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20876 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20877 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20878 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20880 // During Type Legalization, when promoting illegal vector types,
20881 // the backend might introduce new shuffle dag nodes and bitcasts.
20883 // This code performs the following transformation:
20884 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20885 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20887 // We do this only if both the bitcast and the BINOP dag nodes have
20888 // one use. Also, perform this transformation only if the new binary
20889 // operation is legal. This is to avoid introducing dag nodes that
20890 // potentially need to be further expanded (or custom lowered) into a
20891 // less optimal sequence of dag nodes.
20892 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20893 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20894 N0.getOpcode() == ISD::BITCAST) {
20895 SDValue BC0 = N0.getOperand(0);
20896 EVT SVT = BC0.getValueType();
20897 unsigned Opcode = BC0.getOpcode();
20898 unsigned NumElts = VT.getVectorNumElements();
20900 if (BC0.hasOneUse() && SVT.isVector() &&
20901 SVT.getVectorNumElements() * 2 == NumElts &&
20902 TLI.isOperationLegal(Opcode, VT)) {
20903 bool CanFold = false;
20915 unsigned SVTNumElts = SVT.getVectorNumElements();
20916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20917 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20918 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20919 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20920 CanFold = SVOp->getMaskElt(i) < 0;
20923 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20924 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20925 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20926 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20931 // Only handle 128 wide vector from here on.
20932 if (!VT.is128BitVector())
20935 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20936 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20937 // consecutive, non-overlapping, and in the right order.
20938 SmallVector<SDValue, 16> Elts;
20939 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20940 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20942 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20946 if (isTargetShuffle(N->getOpcode())) {
20948 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20949 if (Shuffle.getNode())
20952 // Try recursively combining arbitrary sequences of x86 shuffle
20953 // instructions into higher-order shuffles. We do this after combining
20954 // specific PSHUF instruction sequences into their minimal form so that we
20955 // can evaluate how many specialized shuffle instructions are involved in
20956 // a particular chain.
20957 SmallVector<int, 1> NonceMask; // Just a placeholder.
20958 NonceMask.push_back(0);
20959 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20960 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20962 return SDValue(); // This routine will use CombineTo to replace N.
20968 /// PerformTruncateCombine - Converts truncate operation to
20969 /// a sequence of vector shuffle operations.
20970 /// It is possible when we truncate 256-bit vector to 128-bit vector
20971 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20972 TargetLowering::DAGCombinerInfo &DCI,
20973 const X86Subtarget *Subtarget) {
20977 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20978 /// specific shuffle of a load can be folded into a single element load.
20979 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20980 /// shuffles have been customed lowered so we need to handle those here.
20981 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20982 TargetLowering::DAGCombinerInfo &DCI) {
20983 if (DCI.isBeforeLegalizeOps())
20986 SDValue InVec = N->getOperand(0);
20987 SDValue EltNo = N->getOperand(1);
20989 if (!isa<ConstantSDNode>(EltNo))
20992 EVT VT = InVec.getValueType();
20994 if (InVec.getOpcode() == ISD::BITCAST) {
20995 // Don't duplicate a load with other uses.
20996 if (!InVec.hasOneUse())
20998 EVT BCVT = InVec.getOperand(0).getValueType();
20999 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21001 InVec = InVec.getOperand(0);
21004 if (!isTargetShuffle(InVec.getOpcode()))
21007 // Don't duplicate a load with other uses.
21008 if (!InVec.hasOneUse())
21011 SmallVector<int, 16> ShuffleMask;
21013 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21017 // Select the input vector, guarding against out of range extract vector.
21018 unsigned NumElems = VT.getVectorNumElements();
21019 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21020 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21021 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21022 : InVec.getOperand(1);
21024 // If inputs to shuffle are the same for both ops, then allow 2 uses
21025 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21027 if (LdNode.getOpcode() == ISD::BITCAST) {
21028 // Don't duplicate a load with other uses.
21029 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21032 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21033 LdNode = LdNode.getOperand(0);
21036 if (!ISD::isNormalLoad(LdNode.getNode()))
21039 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21041 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21044 EVT EltVT = N->getValueType(0);
21045 // If there's a bitcast before the shuffle, check if the load type and
21046 // alignment is valid.
21047 unsigned Align = LN0->getAlignment();
21048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21049 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21050 EltVT.getTypeForEVT(*DAG.getContext()));
21052 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21055 // All checks match so transform back to vector_shuffle so that DAG combiner
21056 // can finish the job
21059 // Create shuffle node taking into account the case that its a unary shuffle
21060 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21061 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21062 InVec.getOperand(0), Shuffle,
21064 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21065 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21069 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21070 /// generation and convert it from being a bunch of shuffles and extracts
21071 /// to a simple store and scalar loads to extract the elements.
21072 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21073 TargetLowering::DAGCombinerInfo &DCI) {
21074 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21075 if (NewOp.getNode())
21078 SDValue InputVector = N->getOperand(0);
21080 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21081 // from mmx to v2i32 has a single usage.
21082 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21083 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21084 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21085 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21086 N->getValueType(0),
21087 InputVector.getNode()->getOperand(0));
21089 // Only operate on vectors of 4 elements, where the alternative shuffling
21090 // gets to be more expensive.
21091 if (InputVector.getValueType() != MVT::v4i32)
21094 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21095 // single use which is a sign-extend or zero-extend, and all elements are
21097 SmallVector<SDNode *, 4> Uses;
21098 unsigned ExtractedElements = 0;
21099 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21100 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21101 if (UI.getUse().getResNo() != InputVector.getResNo())
21104 SDNode *Extract = *UI;
21105 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21108 if (Extract->getValueType(0) != MVT::i32)
21110 if (!Extract->hasOneUse())
21112 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21113 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21115 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21118 // Record which element was extracted.
21119 ExtractedElements |=
21120 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21122 Uses.push_back(Extract);
21125 // If not all the elements were used, this may not be worthwhile.
21126 if (ExtractedElements != 15)
21129 // Ok, we've now decided to do the transformation.
21130 SDLoc dl(InputVector);
21132 // Store the value to a temporary stack slot.
21133 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21134 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21135 MachinePointerInfo(), false, false, 0);
21137 // Replace each use (extract) with a load of the appropriate element.
21138 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21139 UE = Uses.end(); UI != UE; ++UI) {
21140 SDNode *Extract = *UI;
21142 // cOMpute the element's address.
21143 SDValue Idx = Extract->getOperand(1);
21145 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21146 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21147 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21148 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21150 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21151 StackPtr, OffsetVal);
21153 // Load the scalar.
21154 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21155 ScalarAddr, MachinePointerInfo(),
21156 false, false, false, 0);
21158 // Replace the exact with the load.
21159 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21162 // The replacement was made in place; don't return anything.
21166 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21167 static std::pair<unsigned, bool>
21168 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21169 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21170 if (!VT.isVector())
21171 return std::make_pair(0, false);
21173 bool NeedSplit = false;
21174 switch (VT.getSimpleVT().SimpleTy) {
21175 default: return std::make_pair(0, false);
21179 if (!Subtarget->hasAVX2())
21181 if (!Subtarget->hasAVX())
21182 return std::make_pair(0, false);
21187 if (!Subtarget->hasSSE2())
21188 return std::make_pair(0, false);
21191 // SSE2 has only a small subset of the operations.
21192 bool hasUnsigned = Subtarget->hasSSE41() ||
21193 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21194 bool hasSigned = Subtarget->hasSSE41() ||
21195 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21197 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21200 // Check for x CC y ? x : y.
21201 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21202 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21207 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21210 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21213 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21216 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21218 // Check for x CC y ? y : x -- a min/max with reversed arms.
21219 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21220 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21225 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21228 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21231 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21234 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21238 return std::make_pair(Opc, NeedSplit);
21242 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21243 const X86Subtarget *Subtarget) {
21245 SDValue Cond = N->getOperand(0);
21246 SDValue LHS = N->getOperand(1);
21247 SDValue RHS = N->getOperand(2);
21249 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21250 SDValue CondSrc = Cond->getOperand(0);
21251 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21252 Cond = CondSrc->getOperand(0);
21255 MVT VT = N->getSimpleValueType(0);
21256 MVT EltVT = VT.getVectorElementType();
21257 unsigned NumElems = VT.getVectorNumElements();
21258 // There is no blend with immediate in AVX-512.
21259 if (VT.is512BitVector())
21262 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21264 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21267 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21270 // A vselect where all conditions and data are constants can be optimized into
21271 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21272 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21273 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21276 unsigned MaskValue = 0;
21277 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21280 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21281 for (unsigned i = 0; i < NumElems; ++i) {
21282 // Be sure we emit undef where we can.
21283 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21284 ShuffleMask[i] = -1;
21286 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21289 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21292 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21294 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21295 TargetLowering::DAGCombinerInfo &DCI,
21296 const X86Subtarget *Subtarget) {
21298 SDValue Cond = N->getOperand(0);
21299 // Get the LHS/RHS of the select.
21300 SDValue LHS = N->getOperand(1);
21301 SDValue RHS = N->getOperand(2);
21302 EVT VT = LHS.getValueType();
21303 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21305 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21306 // instructions match the semantics of the common C idiom x<y?x:y but not
21307 // x<=y?x:y, because of how they handle negative zero (which can be
21308 // ignored in unsafe-math mode).
21309 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21310 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21311 (Subtarget->hasSSE2() ||
21312 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21313 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21315 unsigned Opcode = 0;
21316 // Check for x CC y ? x : y.
21317 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21318 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21322 // Converting this to a min would handle NaNs incorrectly, and swapping
21323 // the operands would cause it to handle comparisons between positive
21324 // and negative zero incorrectly.
21325 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21326 if (!DAG.getTarget().Options.UnsafeFPMath &&
21327 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21329 std::swap(LHS, RHS);
21331 Opcode = X86ISD::FMIN;
21334 // Converting this to a min would handle comparisons between positive
21335 // and negative zero incorrectly.
21336 if (!DAG.getTarget().Options.UnsafeFPMath &&
21337 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21339 Opcode = X86ISD::FMIN;
21342 // Converting this to a min would handle both negative zeros and NaNs
21343 // incorrectly, but we can swap the operands to fix both.
21344 std::swap(LHS, RHS);
21348 Opcode = X86ISD::FMIN;
21352 // Converting this to a max would handle comparisons between positive
21353 // and negative zero incorrectly.
21354 if (!DAG.getTarget().Options.UnsafeFPMath &&
21355 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21357 Opcode = X86ISD::FMAX;
21360 // Converting this to a max would handle NaNs incorrectly, and swapping
21361 // the operands would cause it to handle comparisons between positive
21362 // and negative zero incorrectly.
21363 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21364 if (!DAG.getTarget().Options.UnsafeFPMath &&
21365 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21367 std::swap(LHS, RHS);
21369 Opcode = X86ISD::FMAX;
21372 // Converting this to a max would handle both negative zeros and NaNs
21373 // incorrectly, but we can swap the operands to fix both.
21374 std::swap(LHS, RHS);
21378 Opcode = X86ISD::FMAX;
21381 // Check for x CC y ? y : x -- a min/max with reversed arms.
21382 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21383 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21387 // Converting this to a min would handle comparisons between positive
21388 // and negative zero incorrectly, and swapping the operands would
21389 // cause it to handle NaNs incorrectly.
21390 if (!DAG.getTarget().Options.UnsafeFPMath &&
21391 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21392 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21394 std::swap(LHS, RHS);
21396 Opcode = X86ISD::FMIN;
21399 // Converting this to a min would handle NaNs incorrectly.
21400 if (!DAG.getTarget().Options.UnsafeFPMath &&
21401 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21403 Opcode = X86ISD::FMIN;
21406 // Converting this to a min would handle both negative zeros and NaNs
21407 // incorrectly, but we can swap the operands to fix both.
21408 std::swap(LHS, RHS);
21412 Opcode = X86ISD::FMIN;
21416 // Converting this to a max would handle NaNs incorrectly.
21417 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21419 Opcode = X86ISD::FMAX;
21422 // Converting this to a max would handle comparisons between positive
21423 // and negative zero incorrectly, and swapping the operands would
21424 // cause it to handle NaNs incorrectly.
21425 if (!DAG.getTarget().Options.UnsafeFPMath &&
21426 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21427 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21429 std::swap(LHS, RHS);
21431 Opcode = X86ISD::FMAX;
21434 // Converting this to a max would handle both negative zeros and NaNs
21435 // incorrectly, but we can swap the operands to fix both.
21436 std::swap(LHS, RHS);
21440 Opcode = X86ISD::FMAX;
21446 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21449 EVT CondVT = Cond.getValueType();
21450 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21451 CondVT.getVectorElementType() == MVT::i1) {
21452 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21453 // lowering on KNL. In this case we convert it to
21454 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21455 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21456 // Since SKX these selects have a proper lowering.
21457 EVT OpVT = LHS.getValueType();
21458 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21459 (OpVT.getVectorElementType() == MVT::i8 ||
21460 OpVT.getVectorElementType() == MVT::i16) &&
21461 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21462 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21463 DCI.AddToWorklist(Cond.getNode());
21464 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21467 // If this is a select between two integer constants, try to do some
21469 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21470 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21471 // Don't do this for crazy integer types.
21472 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21473 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21474 // so that TrueC (the true value) is larger than FalseC.
21475 bool NeedsCondInvert = false;
21477 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21478 // Efficiently invertible.
21479 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21480 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21481 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21482 NeedsCondInvert = true;
21483 std::swap(TrueC, FalseC);
21486 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21487 if (FalseC->getAPIntValue() == 0 &&
21488 TrueC->getAPIntValue().isPowerOf2()) {
21489 if (NeedsCondInvert) // Invert the condition if needed.
21490 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21491 DAG.getConstant(1, Cond.getValueType()));
21493 // Zero extend the condition if needed.
21494 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21496 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21497 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21498 DAG.getConstant(ShAmt, MVT::i8));
21501 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21502 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21503 if (NeedsCondInvert) // Invert the condition if needed.
21504 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21505 DAG.getConstant(1, Cond.getValueType()));
21507 // Zero extend the condition if needed.
21508 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21509 FalseC->getValueType(0), Cond);
21510 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21511 SDValue(FalseC, 0));
21514 // Optimize cases that will turn into an LEA instruction. This requires
21515 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21516 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21517 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21518 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21520 bool isFastMultiplier = false;
21522 switch ((unsigned char)Diff) {
21524 case 1: // result = add base, cond
21525 case 2: // result = lea base( , cond*2)
21526 case 3: // result = lea base(cond, cond*2)
21527 case 4: // result = lea base( , cond*4)
21528 case 5: // result = lea base(cond, cond*4)
21529 case 8: // result = lea base( , cond*8)
21530 case 9: // result = lea base(cond, cond*8)
21531 isFastMultiplier = true;
21536 if (isFastMultiplier) {
21537 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21538 if (NeedsCondInvert) // Invert the condition if needed.
21539 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21540 DAG.getConstant(1, Cond.getValueType()));
21542 // Zero extend the condition if needed.
21543 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21545 // Scale the condition by the difference.
21547 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21548 DAG.getConstant(Diff, Cond.getValueType()));
21550 // Add the base if non-zero.
21551 if (FalseC->getAPIntValue() != 0)
21552 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21553 SDValue(FalseC, 0));
21560 // Canonicalize max and min:
21561 // (x > y) ? x : y -> (x >= y) ? x : y
21562 // (x < y) ? x : y -> (x <= y) ? x : y
21563 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21564 // the need for an extra compare
21565 // against zero. e.g.
21566 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21568 // testl %edi, %edi
21570 // cmovgl %edi, %eax
21574 // cmovsl %eax, %edi
21575 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21576 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21577 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21578 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21583 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21584 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21585 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21586 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21591 // Early exit check
21592 if (!TLI.isTypeLegal(VT))
21595 // Match VSELECTs into subs with unsigned saturation.
21596 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21597 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21598 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21599 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21600 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21602 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21603 // left side invert the predicate to simplify logic below.
21605 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21607 CC = ISD::getSetCCInverse(CC, true);
21608 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21612 if (Other.getNode() && Other->getNumOperands() == 2 &&
21613 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21614 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21615 SDValue CondRHS = Cond->getOperand(1);
21617 // Look for a general sub with unsigned saturation first.
21618 // x >= y ? x-y : 0 --> subus x, y
21619 // x > y ? x-y : 0 --> subus x, y
21620 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21621 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21622 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21624 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21625 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21626 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21627 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21628 // If the RHS is a constant we have to reverse the const
21629 // canonicalization.
21630 // x > C-1 ? x+-C : 0 --> subus x, C
21631 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21632 CondRHSConst->getAPIntValue() ==
21633 (-OpRHSConst->getAPIntValue() - 1))
21634 return DAG.getNode(
21635 X86ISD::SUBUS, DL, VT, OpLHS,
21636 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21638 // Another special case: If C was a sign bit, the sub has been
21639 // canonicalized into a xor.
21640 // FIXME: Would it be better to use computeKnownBits to determine
21641 // whether it's safe to decanonicalize the xor?
21642 // x s< 0 ? x^C : 0 --> subus x, C
21643 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21644 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21645 OpRHSConst->getAPIntValue().isSignBit())
21646 // Note that we have to rebuild the RHS constant here to ensure we
21647 // don't rely on particular values of undef lanes.
21648 return DAG.getNode(
21649 X86ISD::SUBUS, DL, VT, OpLHS,
21650 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21655 // Try to match a min/max vector operation.
21656 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21657 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21658 unsigned Opc = ret.first;
21659 bool NeedSplit = ret.second;
21661 if (Opc && NeedSplit) {
21662 unsigned NumElems = VT.getVectorNumElements();
21663 // Extract the LHS vectors
21664 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21665 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21667 // Extract the RHS vectors
21668 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21669 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21671 // Create min/max for each subvector
21672 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21673 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21675 // Merge the result
21676 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21678 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21681 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21682 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21683 // Check if SETCC has already been promoted
21684 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21685 // Check that condition value type matches vselect operand type
21688 assert(Cond.getValueType().isVector() &&
21689 "vector select expects a vector selector!");
21691 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21692 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21694 if (!TValIsAllOnes && !FValIsAllZeros) {
21695 // Try invert the condition if true value is not all 1s and false value
21697 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21698 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21700 if (TValIsAllZeros || FValIsAllOnes) {
21701 SDValue CC = Cond.getOperand(2);
21702 ISD::CondCode NewCC =
21703 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21704 Cond.getOperand(0).getValueType().isInteger());
21705 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21706 std::swap(LHS, RHS);
21707 TValIsAllOnes = FValIsAllOnes;
21708 FValIsAllZeros = TValIsAllZeros;
21712 if (TValIsAllOnes || FValIsAllZeros) {
21715 if (TValIsAllOnes && FValIsAllZeros)
21717 else if (TValIsAllOnes)
21718 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21719 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21720 else if (FValIsAllZeros)
21721 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21722 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21724 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21728 // Try to fold this VSELECT into a MOVSS/MOVSD
21729 if (N->getOpcode() == ISD::VSELECT &&
21730 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21731 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21732 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21733 bool CanFold = false;
21734 unsigned NumElems = Cond.getNumOperands();
21738 if (isZero(Cond.getOperand(0))) {
21741 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21742 // fold (vselect <0,-1> -> (movsd A, B)
21743 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21744 CanFold = isAllOnes(Cond.getOperand(i));
21745 } else if (isAllOnes(Cond.getOperand(0))) {
21749 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21750 // fold (vselect <-1,0> -> (movsd B, A)
21751 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21752 CanFold = isZero(Cond.getOperand(i));
21756 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21757 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21758 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21761 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21762 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21763 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21764 // (v2i64 (bitcast B)))))
21766 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21767 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21768 // (v2f64 (bitcast B)))))
21770 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21771 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21772 // (v2i64 (bitcast A)))))
21774 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21775 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21776 // (v2f64 (bitcast A)))))
21778 CanFold = (isZero(Cond.getOperand(0)) &&
21779 isZero(Cond.getOperand(1)) &&
21780 isAllOnes(Cond.getOperand(2)) &&
21781 isAllOnes(Cond.getOperand(3)));
21783 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21784 isAllOnes(Cond.getOperand(1)) &&
21785 isZero(Cond.getOperand(2)) &&
21786 isZero(Cond.getOperand(3))) {
21788 std::swap(LHS, RHS);
21792 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21793 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21794 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21795 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21797 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21803 // If we know that this node is legal then we know that it is going to be
21804 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21805 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21806 // to simplify previous instructions.
21807 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21808 !DCI.isBeforeLegalize() &&
21809 // We explicitly check against v8i16 and v16i16 because, although
21810 // they're marked as Custom, they might only be legal when Cond is a
21811 // build_vector of constants. This will be taken care in a later
21813 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21814 VT != MVT::v8i16)) {
21815 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21817 // Don't optimize vector selects that map to mask-registers.
21821 // Check all uses of that condition operand to check whether it will be
21822 // consumed by non-BLEND instructions, which may depend on all bits are set
21824 for (SDNode::use_iterator I = Cond->use_begin(),
21825 E = Cond->use_end(); I != E; ++I)
21826 if (I->getOpcode() != ISD::VSELECT)
21827 // TODO: Add other opcodes eventually lowered into BLEND.
21830 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21831 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21833 APInt KnownZero, KnownOne;
21834 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21835 DCI.isBeforeLegalizeOps());
21836 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21837 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21838 DCI.CommitTargetLoweringOpt(TLO);
21841 // We should generate an X86ISD::BLENDI from a vselect if its argument
21842 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21843 // constants. This specific pattern gets generated when we split a
21844 // selector for a 512 bit vector in a machine without AVX512 (but with
21845 // 256-bit vectors), during legalization:
21847 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21849 // Iff we find this pattern and the build_vectors are built from
21850 // constants, we translate the vselect into a shuffle_vector that we
21851 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21852 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21853 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21854 if (Shuffle.getNode())
21861 // Check whether a boolean test is testing a boolean value generated by
21862 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21865 // Simplify the following patterns:
21866 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21867 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21868 // to (Op EFLAGS Cond)
21870 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21871 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21872 // to (Op EFLAGS !Cond)
21874 // where Op could be BRCOND or CMOV.
21876 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21877 // Quit if not CMP and SUB with its value result used.
21878 if (Cmp.getOpcode() != X86ISD::CMP &&
21879 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21882 // Quit if not used as a boolean value.
21883 if (CC != X86::COND_E && CC != X86::COND_NE)
21886 // Check CMP operands. One of them should be 0 or 1 and the other should be
21887 // an SetCC or extended from it.
21888 SDValue Op1 = Cmp.getOperand(0);
21889 SDValue Op2 = Cmp.getOperand(1);
21892 const ConstantSDNode* C = nullptr;
21893 bool needOppositeCond = (CC == X86::COND_E);
21894 bool checkAgainstTrue = false; // Is it a comparison against 1?
21896 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21898 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21900 else // Quit if all operands are not constants.
21903 if (C->getZExtValue() == 1) {
21904 needOppositeCond = !needOppositeCond;
21905 checkAgainstTrue = true;
21906 } else if (C->getZExtValue() != 0)
21907 // Quit if the constant is neither 0 or 1.
21910 bool truncatedToBoolWithAnd = false;
21911 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21912 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21913 SetCC.getOpcode() == ISD::TRUNCATE ||
21914 SetCC.getOpcode() == ISD::AND) {
21915 if (SetCC.getOpcode() == ISD::AND) {
21917 ConstantSDNode *CS;
21918 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21919 CS->getZExtValue() == 1)
21921 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21922 CS->getZExtValue() == 1)
21926 SetCC = SetCC.getOperand(OpIdx);
21927 truncatedToBoolWithAnd = true;
21929 SetCC = SetCC.getOperand(0);
21932 switch (SetCC.getOpcode()) {
21933 case X86ISD::SETCC_CARRY:
21934 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21935 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21936 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21937 // truncated to i1 using 'and'.
21938 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21940 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21941 "Invalid use of SETCC_CARRY!");
21943 case X86ISD::SETCC:
21944 // Set the condition code or opposite one if necessary.
21945 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21946 if (needOppositeCond)
21947 CC = X86::GetOppositeBranchCondition(CC);
21948 return SetCC.getOperand(1);
21949 case X86ISD::CMOV: {
21950 // Check whether false/true value has canonical one, i.e. 0 or 1.
21951 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21952 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21953 // Quit if true value is not a constant.
21956 // Quit if false value is not a constant.
21958 SDValue Op = SetCC.getOperand(0);
21959 // Skip 'zext' or 'trunc' node.
21960 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21961 Op.getOpcode() == ISD::TRUNCATE)
21962 Op = Op.getOperand(0);
21963 // A special case for rdrand/rdseed, where 0 is set if false cond is
21965 if ((Op.getOpcode() != X86ISD::RDRAND &&
21966 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21969 // Quit if false value is not the constant 0 or 1.
21970 bool FValIsFalse = true;
21971 if (FVal && FVal->getZExtValue() != 0) {
21972 if (FVal->getZExtValue() != 1)
21974 // If FVal is 1, opposite cond is needed.
21975 needOppositeCond = !needOppositeCond;
21976 FValIsFalse = false;
21978 // Quit if TVal is not the constant opposite of FVal.
21979 if (FValIsFalse && TVal->getZExtValue() != 1)
21981 if (!FValIsFalse && TVal->getZExtValue() != 0)
21983 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21984 if (needOppositeCond)
21985 CC = X86::GetOppositeBranchCondition(CC);
21986 return SetCC.getOperand(3);
21993 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21994 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21995 TargetLowering::DAGCombinerInfo &DCI,
21996 const X86Subtarget *Subtarget) {
21999 // If the flag operand isn't dead, don't touch this CMOV.
22000 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22003 SDValue FalseOp = N->getOperand(0);
22004 SDValue TrueOp = N->getOperand(1);
22005 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22006 SDValue Cond = N->getOperand(3);
22008 if (CC == X86::COND_E || CC == X86::COND_NE) {
22009 switch (Cond.getOpcode()) {
22013 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22014 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22015 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22021 Flags = checkBoolTestSetCCCombine(Cond, CC);
22022 if (Flags.getNode() &&
22023 // Extra check as FCMOV only supports a subset of X86 cond.
22024 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22025 SDValue Ops[] = { FalseOp, TrueOp,
22026 DAG.getConstant(CC, MVT::i8), Flags };
22027 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22030 // If this is a select between two integer constants, try to do some
22031 // optimizations. Note that the operands are ordered the opposite of SELECT
22033 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22034 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22035 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22036 // larger than FalseC (the false value).
22037 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22038 CC = X86::GetOppositeBranchCondition(CC);
22039 std::swap(TrueC, FalseC);
22040 std::swap(TrueOp, FalseOp);
22043 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22044 // This is efficient for any integer data type (including i8/i16) and
22046 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22047 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22048 DAG.getConstant(CC, MVT::i8), Cond);
22050 // Zero extend the condition if needed.
22051 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22053 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22054 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22055 DAG.getConstant(ShAmt, MVT::i8));
22056 if (N->getNumValues() == 2) // Dead flag value?
22057 return DCI.CombineTo(N, Cond, SDValue());
22061 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22062 // for any integer data type, including i8/i16.
22063 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22064 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22065 DAG.getConstant(CC, MVT::i8), Cond);
22067 // Zero extend the condition if needed.
22068 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22069 FalseC->getValueType(0), Cond);
22070 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22071 SDValue(FalseC, 0));
22073 if (N->getNumValues() == 2) // Dead flag value?
22074 return DCI.CombineTo(N, Cond, SDValue());
22078 // Optimize cases that will turn into an LEA instruction. This requires
22079 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22080 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22081 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22082 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22084 bool isFastMultiplier = false;
22086 switch ((unsigned char)Diff) {
22088 case 1: // result = add base, cond
22089 case 2: // result = lea base( , cond*2)
22090 case 3: // result = lea base(cond, cond*2)
22091 case 4: // result = lea base( , cond*4)
22092 case 5: // result = lea base(cond, cond*4)
22093 case 8: // result = lea base( , cond*8)
22094 case 9: // result = lea base(cond, cond*8)
22095 isFastMultiplier = true;
22100 if (isFastMultiplier) {
22101 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22102 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22103 DAG.getConstant(CC, MVT::i8), Cond);
22104 // Zero extend the condition if needed.
22105 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22107 // Scale the condition by the difference.
22109 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22110 DAG.getConstant(Diff, Cond.getValueType()));
22112 // Add the base if non-zero.
22113 if (FalseC->getAPIntValue() != 0)
22114 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22115 SDValue(FalseC, 0));
22116 if (N->getNumValues() == 2) // Dead flag value?
22117 return DCI.CombineTo(N, Cond, SDValue());
22124 // Handle these cases:
22125 // (select (x != c), e, c) -> select (x != c), e, x),
22126 // (select (x == c), c, e) -> select (x == c), x, e)
22127 // where the c is an integer constant, and the "select" is the combination
22128 // of CMOV and CMP.
22130 // The rationale for this change is that the conditional-move from a constant
22131 // needs two instructions, however, conditional-move from a register needs
22132 // only one instruction.
22134 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22135 // some instruction-combining opportunities. This opt needs to be
22136 // postponed as late as possible.
22138 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22139 // the DCI.xxxx conditions are provided to postpone the optimization as
22140 // late as possible.
22142 ConstantSDNode *CmpAgainst = nullptr;
22143 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22144 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22145 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22147 if (CC == X86::COND_NE &&
22148 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22149 CC = X86::GetOppositeBranchCondition(CC);
22150 std::swap(TrueOp, FalseOp);
22153 if (CC == X86::COND_E &&
22154 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22155 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22156 DAG.getConstant(CC, MVT::i8), Cond };
22157 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22165 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22166 const X86Subtarget *Subtarget) {
22167 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22169 default: return SDValue();
22170 // SSE/AVX/AVX2 blend intrinsics.
22171 case Intrinsic::x86_avx2_pblendvb:
22172 case Intrinsic::x86_avx2_pblendw:
22173 case Intrinsic::x86_avx2_pblendd_128:
22174 case Intrinsic::x86_avx2_pblendd_256:
22175 // Don't try to simplify this intrinsic if we don't have AVX2.
22176 if (!Subtarget->hasAVX2())
22179 case Intrinsic::x86_avx_blend_pd_256:
22180 case Intrinsic::x86_avx_blend_ps_256:
22181 case Intrinsic::x86_avx_blendv_pd_256:
22182 case Intrinsic::x86_avx_blendv_ps_256:
22183 // Don't try to simplify this intrinsic if we don't have AVX.
22184 if (!Subtarget->hasAVX())
22187 case Intrinsic::x86_sse41_pblendw:
22188 case Intrinsic::x86_sse41_blendpd:
22189 case Intrinsic::x86_sse41_blendps:
22190 case Intrinsic::x86_sse41_blendvps:
22191 case Intrinsic::x86_sse41_blendvpd:
22192 case Intrinsic::x86_sse41_pblendvb: {
22193 SDValue Op0 = N->getOperand(1);
22194 SDValue Op1 = N->getOperand(2);
22195 SDValue Mask = N->getOperand(3);
22197 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22198 if (!Subtarget->hasSSE41())
22201 // fold (blend A, A, Mask) -> A
22204 // fold (blend A, B, allZeros) -> A
22205 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22207 // fold (blend A, B, allOnes) -> B
22208 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22211 // Simplify the case where the mask is a constant i32 value.
22212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22213 if (C->isNullValue())
22215 if (C->isAllOnesValue())
22222 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22223 case Intrinsic::x86_sse2_psrai_w:
22224 case Intrinsic::x86_sse2_psrai_d:
22225 case Intrinsic::x86_avx2_psrai_w:
22226 case Intrinsic::x86_avx2_psrai_d:
22227 case Intrinsic::x86_sse2_psra_w:
22228 case Intrinsic::x86_sse2_psra_d:
22229 case Intrinsic::x86_avx2_psra_w:
22230 case Intrinsic::x86_avx2_psra_d: {
22231 SDValue Op0 = N->getOperand(1);
22232 SDValue Op1 = N->getOperand(2);
22233 EVT VT = Op0.getValueType();
22234 assert(VT.isVector() && "Expected a vector type!");
22236 if (isa<BuildVectorSDNode>(Op1))
22237 Op1 = Op1.getOperand(0);
22239 if (!isa<ConstantSDNode>(Op1))
22242 EVT SVT = VT.getVectorElementType();
22243 unsigned SVTBits = SVT.getSizeInBits();
22245 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22246 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22247 uint64_t ShAmt = C.getZExtValue();
22249 // Don't try to convert this shift into a ISD::SRA if the shift
22250 // count is bigger than or equal to the element size.
22251 if (ShAmt >= SVTBits)
22254 // Trivial case: if the shift count is zero, then fold this
22255 // into the first operand.
22259 // Replace this packed shift intrinsic with a target independent
22261 SDValue Splat = DAG.getConstant(C, VT);
22262 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22267 /// PerformMulCombine - Optimize a single multiply with constant into two
22268 /// in order to implement it with two cheaper instructions, e.g.
22269 /// LEA + SHL, LEA + LEA.
22270 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22271 TargetLowering::DAGCombinerInfo &DCI) {
22272 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22275 EVT VT = N->getValueType(0);
22276 if (VT != MVT::i64)
22279 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22282 uint64_t MulAmt = C->getZExtValue();
22283 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22286 uint64_t MulAmt1 = 0;
22287 uint64_t MulAmt2 = 0;
22288 if ((MulAmt % 9) == 0) {
22290 MulAmt2 = MulAmt / 9;
22291 } else if ((MulAmt % 5) == 0) {
22293 MulAmt2 = MulAmt / 5;
22294 } else if ((MulAmt % 3) == 0) {
22296 MulAmt2 = MulAmt / 3;
22299 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22302 if (isPowerOf2_64(MulAmt2) &&
22303 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22304 // If second multiplifer is pow2, issue it first. We want the multiply by
22305 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22307 std::swap(MulAmt1, MulAmt2);
22310 if (isPowerOf2_64(MulAmt1))
22311 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22312 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22314 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22315 DAG.getConstant(MulAmt1, VT));
22317 if (isPowerOf2_64(MulAmt2))
22318 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22319 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22321 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22322 DAG.getConstant(MulAmt2, VT));
22324 // Do not add new nodes to DAG combiner worklist.
22325 DCI.CombineTo(N, NewMul, false);
22330 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22331 SDValue N0 = N->getOperand(0);
22332 SDValue N1 = N->getOperand(1);
22333 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22334 EVT VT = N0.getValueType();
22336 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22337 // since the result of setcc_c is all zero's or all ones.
22338 if (VT.isInteger() && !VT.isVector() &&
22339 N1C && N0.getOpcode() == ISD::AND &&
22340 N0.getOperand(1).getOpcode() == ISD::Constant) {
22341 SDValue N00 = N0.getOperand(0);
22342 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22343 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22344 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22345 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22346 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22347 APInt ShAmt = N1C->getAPIntValue();
22348 Mask = Mask.shl(ShAmt);
22350 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22351 N00, DAG.getConstant(Mask, VT));
22355 // Hardware support for vector shifts is sparse which makes us scalarize the
22356 // vector operations in many cases. Also, on sandybridge ADD is faster than
22358 // (shl V, 1) -> add V,V
22359 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22360 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22361 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22362 // We shift all of the values by one. In many cases we do not have
22363 // hardware support for this operation. This is better expressed as an ADD
22365 if (N1SplatC->getZExtValue() == 1)
22366 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22372 /// \brief Returns a vector of 0s if the node in input is a vector logical
22373 /// shift by a constant amount which is known to be bigger than or equal
22374 /// to the vector element size in bits.
22375 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22376 const X86Subtarget *Subtarget) {
22377 EVT VT = N->getValueType(0);
22379 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22380 (!Subtarget->hasInt256() ||
22381 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22384 SDValue Amt = N->getOperand(1);
22386 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22387 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22388 APInt ShiftAmt = AmtSplat->getAPIntValue();
22389 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22391 // SSE2/AVX2 logical shifts always return a vector of 0s
22392 // if the shift amount is bigger than or equal to
22393 // the element size. The constant shift amount will be
22394 // encoded as a 8-bit immediate.
22395 if (ShiftAmt.trunc(8).uge(MaxAmount))
22396 return getZeroVector(VT, Subtarget, DAG, DL);
22402 /// PerformShiftCombine - Combine shifts.
22403 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22404 TargetLowering::DAGCombinerInfo &DCI,
22405 const X86Subtarget *Subtarget) {
22406 if (N->getOpcode() == ISD::SHL) {
22407 SDValue V = PerformSHLCombine(N, DAG);
22408 if (V.getNode()) return V;
22411 if (N->getOpcode() != ISD::SRA) {
22412 // Try to fold this logical shift into a zero vector.
22413 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22414 if (V.getNode()) return V;
22420 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22421 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22422 // and friends. Likewise for OR -> CMPNEQSS.
22423 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22424 TargetLowering::DAGCombinerInfo &DCI,
22425 const X86Subtarget *Subtarget) {
22428 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22429 // we're requiring SSE2 for both.
22430 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22431 SDValue N0 = N->getOperand(0);
22432 SDValue N1 = N->getOperand(1);
22433 SDValue CMP0 = N0->getOperand(1);
22434 SDValue CMP1 = N1->getOperand(1);
22437 // The SETCCs should both refer to the same CMP.
22438 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22441 SDValue CMP00 = CMP0->getOperand(0);
22442 SDValue CMP01 = CMP0->getOperand(1);
22443 EVT VT = CMP00.getValueType();
22445 if (VT == MVT::f32 || VT == MVT::f64) {
22446 bool ExpectingFlags = false;
22447 // Check for any users that want flags:
22448 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22449 !ExpectingFlags && UI != UE; ++UI)
22450 switch (UI->getOpcode()) {
22455 ExpectingFlags = true;
22457 case ISD::CopyToReg:
22458 case ISD::SIGN_EXTEND:
22459 case ISD::ZERO_EXTEND:
22460 case ISD::ANY_EXTEND:
22464 if (!ExpectingFlags) {
22465 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22466 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22468 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22469 X86::CondCode tmp = cc0;
22474 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22475 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22476 // FIXME: need symbolic constants for these magic numbers.
22477 // See X86ATTInstPrinter.cpp:printSSECC().
22478 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22479 if (Subtarget->hasAVX512()) {
22480 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22481 CMP01, DAG.getConstant(x86cc, MVT::i8));
22482 if (N->getValueType(0) != MVT::i1)
22483 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22487 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22488 CMP00.getValueType(), CMP00, CMP01,
22489 DAG.getConstant(x86cc, MVT::i8));
22491 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22492 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22494 if (is64BitFP && !Subtarget->is64Bit()) {
22495 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22496 // 64-bit integer, since that's not a legal type. Since
22497 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22498 // bits, but can do this little dance to extract the lowest 32 bits
22499 // and work with those going forward.
22500 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22502 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22504 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22505 Vector32, DAG.getIntPtrConstant(0));
22509 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22510 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22511 DAG.getConstant(1, IntVT));
22512 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22513 return OneBitOfTruth;
22521 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22522 /// so it can be folded inside ANDNP.
22523 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22524 EVT VT = N->getValueType(0);
22526 // Match direct AllOnes for 128 and 256-bit vectors
22527 if (ISD::isBuildVectorAllOnes(N))
22530 // Look through a bit convert.
22531 if (N->getOpcode() == ISD::BITCAST)
22532 N = N->getOperand(0).getNode();
22534 // Sometimes the operand may come from a insert_subvector building a 256-bit
22536 if (VT.is256BitVector() &&
22537 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22538 SDValue V1 = N->getOperand(0);
22539 SDValue V2 = N->getOperand(1);
22541 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22542 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22543 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22544 ISD::isBuildVectorAllOnes(V2.getNode()))
22551 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22552 // register. In most cases we actually compare or select YMM-sized registers
22553 // and mixing the two types creates horrible code. This method optimizes
22554 // some of the transition sequences.
22555 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22556 TargetLowering::DAGCombinerInfo &DCI,
22557 const X86Subtarget *Subtarget) {
22558 EVT VT = N->getValueType(0);
22559 if (!VT.is256BitVector())
22562 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22563 N->getOpcode() == ISD::ZERO_EXTEND ||
22564 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22566 SDValue Narrow = N->getOperand(0);
22567 EVT NarrowVT = Narrow->getValueType(0);
22568 if (!NarrowVT.is128BitVector())
22571 if (Narrow->getOpcode() != ISD::XOR &&
22572 Narrow->getOpcode() != ISD::AND &&
22573 Narrow->getOpcode() != ISD::OR)
22576 SDValue N0 = Narrow->getOperand(0);
22577 SDValue N1 = Narrow->getOperand(1);
22580 // The Left side has to be a trunc.
22581 if (N0.getOpcode() != ISD::TRUNCATE)
22584 // The type of the truncated inputs.
22585 EVT WideVT = N0->getOperand(0)->getValueType(0);
22589 // The right side has to be a 'trunc' or a constant vector.
22590 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22591 ConstantSDNode *RHSConstSplat = nullptr;
22592 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22593 RHSConstSplat = RHSBV->getConstantSplatNode();
22594 if (!RHSTrunc && !RHSConstSplat)
22597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22599 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22602 // Set N0 and N1 to hold the inputs to the new wide operation.
22603 N0 = N0->getOperand(0);
22604 if (RHSConstSplat) {
22605 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22606 SDValue(RHSConstSplat, 0));
22607 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22608 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22609 } else if (RHSTrunc) {
22610 N1 = N1->getOperand(0);
22613 // Generate the wide operation.
22614 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22615 unsigned Opcode = N->getOpcode();
22617 case ISD::ANY_EXTEND:
22619 case ISD::ZERO_EXTEND: {
22620 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22621 APInt Mask = APInt::getAllOnesValue(InBits);
22622 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22623 return DAG.getNode(ISD::AND, DL, VT,
22624 Op, DAG.getConstant(Mask, VT));
22626 case ISD::SIGN_EXTEND:
22627 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22628 Op, DAG.getValueType(NarrowVT));
22630 llvm_unreachable("Unexpected opcode");
22634 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22635 TargetLowering::DAGCombinerInfo &DCI,
22636 const X86Subtarget *Subtarget) {
22637 EVT VT = N->getValueType(0);
22638 if (DCI.isBeforeLegalizeOps())
22641 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22645 // Create BEXTR instructions
22646 // BEXTR is ((X >> imm) & (2**size-1))
22647 if (VT == MVT::i32 || VT == MVT::i64) {
22648 SDValue N0 = N->getOperand(0);
22649 SDValue N1 = N->getOperand(1);
22652 // Check for BEXTR.
22653 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22654 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22655 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22656 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22657 if (MaskNode && ShiftNode) {
22658 uint64_t Mask = MaskNode->getZExtValue();
22659 uint64_t Shift = ShiftNode->getZExtValue();
22660 if (isMask_64(Mask)) {
22661 uint64_t MaskSize = CountPopulation_64(Mask);
22662 if (Shift + MaskSize <= VT.getSizeInBits())
22663 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22664 DAG.getConstant(Shift | (MaskSize << 8), VT));
22672 // Want to form ANDNP nodes:
22673 // 1) In the hopes of then easily combining them with OR and AND nodes
22674 // to form PBLEND/PSIGN.
22675 // 2) To match ANDN packed intrinsics
22676 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22679 SDValue N0 = N->getOperand(0);
22680 SDValue N1 = N->getOperand(1);
22683 // Check LHS for vnot
22684 if (N0.getOpcode() == ISD::XOR &&
22685 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22686 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22687 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22689 // Check RHS for vnot
22690 if (N1.getOpcode() == ISD::XOR &&
22691 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22692 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22693 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22698 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22699 TargetLowering::DAGCombinerInfo &DCI,
22700 const X86Subtarget *Subtarget) {
22701 if (DCI.isBeforeLegalizeOps())
22704 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22708 SDValue N0 = N->getOperand(0);
22709 SDValue N1 = N->getOperand(1);
22710 EVT VT = N->getValueType(0);
22712 // look for psign/blend
22713 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22714 if (!Subtarget->hasSSSE3() ||
22715 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22718 // Canonicalize pandn to RHS
22719 if (N0.getOpcode() == X86ISD::ANDNP)
22721 // or (and (m, y), (pandn m, x))
22722 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22723 SDValue Mask = N1.getOperand(0);
22724 SDValue X = N1.getOperand(1);
22726 if (N0.getOperand(0) == Mask)
22727 Y = N0.getOperand(1);
22728 if (N0.getOperand(1) == Mask)
22729 Y = N0.getOperand(0);
22731 // Check to see if the mask appeared in both the AND and ANDNP and
22735 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22736 // Look through mask bitcast.
22737 if (Mask.getOpcode() == ISD::BITCAST)
22738 Mask = Mask.getOperand(0);
22739 if (X.getOpcode() == ISD::BITCAST)
22740 X = X.getOperand(0);
22741 if (Y.getOpcode() == ISD::BITCAST)
22742 Y = Y.getOperand(0);
22744 EVT MaskVT = Mask.getValueType();
22746 // Validate that the Mask operand is a vector sra node.
22747 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22748 // there is no psrai.b
22749 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22750 unsigned SraAmt = ~0;
22751 if (Mask.getOpcode() == ISD::SRA) {
22752 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22753 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22754 SraAmt = AmtConst->getZExtValue();
22755 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22756 SDValue SraC = Mask.getOperand(1);
22757 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22759 if ((SraAmt + 1) != EltBits)
22764 // Now we know we at least have a plendvb with the mask val. See if
22765 // we can form a psignb/w/d.
22766 // psign = x.type == y.type == mask.type && y = sub(0, x);
22767 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22768 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22769 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22770 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22771 "Unsupported VT for PSIGN");
22772 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22773 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22775 // PBLENDVB only available on SSE 4.1
22776 if (!Subtarget->hasSSE41())
22779 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22781 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22782 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22783 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22784 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22785 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22789 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22792 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22793 MachineFunction &MF = DAG.getMachineFunction();
22794 bool OptForSize = MF.getFunction()->getAttributes().
22795 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22797 // SHLD/SHRD instructions have lower register pressure, but on some
22798 // platforms they have higher latency than the equivalent
22799 // series of shifts/or that would otherwise be generated.
22800 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22801 // have higher latencies and we are not optimizing for size.
22802 if (!OptForSize && Subtarget->isSHLDSlow())
22805 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22807 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22809 if (!N0.hasOneUse() || !N1.hasOneUse())
22812 SDValue ShAmt0 = N0.getOperand(1);
22813 if (ShAmt0.getValueType() != MVT::i8)
22815 SDValue ShAmt1 = N1.getOperand(1);
22816 if (ShAmt1.getValueType() != MVT::i8)
22818 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22819 ShAmt0 = ShAmt0.getOperand(0);
22820 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22821 ShAmt1 = ShAmt1.getOperand(0);
22824 unsigned Opc = X86ISD::SHLD;
22825 SDValue Op0 = N0.getOperand(0);
22826 SDValue Op1 = N1.getOperand(0);
22827 if (ShAmt0.getOpcode() == ISD::SUB) {
22828 Opc = X86ISD::SHRD;
22829 std::swap(Op0, Op1);
22830 std::swap(ShAmt0, ShAmt1);
22833 unsigned Bits = VT.getSizeInBits();
22834 if (ShAmt1.getOpcode() == ISD::SUB) {
22835 SDValue Sum = ShAmt1.getOperand(0);
22836 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22837 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22838 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22839 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22840 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22841 return DAG.getNode(Opc, DL, VT,
22843 DAG.getNode(ISD::TRUNCATE, DL,
22846 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22847 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22849 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22850 return DAG.getNode(Opc, DL, VT,
22851 N0.getOperand(0), N1.getOperand(0),
22852 DAG.getNode(ISD::TRUNCATE, DL,
22859 // Generate NEG and CMOV for integer abs.
22860 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22861 EVT VT = N->getValueType(0);
22863 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22864 // 8-bit integer abs to NEG and CMOV.
22865 if (VT.isInteger() && VT.getSizeInBits() == 8)
22868 SDValue N0 = N->getOperand(0);
22869 SDValue N1 = N->getOperand(1);
22872 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22873 // and change it to SUB and CMOV.
22874 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22875 N0.getOpcode() == ISD::ADD &&
22876 N0.getOperand(1) == N1 &&
22877 N1.getOpcode() == ISD::SRA &&
22878 N1.getOperand(0) == N0.getOperand(0))
22879 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22880 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22881 // Generate SUB & CMOV.
22882 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22883 DAG.getConstant(0, VT), N0.getOperand(0));
22885 SDValue Ops[] = { N0.getOperand(0), Neg,
22886 DAG.getConstant(X86::COND_GE, MVT::i8),
22887 SDValue(Neg.getNode(), 1) };
22888 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22893 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22894 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22895 TargetLowering::DAGCombinerInfo &DCI,
22896 const X86Subtarget *Subtarget) {
22897 if (DCI.isBeforeLegalizeOps())
22900 if (Subtarget->hasCMov()) {
22901 SDValue RV = performIntegerAbsCombine(N, DAG);
22909 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22910 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22911 TargetLowering::DAGCombinerInfo &DCI,
22912 const X86Subtarget *Subtarget) {
22913 LoadSDNode *Ld = cast<LoadSDNode>(N);
22914 EVT RegVT = Ld->getValueType(0);
22915 EVT MemVT = Ld->getMemoryVT();
22917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22919 // On Sandybridge unaligned 256bit loads are inefficient.
22920 ISD::LoadExtType Ext = Ld->getExtensionType();
22921 unsigned Alignment = Ld->getAlignment();
22922 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22923 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22924 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22925 unsigned NumElems = RegVT.getVectorNumElements();
22929 SDValue Ptr = Ld->getBasePtr();
22930 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22932 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22934 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22935 Ld->getPointerInfo(), Ld->isVolatile(),
22936 Ld->isNonTemporal(), Ld->isInvariant(),
22938 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22939 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22940 Ld->getPointerInfo(), Ld->isVolatile(),
22941 Ld->isNonTemporal(), Ld->isInvariant(),
22942 std::min(16U, Alignment));
22943 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22945 Load2.getValue(1));
22947 SDValue NewVec = DAG.getUNDEF(RegVT);
22948 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22949 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22950 return DCI.CombineTo(N, NewVec, TF, true);
22956 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22957 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22958 const X86Subtarget *Subtarget) {
22959 StoreSDNode *St = cast<StoreSDNode>(N);
22960 EVT VT = St->getValue().getValueType();
22961 EVT StVT = St->getMemoryVT();
22963 SDValue StoredVal = St->getOperand(1);
22964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22966 // If we are saving a concatenation of two XMM registers, perform two stores.
22967 // On Sandy Bridge, 256-bit memory operations are executed by two
22968 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22969 // memory operation.
22970 unsigned Alignment = St->getAlignment();
22971 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22972 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22973 StVT == VT && !IsAligned) {
22974 unsigned NumElems = VT.getVectorNumElements();
22978 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22979 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22981 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22982 SDValue Ptr0 = St->getBasePtr();
22983 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22985 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22986 St->getPointerInfo(), St->isVolatile(),
22987 St->isNonTemporal(), Alignment);
22988 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22989 St->getPointerInfo(), St->isVolatile(),
22990 St->isNonTemporal(),
22991 std::min(16U, Alignment));
22992 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22995 // Optimize trunc store (of multiple scalars) to shuffle and store.
22996 // First, pack all of the elements in one place. Next, store to memory
22997 // in fewer chunks.
22998 if (St->isTruncatingStore() && VT.isVector()) {
22999 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23000 unsigned NumElems = VT.getVectorNumElements();
23001 assert(StVT != VT && "Cannot truncate to the same type");
23002 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23003 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23005 // From, To sizes and ElemCount must be pow of two
23006 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23007 // We are going to use the original vector elt for storing.
23008 // Accumulated smaller vector elements must be a multiple of the store size.
23009 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23011 unsigned SizeRatio = FromSz / ToSz;
23013 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23015 // Create a type on which we perform the shuffle
23016 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23017 StVT.getScalarType(), NumElems*SizeRatio);
23019 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23021 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23022 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23023 for (unsigned i = 0; i != NumElems; ++i)
23024 ShuffleVec[i] = i * SizeRatio;
23026 // Can't shuffle using an illegal type.
23027 if (!TLI.isTypeLegal(WideVecVT))
23030 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23031 DAG.getUNDEF(WideVecVT),
23033 // At this point all of the data is stored at the bottom of the
23034 // register. We now need to save it to mem.
23036 // Find the largest store unit
23037 MVT StoreType = MVT::i8;
23038 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23039 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23040 MVT Tp = (MVT::SimpleValueType)tp;
23041 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23045 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23046 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23047 (64 <= NumElems * ToSz))
23048 StoreType = MVT::f64;
23050 // Bitcast the original vector into a vector of store-size units
23051 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23052 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23053 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23054 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23055 SmallVector<SDValue, 8> Chains;
23056 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23057 TLI.getPointerTy());
23058 SDValue Ptr = St->getBasePtr();
23060 // Perform one or more big stores into memory.
23061 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23062 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23063 StoreType, ShuffWide,
23064 DAG.getIntPtrConstant(i));
23065 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23066 St->getPointerInfo(), St->isVolatile(),
23067 St->isNonTemporal(), St->getAlignment());
23068 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23069 Chains.push_back(Ch);
23072 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23075 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23076 // the FP state in cases where an emms may be missing.
23077 // A preferable solution to the general problem is to figure out the right
23078 // places to insert EMMS. This qualifies as a quick hack.
23080 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23081 if (VT.getSizeInBits() != 64)
23084 const Function *F = DAG.getMachineFunction().getFunction();
23085 bool NoImplicitFloatOps = F->getAttributes().
23086 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23087 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23088 && Subtarget->hasSSE2();
23089 if ((VT.isVector() ||
23090 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23091 isa<LoadSDNode>(St->getValue()) &&
23092 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23093 St->getChain().hasOneUse() && !St->isVolatile()) {
23094 SDNode* LdVal = St->getValue().getNode();
23095 LoadSDNode *Ld = nullptr;
23096 int TokenFactorIndex = -1;
23097 SmallVector<SDValue, 8> Ops;
23098 SDNode* ChainVal = St->getChain().getNode();
23099 // Must be a store of a load. We currently handle two cases: the load
23100 // is a direct child, and it's under an intervening TokenFactor. It is
23101 // possible to dig deeper under nested TokenFactors.
23102 if (ChainVal == LdVal)
23103 Ld = cast<LoadSDNode>(St->getChain());
23104 else if (St->getValue().hasOneUse() &&
23105 ChainVal->getOpcode() == ISD::TokenFactor) {
23106 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23107 if (ChainVal->getOperand(i).getNode() == LdVal) {
23108 TokenFactorIndex = i;
23109 Ld = cast<LoadSDNode>(St->getValue());
23111 Ops.push_back(ChainVal->getOperand(i));
23115 if (!Ld || !ISD::isNormalLoad(Ld))
23118 // If this is not the MMX case, i.e. we are just turning i64 load/store
23119 // into f64 load/store, avoid the transformation if there are multiple
23120 // uses of the loaded value.
23121 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23126 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23127 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23129 if (Subtarget->is64Bit() || F64IsLegal) {
23130 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23131 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23132 Ld->getPointerInfo(), Ld->isVolatile(),
23133 Ld->isNonTemporal(), Ld->isInvariant(),
23134 Ld->getAlignment());
23135 SDValue NewChain = NewLd.getValue(1);
23136 if (TokenFactorIndex != -1) {
23137 Ops.push_back(NewChain);
23138 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23140 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23141 St->getPointerInfo(),
23142 St->isVolatile(), St->isNonTemporal(),
23143 St->getAlignment());
23146 // Otherwise, lower to two pairs of 32-bit loads / stores.
23147 SDValue LoAddr = Ld->getBasePtr();
23148 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23149 DAG.getConstant(4, MVT::i32));
23151 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23152 Ld->getPointerInfo(),
23153 Ld->isVolatile(), Ld->isNonTemporal(),
23154 Ld->isInvariant(), Ld->getAlignment());
23155 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23156 Ld->getPointerInfo().getWithOffset(4),
23157 Ld->isVolatile(), Ld->isNonTemporal(),
23159 MinAlign(Ld->getAlignment(), 4));
23161 SDValue NewChain = LoLd.getValue(1);
23162 if (TokenFactorIndex != -1) {
23163 Ops.push_back(LoLd);
23164 Ops.push_back(HiLd);
23165 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23168 LoAddr = St->getBasePtr();
23169 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23170 DAG.getConstant(4, MVT::i32));
23172 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23173 St->getPointerInfo(),
23174 St->isVolatile(), St->isNonTemporal(),
23175 St->getAlignment());
23176 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23177 St->getPointerInfo().getWithOffset(4),
23179 St->isNonTemporal(),
23180 MinAlign(St->getAlignment(), 4));
23181 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23186 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23187 /// and return the operands for the horizontal operation in LHS and RHS. A
23188 /// horizontal operation performs the binary operation on successive elements
23189 /// of its first operand, then on successive elements of its second operand,
23190 /// returning the resulting values in a vector. For example, if
23191 /// A = < float a0, float a1, float a2, float a3 >
23193 /// B = < float b0, float b1, float b2, float b3 >
23194 /// then the result of doing a horizontal operation on A and B is
23195 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23196 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23197 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23198 /// set to A, RHS to B, and the routine returns 'true'.
23199 /// Note that the binary operation should have the property that if one of the
23200 /// operands is UNDEF then the result is UNDEF.
23201 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23202 // Look for the following pattern: if
23203 // A = < float a0, float a1, float a2, float a3 >
23204 // B = < float b0, float b1, float b2, float b3 >
23206 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23207 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23208 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23209 // which is A horizontal-op B.
23211 // At least one of the operands should be a vector shuffle.
23212 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23213 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23216 MVT VT = LHS.getSimpleValueType();
23218 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23219 "Unsupported vector type for horizontal add/sub");
23221 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23222 // operate independently on 128-bit lanes.
23223 unsigned NumElts = VT.getVectorNumElements();
23224 unsigned NumLanes = VT.getSizeInBits()/128;
23225 unsigned NumLaneElts = NumElts / NumLanes;
23226 assert((NumLaneElts % 2 == 0) &&
23227 "Vector type should have an even number of elements in each lane");
23228 unsigned HalfLaneElts = NumLaneElts/2;
23230 // View LHS in the form
23231 // LHS = VECTOR_SHUFFLE A, B, LMask
23232 // If LHS is not a shuffle then pretend it is the shuffle
23233 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23234 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23237 SmallVector<int, 16> LMask(NumElts);
23238 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23239 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23240 A = LHS.getOperand(0);
23241 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23242 B = LHS.getOperand(1);
23243 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23244 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23246 if (LHS.getOpcode() != ISD::UNDEF)
23248 for (unsigned i = 0; i != NumElts; ++i)
23252 // Likewise, view RHS in the form
23253 // RHS = VECTOR_SHUFFLE C, D, RMask
23255 SmallVector<int, 16> RMask(NumElts);
23256 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23257 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23258 C = RHS.getOperand(0);
23259 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23260 D = RHS.getOperand(1);
23261 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23262 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23264 if (RHS.getOpcode() != ISD::UNDEF)
23266 for (unsigned i = 0; i != NumElts; ++i)
23270 // Check that the shuffles are both shuffling the same vectors.
23271 if (!(A == C && B == D) && !(A == D && B == C))
23274 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23275 if (!A.getNode() && !B.getNode())
23278 // If A and B occur in reverse order in RHS, then "swap" them (which means
23279 // rewriting the mask).
23281 CommuteVectorShuffleMask(RMask, NumElts);
23283 // At this point LHS and RHS are equivalent to
23284 // LHS = VECTOR_SHUFFLE A, B, LMask
23285 // RHS = VECTOR_SHUFFLE A, B, RMask
23286 // Check that the masks correspond to performing a horizontal operation.
23287 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23288 for (unsigned i = 0; i != NumLaneElts; ++i) {
23289 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23291 // Ignore any UNDEF components.
23292 if (LIdx < 0 || RIdx < 0 ||
23293 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23294 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23297 // Check that successive elements are being operated on. If not, this is
23298 // not a horizontal operation.
23299 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23300 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23301 if (!(LIdx == Index && RIdx == Index + 1) &&
23302 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23307 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23308 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23312 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23313 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23314 const X86Subtarget *Subtarget) {
23315 EVT VT = N->getValueType(0);
23316 SDValue LHS = N->getOperand(0);
23317 SDValue RHS = N->getOperand(1);
23319 // Try to synthesize horizontal adds from adds of shuffles.
23320 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23321 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23322 isHorizontalBinOp(LHS, RHS, true))
23323 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23327 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23328 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23329 const X86Subtarget *Subtarget) {
23330 EVT VT = N->getValueType(0);
23331 SDValue LHS = N->getOperand(0);
23332 SDValue RHS = N->getOperand(1);
23334 // Try to synthesize horizontal subs from subs of shuffles.
23335 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23336 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23337 isHorizontalBinOp(LHS, RHS, false))
23338 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23342 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23343 /// X86ISD::FXOR nodes.
23344 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23345 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23346 // F[X]OR(0.0, x) -> x
23347 // F[X]OR(x, 0.0) -> x
23348 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23349 if (C->getValueAPF().isPosZero())
23350 return N->getOperand(1);
23351 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23352 if (C->getValueAPF().isPosZero())
23353 return N->getOperand(0);
23357 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23358 /// X86ISD::FMAX nodes.
23359 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23360 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23362 // Only perform optimizations if UnsafeMath is used.
23363 if (!DAG.getTarget().Options.UnsafeFPMath)
23366 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23367 // into FMINC and FMAXC, which are Commutative operations.
23368 unsigned NewOp = 0;
23369 switch (N->getOpcode()) {
23370 default: llvm_unreachable("unknown opcode");
23371 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23372 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23375 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23376 N->getOperand(0), N->getOperand(1));
23379 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23380 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23381 // FAND(0.0, x) -> 0.0
23382 // FAND(x, 0.0) -> 0.0
23383 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23384 if (C->getValueAPF().isPosZero())
23385 return N->getOperand(0);
23386 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23387 if (C->getValueAPF().isPosZero())
23388 return N->getOperand(1);
23392 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23393 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23394 // FANDN(x, 0.0) -> 0.0
23395 // FANDN(0.0, x) -> x
23396 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23397 if (C->getValueAPF().isPosZero())
23398 return N->getOperand(1);
23399 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23400 if (C->getValueAPF().isPosZero())
23401 return N->getOperand(1);
23405 static SDValue PerformBTCombine(SDNode *N,
23407 TargetLowering::DAGCombinerInfo &DCI) {
23408 // BT ignores high bits in the bit index operand.
23409 SDValue Op1 = N->getOperand(1);
23410 if (Op1.hasOneUse()) {
23411 unsigned BitWidth = Op1.getValueSizeInBits();
23412 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23413 APInt KnownZero, KnownOne;
23414 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23415 !DCI.isBeforeLegalizeOps());
23416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23417 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23418 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23419 DCI.CommitTargetLoweringOpt(TLO);
23424 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23425 SDValue Op = N->getOperand(0);
23426 if (Op.getOpcode() == ISD::BITCAST)
23427 Op = Op.getOperand(0);
23428 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23429 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23430 VT.getVectorElementType().getSizeInBits() ==
23431 OpVT.getVectorElementType().getSizeInBits()) {
23432 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23437 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23438 const X86Subtarget *Subtarget) {
23439 EVT VT = N->getValueType(0);
23440 if (!VT.isVector())
23443 SDValue N0 = N->getOperand(0);
23444 SDValue N1 = N->getOperand(1);
23445 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23448 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23449 // both SSE and AVX2 since there is no sign-extended shift right
23450 // operation on a vector with 64-bit elements.
23451 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23452 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23453 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23454 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23455 SDValue N00 = N0.getOperand(0);
23457 // EXTLOAD has a better solution on AVX2,
23458 // it may be replaced with X86ISD::VSEXT node.
23459 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23460 if (!ISD::isNormalLoad(N00.getNode()))
23463 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23464 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23466 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23472 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23473 TargetLowering::DAGCombinerInfo &DCI,
23474 const X86Subtarget *Subtarget) {
23475 if (!DCI.isBeforeLegalizeOps())
23478 if (!Subtarget->hasFp256())
23481 EVT VT = N->getValueType(0);
23482 if (VT.isVector() && VT.getSizeInBits() == 256) {
23483 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23491 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23492 const X86Subtarget* Subtarget) {
23494 EVT VT = N->getValueType(0);
23496 // Let legalize expand this if it isn't a legal type yet.
23497 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23500 EVT ScalarVT = VT.getScalarType();
23501 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23502 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23505 SDValue A = N->getOperand(0);
23506 SDValue B = N->getOperand(1);
23507 SDValue C = N->getOperand(2);
23509 bool NegA = (A.getOpcode() == ISD::FNEG);
23510 bool NegB = (B.getOpcode() == ISD::FNEG);
23511 bool NegC = (C.getOpcode() == ISD::FNEG);
23513 // Negative multiplication when NegA xor NegB
23514 bool NegMul = (NegA != NegB);
23516 A = A.getOperand(0);
23518 B = B.getOperand(0);
23520 C = C.getOperand(0);
23524 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23526 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23528 return DAG.getNode(Opcode, dl, VT, A, B, C);
23531 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23532 TargetLowering::DAGCombinerInfo &DCI,
23533 const X86Subtarget *Subtarget) {
23534 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23535 // (and (i32 x86isd::setcc_carry), 1)
23536 // This eliminates the zext. This transformation is necessary because
23537 // ISD::SETCC is always legalized to i8.
23539 SDValue N0 = N->getOperand(0);
23540 EVT VT = N->getValueType(0);
23542 if (N0.getOpcode() == ISD::AND &&
23544 N0.getOperand(0).hasOneUse()) {
23545 SDValue N00 = N0.getOperand(0);
23546 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23547 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23548 if (!C || C->getZExtValue() != 1)
23550 return DAG.getNode(ISD::AND, dl, VT,
23551 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23552 N00.getOperand(0), N00.getOperand(1)),
23553 DAG.getConstant(1, VT));
23557 if (N0.getOpcode() == ISD::TRUNCATE &&
23559 N0.getOperand(0).hasOneUse()) {
23560 SDValue N00 = N0.getOperand(0);
23561 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23562 return DAG.getNode(ISD::AND, dl, VT,
23563 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23564 N00.getOperand(0), N00.getOperand(1)),
23565 DAG.getConstant(1, VT));
23568 if (VT.is256BitVector()) {
23569 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23577 // Optimize x == -y --> x+y == 0
23578 // x != -y --> x+y != 0
23579 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23580 const X86Subtarget* Subtarget) {
23581 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23582 SDValue LHS = N->getOperand(0);
23583 SDValue RHS = N->getOperand(1);
23584 EVT VT = N->getValueType(0);
23587 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23589 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23590 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23591 LHS.getValueType(), RHS, LHS.getOperand(1));
23592 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23593 addV, DAG.getConstant(0, addV.getValueType()), CC);
23595 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23597 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23598 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23599 RHS.getValueType(), LHS, RHS.getOperand(1));
23600 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23601 addV, DAG.getConstant(0, addV.getValueType()), CC);
23604 if (VT.getScalarType() == MVT::i1) {
23605 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23606 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23607 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23608 if (!IsSEXT0 && !IsVZero0)
23610 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23611 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23612 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23614 if (!IsSEXT1 && !IsVZero1)
23617 if (IsSEXT0 && IsVZero1) {
23618 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23619 if (CC == ISD::SETEQ)
23620 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23621 return LHS.getOperand(0);
23623 if (IsSEXT1 && IsVZero0) {
23624 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23625 if (CC == ISD::SETEQ)
23626 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23627 return RHS.getOperand(0);
23634 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23635 const X86Subtarget *Subtarget) {
23637 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23638 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23639 "X86insertps is only defined for v4x32");
23641 SDValue Ld = N->getOperand(1);
23642 if (MayFoldLoad(Ld)) {
23643 // Extract the countS bits from the immediate so we can get the proper
23644 // address when narrowing the vector load to a specific element.
23645 // When the second source op is a memory address, interps doesn't use
23646 // countS and just gets an f32 from that address.
23647 unsigned DestIndex =
23648 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23649 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23653 // Create this as a scalar to vector to match the instruction pattern.
23654 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23655 // countS bits are ignored when loading from memory on insertps, which
23656 // means we don't need to explicitly set them to 0.
23657 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23658 LoadScalarToVector, N->getOperand(2));
23661 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23662 // as "sbb reg,reg", since it can be extended without zext and produces
23663 // an all-ones bit which is more useful than 0/1 in some cases.
23664 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23667 return DAG.getNode(ISD::AND, DL, VT,
23668 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23669 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23670 DAG.getConstant(1, VT));
23671 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23672 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23673 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23674 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23677 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23678 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23679 TargetLowering::DAGCombinerInfo &DCI,
23680 const X86Subtarget *Subtarget) {
23682 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23683 SDValue EFLAGS = N->getOperand(1);
23685 if (CC == X86::COND_A) {
23686 // Try to convert COND_A into COND_B in an attempt to facilitate
23687 // materializing "setb reg".
23689 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23690 // cannot take an immediate as its first operand.
23692 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23693 EFLAGS.getValueType().isInteger() &&
23694 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23695 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23696 EFLAGS.getNode()->getVTList(),
23697 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23698 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23699 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23703 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23704 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23706 if (CC == X86::COND_B)
23707 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23711 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23712 if (Flags.getNode()) {
23713 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23714 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23720 // Optimize branch condition evaluation.
23722 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23723 TargetLowering::DAGCombinerInfo &DCI,
23724 const X86Subtarget *Subtarget) {
23726 SDValue Chain = N->getOperand(0);
23727 SDValue Dest = N->getOperand(1);
23728 SDValue EFLAGS = N->getOperand(3);
23729 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23733 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23734 if (Flags.getNode()) {
23735 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23736 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23743 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23744 SelectionDAG &DAG) {
23745 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23746 // optimize away operation when it's from a constant.
23748 // The general transformation is:
23749 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23750 // AND(VECTOR_CMP(x,y), constant2)
23751 // constant2 = UNARYOP(constant)
23753 // Early exit if this isn't a vector operation, the operand of the
23754 // unary operation isn't a bitwise AND, or if the sizes of the operations
23755 // aren't the same.
23756 EVT VT = N->getValueType(0);
23757 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23758 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23759 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23762 // Now check that the other operand of the AND is a constant. We could
23763 // make the transformation for non-constant splats as well, but it's unclear
23764 // that would be a benefit as it would not eliminate any operations, just
23765 // perform one more step in scalar code before moving to the vector unit.
23766 if (BuildVectorSDNode *BV =
23767 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23768 // Bail out if the vector isn't a constant.
23769 if (!BV->isConstant())
23772 // Everything checks out. Build up the new and improved node.
23774 EVT IntVT = BV->getValueType(0);
23775 // Create a new constant of the appropriate type for the transformed
23777 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23778 // The AND node needs bitcasts to/from an integer vector type around it.
23779 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23780 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23781 N->getOperand(0)->getOperand(0), MaskConst);
23782 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23789 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23790 const X86TargetLowering *XTLI) {
23791 // First try to optimize away the conversion entirely when it's
23792 // conditionally from a constant. Vectors only.
23793 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23794 if (Res != SDValue())
23797 // Now move on to more general possibilities.
23798 SDValue Op0 = N->getOperand(0);
23799 EVT InVT = Op0->getValueType(0);
23801 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23802 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23804 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23805 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23806 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23809 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23810 // a 32-bit target where SSE doesn't support i64->FP operations.
23811 if (Op0.getOpcode() == ISD::LOAD) {
23812 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23813 EVT VT = Ld->getValueType(0);
23814 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23815 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23816 !XTLI->getSubtarget()->is64Bit() &&
23818 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23819 Ld->getChain(), Op0, DAG);
23820 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23827 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23828 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23829 X86TargetLowering::DAGCombinerInfo &DCI) {
23830 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23831 // the result is either zero or one (depending on the input carry bit).
23832 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23833 if (X86::isZeroNode(N->getOperand(0)) &&
23834 X86::isZeroNode(N->getOperand(1)) &&
23835 // We don't have a good way to replace an EFLAGS use, so only do this when
23837 SDValue(N, 1).use_empty()) {
23839 EVT VT = N->getValueType(0);
23840 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23841 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23842 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23843 DAG.getConstant(X86::COND_B,MVT::i8),
23845 DAG.getConstant(1, VT));
23846 return DCI.CombineTo(N, Res1, CarryOut);
23852 // fold (add Y, (sete X, 0)) -> adc 0, Y
23853 // (add Y, (setne X, 0)) -> sbb -1, Y
23854 // (sub (sete X, 0), Y) -> sbb 0, Y
23855 // (sub (setne X, 0), Y) -> adc -1, Y
23856 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23859 // Look through ZExts.
23860 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23861 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23864 SDValue SetCC = Ext.getOperand(0);
23865 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23868 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23869 if (CC != X86::COND_E && CC != X86::COND_NE)
23872 SDValue Cmp = SetCC.getOperand(1);
23873 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23874 !X86::isZeroNode(Cmp.getOperand(1)) ||
23875 !Cmp.getOperand(0).getValueType().isInteger())
23878 SDValue CmpOp0 = Cmp.getOperand(0);
23879 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23880 DAG.getConstant(1, CmpOp0.getValueType()));
23882 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23883 if (CC == X86::COND_NE)
23884 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23885 DL, OtherVal.getValueType(), OtherVal,
23886 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23887 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23888 DL, OtherVal.getValueType(), OtherVal,
23889 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23892 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23893 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23894 const X86Subtarget *Subtarget) {
23895 EVT VT = N->getValueType(0);
23896 SDValue Op0 = N->getOperand(0);
23897 SDValue Op1 = N->getOperand(1);
23899 // Try to synthesize horizontal adds from adds of shuffles.
23900 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23901 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23902 isHorizontalBinOp(Op0, Op1, true))
23903 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23905 return OptimizeConditionalInDecrement(N, DAG);
23908 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23909 const X86Subtarget *Subtarget) {
23910 SDValue Op0 = N->getOperand(0);
23911 SDValue Op1 = N->getOperand(1);
23913 // X86 can't encode an immediate LHS of a sub. See if we can push the
23914 // negation into a preceding instruction.
23915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23916 // If the RHS of the sub is a XOR with one use and a constant, invert the
23917 // immediate. Then add one to the LHS of the sub so we can turn
23918 // X-Y -> X+~Y+1, saving one register.
23919 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23920 isa<ConstantSDNode>(Op1.getOperand(1))) {
23921 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23922 EVT VT = Op0.getValueType();
23923 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23925 DAG.getConstant(~XorC, VT));
23926 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23927 DAG.getConstant(C->getAPIntValue()+1, VT));
23931 // Try to synthesize horizontal adds from adds of shuffles.
23932 EVT VT = N->getValueType(0);
23933 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23934 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23935 isHorizontalBinOp(Op0, Op1, true))
23936 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23938 return OptimizeConditionalInDecrement(N, DAG);
23941 /// performVZEXTCombine - Performs build vector combines
23942 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23943 TargetLowering::DAGCombinerInfo &DCI,
23944 const X86Subtarget *Subtarget) {
23945 // (vzext (bitcast (vzext (x)) -> (vzext x)
23946 SDValue In = N->getOperand(0);
23947 while (In.getOpcode() == ISD::BITCAST)
23948 In = In.getOperand(0);
23950 if (In.getOpcode() != X86ISD::VZEXT)
23953 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23957 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23958 DAGCombinerInfo &DCI) const {
23959 SelectionDAG &DAG = DCI.DAG;
23960 switch (N->getOpcode()) {
23962 case ISD::EXTRACT_VECTOR_ELT:
23963 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23965 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23966 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23967 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23968 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23969 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23970 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23973 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23974 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23975 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23976 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23977 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23978 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23979 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23980 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23981 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23983 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23985 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23986 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23987 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23988 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23989 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23990 case ISD::ANY_EXTEND:
23991 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23992 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23993 case ISD::SIGN_EXTEND_INREG:
23994 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23995 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23996 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23997 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23998 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23999 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24000 case X86ISD::SHUFP: // Handle all target specific shuffles
24001 case X86ISD::PALIGNR:
24002 case X86ISD::UNPCKH:
24003 case X86ISD::UNPCKL:
24004 case X86ISD::MOVHLPS:
24005 case X86ISD::MOVLHPS:
24006 case X86ISD::PSHUFB:
24007 case X86ISD::PSHUFD:
24008 case X86ISD::PSHUFHW:
24009 case X86ISD::PSHUFLW:
24010 case X86ISD::MOVSS:
24011 case X86ISD::MOVSD:
24012 case X86ISD::VPERMILPI:
24013 case X86ISD::VPERM2X128:
24014 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24015 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24016 case ISD::INTRINSIC_WO_CHAIN:
24017 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24018 case X86ISD::INSERTPS:
24019 return PerformINSERTPSCombine(N, DAG, Subtarget);
24020 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24026 /// isTypeDesirableForOp - Return true if the target has native support for
24027 /// the specified value type and it is 'desirable' to use the type for the
24028 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24029 /// instruction encodings are longer and some i16 instructions are slow.
24030 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24031 if (!isTypeLegal(VT))
24033 if (VT != MVT::i16)
24040 case ISD::SIGN_EXTEND:
24041 case ISD::ZERO_EXTEND:
24042 case ISD::ANY_EXTEND:
24055 /// IsDesirableToPromoteOp - This method query the target whether it is
24056 /// beneficial for dag combiner to promote the specified node. If true, it
24057 /// should return the desired promotion type by reference.
24058 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24059 EVT VT = Op.getValueType();
24060 if (VT != MVT::i16)
24063 bool Promote = false;
24064 bool Commute = false;
24065 switch (Op.getOpcode()) {
24068 LoadSDNode *LD = cast<LoadSDNode>(Op);
24069 // If the non-extending load has a single use and it's not live out, then it
24070 // might be folded.
24071 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24072 Op.hasOneUse()*/) {
24073 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24074 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24075 // The only case where we'd want to promote LOAD (rather then it being
24076 // promoted as an operand is when it's only use is liveout.
24077 if (UI->getOpcode() != ISD::CopyToReg)
24084 case ISD::SIGN_EXTEND:
24085 case ISD::ZERO_EXTEND:
24086 case ISD::ANY_EXTEND:
24091 SDValue N0 = Op.getOperand(0);
24092 // Look out for (store (shl (load), x)).
24093 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24106 SDValue N0 = Op.getOperand(0);
24107 SDValue N1 = Op.getOperand(1);
24108 if (!Commute && MayFoldLoad(N1))
24110 // Avoid disabling potential load folding opportunities.
24111 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24113 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24123 //===----------------------------------------------------------------------===//
24124 // X86 Inline Assembly Support
24125 //===----------------------------------------------------------------------===//
24128 // Helper to match a string separated by whitespace.
24129 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24130 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24132 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24133 StringRef piece(*args[i]);
24134 if (!s.startswith(piece)) // Check if the piece matches.
24137 s = s.substr(piece.size());
24138 StringRef::size_type pos = s.find_first_not_of(" \t");
24139 if (pos == 0) // We matched a prefix.
24147 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24150 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24152 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24153 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24154 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24155 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24157 if (AsmPieces.size() == 3)
24159 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24166 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24167 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24169 std::string AsmStr = IA->getAsmString();
24171 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24172 if (!Ty || Ty->getBitWidth() % 16 != 0)
24175 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24176 SmallVector<StringRef, 4> AsmPieces;
24177 SplitString(AsmStr, AsmPieces, ";\n");
24179 switch (AsmPieces.size()) {
24180 default: return false;
24182 // FIXME: this should verify that we are targeting a 486 or better. If not,
24183 // we will turn this bswap into something that will be lowered to logical
24184 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24185 // lower so don't worry about this.
24187 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24188 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24189 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24190 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24191 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24192 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24193 // No need to check constraints, nothing other than the equivalent of
24194 // "=r,0" would be valid here.
24195 return IntrinsicLowering::LowerToByteSwap(CI);
24198 // rorw $$8, ${0:w} --> llvm.bswap.i16
24199 if (CI->getType()->isIntegerTy(16) &&
24200 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24201 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24202 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24204 const std::string &ConstraintsStr = IA->getConstraintString();
24205 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24206 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24207 if (clobbersFlagRegisters(AsmPieces))
24208 return IntrinsicLowering::LowerToByteSwap(CI);
24212 if (CI->getType()->isIntegerTy(32) &&
24213 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24214 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24215 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24216 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24218 const std::string &ConstraintsStr = IA->getConstraintString();
24219 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24220 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24221 if (clobbersFlagRegisters(AsmPieces))
24222 return IntrinsicLowering::LowerToByteSwap(CI);
24225 if (CI->getType()->isIntegerTy(64)) {
24226 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24227 if (Constraints.size() >= 2 &&
24228 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24229 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24230 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24231 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24232 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24233 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24234 return IntrinsicLowering::LowerToByteSwap(CI);
24242 /// getConstraintType - Given a constraint letter, return the type of
24243 /// constraint it is for this target.
24244 X86TargetLowering::ConstraintType
24245 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24246 if (Constraint.size() == 1) {
24247 switch (Constraint[0]) {
24258 return C_RegisterClass;
24282 return TargetLowering::getConstraintType(Constraint);
24285 /// Examine constraint type and operand type and determine a weight value.
24286 /// This object must already have been set up with the operand type
24287 /// and the current alternative constraint selected.
24288 TargetLowering::ConstraintWeight
24289 X86TargetLowering::getSingleConstraintMatchWeight(
24290 AsmOperandInfo &info, const char *constraint) const {
24291 ConstraintWeight weight = CW_Invalid;
24292 Value *CallOperandVal = info.CallOperandVal;
24293 // If we don't have a value, we can't do a match,
24294 // but allow it at the lowest weight.
24295 if (!CallOperandVal)
24297 Type *type = CallOperandVal->getType();
24298 // Look at the constraint type.
24299 switch (*constraint) {
24301 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24312 if (CallOperandVal->getType()->isIntegerTy())
24313 weight = CW_SpecificReg;
24318 if (type->isFloatingPointTy())
24319 weight = CW_SpecificReg;
24322 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24323 weight = CW_SpecificReg;
24327 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24328 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24329 weight = CW_Register;
24332 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24333 if (C->getZExtValue() <= 31)
24334 weight = CW_Constant;
24338 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24339 if (C->getZExtValue() <= 63)
24340 weight = CW_Constant;
24344 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24345 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24346 weight = CW_Constant;
24350 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24351 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24352 weight = CW_Constant;
24356 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24357 if (C->getZExtValue() <= 3)
24358 weight = CW_Constant;
24362 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24363 if (C->getZExtValue() <= 0xff)
24364 weight = CW_Constant;
24369 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24370 weight = CW_Constant;
24374 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24375 if ((C->getSExtValue() >= -0x80000000LL) &&
24376 (C->getSExtValue() <= 0x7fffffffLL))
24377 weight = CW_Constant;
24381 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24382 if (C->getZExtValue() <= 0xffffffff)
24383 weight = CW_Constant;
24390 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24391 /// with another that has more specific requirements based on the type of the
24392 /// corresponding operand.
24393 const char *X86TargetLowering::
24394 LowerXConstraint(EVT ConstraintVT) const {
24395 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24396 // 'f' like normal targets.
24397 if (ConstraintVT.isFloatingPoint()) {
24398 if (Subtarget->hasSSE2())
24400 if (Subtarget->hasSSE1())
24404 return TargetLowering::LowerXConstraint(ConstraintVT);
24407 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24408 /// vector. If it is invalid, don't add anything to Ops.
24409 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24410 std::string &Constraint,
24411 std::vector<SDValue>&Ops,
24412 SelectionDAG &DAG) const {
24415 // Only support length 1 constraints for now.
24416 if (Constraint.length() > 1) return;
24418 char ConstraintLetter = Constraint[0];
24419 switch (ConstraintLetter) {
24422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24423 if (C->getZExtValue() <= 31) {
24424 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24431 if (C->getZExtValue() <= 63) {
24432 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24439 if (isInt<8>(C->getSExtValue())) {
24440 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24447 if (C->getZExtValue() <= 255) {
24448 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24454 // 32-bit signed value
24455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24456 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24457 C->getSExtValue())) {
24458 // Widen to 64 bits here to get it sign extended.
24459 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24462 // FIXME gcc accepts some relocatable values here too, but only in certain
24463 // memory models; it's complicated.
24468 // 32-bit unsigned value
24469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24470 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24471 C->getZExtValue())) {
24472 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24476 // FIXME gcc accepts some relocatable values here too, but only in certain
24477 // memory models; it's complicated.
24481 // Literal immediates are always ok.
24482 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24483 // Widen to 64 bits here to get it sign extended.
24484 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24488 // In any sort of PIC mode addresses need to be computed at runtime by
24489 // adding in a register or some sort of table lookup. These can't
24490 // be used as immediates.
24491 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24494 // If we are in non-pic codegen mode, we allow the address of a global (with
24495 // an optional displacement) to be used with 'i'.
24496 GlobalAddressSDNode *GA = nullptr;
24497 int64_t Offset = 0;
24499 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24501 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24502 Offset += GA->getOffset();
24504 } else if (Op.getOpcode() == ISD::ADD) {
24505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24506 Offset += C->getZExtValue();
24507 Op = Op.getOperand(0);
24510 } else if (Op.getOpcode() == ISD::SUB) {
24511 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24512 Offset += -C->getZExtValue();
24513 Op = Op.getOperand(0);
24518 // Otherwise, this isn't something we can handle, reject it.
24522 const GlobalValue *GV = GA->getGlobal();
24523 // If we require an extra load to get this address, as in PIC mode, we
24524 // can't accept it.
24525 if (isGlobalStubReference(
24526 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24529 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24530 GA->getValueType(0), Offset);
24535 if (Result.getNode()) {
24536 Ops.push_back(Result);
24539 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24542 std::pair<unsigned, const TargetRegisterClass*>
24543 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24545 // First, see if this is a constraint that directly corresponds to an LLVM
24547 if (Constraint.size() == 1) {
24548 // GCC Constraint Letters
24549 switch (Constraint[0]) {
24551 // TODO: Slight differences here in allocation order and leaving
24552 // RIP in the class. Do they matter any more here than they do
24553 // in the normal allocation?
24554 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24555 if (Subtarget->is64Bit()) {
24556 if (VT == MVT::i32 || VT == MVT::f32)
24557 return std::make_pair(0U, &X86::GR32RegClass);
24558 if (VT == MVT::i16)
24559 return std::make_pair(0U, &X86::GR16RegClass);
24560 if (VT == MVT::i8 || VT == MVT::i1)
24561 return std::make_pair(0U, &X86::GR8RegClass);
24562 if (VT == MVT::i64 || VT == MVT::f64)
24563 return std::make_pair(0U, &X86::GR64RegClass);
24566 // 32-bit fallthrough
24567 case 'Q': // Q_REGS
24568 if (VT == MVT::i32 || VT == MVT::f32)
24569 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24570 if (VT == MVT::i16)
24571 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24572 if (VT == MVT::i8 || VT == MVT::i1)
24573 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24574 if (VT == MVT::i64)
24575 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24577 case 'r': // GENERAL_REGS
24578 case 'l': // INDEX_REGS
24579 if (VT == MVT::i8 || VT == MVT::i1)
24580 return std::make_pair(0U, &X86::GR8RegClass);
24581 if (VT == MVT::i16)
24582 return std::make_pair(0U, &X86::GR16RegClass);
24583 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24584 return std::make_pair(0U, &X86::GR32RegClass);
24585 return std::make_pair(0U, &X86::GR64RegClass);
24586 case 'R': // LEGACY_REGS
24587 if (VT == MVT::i8 || VT == MVT::i1)
24588 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24589 if (VT == MVT::i16)
24590 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24591 if (VT == MVT::i32 || !Subtarget->is64Bit())
24592 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24593 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24594 case 'f': // FP Stack registers.
24595 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24596 // value to the correct fpstack register class.
24597 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24598 return std::make_pair(0U, &X86::RFP32RegClass);
24599 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24600 return std::make_pair(0U, &X86::RFP64RegClass);
24601 return std::make_pair(0U, &X86::RFP80RegClass);
24602 case 'y': // MMX_REGS if MMX allowed.
24603 if (!Subtarget->hasMMX()) break;
24604 return std::make_pair(0U, &X86::VR64RegClass);
24605 case 'Y': // SSE_REGS if SSE2 allowed
24606 if (!Subtarget->hasSSE2()) break;
24608 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24609 if (!Subtarget->hasSSE1()) break;
24611 switch (VT.SimpleTy) {
24613 // Scalar SSE types.
24616 return std::make_pair(0U, &X86::FR32RegClass);
24619 return std::make_pair(0U, &X86::FR64RegClass);
24627 return std::make_pair(0U, &X86::VR128RegClass);
24635 return std::make_pair(0U, &X86::VR256RegClass);
24640 return std::make_pair(0U, &X86::VR512RegClass);
24646 // Use the default implementation in TargetLowering to convert the register
24647 // constraint into a member of a register class.
24648 std::pair<unsigned, const TargetRegisterClass*> Res;
24649 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24651 // Not found as a standard register?
24653 // Map st(0) -> st(7) -> ST0
24654 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24655 tolower(Constraint[1]) == 's' &&
24656 tolower(Constraint[2]) == 't' &&
24657 Constraint[3] == '(' &&
24658 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24659 Constraint[5] == ')' &&
24660 Constraint[6] == '}') {
24662 Res.first = X86::FP0+Constraint[4]-'0';
24663 Res.second = &X86::RFP80RegClass;
24667 // GCC allows "st(0)" to be called just plain "st".
24668 if (StringRef("{st}").equals_lower(Constraint)) {
24669 Res.first = X86::FP0;
24670 Res.second = &X86::RFP80RegClass;
24675 if (StringRef("{flags}").equals_lower(Constraint)) {
24676 Res.first = X86::EFLAGS;
24677 Res.second = &X86::CCRRegClass;
24681 // 'A' means EAX + EDX.
24682 if (Constraint == "A") {
24683 Res.first = X86::EAX;
24684 Res.second = &X86::GR32_ADRegClass;
24690 // Otherwise, check to see if this is a register class of the wrong value
24691 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24692 // turn into {ax},{dx}.
24693 if (Res.second->hasType(VT))
24694 return Res; // Correct type already, nothing to do.
24696 // All of the single-register GCC register classes map their values onto
24697 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24698 // really want an 8-bit or 32-bit register, map to the appropriate register
24699 // class and return the appropriate register.
24700 if (Res.second == &X86::GR16RegClass) {
24701 if (VT == MVT::i8 || VT == MVT::i1) {
24702 unsigned DestReg = 0;
24703 switch (Res.first) {
24705 case X86::AX: DestReg = X86::AL; break;
24706 case X86::DX: DestReg = X86::DL; break;
24707 case X86::CX: DestReg = X86::CL; break;
24708 case X86::BX: DestReg = X86::BL; break;
24711 Res.first = DestReg;
24712 Res.second = &X86::GR8RegClass;
24714 } else if (VT == MVT::i32 || VT == MVT::f32) {
24715 unsigned DestReg = 0;
24716 switch (Res.first) {
24718 case X86::AX: DestReg = X86::EAX; break;
24719 case X86::DX: DestReg = X86::EDX; break;
24720 case X86::CX: DestReg = X86::ECX; break;
24721 case X86::BX: DestReg = X86::EBX; break;
24722 case X86::SI: DestReg = X86::ESI; break;
24723 case X86::DI: DestReg = X86::EDI; break;
24724 case X86::BP: DestReg = X86::EBP; break;
24725 case X86::SP: DestReg = X86::ESP; break;
24728 Res.first = DestReg;
24729 Res.second = &X86::GR32RegClass;
24731 } else if (VT == MVT::i64 || VT == MVT::f64) {
24732 unsigned DestReg = 0;
24733 switch (Res.first) {
24735 case X86::AX: DestReg = X86::RAX; break;
24736 case X86::DX: DestReg = X86::RDX; break;
24737 case X86::CX: DestReg = X86::RCX; break;
24738 case X86::BX: DestReg = X86::RBX; break;
24739 case X86::SI: DestReg = X86::RSI; break;
24740 case X86::DI: DestReg = X86::RDI; break;
24741 case X86::BP: DestReg = X86::RBP; break;
24742 case X86::SP: DestReg = X86::RSP; break;
24745 Res.first = DestReg;
24746 Res.second = &X86::GR64RegClass;
24749 } else if (Res.second == &X86::FR32RegClass ||
24750 Res.second == &X86::FR64RegClass ||
24751 Res.second == &X86::VR128RegClass ||
24752 Res.second == &X86::VR256RegClass ||
24753 Res.second == &X86::FR32XRegClass ||
24754 Res.second == &X86::FR64XRegClass ||
24755 Res.second == &X86::VR128XRegClass ||
24756 Res.second == &X86::VR256XRegClass ||
24757 Res.second == &X86::VR512RegClass) {
24758 // Handle references to XMM physical registers that got mapped into the
24759 // wrong class. This can happen with constraints like {xmm0} where the
24760 // target independent register mapper will just pick the first match it can
24761 // find, ignoring the required type.
24763 if (VT == MVT::f32 || VT == MVT::i32)
24764 Res.second = &X86::FR32RegClass;
24765 else if (VT == MVT::f64 || VT == MVT::i64)
24766 Res.second = &X86::FR64RegClass;
24767 else if (X86::VR128RegClass.hasType(VT))
24768 Res.second = &X86::VR128RegClass;
24769 else if (X86::VR256RegClass.hasType(VT))
24770 Res.second = &X86::VR256RegClass;
24771 else if (X86::VR512RegClass.hasType(VT))
24772 Res.second = &X86::VR512RegClass;
24778 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24780 // Scaling factors are not free at all.
24781 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24782 // will take 2 allocations in the out of order engine instead of 1
24783 // for plain addressing mode, i.e. inst (reg1).
24785 // vaddps (%rsi,%drx), %ymm0, %ymm1
24786 // Requires two allocations (one for the load, one for the computation)
24788 // vaddps (%rsi), %ymm0, %ymm1
24789 // Requires just 1 allocation, i.e., freeing allocations for other operations
24790 // and having less micro operations to execute.
24792 // For some X86 architectures, this is even worse because for instance for
24793 // stores, the complex addressing mode forces the instruction to use the
24794 // "load" ports instead of the dedicated "store" port.
24795 // E.g., on Haswell:
24796 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24797 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24798 if (isLegalAddressingMode(AM, Ty))
24799 // Scale represents reg2 * scale, thus account for 1
24800 // as soon as we use a second register.
24801 return AM.Scale != 0;
24805 bool X86TargetLowering::isTargetFTOL() const {
24806 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();