1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILPI:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILPI:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILPI:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 SDValue Op = MaskNode->getOperand(i);
5351 if (Op->getOpcode() == ISD::UNDEF) {
5352 RawMask.push_back((uint64_t)SM_SentinelUndef);
5355 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5358 APInt MaskElement = CN->getAPIntValue();
5360 // We now have to decode the element which could be any integer size and
5361 // extract each byte of it.
5362 for (int j = 0; j < NumBytesPerElement; ++j) {
5363 // Note that this is x86 and so always little endian: the low byte is
5364 // the first byte of the mask.
5365 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5366 MaskElement = MaskElement.lshr(8);
5369 DecodePSHUFBMask(RawMask, Mask);
5373 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5377 SDValue Ptr = MaskLoad->getBasePtr();
5378 if (Ptr->getOpcode() == X86ISD::Wrapper)
5379 Ptr = Ptr->getOperand(0);
5381 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5382 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5385 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5386 // FIXME: Support AVX-512 here.
5387 Type *Ty = C->getType();
5388 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5389 Ty->getVectorNumElements() != 32))
5392 DecodePSHUFBMask(C, Mask);
5398 case X86ISD::VPERMI:
5399 ImmN = N->getOperand(N->getNumOperands()-1);
5400 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5404 case X86ISD::MOVSD: {
5405 // The index 0 always comes from the first element of the second source,
5406 // this is why MOVSS and MOVSD are used in the first place. The other
5407 // elements come from the other positions of the first source vector
5408 Mask.push_back(NumElems);
5409 for (unsigned i = 1; i != NumElems; ++i) {
5414 case X86ISD::VPERM2X128:
5415 ImmN = N->getOperand(N->getNumOperands()-1);
5416 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5417 if (Mask.empty()) return false;
5419 case X86ISD::MOVSLDUP:
5420 DecodeMOVSLDUPMask(VT, Mask);
5422 case X86ISD::MOVSHDUP:
5423 DecodeMOVSHDUPMask(VT, Mask);
5425 case X86ISD::MOVDDUP:
5426 case X86ISD::MOVLHPD:
5427 case X86ISD::MOVLPD:
5428 case X86ISD::MOVLPS:
5429 // Not yet implemented
5431 default: llvm_unreachable("unknown target shuffle node");
5434 // If we have a fake unary shuffle, the shuffle mask is spread across two
5435 // inputs that are actually the same node. Re-map the mask to always point
5436 // into the first input.
5439 if (M >= (int)Mask.size())
5445 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5446 /// element of the result of the vector shuffle.
5447 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5450 return SDValue(); // Limit search depth.
5452 SDValue V = SDValue(N, 0);
5453 EVT VT = V.getValueType();
5454 unsigned Opcode = V.getOpcode();
5456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5458 int Elt = SV->getMaskElt(Index);
5461 return DAG.getUNDEF(VT.getVectorElementType());
5463 unsigned NumElems = VT.getVectorNumElements();
5464 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5465 : SV->getOperand(1);
5466 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5469 // Recurse into target specific vector shuffles to find scalars.
5470 if (isTargetShuffle(Opcode)) {
5471 MVT ShufVT = V.getSimpleValueType();
5472 unsigned NumElems = ShufVT.getVectorNumElements();
5473 SmallVector<int, 16> ShuffleMask;
5476 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5479 int Elt = ShuffleMask[Index];
5481 return DAG.getUNDEF(ShufVT.getVectorElementType());
5483 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5485 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5489 // Actual nodes that may contain scalar elements
5490 if (Opcode == ISD::BITCAST) {
5491 V = V.getOperand(0);
5492 EVT SrcVT = V.getValueType();
5493 unsigned NumElems = VT.getVectorNumElements();
5495 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5499 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5500 return (Index == 0) ? V.getOperand(0)
5501 : DAG.getUNDEF(VT.getVectorElementType());
5503 if (V.getOpcode() == ISD::BUILD_VECTOR)
5504 return V.getOperand(Index);
5509 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5510 /// shuffle operation which come from a consecutively from a zero. The
5511 /// search can start in two different directions, from left or right.
5512 /// We count undefs as zeros until PreferredNum is reached.
5513 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5514 unsigned NumElems, bool ZerosFromLeft,
5516 unsigned PreferredNum = -1U) {
5517 unsigned NumZeros = 0;
5518 for (unsigned i = 0; i != NumElems; ++i) {
5519 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5520 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5524 if (X86::isZeroNode(Elt))
5526 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5527 NumZeros = std::min(NumZeros + 1, PreferredNum);
5535 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5536 /// correspond consecutively to elements from one of the vector operands,
5537 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5539 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5540 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5541 unsigned NumElems, unsigned &OpNum) {
5542 bool SeenV1 = false;
5543 bool SeenV2 = false;
5545 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5546 int Idx = SVOp->getMaskElt(i);
5547 // Ignore undef indicies
5551 if (Idx < (int)NumElems)
5556 // Only accept consecutive elements from the same vector
5557 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5561 OpNum = SeenV1 ? 0 : 1;
5565 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5566 /// logical left shift of a vector.
5567 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5568 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5570 SVOp->getSimpleValueType(0).getVectorNumElements();
5571 unsigned NumZeros = getNumOfConsecutiveZeros(
5572 SVOp, NumElems, false /* check zeros from right */, DAG,
5573 SVOp->getMaskElt(0));
5579 // Considering the elements in the mask that are not consecutive zeros,
5580 // check if they consecutively come from only one of the source vectors.
5582 // V1 = {X, A, B, C} 0
5584 // vector_shuffle V1, V2 <1, 2, 3, X>
5586 if (!isShuffleMaskConsecutive(SVOp,
5587 0, // Mask Start Index
5588 NumElems-NumZeros, // Mask End Index(exclusive)
5589 NumZeros, // Where to start looking in the src vector
5590 NumElems, // Number of elements in vector
5591 OpSrc)) // Which source operand ?
5596 ShVal = SVOp->getOperand(OpSrc);
5600 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5601 /// logical left shift of a vector.
5602 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5603 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5605 SVOp->getSimpleValueType(0).getVectorNumElements();
5606 unsigned NumZeros = getNumOfConsecutiveZeros(
5607 SVOp, NumElems, true /* check zeros from left */, DAG,
5608 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5614 // Considering the elements in the mask that are not consecutive zeros,
5615 // check if they consecutively come from only one of the source vectors.
5617 // 0 { A, B, X, X } = V2
5619 // vector_shuffle V1, V2 <X, X, 4, 5>
5621 if (!isShuffleMaskConsecutive(SVOp,
5622 NumZeros, // Mask Start Index
5623 NumElems, // Mask End Index(exclusive)
5624 0, // Where to start looking in the src vector
5625 NumElems, // Number of elements in vector
5626 OpSrc)) // Which source operand ?
5631 ShVal = SVOp->getOperand(OpSrc);
5635 /// isVectorShift - Returns true if the shuffle can be implemented as a
5636 /// logical left or right shift of a vector.
5637 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5638 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5639 // Although the logic below support any bitwidth size, there are no
5640 // shift instructions which handle more than 128-bit vectors.
5641 if (!SVOp->getSimpleValueType(0).is128BitVector())
5644 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5645 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5651 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5653 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5654 unsigned NumNonZero, unsigned NumZero,
5656 const X86Subtarget* Subtarget,
5657 const TargetLowering &TLI) {
5664 for (unsigned i = 0; i < 16; ++i) {
5665 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5666 if (ThisIsNonZero && First) {
5668 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5670 V = DAG.getUNDEF(MVT::v8i16);
5675 SDValue ThisElt, LastElt;
5676 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5677 if (LastIsNonZero) {
5678 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5679 MVT::i16, Op.getOperand(i-1));
5681 if (ThisIsNonZero) {
5682 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5683 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5684 ThisElt, DAG.getConstant(8, MVT::i8));
5686 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5690 if (ThisElt.getNode())
5691 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5692 DAG.getIntPtrConstant(i/2));
5696 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5699 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5701 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5702 unsigned NumNonZero, unsigned NumZero,
5704 const X86Subtarget* Subtarget,
5705 const TargetLowering &TLI) {
5712 for (unsigned i = 0; i < 8; ++i) {
5713 bool isNonZero = (NonZeros & (1 << i)) != 0;
5717 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5719 V = DAG.getUNDEF(MVT::v8i16);
5722 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5723 MVT::v8i16, V, Op.getOperand(i),
5724 DAG.getIntPtrConstant(i));
5731 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5732 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5733 unsigned NonZeros, unsigned NumNonZero,
5734 unsigned NumZero, SelectionDAG &DAG,
5735 const X86Subtarget *Subtarget,
5736 const TargetLowering &TLI) {
5737 // We know there's at least one non-zero element
5738 unsigned FirstNonZeroIdx = 0;
5739 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5740 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5741 X86::isZeroNode(FirstNonZero)) {
5743 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5747 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5750 SDValue V = FirstNonZero.getOperand(0);
5751 MVT VVT = V.getSimpleValueType();
5752 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5755 unsigned FirstNonZeroDst =
5756 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5757 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5758 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5759 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5761 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5762 SDValue Elem = Op.getOperand(Idx);
5763 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5766 // TODO: What else can be here? Deal with it.
5767 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5770 // TODO: Some optimizations are still possible here
5771 // ex: Getting one element from a vector, and the rest from another.
5772 if (Elem.getOperand(0) != V)
5775 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5778 else if (IncorrectIdx == -1U) {
5782 // There was already one element with an incorrect index.
5783 // We can't optimize this case to an insertps.
5787 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5789 EVT VT = Op.getSimpleValueType();
5790 unsigned ElementMoveMask = 0;
5791 if (IncorrectIdx == -1U)
5792 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5794 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5796 SDValue InsertpsMask =
5797 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5798 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5804 /// getVShift - Return a vector logical shift node.
5806 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5807 unsigned NumBits, SelectionDAG &DAG,
5808 const TargetLowering &TLI, SDLoc dl) {
5809 assert(VT.is128BitVector() && "Unknown type for VShift");
5810 EVT ShVT = MVT::v2i64;
5811 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5812 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5813 return DAG.getNode(ISD::BITCAST, dl, VT,
5814 DAG.getNode(Opc, dl, ShVT, SrcOp,
5815 DAG.getConstant(NumBits,
5816 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5820 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5822 // Check if the scalar load can be widened into a vector load. And if
5823 // the address is "base + cst" see if the cst can be "absorbed" into
5824 // the shuffle mask.
5825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5826 SDValue Ptr = LD->getBasePtr();
5827 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5829 EVT PVT = LD->getValueType(0);
5830 if (PVT != MVT::i32 && PVT != MVT::f32)
5835 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5836 FI = FINode->getIndex();
5838 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5839 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5840 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5841 Offset = Ptr.getConstantOperandVal(1);
5842 Ptr = Ptr.getOperand(0);
5847 // FIXME: 256-bit vector instructions don't require a strict alignment,
5848 // improve this code to support it better.
5849 unsigned RequiredAlign = VT.getSizeInBits()/8;
5850 SDValue Chain = LD->getChain();
5851 // Make sure the stack object alignment is at least 16 or 32.
5852 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5853 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5854 if (MFI->isFixedObjectIndex(FI)) {
5855 // Can't change the alignment. FIXME: It's possible to compute
5856 // the exact stack offset and reference FI + adjust offset instead.
5857 // If someone *really* cares about this. That's the way to implement it.
5860 MFI->setObjectAlignment(FI, RequiredAlign);
5864 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5865 // Ptr + (Offset & ~15).
5868 if ((Offset % RequiredAlign) & 3)
5870 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5872 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5873 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5875 int EltNo = (Offset - StartOffset) >> 2;
5876 unsigned NumElems = VT.getVectorNumElements();
5878 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5879 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5880 LD->getPointerInfo().getWithOffset(StartOffset),
5881 false, false, false, 0);
5883 SmallVector<int, 8> Mask;
5884 for (unsigned i = 0; i != NumElems; ++i)
5885 Mask.push_back(EltNo);
5887 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5893 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5894 /// vector of type 'VT', see if the elements can be replaced by a single large
5895 /// load which has the same value as a build_vector whose operands are 'elts'.
5897 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5899 /// FIXME: we'd also like to handle the case where the last elements are zero
5900 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5901 /// There's even a handy isZeroNode for that purpose.
5902 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5903 SDLoc &DL, SelectionDAG &DAG,
5904 bool isAfterLegalize) {
5905 EVT EltVT = VT.getVectorElementType();
5906 unsigned NumElems = Elts.size();
5908 LoadSDNode *LDBase = nullptr;
5909 unsigned LastLoadedElt = -1U;
5911 // For each element in the initializer, see if we've found a load or an undef.
5912 // If we don't find an initial load element, or later load elements are
5913 // non-consecutive, bail out.
5914 for (unsigned i = 0; i < NumElems; ++i) {
5915 SDValue Elt = Elts[i];
5917 if (!Elt.getNode() ||
5918 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5921 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5923 LDBase = cast<LoadSDNode>(Elt.getNode());
5927 if (Elt.getOpcode() == ISD::UNDEF)
5930 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5931 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5936 // If we have found an entire vector of loads and undefs, then return a large
5937 // load of the entire vector width starting at the base pointer. If we found
5938 // consecutive loads for the low half, generate a vzext_load node.
5939 if (LastLoadedElt == NumElems - 1) {
5941 if (isAfterLegalize &&
5942 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5945 SDValue NewLd = SDValue();
5947 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5948 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5949 LDBase->getPointerInfo(),
5950 LDBase->isVolatile(), LDBase->isNonTemporal(),
5951 LDBase->isInvariant(), 0);
5952 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5953 LDBase->getPointerInfo(),
5954 LDBase->isVolatile(), LDBase->isNonTemporal(),
5955 LDBase->isInvariant(), LDBase->getAlignment());
5957 if (LDBase->hasAnyUseOfValue(1)) {
5958 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5960 SDValue(NewLd.getNode(), 1));
5961 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5962 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5963 SDValue(NewLd.getNode(), 1));
5968 if (NumElems == 4 && LastLoadedElt == 1 &&
5969 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5970 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5971 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5973 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5974 LDBase->getPointerInfo(),
5975 LDBase->getAlignment(),
5976 false/*isVolatile*/, true/*ReadMem*/,
5979 // Make sure the newly-created LOAD is in the same position as LDBase in
5980 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5981 // update uses of LDBase's output chain to use the TokenFactor.
5982 if (LDBase->hasAnyUseOfValue(1)) {
5983 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5984 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5985 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5986 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5987 SDValue(ResNode.getNode(), 1));
5990 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5995 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5996 /// to generate a splat value for the following cases:
5997 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5998 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5999 /// a scalar load, or a constant.
6000 /// The VBROADCAST node is returned when a pattern is found,
6001 /// or SDValue() otherwise.
6002 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6003 SelectionDAG &DAG) {
6004 // VBROADCAST requires AVX.
6005 // TODO: Splats could be generated for non-AVX CPUs using SSE
6006 // instructions, but there's less potential gain for only 128-bit vectors.
6007 if (!Subtarget->hasAVX())
6010 MVT VT = Op.getSimpleValueType();
6013 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6014 "Unsupported vector type for broadcast.");
6019 switch (Op.getOpcode()) {
6021 // Unknown pattern found.
6024 case ISD::BUILD_VECTOR: {
6025 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6026 BitVector UndefElements;
6027 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6029 // We need a splat of a single value to use broadcast, and it doesn't
6030 // make any sense if the value is only in one element of the vector.
6031 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6035 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6036 Ld.getOpcode() == ISD::ConstantFP);
6038 // Make sure that all of the users of a non-constant load are from the
6039 // BUILD_VECTOR node.
6040 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6045 case ISD::VECTOR_SHUFFLE: {
6046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6048 // Shuffles must have a splat mask where the first element is
6050 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6053 SDValue Sc = Op.getOperand(0);
6054 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6055 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6057 if (!Subtarget->hasInt256())
6060 // Use the register form of the broadcast instruction available on AVX2.
6061 if (VT.getSizeInBits() >= 256)
6062 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6063 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6066 Ld = Sc.getOperand(0);
6067 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6068 Ld.getOpcode() == ISD::ConstantFP);
6070 // The scalar_to_vector node and the suspected
6071 // load node must have exactly one user.
6072 // Constants may have multiple users.
6074 // AVX-512 has register version of the broadcast
6075 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6076 Ld.getValueType().getSizeInBits() >= 32;
6077 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6084 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6085 bool IsGE256 = (VT.getSizeInBits() >= 256);
6087 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6088 // instruction to save 8 or more bytes of constant pool data.
6089 // TODO: If multiple splats are generated to load the same constant,
6090 // it may be detrimental to overall size. There needs to be a way to detect
6091 // that condition to know if this is truly a size win.
6092 const Function *F = DAG.getMachineFunction().getFunction();
6093 bool OptForSize = F->getAttributes().
6094 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6096 // Handle broadcasting a single constant scalar from the constant pool
6098 // On Sandybridge (no AVX2), it is still better to load a constant vector
6099 // from the constant pool and not to broadcast it from a scalar.
6100 // But override that restriction when optimizing for size.
6101 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6102 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6103 EVT CVT = Ld.getValueType();
6104 assert(!CVT.isVector() && "Must not broadcast a vector type");
6106 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6107 // For size optimization, also splat v2f64 and v2i64, and for size opt
6108 // with AVX2, also splat i8 and i16.
6109 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6110 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6111 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6112 const Constant *C = nullptr;
6113 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6114 C = CI->getConstantIntValue();
6115 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6116 C = CF->getConstantFPValue();
6118 assert(C && "Invalid constant type");
6120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6121 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6122 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6123 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6124 MachinePointerInfo::getConstantPool(),
6125 false, false, false, Alignment);
6127 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6131 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6133 // Handle AVX2 in-register broadcasts.
6134 if (!IsLoad && Subtarget->hasInt256() &&
6135 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6136 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6138 // The scalar source must be a normal load.
6142 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6143 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6145 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6146 // double since there is no vbroadcastsd xmm
6147 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6148 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6152 // Unsupported broadcast.
6156 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6157 /// underlying vector and index.
6159 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6161 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6163 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6164 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6167 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6169 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6171 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6172 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6175 // In this case the vector is the extract_subvector expression and the index
6176 // is 2, as specified by the shuffle.
6177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6178 SDValue ShuffleVec = SVOp->getOperand(0);
6179 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6180 assert(ShuffleVecVT.getVectorElementType() ==
6181 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6183 int ShuffleIdx = SVOp->getMaskElt(Idx);
6184 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6185 ExtractedFromVec = ShuffleVec;
6191 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6192 MVT VT = Op.getSimpleValueType();
6194 // Skip if insert_vec_elt is not supported.
6195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6196 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6200 unsigned NumElems = Op.getNumOperands();
6204 SmallVector<unsigned, 4> InsertIndices;
6205 SmallVector<int, 8> Mask(NumElems, -1);
6207 for (unsigned i = 0; i != NumElems; ++i) {
6208 unsigned Opc = Op.getOperand(i).getOpcode();
6210 if (Opc == ISD::UNDEF)
6213 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6214 // Quit if more than 1 elements need inserting.
6215 if (InsertIndices.size() > 1)
6218 InsertIndices.push_back(i);
6222 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6223 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6224 // Quit if non-constant index.
6225 if (!isa<ConstantSDNode>(ExtIdx))
6227 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6229 // Quit if extracted from vector of different type.
6230 if (ExtractedFromVec.getValueType() != VT)
6233 if (!VecIn1.getNode())
6234 VecIn1 = ExtractedFromVec;
6235 else if (VecIn1 != ExtractedFromVec) {
6236 if (!VecIn2.getNode())
6237 VecIn2 = ExtractedFromVec;
6238 else if (VecIn2 != ExtractedFromVec)
6239 // Quit if more than 2 vectors to shuffle
6243 if (ExtractedFromVec == VecIn1)
6245 else if (ExtractedFromVec == VecIn2)
6246 Mask[i] = Idx + NumElems;
6249 if (!VecIn1.getNode())
6252 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6253 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6254 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6255 unsigned Idx = InsertIndices[i];
6256 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6257 DAG.getIntPtrConstant(Idx));
6263 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6265 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6267 MVT VT = Op.getSimpleValueType();
6268 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6269 "Unexpected type in LowerBUILD_VECTORvXi1!");
6272 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6273 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6274 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6275 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6278 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 bool AllContants = true;
6285 uint64_t Immediate = 0;
6286 int NonConstIdx = -1;
6287 bool IsSplat = true;
6288 unsigned NumNonConsts = 0;
6289 unsigned NumConsts = 0;
6290 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6291 SDValue In = Op.getOperand(idx);
6292 if (In.getOpcode() == ISD::UNDEF)
6294 if (!isa<ConstantSDNode>(In)) {
6295 AllContants = false;
6301 if (cast<ConstantSDNode>(In)->getZExtValue())
6302 Immediate |= (1ULL << idx);
6304 if (In != Op.getOperand(0))
6309 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6310 DAG.getConstant(Immediate, MVT::i16));
6311 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6312 DAG.getIntPtrConstant(0));
6315 if (NumNonConsts == 1 && NonConstIdx != 0) {
6318 SDValue VecAsImm = DAG.getConstant(Immediate,
6319 MVT::getIntegerVT(VT.getSizeInBits()));
6320 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6323 DstVec = DAG.getUNDEF(VT);
6324 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6325 Op.getOperand(NonConstIdx),
6326 DAG.getIntPtrConstant(NonConstIdx));
6328 if (!IsSplat && (NonConstIdx != 0))
6329 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6330 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6333 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6334 DAG.getConstant(-1, SelectVT),
6335 DAG.getConstant(0, SelectVT));
6337 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6338 DAG.getConstant((Immediate | 1), SelectVT),
6339 DAG.getConstant(Immediate, SelectVT));
6340 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6343 /// \brief Return true if \p N implements a horizontal binop and return the
6344 /// operands for the horizontal binop into V0 and V1.
6346 /// This is a helper function of PerformBUILD_VECTORCombine.
6347 /// This function checks that the build_vector \p N in input implements a
6348 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6349 /// operation to match.
6350 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6351 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6352 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6355 /// This function only analyzes elements of \p N whose indices are
6356 /// in range [BaseIdx, LastIdx).
6357 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6359 unsigned BaseIdx, unsigned LastIdx,
6360 SDValue &V0, SDValue &V1) {
6361 EVT VT = N->getValueType(0);
6363 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6364 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6365 "Invalid Vector in input!");
6367 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6368 bool CanFold = true;
6369 unsigned ExpectedVExtractIdx = BaseIdx;
6370 unsigned NumElts = LastIdx - BaseIdx;
6371 V0 = DAG.getUNDEF(VT);
6372 V1 = DAG.getUNDEF(VT);
6374 // Check if N implements a horizontal binop.
6375 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6376 SDValue Op = N->getOperand(i + BaseIdx);
6379 if (Op->getOpcode() == ISD::UNDEF) {
6380 // Update the expected vector extract index.
6381 if (i * 2 == NumElts)
6382 ExpectedVExtractIdx = BaseIdx;
6383 ExpectedVExtractIdx += 2;
6387 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6392 SDValue Op0 = Op.getOperand(0);
6393 SDValue Op1 = Op.getOperand(1);
6395 // Try to match the following pattern:
6396 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6397 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6398 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6399 Op0.getOperand(0) == Op1.getOperand(0) &&
6400 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6401 isa<ConstantSDNode>(Op1.getOperand(1)));
6405 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6406 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6408 if (i * 2 < NumElts) {
6409 if (V0.getOpcode() == ISD::UNDEF)
6410 V0 = Op0.getOperand(0);
6412 if (V1.getOpcode() == ISD::UNDEF)
6413 V1 = Op0.getOperand(0);
6414 if (i * 2 == NumElts)
6415 ExpectedVExtractIdx = BaseIdx;
6418 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6419 if (I0 == ExpectedVExtractIdx)
6420 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6421 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6422 // Try to match the following dag sequence:
6423 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6424 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6428 ExpectedVExtractIdx += 2;
6434 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6435 /// a concat_vector.
6437 /// This is a helper function of PerformBUILD_VECTORCombine.
6438 /// This function expects two 256-bit vectors called V0 and V1.
6439 /// At first, each vector is split into two separate 128-bit vectors.
6440 /// Then, the resulting 128-bit vectors are used to implement two
6441 /// horizontal binary operations.
6443 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6445 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6446 /// the two new horizontal binop.
6447 /// When Mode is set, the first horizontal binop dag node would take as input
6448 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6449 /// horizontal binop dag node would take as input the lower 128-bit of V1
6450 /// and the upper 128-bit of V1.
6452 /// HADD V0_LO, V0_HI
6453 /// HADD V1_LO, V1_HI
6455 /// Otherwise, the first horizontal binop dag node takes as input the lower
6456 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6457 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6459 /// HADD V0_LO, V1_LO
6460 /// HADD V0_HI, V1_HI
6462 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6463 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6464 /// the upper 128-bits of the result.
6465 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6466 SDLoc DL, SelectionDAG &DAG,
6467 unsigned X86Opcode, bool Mode,
6468 bool isUndefLO, bool isUndefHI) {
6469 EVT VT = V0.getValueType();
6470 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6471 "Invalid nodes in input!");
6473 unsigned NumElts = VT.getVectorNumElements();
6474 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6475 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6476 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6477 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6478 EVT NewVT = V0_LO.getValueType();
6480 SDValue LO = DAG.getUNDEF(NewVT);
6481 SDValue HI = DAG.getUNDEF(NewVT);
6484 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6485 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6486 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6487 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6488 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6492 V1_LO->getOpcode() != ISD::UNDEF))
6493 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6495 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6496 V1_HI->getOpcode() != ISD::UNDEF))
6497 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6500 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6503 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6504 /// sequence of 'vadd + vsub + blendi'.
6505 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6506 const X86Subtarget *Subtarget) {
6508 EVT VT = BV->getValueType(0);
6509 unsigned NumElts = VT.getVectorNumElements();
6510 SDValue InVec0 = DAG.getUNDEF(VT);
6511 SDValue InVec1 = DAG.getUNDEF(VT);
6513 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6514 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6516 // Odd-numbered elements in the input build vector are obtained from
6517 // adding two integer/float elements.
6518 // Even-numbered elements in the input build vector are obtained from
6519 // subtracting two integer/float elements.
6520 unsigned ExpectedOpcode = ISD::FSUB;
6521 unsigned NextExpectedOpcode = ISD::FADD;
6522 bool AddFound = false;
6523 bool SubFound = false;
6525 for (unsigned i = 0, e = NumElts; i != e; i++) {
6526 SDValue Op = BV->getOperand(i);
6528 // Skip 'undef' values.
6529 unsigned Opcode = Op.getOpcode();
6530 if (Opcode == ISD::UNDEF) {
6531 std::swap(ExpectedOpcode, NextExpectedOpcode);
6535 // Early exit if we found an unexpected opcode.
6536 if (Opcode != ExpectedOpcode)
6539 SDValue Op0 = Op.getOperand(0);
6540 SDValue Op1 = Op.getOperand(1);
6542 // Try to match the following pattern:
6543 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6544 // Early exit if we cannot match that sequence.
6545 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6546 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6547 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6548 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6549 Op0.getOperand(1) != Op1.getOperand(1))
6552 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6556 // We found a valid add/sub node. Update the information accordingly.
6562 // Update InVec0 and InVec1.
6563 if (InVec0.getOpcode() == ISD::UNDEF)
6564 InVec0 = Op0.getOperand(0);
6565 if (InVec1.getOpcode() == ISD::UNDEF)
6566 InVec1 = Op1.getOperand(0);
6568 // Make sure that operands in input to each add/sub node always
6569 // come from a same pair of vectors.
6570 if (InVec0 != Op0.getOperand(0)) {
6571 if (ExpectedOpcode == ISD::FSUB)
6574 // FADD is commutable. Try to commute the operands
6575 // and then test again.
6576 std::swap(Op0, Op1);
6577 if (InVec0 != Op0.getOperand(0))
6581 if (InVec1 != Op1.getOperand(0))
6584 // Update the pair of expected opcodes.
6585 std::swap(ExpectedOpcode, NextExpectedOpcode);
6588 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6589 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6590 InVec1.getOpcode() != ISD::UNDEF)
6591 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6596 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6597 const X86Subtarget *Subtarget) {
6599 EVT VT = N->getValueType(0);
6600 unsigned NumElts = VT.getVectorNumElements();
6601 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6602 SDValue InVec0, InVec1;
6604 // Try to match an ADDSUB.
6605 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6606 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6607 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6608 if (Value.getNode())
6612 // Try to match horizontal ADD/SUB.
6613 unsigned NumUndefsLO = 0;
6614 unsigned NumUndefsHI = 0;
6615 unsigned Half = NumElts/2;
6617 // Count the number of UNDEF operands in the build_vector in input.
6618 for (unsigned i = 0, e = Half; i != e; ++i)
6619 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6622 for (unsigned i = Half, e = NumElts; i != e; ++i)
6623 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6626 // Early exit if this is either a build_vector of all UNDEFs or all the
6627 // operands but one are UNDEF.
6628 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6631 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6632 // Try to match an SSE3 float HADD/HSUB.
6633 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6634 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6636 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6637 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6638 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6639 // Try to match an SSSE3 integer HADD/HSUB.
6640 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6641 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6643 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6644 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6647 if (!Subtarget->hasAVX())
6650 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6651 // Try to match an AVX horizontal add/sub of packed single/double
6652 // precision floating point values from 256-bit vectors.
6653 SDValue InVec2, InVec3;
6654 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6655 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6656 ((InVec0.getOpcode() == ISD::UNDEF ||
6657 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6658 ((InVec1.getOpcode() == ISD::UNDEF ||
6659 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6660 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6662 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6663 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6664 ((InVec0.getOpcode() == ISD::UNDEF ||
6665 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6666 ((InVec1.getOpcode() == ISD::UNDEF ||
6667 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6668 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6669 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6670 // Try to match an AVX2 horizontal add/sub of signed integers.
6671 SDValue InVec2, InVec3;
6673 bool CanFold = true;
6675 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6676 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6677 ((InVec0.getOpcode() == ISD::UNDEF ||
6678 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6679 ((InVec1.getOpcode() == ISD::UNDEF ||
6680 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6681 X86Opcode = X86ISD::HADD;
6682 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6683 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6684 ((InVec0.getOpcode() == ISD::UNDEF ||
6685 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6686 ((InVec1.getOpcode() == ISD::UNDEF ||
6687 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6688 X86Opcode = X86ISD::HSUB;
6693 // Fold this build_vector into a single horizontal add/sub.
6694 // Do this only if the target has AVX2.
6695 if (Subtarget->hasAVX2())
6696 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6698 // Do not try to expand this build_vector into a pair of horizontal
6699 // add/sub if we can emit a pair of scalar add/sub.
6700 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6703 // Convert this build_vector into a pair of horizontal binop followed by
6705 bool isUndefLO = NumUndefsLO == Half;
6706 bool isUndefHI = NumUndefsHI == Half;
6707 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6708 isUndefLO, isUndefHI);
6712 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6713 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6715 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6716 X86Opcode = X86ISD::HADD;
6717 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6718 X86Opcode = X86ISD::HSUB;
6719 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6720 X86Opcode = X86ISD::FHADD;
6721 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::FHSUB;
6726 // Don't try to expand this build_vector into a pair of horizontal add/sub
6727 // if we can simply emit a pair of scalar add/sub.
6728 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6731 // Convert this build_vector into two horizontal add/sub followed by
6733 bool isUndefLO = NumUndefsLO == Half;
6734 bool isUndefHI = NumUndefsHI == Half;
6735 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6736 isUndefLO, isUndefHI);
6743 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6746 MVT VT = Op.getSimpleValueType();
6747 MVT ExtVT = VT.getVectorElementType();
6748 unsigned NumElems = Op.getNumOperands();
6750 // Generate vectors for predicate vectors.
6751 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6752 return LowerBUILD_VECTORvXi1(Op, DAG);
6754 // Vectors containing all zeros can be matched by pxor and xorps later
6755 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6756 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6757 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6758 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6761 return getZeroVector(VT, Subtarget, DAG, dl);
6764 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6765 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6766 // vpcmpeqd on 256-bit vectors.
6767 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6768 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6771 if (!VT.is512BitVector())
6772 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6775 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6776 if (Broadcast.getNode())
6779 unsigned EVTBits = ExtVT.getSizeInBits();
6781 unsigned NumZero = 0;
6782 unsigned NumNonZero = 0;
6783 unsigned NonZeros = 0;
6784 bool IsAllConstants = true;
6785 SmallSet<SDValue, 8> Values;
6786 for (unsigned i = 0; i < NumElems; ++i) {
6787 SDValue Elt = Op.getOperand(i);
6788 if (Elt.getOpcode() == ISD::UNDEF)
6791 if (Elt.getOpcode() != ISD::Constant &&
6792 Elt.getOpcode() != ISD::ConstantFP)
6793 IsAllConstants = false;
6794 if (X86::isZeroNode(Elt))
6797 NonZeros |= (1 << i);
6802 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6803 if (NumNonZero == 0)
6804 return DAG.getUNDEF(VT);
6806 // Special case for single non-zero, non-undef, element.
6807 if (NumNonZero == 1) {
6808 unsigned Idx = countTrailingZeros(NonZeros);
6809 SDValue Item = Op.getOperand(Idx);
6811 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6812 // the value are obviously zero, truncate the value to i32 and do the
6813 // insertion that way. Only do this if the value is non-constant or if the
6814 // value is a constant being inserted into element 0. It is cheaper to do
6815 // a constant pool load than it is to do a movd + shuffle.
6816 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6817 (!IsAllConstants || Idx == 0)) {
6818 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6820 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6821 EVT VecVT = MVT::v4i32;
6822 unsigned VecElts = 4;
6824 // Truncate the value (which may itself be a constant) to i32, and
6825 // convert it to a vector with movd (S2V+shuffle to zero extend).
6826 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6827 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6829 // If using the new shuffle lowering, just directly insert this.
6830 if (ExperimentalVectorShuffleLowering)
6832 ISD::BITCAST, dl, VT,
6833 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6835 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6837 // Now we have our 32-bit value zero extended in the low element of
6838 // a vector. If Idx != 0, swizzle it into place.
6840 SmallVector<int, 4> Mask;
6841 Mask.push_back(Idx);
6842 for (unsigned i = 1; i != VecElts; ++i)
6844 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6847 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6851 // If we have a constant or non-constant insertion into the low element of
6852 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6853 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6854 // depending on what the source datatype is.
6857 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6859 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6860 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6861 if (VT.is256BitVector() || VT.is512BitVector()) {
6862 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6863 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6864 Item, DAG.getIntPtrConstant(0));
6866 assert(VT.is128BitVector() && "Expected an SSE value type!");
6867 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6868 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6869 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6872 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6873 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6874 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6875 if (VT.is256BitVector()) {
6876 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6877 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6879 assert(VT.is128BitVector() && "Expected an SSE value type!");
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6886 // Is it a vector logical left shift?
6887 if (NumElems == 2 && Idx == 1 &&
6888 X86::isZeroNode(Op.getOperand(0)) &&
6889 !X86::isZeroNode(Op.getOperand(1))) {
6890 unsigned NumBits = VT.getSizeInBits();
6891 return getVShift(true, VT,
6892 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6893 VT, Op.getOperand(1)),
6894 NumBits/2, DAG, *this, dl);
6897 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6900 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6901 // is a non-constant being inserted into an element other than the low one,
6902 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6903 // movd/movss) to move this into the low element, then shuffle it into
6905 if (EVTBits == 32) {
6906 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6908 // If using the new shuffle lowering, just directly insert this.
6909 if (ExperimentalVectorShuffleLowering)
6910 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6912 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6913 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6914 SmallVector<int, 8> MaskVec;
6915 for (unsigned i = 0; i != NumElems; ++i)
6916 MaskVec.push_back(i == Idx ? 0 : 1);
6917 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6921 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6922 if (Values.size() == 1) {
6923 if (EVTBits == 32) {
6924 // Instead of a shuffle like this:
6925 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6926 // Check if it's possible to issue this instead.
6927 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6928 unsigned Idx = countTrailingZeros(NonZeros);
6929 SDValue Item = Op.getOperand(Idx);
6930 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6931 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6936 // A vector full of immediates; various special cases are already
6937 // handled, so this is best done with a single constant-pool load.
6941 // For AVX-length vectors, build the individual 128-bit pieces and use
6942 // shuffles to put them in place.
6943 if (VT.is256BitVector() || VT.is512BitVector()) {
6944 SmallVector<SDValue, 64> V;
6945 for (unsigned i = 0; i != NumElems; ++i)
6946 V.push_back(Op.getOperand(i));
6948 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6950 // Build both the lower and upper subvector.
6951 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6952 makeArrayRef(&V[0], NumElems/2));
6953 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6954 makeArrayRef(&V[NumElems / 2], NumElems/2));
6956 // Recreate the wider vector with the lower and upper part.
6957 if (VT.is256BitVector())
6958 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6959 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6962 // Let legalizer expand 2-wide build_vectors.
6963 if (EVTBits == 64) {
6964 if (NumNonZero == 1) {
6965 // One half is zero or undef.
6966 unsigned Idx = countTrailingZeros(NonZeros);
6967 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6968 Op.getOperand(Idx));
6969 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6974 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6975 if (EVTBits == 8 && NumElems == 16) {
6976 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6978 if (V.getNode()) return V;
6981 if (EVTBits == 16 && NumElems == 8) {
6982 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6988 if (EVTBits == 32 && NumElems == 4) {
6989 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6990 NumZero, DAG, Subtarget, *this);
6995 // If element VT is == 32 bits, turn it into a number of shuffles.
6996 SmallVector<SDValue, 8> V(NumElems);
6997 if (NumElems == 4 && NumZero > 0) {
6998 for (unsigned i = 0; i < 4; ++i) {
6999 bool isZero = !(NonZeros & (1 << i));
7001 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7003 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7006 for (unsigned i = 0; i < 2; ++i) {
7007 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7010 V[i] = V[i*2]; // Must be a zero vector.
7013 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7016 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7019 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 bool Reverse1 = (NonZeros & 0x3) == 2;
7025 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7029 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7030 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7032 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7035 if (Values.size() > 1 && VT.is128BitVector()) {
7036 // Check for a build vector of consecutive loads.
7037 for (unsigned i = 0; i < NumElems; ++i)
7038 V[i] = Op.getOperand(i);
7040 // Check for elements which are consecutive loads.
7041 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7045 // Check for a build vector from mostly shuffle plus few inserting.
7046 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7050 // For SSE 4.1, use insertps to put the high elements into the low element.
7051 if (getSubtarget()->hasSSE41()) {
7053 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7054 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7056 Result = DAG.getUNDEF(VT);
7058 for (unsigned i = 1; i < NumElems; ++i) {
7059 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7060 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7061 Op.getOperand(i), DAG.getIntPtrConstant(i));
7066 // Otherwise, expand into a number of unpckl*, start by extending each of
7067 // our (non-undef) elements to the full vector width with the element in the
7068 // bottom slot of the vector (which generates no code for SSE).
7069 for (unsigned i = 0; i < NumElems; ++i) {
7070 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7071 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7073 V[i] = DAG.getUNDEF(VT);
7076 // Next, we iteratively mix elements, e.g. for v4f32:
7077 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7078 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7079 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7080 unsigned EltStride = NumElems >> 1;
7081 while (EltStride != 0) {
7082 for (unsigned i = 0; i < EltStride; ++i) {
7083 // If V[i+EltStride] is undef and this is the first round of mixing,
7084 // then it is safe to just drop this shuffle: V[i] is already in the
7085 // right place, the one element (since it's the first round) being
7086 // inserted as undef can be dropped. This isn't safe for successive
7087 // rounds because they will permute elements within both vectors.
7088 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7089 EltStride == NumElems/2)
7092 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7101 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7102 // to create 256-bit vectors from two other 128-bit ones.
7103 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7105 MVT ResVT = Op.getSimpleValueType();
7107 assert((ResVT.is256BitVector() ||
7108 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7110 SDValue V1 = Op.getOperand(0);
7111 SDValue V2 = Op.getOperand(1);
7112 unsigned NumElems = ResVT.getVectorNumElements();
7113 if(ResVT.is256BitVector())
7114 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7116 if (Op.getNumOperands() == 4) {
7117 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7118 ResVT.getVectorNumElements()/2);
7119 SDValue V3 = Op.getOperand(2);
7120 SDValue V4 = Op.getOperand(3);
7121 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7122 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7124 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7127 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7128 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7129 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7130 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7131 Op.getNumOperands() == 4)));
7133 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7134 // from two other 128-bit ones.
7136 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7137 return LowerAVXCONCAT_VECTORS(Op, DAG);
7141 //===----------------------------------------------------------------------===//
7142 // Vector shuffle lowering
7144 // This is an experimental code path for lowering vector shuffles on x86. It is
7145 // designed to handle arbitrary vector shuffles and blends, gracefully
7146 // degrading performance as necessary. It works hard to recognize idiomatic
7147 // shuffles and lower them to optimal instruction patterns without leaving
7148 // a framework that allows reasonably efficient handling of all vector shuffle
7150 //===----------------------------------------------------------------------===//
7152 /// \brief Tiny helper function to identify a no-op mask.
7154 /// This is a somewhat boring predicate function. It checks whether the mask
7155 /// array input, which is assumed to be a single-input shuffle mask of the kind
7156 /// used by the X86 shuffle instructions (not a fully general
7157 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7158 /// in-place shuffle are 'no-op's.
7159 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7160 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7161 if (Mask[i] != -1 && Mask[i] != i)
7166 /// \brief Helper function to classify a mask as a single-input mask.
7168 /// This isn't a generic single-input test because in the vector shuffle
7169 /// lowering we canonicalize single inputs to be the first input operand. This
7170 /// means we can more quickly test for a single input by only checking whether
7171 /// an input from the second operand exists. We also assume that the size of
7172 /// mask corresponds to the size of the input vectors which isn't true in the
7173 /// fully general case.
7174 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7176 if (M >= (int)Mask.size())
7181 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7182 // 2013 will allow us to use it as a non-type template parameter.
7185 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7187 /// See its documentation for details.
7188 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7189 if (Mask.size() != Args.size())
7191 for (int i = 0, e = Mask.size(); i < e; ++i) {
7192 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7193 if (Mask[i] != -1 && Mask[i] != *Args[i])
7201 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7204 /// This is a fast way to test a shuffle mask against a fixed pattern:
7206 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7208 /// It returns true if the mask is exactly as wide as the argument list, and
7209 /// each element of the mask is either -1 (signifying undef) or the value given
7210 /// in the argument.
7211 static const VariadicFunction1<
7212 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7214 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7216 /// This helper function produces an 8-bit shuffle immediate corresponding to
7217 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7218 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7221 /// NB: We rely heavily on "undef" masks preserving the input lane.
7222 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7223 SelectionDAG &DAG) {
7224 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7225 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7226 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7227 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7228 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7231 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7232 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7233 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7234 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7235 return DAG.getConstant(Imm, MVT::i8);
7238 /// \brief Try to emit a blend instruction for a shuffle.
7240 /// This doesn't do any checks for the availability of instructions for blending
7241 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7242 /// be matched in the backend with the type given. What it does check for is
7243 /// that the shuffle mask is in fact a blend.
7244 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7245 SDValue V2, ArrayRef<int> Mask,
7246 SelectionDAG &DAG) {
7248 unsigned BlendMask = 0;
7249 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7250 if (Mask[i] >= Size) {
7251 if (Mask[i] != i + Size)
7252 return SDValue(); // Shuffled V2 input!
7253 BlendMask |= 1u << i;
7256 if (Mask[i] >= 0 && Mask[i] != i)
7257 return SDValue(); // Shuffled V1 input!
7259 switch (VT.SimpleTy) {
7264 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7265 DAG.getConstant(BlendMask, MVT::i8));
7270 // For integer shuffles we need to expand the mask and cast the inputs to
7271 // v8i16s prior to blending.
7272 int Scale = 8 / VT.getVectorNumElements();
7274 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7275 if (Mask[i] >= Size)
7276 for (int j = 0; j < Scale; ++j)
7277 BlendMask |= 1u << (i * Scale + j);
7279 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7280 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7281 return DAG.getNode(ISD::BITCAST, DL, VT,
7282 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7283 DAG.getConstant(BlendMask, MVT::i8)));
7287 llvm_unreachable("Not a supported integer vector type!");
7291 /// \brief Try to lower a vector shuffle as a byte rotation.
7293 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7294 /// byte-rotation of a the concatentation of two vectors. This routine will
7295 /// try to generically lower a vector shuffle through such an instruction. It
7296 /// does not check for the availability of PALIGNR-based lowerings, only the
7297 /// applicability of this strategy to the given mask. This matches shuffle
7298 /// vectors that look like:
7300 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7302 /// Essentially it concatenates V1 and V2, shifts right by some number of
7303 /// elements, and takes the low elements as the result. Note that while this is
7304 /// specified as a *right shift* because x86 is little-endian, it is a *left
7305 /// rotate* of the vector lanes.
7307 /// Note that this only handles 128-bit vector widths currently.
7308 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7311 SelectionDAG &DAG) {
7312 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7314 // We need to detect various ways of spelling a rotation:
7315 // [11, 12, 13, 14, 15, 0, 1, 2]
7316 // [-1, 12, 13, 14, -1, -1, 1, -1]
7317 // [-1, -1, -1, -1, -1, -1, 1, 2]
7318 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7319 // [-1, 4, 5, 6, -1, -1, 9, -1]
7320 // [-1, 4, 5, 6, -1, -1, -1, -1]
7323 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7326 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7328 // Based on the mod-Size value of this mask element determine where
7329 // a rotated vector would have started.
7330 int StartIdx = i - (Mask[i] % Size);
7332 // The identity rotation isn't interesting, stop.
7335 // If we found the tail of a vector the rotation must be the missing
7336 // front. If we found the head of a vector, it must be how much of the head.
7337 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7340 Rotation = CandidateRotation;
7341 else if (Rotation != CandidateRotation)
7342 // The rotations don't match, so we can't match this mask.
7345 // Compute which value this mask is pointing at.
7346 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7348 // Compute which of the two target values this index should be assigned to.
7349 // This reflects whether the high elements are remaining or the low elements
7351 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7353 // Either set up this value if we've not encountered it before, or check
7354 // that it remains consistent.
7357 else if (TargetV != MaskV)
7358 // This may be a rotation, but it pulls from the inputs in some
7359 // unsupported interleaving.
7363 // Check that we successfully analyzed the mask, and normalize the results.
7364 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7365 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7371 // Cast the inputs to v16i8 to match PALIGNR.
7372 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7373 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7375 assert(VT.getSizeInBits() == 128 &&
7376 "Rotate-based lowering only supports 128-bit lowering!");
7377 assert(Mask.size() <= 16 &&
7378 "Can shuffle at most 16 bytes in a 128-bit vector!");
7379 // The actual rotate instruction rotates bytes, so we need to scale the
7380 // rotation based on how many bytes are in the vector.
7381 int Scale = 16 / Mask.size();
7383 return DAG.getNode(ISD::BITCAST, DL, VT,
7384 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7385 DAG.getConstant(Rotation * Scale, MVT::i8)));
7388 /// \brief Compute whether each element of a shuffle is zeroable.
7390 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7391 /// Either it is an undef element in the shuffle mask, the element of the input
7392 /// referenced is undef, or the element of the input referenced is known to be
7393 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7394 /// as many lanes with this technique as possible to simplify the remaining
7396 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7397 SDValue V1, SDValue V2) {
7398 SmallBitVector Zeroable(Mask.size(), false);
7400 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7401 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7403 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7405 // Handle the easy cases.
7406 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7411 // If this is an index into a build_vector node, dig out the input value and
7413 SDValue V = M < Size ? V1 : V2;
7414 if (V.getOpcode() != ISD::BUILD_VECTOR)
7417 SDValue Input = V.getOperand(M % Size);
7418 // The UNDEF opcode check really should be dead code here, but not quite
7419 // worth asserting on (it isn't invalid, just unexpected).
7420 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7427 /// \brief Lower a vector shuffle as a zero or any extension.
7429 /// Given a specific number of elements, element bit width, and extension
7430 /// stride, produce either a zero or any extension based on the available
7431 /// features of the subtarget.
7432 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7433 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7434 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7435 assert(Scale > 1 && "Need a scale to extend.");
7436 int EltBits = VT.getSizeInBits() / NumElements;
7437 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7438 "Only 8, 16, and 32 bit elements can be extended.");
7439 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7441 // Found a valid zext mask! Try various lowering strategies based on the
7442 // input type and available ISA extensions.
7443 if (Subtarget->hasSSE41()) {
7444 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7445 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7446 NumElements / Scale);
7447 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7448 return DAG.getNode(ISD::BITCAST, DL, VT,
7449 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7452 // For any extends we can cheat for larger element sizes and use shuffle
7453 // instructions that can fold with a load and/or copy.
7454 if (AnyExt && EltBits == 32) {
7455 int PSHUFDMask[4] = {0, -1, 1, -1};
7457 ISD::BITCAST, DL, VT,
7458 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7459 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7460 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7462 if (AnyExt && EltBits == 16 && Scale > 2) {
7463 int PSHUFDMask[4] = {0, -1, 0, -1};
7464 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7465 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7466 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7467 int PSHUFHWMask[4] = {1, -1, -1, -1};
7469 ISD::BITCAST, DL, VT,
7470 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7471 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7472 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7475 // If this would require more than 2 unpack instructions to expand, use
7476 // pshufb when available. We can only use more than 2 unpack instructions
7477 // when zero extending i8 elements which also makes it easier to use pshufb.
7478 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7479 assert(NumElements == 16 && "Unexpected byte vector width!");
7480 SDValue PSHUFBMask[16];
7481 for (int i = 0; i < 16; ++i)
7483 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7484 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7485 return DAG.getNode(ISD::BITCAST, DL, VT,
7486 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7487 DAG.getNode(ISD::BUILD_VECTOR, DL,
7488 MVT::v16i8, PSHUFBMask)));
7491 // Otherwise emit a sequence of unpacks.
7493 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7494 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7495 : getZeroVector(InputVT, Subtarget, DAG, DL);
7496 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7497 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7501 } while (Scale > 1);
7502 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7505 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7507 /// This routine will try to do everything in its power to cleverly lower
7508 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7509 /// check for the profitability of this lowering, it tries to aggressively
7510 /// match this pattern. It will use all of the micro-architectural details it
7511 /// can to emit an efficient lowering. It handles both blends with all-zero
7512 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7513 /// masking out later).
7515 /// The reason we have dedicated lowering for zext-style shuffles is that they
7516 /// are both incredibly common and often quite performance sensitive.
7517 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7518 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7519 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7520 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7522 int Bits = VT.getSizeInBits();
7523 int NumElements = Mask.size();
7525 // Define a helper function to check a particular ext-scale and lower to it if
7527 auto Lower = [&](int Scale) -> SDValue {
7530 for (int i = 0; i < NumElements; ++i) {
7532 continue; // Valid anywhere but doesn't tell us anything.
7533 if (i % Scale != 0) {
7534 // Each of the extend elements needs to be zeroable.
7538 // We no lorger are in the anyext case.
7543 // Each of the base elements needs to be consecutive indices into the
7544 // same input vector.
7545 SDValue V = Mask[i] < NumElements ? V1 : V2;
7548 else if (InputV != V)
7549 return SDValue(); // Flip-flopping inputs.
7551 if (Mask[i] % NumElements != i / Scale)
7552 return SDValue(); // Non-consecutive strided elemenst.
7555 // If we fail to find an input, we have a zero-shuffle which should always
7556 // have already been handled.
7557 // FIXME: Maybe handle this here in case during blending we end up with one?
7561 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7562 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7565 // The widest scale possible for extending is to a 64-bit integer.
7566 assert(Bits % 64 == 0 &&
7567 "The number of bits in a vector must be divisible by 64 on x86!");
7568 int NumExtElements = Bits / 64;
7570 // Each iteration, try extending the elements half as much, but into twice as
7572 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7573 assert(NumElements % NumExtElements == 0 &&
7574 "The input vector size must be divisble by the extended size.");
7575 if (SDValue V = Lower(NumElements / NumExtElements))
7579 // No viable ext lowering found.
7583 /// \brief Try to lower insertion of a single element into a zero vector.
7585 /// This is a common pattern that we have especially efficient patterns to lower
7586 /// across all subtarget feature sets.
7587 static SDValue lowerVectorShuffleAsElementInsertion(
7588 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7589 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7590 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7592 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7593 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7595 if (Mask.size() == 2) {
7596 if (!Zeroable[V2Index ^ 1]) {
7597 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7598 // with 2 to flip from {2,3} to {0,1} and vice versa.
7599 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7600 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7601 if (Zeroable[V2Index])
7602 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7608 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7609 if (i != V2Index && !Zeroable[i])
7610 return SDValue(); // Not inserting into a zero vector.
7613 // Step over any bitcasts on either input so we can scan the actual
7614 // BUILD_VECTOR nodes.
7615 while (V1.getOpcode() == ISD::BITCAST)
7616 V1 = V1.getOperand(0);
7617 while (V2.getOpcode() == ISD::BITCAST)
7618 V2 = V2.getOperand(0);
7620 // Check for a single input from a SCALAR_TO_VECTOR node.
7621 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7622 // all the smarts here sunk into that routine. However, the current
7623 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7624 // vector shuffle lowering is dead.
7625 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7626 Mask[V2Index] == (int)Mask.size()) ||
7627 V2.getOpcode() == ISD::BUILD_VECTOR))
7630 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7632 // First, we need to zext the scalar if it is smaller than an i32.
7634 MVT EltVT = VT.getVectorElementType();
7635 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7636 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7637 // Zero-extend directly to i32.
7639 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7642 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7643 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7645 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7648 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7649 // the desired position. Otherwise it is more efficient to do a vector
7650 // shift left. We know that we can do a vector shift left because all
7651 // the inputs are zero.
7652 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7653 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7654 V2Shuffle[V2Index] = 0;
7655 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7657 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7659 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7661 V2Index * EltVT.getSizeInBits(),
7662 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7663 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7669 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7671 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7672 /// support for floating point shuffles but not integer shuffles. These
7673 /// instructions will incur a domain crossing penalty on some chips though so
7674 /// it is better to avoid lowering through this for integer vectors where
7676 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7677 const X86Subtarget *Subtarget,
7678 SelectionDAG &DAG) {
7680 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7681 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7682 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7683 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7684 ArrayRef<int> Mask = SVOp->getMask();
7685 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7687 if (isSingleInputShuffleMask(Mask)) {
7688 // Straight shuffle of a single input vector. Simulate this by using the
7689 // single input as both of the "inputs" to this instruction..
7690 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7692 if (Subtarget->hasAVX()) {
7693 // If we have AVX, we can use VPERMILPS which will allow folding a load
7694 // into the shuffle.
7695 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7696 DAG.getConstant(SHUFPDMask, MVT::i8));
7699 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7700 DAG.getConstant(SHUFPDMask, MVT::i8));
7702 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7703 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7705 // Use dedicated unpack instructions for masks that match their pattern.
7706 if (isShuffleEquivalent(Mask, 0, 2))
7707 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7708 if (isShuffleEquivalent(Mask, 1, 3))
7709 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7711 // If we have a single input, insert that into V1 if we can do so cheaply.
7712 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7713 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7714 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7717 if (Subtarget->hasSSE41())
7719 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7722 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7723 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7724 DAG.getConstant(SHUFPDMask, MVT::i8));
7727 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7729 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7730 /// the integer unit to minimize domain crossing penalties. However, for blends
7731 /// it falls back to the floating point shuffle operation with appropriate bit
7733 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7734 const X86Subtarget *Subtarget,
7735 SelectionDAG &DAG) {
7737 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7738 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7739 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7741 ArrayRef<int> Mask = SVOp->getMask();
7742 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7744 if (isSingleInputShuffleMask(Mask)) {
7745 // Straight shuffle of a single input vector. For everything from SSE2
7746 // onward this has a single fast instruction with no scary immediates.
7747 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7748 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7749 int WidenedMask[4] = {
7750 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7751 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7753 ISD::BITCAST, DL, MVT::v2i64,
7754 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7755 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7758 // Use dedicated unpack instructions for masks that match their pattern.
7759 if (isShuffleEquivalent(Mask, 0, 2))
7760 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7761 if (isShuffleEquivalent(Mask, 1, 3))
7762 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7764 // If we have a single input from V2 insert that into V1 if we can do so
7766 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7767 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7768 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7771 if (Subtarget->hasSSE41())
7773 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7776 // Try to use rotation instructions if available.
7777 if (Subtarget->hasSSSE3())
7778 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7779 DL, MVT::v2i64, V1, V2, Mask, DAG))
7782 // We implement this with SHUFPD which is pretty lame because it will likely
7783 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7784 // However, all the alternatives are still more cycles and newer chips don't
7785 // have this problem. It would be really nice if x86 had better shuffles here.
7786 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7787 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7788 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7789 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7792 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7794 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7795 /// It makes no assumptions about whether this is the *best* lowering, it simply
7797 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7798 ArrayRef<int> Mask, SDValue V1,
7799 SDValue V2, SelectionDAG &DAG) {
7800 SDValue LowV = V1, HighV = V2;
7801 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7804 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7806 if (NumV2Elements == 1) {
7808 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7811 // Compute the index adjacent to V2Index and in the same half by toggling
7813 int V2AdjIndex = V2Index ^ 1;
7815 if (Mask[V2AdjIndex] == -1) {
7816 // Handles all the cases where we have a single V2 element and an undef.
7817 // This will only ever happen in the high lanes because we commute the
7818 // vector otherwise.
7820 std::swap(LowV, HighV);
7821 NewMask[V2Index] -= 4;
7823 // Handle the case where the V2 element ends up adjacent to a V1 element.
7824 // To make this work, blend them together as the first step.
7825 int V1Index = V2AdjIndex;
7826 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7827 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7828 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7830 // Now proceed to reconstruct the final blend as we have the necessary
7831 // high or low half formed.
7838 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7839 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7841 } else if (NumV2Elements == 2) {
7842 if (Mask[0] < 4 && Mask[1] < 4) {
7843 // Handle the easy case where we have V1 in the low lanes and V2 in the
7844 // high lanes. We never see this reversed because we sort the shuffle.
7848 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7849 // trying to place elements directly, just blend them and set up the final
7850 // shuffle to place them.
7852 // The first two blend mask elements are for V1, the second two are for
7854 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7855 Mask[2] < 4 ? Mask[2] : Mask[3],
7856 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7857 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7858 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7859 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7861 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7864 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7865 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7866 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7867 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7870 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7871 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7874 /// \brief Lower 4-lane 32-bit floating point shuffles.
7876 /// Uses instructions exclusively from the floating point unit to minimize
7877 /// domain crossing penalties, as these are sufficient to implement all v4f32
7879 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7880 const X86Subtarget *Subtarget,
7881 SelectionDAG &DAG) {
7883 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7884 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7885 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7887 ArrayRef<int> Mask = SVOp->getMask();
7888 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7891 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7893 if (NumV2Elements == 0) {
7894 if (Subtarget->hasAVX()) {
7895 // If we have AVX, we can use VPERMILPS which will allow folding a load
7896 // into the shuffle.
7897 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7898 getV4X86ShuffleImm8ForMask(Mask, DAG));
7901 // Otherwise, use a straight shuffle of a single input vector. We pass the
7902 // input vector to both operands to simulate this with a SHUFPS.
7903 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7904 getV4X86ShuffleImm8ForMask(Mask, DAG));
7907 // Use dedicated unpack instructions for masks that match their pattern.
7908 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7909 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7910 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7911 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7913 // There are special ways we can lower some single-element blends. However, we
7914 // have custom ways we can lower more complex single-element blends below that
7915 // we defer to if both this and BLENDPS fail to match, so restrict this to
7916 // when the V2 input is targeting element 0 of the mask -- that is the fast
7918 if (NumV2Elements == 1 && Mask[0] >= 4)
7919 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7920 Mask, Subtarget, DAG))
7923 if (Subtarget->hasSSE41())
7925 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7928 // Check for whether we can use INSERTPS to perform the blend. We only use
7929 // INSERTPS when the V1 elements are already in the correct locations
7930 // because otherwise we can just always use two SHUFPS instructions which
7931 // are much smaller to encode than a SHUFPS and an INSERTPS.
7932 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7934 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7937 // When using INSERTPS we can zero any lane of the destination. Collect
7938 // the zero inputs into a mask and drop them from the lanes of V1 which
7939 // actually need to be present as inputs to the INSERTPS.
7940 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7942 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7943 bool InsertNeedsShuffle = false;
7945 for (int i = 0; i < 4; ++i)
7949 } else if (Mask[i] != i) {
7950 InsertNeedsShuffle = true;
7955 // We don't want to use INSERTPS or other insertion techniques if it will
7956 // require shuffling anyways.
7957 if (!InsertNeedsShuffle) {
7958 // If all of V1 is zeroable, replace it with undef.
7959 if ((ZMask | 1 << V2Index) == 0xF)
7960 V1 = DAG.getUNDEF(MVT::v4f32);
7962 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7963 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7965 // Insert the V2 element into the desired position.
7966 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7967 DAG.getConstant(InsertPSMask, MVT::i8));
7971 // Otherwise fall back to a SHUFPS lowering strategy.
7972 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7975 /// \brief Lower 4-lane i32 vector shuffles.
7977 /// We try to handle these with integer-domain shuffles where we can, but for
7978 /// blends we use the floating point domain blend instructions.
7979 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7980 const X86Subtarget *Subtarget,
7981 SelectionDAG &DAG) {
7983 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7984 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7985 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7986 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7987 ArrayRef<int> Mask = SVOp->getMask();
7988 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7991 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7993 if (NumV2Elements == 0) {
7994 // Straight shuffle of a single input vector. For everything from SSE2
7995 // onward this has a single fast instruction with no scary immediates.
7996 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7997 // but we aren't actually going to use the UNPCK instruction because doing
7998 // so prevents folding a load into this instruction or making a copy.
7999 const int UnpackLoMask[] = {0, 0, 1, 1};
8000 const int UnpackHiMask[] = {2, 2, 3, 3};
8001 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8002 Mask = UnpackLoMask;
8003 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8004 Mask = UnpackHiMask;
8006 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8007 getV4X86ShuffleImm8ForMask(Mask, DAG));
8010 // Whenever we can lower this as a zext, that instruction is strictly faster
8011 // than any alternative.
8012 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8013 Mask, Subtarget, DAG))
8016 // Use dedicated unpack instructions for masks that match their pattern.
8017 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8018 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8019 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8020 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8022 // There are special ways we can lower some single-element blends.
8023 if (NumV2Elements == 1)
8024 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8025 Mask, Subtarget, DAG))
8028 if (Subtarget->hasSSE41())
8030 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
8033 // Try to use rotation instructions if available.
8034 if (Subtarget->hasSSSE3())
8035 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8036 DL, MVT::v4i32, V1, V2, Mask, DAG))
8039 // We implement this with SHUFPS because it can blend from two vectors.
8040 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8041 // up the inputs, bypassing domain shift penalties that we would encur if we
8042 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8044 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8045 DAG.getVectorShuffle(
8047 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8048 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8051 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8052 /// shuffle lowering, and the most complex part.
8054 /// The lowering strategy is to try to form pairs of input lanes which are
8055 /// targeted at the same half of the final vector, and then use a dword shuffle
8056 /// to place them onto the right half, and finally unpack the paired lanes into
8057 /// their final position.
8059 /// The exact breakdown of how to form these dword pairs and align them on the
8060 /// correct sides is really tricky. See the comments within the function for
8061 /// more of the details.
8062 static SDValue lowerV8I16SingleInputVectorShuffle(
8063 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8064 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8065 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8066 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8067 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8069 SmallVector<int, 4> LoInputs;
8070 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8071 [](int M) { return M >= 0; });
8072 std::sort(LoInputs.begin(), LoInputs.end());
8073 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8074 SmallVector<int, 4> HiInputs;
8075 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8076 [](int M) { return M >= 0; });
8077 std::sort(HiInputs.begin(), HiInputs.end());
8078 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8080 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8081 int NumHToL = LoInputs.size() - NumLToL;
8083 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8084 int NumHToH = HiInputs.size() - NumLToH;
8085 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8086 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8087 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8088 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8090 // Use dedicated unpack instructions for masks that match their pattern.
8091 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8092 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8093 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8094 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8096 // Try to use rotation instructions if available.
8097 if (Subtarget->hasSSSE3())
8098 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8099 DL, MVT::v8i16, V, V, Mask, DAG))
8102 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8103 // such inputs we can swap two of the dwords across the half mark and end up
8104 // with <=2 inputs to each half in each half. Once there, we can fall through
8105 // to the generic code below. For example:
8107 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8108 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8110 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8111 // and an existing 2-into-2 on the other half. In this case we may have to
8112 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8113 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8114 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8115 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8116 // half than the one we target for fixing) will be fixed when we re-enter this
8117 // path. We will also combine away any sequence of PSHUFD instructions that
8118 // result into a single instruction. Here is an example of the tricky case:
8120 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8121 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8123 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8125 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8126 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8128 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8129 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8131 // The result is fine to be handled by the generic logic.
8132 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8133 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8134 int AOffset, int BOffset) {
8135 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8136 "Must call this with A having 3 or 1 inputs from the A half.");
8137 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8138 "Must call this with B having 1 or 3 inputs from the B half.");
8139 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8140 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8142 // Compute the index of dword with only one word among the three inputs in
8143 // a half by taking the sum of the half with three inputs and subtracting
8144 // the sum of the actual three inputs. The difference is the remaining
8147 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8148 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8149 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8150 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8151 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8152 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8153 int TripleNonInputIdx =
8154 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8155 TripleDWord = TripleNonInputIdx / 2;
8157 // We use xor with one to compute the adjacent DWord to whichever one the
8159 OneInputDWord = (OneInput / 2) ^ 1;
8161 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8162 // and BToA inputs. If there is also such a problem with the BToB and AToB
8163 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8164 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8165 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8166 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8167 // Compute how many inputs will be flipped by swapping these DWords. We
8169 // to balance this to ensure we don't form a 3-1 shuffle in the other
8171 int NumFlippedAToBInputs =
8172 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8173 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8174 int NumFlippedBToBInputs =
8175 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8176 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8177 if ((NumFlippedAToBInputs == 1 &&
8178 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8179 (NumFlippedBToBInputs == 1 &&
8180 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8181 // We choose whether to fix the A half or B half based on whether that
8182 // half has zero flipped inputs. At zero, we may not be able to fix it
8183 // with that half. We also bias towards fixing the B half because that
8184 // will more commonly be the high half, and we have to bias one way.
8185 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8186 ArrayRef<int> Inputs) {
8187 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8188 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8189 PinnedIdx ^ 1) != Inputs.end();
8190 // Determine whether the free index is in the flipped dword or the
8191 // unflipped dword based on where the pinned index is. We use this bit
8192 // in an xor to conditionally select the adjacent dword.
8193 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8194 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8195 FixFreeIdx) != Inputs.end();
8196 if (IsFixIdxInput == IsFixFreeIdxInput)
8198 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8199 FixFreeIdx) != Inputs.end();
8200 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8201 "We need to be changing the number of flipped inputs!");
8202 int PSHUFHalfMask[] = {0, 1, 2, 3};
8203 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8204 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8206 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8209 if (M != -1 && M == FixIdx)
8211 else if (M != -1 && M == FixFreeIdx)
8214 if (NumFlippedBToBInputs != 0) {
8216 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8217 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8219 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8221 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8222 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8227 int PSHUFDMask[] = {0, 1, 2, 3};
8228 PSHUFDMask[ADWord] = BDWord;
8229 PSHUFDMask[BDWord] = ADWord;
8230 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8231 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8232 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8233 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8235 // Adjust the mask to match the new locations of A and B.
8237 if (M != -1 && M/2 == ADWord)
8238 M = 2 * BDWord + M % 2;
8239 else if (M != -1 && M/2 == BDWord)
8240 M = 2 * ADWord + M % 2;
8242 // Recurse back into this routine to re-compute state now that this isn't
8243 // a 3 and 1 problem.
8244 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8247 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8248 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8249 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8250 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8252 // At this point there are at most two inputs to the low and high halves from
8253 // each half. That means the inputs can always be grouped into dwords and
8254 // those dwords can then be moved to the correct half with a dword shuffle.
8255 // We use at most one low and one high word shuffle to collect these paired
8256 // inputs into dwords, and finally a dword shuffle to place them.
8257 int PSHUFLMask[4] = {-1, -1, -1, -1};
8258 int PSHUFHMask[4] = {-1, -1, -1, -1};
8259 int PSHUFDMask[4] = {-1, -1, -1, -1};
8261 // First fix the masks for all the inputs that are staying in their
8262 // original halves. This will then dictate the targets of the cross-half
8264 auto fixInPlaceInputs =
8265 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8266 MutableArrayRef<int> SourceHalfMask,
8267 MutableArrayRef<int> HalfMask, int HalfOffset) {
8268 if (InPlaceInputs.empty())
8270 if (InPlaceInputs.size() == 1) {
8271 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8272 InPlaceInputs[0] - HalfOffset;
8273 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8276 if (IncomingInputs.empty()) {
8277 // Just fix all of the in place inputs.
8278 for (int Input : InPlaceInputs) {
8279 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8280 PSHUFDMask[Input / 2] = Input / 2;
8285 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8286 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8287 InPlaceInputs[0] - HalfOffset;
8288 // Put the second input next to the first so that they are packed into
8289 // a dword. We find the adjacent index by toggling the low bit.
8290 int AdjIndex = InPlaceInputs[0] ^ 1;
8291 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8292 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8293 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8295 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8296 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8298 // Now gather the cross-half inputs and place them into a free dword of
8299 // their target half.
8300 // FIXME: This operation could almost certainly be simplified dramatically to
8301 // look more like the 3-1 fixing operation.
8302 auto moveInputsToRightHalf = [&PSHUFDMask](
8303 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8304 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8305 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8307 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8308 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8310 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8312 int LowWord = Word & ~1;
8313 int HighWord = Word | 1;
8314 return isWordClobbered(SourceHalfMask, LowWord) ||
8315 isWordClobbered(SourceHalfMask, HighWord);
8318 if (IncomingInputs.empty())
8321 if (ExistingInputs.empty()) {
8322 // Map any dwords with inputs from them into the right half.
8323 for (int Input : IncomingInputs) {
8324 // If the source half mask maps over the inputs, turn those into
8325 // swaps and use the swapped lane.
8326 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8327 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8328 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8329 Input - SourceOffset;
8330 // We have to swap the uses in our half mask in one sweep.
8331 for (int &M : HalfMask)
8332 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8334 else if (M == Input)
8335 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8337 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8338 Input - SourceOffset &&
8339 "Previous placement doesn't match!");
8341 // Note that this correctly re-maps both when we do a swap and when
8342 // we observe the other side of the swap above. We rely on that to
8343 // avoid swapping the members of the input list directly.
8344 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8347 // Map the input's dword into the correct half.
8348 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8349 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8351 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8353 "Previous placement doesn't match!");
8356 // And just directly shift any other-half mask elements to be same-half
8357 // as we will have mirrored the dword containing the element into the
8358 // same position within that half.
8359 for (int &M : HalfMask)
8360 if (M >= SourceOffset && M < SourceOffset + 4) {
8361 M = M - SourceOffset + DestOffset;
8362 assert(M >= 0 && "This should never wrap below zero!");
8367 // Ensure we have the input in a viable dword of its current half. This
8368 // is particularly tricky because the original position may be clobbered
8369 // by inputs being moved and *staying* in that half.
8370 if (IncomingInputs.size() == 1) {
8371 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8372 int InputFixed = std::find(std::begin(SourceHalfMask),
8373 std::end(SourceHalfMask), -1) -
8374 std::begin(SourceHalfMask) + SourceOffset;
8375 SourceHalfMask[InputFixed - SourceOffset] =
8376 IncomingInputs[0] - SourceOffset;
8377 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8379 IncomingInputs[0] = InputFixed;
8381 } else if (IncomingInputs.size() == 2) {
8382 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8383 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8384 // We have two non-adjacent or clobbered inputs we need to extract from
8385 // the source half. To do this, we need to map them into some adjacent
8386 // dword slot in the source mask.
8387 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8388 IncomingInputs[1] - SourceOffset};
8390 // If there is a free slot in the source half mask adjacent to one of
8391 // the inputs, place the other input in it. We use (Index XOR 1) to
8392 // compute an adjacent index.
8393 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8394 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8395 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8396 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8397 InputsFixed[1] = InputsFixed[0] ^ 1;
8398 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8399 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8400 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8401 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8402 InputsFixed[0] = InputsFixed[1] ^ 1;
8403 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8404 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8405 // The two inputs are in the same DWord but it is clobbered and the
8406 // adjacent DWord isn't used at all. Move both inputs to the free
8408 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8409 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8410 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8411 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8413 // The only way we hit this point is if there is no clobbering
8414 // (because there are no off-half inputs to this half) and there is no
8415 // free slot adjacent to one of the inputs. In this case, we have to
8416 // swap an input with a non-input.
8417 for (int i = 0; i < 4; ++i)
8418 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8419 "We can't handle any clobbers here!");
8420 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8421 "Cannot have adjacent inputs here!");
8423 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8424 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8426 // We also have to update the final source mask in this case because
8427 // it may need to undo the above swap.
8428 for (int &M : FinalSourceHalfMask)
8429 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8430 M = InputsFixed[1] + SourceOffset;
8431 else if (M == InputsFixed[1] + SourceOffset)
8432 M = (InputsFixed[0] ^ 1) + SourceOffset;
8434 InputsFixed[1] = InputsFixed[0] ^ 1;
8437 // Point everything at the fixed inputs.
8438 for (int &M : HalfMask)
8439 if (M == IncomingInputs[0])
8440 M = InputsFixed[0] + SourceOffset;
8441 else if (M == IncomingInputs[1])
8442 M = InputsFixed[1] + SourceOffset;
8444 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8445 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8448 llvm_unreachable("Unhandled input size!");
8451 // Now hoist the DWord down to the right half.
8452 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8453 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8454 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8455 for (int &M : HalfMask)
8456 for (int Input : IncomingInputs)
8458 M = FreeDWord * 2 + Input % 2;
8460 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8461 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8462 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8463 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8465 // Now enact all the shuffles we've computed to move the inputs into their
8467 if (!isNoopShuffleMask(PSHUFLMask))
8468 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8469 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8470 if (!isNoopShuffleMask(PSHUFHMask))
8471 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8472 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8473 if (!isNoopShuffleMask(PSHUFDMask))
8474 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8475 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8476 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8477 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8479 // At this point, each half should contain all its inputs, and we can then
8480 // just shuffle them into their final position.
8481 assert(std::count_if(LoMask.begin(), LoMask.end(),
8482 [](int M) { return M >= 4; }) == 0 &&
8483 "Failed to lift all the high half inputs to the low mask!");
8484 assert(std::count_if(HiMask.begin(), HiMask.end(),
8485 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8486 "Failed to lift all the low half inputs to the high mask!");
8488 // Do a half shuffle for the low mask.
8489 if (!isNoopShuffleMask(LoMask))
8490 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8491 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8493 // Do a half shuffle with the high mask after shifting its values down.
8494 for (int &M : HiMask)
8497 if (!isNoopShuffleMask(HiMask))
8498 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8499 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8504 /// \brief Detect whether the mask pattern should be lowered through
8507 /// This essentially tests whether viewing the mask as an interleaving of two
8508 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8509 /// lowering it through interleaving is a significantly better strategy.
8510 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8511 int NumEvenInputs[2] = {0, 0};
8512 int NumOddInputs[2] = {0, 0};
8513 int NumLoInputs[2] = {0, 0};
8514 int NumHiInputs[2] = {0, 0};
8515 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8519 int InputIdx = Mask[i] >= Size;
8522 ++NumLoInputs[InputIdx];
8524 ++NumHiInputs[InputIdx];
8527 ++NumEvenInputs[InputIdx];
8529 ++NumOddInputs[InputIdx];
8532 // The minimum number of cross-input results for both the interleaved and
8533 // split cases. If interleaving results in fewer cross-input results, return
8535 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8536 NumEvenInputs[0] + NumOddInputs[1]);
8537 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8538 NumLoInputs[0] + NumHiInputs[1]);
8539 return InterleavedCrosses < SplitCrosses;
8542 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8544 /// This strategy only works when the inputs from each vector fit into a single
8545 /// half of that vector, and generally there are not so many inputs as to leave
8546 /// the in-place shuffles required highly constrained (and thus expensive). It
8547 /// shifts all the inputs into a single side of both input vectors and then
8548 /// uses an unpack to interleave these inputs in a single vector. At that
8549 /// point, we will fall back on the generic single input shuffle lowering.
8550 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8552 MutableArrayRef<int> Mask,
8553 const X86Subtarget *Subtarget,
8554 SelectionDAG &DAG) {
8555 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8556 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8557 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8558 for (int i = 0; i < 8; ++i)
8559 if (Mask[i] >= 0 && Mask[i] < 4)
8560 LoV1Inputs.push_back(i);
8561 else if (Mask[i] >= 4 && Mask[i] < 8)
8562 HiV1Inputs.push_back(i);
8563 else if (Mask[i] >= 8 && Mask[i] < 12)
8564 LoV2Inputs.push_back(i);
8565 else if (Mask[i] >= 12)
8566 HiV2Inputs.push_back(i);
8568 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8569 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8572 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8573 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8574 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8576 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8577 HiV1Inputs.size() + HiV2Inputs.size();
8579 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8580 ArrayRef<int> HiInputs, bool MoveToLo,
8582 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8583 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8584 if (BadInputs.empty())
8587 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8588 int MoveOffset = MoveToLo ? 0 : 4;
8590 if (GoodInputs.empty()) {
8591 for (int BadInput : BadInputs) {
8592 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8593 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8596 if (GoodInputs.size() == 2) {
8597 // If the low inputs are spread across two dwords, pack them into
8599 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8600 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8601 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8602 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8604 // Otherwise pin the good inputs.
8605 for (int GoodInput : GoodInputs)
8606 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8609 if (BadInputs.size() == 2) {
8610 // If we have two bad inputs then there may be either one or two good
8611 // inputs fixed in place. Find a fixed input, and then find the *other*
8612 // two adjacent indices by using modular arithmetic.
8614 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8615 [](int M) { return M >= 0; }) -
8616 std::begin(MoveMask);
8618 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8619 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8620 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8621 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8622 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8623 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8624 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8626 assert(BadInputs.size() == 1 && "All sizes handled");
8627 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8628 std::end(MoveMask), -1) -
8629 std::begin(MoveMask);
8630 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8631 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8635 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8638 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8640 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8643 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8644 // cross-half traffic in the final shuffle.
8646 // Munge the mask to be a single-input mask after the unpack merges the
8650 M = 2 * (M % 4) + (M / 8);
8652 return DAG.getVectorShuffle(
8653 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8654 DL, MVT::v8i16, V1, V2),
8655 DAG.getUNDEF(MVT::v8i16), Mask);
8658 /// \brief Generic lowering of 8-lane i16 shuffles.
8660 /// This handles both single-input shuffles and combined shuffle/blends with
8661 /// two inputs. The single input shuffles are immediately delegated to
8662 /// a dedicated lowering routine.
8664 /// The blends are lowered in one of three fundamental ways. If there are few
8665 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8666 /// of the input is significantly cheaper when lowered as an interleaving of
8667 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8668 /// halves of the inputs separately (making them have relatively few inputs)
8669 /// and then concatenate them.
8670 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8671 const X86Subtarget *Subtarget,
8672 SelectionDAG &DAG) {
8674 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8675 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8676 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8677 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8678 ArrayRef<int> OrigMask = SVOp->getMask();
8679 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8680 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8681 MutableArrayRef<int> Mask(MaskStorage);
8683 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8685 // Whenever we can lower this as a zext, that instruction is strictly faster
8686 // than any alternative.
8687 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8688 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8691 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8692 auto isV2 = [](int M) { return M >= 8; };
8694 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8695 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8697 if (NumV2Inputs == 0)
8698 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8700 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8701 "to be V1-input shuffles.");
8703 // There are special ways we can lower some single-element blends.
8704 if (NumV2Inputs == 1)
8705 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8706 Mask, Subtarget, DAG))
8709 if (Subtarget->hasSSE41())
8711 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8714 // Try to use rotation instructions if available.
8715 if (Subtarget->hasSSSE3())
8716 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8719 if (NumV1Inputs + NumV2Inputs <= 4)
8720 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8722 // Check whether an interleaving lowering is likely to be more efficient.
8723 // This isn't perfect but it is a strong heuristic that tends to work well on
8724 // the kinds of shuffles that show up in practice.
8726 // FIXME: Handle 1x, 2x, and 4x interleaving.
8727 if (shouldLowerAsInterleaving(Mask)) {
8728 // FIXME: Figure out whether we should pack these into the low or high
8731 int EMask[8], OMask[8];
8732 for (int i = 0; i < 4; ++i) {
8733 EMask[i] = Mask[2*i];
8734 OMask[i] = Mask[2*i + 1];
8739 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8740 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8742 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8745 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8746 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8748 for (int i = 0; i < 4; ++i) {
8749 LoBlendMask[i] = Mask[i];
8750 HiBlendMask[i] = Mask[i + 4];
8753 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8754 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8755 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8756 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8758 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8759 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8762 /// \brief Check whether a compaction lowering can be done by dropping even
8763 /// elements and compute how many times even elements must be dropped.
8765 /// This handles shuffles which take every Nth element where N is a power of
8766 /// two. Example shuffle masks:
8768 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8769 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8770 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8771 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8772 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8773 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8775 /// Any of these lanes can of course be undef.
8777 /// This routine only supports N <= 3.
8778 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8781 /// \returns N above, or the number of times even elements must be dropped if
8782 /// there is such a number. Otherwise returns zero.
8783 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8784 // Figure out whether we're looping over two inputs or just one.
8785 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8787 // The modulus for the shuffle vector entries is based on whether this is
8788 // a single input or not.
8789 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8790 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8791 "We should only be called with masks with a power-of-2 size!");
8793 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8795 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8796 // and 2^3 simultaneously. This is because we may have ambiguity with
8797 // partially undef inputs.
8798 bool ViableForN[3] = {true, true, true};
8800 for (int i = 0, e = Mask.size(); i < e; ++i) {
8801 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8806 bool IsAnyViable = false;
8807 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8808 if (ViableForN[j]) {
8811 // The shuffle mask must be equal to (i * 2^N) % M.
8812 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8815 ViableForN[j] = false;
8817 // Early exit if we exhaust the possible powers of two.
8822 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8826 // Return 0 as there is no viable power of two.
8830 /// \brief Generic lowering of v16i8 shuffles.
8832 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8833 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8834 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8835 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8837 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8838 const X86Subtarget *Subtarget,
8839 SelectionDAG &DAG) {
8841 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8842 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8843 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8844 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8845 ArrayRef<int> OrigMask = SVOp->getMask();
8846 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8848 // Try to use rotation instructions if available.
8849 if (Subtarget->hasSSSE3())
8850 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8854 // Try to use a zext lowering.
8855 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8856 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8859 int MaskStorage[16] = {
8860 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8861 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8862 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8863 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8864 MutableArrayRef<int> Mask(MaskStorage);
8865 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8866 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8869 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8871 // For single-input shuffles, there are some nicer lowering tricks we can use.
8872 if (NumV2Elements == 0) {
8873 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8874 // Notably, this handles splat and partial-splat shuffles more efficiently.
8875 // However, it only makes sense if the pre-duplication shuffle simplifies
8876 // things significantly. Currently, this means we need to be able to
8877 // express the pre-duplication shuffle as an i16 shuffle.
8879 // FIXME: We should check for other patterns which can be widened into an
8880 // i16 shuffle as well.
8881 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8882 for (int i = 0; i < 16; i += 2)
8883 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8888 auto tryToWidenViaDuplication = [&]() -> SDValue {
8889 if (!canWidenViaDuplication(Mask))
8891 SmallVector<int, 4> LoInputs;
8892 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8893 [](int M) { return M >= 0 && M < 8; });
8894 std::sort(LoInputs.begin(), LoInputs.end());
8895 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8897 SmallVector<int, 4> HiInputs;
8898 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8899 [](int M) { return M >= 8; });
8900 std::sort(HiInputs.begin(), HiInputs.end());
8901 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8904 bool TargetLo = LoInputs.size() >= HiInputs.size();
8905 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8906 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8908 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8909 SmallDenseMap<int, int, 8> LaneMap;
8910 for (int I : InPlaceInputs) {
8911 PreDupI16Shuffle[I/2] = I/2;
8914 int j = TargetLo ? 0 : 4, je = j + 4;
8915 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8916 // Check if j is already a shuffle of this input. This happens when
8917 // there are two adjacent bytes after we move the low one.
8918 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8919 // If we haven't yet mapped the input, search for a slot into which
8921 while (j < je && PreDupI16Shuffle[j] != -1)
8925 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8928 // Map this input with the i16 shuffle.
8929 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8932 // Update the lane map based on the mapping we ended up with.
8933 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8936 ISD::BITCAST, DL, MVT::v16i8,
8937 DAG.getVectorShuffle(MVT::v8i16, DL,
8938 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8939 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8941 // Unpack the bytes to form the i16s that will be shuffled into place.
8942 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8943 MVT::v16i8, V1, V1);
8945 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8946 for (int i = 0; i < 16; i += 2) {
8948 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8949 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8952 ISD::BITCAST, DL, MVT::v16i8,
8953 DAG.getVectorShuffle(MVT::v8i16, DL,
8954 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8955 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8957 if (SDValue V = tryToWidenViaDuplication())
8961 // Check whether an interleaving lowering is likely to be more efficient.
8962 // This isn't perfect but it is a strong heuristic that tends to work well on
8963 // the kinds of shuffles that show up in practice.
8965 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8966 if (shouldLowerAsInterleaving(Mask)) {
8967 // FIXME: Figure out whether we should pack these into the low or high
8970 int EMask[16], OMask[16];
8971 for (int i = 0; i < 8; ++i) {
8972 EMask[i] = Mask[2*i];
8973 OMask[i] = Mask[2*i + 1];
8978 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8979 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8981 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8984 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8985 // with PSHUFB. It is important to do this before we attempt to generate any
8986 // blends but after all of the single-input lowerings. If the single input
8987 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8988 // want to preserve that and we can DAG combine any longer sequences into
8989 // a PSHUFB in the end. But once we start blending from multiple inputs,
8990 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8991 // and there are *very* few patterns that would actually be faster than the
8992 // PSHUFB approach because of its ability to zero lanes.
8994 // FIXME: The only exceptions to the above are blends which are exact
8995 // interleavings with direct instructions supporting them. We currently don't
8996 // handle those well here.
8997 if (Subtarget->hasSSSE3()) {
9000 for (int i = 0; i < 16; ++i)
9001 if (Mask[i] == -1) {
9002 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9004 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9006 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9008 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9009 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9010 if (isSingleInputShuffleMask(Mask))
9011 return V1; // Single inputs are easy.
9013 // Otherwise, blend the two.
9014 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9015 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9016 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9019 // There are special ways we can lower some single-element blends.
9020 if (NumV2Elements == 1)
9021 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9022 Mask, Subtarget, DAG))
9025 // Check whether a compaction lowering can be done. This handles shuffles
9026 // which take every Nth element for some even N. See the helper function for
9029 // We special case these as they can be particularly efficiently handled with
9030 // the PACKUSB instruction on x86 and they show up in common patterns of
9031 // rearranging bytes to truncate wide elements.
9032 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9033 // NumEvenDrops is the power of two stride of the elements. Another way of
9034 // thinking about it is that we need to drop the even elements this many
9035 // times to get the original input.
9036 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9038 // First we need to zero all the dropped bytes.
9039 assert(NumEvenDrops <= 3 &&
9040 "No support for dropping even elements more than 3 times.");
9041 // We use the mask type to pick which bytes are preserved based on how many
9042 // elements are dropped.
9043 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9044 SDValue ByteClearMask =
9045 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9046 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9047 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9049 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9051 // Now pack things back together.
9052 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9053 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9054 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9055 for (int i = 1; i < NumEvenDrops; ++i) {
9056 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9057 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9063 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9064 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9065 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9066 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9068 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9069 MutableArrayRef<int> V1HalfBlendMask,
9070 MutableArrayRef<int> V2HalfBlendMask) {
9071 for (int i = 0; i < 8; ++i)
9072 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9073 V1HalfBlendMask[i] = HalfMask[i];
9075 } else if (HalfMask[i] >= 16) {
9076 V2HalfBlendMask[i] = HalfMask[i] - 16;
9077 HalfMask[i] = i + 8;
9080 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9081 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9083 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9085 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9086 MutableArrayRef<int> HiBlendMask) {
9088 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9089 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9091 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9092 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9093 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9094 [](int M) { return M >= 0 && M % 2 == 1; })) {
9095 // Use a mask to drop the high bytes.
9096 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9097 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9098 DAG.getConstant(0x00FF, MVT::v8i16));
9100 // This will be a single vector shuffle instead of a blend so nuke V2.
9101 V2 = DAG.getUNDEF(MVT::v8i16);
9103 // Squash the masks to point directly into V1.
9104 for (int &M : LoBlendMask)
9107 for (int &M : HiBlendMask)
9111 // Otherwise just unpack the low half of V into V1 and the high half into
9112 // V2 so that we can blend them as i16s.
9113 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9114 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9115 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9116 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9119 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9120 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9121 return std::make_pair(BlendedLo, BlendedHi);
9123 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9124 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9125 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9127 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9128 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9130 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9133 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9135 /// This routine breaks down the specific type of 128-bit shuffle and
9136 /// dispatches to the lowering routines accordingly.
9137 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9138 MVT VT, const X86Subtarget *Subtarget,
9139 SelectionDAG &DAG) {
9140 switch (VT.SimpleTy) {
9142 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9144 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9146 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9148 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9150 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9152 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9155 llvm_unreachable("Unimplemented!");
9159 /// \brief Test whether there are elements crossing 128-bit lanes in this
9162 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9163 /// and we routinely test for these.
9164 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9165 int LaneSize = 128 / VT.getScalarSizeInBits();
9166 int Size = Mask.size();
9167 for (int i = 0; i < Size; ++i)
9168 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9173 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9175 /// This checks a shuffle mask to see if it is performing the same
9176 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9177 /// that it is also not lane-crossing.
9178 static bool is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask) {
9179 int LaneSize = 128 / VT.getScalarSizeInBits();
9180 int Size = Mask.size();
9181 for (int i = LaneSize; i < Size; ++i)
9182 if (Mask[i] >= 0 && Mask[i] != (Mask[i % LaneSize] + (i / LaneSize) * LaneSize))
9187 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9190 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9191 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9192 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9193 /// we encode the logic here for specific shuffle lowering routines to bail to
9194 /// when they exhaust the features avaible to more directly handle the shuffle.
9195 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9197 const X86Subtarget *Subtarget,
9198 SelectionDAG &DAG) {
9200 MVT VT = Op.getSimpleValueType();
9201 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9202 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9203 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9204 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9205 ArrayRef<int> Mask = SVOp->getMask();
9207 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9208 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9210 int NumElements = VT.getVectorNumElements();
9211 int SplitNumElements = NumElements / 2;
9212 MVT ScalarVT = VT.getScalarType();
9213 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9215 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9216 DAG.getIntPtrConstant(0));
9217 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9218 DAG.getIntPtrConstant(SplitNumElements));
9219 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9220 DAG.getIntPtrConstant(0));
9221 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9222 DAG.getIntPtrConstant(SplitNumElements));
9224 // Now create two 4-way blends of these half-width vectors.
9225 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9226 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9227 for (int i = 0; i < SplitNumElements; ++i) {
9228 int M = HalfMask[i];
9229 if (M >= NumElements) {
9230 V2BlendMask.push_back(M - NumElements);
9231 V1BlendMask.push_back(-1);
9232 BlendMask.push_back(SplitNumElements + i);
9233 } else if (M >= 0) {
9234 V2BlendMask.push_back(-1);
9235 V1BlendMask.push_back(M);
9236 BlendMask.push_back(i);
9238 V2BlendMask.push_back(-1);
9239 V1BlendMask.push_back(-1);
9240 BlendMask.push_back(-1);
9243 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9244 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9245 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9247 SDValue Lo = HalfBlend(LoMask);
9248 SDValue Hi = HalfBlend(HiMask);
9249 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9252 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9254 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9255 /// isn't available.
9256 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9257 const X86Subtarget *Subtarget,
9258 SelectionDAG &DAG) {
9260 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9261 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9263 ArrayRef<int> Mask = SVOp->getMask();
9264 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9266 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9267 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9269 if (isSingleInputShuffleMask(Mask)) {
9270 // Non-half-crossing single input shuffles can be lowerid with an
9271 // interleaved permutation.
9272 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9273 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9274 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9275 DAG.getConstant(VPERMILPMask, MVT::i8));
9278 // X86 has dedicated unpack instructions that can handle specific blend
9279 // operations: UNPCKH and UNPCKL.
9280 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9281 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9282 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9283 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9285 // If we have a single input to the zero element, insert that into V1 if we
9286 // can do so cheaply.
9288 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9289 if (NumV2Elements == 1 && Mask[0] >= 4)
9290 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9291 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9295 lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask, DAG))
9298 // Check if the blend happens to exactly fit that of SHUFPD.
9299 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9300 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9301 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9302 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9303 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9304 DAG.getConstant(SHUFPDMask, MVT::i8));
9306 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9307 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9308 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9309 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9310 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9311 DAG.getConstant(SHUFPDMask, MVT::i8));
9314 // Shuffle the input elements into the desired positions in V1 and V2 and
9315 // blend them together.
9316 int V1Mask[] = {-1, -1, -1, -1};
9317 int V2Mask[] = {-1, -1, -1, -1};
9318 for (int i = 0; i < 4; ++i)
9319 if (Mask[i] >= 0 && Mask[i] < 4)
9320 V1Mask[i] = Mask[i];
9321 else if (Mask[i] >= 4)
9322 V2Mask[i] = Mask[i] - 4;
9324 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9325 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9327 unsigned BlendMask = 0;
9328 for (int i = 0; i < 4; ++i)
9330 BlendMask |= 1 << i;
9332 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9333 DAG.getConstant(BlendMask, MVT::i8));
9336 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9338 /// This routine is only called when we have AVX2 and thus a reasonable
9339 /// instruction set for v4i64 shuffling..
9340 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9341 const X86Subtarget *Subtarget,
9342 SelectionDAG &DAG) {
9344 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9345 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9346 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9347 ArrayRef<int> Mask = SVOp->getMask();
9348 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9349 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9351 // FIXME: Actually implement this using AVX2!!!
9352 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9353 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9354 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9355 DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
9358 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9360 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9361 /// isn't available.
9362 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9363 const X86Subtarget *Subtarget,
9364 SelectionDAG &DAG) {
9366 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9367 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9369 ArrayRef<int> Mask = SVOp->getMask();
9370 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9372 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9373 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9376 lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask, DAG))
9379 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9380 // options to efficiently lower the shuffle.
9381 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask)) {
9382 ArrayRef<int> LoMask = Mask.slice(0, 4);
9383 if (isSingleInputShuffleMask(Mask))
9384 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9385 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9387 // Use dedicated unpack instructions for masks that match their pattern.
9388 if (isShuffleEquivalent(LoMask, 0, 8, 1, 9))
9389 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9390 if (isShuffleEquivalent(LoMask, 2, 10, 3, 11))
9391 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9393 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9394 // have already handled any direct blends.
9395 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9396 for (int &M : SHUFPSMask)
9399 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9402 // If we have a single input shuffle with different shuffle patterns in the
9403 // two 128-bit lanes use the variable mask to VPERMILPS.
9404 if (isSingleInputShuffleMask(Mask)) {
9405 SDValue VPermMask[8];
9406 for (int i = 0; i < 8; ++i)
9407 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9408 : DAG.getConstant(Mask[i], MVT::i32);
9410 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9411 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9414 // Shuffle the input elements into the desired positions in V1 and V2 and
9415 // blend them together.
9416 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9417 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9418 unsigned BlendMask = 0;
9419 for (int i = 0; i < 8; ++i)
9420 if (Mask[i] >= 0 && Mask[i] < 8) {
9421 V1Mask[i] = Mask[i];
9422 } else if (Mask[i] >= 8) {
9423 V2Mask[i] = Mask[i] - 8;
9424 BlendMask |= 1 << i;
9427 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9428 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9430 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9431 DAG.getConstant(BlendMask, MVT::i8));
9434 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9436 /// This routine is only called when we have AVX2 and thus a reasonable
9437 /// instruction set for v8i32 shuffling..
9438 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9439 const X86Subtarget *Subtarget,
9440 SelectionDAG &DAG) {
9442 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9443 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9444 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9445 ArrayRef<int> Mask = SVOp->getMask();
9446 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9447 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9449 // FIXME: Actually implement this using AVX2!!!
9450 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V1);
9451 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V2);
9452 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i32,
9453 DAG.getVectorShuffle(MVT::v8f32, DL, V1, V2, Mask));
9456 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9458 /// This routine is only called when we have AVX2 and thus a reasonable
9459 /// instruction set for v16i16 shuffling..
9460 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9461 const X86Subtarget *Subtarget,
9462 SelectionDAG &DAG) {
9464 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9465 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9466 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9467 ArrayRef<int> Mask = SVOp->getMask();
9468 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9469 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9471 // FIXME: Actually implement this using AVX2!!!
9473 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9476 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9478 /// This routine is only called when we have AVX2 and thus a reasonable
9479 /// instruction set for v32i8 shuffling..
9480 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9481 const X86Subtarget *Subtarget,
9482 SelectionDAG &DAG) {
9484 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9485 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9486 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9487 ArrayRef<int> Mask = SVOp->getMask();
9488 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9489 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9491 // FIXME: Actually implement this using AVX2!!!
9493 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9496 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9498 /// This routine either breaks down the specific type of a 256-bit x86 vector
9499 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9500 /// together based on the available instructions.
9501 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9502 MVT VT, const X86Subtarget *Subtarget,
9503 SelectionDAG &DAG) {
9505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9506 ArrayRef<int> Mask = SVOp->getMask();
9508 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9509 // check for those subtargets here and avoid much of the subtarget querying in
9510 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9511 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9512 // floating point types there eventually, just immediately cast everything to
9513 // a float and operate entirely in that domain.
9514 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9515 int ElementBits = VT.getScalarSizeInBits();
9516 if (ElementBits < 32)
9517 // No floating point type available, decompose into 128-bit vectors.
9518 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9520 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9521 VT.getVectorNumElements());
9522 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9523 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9524 return DAG.getNode(ISD::BITCAST, DL, VT,
9525 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9528 switch (VT.SimpleTy) {
9530 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9532 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9534 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9536 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9538 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9540 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9543 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9547 /// \brief Tiny helper function to test whether a shuffle mask could be
9548 /// simplified by widening the elements being shuffled.
9549 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9550 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9551 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9552 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9553 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9559 /// \brief Top-level lowering for x86 vector shuffles.
9561 /// This handles decomposition, canonicalization, and lowering of all x86
9562 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9563 /// above in helper routines. The canonicalization attempts to widen shuffles
9564 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9565 /// s.t. only one of the two inputs needs to be tested, etc.
9566 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9567 SelectionDAG &DAG) {
9568 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9569 ArrayRef<int> Mask = SVOp->getMask();
9570 SDValue V1 = Op.getOperand(0);
9571 SDValue V2 = Op.getOperand(1);
9572 MVT VT = Op.getSimpleValueType();
9573 int NumElements = VT.getVectorNumElements();
9576 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9578 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9579 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9580 if (V1IsUndef && V2IsUndef)
9581 return DAG.getUNDEF(VT);
9583 // When we create a shuffle node we put the UNDEF node to second operand,
9584 // but in some cases the first operand may be transformed to UNDEF.
9585 // In this case we should just commute the node.
9587 return DAG.getCommutedVectorShuffle(*SVOp);
9589 // Check for non-undef masks pointing at an undef vector and make the masks
9590 // undef as well. This makes it easier to match the shuffle based solely on
9594 if (M >= NumElements) {
9595 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9596 for (int &M : NewMask)
9597 if (M >= NumElements)
9599 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9602 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9603 // lanes but wider integers. We cap this to not form integers larger than i64
9604 // but it might be interesting to form i128 integers to handle flipping the
9605 // low and high halves of AVX 256-bit vectors.
9606 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9607 canWidenShuffleElements(Mask)) {
9608 SmallVector<int, 8> NewMask;
9609 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9610 NewMask.push_back(Mask[i] != -1
9612 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9614 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9615 VT.getVectorNumElements() / 2);
9616 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9617 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9618 return DAG.getNode(ISD::BITCAST, dl, VT,
9619 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9622 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9623 for (int M : SVOp->getMask())
9626 else if (M < NumElements)
9631 // Commute the shuffle as needed such that more elements come from V1 than
9632 // V2. This allows us to match the shuffle pattern strictly on how many
9633 // elements come from V1 without handling the symmetric cases.
9634 if (NumV2Elements > NumV1Elements)
9635 return DAG.getCommutedVectorShuffle(*SVOp);
9637 // When the number of V1 and V2 elements are the same, try to minimize the
9638 // number of uses of V2 in the low half of the vector. When that is tied,
9639 // ensure that the sum of indices for V1 is equal to or lower than the sum
9641 if (NumV1Elements == NumV2Elements) {
9642 int LowV1Elements = 0, LowV2Elements = 0;
9643 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9644 if (M >= NumElements)
9648 if (LowV2Elements > LowV1Elements)
9649 return DAG.getCommutedVectorShuffle(*SVOp);
9651 int SumV1Indices = 0, SumV2Indices = 0;
9652 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9653 if (SVOp->getMask()[i] >= NumElements)
9655 else if (SVOp->getMask()[i] >= 0)
9657 if (SumV2Indices < SumV1Indices)
9658 return DAG.getCommutedVectorShuffle(*SVOp);
9661 // For each vector width, delegate to a specialized lowering routine.
9662 if (VT.getSizeInBits() == 128)
9663 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9665 if (VT.getSizeInBits() == 256)
9666 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9668 llvm_unreachable("Unimplemented!");
9672 //===----------------------------------------------------------------------===//
9673 // Legacy vector shuffle lowering
9675 // This code is the legacy code handling vector shuffles until the above
9676 // replaces its functionality and performance.
9677 //===----------------------------------------------------------------------===//
9679 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9680 bool hasInt256, unsigned *MaskOut = nullptr) {
9681 MVT EltVT = VT.getVectorElementType();
9683 // There is no blend with immediate in AVX-512.
9684 if (VT.is512BitVector())
9687 if (!hasSSE41 || EltVT == MVT::i8)
9689 if (!hasInt256 && VT == MVT::v16i16)
9692 unsigned MaskValue = 0;
9693 unsigned NumElems = VT.getVectorNumElements();
9694 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9695 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9696 unsigned NumElemsInLane = NumElems / NumLanes;
9698 // Blend for v16i16 should be symetric for the both lanes.
9699 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9701 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9702 int EltIdx = MaskVals[i];
9704 if ((EltIdx < 0 || EltIdx == (int)i) &&
9705 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9708 if (((unsigned)EltIdx == (i + NumElems)) &&
9709 (SndLaneEltIdx < 0 ||
9710 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9711 MaskValue |= (1 << i);
9717 *MaskOut = MaskValue;
9721 // Try to lower a shuffle node into a simple blend instruction.
9722 // This function assumes isBlendMask returns true for this
9723 // SuffleVectorSDNode
9724 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9726 const X86Subtarget *Subtarget,
9727 SelectionDAG &DAG) {
9728 MVT VT = SVOp->getSimpleValueType(0);
9729 MVT EltVT = VT.getVectorElementType();
9730 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9731 Subtarget->hasInt256() && "Trying to lower a "
9732 "VECTOR_SHUFFLE to a Blend but "
9733 "with the wrong mask"));
9734 SDValue V1 = SVOp->getOperand(0);
9735 SDValue V2 = SVOp->getOperand(1);
9737 unsigned NumElems = VT.getVectorNumElements();
9739 // Convert i32 vectors to floating point if it is not AVX2.
9740 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9742 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9743 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9745 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9746 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9749 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9750 DAG.getConstant(MaskValue, MVT::i32));
9751 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9754 /// In vector type \p VT, return true if the element at index \p InputIdx
9755 /// falls on a different 128-bit lane than \p OutputIdx.
9756 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9757 unsigned OutputIdx) {
9758 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9759 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9762 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9763 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9764 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9765 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9767 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9768 SelectionDAG &DAG) {
9769 MVT VT = V1.getSimpleValueType();
9770 assert(VT.is128BitVector() || VT.is256BitVector());
9772 MVT EltVT = VT.getVectorElementType();
9773 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9774 unsigned NumElts = VT.getVectorNumElements();
9776 SmallVector<SDValue, 32> PshufbMask;
9777 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9778 int InputIdx = MaskVals[OutputIdx];
9779 unsigned InputByteIdx;
9781 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9782 InputByteIdx = 0x80;
9784 // Cross lane is not allowed.
9785 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9787 InputByteIdx = InputIdx * EltSizeInBytes;
9788 // Index is an byte offset within the 128-bit lane.
9789 InputByteIdx &= 0xf;
9792 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9793 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9794 if (InputByteIdx != 0x80)
9799 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9801 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9802 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9803 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9806 // v8i16 shuffles - Prefer shuffles in the following order:
9807 // 1. [all] pshuflw, pshufhw, optional move
9808 // 2. [ssse3] 1 x pshufb
9809 // 3. [ssse3] 2 x pshufb + 1 x por
9810 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9812 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9813 SelectionDAG &DAG) {
9814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9815 SDValue V1 = SVOp->getOperand(0);
9816 SDValue V2 = SVOp->getOperand(1);
9818 SmallVector<int, 8> MaskVals;
9820 // Determine if more than 1 of the words in each of the low and high quadwords
9821 // of the result come from the same quadword of one of the two inputs. Undef
9822 // mask values count as coming from any quadword, for better codegen.
9824 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9825 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9826 unsigned LoQuad[] = { 0, 0, 0, 0 };
9827 unsigned HiQuad[] = { 0, 0, 0, 0 };
9828 // Indices of quads used.
9829 std::bitset<4> InputQuads;
9830 for (unsigned i = 0; i < 8; ++i) {
9831 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9832 int EltIdx = SVOp->getMaskElt(i);
9833 MaskVals.push_back(EltIdx);
9842 InputQuads.set(EltIdx / 4);
9845 int BestLoQuad = -1;
9846 unsigned MaxQuad = 1;
9847 for (unsigned i = 0; i < 4; ++i) {
9848 if (LoQuad[i] > MaxQuad) {
9850 MaxQuad = LoQuad[i];
9854 int BestHiQuad = -1;
9856 for (unsigned i = 0; i < 4; ++i) {
9857 if (HiQuad[i] > MaxQuad) {
9859 MaxQuad = HiQuad[i];
9863 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9864 // of the two input vectors, shuffle them into one input vector so only a
9865 // single pshufb instruction is necessary. If there are more than 2 input
9866 // quads, disable the next transformation since it does not help SSSE3.
9867 bool V1Used = InputQuads[0] || InputQuads[1];
9868 bool V2Used = InputQuads[2] || InputQuads[3];
9869 if (Subtarget->hasSSSE3()) {
9870 if (InputQuads.count() == 2 && V1Used && V2Used) {
9871 BestLoQuad = InputQuads[0] ? 0 : 1;
9872 BestHiQuad = InputQuads[2] ? 2 : 3;
9874 if (InputQuads.count() > 2) {
9880 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9881 // the shuffle mask. If a quad is scored as -1, that means that it contains
9882 // words from all 4 input quadwords.
9884 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9886 BestLoQuad < 0 ? 0 : BestLoQuad,
9887 BestHiQuad < 0 ? 1 : BestHiQuad
9889 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9890 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9891 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9892 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9894 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9895 // source words for the shuffle, to aid later transformations.
9896 bool AllWordsInNewV = true;
9897 bool InOrder[2] = { true, true };
9898 for (unsigned i = 0; i != 8; ++i) {
9899 int idx = MaskVals[i];
9901 InOrder[i/4] = false;
9902 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9904 AllWordsInNewV = false;
9908 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9909 if (AllWordsInNewV) {
9910 for (int i = 0; i != 8; ++i) {
9911 int idx = MaskVals[i];
9914 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9915 if ((idx != i) && idx < 4)
9917 if ((idx != i) && idx > 3)
9926 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9927 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9928 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9929 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9930 unsigned TargetMask = 0;
9931 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9932 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9934 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9935 getShufflePSHUFLWImmediate(SVOp);
9936 V1 = NewV.getOperand(0);
9937 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9941 // Promote splats to a larger type which usually leads to more efficient code.
9942 // FIXME: Is this true if pshufb is available?
9943 if (SVOp->isSplat())
9944 return PromoteSplat(SVOp, DAG);
9946 // If we have SSSE3, and all words of the result are from 1 input vector,
9947 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9948 // is present, fall back to case 4.
9949 if (Subtarget->hasSSSE3()) {
9950 SmallVector<SDValue,16> pshufbMask;
9952 // If we have elements from both input vectors, set the high bit of the
9953 // shuffle mask element to zero out elements that come from V2 in the V1
9954 // mask, and elements that come from V1 in the V2 mask, so that the two
9955 // results can be OR'd together.
9956 bool TwoInputs = V1Used && V2Used;
9957 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9959 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9961 // Calculate the shuffle mask for the second input, shuffle it, and
9962 // OR it with the first shuffled input.
9963 CommuteVectorShuffleMask(MaskVals, 8);
9964 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9965 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9966 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9969 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9970 // and update MaskVals with new element order.
9971 std::bitset<8> InOrder;
9972 if (BestLoQuad >= 0) {
9973 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9974 for (int i = 0; i != 4; ++i) {
9975 int idx = MaskVals[i];
9978 } else if ((idx / 4) == BestLoQuad) {
9983 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9986 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9988 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9990 getShufflePSHUFLWImmediate(SVOp), DAG);
9994 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9995 // and update MaskVals with the new element order.
9996 if (BestHiQuad >= 0) {
9997 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9998 for (unsigned i = 4; i != 8; ++i) {
9999 int idx = MaskVals[i];
10002 } else if ((idx / 4) == BestHiQuad) {
10003 MaskV[i] = (idx & 3) + 4;
10007 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10010 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10012 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10013 NewV.getOperand(0),
10014 getShufflePSHUFHWImmediate(SVOp), DAG);
10018 // In case BestHi & BestLo were both -1, which means each quadword has a word
10019 // from each of the four input quadwords, calculate the InOrder bitvector now
10020 // before falling through to the insert/extract cleanup.
10021 if (BestLoQuad == -1 && BestHiQuad == -1) {
10023 for (int i = 0; i != 8; ++i)
10024 if (MaskVals[i] < 0 || MaskVals[i] == i)
10028 // The other elements are put in the right place using pextrw and pinsrw.
10029 for (unsigned i = 0; i != 8; ++i) {
10032 int EltIdx = MaskVals[i];
10035 SDValue ExtOp = (EltIdx < 8) ?
10036 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10037 DAG.getIntPtrConstant(EltIdx)) :
10038 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10039 DAG.getIntPtrConstant(EltIdx - 8));
10040 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10041 DAG.getIntPtrConstant(i));
10046 /// \brief v16i16 shuffles
10048 /// FIXME: We only support generation of a single pshufb currently. We can
10049 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10050 /// well (e.g 2 x pshufb + 1 x por).
10052 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10054 SDValue V1 = SVOp->getOperand(0);
10055 SDValue V2 = SVOp->getOperand(1);
10058 if (V2.getOpcode() != ISD::UNDEF)
10061 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10062 return getPSHUFB(MaskVals, V1, dl, DAG);
10065 // v16i8 shuffles - Prefer shuffles in the following order:
10066 // 1. [ssse3] 1 x pshufb
10067 // 2. [ssse3] 2 x pshufb + 1 x por
10068 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10069 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10070 const X86Subtarget* Subtarget,
10071 SelectionDAG &DAG) {
10072 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10073 SDValue V1 = SVOp->getOperand(0);
10074 SDValue V2 = SVOp->getOperand(1);
10076 ArrayRef<int> MaskVals = SVOp->getMask();
10078 // Promote splats to a larger type which usually leads to more efficient code.
10079 // FIXME: Is this true if pshufb is available?
10080 if (SVOp->isSplat())
10081 return PromoteSplat(SVOp, DAG);
10083 // If we have SSSE3, case 1 is generated when all result bytes come from
10084 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10085 // present, fall back to case 3.
10087 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10088 if (Subtarget->hasSSSE3()) {
10089 SmallVector<SDValue,16> pshufbMask;
10091 // If all result elements are from one input vector, then only translate
10092 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10094 // Otherwise, we have elements from both input vectors, and must zero out
10095 // elements that come from V2 in the first mask, and V1 in the second mask
10096 // so that we can OR them together.
10097 for (unsigned i = 0; i != 16; ++i) {
10098 int EltIdx = MaskVals[i];
10099 if (EltIdx < 0 || EltIdx >= 16)
10101 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10103 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10104 DAG.getNode(ISD::BUILD_VECTOR, dl,
10105 MVT::v16i8, pshufbMask));
10107 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10108 // the 2nd operand if it's undefined or zero.
10109 if (V2.getOpcode() == ISD::UNDEF ||
10110 ISD::isBuildVectorAllZeros(V2.getNode()))
10113 // Calculate the shuffle mask for the second input, shuffle it, and
10114 // OR it with the first shuffled input.
10115 pshufbMask.clear();
10116 for (unsigned i = 0; i != 16; ++i) {
10117 int EltIdx = MaskVals[i];
10118 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10119 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10121 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10122 DAG.getNode(ISD::BUILD_VECTOR, dl,
10123 MVT::v16i8, pshufbMask));
10124 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10127 // No SSSE3 - Calculate in place words and then fix all out of place words
10128 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10129 // the 16 different words that comprise the two doublequadword input vectors.
10130 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10131 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10133 for (int i = 0; i != 8; ++i) {
10134 int Elt0 = MaskVals[i*2];
10135 int Elt1 = MaskVals[i*2+1];
10137 // This word of the result is all undef, skip it.
10138 if (Elt0 < 0 && Elt1 < 0)
10141 // This word of the result is already in the correct place, skip it.
10142 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10145 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10146 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10149 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10150 // using a single extract together, load it and store it.
10151 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10152 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10153 DAG.getIntPtrConstant(Elt1 / 2));
10154 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10155 DAG.getIntPtrConstant(i));
10159 // If Elt1 is defined, extract it from the appropriate source. If the
10160 // source byte is not also odd, shift the extracted word left 8 bits
10161 // otherwise clear the bottom 8 bits if we need to do an or.
10163 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10164 DAG.getIntPtrConstant(Elt1 / 2));
10165 if ((Elt1 & 1) == 0)
10166 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10168 TLI.getShiftAmountTy(InsElt.getValueType())));
10169 else if (Elt0 >= 0)
10170 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10171 DAG.getConstant(0xFF00, MVT::i16));
10173 // If Elt0 is defined, extract it from the appropriate source. If the
10174 // source byte is not also even, shift the extracted word right 8 bits. If
10175 // Elt1 was also defined, OR the extracted values together before
10176 // inserting them in the result.
10178 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10179 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10180 if ((Elt0 & 1) != 0)
10181 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10183 TLI.getShiftAmountTy(InsElt0.getValueType())));
10184 else if (Elt1 >= 0)
10185 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10186 DAG.getConstant(0x00FF, MVT::i16));
10187 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10190 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10191 DAG.getIntPtrConstant(i));
10193 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10196 // v32i8 shuffles - Translate to VPSHUFB if possible.
10198 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10199 const X86Subtarget *Subtarget,
10200 SelectionDAG &DAG) {
10201 MVT VT = SVOp->getSimpleValueType(0);
10202 SDValue V1 = SVOp->getOperand(0);
10203 SDValue V2 = SVOp->getOperand(1);
10205 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10207 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10208 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10209 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10211 // VPSHUFB may be generated if
10212 // (1) one of input vector is undefined or zeroinitializer.
10213 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10214 // And (2) the mask indexes don't cross the 128-bit lane.
10215 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10216 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10219 if (V1IsAllZero && !V2IsAllZero) {
10220 CommuteVectorShuffleMask(MaskVals, 32);
10223 return getPSHUFB(MaskVals, V1, dl, DAG);
10226 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10227 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10228 /// done when every pair / quad of shuffle mask elements point to elements in
10229 /// the right sequence. e.g.
10230 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10232 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10233 SelectionDAG &DAG) {
10234 MVT VT = SVOp->getSimpleValueType(0);
10236 unsigned NumElems = VT.getVectorNumElements();
10239 switch (VT.SimpleTy) {
10240 default: llvm_unreachable("Unexpected!");
10243 return SDValue(SVOp, 0);
10244 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10245 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10246 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10247 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10248 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10249 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10252 SmallVector<int, 8> MaskVec;
10253 for (unsigned i = 0; i != NumElems; i += Scale) {
10255 for (unsigned j = 0; j != Scale; ++j) {
10256 int EltIdx = SVOp->getMaskElt(i+j);
10260 StartIdx = (EltIdx / Scale);
10261 if (EltIdx != (int)(StartIdx*Scale + j))
10264 MaskVec.push_back(StartIdx);
10267 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10268 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10269 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10272 /// getVZextMovL - Return a zero-extending vector move low node.
10274 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10275 SDValue SrcOp, SelectionDAG &DAG,
10276 const X86Subtarget *Subtarget, SDLoc dl) {
10277 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10278 LoadSDNode *LD = nullptr;
10279 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10280 LD = dyn_cast<LoadSDNode>(SrcOp);
10282 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10284 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10285 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10286 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10287 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10288 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10290 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10291 return DAG.getNode(ISD::BITCAST, dl, VT,
10292 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10293 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10295 SrcOp.getOperand(0)
10301 return DAG.getNode(ISD::BITCAST, dl, VT,
10302 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10303 DAG.getNode(ISD::BITCAST, dl,
10307 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10308 /// which could not be matched by any known target speficic shuffle
10310 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10312 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10313 if (NewOp.getNode())
10316 MVT VT = SVOp->getSimpleValueType(0);
10318 unsigned NumElems = VT.getVectorNumElements();
10319 unsigned NumLaneElems = NumElems / 2;
10322 MVT EltVT = VT.getVectorElementType();
10323 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10326 SmallVector<int, 16> Mask;
10327 for (unsigned l = 0; l < 2; ++l) {
10328 // Build a shuffle mask for the output, discovering on the fly which
10329 // input vectors to use as shuffle operands (recorded in InputUsed).
10330 // If building a suitable shuffle vector proves too hard, then bail
10331 // out with UseBuildVector set.
10332 bool UseBuildVector = false;
10333 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10334 unsigned LaneStart = l * NumLaneElems;
10335 for (unsigned i = 0; i != NumLaneElems; ++i) {
10336 // The mask element. This indexes into the input.
10337 int Idx = SVOp->getMaskElt(i+LaneStart);
10339 // the mask element does not index into any input vector.
10340 Mask.push_back(-1);
10344 // The input vector this mask element indexes into.
10345 int Input = Idx / NumLaneElems;
10347 // Turn the index into an offset from the start of the input vector.
10348 Idx -= Input * NumLaneElems;
10350 // Find or create a shuffle vector operand to hold this input.
10352 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10353 if (InputUsed[OpNo] == Input)
10354 // This input vector is already an operand.
10356 if (InputUsed[OpNo] < 0) {
10357 // Create a new operand for this input vector.
10358 InputUsed[OpNo] = Input;
10363 if (OpNo >= array_lengthof(InputUsed)) {
10364 // More than two input vectors used! Give up on trying to create a
10365 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10366 UseBuildVector = true;
10370 // Add the mask index for the new shuffle vector.
10371 Mask.push_back(Idx + OpNo * NumLaneElems);
10374 if (UseBuildVector) {
10375 SmallVector<SDValue, 16> SVOps;
10376 for (unsigned i = 0; i != NumLaneElems; ++i) {
10377 // The mask element. This indexes into the input.
10378 int Idx = SVOp->getMaskElt(i+LaneStart);
10380 SVOps.push_back(DAG.getUNDEF(EltVT));
10384 // The input vector this mask element indexes into.
10385 int Input = Idx / NumElems;
10387 // Turn the index into an offset from the start of the input vector.
10388 Idx -= Input * NumElems;
10390 // Extract the vector element by hand.
10391 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10392 SVOp->getOperand(Input),
10393 DAG.getIntPtrConstant(Idx)));
10396 // Construct the output using a BUILD_VECTOR.
10397 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10398 } else if (InputUsed[0] < 0) {
10399 // No input vectors were used! The result is undefined.
10400 Output[l] = DAG.getUNDEF(NVT);
10402 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10403 (InputUsed[0] % 2) * NumLaneElems,
10405 // If only one input was used, use an undefined vector for the other.
10406 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10407 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10408 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10409 // At least one input vector was used. Create a new shuffle vector.
10410 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10416 // Concatenate the result back
10417 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10420 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10421 /// 4 elements, and match them with several different shuffle types.
10423 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10424 SDValue V1 = SVOp->getOperand(0);
10425 SDValue V2 = SVOp->getOperand(1);
10427 MVT VT = SVOp->getSimpleValueType(0);
10429 assert(VT.is128BitVector() && "Unsupported vector size");
10431 std::pair<int, int> Locs[4];
10432 int Mask1[] = { -1, -1, -1, -1 };
10433 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10435 unsigned NumHi = 0;
10436 unsigned NumLo = 0;
10437 for (unsigned i = 0; i != 4; ++i) {
10438 int Idx = PermMask[i];
10440 Locs[i] = std::make_pair(-1, -1);
10442 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10444 Locs[i] = std::make_pair(0, NumLo);
10445 Mask1[NumLo] = Idx;
10448 Locs[i] = std::make_pair(1, NumHi);
10450 Mask1[2+NumHi] = Idx;
10456 if (NumLo <= 2 && NumHi <= 2) {
10457 // If no more than two elements come from either vector. This can be
10458 // implemented with two shuffles. First shuffle gather the elements.
10459 // The second shuffle, which takes the first shuffle as both of its
10460 // vector operands, put the elements into the right order.
10461 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10463 int Mask2[] = { -1, -1, -1, -1 };
10465 for (unsigned i = 0; i != 4; ++i)
10466 if (Locs[i].first != -1) {
10467 unsigned Idx = (i < 2) ? 0 : 4;
10468 Idx += Locs[i].first * 2 + Locs[i].second;
10472 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10475 if (NumLo == 3 || NumHi == 3) {
10476 // Otherwise, we must have three elements from one vector, call it X, and
10477 // one element from the other, call it Y. First, use a shufps to build an
10478 // intermediate vector with the one element from Y and the element from X
10479 // that will be in the same half in the final destination (the indexes don't
10480 // matter). Then, use a shufps to build the final vector, taking the half
10481 // containing the element from Y from the intermediate, and the other half
10484 // Normalize it so the 3 elements come from V1.
10485 CommuteVectorShuffleMask(PermMask, 4);
10489 // Find the element from V2.
10491 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10492 int Val = PermMask[HiIndex];
10499 Mask1[0] = PermMask[HiIndex];
10501 Mask1[2] = PermMask[HiIndex^1];
10503 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10505 if (HiIndex >= 2) {
10506 Mask1[0] = PermMask[0];
10507 Mask1[1] = PermMask[1];
10508 Mask1[2] = HiIndex & 1 ? 6 : 4;
10509 Mask1[3] = HiIndex & 1 ? 4 : 6;
10510 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10513 Mask1[0] = HiIndex & 1 ? 2 : 0;
10514 Mask1[1] = HiIndex & 1 ? 0 : 2;
10515 Mask1[2] = PermMask[2];
10516 Mask1[3] = PermMask[3];
10521 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10524 // Break it into (shuffle shuffle_hi, shuffle_lo).
10525 int LoMask[] = { -1, -1, -1, -1 };
10526 int HiMask[] = { -1, -1, -1, -1 };
10528 int *MaskPtr = LoMask;
10529 unsigned MaskIdx = 0;
10530 unsigned LoIdx = 0;
10531 unsigned HiIdx = 2;
10532 for (unsigned i = 0; i != 4; ++i) {
10539 int Idx = PermMask[i];
10541 Locs[i] = std::make_pair(-1, -1);
10542 } else if (Idx < 4) {
10543 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10544 MaskPtr[LoIdx] = Idx;
10547 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10548 MaskPtr[HiIdx] = Idx;
10553 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10554 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10555 int MaskOps[] = { -1, -1, -1, -1 };
10556 for (unsigned i = 0; i != 4; ++i)
10557 if (Locs[i].first != -1)
10558 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10559 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10562 static bool MayFoldVectorLoad(SDValue V) {
10563 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10564 V = V.getOperand(0);
10566 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10567 V = V.getOperand(0);
10568 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10569 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10570 // BUILD_VECTOR (load), undef
10571 V = V.getOperand(0);
10573 return MayFoldLoad(V);
10577 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10578 MVT VT = Op.getSimpleValueType();
10580 // Canonizalize to v2f64.
10581 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10582 return DAG.getNode(ISD::BITCAST, dl, VT,
10583 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10588 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10590 SDValue V1 = Op.getOperand(0);
10591 SDValue V2 = Op.getOperand(1);
10592 MVT VT = Op.getSimpleValueType();
10594 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10596 if (HasSSE2 && VT == MVT::v2f64)
10597 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10599 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10600 return DAG.getNode(ISD::BITCAST, dl, VT,
10601 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10602 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10603 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10607 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10608 SDValue V1 = Op.getOperand(0);
10609 SDValue V2 = Op.getOperand(1);
10610 MVT VT = Op.getSimpleValueType();
10612 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10613 "unsupported shuffle type");
10615 if (V2.getOpcode() == ISD::UNDEF)
10619 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10623 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10624 SDValue V1 = Op.getOperand(0);
10625 SDValue V2 = Op.getOperand(1);
10626 MVT VT = Op.getSimpleValueType();
10627 unsigned NumElems = VT.getVectorNumElements();
10629 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10630 // operand of these instructions is only memory, so check if there's a
10631 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10633 bool CanFoldLoad = false;
10635 // Trivial case, when V2 comes from a load.
10636 if (MayFoldVectorLoad(V2))
10637 CanFoldLoad = true;
10639 // When V1 is a load, it can be folded later into a store in isel, example:
10640 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10642 // (MOVLPSmr addr:$src1, VR128:$src2)
10643 // So, recognize this potential and also use MOVLPS or MOVLPD
10644 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10645 CanFoldLoad = true;
10647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10649 if (HasSSE2 && NumElems == 2)
10650 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10653 // If we don't care about the second element, proceed to use movss.
10654 if (SVOp->getMaskElt(1) != -1)
10655 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10658 // movl and movlp will both match v2i64, but v2i64 is never matched by
10659 // movl earlier because we make it strict to avoid messing with the movlp load
10660 // folding logic (see the code above getMOVLP call). Match it here then,
10661 // this is horrible, but will stay like this until we move all shuffle
10662 // matching to x86 specific nodes. Note that for the 1st condition all
10663 // types are matched with movsd.
10665 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10666 // as to remove this logic from here, as much as possible
10667 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10668 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10669 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10672 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10674 // Invert the operand order and use SHUFPS to match it.
10675 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10676 getShuffleSHUFImmediate(SVOp), DAG);
10679 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10680 SelectionDAG &DAG) {
10682 MVT VT = Load->getSimpleValueType(0);
10683 MVT EVT = VT.getVectorElementType();
10684 SDValue Addr = Load->getOperand(1);
10685 SDValue NewAddr = DAG.getNode(
10686 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10687 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10690 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10691 DAG.getMachineFunction().getMachineMemOperand(
10692 Load->getMemOperand(), 0, EVT.getStoreSize()));
10696 // It is only safe to call this function if isINSERTPSMask is true for
10697 // this shufflevector mask.
10698 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10699 SelectionDAG &DAG) {
10700 // Generate an insertps instruction when inserting an f32 from memory onto a
10701 // v4f32 or when copying a member from one v4f32 to another.
10702 // We also use it for transferring i32 from one register to another,
10703 // since it simply copies the same bits.
10704 // If we're transferring an i32 from memory to a specific element in a
10705 // register, we output a generic DAG that will match the PINSRD
10707 MVT VT = SVOp->getSimpleValueType(0);
10708 MVT EVT = VT.getVectorElementType();
10709 SDValue V1 = SVOp->getOperand(0);
10710 SDValue V2 = SVOp->getOperand(1);
10711 auto Mask = SVOp->getMask();
10712 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10713 "unsupported vector type for insertps/pinsrd");
10715 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10716 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10717 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10721 unsigned DestIndex;
10725 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10728 // If we have 1 element from each vector, we have to check if we're
10729 // changing V1's element's place. If so, we're done. Otherwise, we
10730 // should assume we're changing V2's element's place and behave
10732 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10733 assert(DestIndex <= INT32_MAX && "truncated destination index");
10734 if (FromV1 == FromV2 &&
10735 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10739 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10742 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10743 "More than one element from V1 and from V2, or no elements from one "
10744 "of the vectors. This case should not have returned true from "
10749 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10752 // Get an index into the source vector in the range [0,4) (the mask is
10753 // in the range [0,8) because it can address V1 and V2)
10754 unsigned SrcIndex = Mask[DestIndex] % 4;
10755 if (MayFoldLoad(From)) {
10756 // Trivial case, when From comes from a load and is only used by the
10757 // shuffle. Make it use insertps from the vector that we need from that
10760 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10761 if (!NewLoad.getNode())
10764 if (EVT == MVT::f32) {
10765 // Create this as a scalar to vector to match the instruction pattern.
10766 SDValue LoadScalarToVector =
10767 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10768 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10769 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10771 } else { // EVT == MVT::i32
10772 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10773 // instruction, to match the PINSRD instruction, which loads an i32 to a
10774 // certain vector element.
10775 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10776 DAG.getConstant(DestIndex, MVT::i32));
10780 // Vector-element-to-vector
10781 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10782 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10785 // Reduce a vector shuffle to zext.
10786 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10787 SelectionDAG &DAG) {
10788 // PMOVZX is only available from SSE41.
10789 if (!Subtarget->hasSSE41())
10792 MVT VT = Op.getSimpleValueType();
10794 // Only AVX2 support 256-bit vector integer extending.
10795 if (!Subtarget->hasInt256() && VT.is256BitVector())
10798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10800 SDValue V1 = Op.getOperand(0);
10801 SDValue V2 = Op.getOperand(1);
10802 unsigned NumElems = VT.getVectorNumElements();
10804 // Extending is an unary operation and the element type of the source vector
10805 // won't be equal to or larger than i64.
10806 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10807 VT.getVectorElementType() == MVT::i64)
10810 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10811 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10812 while ((1U << Shift) < NumElems) {
10813 if (SVOp->getMaskElt(1U << Shift) == 1)
10816 // The maximal ratio is 8, i.e. from i8 to i64.
10821 // Check the shuffle mask.
10822 unsigned Mask = (1U << Shift) - 1;
10823 for (unsigned i = 0; i != NumElems; ++i) {
10824 int EltIdx = SVOp->getMaskElt(i);
10825 if ((i & Mask) != 0 && EltIdx != -1)
10827 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10831 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10832 MVT NeVT = MVT::getIntegerVT(NBits);
10833 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10835 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10838 // Simplify the operand as it's prepared to be fed into shuffle.
10839 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10840 if (V1.getOpcode() == ISD::BITCAST &&
10841 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10842 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10843 V1.getOperand(0).getOperand(0)
10844 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10845 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10846 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10847 ConstantSDNode *CIdx =
10848 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10849 // If it's foldable, i.e. normal load with single use, we will let code
10850 // selection to fold it. Otherwise, we will short the conversion sequence.
10851 if (CIdx && CIdx->getZExtValue() == 0 &&
10852 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10853 MVT FullVT = V.getSimpleValueType();
10854 MVT V1VT = V1.getSimpleValueType();
10855 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10856 // The "ext_vec_elt" node is wider than the result node.
10857 // In this case we should extract subvector from V.
10858 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10859 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10860 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10861 FullVT.getVectorNumElements()/Ratio);
10862 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10863 DAG.getIntPtrConstant(0));
10865 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10869 return DAG.getNode(ISD::BITCAST, DL, VT,
10870 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10873 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10874 SelectionDAG &DAG) {
10875 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10876 MVT VT = Op.getSimpleValueType();
10878 SDValue V1 = Op.getOperand(0);
10879 SDValue V2 = Op.getOperand(1);
10881 if (isZeroShuffle(SVOp))
10882 return getZeroVector(VT, Subtarget, DAG, dl);
10884 // Handle splat operations
10885 if (SVOp->isSplat()) {
10886 // Use vbroadcast whenever the splat comes from a foldable load
10887 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10888 if (Broadcast.getNode())
10892 // Check integer expanding shuffles.
10893 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10894 if (NewOp.getNode())
10897 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10899 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10900 VT == MVT::v32i8) {
10901 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10902 if (NewOp.getNode())
10903 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10904 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10905 // FIXME: Figure out a cleaner way to do this.
10906 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10907 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10908 if (NewOp.getNode()) {
10909 MVT NewVT = NewOp.getSimpleValueType();
10910 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10911 NewVT, true, false))
10912 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10915 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10916 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10917 if (NewOp.getNode()) {
10918 MVT NewVT = NewOp.getSimpleValueType();
10919 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10920 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10929 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10931 SDValue V1 = Op.getOperand(0);
10932 SDValue V2 = Op.getOperand(1);
10933 MVT VT = Op.getSimpleValueType();
10935 unsigned NumElems = VT.getVectorNumElements();
10936 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10937 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10938 bool V1IsSplat = false;
10939 bool V2IsSplat = false;
10940 bool HasSSE2 = Subtarget->hasSSE2();
10941 bool HasFp256 = Subtarget->hasFp256();
10942 bool HasInt256 = Subtarget->hasInt256();
10943 MachineFunction &MF = DAG.getMachineFunction();
10944 bool OptForSize = MF.getFunction()->getAttributes().
10945 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10947 // Check if we should use the experimental vector shuffle lowering. If so,
10948 // delegate completely to that code path.
10949 if (ExperimentalVectorShuffleLowering)
10950 return lowerVectorShuffle(Op, Subtarget, DAG);
10952 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10954 if (V1IsUndef && V2IsUndef)
10955 return DAG.getUNDEF(VT);
10957 // When we create a shuffle node we put the UNDEF node to second operand,
10958 // but in some cases the first operand may be transformed to UNDEF.
10959 // In this case we should just commute the node.
10961 return DAG.getCommutedVectorShuffle(*SVOp);
10963 // Vector shuffle lowering takes 3 steps:
10965 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10966 // narrowing and commutation of operands should be handled.
10967 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10969 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10970 // so the shuffle can be broken into other shuffles and the legalizer can
10971 // try the lowering again.
10973 // The general idea is that no vector_shuffle operation should be left to
10974 // be matched during isel, all of them must be converted to a target specific
10977 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10978 // narrowing and commutation of operands should be handled. The actual code
10979 // doesn't include all of those, work in progress...
10980 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10981 if (NewOp.getNode())
10984 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10986 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10987 // unpckh_undef). Only use pshufd if speed is more important than size.
10988 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10989 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10990 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10991 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10993 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10994 V2IsUndef && MayFoldVectorLoad(V1))
10995 return getMOVDDup(Op, dl, V1, DAG);
10997 if (isMOVHLPS_v_undef_Mask(M, VT))
10998 return getMOVHighToLow(Op, dl, DAG);
11000 // Use to match splats
11001 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11002 (VT == MVT::v2f64 || VT == MVT::v2i64))
11003 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11005 if (isPSHUFDMask(M, VT)) {
11006 // The actual implementation will match the mask in the if above and then
11007 // during isel it can match several different instructions, not only pshufd
11008 // as its name says, sad but true, emulate the behavior for now...
11009 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11010 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11012 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11014 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11015 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11017 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11018 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11021 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11025 if (isPALIGNRMask(M, VT, Subtarget))
11026 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11027 getShufflePALIGNRImmediate(SVOp),
11030 if (isVALIGNMask(M, VT, Subtarget))
11031 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11032 getShuffleVALIGNImmediate(SVOp),
11035 // Check if this can be converted into a logical shift.
11036 bool isLeft = false;
11037 unsigned ShAmt = 0;
11039 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11040 if (isShift && ShVal.hasOneUse()) {
11041 // If the shifted value has multiple uses, it may be cheaper to use
11042 // v_set0 + movlhps or movhlps, etc.
11043 MVT EltVT = VT.getVectorElementType();
11044 ShAmt *= EltVT.getSizeInBits();
11045 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11048 if (isMOVLMask(M, VT)) {
11049 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11050 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11051 if (!isMOVLPMask(M, VT)) {
11052 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11053 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11055 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11056 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11060 // FIXME: fold these into legal mask.
11061 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11062 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11064 if (isMOVHLPSMask(M, VT))
11065 return getMOVHighToLow(Op, dl, DAG);
11067 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11068 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11070 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11071 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11073 if (isMOVLPMask(M, VT))
11074 return getMOVLP(Op, dl, DAG, HasSSE2);
11076 if (ShouldXformToMOVHLPS(M, VT) ||
11077 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11078 return DAG.getCommutedVectorShuffle(*SVOp);
11081 // No better options. Use a vshldq / vsrldq.
11082 MVT EltVT = VT.getVectorElementType();
11083 ShAmt *= EltVT.getSizeInBits();
11084 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11087 bool Commuted = false;
11088 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11089 // 1,1,1,1 -> v8i16 though.
11090 BitVector UndefElements;
11091 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11092 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11094 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11095 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11098 // Canonicalize the splat or undef, if present, to be on the RHS.
11099 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11100 CommuteVectorShuffleMask(M, NumElems);
11102 std::swap(V1IsSplat, V2IsSplat);
11106 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11107 // Shuffling low element of v1 into undef, just return v1.
11110 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11111 // the instruction selector will not match, so get a canonical MOVL with
11112 // swapped operands to undo the commute.
11113 return getMOVL(DAG, dl, VT, V2, V1);
11116 if (isUNPCKLMask(M, VT, HasInt256))
11117 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11119 if (isUNPCKHMask(M, VT, HasInt256))
11120 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11123 // Normalize mask so all entries that point to V2 points to its first
11124 // element then try to match unpck{h|l} again. If match, return a
11125 // new vector_shuffle with the corrected mask.p
11126 SmallVector<int, 8> NewMask(M.begin(), M.end());
11127 NormalizeMask(NewMask, NumElems);
11128 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11129 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11130 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11131 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11135 // Commute is back and try unpck* again.
11136 // FIXME: this seems wrong.
11137 CommuteVectorShuffleMask(M, NumElems);
11139 std::swap(V1IsSplat, V2IsSplat);
11141 if (isUNPCKLMask(M, VT, HasInt256))
11142 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11144 if (isUNPCKHMask(M, VT, HasInt256))
11145 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11148 // Normalize the node to match x86 shuffle ops if needed
11149 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11150 return DAG.getCommutedVectorShuffle(*SVOp);
11152 // The checks below are all present in isShuffleMaskLegal, but they are
11153 // inlined here right now to enable us to directly emit target specific
11154 // nodes, and remove one by one until they don't return Op anymore.
11156 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11157 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11158 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11159 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11162 if (isPSHUFHWMask(M, VT, HasInt256))
11163 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11164 getShufflePSHUFHWImmediate(SVOp),
11167 if (isPSHUFLWMask(M, VT, HasInt256))
11168 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11169 getShufflePSHUFLWImmediate(SVOp),
11172 unsigned MaskValue;
11173 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11175 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11177 if (isSHUFPMask(M, VT))
11178 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11179 getShuffleSHUFImmediate(SVOp), DAG);
11181 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11182 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11183 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11184 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11186 //===--------------------------------------------------------------------===//
11187 // Generate target specific nodes for 128 or 256-bit shuffles only
11188 // supported in the AVX instruction set.
11191 // Handle VMOVDDUPY permutations
11192 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11193 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11195 // Handle VPERMILPS/D* permutations
11196 if (isVPERMILPMask(M, VT)) {
11197 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11198 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11199 getShuffleSHUFImmediate(SVOp), DAG);
11200 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11201 getShuffleSHUFImmediate(SVOp), DAG);
11205 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11206 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11207 Idx*(NumElems/2), DAG, dl);
11209 // Handle VPERM2F128/VPERM2I128 permutations
11210 if (isVPERM2X128Mask(M, VT, HasFp256))
11211 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11212 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11214 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11215 return getINSERTPS(SVOp, dl, DAG);
11218 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11219 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11221 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11222 VT.is512BitVector()) {
11223 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11224 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11225 SmallVector<SDValue, 16> permclMask;
11226 for (unsigned i = 0; i != NumElems; ++i) {
11227 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11230 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11232 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11233 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11234 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11235 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11236 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11239 //===--------------------------------------------------------------------===//
11240 // Since no target specific shuffle was selected for this generic one,
11241 // lower it into other known shuffles. FIXME: this isn't true yet, but
11242 // this is the plan.
11245 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11246 if (VT == MVT::v8i16) {
11247 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11248 if (NewOp.getNode())
11252 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11253 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11254 if (NewOp.getNode())
11258 if (VT == MVT::v16i8) {
11259 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11260 if (NewOp.getNode())
11264 if (VT == MVT::v32i8) {
11265 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11266 if (NewOp.getNode())
11270 // Handle all 128-bit wide vectors with 4 elements, and match them with
11271 // several different shuffle types.
11272 if (NumElems == 4 && VT.is128BitVector())
11273 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11275 // Handle general 256-bit shuffles
11276 if (VT.is256BitVector())
11277 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11282 // This function assumes its argument is a BUILD_VECTOR of constants or
11283 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11285 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11286 unsigned &MaskValue) {
11288 unsigned NumElems = BuildVector->getNumOperands();
11289 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11290 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11291 unsigned NumElemsInLane = NumElems / NumLanes;
11293 // Blend for v16i16 should be symetric for the both lanes.
11294 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11295 SDValue EltCond = BuildVector->getOperand(i);
11296 SDValue SndLaneEltCond =
11297 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11299 int Lane1Cond = -1, Lane2Cond = -1;
11300 if (isa<ConstantSDNode>(EltCond))
11301 Lane1Cond = !isZero(EltCond);
11302 if (isa<ConstantSDNode>(SndLaneEltCond))
11303 Lane2Cond = !isZero(SndLaneEltCond);
11305 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11306 // Lane1Cond != 0, means we want the first argument.
11307 // Lane1Cond == 0, means we want the second argument.
11308 // The encoding of this argument is 0 for the first argument, 1
11309 // for the second. Therefore, invert the condition.
11310 MaskValue |= !Lane1Cond << i;
11311 else if (Lane1Cond < 0)
11312 MaskValue |= !Lane2Cond << i;
11319 // Try to lower a vselect node into a simple blend instruction.
11320 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11321 SelectionDAG &DAG) {
11322 SDValue Cond = Op.getOperand(0);
11323 SDValue LHS = Op.getOperand(1);
11324 SDValue RHS = Op.getOperand(2);
11326 MVT VT = Op.getSimpleValueType();
11327 MVT EltVT = VT.getVectorElementType();
11328 unsigned NumElems = VT.getVectorNumElements();
11330 // There is no blend with immediate in AVX-512.
11331 if (VT.is512BitVector())
11334 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11336 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11339 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11342 // Check the mask for BLEND and build the value.
11343 unsigned MaskValue = 0;
11344 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11347 // Convert i32 vectors to floating point if it is not AVX2.
11348 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11350 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11351 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11353 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11354 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11357 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11358 DAG.getConstant(MaskValue, MVT::i32));
11359 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11362 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11363 // A vselect where all conditions and data are constants can be optimized into
11364 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11365 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11366 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11367 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11370 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11371 if (BlendOp.getNode())
11374 // Some types for vselect were previously set to Expand, not Legal or
11375 // Custom. Return an empty SDValue so we fall-through to Expand, after
11376 // the Custom lowering phase.
11377 MVT VT = Op.getSimpleValueType();
11378 switch (VT.SimpleTy) {
11383 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11388 // We couldn't create a "Blend with immediate" node.
11389 // This node should still be legal, but we'll have to emit a blendv*
11394 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11395 MVT VT = Op.getSimpleValueType();
11398 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11401 if (VT.getSizeInBits() == 8) {
11402 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11403 Op.getOperand(0), Op.getOperand(1));
11404 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11405 DAG.getValueType(VT));
11406 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11409 if (VT.getSizeInBits() == 16) {
11410 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11411 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11413 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11414 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11415 DAG.getNode(ISD::BITCAST, dl,
11418 Op.getOperand(1)));
11419 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11420 Op.getOperand(0), Op.getOperand(1));
11421 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11422 DAG.getValueType(VT));
11423 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11426 if (VT == MVT::f32) {
11427 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11428 // the result back to FR32 register. It's only worth matching if the
11429 // result has a single use which is a store or a bitcast to i32. And in
11430 // the case of a store, it's not worth it if the index is a constant 0,
11431 // because a MOVSSmr can be used instead, which is smaller and faster.
11432 if (!Op.hasOneUse())
11434 SDNode *User = *Op.getNode()->use_begin();
11435 if ((User->getOpcode() != ISD::STORE ||
11436 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11437 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11438 (User->getOpcode() != ISD::BITCAST ||
11439 User->getValueType(0) != MVT::i32))
11441 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11442 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11445 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11448 if (VT == MVT::i32 || VT == MVT::i64) {
11449 // ExtractPS/pextrq works with constant index.
11450 if (isa<ConstantSDNode>(Op.getOperand(1)))
11456 /// Extract one bit from mask vector, like v16i1 or v8i1.
11457 /// AVX-512 feature.
11459 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11460 SDValue Vec = Op.getOperand(0);
11462 MVT VecVT = Vec.getSimpleValueType();
11463 SDValue Idx = Op.getOperand(1);
11464 MVT EltVT = Op.getSimpleValueType();
11466 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11468 // variable index can't be handled in mask registers,
11469 // extend vector to VR512
11470 if (!isa<ConstantSDNode>(Idx)) {
11471 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11472 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11473 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11474 ExtVT.getVectorElementType(), Ext, Idx);
11475 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11478 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11479 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11480 unsigned MaxSift = rc->getSize()*8 - 1;
11481 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11482 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11483 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11484 DAG.getConstant(MaxSift, MVT::i8));
11485 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11486 DAG.getIntPtrConstant(0));
11490 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11491 SelectionDAG &DAG) const {
11493 SDValue Vec = Op.getOperand(0);
11494 MVT VecVT = Vec.getSimpleValueType();
11495 SDValue Idx = Op.getOperand(1);
11497 if (Op.getSimpleValueType() == MVT::i1)
11498 return ExtractBitFromMaskVector(Op, DAG);
11500 if (!isa<ConstantSDNode>(Idx)) {
11501 if (VecVT.is512BitVector() ||
11502 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11503 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11506 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11507 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11508 MaskEltVT.getSizeInBits());
11510 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11511 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11512 getZeroVector(MaskVT, Subtarget, DAG, dl),
11513 Idx, DAG.getConstant(0, getPointerTy()));
11514 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11515 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11516 Perm, DAG.getConstant(0, getPointerTy()));
11521 // If this is a 256-bit vector result, first extract the 128-bit vector and
11522 // then extract the element from the 128-bit vector.
11523 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11525 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11526 // Get the 128-bit vector.
11527 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11528 MVT EltVT = VecVT.getVectorElementType();
11530 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11532 //if (IdxVal >= NumElems/2)
11533 // IdxVal -= NumElems/2;
11534 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11535 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11536 DAG.getConstant(IdxVal, MVT::i32));
11539 assert(VecVT.is128BitVector() && "Unexpected vector length");
11541 if (Subtarget->hasSSE41()) {
11542 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11547 MVT VT = Op.getSimpleValueType();
11548 // TODO: handle v16i8.
11549 if (VT.getSizeInBits() == 16) {
11550 SDValue Vec = Op.getOperand(0);
11551 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11553 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11554 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11555 DAG.getNode(ISD::BITCAST, dl,
11557 Op.getOperand(1)));
11558 // Transform it so it match pextrw which produces a 32-bit result.
11559 MVT EltVT = MVT::i32;
11560 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11561 Op.getOperand(0), Op.getOperand(1));
11562 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11563 DAG.getValueType(VT));
11564 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11567 if (VT.getSizeInBits() == 32) {
11568 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11572 // SHUFPS the element to the lowest double word, then movss.
11573 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11574 MVT VVT = Op.getOperand(0).getSimpleValueType();
11575 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11576 DAG.getUNDEF(VVT), Mask);
11577 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11578 DAG.getIntPtrConstant(0));
11581 if (VT.getSizeInBits() == 64) {
11582 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11583 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11584 // to match extract_elt for f64.
11585 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11589 // UNPCKHPD the element to the lowest double word, then movsd.
11590 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11591 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11592 int Mask[2] = { 1, -1 };
11593 MVT VVT = Op.getOperand(0).getSimpleValueType();
11594 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11595 DAG.getUNDEF(VVT), Mask);
11596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11597 DAG.getIntPtrConstant(0));
11603 /// Insert one bit to mask vector, like v16i1 or v8i1.
11604 /// AVX-512 feature.
11606 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11608 SDValue Vec = Op.getOperand(0);
11609 SDValue Elt = Op.getOperand(1);
11610 SDValue Idx = Op.getOperand(2);
11611 MVT VecVT = Vec.getSimpleValueType();
11613 if (!isa<ConstantSDNode>(Idx)) {
11614 // Non constant index. Extend source and destination,
11615 // insert element and then truncate the result.
11616 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11617 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11618 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11619 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11620 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11621 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11624 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11625 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11626 if (Vec.getOpcode() == ISD::UNDEF)
11627 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11628 DAG.getConstant(IdxVal, MVT::i8));
11629 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11630 unsigned MaxSift = rc->getSize()*8 - 1;
11631 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11632 DAG.getConstant(MaxSift, MVT::i8));
11633 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11634 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11635 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11638 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11639 SelectionDAG &DAG) const {
11640 MVT VT = Op.getSimpleValueType();
11641 MVT EltVT = VT.getVectorElementType();
11643 if (EltVT == MVT::i1)
11644 return InsertBitToMaskVector(Op, DAG);
11647 SDValue N0 = Op.getOperand(0);
11648 SDValue N1 = Op.getOperand(1);
11649 SDValue N2 = Op.getOperand(2);
11650 if (!isa<ConstantSDNode>(N2))
11652 auto *N2C = cast<ConstantSDNode>(N2);
11653 unsigned IdxVal = N2C->getZExtValue();
11655 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11656 // into that, and then insert the subvector back into the result.
11657 if (VT.is256BitVector() || VT.is512BitVector()) {
11658 // Get the desired 128-bit vector half.
11659 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11661 // Insert the element into the desired half.
11662 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11663 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11665 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11666 DAG.getConstant(IdxIn128, MVT::i32));
11668 // Insert the changed part back to the 256-bit vector
11669 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11671 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11673 if (Subtarget->hasSSE41()) {
11674 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11676 if (VT == MVT::v8i16) {
11677 Opc = X86ISD::PINSRW;
11679 assert(VT == MVT::v16i8);
11680 Opc = X86ISD::PINSRB;
11683 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11685 if (N1.getValueType() != MVT::i32)
11686 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11687 if (N2.getValueType() != MVT::i32)
11688 N2 = DAG.getIntPtrConstant(IdxVal);
11689 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11692 if (EltVT == MVT::f32) {
11693 // Bits [7:6] of the constant are the source select. This will always be
11694 // zero here. The DAG Combiner may combine an extract_elt index into
11696 // bits. For example (insert (extract, 3), 2) could be matched by
11698 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11699 // Bits [5:4] of the constant are the destination select. This is the
11700 // value of the incoming immediate.
11701 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11702 // combine either bitwise AND or insert of float 0.0 to set these bits.
11703 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11704 // Create this as a scalar to vector..
11705 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11706 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11709 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11710 // PINSR* works with constant index.
11715 if (EltVT == MVT::i8)
11718 if (EltVT.getSizeInBits() == 16) {
11719 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11720 // as its second argument.
11721 if (N1.getValueType() != MVT::i32)
11722 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11723 if (N2.getValueType() != MVT::i32)
11724 N2 = DAG.getIntPtrConstant(IdxVal);
11725 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11730 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11732 MVT OpVT = Op.getSimpleValueType();
11734 // If this is a 256-bit vector result, first insert into a 128-bit
11735 // vector and then insert into the 256-bit vector.
11736 if (!OpVT.is128BitVector()) {
11737 // Insert into a 128-bit vector.
11738 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11739 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11740 OpVT.getVectorNumElements() / SizeFactor);
11742 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11744 // Insert the 128-bit vector.
11745 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11748 if (OpVT == MVT::v1i64 &&
11749 Op.getOperand(0).getValueType() == MVT::i64)
11750 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11752 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11753 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11754 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11755 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11758 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11759 // a simple subregister reference or explicit instructions to grab
11760 // upper bits of a vector.
11761 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11762 SelectionDAG &DAG) {
11764 SDValue In = Op.getOperand(0);
11765 SDValue Idx = Op.getOperand(1);
11766 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11767 MVT ResVT = Op.getSimpleValueType();
11768 MVT InVT = In.getSimpleValueType();
11770 if (Subtarget->hasFp256()) {
11771 if (ResVT.is128BitVector() &&
11772 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11773 isa<ConstantSDNode>(Idx)) {
11774 return Extract128BitVector(In, IdxVal, DAG, dl);
11776 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11777 isa<ConstantSDNode>(Idx)) {
11778 return Extract256BitVector(In, IdxVal, DAG, dl);
11784 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11785 // simple superregister reference or explicit instructions to insert
11786 // the upper bits of a vector.
11787 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11788 SelectionDAG &DAG) {
11789 if (Subtarget->hasFp256()) {
11790 SDLoc dl(Op.getNode());
11791 SDValue Vec = Op.getNode()->getOperand(0);
11792 SDValue SubVec = Op.getNode()->getOperand(1);
11793 SDValue Idx = Op.getNode()->getOperand(2);
11795 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11796 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11797 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11798 isa<ConstantSDNode>(Idx)) {
11799 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11800 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11803 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11804 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11805 isa<ConstantSDNode>(Idx)) {
11806 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11807 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11813 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11814 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11815 // one of the above mentioned nodes. It has to be wrapped because otherwise
11816 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11817 // be used to form addressing mode. These wrapped nodes will be selected
11820 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11821 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11823 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11824 // global base reg.
11825 unsigned char OpFlag = 0;
11826 unsigned WrapperKind = X86ISD::Wrapper;
11827 CodeModel::Model M = DAG.getTarget().getCodeModel();
11829 if (Subtarget->isPICStyleRIPRel() &&
11830 (M == CodeModel::Small || M == CodeModel::Kernel))
11831 WrapperKind = X86ISD::WrapperRIP;
11832 else if (Subtarget->isPICStyleGOT())
11833 OpFlag = X86II::MO_GOTOFF;
11834 else if (Subtarget->isPICStyleStubPIC())
11835 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11837 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11838 CP->getAlignment(),
11839 CP->getOffset(), OpFlag);
11841 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11842 // With PIC, the address is actually $g + Offset.
11844 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11845 DAG.getNode(X86ISD::GlobalBaseReg,
11846 SDLoc(), getPointerTy()),
11853 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11854 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11856 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11857 // global base reg.
11858 unsigned char OpFlag = 0;
11859 unsigned WrapperKind = X86ISD::Wrapper;
11860 CodeModel::Model M = DAG.getTarget().getCodeModel();
11862 if (Subtarget->isPICStyleRIPRel() &&
11863 (M == CodeModel::Small || M == CodeModel::Kernel))
11864 WrapperKind = X86ISD::WrapperRIP;
11865 else if (Subtarget->isPICStyleGOT())
11866 OpFlag = X86II::MO_GOTOFF;
11867 else if (Subtarget->isPICStyleStubPIC())
11868 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11870 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11873 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11875 // With PIC, the address is actually $g + Offset.
11877 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11878 DAG.getNode(X86ISD::GlobalBaseReg,
11879 SDLoc(), getPointerTy()),
11886 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11887 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11889 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11890 // global base reg.
11891 unsigned char OpFlag = 0;
11892 unsigned WrapperKind = X86ISD::Wrapper;
11893 CodeModel::Model M = DAG.getTarget().getCodeModel();
11895 if (Subtarget->isPICStyleRIPRel() &&
11896 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11897 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11898 OpFlag = X86II::MO_GOTPCREL;
11899 WrapperKind = X86ISD::WrapperRIP;
11900 } else if (Subtarget->isPICStyleGOT()) {
11901 OpFlag = X86II::MO_GOT;
11902 } else if (Subtarget->isPICStyleStubPIC()) {
11903 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11904 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11905 OpFlag = X86II::MO_DARWIN_NONLAZY;
11908 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11911 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11913 // With PIC, the address is actually $g + Offset.
11914 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11915 !Subtarget->is64Bit()) {
11916 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11917 DAG.getNode(X86ISD::GlobalBaseReg,
11918 SDLoc(), getPointerTy()),
11922 // For symbols that require a load from a stub to get the address, emit the
11924 if (isGlobalStubReference(OpFlag))
11925 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11926 MachinePointerInfo::getGOT(), false, false, false, 0);
11932 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11933 // Create the TargetBlockAddressAddress node.
11934 unsigned char OpFlags =
11935 Subtarget->ClassifyBlockAddressReference();
11936 CodeModel::Model M = DAG.getTarget().getCodeModel();
11937 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11938 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11940 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11943 if (Subtarget->isPICStyleRIPRel() &&
11944 (M == CodeModel::Small || M == CodeModel::Kernel))
11945 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11947 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11949 // With PIC, the address is actually $g + Offset.
11950 if (isGlobalRelativeToPICBase(OpFlags)) {
11951 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11952 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11960 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11961 int64_t Offset, SelectionDAG &DAG) const {
11962 // Create the TargetGlobalAddress node, folding in the constant
11963 // offset if it is legal.
11964 unsigned char OpFlags =
11965 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11966 CodeModel::Model M = DAG.getTarget().getCodeModel();
11968 if (OpFlags == X86II::MO_NO_FLAG &&
11969 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11970 // A direct static reference to a global.
11971 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11974 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11977 if (Subtarget->isPICStyleRIPRel() &&
11978 (M == CodeModel::Small || M == CodeModel::Kernel))
11979 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11981 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11983 // With PIC, the address is actually $g + Offset.
11984 if (isGlobalRelativeToPICBase(OpFlags)) {
11985 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11986 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11990 // For globals that require a load from a stub to get the address, emit the
11992 if (isGlobalStubReference(OpFlags))
11993 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11994 MachinePointerInfo::getGOT(), false, false, false, 0);
11996 // If there was a non-zero offset that we didn't fold, create an explicit
11997 // addition for it.
11999 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12000 DAG.getConstant(Offset, getPointerTy()));
12006 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12007 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12008 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12009 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12013 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12014 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12015 unsigned char OperandFlags, bool LocalDynamic = false) {
12016 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12017 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12019 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12020 GA->getValueType(0),
12024 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12028 SDValue Ops[] = { Chain, TGA, *InFlag };
12029 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12031 SDValue Ops[] = { Chain, TGA };
12032 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12035 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12036 MFI->setAdjustsStack(true);
12038 SDValue Flag = Chain.getValue(1);
12039 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12042 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12044 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12047 SDLoc dl(GA); // ? function entry point might be better
12048 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12049 DAG.getNode(X86ISD::GlobalBaseReg,
12050 SDLoc(), PtrVT), InFlag);
12051 InFlag = Chain.getValue(1);
12053 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12056 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12058 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12060 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12061 X86::RAX, X86II::MO_TLSGD);
12064 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12070 // Get the start address of the TLS block for this module.
12071 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12072 .getInfo<X86MachineFunctionInfo>();
12073 MFI->incNumLocalDynamicTLSAccesses();
12077 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12078 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12081 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12082 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12083 InFlag = Chain.getValue(1);
12084 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12085 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12088 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12092 unsigned char OperandFlags = X86II::MO_DTPOFF;
12093 unsigned WrapperKind = X86ISD::Wrapper;
12094 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12095 GA->getValueType(0),
12096 GA->getOffset(), OperandFlags);
12097 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12099 // Add x@dtpoff with the base.
12100 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12103 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12104 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12105 const EVT PtrVT, TLSModel::Model model,
12106 bool is64Bit, bool isPIC) {
12109 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12110 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12111 is64Bit ? 257 : 256));
12113 SDValue ThreadPointer =
12114 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12115 MachinePointerInfo(Ptr), false, false, false, 0);
12117 unsigned char OperandFlags = 0;
12118 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12120 unsigned WrapperKind = X86ISD::Wrapper;
12121 if (model == TLSModel::LocalExec) {
12122 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12123 } else if (model == TLSModel::InitialExec) {
12125 OperandFlags = X86II::MO_GOTTPOFF;
12126 WrapperKind = X86ISD::WrapperRIP;
12128 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12131 llvm_unreachable("Unexpected model");
12134 // emit "addl x@ntpoff,%eax" (local exec)
12135 // or "addl x@indntpoff,%eax" (initial exec)
12136 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12138 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12139 GA->getOffset(), OperandFlags);
12140 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12142 if (model == TLSModel::InitialExec) {
12143 if (isPIC && !is64Bit) {
12144 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12145 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12149 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12150 MachinePointerInfo::getGOT(), false, false, false, 0);
12153 // The address of the thread local variable is the add of the thread
12154 // pointer with the offset of the variable.
12155 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12159 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12161 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12162 const GlobalValue *GV = GA->getGlobal();
12164 if (Subtarget->isTargetELF()) {
12165 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12168 case TLSModel::GeneralDynamic:
12169 if (Subtarget->is64Bit())
12170 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12171 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12172 case TLSModel::LocalDynamic:
12173 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12174 Subtarget->is64Bit());
12175 case TLSModel::InitialExec:
12176 case TLSModel::LocalExec:
12177 return LowerToTLSExecModel(
12178 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12179 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12181 llvm_unreachable("Unknown TLS model.");
12184 if (Subtarget->isTargetDarwin()) {
12185 // Darwin only has one model of TLS. Lower to that.
12186 unsigned char OpFlag = 0;
12187 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12188 X86ISD::WrapperRIP : X86ISD::Wrapper;
12190 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12191 // global base reg.
12192 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12193 !Subtarget->is64Bit();
12195 OpFlag = X86II::MO_TLVP_PIC_BASE;
12197 OpFlag = X86II::MO_TLVP;
12199 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12200 GA->getValueType(0),
12201 GA->getOffset(), OpFlag);
12202 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12204 // With PIC32, the address is actually $g + Offset.
12206 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12207 DAG.getNode(X86ISD::GlobalBaseReg,
12208 SDLoc(), getPointerTy()),
12211 // Lowering the machine isd will make sure everything is in the right
12213 SDValue Chain = DAG.getEntryNode();
12214 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12215 SDValue Args[] = { Chain, Offset };
12216 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12218 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12219 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12220 MFI->setAdjustsStack(true);
12222 // And our return value (tls address) is in the standard call return value
12224 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12225 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12226 Chain.getValue(1));
12229 if (Subtarget->isTargetKnownWindowsMSVC() ||
12230 Subtarget->isTargetWindowsGNU()) {
12231 // Just use the implicit TLS architecture
12232 // Need to generate someting similar to:
12233 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12235 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12236 // mov rcx, qword [rdx+rcx*8]
12237 // mov eax, .tls$:tlsvar
12238 // [rax+rcx] contains the address
12239 // Windows 64bit: gs:0x58
12240 // Windows 32bit: fs:__tls_array
12243 SDValue Chain = DAG.getEntryNode();
12245 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12246 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12247 // use its literal value of 0x2C.
12248 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12249 ? Type::getInt8PtrTy(*DAG.getContext(),
12251 : Type::getInt32PtrTy(*DAG.getContext(),
12255 Subtarget->is64Bit()
12256 ? DAG.getIntPtrConstant(0x58)
12257 : (Subtarget->isTargetWindowsGNU()
12258 ? DAG.getIntPtrConstant(0x2C)
12259 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12261 SDValue ThreadPointer =
12262 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12263 MachinePointerInfo(Ptr), false, false, false, 0);
12265 // Load the _tls_index variable
12266 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12267 if (Subtarget->is64Bit())
12268 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12269 IDX, MachinePointerInfo(), MVT::i32,
12270 false, false, false, 0);
12272 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12273 false, false, false, 0);
12275 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12277 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12279 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12280 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12281 false, false, false, 0);
12283 // Get the offset of start of .tls section
12284 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12285 GA->getValueType(0),
12286 GA->getOffset(), X86II::MO_SECREL);
12287 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12289 // The address of the thread local variable is the add of the thread
12290 // pointer with the offset of the variable.
12291 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12294 llvm_unreachable("TLS not implemented for this target.");
12297 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12298 /// and take a 2 x i32 value to shift plus a shift amount.
12299 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12300 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12301 MVT VT = Op.getSimpleValueType();
12302 unsigned VTBits = VT.getSizeInBits();
12304 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12305 SDValue ShOpLo = Op.getOperand(0);
12306 SDValue ShOpHi = Op.getOperand(1);
12307 SDValue ShAmt = Op.getOperand(2);
12308 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12309 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12311 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12312 DAG.getConstant(VTBits - 1, MVT::i8));
12313 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12314 DAG.getConstant(VTBits - 1, MVT::i8))
12315 : DAG.getConstant(0, VT);
12317 SDValue Tmp2, Tmp3;
12318 if (Op.getOpcode() == ISD::SHL_PARTS) {
12319 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12320 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12322 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12323 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12326 // If the shift amount is larger or equal than the width of a part we can't
12327 // rely on the results of shld/shrd. Insert a test and select the appropriate
12328 // values for large shift amounts.
12329 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12330 DAG.getConstant(VTBits, MVT::i8));
12331 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12332 AndNode, DAG.getConstant(0, MVT::i8));
12335 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12336 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12337 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12339 if (Op.getOpcode() == ISD::SHL_PARTS) {
12340 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12341 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12343 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12344 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12347 SDValue Ops[2] = { Lo, Hi };
12348 return DAG.getMergeValues(Ops, dl);
12351 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12352 SelectionDAG &DAG) const {
12353 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12355 if (SrcVT.isVector())
12358 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12359 "Unknown SINT_TO_FP to lower!");
12361 // These are really Legal; return the operand so the caller accepts it as
12363 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12365 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12366 Subtarget->is64Bit()) {
12371 unsigned Size = SrcVT.getSizeInBits()/8;
12372 MachineFunction &MF = DAG.getMachineFunction();
12373 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12374 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12375 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12377 MachinePointerInfo::getFixedStack(SSFI),
12379 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12382 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12384 SelectionDAG &DAG) const {
12388 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12390 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12392 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12394 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12396 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12397 MachineMemOperand *MMO;
12399 int SSFI = FI->getIndex();
12401 DAG.getMachineFunction()
12402 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12403 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12405 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12406 StackSlot = StackSlot.getOperand(1);
12408 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12409 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12411 Tys, Ops, SrcVT, MMO);
12414 Chain = Result.getValue(1);
12415 SDValue InFlag = Result.getValue(2);
12417 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12418 // shouldn't be necessary except that RFP cannot be live across
12419 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12420 MachineFunction &MF = DAG.getMachineFunction();
12421 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12422 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12423 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12424 Tys = DAG.getVTList(MVT::Other);
12426 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12428 MachineMemOperand *MMO =
12429 DAG.getMachineFunction()
12430 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12431 MachineMemOperand::MOStore, SSFISize, SSFISize);
12433 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12434 Ops, Op.getValueType(), MMO);
12435 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12436 MachinePointerInfo::getFixedStack(SSFI),
12437 false, false, false, 0);
12443 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12444 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12445 SelectionDAG &DAG) const {
12446 // This algorithm is not obvious. Here it is what we're trying to output:
12449 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12450 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12452 haddpd %xmm0, %xmm0
12454 pshufd $0x4e, %xmm0, %xmm1
12460 LLVMContext *Context = DAG.getContext();
12462 // Build some magic constants.
12463 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12464 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12465 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12467 SmallVector<Constant*,2> CV1;
12469 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12470 APInt(64, 0x4330000000000000ULL))));
12472 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12473 APInt(64, 0x4530000000000000ULL))));
12474 Constant *C1 = ConstantVector::get(CV1);
12475 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12477 // Load the 64-bit value into an XMM register.
12478 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12480 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12481 MachinePointerInfo::getConstantPool(),
12482 false, false, false, 16);
12483 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12484 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12487 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12488 MachinePointerInfo::getConstantPool(),
12489 false, false, false, 16);
12490 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12491 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12494 if (Subtarget->hasSSE3()) {
12495 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12496 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12498 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12499 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12501 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12502 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12506 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12507 DAG.getIntPtrConstant(0));
12510 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12511 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12512 SelectionDAG &DAG) const {
12514 // FP constant to bias correct the final result.
12515 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12518 // Load the 32-bit value into an XMM register.
12519 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12522 // Zero out the upper parts of the register.
12523 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12525 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12526 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12527 DAG.getIntPtrConstant(0));
12529 // Or the load with the bias.
12530 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12531 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12532 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12533 MVT::v2f64, Load)),
12534 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12535 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12536 MVT::v2f64, Bias)));
12537 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12538 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12539 DAG.getIntPtrConstant(0));
12541 // Subtract the bias.
12542 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12544 // Handle final rounding.
12545 EVT DestVT = Op.getValueType();
12547 if (DestVT.bitsLT(MVT::f64))
12548 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12549 DAG.getIntPtrConstant(0));
12550 if (DestVT.bitsGT(MVT::f64))
12551 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12553 // Handle final rounding.
12557 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12558 SelectionDAG &DAG) const {
12559 SDValue N0 = Op.getOperand(0);
12560 MVT SVT = N0.getSimpleValueType();
12563 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12564 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12565 "Custom UINT_TO_FP is not supported!");
12567 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12568 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12569 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12572 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12573 SelectionDAG &DAG) const {
12574 SDValue N0 = Op.getOperand(0);
12577 if (Op.getValueType().isVector())
12578 return lowerUINT_TO_FP_vec(Op, DAG);
12580 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12581 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12582 // the optimization here.
12583 if (DAG.SignBitIsZero(N0))
12584 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12586 MVT SrcVT = N0.getSimpleValueType();
12587 MVT DstVT = Op.getSimpleValueType();
12588 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12589 return LowerUINT_TO_FP_i64(Op, DAG);
12590 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12591 return LowerUINT_TO_FP_i32(Op, DAG);
12592 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12595 // Make a 64-bit buffer, and use it to build an FILD.
12596 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12597 if (SrcVT == MVT::i32) {
12598 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12599 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12600 getPointerTy(), StackSlot, WordOff);
12601 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12602 StackSlot, MachinePointerInfo(),
12604 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12605 OffsetSlot, MachinePointerInfo(),
12607 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12611 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12612 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12613 StackSlot, MachinePointerInfo(),
12615 // For i64 source, we need to add the appropriate power of 2 if the input
12616 // was negative. This is the same as the optimization in
12617 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12618 // we must be careful to do the computation in x87 extended precision, not
12619 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12620 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12621 MachineMemOperand *MMO =
12622 DAG.getMachineFunction()
12623 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12624 MachineMemOperand::MOLoad, 8, 8);
12626 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12627 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12628 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12631 APInt FF(32, 0x5F800000ULL);
12633 // Check whether the sign bit is set.
12634 SDValue SignSet = DAG.getSetCC(dl,
12635 getSetCCResultType(*DAG.getContext(), MVT::i64),
12636 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12639 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12640 SDValue FudgePtr = DAG.getConstantPool(
12641 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12644 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12645 SDValue Zero = DAG.getIntPtrConstant(0);
12646 SDValue Four = DAG.getIntPtrConstant(4);
12647 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12649 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12651 // Load the value out, extending it from f32 to f80.
12652 // FIXME: Avoid the extend by constructing the right constant pool?
12653 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12654 FudgePtr, MachinePointerInfo::getConstantPool(),
12655 MVT::f32, false, false, false, 4);
12656 // Extend everything to 80 bits to force it to be done on x87.
12657 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12658 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12661 std::pair<SDValue,SDValue>
12662 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12663 bool IsSigned, bool IsReplace) const {
12666 EVT DstTy = Op.getValueType();
12668 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12669 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12673 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12674 DstTy.getSimpleVT() >= MVT::i16 &&
12675 "Unknown FP_TO_INT to lower!");
12677 // These are really Legal.
12678 if (DstTy == MVT::i32 &&
12679 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12680 return std::make_pair(SDValue(), SDValue());
12681 if (Subtarget->is64Bit() &&
12682 DstTy == MVT::i64 &&
12683 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12684 return std::make_pair(SDValue(), SDValue());
12686 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12687 // stack slot, or into the FTOL runtime function.
12688 MachineFunction &MF = DAG.getMachineFunction();
12689 unsigned MemSize = DstTy.getSizeInBits()/8;
12690 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12691 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12694 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12695 Opc = X86ISD::WIN_FTOL;
12697 switch (DstTy.getSimpleVT().SimpleTy) {
12698 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12699 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12700 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12701 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12704 SDValue Chain = DAG.getEntryNode();
12705 SDValue Value = Op.getOperand(0);
12706 EVT TheVT = Op.getOperand(0).getValueType();
12707 // FIXME This causes a redundant load/store if the SSE-class value is already
12708 // in memory, such as if it is on the callstack.
12709 if (isScalarFPTypeInSSEReg(TheVT)) {
12710 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12711 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12712 MachinePointerInfo::getFixedStack(SSFI),
12714 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12716 Chain, StackSlot, DAG.getValueType(TheVT)
12719 MachineMemOperand *MMO =
12720 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12721 MachineMemOperand::MOLoad, MemSize, MemSize);
12722 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12723 Chain = Value.getValue(1);
12724 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12725 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12728 MachineMemOperand *MMO =
12729 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12730 MachineMemOperand::MOStore, MemSize, MemSize);
12732 if (Opc != X86ISD::WIN_FTOL) {
12733 // Build the FP_TO_INT*_IN_MEM
12734 SDValue Ops[] = { Chain, Value, StackSlot };
12735 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12737 return std::make_pair(FIST, StackSlot);
12739 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12740 DAG.getVTList(MVT::Other, MVT::Glue),
12742 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12743 MVT::i32, ftol.getValue(1));
12744 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12745 MVT::i32, eax.getValue(2));
12746 SDValue Ops[] = { eax, edx };
12747 SDValue pair = IsReplace
12748 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12749 : DAG.getMergeValues(Ops, DL);
12750 return std::make_pair(pair, SDValue());
12754 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12755 const X86Subtarget *Subtarget) {
12756 MVT VT = Op->getSimpleValueType(0);
12757 SDValue In = Op->getOperand(0);
12758 MVT InVT = In.getSimpleValueType();
12761 // Optimize vectors in AVX mode:
12764 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12765 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12766 // Concat upper and lower parts.
12769 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12770 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12771 // Concat upper and lower parts.
12774 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12775 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12776 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12779 if (Subtarget->hasInt256())
12780 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12782 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12783 SDValue Undef = DAG.getUNDEF(InVT);
12784 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12785 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12786 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12788 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12789 VT.getVectorNumElements()/2);
12791 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12792 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12794 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12797 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12798 SelectionDAG &DAG) {
12799 MVT VT = Op->getSimpleValueType(0);
12800 SDValue In = Op->getOperand(0);
12801 MVT InVT = In.getSimpleValueType();
12803 unsigned int NumElts = VT.getVectorNumElements();
12804 if (NumElts != 8 && NumElts != 16)
12807 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12808 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12810 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12811 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12812 // Now we have only mask extension
12813 assert(InVT.getVectorElementType() == MVT::i1);
12814 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12815 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12816 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12817 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12818 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12819 MachinePointerInfo::getConstantPool(),
12820 false, false, false, Alignment);
12822 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12823 if (VT.is512BitVector())
12825 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12828 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12829 SelectionDAG &DAG) {
12830 if (Subtarget->hasFp256()) {
12831 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12839 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12840 SelectionDAG &DAG) {
12842 MVT VT = Op.getSimpleValueType();
12843 SDValue In = Op.getOperand(0);
12844 MVT SVT = In.getSimpleValueType();
12846 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12847 return LowerZERO_EXTEND_AVX512(Op, DAG);
12849 if (Subtarget->hasFp256()) {
12850 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12855 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12856 VT.getVectorNumElements() != SVT.getVectorNumElements());
12860 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12862 MVT VT = Op.getSimpleValueType();
12863 SDValue In = Op.getOperand(0);
12864 MVT InVT = In.getSimpleValueType();
12866 if (VT == MVT::i1) {
12867 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12868 "Invalid scalar TRUNCATE operation");
12869 if (InVT.getSizeInBits() >= 32)
12871 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12872 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12874 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12875 "Invalid TRUNCATE operation");
12877 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12878 if (VT.getVectorElementType().getSizeInBits() >=8)
12879 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12881 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12882 unsigned NumElts = InVT.getVectorNumElements();
12883 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12884 if (InVT.getSizeInBits() < 512) {
12885 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12886 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12890 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12891 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12892 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12893 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12894 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12895 MachinePointerInfo::getConstantPool(),
12896 false, false, false, Alignment);
12897 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12898 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12899 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12902 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12903 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12904 if (Subtarget->hasInt256()) {
12905 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12906 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12907 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12909 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12910 DAG.getIntPtrConstant(0));
12913 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12914 DAG.getIntPtrConstant(0));
12915 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12916 DAG.getIntPtrConstant(2));
12917 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12918 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12919 static const int ShufMask[] = {0, 2, 4, 6};
12920 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12923 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12924 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12925 if (Subtarget->hasInt256()) {
12926 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12928 SmallVector<SDValue,32> pshufbMask;
12929 for (unsigned i = 0; i < 2; ++i) {
12930 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12931 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12932 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12933 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12934 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12935 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12936 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12937 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12938 for (unsigned j = 0; j < 8; ++j)
12939 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12941 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12942 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12943 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12945 static const int ShufMask[] = {0, 2, -1, -1};
12946 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12948 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12949 DAG.getIntPtrConstant(0));
12950 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12953 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12954 DAG.getIntPtrConstant(0));
12956 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12957 DAG.getIntPtrConstant(4));
12959 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12960 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12962 // The PSHUFB mask:
12963 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12964 -1, -1, -1, -1, -1, -1, -1, -1};
12966 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12967 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12968 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12970 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12971 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12973 // The MOVLHPS Mask:
12974 static const int ShufMask2[] = {0, 1, 4, 5};
12975 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12976 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12979 // Handle truncation of V256 to V128 using shuffles.
12980 if (!VT.is128BitVector() || !InVT.is256BitVector())
12983 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12985 unsigned NumElems = VT.getVectorNumElements();
12986 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12988 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12989 // Prepare truncation shuffle mask
12990 for (unsigned i = 0; i != NumElems; ++i)
12991 MaskVec[i] = i * 2;
12992 SDValue V = DAG.getVectorShuffle(NVT, DL,
12993 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12994 DAG.getUNDEF(NVT), &MaskVec[0]);
12995 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12996 DAG.getIntPtrConstant(0));
12999 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13000 SelectionDAG &DAG) const {
13001 assert(!Op.getSimpleValueType().isVector());
13003 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13004 /*IsSigned=*/ true, /*IsReplace=*/ false);
13005 SDValue FIST = Vals.first, StackSlot = Vals.second;
13006 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13007 if (!FIST.getNode()) return Op;
13009 if (StackSlot.getNode())
13010 // Load the result.
13011 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13012 FIST, StackSlot, MachinePointerInfo(),
13013 false, false, false, 0);
13015 // The node is the result.
13019 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13020 SelectionDAG &DAG) const {
13021 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13022 /*IsSigned=*/ false, /*IsReplace=*/ false);
13023 SDValue FIST = Vals.first, StackSlot = Vals.second;
13024 assert(FIST.getNode() && "Unexpected failure");
13026 if (StackSlot.getNode())
13027 // Load the result.
13028 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13029 FIST, StackSlot, MachinePointerInfo(),
13030 false, false, false, 0);
13032 // The node is the result.
13036 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13038 MVT VT = Op.getSimpleValueType();
13039 SDValue In = Op.getOperand(0);
13040 MVT SVT = In.getSimpleValueType();
13042 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13044 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13045 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13046 In, DAG.getUNDEF(SVT)));
13049 // The only differences between FABS and FNEG are the mask and the logic op.
13050 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13051 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13052 "Wrong opcode for lowering FABS or FNEG.");
13054 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13056 MVT VT = Op.getSimpleValueType();
13057 // Assume scalar op for initialization; update for vector if needed.
13058 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13059 // generate a 16-byte vector constant and logic op even for the scalar case.
13060 // Using a 16-byte mask allows folding the load of the mask with
13061 // the logic op, so it can save (~4 bytes) on code size.
13063 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13064 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13065 // decide if we should generate a 16-byte constant mask when we only need 4 or
13066 // 8 bytes for the scalar case.
13067 if (VT.isVector()) {
13068 EltVT = VT.getVectorElementType();
13069 NumElts = VT.getVectorNumElements();
13072 unsigned EltBits = EltVT.getSizeInBits();
13073 LLVMContext *Context = DAG.getContext();
13074 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13076 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13077 Constant *C = ConstantInt::get(*Context, MaskElt);
13078 C = ConstantVector::getSplat(NumElts, C);
13079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13080 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13081 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13082 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13083 MachinePointerInfo::getConstantPool(),
13084 false, false, false, Alignment);
13086 if (VT.isVector()) {
13087 // For a vector, cast operands to a vector type, perform the logic op,
13088 // and cast the result back to the original value type.
13089 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13090 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13091 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13092 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13093 return DAG.getNode(ISD::BITCAST, dl, VT,
13094 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13096 // If not vector, then scalar.
13097 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13098 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13101 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13102 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13103 LLVMContext *Context = DAG.getContext();
13104 SDValue Op0 = Op.getOperand(0);
13105 SDValue Op1 = Op.getOperand(1);
13107 MVT VT = Op.getSimpleValueType();
13108 MVT SrcVT = Op1.getSimpleValueType();
13110 // If second operand is smaller, extend it first.
13111 if (SrcVT.bitsLT(VT)) {
13112 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13115 // And if it is bigger, shrink it first.
13116 if (SrcVT.bitsGT(VT)) {
13117 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13121 // At this point the operands and the result should have the same
13122 // type, and that won't be f80 since that is not custom lowered.
13124 // First get the sign bit of second operand.
13125 SmallVector<Constant*,4> CV;
13126 if (SrcVT == MVT::f64) {
13127 const fltSemantics &Sem = APFloat::IEEEdouble;
13128 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13129 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13131 const fltSemantics &Sem = APFloat::IEEEsingle;
13132 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13133 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13134 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13135 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13137 Constant *C = ConstantVector::get(CV);
13138 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13139 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13140 MachinePointerInfo::getConstantPool(),
13141 false, false, false, 16);
13142 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13144 // Shift sign bit right or left if the two operands have different types.
13145 if (SrcVT.bitsGT(VT)) {
13146 // Op0 is MVT::f32, Op1 is MVT::f64.
13147 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13148 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13149 DAG.getConstant(32, MVT::i32));
13150 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13151 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13152 DAG.getIntPtrConstant(0));
13155 // Clear first operand sign bit.
13157 if (VT == MVT::f64) {
13158 const fltSemantics &Sem = APFloat::IEEEdouble;
13159 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13160 APInt(64, ~(1ULL << 63)))));
13161 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13163 const fltSemantics &Sem = APFloat::IEEEsingle;
13164 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13165 APInt(32, ~(1U << 31)))));
13166 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13167 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13168 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13170 C = ConstantVector::get(CV);
13171 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13172 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13173 MachinePointerInfo::getConstantPool(),
13174 false, false, false, 16);
13175 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13177 // Or the value with the sign bit.
13178 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13181 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13182 SDValue N0 = Op.getOperand(0);
13184 MVT VT = Op.getSimpleValueType();
13186 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13187 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13188 DAG.getConstant(1, VT));
13189 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13192 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13194 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13195 SelectionDAG &DAG) {
13196 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13198 if (!Subtarget->hasSSE41())
13201 if (!Op->hasOneUse())
13204 SDNode *N = Op.getNode();
13207 SmallVector<SDValue, 8> Opnds;
13208 DenseMap<SDValue, unsigned> VecInMap;
13209 SmallVector<SDValue, 8> VecIns;
13210 EVT VT = MVT::Other;
13212 // Recognize a special case where a vector is casted into wide integer to
13214 Opnds.push_back(N->getOperand(0));
13215 Opnds.push_back(N->getOperand(1));
13217 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13218 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13219 // BFS traverse all OR'd operands.
13220 if (I->getOpcode() == ISD::OR) {
13221 Opnds.push_back(I->getOperand(0));
13222 Opnds.push_back(I->getOperand(1));
13223 // Re-evaluate the number of nodes to be traversed.
13224 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13228 // Quit if a non-EXTRACT_VECTOR_ELT
13229 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13232 // Quit if without a constant index.
13233 SDValue Idx = I->getOperand(1);
13234 if (!isa<ConstantSDNode>(Idx))
13237 SDValue ExtractedFromVec = I->getOperand(0);
13238 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13239 if (M == VecInMap.end()) {
13240 VT = ExtractedFromVec.getValueType();
13241 // Quit if not 128/256-bit vector.
13242 if (!VT.is128BitVector() && !VT.is256BitVector())
13244 // Quit if not the same type.
13245 if (VecInMap.begin() != VecInMap.end() &&
13246 VT != VecInMap.begin()->first.getValueType())
13248 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13249 VecIns.push_back(ExtractedFromVec);
13251 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13254 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13255 "Not extracted from 128-/256-bit vector.");
13257 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13259 for (DenseMap<SDValue, unsigned>::const_iterator
13260 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13261 // Quit if not all elements are used.
13262 if (I->second != FullMask)
13266 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13268 // Cast all vectors into TestVT for PTEST.
13269 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13270 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13272 // If more than one full vectors are evaluated, OR them first before PTEST.
13273 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13274 // Each iteration will OR 2 nodes and append the result until there is only
13275 // 1 node left, i.e. the final OR'd value of all vectors.
13276 SDValue LHS = VecIns[Slot];
13277 SDValue RHS = VecIns[Slot + 1];
13278 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13281 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13282 VecIns.back(), VecIns.back());
13285 /// \brief return true if \c Op has a use that doesn't just read flags.
13286 static bool hasNonFlagsUse(SDValue Op) {
13287 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13289 SDNode *User = *UI;
13290 unsigned UOpNo = UI.getOperandNo();
13291 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13292 // Look pass truncate.
13293 UOpNo = User->use_begin().getOperandNo();
13294 User = *User->use_begin();
13297 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13298 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13304 /// Emit nodes that will be selected as "test Op0,Op0", or something
13306 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13307 SelectionDAG &DAG) const {
13308 if (Op.getValueType() == MVT::i1)
13309 // KORTEST instruction should be selected
13310 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13311 DAG.getConstant(0, Op.getValueType()));
13313 // CF and OF aren't always set the way we want. Determine which
13314 // of these we need.
13315 bool NeedCF = false;
13316 bool NeedOF = false;
13319 case X86::COND_A: case X86::COND_AE:
13320 case X86::COND_B: case X86::COND_BE:
13323 case X86::COND_G: case X86::COND_GE:
13324 case X86::COND_L: case X86::COND_LE:
13325 case X86::COND_O: case X86::COND_NO: {
13326 // Check if we really need to set the
13327 // Overflow flag. If NoSignedWrap is present
13328 // that is not actually needed.
13329 switch (Op->getOpcode()) {
13334 const BinaryWithFlagsSDNode *BinNode =
13335 cast<BinaryWithFlagsSDNode>(Op.getNode());
13336 if (BinNode->hasNoSignedWrap())
13346 // See if we can use the EFLAGS value from the operand instead of
13347 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13348 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13349 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13350 // Emit a CMP with 0, which is the TEST pattern.
13351 //if (Op.getValueType() == MVT::i1)
13352 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13353 // DAG.getConstant(0, MVT::i1));
13354 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13355 DAG.getConstant(0, Op.getValueType()));
13357 unsigned Opcode = 0;
13358 unsigned NumOperands = 0;
13360 // Truncate operations may prevent the merge of the SETCC instruction
13361 // and the arithmetic instruction before it. Attempt to truncate the operands
13362 // of the arithmetic instruction and use a reduced bit-width instruction.
13363 bool NeedTruncation = false;
13364 SDValue ArithOp = Op;
13365 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13366 SDValue Arith = Op->getOperand(0);
13367 // Both the trunc and the arithmetic op need to have one user each.
13368 if (Arith->hasOneUse())
13369 switch (Arith.getOpcode()) {
13376 NeedTruncation = true;
13382 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13383 // which may be the result of a CAST. We use the variable 'Op', which is the
13384 // non-casted variable when we check for possible users.
13385 switch (ArithOp.getOpcode()) {
13387 // Due to an isel shortcoming, be conservative if this add is likely to be
13388 // selected as part of a load-modify-store instruction. When the root node
13389 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13390 // uses of other nodes in the match, such as the ADD in this case. This
13391 // leads to the ADD being left around and reselected, with the result being
13392 // two adds in the output. Alas, even if none our users are stores, that
13393 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13394 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13395 // climbing the DAG back to the root, and it doesn't seem to be worth the
13397 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13398 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13399 if (UI->getOpcode() != ISD::CopyToReg &&
13400 UI->getOpcode() != ISD::SETCC &&
13401 UI->getOpcode() != ISD::STORE)
13404 if (ConstantSDNode *C =
13405 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13406 // An add of one will be selected as an INC.
13407 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13408 Opcode = X86ISD::INC;
13413 // An add of negative one (subtract of one) will be selected as a DEC.
13414 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13415 Opcode = X86ISD::DEC;
13421 // Otherwise use a regular EFLAGS-setting add.
13422 Opcode = X86ISD::ADD;
13427 // If we have a constant logical shift that's only used in a comparison
13428 // against zero turn it into an equivalent AND. This allows turning it into
13429 // a TEST instruction later.
13430 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13431 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13432 EVT VT = Op.getValueType();
13433 unsigned BitWidth = VT.getSizeInBits();
13434 unsigned ShAmt = Op->getConstantOperandVal(1);
13435 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13437 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13438 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13439 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13440 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13442 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13443 DAG.getConstant(Mask, VT));
13444 DAG.ReplaceAllUsesWith(Op, New);
13450 // If the primary and result isn't used, don't bother using X86ISD::AND,
13451 // because a TEST instruction will be better.
13452 if (!hasNonFlagsUse(Op))
13458 // Due to the ISEL shortcoming noted above, be conservative if this op is
13459 // likely to be selected as part of a load-modify-store instruction.
13460 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13461 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13462 if (UI->getOpcode() == ISD::STORE)
13465 // Otherwise use a regular EFLAGS-setting instruction.
13466 switch (ArithOp.getOpcode()) {
13467 default: llvm_unreachable("unexpected operator!");
13468 case ISD::SUB: Opcode = X86ISD::SUB; break;
13469 case ISD::XOR: Opcode = X86ISD::XOR; break;
13470 case ISD::AND: Opcode = X86ISD::AND; break;
13472 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13473 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13474 if (EFLAGS.getNode())
13477 Opcode = X86ISD::OR;
13491 return SDValue(Op.getNode(), 1);
13497 // If we found that truncation is beneficial, perform the truncation and
13499 if (NeedTruncation) {
13500 EVT VT = Op.getValueType();
13501 SDValue WideVal = Op->getOperand(0);
13502 EVT WideVT = WideVal.getValueType();
13503 unsigned ConvertedOp = 0;
13504 // Use a target machine opcode to prevent further DAGCombine
13505 // optimizations that may separate the arithmetic operations
13506 // from the setcc node.
13507 switch (WideVal.getOpcode()) {
13509 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13510 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13511 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13512 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13513 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13518 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13519 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13520 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13521 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13527 // Emit a CMP with 0, which is the TEST pattern.
13528 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13529 DAG.getConstant(0, Op.getValueType()));
13531 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13532 SmallVector<SDValue, 4> Ops;
13533 for (unsigned i = 0; i != NumOperands; ++i)
13534 Ops.push_back(Op.getOperand(i));
13536 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13537 DAG.ReplaceAllUsesWith(Op, New);
13538 return SDValue(New.getNode(), 1);
13541 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13543 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13544 SDLoc dl, SelectionDAG &DAG) const {
13545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13546 if (C->getAPIntValue() == 0)
13547 return EmitTest(Op0, X86CC, dl, DAG);
13549 if (Op0.getValueType() == MVT::i1)
13550 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13553 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13554 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13555 // Do the comparison at i32 if it's smaller, besides the Atom case.
13556 // This avoids subregister aliasing issues. Keep the smaller reference
13557 // if we're optimizing for size, however, as that'll allow better folding
13558 // of memory operations.
13559 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13560 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13561 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13562 !Subtarget->isAtom()) {
13563 unsigned ExtendOp =
13564 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13565 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13566 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13568 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13569 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13570 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13572 return SDValue(Sub.getNode(), 1);
13574 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13577 /// Convert a comparison if required by the subtarget.
13578 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13579 SelectionDAG &DAG) const {
13580 // If the subtarget does not support the FUCOMI instruction, floating-point
13581 // comparisons have to be converted.
13582 if (Subtarget->hasCMov() ||
13583 Cmp.getOpcode() != X86ISD::CMP ||
13584 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13585 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13588 // The instruction selector will select an FUCOM instruction instead of
13589 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13590 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13591 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13593 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13594 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13595 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13596 DAG.getConstant(8, MVT::i8));
13597 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13598 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13601 static bool isAllOnes(SDValue V) {
13602 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13603 return C && C->isAllOnesValue();
13606 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13607 /// if it's possible.
13608 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13609 SDLoc dl, SelectionDAG &DAG) const {
13610 SDValue Op0 = And.getOperand(0);
13611 SDValue Op1 = And.getOperand(1);
13612 if (Op0.getOpcode() == ISD::TRUNCATE)
13613 Op0 = Op0.getOperand(0);
13614 if (Op1.getOpcode() == ISD::TRUNCATE)
13615 Op1 = Op1.getOperand(0);
13618 if (Op1.getOpcode() == ISD::SHL)
13619 std::swap(Op0, Op1);
13620 if (Op0.getOpcode() == ISD::SHL) {
13621 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13622 if (And00C->getZExtValue() == 1) {
13623 // If we looked past a truncate, check that it's only truncating away
13625 unsigned BitWidth = Op0.getValueSizeInBits();
13626 unsigned AndBitWidth = And.getValueSizeInBits();
13627 if (BitWidth > AndBitWidth) {
13629 DAG.computeKnownBits(Op0, Zeros, Ones);
13630 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13634 RHS = Op0.getOperand(1);
13636 } else if (Op1.getOpcode() == ISD::Constant) {
13637 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13638 uint64_t AndRHSVal = AndRHS->getZExtValue();
13639 SDValue AndLHS = Op0;
13641 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13642 LHS = AndLHS.getOperand(0);
13643 RHS = AndLHS.getOperand(1);
13646 // Use BT if the immediate can't be encoded in a TEST instruction.
13647 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13649 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13653 if (LHS.getNode()) {
13654 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13655 // instruction. Since the shift amount is in-range-or-undefined, we know
13656 // that doing a bittest on the i32 value is ok. We extend to i32 because
13657 // the encoding for the i16 version is larger than the i32 version.
13658 // Also promote i16 to i32 for performance / code size reason.
13659 if (LHS.getValueType() == MVT::i8 ||
13660 LHS.getValueType() == MVT::i16)
13661 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13663 // If the operand types disagree, extend the shift amount to match. Since
13664 // BT ignores high bits (like shifts) we can use anyextend.
13665 if (LHS.getValueType() != RHS.getValueType())
13666 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13668 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13669 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13670 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13671 DAG.getConstant(Cond, MVT::i8), BT);
13677 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13679 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13684 // SSE Condition code mapping:
13693 switch (SetCCOpcode) {
13694 default: llvm_unreachable("Unexpected SETCC condition");
13696 case ISD::SETEQ: SSECC = 0; break;
13698 case ISD::SETGT: Swap = true; // Fallthrough
13700 case ISD::SETOLT: SSECC = 1; break;
13702 case ISD::SETGE: Swap = true; // Fallthrough
13704 case ISD::SETOLE: SSECC = 2; break;
13705 case ISD::SETUO: SSECC = 3; break;
13707 case ISD::SETNE: SSECC = 4; break;
13708 case ISD::SETULE: Swap = true; // Fallthrough
13709 case ISD::SETUGE: SSECC = 5; break;
13710 case ISD::SETULT: Swap = true; // Fallthrough
13711 case ISD::SETUGT: SSECC = 6; break;
13712 case ISD::SETO: SSECC = 7; break;
13714 case ISD::SETONE: SSECC = 8; break;
13717 std::swap(Op0, Op1);
13722 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13723 // ones, and then concatenate the result back.
13724 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13725 MVT VT = Op.getSimpleValueType();
13727 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13728 "Unsupported value type for operation");
13730 unsigned NumElems = VT.getVectorNumElements();
13732 SDValue CC = Op.getOperand(2);
13734 // Extract the LHS vectors
13735 SDValue LHS = Op.getOperand(0);
13736 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13737 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13739 // Extract the RHS vectors
13740 SDValue RHS = Op.getOperand(1);
13741 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13742 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13744 // Issue the operation on the smaller types and concatenate the result back
13745 MVT EltVT = VT.getVectorElementType();
13746 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13747 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13748 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13749 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13752 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13753 const X86Subtarget *Subtarget) {
13754 SDValue Op0 = Op.getOperand(0);
13755 SDValue Op1 = Op.getOperand(1);
13756 SDValue CC = Op.getOperand(2);
13757 MVT VT = Op.getSimpleValueType();
13760 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13761 Op.getValueType().getScalarType() == MVT::i1 &&
13762 "Cannot set masked compare for this operation");
13764 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13766 bool Unsigned = false;
13769 switch (SetCCOpcode) {
13770 default: llvm_unreachable("Unexpected SETCC condition");
13771 case ISD::SETNE: SSECC = 4; break;
13772 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13773 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13774 case ISD::SETLT: Swap = true; //fall-through
13775 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13776 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13777 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13778 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13779 case ISD::SETULE: Unsigned = true; //fall-through
13780 case ISD::SETLE: SSECC = 2; break;
13784 std::swap(Op0, Op1);
13786 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13787 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13788 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13789 DAG.getConstant(SSECC, MVT::i8));
13792 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13793 /// operand \p Op1. If non-trivial (for example because it's not constant)
13794 /// return an empty value.
13795 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13797 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13801 MVT VT = Op1.getSimpleValueType();
13802 MVT EVT = VT.getVectorElementType();
13803 unsigned n = VT.getVectorNumElements();
13804 SmallVector<SDValue, 8> ULTOp1;
13806 for (unsigned i = 0; i < n; ++i) {
13807 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13808 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13811 // Avoid underflow.
13812 APInt Val = Elt->getAPIntValue();
13816 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13819 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13822 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13823 SelectionDAG &DAG) {
13824 SDValue Op0 = Op.getOperand(0);
13825 SDValue Op1 = Op.getOperand(1);
13826 SDValue CC = Op.getOperand(2);
13827 MVT VT = Op.getSimpleValueType();
13828 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13829 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13834 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13835 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13838 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13839 unsigned Opc = X86ISD::CMPP;
13840 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13841 assert(VT.getVectorNumElements() <= 16);
13842 Opc = X86ISD::CMPM;
13844 // In the two special cases we can't handle, emit two comparisons.
13847 unsigned CombineOpc;
13848 if (SetCCOpcode == ISD::SETUEQ) {
13849 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13851 assert(SetCCOpcode == ISD::SETONE);
13852 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13855 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13856 DAG.getConstant(CC0, MVT::i8));
13857 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13858 DAG.getConstant(CC1, MVT::i8));
13859 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13861 // Handle all other FP comparisons here.
13862 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13863 DAG.getConstant(SSECC, MVT::i8));
13866 // Break 256-bit integer vector compare into smaller ones.
13867 if (VT.is256BitVector() && !Subtarget->hasInt256())
13868 return Lower256IntVSETCC(Op, DAG);
13870 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13871 EVT OpVT = Op1.getValueType();
13872 if (Subtarget->hasAVX512()) {
13873 if (Op1.getValueType().is512BitVector() ||
13874 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13875 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13876 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13878 // In AVX-512 architecture setcc returns mask with i1 elements,
13879 // But there is no compare instruction for i8 and i16 elements in KNL.
13880 // We are not talking about 512-bit operands in this case, these
13881 // types are illegal.
13883 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13884 OpVT.getVectorElementType().getSizeInBits() >= 8))
13885 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13886 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13889 // We are handling one of the integer comparisons here. Since SSE only has
13890 // GT and EQ comparisons for integer, swapping operands and multiple
13891 // operations may be required for some comparisons.
13893 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13894 bool Subus = false;
13896 switch (SetCCOpcode) {
13897 default: llvm_unreachable("Unexpected SETCC condition");
13898 case ISD::SETNE: Invert = true;
13899 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13900 case ISD::SETLT: Swap = true;
13901 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13902 case ISD::SETGE: Swap = true;
13903 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13904 Invert = true; break;
13905 case ISD::SETULT: Swap = true;
13906 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13907 FlipSigns = true; break;
13908 case ISD::SETUGE: Swap = true;
13909 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13910 FlipSigns = true; Invert = true; break;
13913 // Special case: Use min/max operations for SETULE/SETUGE
13914 MVT VET = VT.getVectorElementType();
13916 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13917 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13920 switch (SetCCOpcode) {
13922 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13923 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13926 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13929 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13930 if (!MinMax && hasSubus) {
13931 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13933 // t = psubus Op0, Op1
13934 // pcmpeq t, <0..0>
13935 switch (SetCCOpcode) {
13937 case ISD::SETULT: {
13938 // If the comparison is against a constant we can turn this into a
13939 // setule. With psubus, setule does not require a swap. This is
13940 // beneficial because the constant in the register is no longer
13941 // destructed as the destination so it can be hoisted out of a loop.
13942 // Only do this pre-AVX since vpcmp* is no longer destructive.
13943 if (Subtarget->hasAVX())
13945 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13946 if (ULEOp1.getNode()) {
13948 Subus = true; Invert = false; Swap = false;
13952 // Psubus is better than flip-sign because it requires no inversion.
13953 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13954 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13958 Opc = X86ISD::SUBUS;
13964 std::swap(Op0, Op1);
13966 // Check that the operation in question is available (most are plain SSE2,
13967 // but PCMPGTQ and PCMPEQQ have different requirements).
13968 if (VT == MVT::v2i64) {
13969 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13970 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13972 // First cast everything to the right type.
13973 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13974 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13976 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13977 // bits of the inputs before performing those operations. The lower
13978 // compare is always unsigned.
13981 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13983 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13984 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13985 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13986 Sign, Zero, Sign, Zero);
13988 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13989 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13991 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13992 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13993 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13995 // Create masks for only the low parts/high parts of the 64 bit integers.
13996 static const int MaskHi[] = { 1, 1, 3, 3 };
13997 static const int MaskLo[] = { 0, 0, 2, 2 };
13998 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13999 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14000 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14002 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14003 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14006 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14008 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14011 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14012 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14013 // pcmpeqd + pshufd + pand.
14014 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14016 // First cast everything to the right type.
14017 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14018 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14021 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14023 // Make sure the lower and upper halves are both all-ones.
14024 static const int Mask[] = { 1, 0, 3, 2 };
14025 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14026 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14029 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14031 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14035 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14036 // bits of the inputs before performing those operations.
14038 EVT EltVT = VT.getVectorElementType();
14039 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14040 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14041 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14044 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14046 // If the logical-not of the result is required, perform that now.
14048 Result = DAG.getNOT(dl, Result, VT);
14051 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14054 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14055 getZeroVector(VT, Subtarget, DAG, dl));
14060 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14062 MVT VT = Op.getSimpleValueType();
14064 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14066 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14067 && "SetCC type must be 8-bit or 1-bit integer");
14068 SDValue Op0 = Op.getOperand(0);
14069 SDValue Op1 = Op.getOperand(1);
14071 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14073 // Optimize to BT if possible.
14074 // Lower (X & (1 << N)) == 0 to BT(X, N).
14075 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14076 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14077 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14078 Op1.getOpcode() == ISD::Constant &&
14079 cast<ConstantSDNode>(Op1)->isNullValue() &&
14080 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14081 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14082 if (NewSetCC.getNode())
14086 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14088 if (Op1.getOpcode() == ISD::Constant &&
14089 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14090 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14091 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14093 // If the input is a setcc, then reuse the input setcc or use a new one with
14094 // the inverted condition.
14095 if (Op0.getOpcode() == X86ISD::SETCC) {
14096 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14097 bool Invert = (CC == ISD::SETNE) ^
14098 cast<ConstantSDNode>(Op1)->isNullValue();
14102 CCode = X86::GetOppositeBranchCondition(CCode);
14103 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14104 DAG.getConstant(CCode, MVT::i8),
14105 Op0.getOperand(1));
14107 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14111 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14112 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14113 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14115 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14116 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14119 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14120 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14121 if (X86CC == X86::COND_INVALID)
14124 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14125 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14126 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14127 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14129 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14133 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14134 static bool isX86LogicalCmp(SDValue Op) {
14135 unsigned Opc = Op.getNode()->getOpcode();
14136 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14137 Opc == X86ISD::SAHF)
14139 if (Op.getResNo() == 1 &&
14140 (Opc == X86ISD::ADD ||
14141 Opc == X86ISD::SUB ||
14142 Opc == X86ISD::ADC ||
14143 Opc == X86ISD::SBB ||
14144 Opc == X86ISD::SMUL ||
14145 Opc == X86ISD::UMUL ||
14146 Opc == X86ISD::INC ||
14147 Opc == X86ISD::DEC ||
14148 Opc == X86ISD::OR ||
14149 Opc == X86ISD::XOR ||
14150 Opc == X86ISD::AND))
14153 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14159 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14160 if (V.getOpcode() != ISD::TRUNCATE)
14163 SDValue VOp0 = V.getOperand(0);
14164 unsigned InBits = VOp0.getValueSizeInBits();
14165 unsigned Bits = V.getValueSizeInBits();
14166 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14169 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14170 bool addTest = true;
14171 SDValue Cond = Op.getOperand(0);
14172 SDValue Op1 = Op.getOperand(1);
14173 SDValue Op2 = Op.getOperand(2);
14175 EVT VT = Op1.getValueType();
14178 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14179 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14180 // sequence later on.
14181 if (Cond.getOpcode() == ISD::SETCC &&
14182 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14183 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14184 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14185 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14186 int SSECC = translateX86FSETCC(
14187 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14190 if (Subtarget->hasAVX512()) {
14191 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14192 DAG.getConstant(SSECC, MVT::i8));
14193 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14195 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14196 DAG.getConstant(SSECC, MVT::i8));
14197 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14198 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14199 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14203 if (Cond.getOpcode() == ISD::SETCC) {
14204 SDValue NewCond = LowerSETCC(Cond, DAG);
14205 if (NewCond.getNode())
14209 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14210 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14211 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14212 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14213 if (Cond.getOpcode() == X86ISD::SETCC &&
14214 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14215 isZero(Cond.getOperand(1).getOperand(1))) {
14216 SDValue Cmp = Cond.getOperand(1);
14218 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14220 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14221 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14222 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14224 SDValue CmpOp0 = Cmp.getOperand(0);
14225 // Apply further optimizations for special cases
14226 // (select (x != 0), -1, 0) -> neg & sbb
14227 // (select (x == 0), 0, -1) -> neg & sbb
14228 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14229 if (YC->isNullValue() &&
14230 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14231 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14232 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14233 DAG.getConstant(0, CmpOp0.getValueType()),
14235 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14236 DAG.getConstant(X86::COND_B, MVT::i8),
14237 SDValue(Neg.getNode(), 1));
14241 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14242 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14243 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14245 SDValue Res = // Res = 0 or -1.
14246 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14247 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14249 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14250 Res = DAG.getNOT(DL, Res, Res.getValueType());
14252 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14253 if (!N2C || !N2C->isNullValue())
14254 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14259 // Look past (and (setcc_carry (cmp ...)), 1).
14260 if (Cond.getOpcode() == ISD::AND &&
14261 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14262 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14263 if (C && C->getAPIntValue() == 1)
14264 Cond = Cond.getOperand(0);
14267 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14268 // setting operand in place of the X86ISD::SETCC.
14269 unsigned CondOpcode = Cond.getOpcode();
14270 if (CondOpcode == X86ISD::SETCC ||
14271 CondOpcode == X86ISD::SETCC_CARRY) {
14272 CC = Cond.getOperand(0);
14274 SDValue Cmp = Cond.getOperand(1);
14275 unsigned Opc = Cmp.getOpcode();
14276 MVT VT = Op.getSimpleValueType();
14278 bool IllegalFPCMov = false;
14279 if (VT.isFloatingPoint() && !VT.isVector() &&
14280 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14281 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14283 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14284 Opc == X86ISD::BT) { // FIXME
14288 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14289 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14290 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14291 Cond.getOperand(0).getValueType() != MVT::i8)) {
14292 SDValue LHS = Cond.getOperand(0);
14293 SDValue RHS = Cond.getOperand(1);
14294 unsigned X86Opcode;
14297 switch (CondOpcode) {
14298 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14299 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14300 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14301 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14302 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14303 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14304 default: llvm_unreachable("unexpected overflowing operator");
14306 if (CondOpcode == ISD::UMULO)
14307 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14310 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14312 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14314 if (CondOpcode == ISD::UMULO)
14315 Cond = X86Op.getValue(2);
14317 Cond = X86Op.getValue(1);
14319 CC = DAG.getConstant(X86Cond, MVT::i8);
14324 // Look pass the truncate if the high bits are known zero.
14325 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14326 Cond = Cond.getOperand(0);
14328 // We know the result of AND is compared against zero. Try to match
14330 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14331 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14332 if (NewSetCC.getNode()) {
14333 CC = NewSetCC.getOperand(0);
14334 Cond = NewSetCC.getOperand(1);
14341 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14342 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14345 // a < b ? -1 : 0 -> RES = ~setcc_carry
14346 // a < b ? 0 : -1 -> RES = setcc_carry
14347 // a >= b ? -1 : 0 -> RES = setcc_carry
14348 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14349 if (Cond.getOpcode() == X86ISD::SUB) {
14350 Cond = ConvertCmpIfNecessary(Cond, DAG);
14351 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14353 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14354 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14355 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14356 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14357 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14358 return DAG.getNOT(DL, Res, Res.getValueType());
14363 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14364 // widen the cmov and push the truncate through. This avoids introducing a new
14365 // branch during isel and doesn't add any extensions.
14366 if (Op.getValueType() == MVT::i8 &&
14367 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14368 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14369 if (T1.getValueType() == T2.getValueType() &&
14370 // Blacklist CopyFromReg to avoid partial register stalls.
14371 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14372 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14373 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14374 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14378 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14379 // condition is true.
14380 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14381 SDValue Ops[] = { Op2, Op1, CC, Cond };
14382 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14385 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14386 MVT VT = Op->getSimpleValueType(0);
14387 SDValue In = Op->getOperand(0);
14388 MVT InVT = In.getSimpleValueType();
14391 unsigned int NumElts = VT.getVectorNumElements();
14392 if (NumElts != 8 && NumElts != 16)
14395 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14396 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14399 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14401 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14402 Constant *C = ConstantInt::get(*DAG.getContext(),
14403 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14405 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14406 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14407 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14408 MachinePointerInfo::getConstantPool(),
14409 false, false, false, Alignment);
14410 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14411 if (VT.is512BitVector())
14413 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14416 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14417 SelectionDAG &DAG) {
14418 MVT VT = Op->getSimpleValueType(0);
14419 SDValue In = Op->getOperand(0);
14420 MVT InVT = In.getSimpleValueType();
14423 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14424 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14426 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14427 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14428 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14431 if (Subtarget->hasInt256())
14432 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14434 // Optimize vectors in AVX mode
14435 // Sign extend v8i16 to v8i32 and
14438 // Divide input vector into two parts
14439 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14440 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14441 // concat the vectors to original VT
14443 unsigned NumElems = InVT.getVectorNumElements();
14444 SDValue Undef = DAG.getUNDEF(InVT);
14446 SmallVector<int,8> ShufMask1(NumElems, -1);
14447 for (unsigned i = 0; i != NumElems/2; ++i)
14450 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14452 SmallVector<int,8> ShufMask2(NumElems, -1);
14453 for (unsigned i = 0; i != NumElems/2; ++i)
14454 ShufMask2[i] = i + NumElems/2;
14456 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14458 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14459 VT.getVectorNumElements()/2);
14461 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14462 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14464 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14467 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14468 // may emit an illegal shuffle but the expansion is still better than scalar
14469 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14470 // we'll emit a shuffle and a arithmetic shift.
14471 // TODO: It is possible to support ZExt by zeroing the undef values during
14472 // the shuffle phase or after the shuffle.
14473 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14474 SelectionDAG &DAG) {
14475 MVT RegVT = Op.getSimpleValueType();
14476 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14477 assert(RegVT.isInteger() &&
14478 "We only custom lower integer vector sext loads.");
14480 // Nothing useful we can do without SSE2 shuffles.
14481 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14483 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14485 EVT MemVT = Ld->getMemoryVT();
14486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14487 unsigned RegSz = RegVT.getSizeInBits();
14489 ISD::LoadExtType Ext = Ld->getExtensionType();
14491 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14492 && "Only anyext and sext are currently implemented.");
14493 assert(MemVT != RegVT && "Cannot extend to the same type");
14494 assert(MemVT.isVector() && "Must load a vector from memory");
14496 unsigned NumElems = RegVT.getVectorNumElements();
14497 unsigned MemSz = MemVT.getSizeInBits();
14498 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14500 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14501 // The only way in which we have a legal 256-bit vector result but not the
14502 // integer 256-bit operations needed to directly lower a sextload is if we
14503 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14504 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14505 // correctly legalized. We do this late to allow the canonical form of
14506 // sextload to persist throughout the rest of the DAG combiner -- it wants
14507 // to fold together any extensions it can, and so will fuse a sign_extend
14508 // of an sextload into a sextload targeting a wider value.
14510 if (MemSz == 128) {
14511 // Just switch this to a normal load.
14512 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14513 "it must be a legal 128-bit vector "
14515 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14516 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14517 Ld->isInvariant(), Ld->getAlignment());
14519 assert(MemSz < 128 &&
14520 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14521 // Do an sext load to a 128-bit vector type. We want to use the same
14522 // number of elements, but elements half as wide. This will end up being
14523 // recursively lowered by this routine, but will succeed as we definitely
14524 // have all the necessary features if we're using AVX1.
14526 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14527 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14529 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14530 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14531 Ld->isNonTemporal(), Ld->isInvariant(),
14532 Ld->getAlignment());
14535 // Replace chain users with the new chain.
14536 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14537 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14539 // Finally, do a normal sign-extend to the desired register.
14540 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14543 // All sizes must be a power of two.
14544 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14545 "Non-power-of-two elements are not custom lowered!");
14547 // Attempt to load the original value using scalar loads.
14548 // Find the largest scalar type that divides the total loaded size.
14549 MVT SclrLoadTy = MVT::i8;
14550 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14551 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14552 MVT Tp = (MVT::SimpleValueType)tp;
14553 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14558 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14559 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14561 SclrLoadTy = MVT::f64;
14563 // Calculate the number of scalar loads that we need to perform
14564 // in order to load our vector from memory.
14565 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14567 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14568 "Can only lower sext loads with a single scalar load!");
14570 unsigned loadRegZize = RegSz;
14571 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14574 // Represent our vector as a sequence of elements which are the
14575 // largest scalar that we can load.
14576 EVT LoadUnitVecVT = EVT::getVectorVT(
14577 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14579 // Represent the data using the same element type that is stored in
14580 // memory. In practice, we ''widen'' MemVT.
14582 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14583 loadRegZize / MemVT.getScalarType().getSizeInBits());
14585 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14586 "Invalid vector type");
14588 // We can't shuffle using an illegal type.
14589 assert(TLI.isTypeLegal(WideVecVT) &&
14590 "We only lower types that form legal widened vector types");
14592 SmallVector<SDValue, 8> Chains;
14593 SDValue Ptr = Ld->getBasePtr();
14594 SDValue Increment =
14595 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14596 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14598 for (unsigned i = 0; i < NumLoads; ++i) {
14599 // Perform a single load.
14600 SDValue ScalarLoad =
14601 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14602 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14603 Ld->getAlignment());
14604 Chains.push_back(ScalarLoad.getValue(1));
14605 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14606 // another round of DAGCombining.
14608 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14610 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14611 ScalarLoad, DAG.getIntPtrConstant(i));
14613 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14616 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14618 // Bitcast the loaded value to a vector of the original element type, in
14619 // the size of the target vector type.
14620 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14621 unsigned SizeRatio = RegSz / MemSz;
14623 if (Ext == ISD::SEXTLOAD) {
14624 // If we have SSE4.1, we can directly emit a VSEXT node.
14625 if (Subtarget->hasSSE41()) {
14626 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14627 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14631 // Otherwise we'll shuffle the small elements in the high bits of the
14632 // larger type and perform an arithmetic shift. If the shift is not legal
14633 // it's better to scalarize.
14634 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14635 "We can't implement a sext load without an arithmetic right shift!");
14637 // Redistribute the loaded elements into the different locations.
14638 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14639 for (unsigned i = 0; i != NumElems; ++i)
14640 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14642 SDValue Shuff = DAG.getVectorShuffle(
14643 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14645 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14647 // Build the arithmetic shift.
14648 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14649 MemVT.getVectorElementType().getSizeInBits();
14651 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14653 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14657 // Redistribute the loaded elements into the different locations.
14658 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14659 for (unsigned i = 0; i != NumElems; ++i)
14660 ShuffleVec[i * SizeRatio] = i;
14662 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14663 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14665 // Bitcast to the requested type.
14666 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14667 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14671 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14672 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14673 // from the AND / OR.
14674 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14675 Opc = Op.getOpcode();
14676 if (Opc != ISD::OR && Opc != ISD::AND)
14678 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14679 Op.getOperand(0).hasOneUse() &&
14680 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14681 Op.getOperand(1).hasOneUse());
14684 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14685 // 1 and that the SETCC node has a single use.
14686 static bool isXor1OfSetCC(SDValue Op) {
14687 if (Op.getOpcode() != ISD::XOR)
14689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14690 if (N1C && N1C->getAPIntValue() == 1) {
14691 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14692 Op.getOperand(0).hasOneUse();
14697 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14698 bool addTest = true;
14699 SDValue Chain = Op.getOperand(0);
14700 SDValue Cond = Op.getOperand(1);
14701 SDValue Dest = Op.getOperand(2);
14704 bool Inverted = false;
14706 if (Cond.getOpcode() == ISD::SETCC) {
14707 // Check for setcc([su]{add,sub,mul}o == 0).
14708 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14709 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14710 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14711 Cond.getOperand(0).getResNo() == 1 &&
14712 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14713 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14714 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14715 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14716 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14717 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14719 Cond = Cond.getOperand(0);
14721 SDValue NewCond = LowerSETCC(Cond, DAG);
14722 if (NewCond.getNode())
14727 // FIXME: LowerXALUO doesn't handle these!!
14728 else if (Cond.getOpcode() == X86ISD::ADD ||
14729 Cond.getOpcode() == X86ISD::SUB ||
14730 Cond.getOpcode() == X86ISD::SMUL ||
14731 Cond.getOpcode() == X86ISD::UMUL)
14732 Cond = LowerXALUO(Cond, DAG);
14735 // Look pass (and (setcc_carry (cmp ...)), 1).
14736 if (Cond.getOpcode() == ISD::AND &&
14737 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14738 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14739 if (C && C->getAPIntValue() == 1)
14740 Cond = Cond.getOperand(0);
14743 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14744 // setting operand in place of the X86ISD::SETCC.
14745 unsigned CondOpcode = Cond.getOpcode();
14746 if (CondOpcode == X86ISD::SETCC ||
14747 CondOpcode == X86ISD::SETCC_CARRY) {
14748 CC = Cond.getOperand(0);
14750 SDValue Cmp = Cond.getOperand(1);
14751 unsigned Opc = Cmp.getOpcode();
14752 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14753 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14757 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14761 // These can only come from an arithmetic instruction with overflow,
14762 // e.g. SADDO, UADDO.
14763 Cond = Cond.getNode()->getOperand(1);
14769 CondOpcode = Cond.getOpcode();
14770 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14771 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14772 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14773 Cond.getOperand(0).getValueType() != MVT::i8)) {
14774 SDValue LHS = Cond.getOperand(0);
14775 SDValue RHS = Cond.getOperand(1);
14776 unsigned X86Opcode;
14779 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14780 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14782 switch (CondOpcode) {
14783 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14787 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14790 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14791 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14795 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14798 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14799 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14800 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14801 default: llvm_unreachable("unexpected overflowing operator");
14804 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14805 if (CondOpcode == ISD::UMULO)
14806 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14809 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14811 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14813 if (CondOpcode == ISD::UMULO)
14814 Cond = X86Op.getValue(2);
14816 Cond = X86Op.getValue(1);
14818 CC = DAG.getConstant(X86Cond, MVT::i8);
14822 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14823 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14824 if (CondOpc == ISD::OR) {
14825 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14826 // two branches instead of an explicit OR instruction with a
14828 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14829 isX86LogicalCmp(Cmp)) {
14830 CC = Cond.getOperand(0).getOperand(0);
14831 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14832 Chain, Dest, CC, Cmp);
14833 CC = Cond.getOperand(1).getOperand(0);
14837 } else { // ISD::AND
14838 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14839 // two branches instead of an explicit AND instruction with a
14840 // separate test. However, we only do this if this block doesn't
14841 // have a fall-through edge, because this requires an explicit
14842 // jmp when the condition is false.
14843 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14844 isX86LogicalCmp(Cmp) &&
14845 Op.getNode()->hasOneUse()) {
14846 X86::CondCode CCode =
14847 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14848 CCode = X86::GetOppositeBranchCondition(CCode);
14849 CC = DAG.getConstant(CCode, MVT::i8);
14850 SDNode *User = *Op.getNode()->use_begin();
14851 // Look for an unconditional branch following this conditional branch.
14852 // We need this because we need to reverse the successors in order
14853 // to implement FCMP_OEQ.
14854 if (User->getOpcode() == ISD::BR) {
14855 SDValue FalseBB = User->getOperand(1);
14857 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14858 assert(NewBR == User);
14862 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14863 Chain, Dest, CC, Cmp);
14864 X86::CondCode CCode =
14865 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14866 CCode = X86::GetOppositeBranchCondition(CCode);
14867 CC = DAG.getConstant(CCode, MVT::i8);
14873 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14874 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14875 // It should be transformed during dag combiner except when the condition
14876 // is set by a arithmetics with overflow node.
14877 X86::CondCode CCode =
14878 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14879 CCode = X86::GetOppositeBranchCondition(CCode);
14880 CC = DAG.getConstant(CCode, MVT::i8);
14881 Cond = Cond.getOperand(0).getOperand(1);
14883 } else if (Cond.getOpcode() == ISD::SETCC &&
14884 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14885 // For FCMP_OEQ, we can emit
14886 // two branches instead of an explicit AND instruction with a
14887 // separate test. However, we only do this if this block doesn't
14888 // have a fall-through edge, because this requires an explicit
14889 // jmp when the condition is false.
14890 if (Op.getNode()->hasOneUse()) {
14891 SDNode *User = *Op.getNode()->use_begin();
14892 // Look for an unconditional branch following this conditional branch.
14893 // We need this because we need to reverse the successors in order
14894 // to implement FCMP_OEQ.
14895 if (User->getOpcode() == ISD::BR) {
14896 SDValue FalseBB = User->getOperand(1);
14898 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14899 assert(NewBR == User);
14903 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14904 Cond.getOperand(0), Cond.getOperand(1));
14905 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14906 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14907 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14908 Chain, Dest, CC, Cmp);
14909 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14914 } else if (Cond.getOpcode() == ISD::SETCC &&
14915 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14916 // For FCMP_UNE, we can emit
14917 // two branches instead of an explicit AND instruction with a
14918 // separate test. However, we only do this if this block doesn't
14919 // have a fall-through edge, because this requires an explicit
14920 // jmp when the condition is false.
14921 if (Op.getNode()->hasOneUse()) {
14922 SDNode *User = *Op.getNode()->use_begin();
14923 // Look for an unconditional branch following this conditional branch.
14924 // We need this because we need to reverse the successors in order
14925 // to implement FCMP_UNE.
14926 if (User->getOpcode() == ISD::BR) {
14927 SDValue FalseBB = User->getOperand(1);
14929 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14930 assert(NewBR == User);
14933 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14934 Cond.getOperand(0), Cond.getOperand(1));
14935 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14936 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14937 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14938 Chain, Dest, CC, Cmp);
14939 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14949 // Look pass the truncate if the high bits are known zero.
14950 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14951 Cond = Cond.getOperand(0);
14953 // We know the result of AND is compared against zero. Try to match
14955 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14956 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14957 if (NewSetCC.getNode()) {
14958 CC = NewSetCC.getOperand(0);
14959 Cond = NewSetCC.getOperand(1);
14966 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14967 CC = DAG.getConstant(X86Cond, MVT::i8);
14968 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14970 Cond = ConvertCmpIfNecessary(Cond, DAG);
14971 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14972 Chain, Dest, CC, Cond);
14975 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14976 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14977 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14978 // that the guard pages used by the OS virtual memory manager are allocated in
14979 // correct sequence.
14981 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14982 SelectionDAG &DAG) const {
14983 MachineFunction &MF = DAG.getMachineFunction();
14984 bool SplitStack = MF.shouldSplitStack();
14985 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14991 SDNode* Node = Op.getNode();
14993 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14994 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14995 " not tell us which reg is the stack pointer!");
14996 EVT VT = Node->getValueType(0);
14997 SDValue Tmp1 = SDValue(Node, 0);
14998 SDValue Tmp2 = SDValue(Node, 1);
14999 SDValue Tmp3 = Node->getOperand(2);
15000 SDValue Chain = Tmp1.getOperand(0);
15002 // Chain the dynamic stack allocation so that it doesn't modify the stack
15003 // pointer when other instructions are using the stack.
15004 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15007 SDValue Size = Tmp2.getOperand(1);
15008 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15009 Chain = SP.getValue(1);
15010 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15011 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15012 unsigned StackAlign = TFI.getStackAlignment();
15013 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15014 if (Align > StackAlign)
15015 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15016 DAG.getConstant(-(uint64_t)Align, VT));
15017 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15019 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15020 DAG.getIntPtrConstant(0, true), SDValue(),
15023 SDValue Ops[2] = { Tmp1, Tmp2 };
15024 return DAG.getMergeValues(Ops, dl);
15028 SDValue Chain = Op.getOperand(0);
15029 SDValue Size = Op.getOperand(1);
15030 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15031 EVT VT = Op.getNode()->getValueType(0);
15033 bool Is64Bit = Subtarget->is64Bit();
15034 EVT SPTy = getPointerTy();
15037 MachineRegisterInfo &MRI = MF.getRegInfo();
15040 // The 64 bit implementation of segmented stacks needs to clobber both r10
15041 // r11. This makes it impossible to use it along with nested parameters.
15042 const Function *F = MF.getFunction();
15044 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15046 if (I->hasNestAttr())
15047 report_fatal_error("Cannot use segmented stacks with functions that "
15048 "have nested arguments.");
15051 const TargetRegisterClass *AddrRegClass =
15052 getRegClassFor(getPointerTy());
15053 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15054 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15055 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15056 DAG.getRegister(Vreg, SPTy));
15057 SDValue Ops1[2] = { Value, Chain };
15058 return DAG.getMergeValues(Ops1, dl);
15061 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15063 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15064 Flag = Chain.getValue(1);
15065 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15067 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15069 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15070 DAG.getSubtarget().getRegisterInfo());
15071 unsigned SPReg = RegInfo->getStackRegister();
15072 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15073 Chain = SP.getValue(1);
15076 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15077 DAG.getConstant(-(uint64_t)Align, VT));
15078 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15081 SDValue Ops1[2] = { SP, Chain };
15082 return DAG.getMergeValues(Ops1, dl);
15086 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15087 MachineFunction &MF = DAG.getMachineFunction();
15088 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15090 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15093 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15094 // vastart just stores the address of the VarArgsFrameIndex slot into the
15095 // memory location argument.
15096 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15098 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15099 MachinePointerInfo(SV), false, false, 0);
15103 // gp_offset (0 - 6 * 8)
15104 // fp_offset (48 - 48 + 8 * 16)
15105 // overflow_arg_area (point to parameters coming in memory).
15107 SmallVector<SDValue, 8> MemOps;
15108 SDValue FIN = Op.getOperand(1);
15110 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15111 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15113 FIN, MachinePointerInfo(SV), false, false, 0);
15114 MemOps.push_back(Store);
15117 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15118 FIN, DAG.getIntPtrConstant(4));
15119 Store = DAG.getStore(Op.getOperand(0), DL,
15120 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15122 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15123 MemOps.push_back(Store);
15125 // Store ptr to overflow_arg_area
15126 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15127 FIN, DAG.getIntPtrConstant(4));
15128 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15130 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15131 MachinePointerInfo(SV, 8),
15133 MemOps.push_back(Store);
15135 // Store ptr to reg_save_area.
15136 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15137 FIN, DAG.getIntPtrConstant(8));
15138 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15140 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15141 MachinePointerInfo(SV, 16), false, false, 0);
15142 MemOps.push_back(Store);
15143 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15146 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15147 assert(Subtarget->is64Bit() &&
15148 "LowerVAARG only handles 64-bit va_arg!");
15149 assert((Subtarget->isTargetLinux() ||
15150 Subtarget->isTargetDarwin()) &&
15151 "Unhandled target in LowerVAARG");
15152 assert(Op.getNode()->getNumOperands() == 4);
15153 SDValue Chain = Op.getOperand(0);
15154 SDValue SrcPtr = Op.getOperand(1);
15155 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15156 unsigned Align = Op.getConstantOperandVal(3);
15159 EVT ArgVT = Op.getNode()->getValueType(0);
15160 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15161 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15164 // Decide which area this value should be read from.
15165 // TODO: Implement the AMD64 ABI in its entirety. This simple
15166 // selection mechanism works only for the basic types.
15167 if (ArgVT == MVT::f80) {
15168 llvm_unreachable("va_arg for f80 not yet implemented");
15169 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15170 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15171 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15172 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15174 llvm_unreachable("Unhandled argument type in LowerVAARG");
15177 if (ArgMode == 2) {
15178 // Sanity Check: Make sure using fp_offset makes sense.
15179 assert(!DAG.getTarget().Options.UseSoftFloat &&
15180 !(DAG.getMachineFunction()
15181 .getFunction()->getAttributes()
15182 .hasAttribute(AttributeSet::FunctionIndex,
15183 Attribute::NoImplicitFloat)) &&
15184 Subtarget->hasSSE1());
15187 // Insert VAARG_64 node into the DAG
15188 // VAARG_64 returns two values: Variable Argument Address, Chain
15189 SmallVector<SDValue, 11> InstOps;
15190 InstOps.push_back(Chain);
15191 InstOps.push_back(SrcPtr);
15192 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15193 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15194 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15195 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15196 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15197 VTs, InstOps, MVT::i64,
15198 MachinePointerInfo(SV),
15200 /*Volatile=*/false,
15202 /*WriteMem=*/true);
15203 Chain = VAARG.getValue(1);
15205 // Load the next argument and return it
15206 return DAG.getLoad(ArgVT, dl,
15209 MachinePointerInfo(),
15210 false, false, false, 0);
15213 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15214 SelectionDAG &DAG) {
15215 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15216 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15217 SDValue Chain = Op.getOperand(0);
15218 SDValue DstPtr = Op.getOperand(1);
15219 SDValue SrcPtr = Op.getOperand(2);
15220 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15221 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15224 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15225 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15227 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15230 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15231 // amount is a constant. Takes immediate version of shift as input.
15232 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15233 SDValue SrcOp, uint64_t ShiftAmt,
15234 SelectionDAG &DAG) {
15235 MVT ElementType = VT.getVectorElementType();
15237 // Fold this packed shift into its first operand if ShiftAmt is 0.
15241 // Check for ShiftAmt >= element width
15242 if (ShiftAmt >= ElementType.getSizeInBits()) {
15243 if (Opc == X86ISD::VSRAI)
15244 ShiftAmt = ElementType.getSizeInBits() - 1;
15246 return DAG.getConstant(0, VT);
15249 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15250 && "Unknown target vector shift-by-constant node");
15252 // Fold this packed vector shift into a build vector if SrcOp is a
15253 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15254 if (VT == SrcOp.getSimpleValueType() &&
15255 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15256 SmallVector<SDValue, 8> Elts;
15257 unsigned NumElts = SrcOp->getNumOperands();
15258 ConstantSDNode *ND;
15261 default: llvm_unreachable(nullptr);
15262 case X86ISD::VSHLI:
15263 for (unsigned i=0; i!=NumElts; ++i) {
15264 SDValue CurrentOp = SrcOp->getOperand(i);
15265 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15266 Elts.push_back(CurrentOp);
15269 ND = cast<ConstantSDNode>(CurrentOp);
15270 const APInt &C = ND->getAPIntValue();
15271 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15274 case X86ISD::VSRLI:
15275 for (unsigned i=0; i!=NumElts; ++i) {
15276 SDValue CurrentOp = SrcOp->getOperand(i);
15277 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15278 Elts.push_back(CurrentOp);
15281 ND = cast<ConstantSDNode>(CurrentOp);
15282 const APInt &C = ND->getAPIntValue();
15283 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15286 case X86ISD::VSRAI:
15287 for (unsigned i=0; i!=NumElts; ++i) {
15288 SDValue CurrentOp = SrcOp->getOperand(i);
15289 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15290 Elts.push_back(CurrentOp);
15293 ND = cast<ConstantSDNode>(CurrentOp);
15294 const APInt &C = ND->getAPIntValue();
15295 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15300 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15303 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15306 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15307 // may or may not be a constant. Takes immediate version of shift as input.
15308 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15309 SDValue SrcOp, SDValue ShAmt,
15310 SelectionDAG &DAG) {
15311 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15313 // Catch shift-by-constant.
15314 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15315 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15316 CShAmt->getZExtValue(), DAG);
15318 // Change opcode to non-immediate version
15320 default: llvm_unreachable("Unknown target vector shift node");
15321 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15322 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15323 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15326 // Need to build a vector containing shift amount
15327 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15330 ShOps[1] = DAG.getConstant(0, MVT::i32);
15331 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15332 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15334 // The return type has to be a 128-bit type with the same element
15335 // type as the input type.
15336 MVT EltVT = VT.getVectorElementType();
15337 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15339 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15340 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15343 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15344 /// necessary casting for \p Mask when lowering masking intrinsics.
15345 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15346 SDValue PreservedSrc, SelectionDAG &DAG) {
15347 EVT VT = Op.getValueType();
15348 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15349 MVT::i1, VT.getVectorNumElements());
15352 assert(MaskVT.isSimple() && "invalid mask type");
15353 return DAG.getNode(ISD::VSELECT, dl, VT,
15354 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15358 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15360 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15361 case Intrinsic::x86_fma_vfmadd_ps:
15362 case Intrinsic::x86_fma_vfmadd_pd:
15363 case Intrinsic::x86_fma_vfmadd_ps_256:
15364 case Intrinsic::x86_fma_vfmadd_pd_256:
15365 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15366 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15367 return X86ISD::FMADD;
15368 case Intrinsic::x86_fma_vfmsub_ps:
15369 case Intrinsic::x86_fma_vfmsub_pd:
15370 case Intrinsic::x86_fma_vfmsub_ps_256:
15371 case Intrinsic::x86_fma_vfmsub_pd_256:
15372 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15373 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15374 return X86ISD::FMSUB;
15375 case Intrinsic::x86_fma_vfnmadd_ps:
15376 case Intrinsic::x86_fma_vfnmadd_pd:
15377 case Intrinsic::x86_fma_vfnmadd_ps_256:
15378 case Intrinsic::x86_fma_vfnmadd_pd_256:
15379 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15380 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15381 return X86ISD::FNMADD;
15382 case Intrinsic::x86_fma_vfnmsub_ps:
15383 case Intrinsic::x86_fma_vfnmsub_pd:
15384 case Intrinsic::x86_fma_vfnmsub_ps_256:
15385 case Intrinsic::x86_fma_vfnmsub_pd_256:
15386 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15387 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15388 return X86ISD::FNMSUB;
15389 case Intrinsic::x86_fma_vfmaddsub_ps:
15390 case Intrinsic::x86_fma_vfmaddsub_pd:
15391 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15392 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15393 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15394 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15395 return X86ISD::FMADDSUB;
15396 case Intrinsic::x86_fma_vfmsubadd_ps:
15397 case Intrinsic::x86_fma_vfmsubadd_pd:
15398 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15399 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15400 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15401 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15402 return X86ISD::FMSUBADD;
15406 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15408 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15410 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15412 switch(IntrData->Type) {
15413 case INTR_TYPE_1OP:
15414 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15415 case INTR_TYPE_2OP:
15416 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15418 case INTR_TYPE_3OP:
15419 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15420 Op.getOperand(2), Op.getOperand(3));
15421 case COMI: { // Comparison intrinsics
15422 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15423 SDValue LHS = Op.getOperand(1);
15424 SDValue RHS = Op.getOperand(2);
15425 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15426 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15427 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15428 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15429 DAG.getConstant(X86CC, MVT::i8), Cond);
15430 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15433 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15434 Op.getOperand(1), Op.getOperand(2), DAG);
15441 default: return SDValue(); // Don't custom lower most intrinsics.
15443 // Arithmetic intrinsics.
15444 case Intrinsic::x86_sse2_pmulu_dq:
15445 case Intrinsic::x86_avx2_pmulu_dq:
15446 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15447 Op.getOperand(1), Op.getOperand(2));
15449 case Intrinsic::x86_sse41_pmuldq:
15450 case Intrinsic::x86_avx2_pmul_dq:
15451 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15452 Op.getOperand(1), Op.getOperand(2));
15454 case Intrinsic::x86_sse2_pmulhu_w:
15455 case Intrinsic::x86_avx2_pmulhu_w:
15456 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15457 Op.getOperand(1), Op.getOperand(2));
15459 case Intrinsic::x86_sse2_pmulh_w:
15460 case Intrinsic::x86_avx2_pmulh_w:
15461 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15462 Op.getOperand(1), Op.getOperand(2));
15464 // SSE/SSE2/AVX floating point max/min intrinsics.
15465 case Intrinsic::x86_sse_max_ps:
15466 case Intrinsic::x86_sse2_max_pd:
15467 case Intrinsic::x86_avx_max_ps_256:
15468 case Intrinsic::x86_avx_max_pd_256:
15469 case Intrinsic::x86_sse_min_ps:
15470 case Intrinsic::x86_sse2_min_pd:
15471 case Intrinsic::x86_avx_min_ps_256:
15472 case Intrinsic::x86_avx_min_pd_256: {
15475 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15476 case Intrinsic::x86_sse_max_ps:
15477 case Intrinsic::x86_sse2_max_pd:
15478 case Intrinsic::x86_avx_max_ps_256:
15479 case Intrinsic::x86_avx_max_pd_256:
15480 Opcode = X86ISD::FMAX;
15482 case Intrinsic::x86_sse_min_ps:
15483 case Intrinsic::x86_sse2_min_pd:
15484 case Intrinsic::x86_avx_min_ps_256:
15485 case Intrinsic::x86_avx_min_pd_256:
15486 Opcode = X86ISD::FMIN;
15489 return DAG.getNode(Opcode, dl, Op.getValueType(),
15490 Op.getOperand(1), Op.getOperand(2));
15493 // AVX2 variable shift intrinsics
15494 case Intrinsic::x86_avx2_psllv_d:
15495 case Intrinsic::x86_avx2_psllv_q:
15496 case Intrinsic::x86_avx2_psllv_d_256:
15497 case Intrinsic::x86_avx2_psllv_q_256:
15498 case Intrinsic::x86_avx2_psrlv_d:
15499 case Intrinsic::x86_avx2_psrlv_q:
15500 case Intrinsic::x86_avx2_psrlv_d_256:
15501 case Intrinsic::x86_avx2_psrlv_q_256:
15502 case Intrinsic::x86_avx2_psrav_d:
15503 case Intrinsic::x86_avx2_psrav_d_256: {
15506 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15507 case Intrinsic::x86_avx2_psllv_d:
15508 case Intrinsic::x86_avx2_psllv_q:
15509 case Intrinsic::x86_avx2_psllv_d_256:
15510 case Intrinsic::x86_avx2_psllv_q_256:
15513 case Intrinsic::x86_avx2_psrlv_d:
15514 case Intrinsic::x86_avx2_psrlv_q:
15515 case Intrinsic::x86_avx2_psrlv_d_256:
15516 case Intrinsic::x86_avx2_psrlv_q_256:
15519 case Intrinsic::x86_avx2_psrav_d:
15520 case Intrinsic::x86_avx2_psrav_d_256:
15524 return DAG.getNode(Opcode, dl, Op.getValueType(),
15525 Op.getOperand(1), Op.getOperand(2));
15528 case Intrinsic::x86_sse2_packssdw_128:
15529 case Intrinsic::x86_sse2_packsswb_128:
15530 case Intrinsic::x86_avx2_packssdw:
15531 case Intrinsic::x86_avx2_packsswb:
15532 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15533 Op.getOperand(1), Op.getOperand(2));
15535 case Intrinsic::x86_sse2_packuswb_128:
15536 case Intrinsic::x86_sse41_packusdw:
15537 case Intrinsic::x86_avx2_packuswb:
15538 case Intrinsic::x86_avx2_packusdw:
15539 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15540 Op.getOperand(1), Op.getOperand(2));
15542 case Intrinsic::x86_ssse3_pshuf_b_128:
15543 case Intrinsic::x86_avx2_pshuf_b:
15544 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15545 Op.getOperand(1), Op.getOperand(2));
15547 case Intrinsic::x86_sse2_pshuf_d:
15548 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15549 Op.getOperand(1), Op.getOperand(2));
15551 case Intrinsic::x86_sse2_pshufl_w:
15552 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15553 Op.getOperand(1), Op.getOperand(2));
15555 case Intrinsic::x86_sse2_pshufh_w:
15556 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15557 Op.getOperand(1), Op.getOperand(2));
15559 case Intrinsic::x86_ssse3_psign_b_128:
15560 case Intrinsic::x86_ssse3_psign_w_128:
15561 case Intrinsic::x86_ssse3_psign_d_128:
15562 case Intrinsic::x86_avx2_psign_b:
15563 case Intrinsic::x86_avx2_psign_w:
15564 case Intrinsic::x86_avx2_psign_d:
15565 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15566 Op.getOperand(1), Op.getOperand(2));
15568 case Intrinsic::x86_avx2_permd:
15569 case Intrinsic::x86_avx2_permps:
15570 // Operands intentionally swapped. Mask is last operand to intrinsic,
15571 // but second operand for node/instruction.
15572 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15573 Op.getOperand(2), Op.getOperand(1));
15575 case Intrinsic::x86_avx512_mask_valign_q_512:
15576 case Intrinsic::x86_avx512_mask_valign_d_512:
15577 // Vector source operands are swapped.
15578 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15579 Op.getValueType(), Op.getOperand(2),
15582 Op.getOperand(5), Op.getOperand(4), DAG);
15584 // ptest and testp intrinsics. The intrinsic these come from are designed to
15585 // return an integer value, not just an instruction so lower it to the ptest
15586 // or testp pattern and a setcc for the result.
15587 case Intrinsic::x86_sse41_ptestz:
15588 case Intrinsic::x86_sse41_ptestc:
15589 case Intrinsic::x86_sse41_ptestnzc:
15590 case Intrinsic::x86_avx_ptestz_256:
15591 case Intrinsic::x86_avx_ptestc_256:
15592 case Intrinsic::x86_avx_ptestnzc_256:
15593 case Intrinsic::x86_avx_vtestz_ps:
15594 case Intrinsic::x86_avx_vtestc_ps:
15595 case Intrinsic::x86_avx_vtestnzc_ps:
15596 case Intrinsic::x86_avx_vtestz_pd:
15597 case Intrinsic::x86_avx_vtestc_pd:
15598 case Intrinsic::x86_avx_vtestnzc_pd:
15599 case Intrinsic::x86_avx_vtestz_ps_256:
15600 case Intrinsic::x86_avx_vtestc_ps_256:
15601 case Intrinsic::x86_avx_vtestnzc_ps_256:
15602 case Intrinsic::x86_avx_vtestz_pd_256:
15603 case Intrinsic::x86_avx_vtestc_pd_256:
15604 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15605 bool IsTestPacked = false;
15608 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15609 case Intrinsic::x86_avx_vtestz_ps:
15610 case Intrinsic::x86_avx_vtestz_pd:
15611 case Intrinsic::x86_avx_vtestz_ps_256:
15612 case Intrinsic::x86_avx_vtestz_pd_256:
15613 IsTestPacked = true; // Fallthrough
15614 case Intrinsic::x86_sse41_ptestz:
15615 case Intrinsic::x86_avx_ptestz_256:
15617 X86CC = X86::COND_E;
15619 case Intrinsic::x86_avx_vtestc_ps:
15620 case Intrinsic::x86_avx_vtestc_pd:
15621 case Intrinsic::x86_avx_vtestc_ps_256:
15622 case Intrinsic::x86_avx_vtestc_pd_256:
15623 IsTestPacked = true; // Fallthrough
15624 case Intrinsic::x86_sse41_ptestc:
15625 case Intrinsic::x86_avx_ptestc_256:
15627 X86CC = X86::COND_B;
15629 case Intrinsic::x86_avx_vtestnzc_ps:
15630 case Intrinsic::x86_avx_vtestnzc_pd:
15631 case Intrinsic::x86_avx_vtestnzc_ps_256:
15632 case Intrinsic::x86_avx_vtestnzc_pd_256:
15633 IsTestPacked = true; // Fallthrough
15634 case Intrinsic::x86_sse41_ptestnzc:
15635 case Intrinsic::x86_avx_ptestnzc_256:
15637 X86CC = X86::COND_A;
15641 SDValue LHS = Op.getOperand(1);
15642 SDValue RHS = Op.getOperand(2);
15643 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15644 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15645 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15646 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15647 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15649 case Intrinsic::x86_avx512_kortestz_w:
15650 case Intrinsic::x86_avx512_kortestc_w: {
15651 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15652 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15653 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15654 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15655 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15656 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15657 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15660 case Intrinsic::x86_sse42_pcmpistria128:
15661 case Intrinsic::x86_sse42_pcmpestria128:
15662 case Intrinsic::x86_sse42_pcmpistric128:
15663 case Intrinsic::x86_sse42_pcmpestric128:
15664 case Intrinsic::x86_sse42_pcmpistrio128:
15665 case Intrinsic::x86_sse42_pcmpestrio128:
15666 case Intrinsic::x86_sse42_pcmpistris128:
15667 case Intrinsic::x86_sse42_pcmpestris128:
15668 case Intrinsic::x86_sse42_pcmpistriz128:
15669 case Intrinsic::x86_sse42_pcmpestriz128: {
15673 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15674 case Intrinsic::x86_sse42_pcmpistria128:
15675 Opcode = X86ISD::PCMPISTRI;
15676 X86CC = X86::COND_A;
15678 case Intrinsic::x86_sse42_pcmpestria128:
15679 Opcode = X86ISD::PCMPESTRI;
15680 X86CC = X86::COND_A;
15682 case Intrinsic::x86_sse42_pcmpistric128:
15683 Opcode = X86ISD::PCMPISTRI;
15684 X86CC = X86::COND_B;
15686 case Intrinsic::x86_sse42_pcmpestric128:
15687 Opcode = X86ISD::PCMPESTRI;
15688 X86CC = X86::COND_B;
15690 case Intrinsic::x86_sse42_pcmpistrio128:
15691 Opcode = X86ISD::PCMPISTRI;
15692 X86CC = X86::COND_O;
15694 case Intrinsic::x86_sse42_pcmpestrio128:
15695 Opcode = X86ISD::PCMPESTRI;
15696 X86CC = X86::COND_O;
15698 case Intrinsic::x86_sse42_pcmpistris128:
15699 Opcode = X86ISD::PCMPISTRI;
15700 X86CC = X86::COND_S;
15702 case Intrinsic::x86_sse42_pcmpestris128:
15703 Opcode = X86ISD::PCMPESTRI;
15704 X86CC = X86::COND_S;
15706 case Intrinsic::x86_sse42_pcmpistriz128:
15707 Opcode = X86ISD::PCMPISTRI;
15708 X86CC = X86::COND_E;
15710 case Intrinsic::x86_sse42_pcmpestriz128:
15711 Opcode = X86ISD::PCMPESTRI;
15712 X86CC = X86::COND_E;
15715 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15716 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15717 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15718 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15719 DAG.getConstant(X86CC, MVT::i8),
15720 SDValue(PCMP.getNode(), 1));
15721 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15724 case Intrinsic::x86_sse42_pcmpistri128:
15725 case Intrinsic::x86_sse42_pcmpestri128: {
15727 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15728 Opcode = X86ISD::PCMPISTRI;
15730 Opcode = X86ISD::PCMPESTRI;
15732 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15733 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15734 return DAG.getNode(Opcode, dl, VTs, NewOps);
15737 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15738 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15739 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15740 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15741 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15742 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15743 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15744 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15745 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15746 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15747 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15748 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15749 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15750 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15751 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15752 dl, Op.getValueType(),
15756 Op.getOperand(4), Op.getOperand(1), DAG);
15761 case Intrinsic::x86_fma_vfmadd_ps:
15762 case Intrinsic::x86_fma_vfmadd_pd:
15763 case Intrinsic::x86_fma_vfmsub_ps:
15764 case Intrinsic::x86_fma_vfmsub_pd:
15765 case Intrinsic::x86_fma_vfnmadd_ps:
15766 case Intrinsic::x86_fma_vfnmadd_pd:
15767 case Intrinsic::x86_fma_vfnmsub_ps:
15768 case Intrinsic::x86_fma_vfnmsub_pd:
15769 case Intrinsic::x86_fma_vfmaddsub_ps:
15770 case Intrinsic::x86_fma_vfmaddsub_pd:
15771 case Intrinsic::x86_fma_vfmsubadd_ps:
15772 case Intrinsic::x86_fma_vfmsubadd_pd:
15773 case Intrinsic::x86_fma_vfmadd_ps_256:
15774 case Intrinsic::x86_fma_vfmadd_pd_256:
15775 case Intrinsic::x86_fma_vfmsub_ps_256:
15776 case Intrinsic::x86_fma_vfmsub_pd_256:
15777 case Intrinsic::x86_fma_vfnmadd_ps_256:
15778 case Intrinsic::x86_fma_vfnmadd_pd_256:
15779 case Intrinsic::x86_fma_vfnmsub_ps_256:
15780 case Intrinsic::x86_fma_vfnmsub_pd_256:
15781 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15782 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15783 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15784 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15785 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15786 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15790 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15791 SDValue Src, SDValue Mask, SDValue Base,
15792 SDValue Index, SDValue ScaleOp, SDValue Chain,
15793 const X86Subtarget * Subtarget) {
15795 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15796 assert(C && "Invalid scale type");
15797 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15798 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15799 Index.getSimpleValueType().getVectorNumElements());
15801 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15803 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15805 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15806 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15807 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15808 SDValue Segment = DAG.getRegister(0, MVT::i32);
15809 if (Src.getOpcode() == ISD::UNDEF)
15810 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15811 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15812 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15813 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15814 return DAG.getMergeValues(RetOps, dl);
15817 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15818 SDValue Src, SDValue Mask, SDValue Base,
15819 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15822 assert(C && "Invalid scale type");
15823 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15824 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15825 SDValue Segment = DAG.getRegister(0, MVT::i32);
15826 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15827 Index.getSimpleValueType().getVectorNumElements());
15829 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15831 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15833 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15834 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15835 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15836 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15837 return SDValue(Res, 1);
15840 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15841 SDValue Mask, SDValue Base, SDValue Index,
15842 SDValue ScaleOp, SDValue Chain) {
15844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15845 assert(C && "Invalid scale type");
15846 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15847 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15848 SDValue Segment = DAG.getRegister(0, MVT::i32);
15850 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15852 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15854 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15856 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15857 //SDVTList VTs = DAG.getVTList(MVT::Other);
15858 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15859 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15860 return SDValue(Res, 0);
15863 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15864 // read performance monitor counters (x86_rdpmc).
15865 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15866 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15867 SmallVectorImpl<SDValue> &Results) {
15868 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15869 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15872 // The ECX register is used to select the index of the performance counter
15874 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15876 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15878 // Reads the content of a 64-bit performance counter and returns it in the
15879 // registers EDX:EAX.
15880 if (Subtarget->is64Bit()) {
15881 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15882 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15885 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15886 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15889 Chain = HI.getValue(1);
15891 if (Subtarget->is64Bit()) {
15892 // The EAX register is loaded with the low-order 32 bits. The EDX register
15893 // is loaded with the supported high-order bits of the counter.
15894 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15895 DAG.getConstant(32, MVT::i8));
15896 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15897 Results.push_back(Chain);
15901 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15902 SDValue Ops[] = { LO, HI };
15903 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15904 Results.push_back(Pair);
15905 Results.push_back(Chain);
15908 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15909 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15910 // also used to custom lower READCYCLECOUNTER nodes.
15911 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15912 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15913 SmallVectorImpl<SDValue> &Results) {
15914 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15915 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15918 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15919 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15920 // and the EAX register is loaded with the low-order 32 bits.
15921 if (Subtarget->is64Bit()) {
15922 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15923 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15926 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15927 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15930 SDValue Chain = HI.getValue(1);
15932 if (Opcode == X86ISD::RDTSCP_DAG) {
15933 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15935 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15936 // the ECX register. Add 'ecx' explicitly to the chain.
15937 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15939 // Explicitly store the content of ECX at the location passed in input
15940 // to the 'rdtscp' intrinsic.
15941 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15942 MachinePointerInfo(), false, false, 0);
15945 if (Subtarget->is64Bit()) {
15946 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15947 // the EAX register is loaded with the low-order 32 bits.
15948 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15949 DAG.getConstant(32, MVT::i8));
15950 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15951 Results.push_back(Chain);
15955 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15956 SDValue Ops[] = { LO, HI };
15957 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15958 Results.push_back(Pair);
15959 Results.push_back(Chain);
15962 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15963 SelectionDAG &DAG) {
15964 SmallVector<SDValue, 2> Results;
15966 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15968 return DAG.getMergeValues(Results, DL);
15972 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15973 SelectionDAG &DAG) {
15974 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15976 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15981 switch(IntrData->Type) {
15983 llvm_unreachable("Unknown Intrinsic Type");
15987 // Emit the node with the right value type.
15988 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15989 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15991 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15992 // Otherwise return the value from Rand, which is always 0, casted to i32.
15993 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15994 DAG.getConstant(1, Op->getValueType(1)),
15995 DAG.getConstant(X86::COND_B, MVT::i32),
15996 SDValue(Result.getNode(), 1) };
15997 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15998 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16001 // Return { result, isValid, chain }.
16002 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16003 SDValue(Result.getNode(), 2));
16006 //gather(v1, mask, index, base, scale);
16007 SDValue Chain = Op.getOperand(0);
16008 SDValue Src = Op.getOperand(2);
16009 SDValue Base = Op.getOperand(3);
16010 SDValue Index = Op.getOperand(4);
16011 SDValue Mask = Op.getOperand(5);
16012 SDValue Scale = Op.getOperand(6);
16013 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16017 //scatter(base, mask, index, v1, scale);
16018 SDValue Chain = Op.getOperand(0);
16019 SDValue Base = Op.getOperand(2);
16020 SDValue Mask = Op.getOperand(3);
16021 SDValue Index = Op.getOperand(4);
16022 SDValue Src = Op.getOperand(5);
16023 SDValue Scale = Op.getOperand(6);
16024 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16027 SDValue Hint = Op.getOperand(6);
16029 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16030 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16031 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16032 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16033 SDValue Chain = Op.getOperand(0);
16034 SDValue Mask = Op.getOperand(2);
16035 SDValue Index = Op.getOperand(3);
16036 SDValue Base = Op.getOperand(4);
16037 SDValue Scale = Op.getOperand(5);
16038 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16040 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16042 SmallVector<SDValue, 2> Results;
16043 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16044 return DAG.getMergeValues(Results, dl);
16046 // Read Performance Monitoring Counters.
16048 SmallVector<SDValue, 2> Results;
16049 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16050 return DAG.getMergeValues(Results, dl);
16052 // XTEST intrinsics.
16054 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16055 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16056 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16057 DAG.getConstant(X86::COND_NE, MVT::i8),
16059 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16060 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16061 Ret, SDValue(InTrans.getNode(), 1));
16065 SmallVector<SDValue, 2> Results;
16066 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16067 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16068 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16069 DAG.getConstant(-1, MVT::i8));
16070 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16071 Op.getOperand(4), GenCF.getValue(1));
16072 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16073 Op.getOperand(5), MachinePointerInfo(),
16075 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16076 DAG.getConstant(X86::COND_B, MVT::i8),
16078 Results.push_back(SetCC);
16079 Results.push_back(Store);
16080 return DAG.getMergeValues(Results, dl);
16085 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16086 SelectionDAG &DAG) const {
16087 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16088 MFI->setReturnAddressIsTaken(true);
16090 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16093 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16095 EVT PtrVT = getPointerTy();
16098 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16099 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16100 DAG.getSubtarget().getRegisterInfo());
16101 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16102 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16103 DAG.getNode(ISD::ADD, dl, PtrVT,
16104 FrameAddr, Offset),
16105 MachinePointerInfo(), false, false, false, 0);
16108 // Just load the return address.
16109 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16110 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16111 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16114 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16115 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16116 MFI->setFrameAddressIsTaken(true);
16118 EVT VT = Op.getValueType();
16119 SDLoc dl(Op); // FIXME probably not meaningful
16120 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16121 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16122 DAG.getSubtarget().getRegisterInfo());
16123 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16124 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16125 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16126 "Invalid Frame Register!");
16127 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16129 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16130 MachinePointerInfo(),
16131 false, false, false, 0);
16135 // FIXME? Maybe this could be a TableGen attribute on some registers and
16136 // this table could be generated automatically from RegInfo.
16137 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16139 unsigned Reg = StringSwitch<unsigned>(RegName)
16140 .Case("esp", X86::ESP)
16141 .Case("rsp", X86::RSP)
16145 report_fatal_error("Invalid register name global variable");
16148 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16149 SelectionDAG &DAG) const {
16150 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16151 DAG.getSubtarget().getRegisterInfo());
16152 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16155 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16156 SDValue Chain = Op.getOperand(0);
16157 SDValue Offset = Op.getOperand(1);
16158 SDValue Handler = Op.getOperand(2);
16161 EVT PtrVT = getPointerTy();
16162 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16163 DAG.getSubtarget().getRegisterInfo());
16164 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16165 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16166 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16167 "Invalid Frame Register!");
16168 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16169 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16171 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16172 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16173 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16174 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16176 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16178 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16179 DAG.getRegister(StoreAddrReg, PtrVT));
16182 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16183 SelectionDAG &DAG) const {
16185 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16186 DAG.getVTList(MVT::i32, MVT::Other),
16187 Op.getOperand(0), Op.getOperand(1));
16190 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16191 SelectionDAG &DAG) const {
16193 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16194 Op.getOperand(0), Op.getOperand(1));
16197 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16198 return Op.getOperand(0);
16201 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16202 SelectionDAG &DAG) const {
16203 SDValue Root = Op.getOperand(0);
16204 SDValue Trmp = Op.getOperand(1); // trampoline
16205 SDValue FPtr = Op.getOperand(2); // nested function
16206 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16209 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16210 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16212 if (Subtarget->is64Bit()) {
16213 SDValue OutChains[6];
16215 // Large code-model.
16216 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16217 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16219 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16220 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16222 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16224 // Load the pointer to the nested function into R11.
16225 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16226 SDValue Addr = Trmp;
16227 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16228 Addr, MachinePointerInfo(TrmpAddr),
16231 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16232 DAG.getConstant(2, MVT::i64));
16233 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16234 MachinePointerInfo(TrmpAddr, 2),
16237 // Load the 'nest' parameter value into R10.
16238 // R10 is specified in X86CallingConv.td
16239 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16240 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16241 DAG.getConstant(10, MVT::i64));
16242 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16243 Addr, MachinePointerInfo(TrmpAddr, 10),
16246 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16247 DAG.getConstant(12, MVT::i64));
16248 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16249 MachinePointerInfo(TrmpAddr, 12),
16252 // Jump to the nested function.
16253 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16254 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16255 DAG.getConstant(20, MVT::i64));
16256 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16257 Addr, MachinePointerInfo(TrmpAddr, 20),
16260 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16261 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16262 DAG.getConstant(22, MVT::i64));
16263 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16264 MachinePointerInfo(TrmpAddr, 22),
16267 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16269 const Function *Func =
16270 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16271 CallingConv::ID CC = Func->getCallingConv();
16276 llvm_unreachable("Unsupported calling convention");
16277 case CallingConv::C:
16278 case CallingConv::X86_StdCall: {
16279 // Pass 'nest' parameter in ECX.
16280 // Must be kept in sync with X86CallingConv.td
16281 NestReg = X86::ECX;
16283 // Check that ECX wasn't needed by an 'inreg' parameter.
16284 FunctionType *FTy = Func->getFunctionType();
16285 const AttributeSet &Attrs = Func->getAttributes();
16287 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16288 unsigned InRegCount = 0;
16291 for (FunctionType::param_iterator I = FTy->param_begin(),
16292 E = FTy->param_end(); I != E; ++I, ++Idx)
16293 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16294 // FIXME: should only count parameters that are lowered to integers.
16295 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16297 if (InRegCount > 2) {
16298 report_fatal_error("Nest register in use - reduce number of inreg"
16304 case CallingConv::X86_FastCall:
16305 case CallingConv::X86_ThisCall:
16306 case CallingConv::Fast:
16307 // Pass 'nest' parameter in EAX.
16308 // Must be kept in sync with X86CallingConv.td
16309 NestReg = X86::EAX;
16313 SDValue OutChains[4];
16314 SDValue Addr, Disp;
16316 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16317 DAG.getConstant(10, MVT::i32));
16318 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16320 // This is storing the opcode for MOV32ri.
16321 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16322 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16323 OutChains[0] = DAG.getStore(Root, dl,
16324 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16325 Trmp, MachinePointerInfo(TrmpAddr),
16328 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16329 DAG.getConstant(1, MVT::i32));
16330 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16331 MachinePointerInfo(TrmpAddr, 1),
16334 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16335 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16336 DAG.getConstant(5, MVT::i32));
16337 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16338 MachinePointerInfo(TrmpAddr, 5),
16341 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16342 DAG.getConstant(6, MVT::i32));
16343 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16344 MachinePointerInfo(TrmpAddr, 6),
16347 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16351 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16352 SelectionDAG &DAG) const {
16354 The rounding mode is in bits 11:10 of FPSR, and has the following
16356 00 Round to nearest
16361 FLT_ROUNDS, on the other hand, expects the following:
16368 To perform the conversion, we do:
16369 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16372 MachineFunction &MF = DAG.getMachineFunction();
16373 const TargetMachine &TM = MF.getTarget();
16374 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16375 unsigned StackAlignment = TFI.getStackAlignment();
16376 MVT VT = Op.getSimpleValueType();
16379 // Save FP Control Word to stack slot
16380 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16381 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16383 MachineMemOperand *MMO =
16384 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16385 MachineMemOperand::MOStore, 2, 2);
16387 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16388 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16389 DAG.getVTList(MVT::Other),
16390 Ops, MVT::i16, MMO);
16392 // Load FP Control Word from stack slot
16393 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16394 MachinePointerInfo(), false, false, false, 0);
16396 // Transform as necessary
16398 DAG.getNode(ISD::SRL, DL, MVT::i16,
16399 DAG.getNode(ISD::AND, DL, MVT::i16,
16400 CWD, DAG.getConstant(0x800, MVT::i16)),
16401 DAG.getConstant(11, MVT::i8));
16403 DAG.getNode(ISD::SRL, DL, MVT::i16,
16404 DAG.getNode(ISD::AND, DL, MVT::i16,
16405 CWD, DAG.getConstant(0x400, MVT::i16)),
16406 DAG.getConstant(9, MVT::i8));
16409 DAG.getNode(ISD::AND, DL, MVT::i16,
16410 DAG.getNode(ISD::ADD, DL, MVT::i16,
16411 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16412 DAG.getConstant(1, MVT::i16)),
16413 DAG.getConstant(3, MVT::i16));
16415 return DAG.getNode((VT.getSizeInBits() < 16 ?
16416 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16419 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16420 MVT VT = Op.getSimpleValueType();
16422 unsigned NumBits = VT.getSizeInBits();
16425 Op = Op.getOperand(0);
16426 if (VT == MVT::i8) {
16427 // Zero extend to i32 since there is not an i8 bsr.
16429 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16432 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16433 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16434 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16436 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16439 DAG.getConstant(NumBits+NumBits-1, OpVT),
16440 DAG.getConstant(X86::COND_E, MVT::i8),
16443 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16445 // Finally xor with NumBits-1.
16446 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16449 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16453 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16454 MVT VT = Op.getSimpleValueType();
16456 unsigned NumBits = VT.getSizeInBits();
16459 Op = Op.getOperand(0);
16460 if (VT == MVT::i8) {
16461 // Zero extend to i32 since there is not an i8 bsr.
16463 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16466 // Issue a bsr (scan bits in reverse).
16467 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16468 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16470 // And xor with NumBits-1.
16471 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16474 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16478 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16479 MVT VT = Op.getSimpleValueType();
16480 unsigned NumBits = VT.getSizeInBits();
16482 Op = Op.getOperand(0);
16484 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16485 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16486 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16488 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16491 DAG.getConstant(NumBits, VT),
16492 DAG.getConstant(X86::COND_E, MVT::i8),
16495 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16498 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16499 // ones, and then concatenate the result back.
16500 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16501 MVT VT = Op.getSimpleValueType();
16503 assert(VT.is256BitVector() && VT.isInteger() &&
16504 "Unsupported value type for operation");
16506 unsigned NumElems = VT.getVectorNumElements();
16509 // Extract the LHS vectors
16510 SDValue LHS = Op.getOperand(0);
16511 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16512 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16514 // Extract the RHS vectors
16515 SDValue RHS = Op.getOperand(1);
16516 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16517 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16519 MVT EltVT = VT.getVectorElementType();
16520 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16522 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16523 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16524 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16527 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16528 assert(Op.getSimpleValueType().is256BitVector() &&
16529 Op.getSimpleValueType().isInteger() &&
16530 "Only handle AVX 256-bit vector integer operation");
16531 return Lower256IntArith(Op, DAG);
16534 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16535 assert(Op.getSimpleValueType().is256BitVector() &&
16536 Op.getSimpleValueType().isInteger() &&
16537 "Only handle AVX 256-bit vector integer operation");
16538 return Lower256IntArith(Op, DAG);
16541 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16542 SelectionDAG &DAG) {
16544 MVT VT = Op.getSimpleValueType();
16546 // Decompose 256-bit ops into smaller 128-bit ops.
16547 if (VT.is256BitVector() && !Subtarget->hasInt256())
16548 return Lower256IntArith(Op, DAG);
16550 SDValue A = Op.getOperand(0);
16551 SDValue B = Op.getOperand(1);
16553 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16554 if (VT == MVT::v4i32) {
16555 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16556 "Should not custom lower when pmuldq is available!");
16558 // Extract the odd parts.
16559 static const int UnpackMask[] = { 1, -1, 3, -1 };
16560 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16561 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16563 // Multiply the even parts.
16564 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16565 // Now multiply odd parts.
16566 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16568 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16569 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16571 // Merge the two vectors back together with a shuffle. This expands into 2
16573 static const int ShufMask[] = { 0, 4, 2, 6 };
16574 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16577 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16578 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16580 // Ahi = psrlqi(a, 32);
16581 // Bhi = psrlqi(b, 32);
16583 // AloBlo = pmuludq(a, b);
16584 // AloBhi = pmuludq(a, Bhi);
16585 // AhiBlo = pmuludq(Ahi, b);
16587 // AloBhi = psllqi(AloBhi, 32);
16588 // AhiBlo = psllqi(AhiBlo, 32);
16589 // return AloBlo + AloBhi + AhiBlo;
16591 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16592 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16594 // Bit cast to 32-bit vectors for MULUDQ
16595 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16596 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16597 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16598 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16599 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16600 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16602 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16603 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16604 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16606 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16607 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16609 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16610 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16613 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16614 assert(Subtarget->isTargetWin64() && "Unexpected target");
16615 EVT VT = Op.getValueType();
16616 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16617 "Unexpected return type for lowering");
16621 switch (Op->getOpcode()) {
16622 default: llvm_unreachable("Unexpected request for libcall!");
16623 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16624 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16625 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16626 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16627 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16628 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16632 SDValue InChain = DAG.getEntryNode();
16634 TargetLowering::ArgListTy Args;
16635 TargetLowering::ArgListEntry Entry;
16636 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16637 EVT ArgVT = Op->getOperand(i).getValueType();
16638 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16639 "Unexpected argument type for lowering");
16640 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16641 Entry.Node = StackPtr;
16642 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16644 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16645 Entry.Ty = PointerType::get(ArgTy,0);
16646 Entry.isSExt = false;
16647 Entry.isZExt = false;
16648 Args.push_back(Entry);
16651 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16654 TargetLowering::CallLoweringInfo CLI(DAG);
16655 CLI.setDebugLoc(dl).setChain(InChain)
16656 .setCallee(getLibcallCallingConv(LC),
16657 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16658 Callee, std::move(Args), 0)
16659 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16661 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16662 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16665 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16666 SelectionDAG &DAG) {
16667 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16668 EVT VT = Op0.getValueType();
16671 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16672 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16674 // PMULxD operations multiply each even value (starting at 0) of LHS with
16675 // the related value of RHS and produce a widen result.
16676 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16677 // => <2 x i64> <ae|cg>
16679 // In other word, to have all the results, we need to perform two PMULxD:
16680 // 1. one with the even values.
16681 // 2. one with the odd values.
16682 // To achieve #2, with need to place the odd values at an even position.
16684 // Place the odd value at an even position (basically, shift all values 1
16685 // step to the left):
16686 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16687 // <a|b|c|d> => <b|undef|d|undef>
16688 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16689 // <e|f|g|h> => <f|undef|h|undef>
16690 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16692 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16694 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16695 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16697 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16698 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16699 // => <2 x i64> <ae|cg>
16700 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16701 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16702 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16703 // => <2 x i64> <bf|dh>
16704 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16705 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16707 // Shuffle it back into the right order.
16708 SDValue Highs, Lows;
16709 if (VT == MVT::v8i32) {
16710 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16711 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16712 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16713 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16715 const int HighMask[] = {1, 5, 3, 7};
16716 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16717 const int LowMask[] = {0, 4, 2, 6};
16718 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16721 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16722 // unsigned multiply.
16723 if (IsSigned && !Subtarget->hasSSE41()) {
16725 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16726 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16727 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16728 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16729 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16731 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16732 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16735 // The first result of MUL_LOHI is actually the low value, followed by the
16737 SDValue Ops[] = {Lows, Highs};
16738 return DAG.getMergeValues(Ops, dl);
16741 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16742 const X86Subtarget *Subtarget) {
16743 MVT VT = Op.getSimpleValueType();
16745 SDValue R = Op.getOperand(0);
16746 SDValue Amt = Op.getOperand(1);
16748 // Optimize shl/srl/sra with constant shift amount.
16749 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16750 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16751 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16753 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16754 (Subtarget->hasInt256() &&
16755 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16756 (Subtarget->hasAVX512() &&
16757 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16758 if (Op.getOpcode() == ISD::SHL)
16759 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16761 if (Op.getOpcode() == ISD::SRL)
16762 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16764 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16765 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16769 if (VT == MVT::v16i8) {
16770 if (Op.getOpcode() == ISD::SHL) {
16771 // Make a large shift.
16772 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16773 MVT::v8i16, R, ShiftAmt,
16775 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16776 // Zero out the rightmost bits.
16777 SmallVector<SDValue, 16> V(16,
16778 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16780 return DAG.getNode(ISD::AND, dl, VT, SHL,
16781 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16783 if (Op.getOpcode() == ISD::SRL) {
16784 // Make a large shift.
16785 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16786 MVT::v8i16, R, ShiftAmt,
16788 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16789 // Zero out the leftmost bits.
16790 SmallVector<SDValue, 16> V(16,
16791 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16793 return DAG.getNode(ISD::AND, dl, VT, SRL,
16794 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16796 if (Op.getOpcode() == ISD::SRA) {
16797 if (ShiftAmt == 7) {
16798 // R s>> 7 === R s< 0
16799 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16800 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16803 // R s>> a === ((R u>> a) ^ m) - m
16804 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16805 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16807 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16808 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16809 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16812 llvm_unreachable("Unknown shift opcode.");
16815 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16816 if (Op.getOpcode() == ISD::SHL) {
16817 // Make a large shift.
16818 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16819 MVT::v16i16, R, ShiftAmt,
16821 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16822 // Zero out the rightmost bits.
16823 SmallVector<SDValue, 32> V(32,
16824 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16826 return DAG.getNode(ISD::AND, dl, VT, SHL,
16827 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16829 if (Op.getOpcode() == ISD::SRL) {
16830 // Make a large shift.
16831 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16832 MVT::v16i16, R, ShiftAmt,
16834 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16835 // Zero out the leftmost bits.
16836 SmallVector<SDValue, 32> V(32,
16837 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16839 return DAG.getNode(ISD::AND, dl, VT, SRL,
16840 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16842 if (Op.getOpcode() == ISD::SRA) {
16843 if (ShiftAmt == 7) {
16844 // R s>> 7 === R s< 0
16845 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16846 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16849 // R s>> a === ((R u>> a) ^ m) - m
16850 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16851 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16853 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16854 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16855 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16858 llvm_unreachable("Unknown shift opcode.");
16863 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16864 if (!Subtarget->is64Bit() &&
16865 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16866 Amt.getOpcode() == ISD::BITCAST &&
16867 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16868 Amt = Amt.getOperand(0);
16869 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16870 VT.getVectorNumElements();
16871 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16872 uint64_t ShiftAmt = 0;
16873 for (unsigned i = 0; i != Ratio; ++i) {
16874 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16878 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16880 // Check remaining shift amounts.
16881 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16882 uint64_t ShAmt = 0;
16883 for (unsigned j = 0; j != Ratio; ++j) {
16884 ConstantSDNode *C =
16885 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16889 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16891 if (ShAmt != ShiftAmt)
16894 switch (Op.getOpcode()) {
16896 llvm_unreachable("Unknown shift opcode!");
16898 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16901 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16904 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16912 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16913 const X86Subtarget* Subtarget) {
16914 MVT VT = Op.getSimpleValueType();
16916 SDValue R = Op.getOperand(0);
16917 SDValue Amt = Op.getOperand(1);
16919 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16920 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16921 (Subtarget->hasInt256() &&
16922 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16923 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16924 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16926 EVT EltVT = VT.getVectorElementType();
16928 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16929 unsigned NumElts = VT.getVectorNumElements();
16931 for (i = 0; i != NumElts; ++i) {
16932 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16936 for (j = i; j != NumElts; ++j) {
16937 SDValue Arg = Amt.getOperand(j);
16938 if (Arg.getOpcode() == ISD::UNDEF) continue;
16939 if (Arg != Amt.getOperand(i))
16942 if (i != NumElts && j == NumElts)
16943 BaseShAmt = Amt.getOperand(i);
16945 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16946 Amt = Amt.getOperand(0);
16947 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16948 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16949 SDValue InVec = Amt.getOperand(0);
16950 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16951 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16953 for (; i != NumElts; ++i) {
16954 SDValue Arg = InVec.getOperand(i);
16955 if (Arg.getOpcode() == ISD::UNDEF) continue;
16959 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16960 if (ConstantSDNode *C =
16961 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16962 unsigned SplatIdx =
16963 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16964 if (C->getZExtValue() == SplatIdx)
16965 BaseShAmt = InVec.getOperand(1);
16968 if (!BaseShAmt.getNode())
16969 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16970 DAG.getIntPtrConstant(0));
16974 if (BaseShAmt.getNode()) {
16975 if (EltVT.bitsGT(MVT::i32))
16976 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16977 else if (EltVT.bitsLT(MVT::i32))
16978 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16980 switch (Op.getOpcode()) {
16982 llvm_unreachable("Unknown shift opcode!");
16984 switch (VT.SimpleTy) {
16985 default: return SDValue();
16994 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16997 switch (VT.SimpleTy) {
16998 default: return SDValue();
17005 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17008 switch (VT.SimpleTy) {
17009 default: return SDValue();
17018 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17024 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17025 if (!Subtarget->is64Bit() &&
17026 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17027 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17028 Amt.getOpcode() == ISD::BITCAST &&
17029 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17030 Amt = Amt.getOperand(0);
17031 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17032 VT.getVectorNumElements();
17033 std::vector<SDValue> Vals(Ratio);
17034 for (unsigned i = 0; i != Ratio; ++i)
17035 Vals[i] = Amt.getOperand(i);
17036 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17037 for (unsigned j = 0; j != Ratio; ++j)
17038 if (Vals[j] != Amt.getOperand(i + j))
17041 switch (Op.getOpcode()) {
17043 llvm_unreachable("Unknown shift opcode!");
17045 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17047 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17049 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17056 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17057 SelectionDAG &DAG) {
17058 MVT VT = Op.getSimpleValueType();
17060 SDValue R = Op.getOperand(0);
17061 SDValue Amt = Op.getOperand(1);
17064 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17065 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17067 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17071 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17075 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17077 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17078 if (Subtarget->hasInt256()) {
17079 if (Op.getOpcode() == ISD::SRL &&
17080 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17081 VT == MVT::v4i64 || VT == MVT::v8i32))
17083 if (Op.getOpcode() == ISD::SHL &&
17084 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17085 VT == MVT::v4i64 || VT == MVT::v8i32))
17087 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17091 // If possible, lower this packed shift into a vector multiply instead of
17092 // expanding it into a sequence of scalar shifts.
17093 // Do this only if the vector shift count is a constant build_vector.
17094 if (Op.getOpcode() == ISD::SHL &&
17095 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17096 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17097 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17098 SmallVector<SDValue, 8> Elts;
17099 EVT SVT = VT.getScalarType();
17100 unsigned SVTBits = SVT.getSizeInBits();
17101 const APInt &One = APInt(SVTBits, 1);
17102 unsigned NumElems = VT.getVectorNumElements();
17104 for (unsigned i=0; i !=NumElems; ++i) {
17105 SDValue Op = Amt->getOperand(i);
17106 if (Op->getOpcode() == ISD::UNDEF) {
17107 Elts.push_back(Op);
17111 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17112 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17113 uint64_t ShAmt = C.getZExtValue();
17114 if (ShAmt >= SVTBits) {
17115 Elts.push_back(DAG.getUNDEF(SVT));
17118 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17120 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17121 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17124 // Lower SHL with variable shift amount.
17125 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17126 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17128 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17129 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17130 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17131 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17134 // If possible, lower this shift as a sequence of two shifts by
17135 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17137 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17139 // Could be rewritten as:
17140 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17142 // The advantage is that the two shifts from the example would be
17143 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17144 // the vector shift into four scalar shifts plus four pairs of vector
17146 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17147 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17148 unsigned TargetOpcode = X86ISD::MOVSS;
17149 bool CanBeSimplified;
17150 // The splat value for the first packed shift (the 'X' from the example).
17151 SDValue Amt1 = Amt->getOperand(0);
17152 // The splat value for the second packed shift (the 'Y' from the example).
17153 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17154 Amt->getOperand(2);
17156 // See if it is possible to replace this node with a sequence of
17157 // two shifts followed by a MOVSS/MOVSD
17158 if (VT == MVT::v4i32) {
17159 // Check if it is legal to use a MOVSS.
17160 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17161 Amt2 == Amt->getOperand(3);
17162 if (!CanBeSimplified) {
17163 // Otherwise, check if we can still simplify this node using a MOVSD.
17164 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17165 Amt->getOperand(2) == Amt->getOperand(3);
17166 TargetOpcode = X86ISD::MOVSD;
17167 Amt2 = Amt->getOperand(2);
17170 // Do similar checks for the case where the machine value type
17172 CanBeSimplified = Amt1 == Amt->getOperand(1);
17173 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17174 CanBeSimplified = Amt2 == Amt->getOperand(i);
17176 if (!CanBeSimplified) {
17177 TargetOpcode = X86ISD::MOVSD;
17178 CanBeSimplified = true;
17179 Amt2 = Amt->getOperand(4);
17180 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17181 CanBeSimplified = Amt1 == Amt->getOperand(i);
17182 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17183 CanBeSimplified = Amt2 == Amt->getOperand(j);
17187 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17188 isa<ConstantSDNode>(Amt2)) {
17189 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17190 EVT CastVT = MVT::v4i32;
17192 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17193 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17195 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17196 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17197 if (TargetOpcode == X86ISD::MOVSD)
17198 CastVT = MVT::v2i64;
17199 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17200 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17201 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17203 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17207 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17208 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17211 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17212 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17214 // Turn 'a' into a mask suitable for VSELECT
17215 SDValue VSelM = DAG.getConstant(0x80, VT);
17216 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17217 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17219 SDValue CM1 = DAG.getConstant(0x0f, VT);
17220 SDValue CM2 = DAG.getConstant(0x3f, VT);
17222 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17223 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17224 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17225 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17226 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17229 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17230 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17231 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17233 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17234 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17235 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17236 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17237 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17240 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17241 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17242 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17244 // return VSELECT(r, r+r, a);
17245 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17246 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17250 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17251 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17252 // solution better.
17253 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17254 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17256 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17257 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17258 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17259 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17260 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17263 // Decompose 256-bit shifts into smaller 128-bit shifts.
17264 if (VT.is256BitVector()) {
17265 unsigned NumElems = VT.getVectorNumElements();
17266 MVT EltVT = VT.getVectorElementType();
17267 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17269 // Extract the two vectors
17270 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17271 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17273 // Recreate the shift amount vectors
17274 SDValue Amt1, Amt2;
17275 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17276 // Constant shift amount
17277 SmallVector<SDValue, 4> Amt1Csts;
17278 SmallVector<SDValue, 4> Amt2Csts;
17279 for (unsigned i = 0; i != NumElems/2; ++i)
17280 Amt1Csts.push_back(Amt->getOperand(i));
17281 for (unsigned i = NumElems/2; i != NumElems; ++i)
17282 Amt2Csts.push_back(Amt->getOperand(i));
17284 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17285 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17287 // Variable shift amount
17288 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17289 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17292 // Issue new vector shifts for the smaller types
17293 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17294 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17296 // Concatenate the result back
17297 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17303 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17304 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17305 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17306 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17307 // has only one use.
17308 SDNode *N = Op.getNode();
17309 SDValue LHS = N->getOperand(0);
17310 SDValue RHS = N->getOperand(1);
17311 unsigned BaseOp = 0;
17314 switch (Op.getOpcode()) {
17315 default: llvm_unreachable("Unknown ovf instruction!");
17317 // A subtract of one will be selected as a INC. Note that INC doesn't
17318 // set CF, so we can't do this for UADDO.
17319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17321 BaseOp = X86ISD::INC;
17322 Cond = X86::COND_O;
17325 BaseOp = X86ISD::ADD;
17326 Cond = X86::COND_O;
17329 BaseOp = X86ISD::ADD;
17330 Cond = X86::COND_B;
17333 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17334 // set CF, so we can't do this for USUBO.
17335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17337 BaseOp = X86ISD::DEC;
17338 Cond = X86::COND_O;
17341 BaseOp = X86ISD::SUB;
17342 Cond = X86::COND_O;
17345 BaseOp = X86ISD::SUB;
17346 Cond = X86::COND_B;
17349 BaseOp = X86ISD::SMUL;
17350 Cond = X86::COND_O;
17352 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17353 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17355 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17358 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17359 DAG.getConstant(X86::COND_O, MVT::i32),
17360 SDValue(Sum.getNode(), 2));
17362 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17366 // Also sets EFLAGS.
17367 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17368 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17371 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17372 DAG.getConstant(Cond, MVT::i32),
17373 SDValue(Sum.getNode(), 1));
17375 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17378 // Sign extension of the low part of vector elements. This may be used either
17379 // when sign extend instructions are not available or if the vector element
17380 // sizes already match the sign-extended size. If the vector elements are in
17381 // their pre-extended size and sign extend instructions are available, that will
17382 // be handled by LowerSIGN_EXTEND.
17383 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17384 SelectionDAG &DAG) const {
17386 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17387 MVT VT = Op.getSimpleValueType();
17389 if (!Subtarget->hasSSE2() || !VT.isVector())
17392 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17393 ExtraVT.getScalarType().getSizeInBits();
17395 switch (VT.SimpleTy) {
17396 default: return SDValue();
17399 if (!Subtarget->hasFp256())
17401 if (!Subtarget->hasInt256()) {
17402 // needs to be split
17403 unsigned NumElems = VT.getVectorNumElements();
17405 // Extract the LHS vectors
17406 SDValue LHS = Op.getOperand(0);
17407 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17408 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17410 MVT EltVT = VT.getVectorElementType();
17411 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17413 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17414 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17415 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17417 SDValue Extra = DAG.getValueType(ExtraVT);
17419 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17420 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17422 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17427 SDValue Op0 = Op.getOperand(0);
17429 // This is a sign extension of some low part of vector elements without
17430 // changing the size of the vector elements themselves:
17431 // Shift-Left + Shift-Right-Algebraic.
17432 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17434 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17440 /// Returns true if the operand type is exactly twice the native width, and
17441 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17442 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17443 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17444 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17445 const X86Subtarget &Subtarget =
17446 getTargetMachine().getSubtarget<X86Subtarget>();
17447 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17450 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17451 else if (OpWidth == 128)
17452 return Subtarget.hasCmpxchg16b();
17457 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17458 return needsCmpXchgNb(SI->getValueOperand()->getType());
17461 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17462 return false; // FIXME, currently these are expanded separately in this file.
17465 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17466 const X86Subtarget &Subtarget =
17467 getTargetMachine().getSubtarget<X86Subtarget>();
17468 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17469 const Type *MemType = AI->getType();
17471 // If the operand is too big, we must see if cmpxchg8/16b is available
17472 // and default to library calls otherwise.
17473 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17474 return needsCmpXchgNb(MemType);
17476 AtomicRMWInst::BinOp Op = AI->getOperation();
17479 llvm_unreachable("Unknown atomic operation");
17480 case AtomicRMWInst::Xchg:
17481 case AtomicRMWInst::Add:
17482 case AtomicRMWInst::Sub:
17483 // It's better to use xadd, xsub or xchg for these in all cases.
17485 case AtomicRMWInst::Or:
17486 case AtomicRMWInst::And:
17487 case AtomicRMWInst::Xor:
17488 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17489 // prefix to a normal instruction for these operations.
17490 return !AI->use_empty();
17491 case AtomicRMWInst::Nand:
17492 case AtomicRMWInst::Max:
17493 case AtomicRMWInst::Min:
17494 case AtomicRMWInst::UMax:
17495 case AtomicRMWInst::UMin:
17496 // These always require a non-trivial set of data operations on x86. We must
17497 // use a cmpxchg loop.
17502 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17503 SelectionDAG &DAG) {
17505 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17506 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17507 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17508 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17510 // The only fence that needs an instruction is a sequentially-consistent
17511 // cross-thread fence.
17512 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17513 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17514 // no-sse2). There isn't any reason to disable it if the target processor
17516 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17517 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17519 SDValue Chain = Op.getOperand(0);
17520 SDValue Zero = DAG.getConstant(0, MVT::i32);
17522 DAG.getRegister(X86::ESP, MVT::i32), // Base
17523 DAG.getTargetConstant(1, MVT::i8), // Scale
17524 DAG.getRegister(0, MVT::i32), // Index
17525 DAG.getTargetConstant(0, MVT::i32), // Disp
17526 DAG.getRegister(0, MVT::i32), // Segment.
17530 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17531 return SDValue(Res, 0);
17534 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17535 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17538 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17539 SelectionDAG &DAG) {
17540 MVT T = Op.getSimpleValueType();
17544 switch(T.SimpleTy) {
17545 default: llvm_unreachable("Invalid value type!");
17546 case MVT::i8: Reg = X86::AL; size = 1; break;
17547 case MVT::i16: Reg = X86::AX; size = 2; break;
17548 case MVT::i32: Reg = X86::EAX; size = 4; break;
17550 assert(Subtarget->is64Bit() && "Node not type legal!");
17551 Reg = X86::RAX; size = 8;
17554 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17555 Op.getOperand(2), SDValue());
17556 SDValue Ops[] = { cpIn.getValue(0),
17559 DAG.getTargetConstant(size, MVT::i8),
17560 cpIn.getValue(1) };
17561 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17562 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17563 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17567 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17568 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17569 MVT::i32, cpOut.getValue(2));
17570 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17571 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17573 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17574 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17575 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17579 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17580 SelectionDAG &DAG) {
17581 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17582 MVT DstVT = Op.getSimpleValueType();
17584 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17585 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17586 if (DstVT != MVT::f64)
17587 // This conversion needs to be expanded.
17590 SDValue InVec = Op->getOperand(0);
17592 unsigned NumElts = SrcVT.getVectorNumElements();
17593 EVT SVT = SrcVT.getVectorElementType();
17595 // Widen the vector in input in the case of MVT::v2i32.
17596 // Example: from MVT::v2i32 to MVT::v4i32.
17597 SmallVector<SDValue, 16> Elts;
17598 for (unsigned i = 0, e = NumElts; i != e; ++i)
17599 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17600 DAG.getIntPtrConstant(i)));
17602 // Explicitly mark the extra elements as Undef.
17603 SDValue Undef = DAG.getUNDEF(SVT);
17604 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17605 Elts.push_back(Undef);
17607 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17608 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17609 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17610 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17611 DAG.getIntPtrConstant(0));
17614 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17615 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17616 assert((DstVT == MVT::i64 ||
17617 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17618 "Unexpected custom BITCAST");
17619 // i64 <=> MMX conversions are Legal.
17620 if (SrcVT==MVT::i64 && DstVT.isVector())
17622 if (DstVT==MVT::i64 && SrcVT.isVector())
17624 // MMX <=> MMX conversions are Legal.
17625 if (SrcVT.isVector() && DstVT.isVector())
17627 // All other conversions need to be expanded.
17631 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17632 SDNode *Node = Op.getNode();
17634 EVT T = Node->getValueType(0);
17635 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17636 DAG.getConstant(0, T), Node->getOperand(2));
17637 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17638 cast<AtomicSDNode>(Node)->getMemoryVT(),
17639 Node->getOperand(0),
17640 Node->getOperand(1), negOp,
17641 cast<AtomicSDNode>(Node)->getMemOperand(),
17642 cast<AtomicSDNode>(Node)->getOrdering(),
17643 cast<AtomicSDNode>(Node)->getSynchScope());
17646 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17647 SDNode *Node = Op.getNode();
17649 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17651 // Convert seq_cst store -> xchg
17652 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17653 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17654 // (The only way to get a 16-byte store is cmpxchg16b)
17655 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17656 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17657 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17658 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17659 cast<AtomicSDNode>(Node)->getMemoryVT(),
17660 Node->getOperand(0),
17661 Node->getOperand(1), Node->getOperand(2),
17662 cast<AtomicSDNode>(Node)->getMemOperand(),
17663 cast<AtomicSDNode>(Node)->getOrdering(),
17664 cast<AtomicSDNode>(Node)->getSynchScope());
17665 return Swap.getValue(1);
17667 // Other atomic stores have a simple pattern.
17671 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17672 EVT VT = Op.getNode()->getSimpleValueType(0);
17674 // Let legalize expand this if it isn't a legal type yet.
17675 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17678 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17681 bool ExtraOp = false;
17682 switch (Op.getOpcode()) {
17683 default: llvm_unreachable("Invalid code");
17684 case ISD::ADDC: Opc = X86ISD::ADD; break;
17685 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17686 case ISD::SUBC: Opc = X86ISD::SUB; break;
17687 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17691 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17693 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17694 Op.getOperand(1), Op.getOperand(2));
17697 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17698 SelectionDAG &DAG) {
17699 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17701 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17702 // which returns the values as { float, float } (in XMM0) or
17703 // { double, double } (which is returned in XMM0, XMM1).
17705 SDValue Arg = Op.getOperand(0);
17706 EVT ArgVT = Arg.getValueType();
17707 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17709 TargetLowering::ArgListTy Args;
17710 TargetLowering::ArgListEntry Entry;
17714 Entry.isSExt = false;
17715 Entry.isZExt = false;
17716 Args.push_back(Entry);
17718 bool isF64 = ArgVT == MVT::f64;
17719 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17720 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17721 // the results are returned via SRet in memory.
17722 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17723 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17724 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17726 Type *RetTy = isF64
17727 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17728 : (Type*)VectorType::get(ArgTy, 4);
17730 TargetLowering::CallLoweringInfo CLI(DAG);
17731 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17732 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17734 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17737 // Returned in xmm0 and xmm1.
17738 return CallResult.first;
17740 // Returned in bits 0:31 and 32:64 xmm0.
17741 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17742 CallResult.first, DAG.getIntPtrConstant(0));
17743 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17744 CallResult.first, DAG.getIntPtrConstant(1));
17745 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17746 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17749 /// LowerOperation - Provide custom lowering hooks for some operations.
17751 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17752 switch (Op.getOpcode()) {
17753 default: llvm_unreachable("Should not custom lower this!");
17754 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17755 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17756 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17757 return LowerCMP_SWAP(Op, Subtarget, DAG);
17758 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17759 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17760 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17761 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17762 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17763 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17764 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17765 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17766 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17767 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17768 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17769 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17770 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17771 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17772 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17773 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17774 case ISD::SHL_PARTS:
17775 case ISD::SRA_PARTS:
17776 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17777 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17778 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17779 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17780 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17781 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17782 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17783 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17784 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17785 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17786 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17788 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17789 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17790 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17791 case ISD::SETCC: return LowerSETCC(Op, DAG);
17792 case ISD::SELECT: return LowerSELECT(Op, DAG);
17793 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17794 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17795 case ISD::VASTART: return LowerVASTART(Op, DAG);
17796 case ISD::VAARG: return LowerVAARG(Op, DAG);
17797 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17798 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17799 case ISD::INTRINSIC_VOID:
17800 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17801 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17802 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17803 case ISD::FRAME_TO_ARGS_OFFSET:
17804 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17805 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17806 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17807 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17808 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17809 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17810 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17811 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17812 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17813 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17814 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17815 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17816 case ISD::UMUL_LOHI:
17817 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17820 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17826 case ISD::UMULO: return LowerXALUO(Op, DAG);
17827 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17828 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17832 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17833 case ISD::ADD: return LowerADD(Op, DAG);
17834 case ISD::SUB: return LowerSUB(Op, DAG);
17835 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17839 static void ReplaceATOMIC_LOAD(SDNode *Node,
17840 SmallVectorImpl<SDValue> &Results,
17841 SelectionDAG &DAG) {
17843 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17845 // Convert wide load -> cmpxchg8b/cmpxchg16b
17846 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17847 // (The only way to get a 16-byte load is cmpxchg16b)
17848 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17849 SDValue Zero = DAG.getConstant(0, VT);
17850 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17852 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17853 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17854 cast<AtomicSDNode>(Node)->getMemOperand(),
17855 cast<AtomicSDNode>(Node)->getOrdering(),
17856 cast<AtomicSDNode>(Node)->getOrdering(),
17857 cast<AtomicSDNode>(Node)->getSynchScope());
17858 Results.push_back(Swap.getValue(0));
17859 Results.push_back(Swap.getValue(2));
17862 /// ReplaceNodeResults - Replace a node with an illegal result type
17863 /// with a new node built out of custom code.
17864 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17865 SmallVectorImpl<SDValue>&Results,
17866 SelectionDAG &DAG) const {
17868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17869 switch (N->getOpcode()) {
17871 llvm_unreachable("Do not know how to custom type legalize this operation!");
17872 case ISD::SIGN_EXTEND_INREG:
17877 // We don't want to expand or promote these.
17884 case ISD::UDIVREM: {
17885 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17886 Results.push_back(V);
17889 case ISD::FP_TO_SINT:
17890 case ISD::FP_TO_UINT: {
17891 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17893 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17896 std::pair<SDValue,SDValue> Vals =
17897 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17898 SDValue FIST = Vals.first, StackSlot = Vals.second;
17899 if (FIST.getNode()) {
17900 EVT VT = N->getValueType(0);
17901 // Return a load from the stack slot.
17902 if (StackSlot.getNode())
17903 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17904 MachinePointerInfo(),
17905 false, false, false, 0));
17907 Results.push_back(FIST);
17911 case ISD::UINT_TO_FP: {
17912 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17913 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17914 N->getValueType(0) != MVT::v2f32)
17916 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17918 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17920 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17921 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17922 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17923 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17924 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17925 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17928 case ISD::FP_ROUND: {
17929 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17931 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17932 Results.push_back(V);
17935 case ISD::INTRINSIC_W_CHAIN: {
17936 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17938 default : llvm_unreachable("Do not know how to custom type "
17939 "legalize this intrinsic operation!");
17940 case Intrinsic::x86_rdtsc:
17941 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17943 case Intrinsic::x86_rdtscp:
17944 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17946 case Intrinsic::x86_rdpmc:
17947 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17950 case ISD::READCYCLECOUNTER: {
17951 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17954 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17955 EVT T = N->getValueType(0);
17956 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17957 bool Regs64bit = T == MVT::i128;
17958 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17959 SDValue cpInL, cpInH;
17960 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17961 DAG.getConstant(0, HalfT));
17962 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17963 DAG.getConstant(1, HalfT));
17964 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17965 Regs64bit ? X86::RAX : X86::EAX,
17967 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17968 Regs64bit ? X86::RDX : X86::EDX,
17969 cpInH, cpInL.getValue(1));
17970 SDValue swapInL, swapInH;
17971 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17972 DAG.getConstant(0, HalfT));
17973 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17974 DAG.getConstant(1, HalfT));
17975 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17976 Regs64bit ? X86::RBX : X86::EBX,
17977 swapInL, cpInH.getValue(1));
17978 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17979 Regs64bit ? X86::RCX : X86::ECX,
17980 swapInH, swapInL.getValue(1));
17981 SDValue Ops[] = { swapInH.getValue(0),
17983 swapInH.getValue(1) };
17984 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17985 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17986 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17987 X86ISD::LCMPXCHG8_DAG;
17988 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17989 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17990 Regs64bit ? X86::RAX : X86::EAX,
17991 HalfT, Result.getValue(1));
17992 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17993 Regs64bit ? X86::RDX : X86::EDX,
17994 HalfT, cpOutL.getValue(2));
17995 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17997 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17998 MVT::i32, cpOutH.getValue(2));
18000 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18001 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18002 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18004 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18005 Results.push_back(Success);
18006 Results.push_back(EFLAGS.getValue(1));
18009 case ISD::ATOMIC_SWAP:
18010 case ISD::ATOMIC_LOAD_ADD:
18011 case ISD::ATOMIC_LOAD_SUB:
18012 case ISD::ATOMIC_LOAD_AND:
18013 case ISD::ATOMIC_LOAD_OR:
18014 case ISD::ATOMIC_LOAD_XOR:
18015 case ISD::ATOMIC_LOAD_NAND:
18016 case ISD::ATOMIC_LOAD_MIN:
18017 case ISD::ATOMIC_LOAD_MAX:
18018 case ISD::ATOMIC_LOAD_UMIN:
18019 case ISD::ATOMIC_LOAD_UMAX:
18020 // Delegate to generic TypeLegalization. Situations we can really handle
18021 // should have already been dealt with by AtomicExpandPass.cpp.
18023 case ISD::ATOMIC_LOAD: {
18024 ReplaceATOMIC_LOAD(N, Results, DAG);
18027 case ISD::BITCAST: {
18028 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18029 EVT DstVT = N->getValueType(0);
18030 EVT SrcVT = N->getOperand(0)->getValueType(0);
18032 if (SrcVT != MVT::f64 ||
18033 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18036 unsigned NumElts = DstVT.getVectorNumElements();
18037 EVT SVT = DstVT.getVectorElementType();
18038 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18039 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18040 MVT::v2f64, N->getOperand(0));
18041 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18043 if (ExperimentalVectorWideningLegalization) {
18044 // If we are legalizing vectors by widening, we already have the desired
18045 // legal vector type, just return it.
18046 Results.push_back(ToVecInt);
18050 SmallVector<SDValue, 8> Elts;
18051 for (unsigned i = 0, e = NumElts; i != e; ++i)
18052 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18053 ToVecInt, DAG.getIntPtrConstant(i)));
18055 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18060 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18062 default: return nullptr;
18063 case X86ISD::BSF: return "X86ISD::BSF";
18064 case X86ISD::BSR: return "X86ISD::BSR";
18065 case X86ISD::SHLD: return "X86ISD::SHLD";
18066 case X86ISD::SHRD: return "X86ISD::SHRD";
18067 case X86ISD::FAND: return "X86ISD::FAND";
18068 case X86ISD::FANDN: return "X86ISD::FANDN";
18069 case X86ISD::FOR: return "X86ISD::FOR";
18070 case X86ISD::FXOR: return "X86ISD::FXOR";
18071 case X86ISD::FSRL: return "X86ISD::FSRL";
18072 case X86ISD::FILD: return "X86ISD::FILD";
18073 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18074 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18075 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18076 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18077 case X86ISD::FLD: return "X86ISD::FLD";
18078 case X86ISD::FST: return "X86ISD::FST";
18079 case X86ISD::CALL: return "X86ISD::CALL";
18080 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18081 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18082 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18083 case X86ISD::BT: return "X86ISD::BT";
18084 case X86ISD::CMP: return "X86ISD::CMP";
18085 case X86ISD::COMI: return "X86ISD::COMI";
18086 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18087 case X86ISD::CMPM: return "X86ISD::CMPM";
18088 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18089 case X86ISD::SETCC: return "X86ISD::SETCC";
18090 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18091 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18092 case X86ISD::CMOV: return "X86ISD::CMOV";
18093 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18094 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18095 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18096 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18097 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18098 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18099 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18100 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18101 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18102 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18103 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18104 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18105 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18106 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18107 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18108 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18109 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18110 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18111 case X86ISD::HADD: return "X86ISD::HADD";
18112 case X86ISD::HSUB: return "X86ISD::HSUB";
18113 case X86ISD::FHADD: return "X86ISD::FHADD";
18114 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18115 case X86ISD::UMAX: return "X86ISD::UMAX";
18116 case X86ISD::UMIN: return "X86ISD::UMIN";
18117 case X86ISD::SMAX: return "X86ISD::SMAX";
18118 case X86ISD::SMIN: return "X86ISD::SMIN";
18119 case X86ISD::FMAX: return "X86ISD::FMAX";
18120 case X86ISD::FMIN: return "X86ISD::FMIN";
18121 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18122 case X86ISD::FMINC: return "X86ISD::FMINC";
18123 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18124 case X86ISD::FRCP: return "X86ISD::FRCP";
18125 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18126 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18127 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18128 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18129 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18130 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18131 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18132 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18133 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18134 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18135 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18136 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18137 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18138 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18139 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18140 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18141 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18142 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18143 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18144 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18145 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18146 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18147 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18148 case X86ISD::VSHL: return "X86ISD::VSHL";
18149 case X86ISD::VSRL: return "X86ISD::VSRL";
18150 case X86ISD::VSRA: return "X86ISD::VSRA";
18151 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18152 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18153 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18154 case X86ISD::CMPP: return "X86ISD::CMPP";
18155 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18156 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18157 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18158 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18159 case X86ISD::ADD: return "X86ISD::ADD";
18160 case X86ISD::SUB: return "X86ISD::SUB";
18161 case X86ISD::ADC: return "X86ISD::ADC";
18162 case X86ISD::SBB: return "X86ISD::SBB";
18163 case X86ISD::SMUL: return "X86ISD::SMUL";
18164 case X86ISD::UMUL: return "X86ISD::UMUL";
18165 case X86ISD::INC: return "X86ISD::INC";
18166 case X86ISD::DEC: return "X86ISD::DEC";
18167 case X86ISD::OR: return "X86ISD::OR";
18168 case X86ISD::XOR: return "X86ISD::XOR";
18169 case X86ISD::AND: return "X86ISD::AND";
18170 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18171 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18172 case X86ISD::PTEST: return "X86ISD::PTEST";
18173 case X86ISD::TESTP: return "X86ISD::TESTP";
18174 case X86ISD::TESTM: return "X86ISD::TESTM";
18175 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18176 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18177 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18178 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18179 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18180 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18181 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18182 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18183 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18184 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18185 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18186 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18187 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18188 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18189 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18190 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18191 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18192 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18193 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18194 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18195 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18196 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18197 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18198 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18199 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18200 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18201 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18202 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18203 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18204 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18205 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18206 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18207 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18208 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18209 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18210 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18211 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18212 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18213 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18214 case X86ISD::SAHF: return "X86ISD::SAHF";
18215 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18216 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18217 case X86ISD::FMADD: return "X86ISD::FMADD";
18218 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18219 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18220 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18221 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18222 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18223 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18224 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18225 case X86ISD::XTEST: return "X86ISD::XTEST";
18229 // isLegalAddressingMode - Return true if the addressing mode represented
18230 // by AM is legal for this target, for a load/store of the specified type.
18231 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18233 // X86 supports extremely general addressing modes.
18234 CodeModel::Model M = getTargetMachine().getCodeModel();
18235 Reloc::Model R = getTargetMachine().getRelocationModel();
18237 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18238 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18243 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18245 // If a reference to this global requires an extra load, we can't fold it.
18246 if (isGlobalStubReference(GVFlags))
18249 // If BaseGV requires a register for the PIC base, we cannot also have a
18250 // BaseReg specified.
18251 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18254 // If lower 4G is not available, then we must use rip-relative addressing.
18255 if ((M != CodeModel::Small || R != Reloc::Static) &&
18256 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18260 switch (AM.Scale) {
18266 // These scales always work.
18271 // These scales are formed with basereg+scalereg. Only accept if there is
18276 default: // Other stuff never works.
18283 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18284 unsigned Bits = Ty->getScalarSizeInBits();
18286 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18287 // particularly cheaper than those without.
18291 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18292 // variable shifts just as cheap as scalar ones.
18293 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18296 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18297 // fully general vector.
18301 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18302 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18304 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18305 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18306 return NumBits1 > NumBits2;
18309 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18310 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18313 if (!isTypeLegal(EVT::getEVT(Ty1)))
18316 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18318 // Assuming the caller doesn't have a zeroext or signext return parameter,
18319 // truncation all the way down to i1 is valid.
18323 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18324 return isInt<32>(Imm);
18327 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18328 // Can also use sub to handle negated immediates.
18329 return isInt<32>(Imm);
18332 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18333 if (!VT1.isInteger() || !VT2.isInteger())
18335 unsigned NumBits1 = VT1.getSizeInBits();
18336 unsigned NumBits2 = VT2.getSizeInBits();
18337 return NumBits1 > NumBits2;
18340 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18341 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18342 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18345 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18346 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18347 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18350 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18351 EVT VT1 = Val.getValueType();
18352 if (isZExtFree(VT1, VT2))
18355 if (Val.getOpcode() != ISD::LOAD)
18358 if (!VT1.isSimple() || !VT1.isInteger() ||
18359 !VT2.isSimple() || !VT2.isInteger())
18362 switch (VT1.getSimpleVT().SimpleTy) {
18367 // X86 has 8, 16, and 32-bit zero-extending loads.
18375 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18376 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18379 VT = VT.getScalarType();
18381 if (!VT.isSimple())
18384 switch (VT.getSimpleVT().SimpleTy) {
18395 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18396 // i16 instructions are longer (0x66 prefix) and potentially slower.
18397 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18400 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18401 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18402 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18403 /// are assumed to be legal.
18405 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18407 if (!VT.isSimple())
18410 MVT SVT = VT.getSimpleVT();
18412 // Very little shuffling can be done for 64-bit vectors right now.
18413 if (VT.getSizeInBits() == 64)
18416 // If this is a single-input shuffle with no 128 bit lane crossings we can
18417 // lower it into pshufb.
18418 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18419 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18420 bool isLegal = true;
18421 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18422 if (M[I] >= (int)SVT.getVectorNumElements() ||
18423 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18432 // FIXME: blends, shifts.
18433 return (SVT.getVectorNumElements() == 2 ||
18434 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18435 isMOVLMask(M, SVT) ||
18436 isMOVHLPSMask(M, SVT) ||
18437 isSHUFPMask(M, SVT) ||
18438 isPSHUFDMask(M, SVT) ||
18439 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18440 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18441 isPALIGNRMask(M, SVT, Subtarget) ||
18442 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18443 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18444 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18445 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18446 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18450 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18452 if (!VT.isSimple())
18455 MVT SVT = VT.getSimpleVT();
18456 unsigned NumElts = SVT.getVectorNumElements();
18457 // FIXME: This collection of masks seems suspect.
18460 if (NumElts == 4 && SVT.is128BitVector()) {
18461 return (isMOVLMask(Mask, SVT) ||
18462 isCommutedMOVLMask(Mask, SVT, true) ||
18463 isSHUFPMask(Mask, SVT) ||
18464 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18469 //===----------------------------------------------------------------------===//
18470 // X86 Scheduler Hooks
18471 //===----------------------------------------------------------------------===//
18473 /// Utility function to emit xbegin specifying the start of an RTM region.
18474 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18475 const TargetInstrInfo *TII) {
18476 DebugLoc DL = MI->getDebugLoc();
18478 const BasicBlock *BB = MBB->getBasicBlock();
18479 MachineFunction::iterator I = MBB;
18482 // For the v = xbegin(), we generate
18493 MachineBasicBlock *thisMBB = MBB;
18494 MachineFunction *MF = MBB->getParent();
18495 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18496 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18497 MF->insert(I, mainMBB);
18498 MF->insert(I, sinkMBB);
18500 // Transfer the remainder of BB and its successor edges to sinkMBB.
18501 sinkMBB->splice(sinkMBB->begin(), MBB,
18502 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18503 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18507 // # fallthrough to mainMBB
18508 // # abortion to sinkMBB
18509 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18510 thisMBB->addSuccessor(mainMBB);
18511 thisMBB->addSuccessor(sinkMBB);
18515 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18516 mainMBB->addSuccessor(sinkMBB);
18519 // EAX is live into the sinkMBB
18520 sinkMBB->addLiveIn(X86::EAX);
18521 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18522 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18525 MI->eraseFromParent();
18529 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18530 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18531 // in the .td file.
18532 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18533 const TargetInstrInfo *TII) {
18535 switch (MI->getOpcode()) {
18536 default: llvm_unreachable("illegal opcode!");
18537 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18538 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18539 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18540 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18541 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18542 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18543 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18544 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18547 DebugLoc dl = MI->getDebugLoc();
18548 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18550 unsigned NumArgs = MI->getNumOperands();
18551 for (unsigned i = 1; i < NumArgs; ++i) {
18552 MachineOperand &Op = MI->getOperand(i);
18553 if (!(Op.isReg() && Op.isImplicit()))
18554 MIB.addOperand(Op);
18556 if (MI->hasOneMemOperand())
18557 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18559 BuildMI(*BB, MI, dl,
18560 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18561 .addReg(X86::XMM0);
18563 MI->eraseFromParent();
18567 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18568 // defs in an instruction pattern
18569 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18570 const TargetInstrInfo *TII) {
18572 switch (MI->getOpcode()) {
18573 default: llvm_unreachable("illegal opcode!");
18574 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18575 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18576 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18577 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18578 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18579 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18580 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18581 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18584 DebugLoc dl = MI->getDebugLoc();
18585 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18587 unsigned NumArgs = MI->getNumOperands(); // remove the results
18588 for (unsigned i = 1; i < NumArgs; ++i) {
18589 MachineOperand &Op = MI->getOperand(i);
18590 if (!(Op.isReg() && Op.isImplicit()))
18591 MIB.addOperand(Op);
18593 if (MI->hasOneMemOperand())
18594 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18596 BuildMI(*BB, MI, dl,
18597 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18600 MI->eraseFromParent();
18604 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18605 const TargetInstrInfo *TII,
18606 const X86Subtarget* Subtarget) {
18607 DebugLoc dl = MI->getDebugLoc();
18609 // Address into RAX/EAX, other two args into ECX, EDX.
18610 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18611 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18612 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18613 for (int i = 0; i < X86::AddrNumOperands; ++i)
18614 MIB.addOperand(MI->getOperand(i));
18616 unsigned ValOps = X86::AddrNumOperands;
18617 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18618 .addReg(MI->getOperand(ValOps).getReg());
18619 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18620 .addReg(MI->getOperand(ValOps+1).getReg());
18622 // The instruction doesn't actually take any operands though.
18623 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18625 MI->eraseFromParent(); // The pseudo is gone now.
18629 MachineBasicBlock *
18630 X86TargetLowering::EmitVAARG64WithCustomInserter(
18632 MachineBasicBlock *MBB) const {
18633 // Emit va_arg instruction on X86-64.
18635 // Operands to this pseudo-instruction:
18636 // 0 ) Output : destination address (reg)
18637 // 1-5) Input : va_list address (addr, i64mem)
18638 // 6 ) ArgSize : Size (in bytes) of vararg type
18639 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18640 // 8 ) Align : Alignment of type
18641 // 9 ) EFLAGS (implicit-def)
18643 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18644 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18646 unsigned DestReg = MI->getOperand(0).getReg();
18647 MachineOperand &Base = MI->getOperand(1);
18648 MachineOperand &Scale = MI->getOperand(2);
18649 MachineOperand &Index = MI->getOperand(3);
18650 MachineOperand &Disp = MI->getOperand(4);
18651 MachineOperand &Segment = MI->getOperand(5);
18652 unsigned ArgSize = MI->getOperand(6).getImm();
18653 unsigned ArgMode = MI->getOperand(7).getImm();
18654 unsigned Align = MI->getOperand(8).getImm();
18656 // Memory Reference
18657 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18658 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18659 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18661 // Machine Information
18662 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18663 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18664 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18665 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18666 DebugLoc DL = MI->getDebugLoc();
18668 // struct va_list {
18671 // i64 overflow_area (address)
18672 // i64 reg_save_area (address)
18674 // sizeof(va_list) = 24
18675 // alignment(va_list) = 8
18677 unsigned TotalNumIntRegs = 6;
18678 unsigned TotalNumXMMRegs = 8;
18679 bool UseGPOffset = (ArgMode == 1);
18680 bool UseFPOffset = (ArgMode == 2);
18681 unsigned MaxOffset = TotalNumIntRegs * 8 +
18682 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18684 /* Align ArgSize to a multiple of 8 */
18685 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18686 bool NeedsAlign = (Align > 8);
18688 MachineBasicBlock *thisMBB = MBB;
18689 MachineBasicBlock *overflowMBB;
18690 MachineBasicBlock *offsetMBB;
18691 MachineBasicBlock *endMBB;
18693 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18694 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18695 unsigned OffsetReg = 0;
18697 if (!UseGPOffset && !UseFPOffset) {
18698 // If we only pull from the overflow region, we don't create a branch.
18699 // We don't need to alter control flow.
18700 OffsetDestReg = 0; // unused
18701 OverflowDestReg = DestReg;
18703 offsetMBB = nullptr;
18704 overflowMBB = thisMBB;
18707 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18708 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18709 // If not, pull from overflow_area. (branch to overflowMBB)
18714 // offsetMBB overflowMBB
18719 // Registers for the PHI in endMBB
18720 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18721 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18723 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18724 MachineFunction *MF = MBB->getParent();
18725 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18726 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18727 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18729 MachineFunction::iterator MBBIter = MBB;
18732 // Insert the new basic blocks
18733 MF->insert(MBBIter, offsetMBB);
18734 MF->insert(MBBIter, overflowMBB);
18735 MF->insert(MBBIter, endMBB);
18737 // Transfer the remainder of MBB and its successor edges to endMBB.
18738 endMBB->splice(endMBB->begin(), thisMBB,
18739 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18740 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18742 // Make offsetMBB and overflowMBB successors of thisMBB
18743 thisMBB->addSuccessor(offsetMBB);
18744 thisMBB->addSuccessor(overflowMBB);
18746 // endMBB is a successor of both offsetMBB and overflowMBB
18747 offsetMBB->addSuccessor(endMBB);
18748 overflowMBB->addSuccessor(endMBB);
18750 // Load the offset value into a register
18751 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18752 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18756 .addDisp(Disp, UseFPOffset ? 4 : 0)
18757 .addOperand(Segment)
18758 .setMemRefs(MMOBegin, MMOEnd);
18760 // Check if there is enough room left to pull this argument.
18761 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18763 .addImm(MaxOffset + 8 - ArgSizeA8);
18765 // Branch to "overflowMBB" if offset >= max
18766 // Fall through to "offsetMBB" otherwise
18767 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18768 .addMBB(overflowMBB);
18771 // In offsetMBB, emit code to use the reg_save_area.
18773 assert(OffsetReg != 0);
18775 // Read the reg_save_area address.
18776 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18777 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18782 .addOperand(Segment)
18783 .setMemRefs(MMOBegin, MMOEnd);
18785 // Zero-extend the offset
18786 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18787 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18790 .addImm(X86::sub_32bit);
18792 // Add the offset to the reg_save_area to get the final address.
18793 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18794 .addReg(OffsetReg64)
18795 .addReg(RegSaveReg);
18797 // Compute the offset for the next argument
18798 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18799 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18801 .addImm(UseFPOffset ? 16 : 8);
18803 // Store it back into the va_list.
18804 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18808 .addDisp(Disp, UseFPOffset ? 4 : 0)
18809 .addOperand(Segment)
18810 .addReg(NextOffsetReg)
18811 .setMemRefs(MMOBegin, MMOEnd);
18814 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18819 // Emit code to use overflow area
18822 // Load the overflow_area address into a register.
18823 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18824 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18829 .addOperand(Segment)
18830 .setMemRefs(MMOBegin, MMOEnd);
18832 // If we need to align it, do so. Otherwise, just copy the address
18833 // to OverflowDestReg.
18835 // Align the overflow address
18836 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18837 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18839 // aligned_addr = (addr + (align-1)) & ~(align-1)
18840 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18841 .addReg(OverflowAddrReg)
18844 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18846 .addImm(~(uint64_t)(Align-1));
18848 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18849 .addReg(OverflowAddrReg);
18852 // Compute the next overflow address after this argument.
18853 // (the overflow address should be kept 8-byte aligned)
18854 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18855 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18856 .addReg(OverflowDestReg)
18857 .addImm(ArgSizeA8);
18859 // Store the new overflow address.
18860 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18865 .addOperand(Segment)
18866 .addReg(NextAddrReg)
18867 .setMemRefs(MMOBegin, MMOEnd);
18869 // If we branched, emit the PHI to the front of endMBB.
18871 BuildMI(*endMBB, endMBB->begin(), DL,
18872 TII->get(X86::PHI), DestReg)
18873 .addReg(OffsetDestReg).addMBB(offsetMBB)
18874 .addReg(OverflowDestReg).addMBB(overflowMBB);
18877 // Erase the pseudo instruction
18878 MI->eraseFromParent();
18883 MachineBasicBlock *
18884 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18886 MachineBasicBlock *MBB) const {
18887 // Emit code to save XMM registers to the stack. The ABI says that the
18888 // number of registers to save is given in %al, so it's theoretically
18889 // possible to do an indirect jump trick to avoid saving all of them,
18890 // however this code takes a simpler approach and just executes all
18891 // of the stores if %al is non-zero. It's less code, and it's probably
18892 // easier on the hardware branch predictor, and stores aren't all that
18893 // expensive anyway.
18895 // Create the new basic blocks. One block contains all the XMM stores,
18896 // and one block is the final destination regardless of whether any
18897 // stores were performed.
18898 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18899 MachineFunction *F = MBB->getParent();
18900 MachineFunction::iterator MBBIter = MBB;
18902 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18903 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18904 F->insert(MBBIter, XMMSaveMBB);
18905 F->insert(MBBIter, EndMBB);
18907 // Transfer the remainder of MBB and its successor edges to EndMBB.
18908 EndMBB->splice(EndMBB->begin(), MBB,
18909 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18910 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18912 // The original block will now fall through to the XMM save block.
18913 MBB->addSuccessor(XMMSaveMBB);
18914 // The XMMSaveMBB will fall through to the end block.
18915 XMMSaveMBB->addSuccessor(EndMBB);
18917 // Now add the instructions.
18918 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18919 DebugLoc DL = MI->getDebugLoc();
18921 unsigned CountReg = MI->getOperand(0).getReg();
18922 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18923 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18925 if (!Subtarget->isTargetWin64()) {
18926 // If %al is 0, branch around the XMM save block.
18927 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18928 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18929 MBB->addSuccessor(EndMBB);
18932 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18933 // that was just emitted, but clearly shouldn't be "saved".
18934 assert((MI->getNumOperands() <= 3 ||
18935 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18936 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18937 && "Expected last argument to be EFLAGS");
18938 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18939 // In the XMM save block, save all the XMM argument registers.
18940 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18941 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18942 MachineMemOperand *MMO =
18943 F->getMachineMemOperand(
18944 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18945 MachineMemOperand::MOStore,
18946 /*Size=*/16, /*Align=*/16);
18947 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18948 .addFrameIndex(RegSaveFrameIndex)
18949 .addImm(/*Scale=*/1)
18950 .addReg(/*IndexReg=*/0)
18951 .addImm(/*Disp=*/Offset)
18952 .addReg(/*Segment=*/0)
18953 .addReg(MI->getOperand(i).getReg())
18954 .addMemOperand(MMO);
18957 MI->eraseFromParent(); // The pseudo instruction is gone now.
18962 // The EFLAGS operand of SelectItr might be missing a kill marker
18963 // because there were multiple uses of EFLAGS, and ISel didn't know
18964 // which to mark. Figure out whether SelectItr should have had a
18965 // kill marker, and set it if it should. Returns the correct kill
18967 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18968 MachineBasicBlock* BB,
18969 const TargetRegisterInfo* TRI) {
18970 // Scan forward through BB for a use/def of EFLAGS.
18971 MachineBasicBlock::iterator miI(std::next(SelectItr));
18972 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18973 const MachineInstr& mi = *miI;
18974 if (mi.readsRegister(X86::EFLAGS))
18976 if (mi.definesRegister(X86::EFLAGS))
18977 break; // Should have kill-flag - update below.
18980 // If we hit the end of the block, check whether EFLAGS is live into a
18982 if (miI == BB->end()) {
18983 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18984 sEnd = BB->succ_end();
18985 sItr != sEnd; ++sItr) {
18986 MachineBasicBlock* succ = *sItr;
18987 if (succ->isLiveIn(X86::EFLAGS))
18992 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18993 // out. SelectMI should have a kill flag on EFLAGS.
18994 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18998 MachineBasicBlock *
18999 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19000 MachineBasicBlock *BB) const {
19001 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19002 DebugLoc DL = MI->getDebugLoc();
19004 // To "insert" a SELECT_CC instruction, we actually have to insert the
19005 // diamond control-flow pattern. The incoming instruction knows the
19006 // destination vreg to set, the condition code register to branch on, the
19007 // true/false values to select between, and a branch opcode to use.
19008 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19009 MachineFunction::iterator It = BB;
19015 // cmpTY ccX, r1, r2
19017 // fallthrough --> copy0MBB
19018 MachineBasicBlock *thisMBB = BB;
19019 MachineFunction *F = BB->getParent();
19020 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19021 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19022 F->insert(It, copy0MBB);
19023 F->insert(It, sinkMBB);
19025 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19026 // live into the sink and copy blocks.
19027 const TargetRegisterInfo *TRI =
19028 BB->getParent()->getSubtarget().getRegisterInfo();
19029 if (!MI->killsRegister(X86::EFLAGS) &&
19030 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19031 copy0MBB->addLiveIn(X86::EFLAGS);
19032 sinkMBB->addLiveIn(X86::EFLAGS);
19035 // Transfer the remainder of BB and its successor edges to sinkMBB.
19036 sinkMBB->splice(sinkMBB->begin(), BB,
19037 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19038 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19040 // Add the true and fallthrough blocks as its successors.
19041 BB->addSuccessor(copy0MBB);
19042 BB->addSuccessor(sinkMBB);
19044 // Create the conditional branch instruction.
19046 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19047 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19050 // %FalseValue = ...
19051 // # fallthrough to sinkMBB
19052 copy0MBB->addSuccessor(sinkMBB);
19055 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19057 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19058 TII->get(X86::PHI), MI->getOperand(0).getReg())
19059 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19060 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19062 MI->eraseFromParent(); // The pseudo instruction is gone now.
19066 MachineBasicBlock *
19067 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19068 MachineBasicBlock *BB) const {
19069 MachineFunction *MF = BB->getParent();
19070 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19071 DebugLoc DL = MI->getDebugLoc();
19072 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19074 assert(MF->shouldSplitStack());
19076 const bool Is64Bit = Subtarget->is64Bit();
19077 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19079 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19080 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19083 // ... [Till the alloca]
19084 // If stacklet is not large enough, jump to mallocMBB
19087 // Allocate by subtracting from RSP
19088 // Jump to continueMBB
19091 // Allocate by call to runtime
19095 // [rest of original BB]
19098 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19099 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19100 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19102 MachineRegisterInfo &MRI = MF->getRegInfo();
19103 const TargetRegisterClass *AddrRegClass =
19104 getRegClassFor(getPointerTy());
19106 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19107 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19108 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19109 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19110 sizeVReg = MI->getOperand(1).getReg(),
19111 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19113 MachineFunction::iterator MBBIter = BB;
19116 MF->insert(MBBIter, bumpMBB);
19117 MF->insert(MBBIter, mallocMBB);
19118 MF->insert(MBBIter, continueMBB);
19120 continueMBB->splice(continueMBB->begin(), BB,
19121 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19122 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19124 // Add code to the main basic block to check if the stack limit has been hit,
19125 // and if so, jump to mallocMBB otherwise to bumpMBB.
19126 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19127 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19128 .addReg(tmpSPVReg).addReg(sizeVReg);
19129 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19130 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19131 .addReg(SPLimitVReg);
19132 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19134 // bumpMBB simply decreases the stack pointer, since we know the current
19135 // stacklet has enough space.
19136 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19137 .addReg(SPLimitVReg);
19138 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19139 .addReg(SPLimitVReg);
19140 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19142 // Calls into a routine in libgcc to allocate more space from the heap.
19143 const uint32_t *RegMask = MF->getTarget()
19144 .getSubtargetImpl()
19145 ->getRegisterInfo()
19146 ->getCallPreservedMask(CallingConv::C);
19148 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19150 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19151 .addExternalSymbol("__morestack_allocate_stack_space")
19152 .addRegMask(RegMask)
19153 .addReg(X86::RDI, RegState::Implicit)
19154 .addReg(X86::RAX, RegState::ImplicitDefine);
19155 } else if (Is64Bit) {
19156 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19158 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19159 .addExternalSymbol("__morestack_allocate_stack_space")
19160 .addRegMask(RegMask)
19161 .addReg(X86::EDI, RegState::Implicit)
19162 .addReg(X86::EAX, RegState::ImplicitDefine);
19164 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19166 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19167 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19168 .addExternalSymbol("__morestack_allocate_stack_space")
19169 .addRegMask(RegMask)
19170 .addReg(X86::EAX, RegState::ImplicitDefine);
19174 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19177 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19178 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19179 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19181 // Set up the CFG correctly.
19182 BB->addSuccessor(bumpMBB);
19183 BB->addSuccessor(mallocMBB);
19184 mallocMBB->addSuccessor(continueMBB);
19185 bumpMBB->addSuccessor(continueMBB);
19187 // Take care of the PHI nodes.
19188 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19189 MI->getOperand(0).getReg())
19190 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19191 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19193 // Delete the original pseudo instruction.
19194 MI->eraseFromParent();
19197 return continueMBB;
19200 MachineBasicBlock *
19201 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19202 MachineBasicBlock *BB) const {
19203 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19204 DebugLoc DL = MI->getDebugLoc();
19206 assert(!Subtarget->isTargetMacho());
19208 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19209 // non-trivial part is impdef of ESP.
19211 if (Subtarget->isTargetWin64()) {
19212 if (Subtarget->isTargetCygMing()) {
19213 // ___chkstk(Mingw64):
19214 // Clobbers R10, R11, RAX and EFLAGS.
19216 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19217 .addExternalSymbol("___chkstk")
19218 .addReg(X86::RAX, RegState::Implicit)
19219 .addReg(X86::RSP, RegState::Implicit)
19220 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19221 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19222 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19224 // __chkstk(MSVCRT): does not update stack pointer.
19225 // Clobbers R10, R11 and EFLAGS.
19226 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19227 .addExternalSymbol("__chkstk")
19228 .addReg(X86::RAX, RegState::Implicit)
19229 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19230 // RAX has the offset to be subtracted from RSP.
19231 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19236 const char *StackProbeSymbol =
19237 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19239 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19240 .addExternalSymbol(StackProbeSymbol)
19241 .addReg(X86::EAX, RegState::Implicit)
19242 .addReg(X86::ESP, RegState::Implicit)
19243 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19244 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19245 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19248 MI->eraseFromParent(); // The pseudo instruction is gone now.
19252 MachineBasicBlock *
19253 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19254 MachineBasicBlock *BB) const {
19255 // This is pretty easy. We're taking the value that we received from
19256 // our load from the relocation, sticking it in either RDI (x86-64)
19257 // or EAX and doing an indirect call. The return value will then
19258 // be in the normal return register.
19259 MachineFunction *F = BB->getParent();
19260 const X86InstrInfo *TII =
19261 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19262 DebugLoc DL = MI->getDebugLoc();
19264 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19265 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19267 // Get a register mask for the lowered call.
19268 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19269 // proper register mask.
19270 const uint32_t *RegMask = F->getTarget()
19271 .getSubtargetImpl()
19272 ->getRegisterInfo()
19273 ->getCallPreservedMask(CallingConv::C);
19274 if (Subtarget->is64Bit()) {
19275 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19276 TII->get(X86::MOV64rm), X86::RDI)
19278 .addImm(0).addReg(0)
19279 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19280 MI->getOperand(3).getTargetFlags())
19282 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19283 addDirectMem(MIB, X86::RDI);
19284 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19285 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19286 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19287 TII->get(X86::MOV32rm), X86::EAX)
19289 .addImm(0).addReg(0)
19290 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19291 MI->getOperand(3).getTargetFlags())
19293 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19294 addDirectMem(MIB, X86::EAX);
19295 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19297 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19298 TII->get(X86::MOV32rm), X86::EAX)
19299 .addReg(TII->getGlobalBaseReg(F))
19300 .addImm(0).addReg(0)
19301 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19302 MI->getOperand(3).getTargetFlags())
19304 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19305 addDirectMem(MIB, X86::EAX);
19306 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19309 MI->eraseFromParent(); // The pseudo instruction is gone now.
19313 MachineBasicBlock *
19314 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19315 MachineBasicBlock *MBB) const {
19316 DebugLoc DL = MI->getDebugLoc();
19317 MachineFunction *MF = MBB->getParent();
19318 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19319 MachineRegisterInfo &MRI = MF->getRegInfo();
19321 const BasicBlock *BB = MBB->getBasicBlock();
19322 MachineFunction::iterator I = MBB;
19325 // Memory Reference
19326 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19327 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19330 unsigned MemOpndSlot = 0;
19332 unsigned CurOp = 0;
19334 DstReg = MI->getOperand(CurOp++).getReg();
19335 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19336 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19337 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19338 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19340 MemOpndSlot = CurOp;
19342 MVT PVT = getPointerTy();
19343 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19344 "Invalid Pointer Size!");
19346 // For v = setjmp(buf), we generate
19349 // buf[LabelOffset] = restoreMBB
19350 // SjLjSetup restoreMBB
19356 // v = phi(main, restore)
19361 MachineBasicBlock *thisMBB = MBB;
19362 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19363 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19364 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19365 MF->insert(I, mainMBB);
19366 MF->insert(I, sinkMBB);
19367 MF->push_back(restoreMBB);
19369 MachineInstrBuilder MIB;
19371 // Transfer the remainder of BB and its successor edges to sinkMBB.
19372 sinkMBB->splice(sinkMBB->begin(), MBB,
19373 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19374 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19377 unsigned PtrStoreOpc = 0;
19378 unsigned LabelReg = 0;
19379 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19380 Reloc::Model RM = MF->getTarget().getRelocationModel();
19381 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19382 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19384 // Prepare IP either in reg or imm.
19385 if (!UseImmLabel) {
19386 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19387 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19388 LabelReg = MRI.createVirtualRegister(PtrRC);
19389 if (Subtarget->is64Bit()) {
19390 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19394 .addMBB(restoreMBB)
19397 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19398 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19399 .addReg(XII->getGlobalBaseReg(MF))
19402 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19406 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19408 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19409 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19410 if (i == X86::AddrDisp)
19411 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19413 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19416 MIB.addReg(LabelReg);
19418 MIB.addMBB(restoreMBB);
19419 MIB.setMemRefs(MMOBegin, MMOEnd);
19421 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19422 .addMBB(restoreMBB);
19424 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19425 MF->getSubtarget().getRegisterInfo());
19426 MIB.addRegMask(RegInfo->getNoPreservedMask());
19427 thisMBB->addSuccessor(mainMBB);
19428 thisMBB->addSuccessor(restoreMBB);
19432 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19433 mainMBB->addSuccessor(sinkMBB);
19436 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19437 TII->get(X86::PHI), DstReg)
19438 .addReg(mainDstReg).addMBB(mainMBB)
19439 .addReg(restoreDstReg).addMBB(restoreMBB);
19442 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19443 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19444 restoreMBB->addSuccessor(sinkMBB);
19446 MI->eraseFromParent();
19450 MachineBasicBlock *
19451 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19452 MachineBasicBlock *MBB) const {
19453 DebugLoc DL = MI->getDebugLoc();
19454 MachineFunction *MF = MBB->getParent();
19455 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19456 MachineRegisterInfo &MRI = MF->getRegInfo();
19458 // Memory Reference
19459 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19460 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19462 MVT PVT = getPointerTy();
19463 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19464 "Invalid Pointer Size!");
19466 const TargetRegisterClass *RC =
19467 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19468 unsigned Tmp = MRI.createVirtualRegister(RC);
19469 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19470 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19471 MF->getSubtarget().getRegisterInfo());
19472 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19473 unsigned SP = RegInfo->getStackRegister();
19475 MachineInstrBuilder MIB;
19477 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19478 const int64_t SPOffset = 2 * PVT.getStoreSize();
19480 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19481 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19484 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19485 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19486 MIB.addOperand(MI->getOperand(i));
19487 MIB.setMemRefs(MMOBegin, MMOEnd);
19489 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19490 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19491 if (i == X86::AddrDisp)
19492 MIB.addDisp(MI->getOperand(i), LabelOffset);
19494 MIB.addOperand(MI->getOperand(i));
19496 MIB.setMemRefs(MMOBegin, MMOEnd);
19498 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19499 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19500 if (i == X86::AddrDisp)
19501 MIB.addDisp(MI->getOperand(i), SPOffset);
19503 MIB.addOperand(MI->getOperand(i));
19505 MIB.setMemRefs(MMOBegin, MMOEnd);
19507 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19509 MI->eraseFromParent();
19513 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19514 // accumulator loops. Writing back to the accumulator allows the coalescer
19515 // to remove extra copies in the loop.
19516 MachineBasicBlock *
19517 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19518 MachineBasicBlock *MBB) const {
19519 MachineOperand &AddendOp = MI->getOperand(3);
19521 // Bail out early if the addend isn't a register - we can't switch these.
19522 if (!AddendOp.isReg())
19525 MachineFunction &MF = *MBB->getParent();
19526 MachineRegisterInfo &MRI = MF.getRegInfo();
19528 // Check whether the addend is defined by a PHI:
19529 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19530 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19531 if (!AddendDef.isPHI())
19534 // Look for the following pattern:
19536 // %addend = phi [%entry, 0], [%loop, %result]
19538 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19542 // %addend = phi [%entry, 0], [%loop, %result]
19544 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19546 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19547 assert(AddendDef.getOperand(i).isReg());
19548 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19549 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19550 if (&PHISrcInst == MI) {
19551 // Found a matching instruction.
19552 unsigned NewFMAOpc = 0;
19553 switch (MI->getOpcode()) {
19554 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19555 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19556 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19557 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19558 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19559 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19560 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19561 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19562 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19563 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19564 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19565 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19566 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19567 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19568 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19569 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19570 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19571 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19572 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19573 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19574 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19575 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19576 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19577 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19578 default: llvm_unreachable("Unrecognized FMA variant.");
19581 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19582 MachineInstrBuilder MIB =
19583 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19584 .addOperand(MI->getOperand(0))
19585 .addOperand(MI->getOperand(3))
19586 .addOperand(MI->getOperand(2))
19587 .addOperand(MI->getOperand(1));
19588 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19589 MI->eraseFromParent();
19596 MachineBasicBlock *
19597 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19598 MachineBasicBlock *BB) const {
19599 switch (MI->getOpcode()) {
19600 default: llvm_unreachable("Unexpected instr type to insert");
19601 case X86::TAILJMPd64:
19602 case X86::TAILJMPr64:
19603 case X86::TAILJMPm64:
19604 llvm_unreachable("TAILJMP64 would not be touched here.");
19605 case X86::TCRETURNdi64:
19606 case X86::TCRETURNri64:
19607 case X86::TCRETURNmi64:
19609 case X86::WIN_ALLOCA:
19610 return EmitLoweredWinAlloca(MI, BB);
19611 case X86::SEG_ALLOCA_32:
19612 case X86::SEG_ALLOCA_64:
19613 return EmitLoweredSegAlloca(MI, BB);
19614 case X86::TLSCall_32:
19615 case X86::TLSCall_64:
19616 return EmitLoweredTLSCall(MI, BB);
19617 case X86::CMOV_GR8:
19618 case X86::CMOV_FR32:
19619 case X86::CMOV_FR64:
19620 case X86::CMOV_V4F32:
19621 case X86::CMOV_V2F64:
19622 case X86::CMOV_V2I64:
19623 case X86::CMOV_V8F32:
19624 case X86::CMOV_V4F64:
19625 case X86::CMOV_V4I64:
19626 case X86::CMOV_V16F32:
19627 case X86::CMOV_V8F64:
19628 case X86::CMOV_V8I64:
19629 case X86::CMOV_GR16:
19630 case X86::CMOV_GR32:
19631 case X86::CMOV_RFP32:
19632 case X86::CMOV_RFP64:
19633 case X86::CMOV_RFP80:
19634 return EmitLoweredSelect(MI, BB);
19636 case X86::FP32_TO_INT16_IN_MEM:
19637 case X86::FP32_TO_INT32_IN_MEM:
19638 case X86::FP32_TO_INT64_IN_MEM:
19639 case X86::FP64_TO_INT16_IN_MEM:
19640 case X86::FP64_TO_INT32_IN_MEM:
19641 case X86::FP64_TO_INT64_IN_MEM:
19642 case X86::FP80_TO_INT16_IN_MEM:
19643 case X86::FP80_TO_INT32_IN_MEM:
19644 case X86::FP80_TO_INT64_IN_MEM: {
19645 MachineFunction *F = BB->getParent();
19646 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19647 DebugLoc DL = MI->getDebugLoc();
19649 // Change the floating point control register to use "round towards zero"
19650 // mode when truncating to an integer value.
19651 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19652 addFrameReference(BuildMI(*BB, MI, DL,
19653 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19655 // Load the old value of the high byte of the control word...
19657 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19658 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19661 // Set the high part to be round to zero...
19662 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19665 // Reload the modified control word now...
19666 addFrameReference(BuildMI(*BB, MI, DL,
19667 TII->get(X86::FLDCW16m)), CWFrameIdx);
19669 // Restore the memory image of control word to original value
19670 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19673 // Get the X86 opcode to use.
19675 switch (MI->getOpcode()) {
19676 default: llvm_unreachable("illegal opcode!");
19677 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19678 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19679 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19680 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19681 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19682 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19683 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19684 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19685 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19689 MachineOperand &Op = MI->getOperand(0);
19691 AM.BaseType = X86AddressMode::RegBase;
19692 AM.Base.Reg = Op.getReg();
19694 AM.BaseType = X86AddressMode::FrameIndexBase;
19695 AM.Base.FrameIndex = Op.getIndex();
19697 Op = MI->getOperand(1);
19699 AM.Scale = Op.getImm();
19700 Op = MI->getOperand(2);
19702 AM.IndexReg = Op.getImm();
19703 Op = MI->getOperand(3);
19704 if (Op.isGlobal()) {
19705 AM.GV = Op.getGlobal();
19707 AM.Disp = Op.getImm();
19709 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19710 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19712 // Reload the original control word now.
19713 addFrameReference(BuildMI(*BB, MI, DL,
19714 TII->get(X86::FLDCW16m)), CWFrameIdx);
19716 MI->eraseFromParent(); // The pseudo instruction is gone now.
19719 // String/text processing lowering.
19720 case X86::PCMPISTRM128REG:
19721 case X86::VPCMPISTRM128REG:
19722 case X86::PCMPISTRM128MEM:
19723 case X86::VPCMPISTRM128MEM:
19724 case X86::PCMPESTRM128REG:
19725 case X86::VPCMPESTRM128REG:
19726 case X86::PCMPESTRM128MEM:
19727 case X86::VPCMPESTRM128MEM:
19728 assert(Subtarget->hasSSE42() &&
19729 "Target must have SSE4.2 or AVX features enabled");
19730 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19732 // String/text processing lowering.
19733 case X86::PCMPISTRIREG:
19734 case X86::VPCMPISTRIREG:
19735 case X86::PCMPISTRIMEM:
19736 case X86::VPCMPISTRIMEM:
19737 case X86::PCMPESTRIREG:
19738 case X86::VPCMPESTRIREG:
19739 case X86::PCMPESTRIMEM:
19740 case X86::VPCMPESTRIMEM:
19741 assert(Subtarget->hasSSE42() &&
19742 "Target must have SSE4.2 or AVX features enabled");
19743 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19745 // Thread synchronization.
19747 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19752 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19754 case X86::VASTART_SAVE_XMM_REGS:
19755 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19757 case X86::VAARG_64:
19758 return EmitVAARG64WithCustomInserter(MI, BB);
19760 case X86::EH_SjLj_SetJmp32:
19761 case X86::EH_SjLj_SetJmp64:
19762 return emitEHSjLjSetJmp(MI, BB);
19764 case X86::EH_SjLj_LongJmp32:
19765 case X86::EH_SjLj_LongJmp64:
19766 return emitEHSjLjLongJmp(MI, BB);
19768 case TargetOpcode::STACKMAP:
19769 case TargetOpcode::PATCHPOINT:
19770 return emitPatchPoint(MI, BB);
19772 case X86::VFMADDPDr213r:
19773 case X86::VFMADDPSr213r:
19774 case X86::VFMADDSDr213r:
19775 case X86::VFMADDSSr213r:
19776 case X86::VFMSUBPDr213r:
19777 case X86::VFMSUBPSr213r:
19778 case X86::VFMSUBSDr213r:
19779 case X86::VFMSUBSSr213r:
19780 case X86::VFNMADDPDr213r:
19781 case X86::VFNMADDPSr213r:
19782 case X86::VFNMADDSDr213r:
19783 case X86::VFNMADDSSr213r:
19784 case X86::VFNMSUBPDr213r:
19785 case X86::VFNMSUBPSr213r:
19786 case X86::VFNMSUBSDr213r:
19787 case X86::VFNMSUBSSr213r:
19788 case X86::VFMADDPDr213rY:
19789 case X86::VFMADDPSr213rY:
19790 case X86::VFMSUBPDr213rY:
19791 case X86::VFMSUBPSr213rY:
19792 case X86::VFNMADDPDr213rY:
19793 case X86::VFNMADDPSr213rY:
19794 case X86::VFNMSUBPDr213rY:
19795 case X86::VFNMSUBPSr213rY:
19796 return emitFMA3Instr(MI, BB);
19800 //===----------------------------------------------------------------------===//
19801 // X86 Optimization Hooks
19802 //===----------------------------------------------------------------------===//
19804 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19807 const SelectionDAG &DAG,
19808 unsigned Depth) const {
19809 unsigned BitWidth = KnownZero.getBitWidth();
19810 unsigned Opc = Op.getOpcode();
19811 assert((Opc >= ISD::BUILTIN_OP_END ||
19812 Opc == ISD::INTRINSIC_WO_CHAIN ||
19813 Opc == ISD::INTRINSIC_W_CHAIN ||
19814 Opc == ISD::INTRINSIC_VOID) &&
19815 "Should use MaskedValueIsZero if you don't know whether Op"
19816 " is a target node!");
19818 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19832 // These nodes' second result is a boolean.
19833 if (Op.getResNo() == 0)
19836 case X86ISD::SETCC:
19837 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19839 case ISD::INTRINSIC_WO_CHAIN: {
19840 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19841 unsigned NumLoBits = 0;
19844 case Intrinsic::x86_sse_movmsk_ps:
19845 case Intrinsic::x86_avx_movmsk_ps_256:
19846 case Intrinsic::x86_sse2_movmsk_pd:
19847 case Intrinsic::x86_avx_movmsk_pd_256:
19848 case Intrinsic::x86_mmx_pmovmskb:
19849 case Intrinsic::x86_sse2_pmovmskb_128:
19850 case Intrinsic::x86_avx2_pmovmskb: {
19851 // High bits of movmskp{s|d}, pmovmskb are known zero.
19853 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19854 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19855 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19856 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19857 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19858 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19859 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19860 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19862 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19871 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19873 const SelectionDAG &,
19874 unsigned Depth) const {
19875 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19876 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19877 return Op.getValueType().getScalarType().getSizeInBits();
19883 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19884 /// node is a GlobalAddress + offset.
19885 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19886 const GlobalValue* &GA,
19887 int64_t &Offset) const {
19888 if (N->getOpcode() == X86ISD::Wrapper) {
19889 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19890 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19891 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19895 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19898 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19899 /// same as extracting the high 128-bit part of 256-bit vector and then
19900 /// inserting the result into the low part of a new 256-bit vector
19901 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19902 EVT VT = SVOp->getValueType(0);
19903 unsigned NumElems = VT.getVectorNumElements();
19905 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19906 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19907 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19908 SVOp->getMaskElt(j) >= 0)
19914 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19915 /// same as extracting the low 128-bit part of 256-bit vector and then
19916 /// inserting the result into the high part of a new 256-bit vector
19917 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19918 EVT VT = SVOp->getValueType(0);
19919 unsigned NumElems = VT.getVectorNumElements();
19921 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19922 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19923 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19924 SVOp->getMaskElt(j) >= 0)
19930 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19931 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19932 TargetLowering::DAGCombinerInfo &DCI,
19933 const X86Subtarget* Subtarget) {
19935 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19936 SDValue V1 = SVOp->getOperand(0);
19937 SDValue V2 = SVOp->getOperand(1);
19938 EVT VT = SVOp->getValueType(0);
19939 unsigned NumElems = VT.getVectorNumElements();
19941 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19942 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19946 // V UNDEF BUILD_VECTOR UNDEF
19948 // CONCAT_VECTOR CONCAT_VECTOR
19951 // RESULT: V + zero extended
19953 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19954 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19955 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19958 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19961 // To match the shuffle mask, the first half of the mask should
19962 // be exactly the first vector, and all the rest a splat with the
19963 // first element of the second one.
19964 for (unsigned i = 0; i != NumElems/2; ++i)
19965 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19966 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19969 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19970 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19971 if (Ld->hasNUsesOfValue(1, 0)) {
19972 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19973 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19975 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19977 Ld->getPointerInfo(),
19978 Ld->getAlignment(),
19979 false/*isVolatile*/, true/*ReadMem*/,
19980 false/*WriteMem*/);
19982 // Make sure the newly-created LOAD is in the same position as Ld in
19983 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19984 // and update uses of Ld's output chain to use the TokenFactor.
19985 if (Ld->hasAnyUseOfValue(1)) {
19986 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19987 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19988 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19989 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19990 SDValue(ResNode.getNode(), 1));
19993 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19997 // Emit a zeroed vector and insert the desired subvector on its
19999 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20000 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20001 return DCI.CombineTo(N, InsV);
20004 //===--------------------------------------------------------------------===//
20005 // Combine some shuffles into subvector extracts and inserts:
20008 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20009 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20010 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20011 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20012 return DCI.CombineTo(N, InsV);
20015 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20016 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20017 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20018 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20019 return DCI.CombineTo(N, InsV);
20025 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20028 /// This is the leaf of the recursive combinine below. When we have found some
20029 /// chain of single-use x86 shuffle instructions and accumulated the combined
20030 /// shuffle mask represented by them, this will try to pattern match that mask
20031 /// into either a single instruction if there is a special purpose instruction
20032 /// for this operation, or into a PSHUFB instruction which is a fully general
20033 /// instruction but should only be used to replace chains over a certain depth.
20034 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20035 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20036 TargetLowering::DAGCombinerInfo &DCI,
20037 const X86Subtarget *Subtarget) {
20038 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20040 // Find the operand that enters the chain. Note that multiple uses are OK
20041 // here, we're not going to remove the operand we find.
20042 SDValue Input = Op.getOperand(0);
20043 while (Input.getOpcode() == ISD::BITCAST)
20044 Input = Input.getOperand(0);
20046 MVT VT = Input.getSimpleValueType();
20047 MVT RootVT = Root.getSimpleValueType();
20050 // Just remove no-op shuffle masks.
20051 if (Mask.size() == 1) {
20052 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20057 // Use the float domain if the operand type is a floating point type.
20058 bool FloatDomain = VT.isFloatingPoint();
20060 // For floating point shuffles, we don't have free copies in the shuffle
20061 // instructions or the ability to load as part of the instruction, so
20062 // canonicalize their shuffles to UNPCK or MOV variants.
20064 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20065 // vectors because it can have a load folded into it that UNPCK cannot. This
20066 // doesn't preclude something switching to the shorter encoding post-RA.
20068 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20069 bool Lo = Mask.equals(0, 0);
20072 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20073 // is no slower than UNPCKLPD but has the option to fold the input operand
20074 // into even an unaligned memory load.
20075 if (Lo && Subtarget->hasSSE3()) {
20076 Shuffle = X86ISD::MOVDDUP;
20077 ShuffleVT = MVT::v2f64;
20079 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20080 // than the UNPCK variants.
20081 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20082 ShuffleVT = MVT::v4f32;
20084 if (Depth == 1 && Root->getOpcode() == Shuffle)
20085 return false; // Nothing to do!
20086 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20087 DCI.AddToWorklist(Op.getNode());
20088 if (Shuffle == X86ISD::MOVDDUP)
20089 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20091 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20092 DCI.AddToWorklist(Op.getNode());
20093 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20097 if (Subtarget->hasSSE3() &&
20098 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20099 bool Lo = Mask.equals(0, 0, 2, 2);
20100 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20101 MVT ShuffleVT = MVT::v4f32;
20102 if (Depth == 1 && Root->getOpcode() == Shuffle)
20103 return false; // Nothing to do!
20104 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20105 DCI.AddToWorklist(Op.getNode());
20106 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20107 DCI.AddToWorklist(Op.getNode());
20108 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20112 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20113 bool Lo = Mask.equals(0, 0, 1, 1);
20114 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20115 MVT ShuffleVT = MVT::v4f32;
20116 if (Depth == 1 && Root->getOpcode() == Shuffle)
20117 return false; // Nothing to do!
20118 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20119 DCI.AddToWorklist(Op.getNode());
20120 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20121 DCI.AddToWorklist(Op.getNode());
20122 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20128 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20129 // variants as none of these have single-instruction variants that are
20130 // superior to the UNPCK formulation.
20131 if (!FloatDomain &&
20132 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20133 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20134 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20135 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20137 bool Lo = Mask[0] == 0;
20138 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20139 if (Depth == 1 && Root->getOpcode() == Shuffle)
20140 return false; // Nothing to do!
20142 switch (Mask.size()) {
20144 ShuffleVT = MVT::v8i16;
20147 ShuffleVT = MVT::v16i8;
20150 llvm_unreachable("Impossible mask size!");
20152 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20153 DCI.AddToWorklist(Op.getNode());
20154 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20155 DCI.AddToWorklist(Op.getNode());
20156 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20161 // Don't try to re-form single instruction chains under any circumstances now
20162 // that we've done encoding canonicalization for them.
20166 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20167 // can replace them with a single PSHUFB instruction profitably. Intel's
20168 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20169 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20170 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20171 SmallVector<SDValue, 16> PSHUFBMask;
20172 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20173 int Ratio = 16 / Mask.size();
20174 for (unsigned i = 0; i < 16; ++i) {
20175 if (Mask[i / Ratio] == SM_SentinelUndef) {
20176 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20179 int M = Mask[i / Ratio] != SM_SentinelZero
20180 ? Ratio * Mask[i / Ratio] + i % Ratio
20182 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20184 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20185 DCI.AddToWorklist(Op.getNode());
20186 SDValue PSHUFBMaskOp =
20187 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20188 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20189 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20190 DCI.AddToWorklist(Op.getNode());
20191 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20196 // Failed to find any combines.
20200 /// \brief Fully generic combining of x86 shuffle instructions.
20202 /// This should be the last combine run over the x86 shuffle instructions. Once
20203 /// they have been fully optimized, this will recursively consider all chains
20204 /// of single-use shuffle instructions, build a generic model of the cumulative
20205 /// shuffle operation, and check for simpler instructions which implement this
20206 /// operation. We use this primarily for two purposes:
20208 /// 1) Collapse generic shuffles to specialized single instructions when
20209 /// equivalent. In most cases, this is just an encoding size win, but
20210 /// sometimes we will collapse multiple generic shuffles into a single
20211 /// special-purpose shuffle.
20212 /// 2) Look for sequences of shuffle instructions with 3 or more total
20213 /// instructions, and replace them with the slightly more expensive SSSE3
20214 /// PSHUFB instruction if available. We do this as the last combining step
20215 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20216 /// a suitable short sequence of other instructions. The PHUFB will either
20217 /// use a register or have to read from memory and so is slightly (but only
20218 /// slightly) more expensive than the other shuffle instructions.
20220 /// Because this is inherently a quadratic operation (for each shuffle in
20221 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20222 /// This should never be an issue in practice as the shuffle lowering doesn't
20223 /// produce sequences of more than 8 instructions.
20225 /// FIXME: We will currently miss some cases where the redundant shuffling
20226 /// would simplify under the threshold for PSHUFB formation because of
20227 /// combine-ordering. To fix this, we should do the redundant instruction
20228 /// combining in this recursive walk.
20229 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20230 ArrayRef<int> RootMask,
20231 int Depth, bool HasPSHUFB,
20233 TargetLowering::DAGCombinerInfo &DCI,
20234 const X86Subtarget *Subtarget) {
20235 // Bound the depth of our recursive combine because this is ultimately
20236 // quadratic in nature.
20240 // Directly rip through bitcasts to find the underlying operand.
20241 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20242 Op = Op.getOperand(0);
20244 MVT VT = Op.getSimpleValueType();
20245 if (!VT.isVector())
20246 return false; // Bail if we hit a non-vector.
20247 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20248 // version should be added.
20249 if (VT.getSizeInBits() != 128)
20252 assert(Root.getSimpleValueType().isVector() &&
20253 "Shuffles operate on vector types!");
20254 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20255 "Can only combine shuffles of the same vector register size.");
20257 if (!isTargetShuffle(Op.getOpcode()))
20259 SmallVector<int, 16> OpMask;
20261 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20262 // We only can combine unary shuffles which we can decode the mask for.
20263 if (!HaveMask || !IsUnary)
20266 assert(VT.getVectorNumElements() == OpMask.size() &&
20267 "Different mask size from vector size!");
20268 assert(((RootMask.size() > OpMask.size() &&
20269 RootMask.size() % OpMask.size() == 0) ||
20270 (OpMask.size() > RootMask.size() &&
20271 OpMask.size() % RootMask.size() == 0) ||
20272 OpMask.size() == RootMask.size()) &&
20273 "The smaller number of elements must divide the larger.");
20274 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20275 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20276 assert(((RootRatio == 1 && OpRatio == 1) ||
20277 (RootRatio == 1) != (OpRatio == 1)) &&
20278 "Must not have a ratio for both incoming and op masks!");
20280 SmallVector<int, 16> Mask;
20281 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20283 // Merge this shuffle operation's mask into our accumulated mask. Note that
20284 // this shuffle's mask will be the first applied to the input, followed by the
20285 // root mask to get us all the way to the root value arrangement. The reason
20286 // for this order is that we are recursing up the operation chain.
20287 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20288 int RootIdx = i / RootRatio;
20289 if (RootMask[RootIdx] < 0) {
20290 // This is a zero or undef lane, we're done.
20291 Mask.push_back(RootMask[RootIdx]);
20295 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20296 int OpIdx = RootMaskedIdx / OpRatio;
20297 if (OpMask[OpIdx] < 0) {
20298 // The incoming lanes are zero or undef, it doesn't matter which ones we
20300 Mask.push_back(OpMask[OpIdx]);
20304 // Ok, we have non-zero lanes, map them through.
20305 Mask.push_back(OpMask[OpIdx] * OpRatio +
20306 RootMaskedIdx % OpRatio);
20309 // See if we can recurse into the operand to combine more things.
20310 switch (Op.getOpcode()) {
20311 case X86ISD::PSHUFB:
20313 case X86ISD::PSHUFD:
20314 case X86ISD::PSHUFHW:
20315 case X86ISD::PSHUFLW:
20316 if (Op.getOperand(0).hasOneUse() &&
20317 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20318 HasPSHUFB, DAG, DCI, Subtarget))
20322 case X86ISD::UNPCKL:
20323 case X86ISD::UNPCKH:
20324 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20325 // We can't check for single use, we have to check that this shuffle is the only user.
20326 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20327 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20328 HasPSHUFB, DAG, DCI, Subtarget))
20333 // Minor canonicalization of the accumulated shuffle mask to make it easier
20334 // to match below. All this does is detect masks with squential pairs of
20335 // elements, and shrink them to the half-width mask. It does this in a loop
20336 // so it will reduce the size of the mask to the minimal width mask which
20337 // performs an equivalent shuffle.
20338 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20339 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20340 Mask[i] = Mask[2 * i] / 2;
20341 Mask.resize(Mask.size() / 2);
20344 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20348 /// \brief Get the PSHUF-style mask from PSHUF node.
20350 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20351 /// PSHUF-style masks that can be reused with such instructions.
20352 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20353 SmallVector<int, 4> Mask;
20355 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20359 switch (N.getOpcode()) {
20360 case X86ISD::PSHUFD:
20362 case X86ISD::PSHUFLW:
20365 case X86ISD::PSHUFHW:
20366 Mask.erase(Mask.begin(), Mask.begin() + 4);
20367 for (int &M : Mask)
20371 llvm_unreachable("No valid shuffle instruction found!");
20375 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20377 /// We walk up the chain and look for a combinable shuffle, skipping over
20378 /// shuffles that we could hoist this shuffle's transformation past without
20379 /// altering anything.
20381 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20383 TargetLowering::DAGCombinerInfo &DCI) {
20384 assert(N.getOpcode() == X86ISD::PSHUFD &&
20385 "Called with something other than an x86 128-bit half shuffle!");
20388 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20389 // of the shuffles in the chain so that we can form a fresh chain to replace
20391 SmallVector<SDValue, 8> Chain;
20392 SDValue V = N.getOperand(0);
20393 for (; V.hasOneUse(); V = V.getOperand(0)) {
20394 switch (V.getOpcode()) {
20396 return SDValue(); // Nothing combined!
20399 // Skip bitcasts as we always know the type for the target specific
20403 case X86ISD::PSHUFD:
20404 // Found another dword shuffle.
20407 case X86ISD::PSHUFLW:
20408 // Check that the low words (being shuffled) are the identity in the
20409 // dword shuffle, and the high words are self-contained.
20410 if (Mask[0] != 0 || Mask[1] != 1 ||
20411 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20414 Chain.push_back(V);
20417 case X86ISD::PSHUFHW:
20418 // Check that the high words (being shuffled) are the identity in the
20419 // dword shuffle, and the low words are self-contained.
20420 if (Mask[2] != 2 || Mask[3] != 3 ||
20421 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20424 Chain.push_back(V);
20427 case X86ISD::UNPCKL:
20428 case X86ISD::UNPCKH:
20429 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20430 // shuffle into a preceding word shuffle.
20431 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20434 // Search for a half-shuffle which we can combine with.
20435 unsigned CombineOp =
20436 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20437 if (V.getOperand(0) != V.getOperand(1) ||
20438 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20440 Chain.push_back(V);
20441 V = V.getOperand(0);
20443 switch (V.getOpcode()) {
20445 return SDValue(); // Nothing to combine.
20447 case X86ISD::PSHUFLW:
20448 case X86ISD::PSHUFHW:
20449 if (V.getOpcode() == CombineOp)
20452 Chain.push_back(V);
20456 V = V.getOperand(0);
20460 } while (V.hasOneUse());
20463 // Break out of the loop if we break out of the switch.
20467 if (!V.hasOneUse())
20468 // We fell out of the loop without finding a viable combining instruction.
20471 // Merge this node's mask and our incoming mask.
20472 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20473 for (int &M : Mask)
20475 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20476 getV4X86ShuffleImm8ForMask(Mask, DAG));
20478 // Rebuild the chain around this new shuffle.
20479 while (!Chain.empty()) {
20480 SDValue W = Chain.pop_back_val();
20482 if (V.getValueType() != W.getOperand(0).getValueType())
20483 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20485 switch (W.getOpcode()) {
20487 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20489 case X86ISD::UNPCKL:
20490 case X86ISD::UNPCKH:
20491 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20494 case X86ISD::PSHUFD:
20495 case X86ISD::PSHUFLW:
20496 case X86ISD::PSHUFHW:
20497 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20501 if (V.getValueType() != N.getValueType())
20502 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20504 // Return the new chain to replace N.
20508 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20510 /// We walk up the chain, skipping shuffles of the other half and looking
20511 /// through shuffles which switch halves trying to find a shuffle of the same
20512 /// pair of dwords.
20513 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20515 TargetLowering::DAGCombinerInfo &DCI) {
20517 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20518 "Called with something other than an x86 128-bit half shuffle!");
20520 unsigned CombineOpcode = N.getOpcode();
20522 // Walk up a single-use chain looking for a combinable shuffle.
20523 SDValue V = N.getOperand(0);
20524 for (; V.hasOneUse(); V = V.getOperand(0)) {
20525 switch (V.getOpcode()) {
20527 return false; // Nothing combined!
20530 // Skip bitcasts as we always know the type for the target specific
20534 case X86ISD::PSHUFLW:
20535 case X86ISD::PSHUFHW:
20536 if (V.getOpcode() == CombineOpcode)
20539 // Other-half shuffles are no-ops.
20542 // Break out of the loop if we break out of the switch.
20546 if (!V.hasOneUse())
20547 // We fell out of the loop without finding a viable combining instruction.
20550 // Combine away the bottom node as its shuffle will be accumulated into
20551 // a preceding shuffle.
20552 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20554 // Record the old value.
20557 // Merge this node's mask and our incoming mask (adjusted to account for all
20558 // the pshufd instructions encountered).
20559 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20560 for (int &M : Mask)
20562 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20563 getV4X86ShuffleImm8ForMask(Mask, DAG));
20565 // Check that the shuffles didn't cancel each other out. If not, we need to
20566 // combine to the new one.
20568 // Replace the combinable shuffle with the combined one, updating all users
20569 // so that we re-evaluate the chain here.
20570 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20575 /// \brief Try to combine x86 target specific shuffles.
20576 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20577 TargetLowering::DAGCombinerInfo &DCI,
20578 const X86Subtarget *Subtarget) {
20580 MVT VT = N.getSimpleValueType();
20581 SmallVector<int, 4> Mask;
20583 switch (N.getOpcode()) {
20584 case X86ISD::PSHUFD:
20585 case X86ISD::PSHUFLW:
20586 case X86ISD::PSHUFHW:
20587 Mask = getPSHUFShuffleMask(N);
20588 assert(Mask.size() == 4);
20594 // Nuke no-op shuffles that show up after combining.
20595 if (isNoopShuffleMask(Mask))
20596 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20598 // Look for simplifications involving one or two shuffle instructions.
20599 SDValue V = N.getOperand(0);
20600 switch (N.getOpcode()) {
20603 case X86ISD::PSHUFLW:
20604 case X86ISD::PSHUFHW:
20605 assert(VT == MVT::v8i16);
20608 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20609 return SDValue(); // We combined away this shuffle, so we're done.
20611 // See if this reduces to a PSHUFD which is no more expensive and can
20612 // combine with more operations.
20613 if (canWidenShuffleElements(Mask)) {
20614 int DMask[] = {-1, -1, -1, -1};
20615 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20616 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20617 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20618 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20619 DCI.AddToWorklist(V.getNode());
20620 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20621 getV4X86ShuffleImm8ForMask(DMask, DAG));
20622 DCI.AddToWorklist(V.getNode());
20623 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20626 // Look for shuffle patterns which can be implemented as a single unpack.
20627 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20628 // only works when we have a PSHUFD followed by two half-shuffles.
20629 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20630 (V.getOpcode() == X86ISD::PSHUFLW ||
20631 V.getOpcode() == X86ISD::PSHUFHW) &&
20632 V.getOpcode() != N.getOpcode() &&
20634 SDValue D = V.getOperand(0);
20635 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20636 D = D.getOperand(0);
20637 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20638 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20639 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20640 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20641 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20643 for (int i = 0; i < 4; ++i) {
20644 WordMask[i + NOffset] = Mask[i] + NOffset;
20645 WordMask[i + VOffset] = VMask[i] + VOffset;
20647 // Map the word mask through the DWord mask.
20649 for (int i = 0; i < 8; ++i)
20650 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20651 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20652 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20653 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20654 std::begin(UnpackLoMask)) ||
20655 std::equal(std::begin(MappedMask), std::end(MappedMask),
20656 std::begin(UnpackHiMask))) {
20657 // We can replace all three shuffles with an unpack.
20658 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20659 DCI.AddToWorklist(V.getNode());
20660 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20662 DL, MVT::v8i16, V, V);
20669 case X86ISD::PSHUFD:
20670 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20679 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20681 /// We combine this directly on the abstract vector shuffle nodes so it is
20682 /// easier to generically match. We also insert dummy vector shuffle nodes for
20683 /// the operands which explicitly discard the lanes which are unused by this
20684 /// operation to try to flow through the rest of the combiner the fact that
20685 /// they're unused.
20686 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20688 EVT VT = N->getValueType(0);
20690 // We only handle target-independent shuffles.
20691 // FIXME: It would be easy and harmless to use the target shuffle mask
20692 // extraction tool to support more.
20693 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20696 auto *SVN = cast<ShuffleVectorSDNode>(N);
20697 ArrayRef<int> Mask = SVN->getMask();
20698 SDValue V1 = N->getOperand(0);
20699 SDValue V2 = N->getOperand(1);
20701 // We require the first shuffle operand to be the SUB node, and the second to
20702 // be the ADD node.
20703 // FIXME: We should support the commuted patterns.
20704 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20707 // If there are other uses of these operations we can't fold them.
20708 if (!V1->hasOneUse() || !V2->hasOneUse())
20711 // Ensure that both operations have the same operands. Note that we can
20712 // commute the FADD operands.
20713 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20714 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20715 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20718 // We're looking for blends between FADD and FSUB nodes. We insist on these
20719 // nodes being lined up in a specific expected pattern.
20720 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20721 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20722 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20725 // Only specific types are legal at this point, assert so we notice if and
20726 // when these change.
20727 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20728 VT == MVT::v4f64) &&
20729 "Unknown vector type encountered!");
20731 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20734 /// PerformShuffleCombine - Performs several different shuffle combines.
20735 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20736 TargetLowering::DAGCombinerInfo &DCI,
20737 const X86Subtarget *Subtarget) {
20739 SDValue N0 = N->getOperand(0);
20740 SDValue N1 = N->getOperand(1);
20741 EVT VT = N->getValueType(0);
20743 // Don't create instructions with illegal types after legalize types has run.
20744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20745 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20748 // If we have legalized the vector types, look for blends of FADD and FSUB
20749 // nodes that we can fuse into an ADDSUB node.
20750 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20751 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20754 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20755 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20756 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20757 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20759 // During Type Legalization, when promoting illegal vector types,
20760 // the backend might introduce new shuffle dag nodes and bitcasts.
20762 // This code performs the following transformation:
20763 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20764 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20766 // We do this only if both the bitcast and the BINOP dag nodes have
20767 // one use. Also, perform this transformation only if the new binary
20768 // operation is legal. This is to avoid introducing dag nodes that
20769 // potentially need to be further expanded (or custom lowered) into a
20770 // less optimal sequence of dag nodes.
20771 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20772 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20773 N0.getOpcode() == ISD::BITCAST) {
20774 SDValue BC0 = N0.getOperand(0);
20775 EVT SVT = BC0.getValueType();
20776 unsigned Opcode = BC0.getOpcode();
20777 unsigned NumElts = VT.getVectorNumElements();
20779 if (BC0.hasOneUse() && SVT.isVector() &&
20780 SVT.getVectorNumElements() * 2 == NumElts &&
20781 TLI.isOperationLegal(Opcode, VT)) {
20782 bool CanFold = false;
20794 unsigned SVTNumElts = SVT.getVectorNumElements();
20795 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20796 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20797 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20798 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20799 CanFold = SVOp->getMaskElt(i) < 0;
20802 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20803 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20804 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20805 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20810 // Only handle 128 wide vector from here on.
20811 if (!VT.is128BitVector())
20814 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20815 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20816 // consecutive, non-overlapping, and in the right order.
20817 SmallVector<SDValue, 16> Elts;
20818 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20819 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20821 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20825 if (isTargetShuffle(N->getOpcode())) {
20827 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20828 if (Shuffle.getNode())
20831 // Try recursively combining arbitrary sequences of x86 shuffle
20832 // instructions into higher-order shuffles. We do this after combining
20833 // specific PSHUF instruction sequences into their minimal form so that we
20834 // can evaluate how many specialized shuffle instructions are involved in
20835 // a particular chain.
20836 SmallVector<int, 1> NonceMask; // Just a placeholder.
20837 NonceMask.push_back(0);
20838 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20839 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20841 return SDValue(); // This routine will use CombineTo to replace N.
20847 /// PerformTruncateCombine - Converts truncate operation to
20848 /// a sequence of vector shuffle operations.
20849 /// It is possible when we truncate 256-bit vector to 128-bit vector
20850 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20851 TargetLowering::DAGCombinerInfo &DCI,
20852 const X86Subtarget *Subtarget) {
20856 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20857 /// specific shuffle of a load can be folded into a single element load.
20858 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20859 /// shuffles have been customed lowered so we need to handle those here.
20860 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20861 TargetLowering::DAGCombinerInfo &DCI) {
20862 if (DCI.isBeforeLegalizeOps())
20865 SDValue InVec = N->getOperand(0);
20866 SDValue EltNo = N->getOperand(1);
20868 if (!isa<ConstantSDNode>(EltNo))
20871 EVT VT = InVec.getValueType();
20873 if (InVec.getOpcode() == ISD::BITCAST) {
20874 // Don't duplicate a load with other uses.
20875 if (!InVec.hasOneUse())
20877 EVT BCVT = InVec.getOperand(0).getValueType();
20878 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20880 InVec = InVec.getOperand(0);
20883 if (!isTargetShuffle(InVec.getOpcode()))
20886 // Don't duplicate a load with other uses.
20887 if (!InVec.hasOneUse())
20890 SmallVector<int, 16> ShuffleMask;
20892 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20896 // Select the input vector, guarding against out of range extract vector.
20897 unsigned NumElems = VT.getVectorNumElements();
20898 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20899 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20900 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20901 : InVec.getOperand(1);
20903 // If inputs to shuffle are the same for both ops, then allow 2 uses
20904 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20906 if (LdNode.getOpcode() == ISD::BITCAST) {
20907 // Don't duplicate a load with other uses.
20908 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20911 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20912 LdNode = LdNode.getOperand(0);
20915 if (!ISD::isNormalLoad(LdNode.getNode()))
20918 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20920 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20923 EVT EltVT = N->getValueType(0);
20924 // If there's a bitcast before the shuffle, check if the load type and
20925 // alignment is valid.
20926 unsigned Align = LN0->getAlignment();
20927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20928 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20929 EltVT.getTypeForEVT(*DAG.getContext()));
20931 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20934 // All checks match so transform back to vector_shuffle so that DAG combiner
20935 // can finish the job
20938 // Create shuffle node taking into account the case that its a unary shuffle
20939 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20940 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20941 InVec.getOperand(0), Shuffle,
20943 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20944 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20948 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20949 /// generation and convert it from being a bunch of shuffles and extracts
20950 /// to a simple store and scalar loads to extract the elements.
20951 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20952 TargetLowering::DAGCombinerInfo &DCI) {
20953 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20954 if (NewOp.getNode())
20957 SDValue InputVector = N->getOperand(0);
20959 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20960 // from mmx to v2i32 has a single usage.
20961 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20962 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20963 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20964 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20965 N->getValueType(0),
20966 InputVector.getNode()->getOperand(0));
20968 // Only operate on vectors of 4 elements, where the alternative shuffling
20969 // gets to be more expensive.
20970 if (InputVector.getValueType() != MVT::v4i32)
20973 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20974 // single use which is a sign-extend or zero-extend, and all elements are
20976 SmallVector<SDNode *, 4> Uses;
20977 unsigned ExtractedElements = 0;
20978 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20979 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20980 if (UI.getUse().getResNo() != InputVector.getResNo())
20983 SDNode *Extract = *UI;
20984 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20987 if (Extract->getValueType(0) != MVT::i32)
20989 if (!Extract->hasOneUse())
20991 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20992 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20994 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20997 // Record which element was extracted.
20998 ExtractedElements |=
20999 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21001 Uses.push_back(Extract);
21004 // If not all the elements were used, this may not be worthwhile.
21005 if (ExtractedElements != 15)
21008 // Ok, we've now decided to do the transformation.
21009 SDLoc dl(InputVector);
21011 // Store the value to a temporary stack slot.
21012 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21013 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21014 MachinePointerInfo(), false, false, 0);
21016 // Replace each use (extract) with a load of the appropriate element.
21017 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21018 UE = Uses.end(); UI != UE; ++UI) {
21019 SDNode *Extract = *UI;
21021 // cOMpute the element's address.
21022 SDValue Idx = Extract->getOperand(1);
21024 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21025 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21027 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21029 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21030 StackPtr, OffsetVal);
21032 // Load the scalar.
21033 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21034 ScalarAddr, MachinePointerInfo(),
21035 false, false, false, 0);
21037 // Replace the exact with the load.
21038 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21041 // The replacement was made in place; don't return anything.
21045 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21046 static std::pair<unsigned, bool>
21047 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21048 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21049 if (!VT.isVector())
21050 return std::make_pair(0, false);
21052 bool NeedSplit = false;
21053 switch (VT.getSimpleVT().SimpleTy) {
21054 default: return std::make_pair(0, false);
21058 if (!Subtarget->hasAVX2())
21060 if (!Subtarget->hasAVX())
21061 return std::make_pair(0, false);
21066 if (!Subtarget->hasSSE2())
21067 return std::make_pair(0, false);
21070 // SSE2 has only a small subset of the operations.
21071 bool hasUnsigned = Subtarget->hasSSE41() ||
21072 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21073 bool hasSigned = Subtarget->hasSSE41() ||
21074 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21076 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21079 // Check for x CC y ? x : y.
21080 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21081 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21086 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21089 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21092 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21095 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21097 // Check for x CC y ? y : x -- a min/max with reversed arms.
21098 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21099 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21104 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21107 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21110 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21113 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21117 return std::make_pair(Opc, NeedSplit);
21121 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21122 const X86Subtarget *Subtarget) {
21124 SDValue Cond = N->getOperand(0);
21125 SDValue LHS = N->getOperand(1);
21126 SDValue RHS = N->getOperand(2);
21128 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21129 SDValue CondSrc = Cond->getOperand(0);
21130 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21131 Cond = CondSrc->getOperand(0);
21134 MVT VT = N->getSimpleValueType(0);
21135 MVT EltVT = VT.getVectorElementType();
21136 unsigned NumElems = VT.getVectorNumElements();
21137 // There is no blend with immediate in AVX-512.
21138 if (VT.is512BitVector())
21141 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21143 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21146 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21149 // A vselect where all conditions and data are constants can be optimized into
21150 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21151 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21152 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21155 unsigned MaskValue = 0;
21156 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21159 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21160 for (unsigned i = 0; i < NumElems; ++i) {
21161 // Be sure we emit undef where we can.
21162 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21163 ShuffleMask[i] = -1;
21165 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21168 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21171 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21173 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21174 TargetLowering::DAGCombinerInfo &DCI,
21175 const X86Subtarget *Subtarget) {
21177 SDValue Cond = N->getOperand(0);
21178 // Get the LHS/RHS of the select.
21179 SDValue LHS = N->getOperand(1);
21180 SDValue RHS = N->getOperand(2);
21181 EVT VT = LHS.getValueType();
21182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21184 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21185 // instructions match the semantics of the common C idiom x<y?x:y but not
21186 // x<=y?x:y, because of how they handle negative zero (which can be
21187 // ignored in unsafe-math mode).
21188 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21189 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21190 (Subtarget->hasSSE2() ||
21191 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21192 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21194 unsigned Opcode = 0;
21195 // Check for x CC y ? x : y.
21196 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21197 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21201 // Converting this to a min would handle NaNs incorrectly, and swapping
21202 // the operands would cause it to handle comparisons between positive
21203 // and negative zero incorrectly.
21204 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21205 if (!DAG.getTarget().Options.UnsafeFPMath &&
21206 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21208 std::swap(LHS, RHS);
21210 Opcode = X86ISD::FMIN;
21213 // Converting this to a min would handle comparisons between positive
21214 // and negative zero incorrectly.
21215 if (!DAG.getTarget().Options.UnsafeFPMath &&
21216 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21218 Opcode = X86ISD::FMIN;
21221 // Converting this to a min would handle both negative zeros and NaNs
21222 // incorrectly, but we can swap the operands to fix both.
21223 std::swap(LHS, RHS);
21227 Opcode = X86ISD::FMIN;
21231 // Converting this to a max would handle comparisons between positive
21232 // and negative zero incorrectly.
21233 if (!DAG.getTarget().Options.UnsafeFPMath &&
21234 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21236 Opcode = X86ISD::FMAX;
21239 // Converting this to a max would handle NaNs incorrectly, and swapping
21240 // the operands would cause it to handle comparisons between positive
21241 // and negative zero incorrectly.
21242 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21243 if (!DAG.getTarget().Options.UnsafeFPMath &&
21244 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21246 std::swap(LHS, RHS);
21248 Opcode = X86ISD::FMAX;
21251 // Converting this to a max would handle both negative zeros and NaNs
21252 // incorrectly, but we can swap the operands to fix both.
21253 std::swap(LHS, RHS);
21257 Opcode = X86ISD::FMAX;
21260 // Check for x CC y ? y : x -- a min/max with reversed arms.
21261 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21262 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21266 // Converting this to a min would handle comparisons between positive
21267 // and negative zero incorrectly, and swapping the operands would
21268 // cause it to handle NaNs incorrectly.
21269 if (!DAG.getTarget().Options.UnsafeFPMath &&
21270 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21271 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21273 std::swap(LHS, RHS);
21275 Opcode = X86ISD::FMIN;
21278 // Converting this to a min would handle NaNs incorrectly.
21279 if (!DAG.getTarget().Options.UnsafeFPMath &&
21280 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21282 Opcode = X86ISD::FMIN;
21285 // Converting this to a min would handle both negative zeros and NaNs
21286 // incorrectly, but we can swap the operands to fix both.
21287 std::swap(LHS, RHS);
21291 Opcode = X86ISD::FMIN;
21295 // Converting this to a max would handle NaNs incorrectly.
21296 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21298 Opcode = X86ISD::FMAX;
21301 // Converting this to a max would handle comparisons between positive
21302 // and negative zero incorrectly, and swapping the operands would
21303 // cause it to handle NaNs incorrectly.
21304 if (!DAG.getTarget().Options.UnsafeFPMath &&
21305 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21306 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21308 std::swap(LHS, RHS);
21310 Opcode = X86ISD::FMAX;
21313 // Converting this to a max would handle both negative zeros and NaNs
21314 // incorrectly, but we can swap the operands to fix both.
21315 std::swap(LHS, RHS);
21319 Opcode = X86ISD::FMAX;
21325 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21328 EVT CondVT = Cond.getValueType();
21329 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21330 CondVT.getVectorElementType() == MVT::i1) {
21331 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21332 // lowering on KNL. In this case we convert it to
21333 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21334 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21335 // Since SKX these selects have a proper lowering.
21336 EVT OpVT = LHS.getValueType();
21337 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21338 (OpVT.getVectorElementType() == MVT::i8 ||
21339 OpVT.getVectorElementType() == MVT::i16) &&
21340 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21341 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21342 DCI.AddToWorklist(Cond.getNode());
21343 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21346 // If this is a select between two integer constants, try to do some
21348 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21349 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21350 // Don't do this for crazy integer types.
21351 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21352 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21353 // so that TrueC (the true value) is larger than FalseC.
21354 bool NeedsCondInvert = false;
21356 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21357 // Efficiently invertible.
21358 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21359 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21360 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21361 NeedsCondInvert = true;
21362 std::swap(TrueC, FalseC);
21365 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21366 if (FalseC->getAPIntValue() == 0 &&
21367 TrueC->getAPIntValue().isPowerOf2()) {
21368 if (NeedsCondInvert) // Invert the condition if needed.
21369 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21370 DAG.getConstant(1, Cond.getValueType()));
21372 // Zero extend the condition if needed.
21373 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21375 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21376 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21377 DAG.getConstant(ShAmt, MVT::i8));
21380 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21381 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21382 if (NeedsCondInvert) // Invert the condition if needed.
21383 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21384 DAG.getConstant(1, Cond.getValueType()));
21386 // Zero extend the condition if needed.
21387 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21388 FalseC->getValueType(0), Cond);
21389 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21390 SDValue(FalseC, 0));
21393 // Optimize cases that will turn into an LEA instruction. This requires
21394 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21395 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21396 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21397 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21399 bool isFastMultiplier = false;
21401 switch ((unsigned char)Diff) {
21403 case 1: // result = add base, cond
21404 case 2: // result = lea base( , cond*2)
21405 case 3: // result = lea base(cond, cond*2)
21406 case 4: // result = lea base( , cond*4)
21407 case 5: // result = lea base(cond, cond*4)
21408 case 8: // result = lea base( , cond*8)
21409 case 9: // result = lea base(cond, cond*8)
21410 isFastMultiplier = true;
21415 if (isFastMultiplier) {
21416 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21417 if (NeedsCondInvert) // Invert the condition if needed.
21418 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21419 DAG.getConstant(1, Cond.getValueType()));
21421 // Zero extend the condition if needed.
21422 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21424 // Scale the condition by the difference.
21426 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21427 DAG.getConstant(Diff, Cond.getValueType()));
21429 // Add the base if non-zero.
21430 if (FalseC->getAPIntValue() != 0)
21431 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21432 SDValue(FalseC, 0));
21439 // Canonicalize max and min:
21440 // (x > y) ? x : y -> (x >= y) ? x : y
21441 // (x < y) ? x : y -> (x <= y) ? x : y
21442 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21443 // the need for an extra compare
21444 // against zero. e.g.
21445 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21447 // testl %edi, %edi
21449 // cmovgl %edi, %eax
21453 // cmovsl %eax, %edi
21454 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21455 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21456 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21457 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21462 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21463 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21464 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21465 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21470 // Early exit check
21471 if (!TLI.isTypeLegal(VT))
21474 // Match VSELECTs into subs with unsigned saturation.
21475 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21476 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21477 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21478 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21479 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21481 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21482 // left side invert the predicate to simplify logic below.
21484 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21486 CC = ISD::getSetCCInverse(CC, true);
21487 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21491 if (Other.getNode() && Other->getNumOperands() == 2 &&
21492 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21493 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21494 SDValue CondRHS = Cond->getOperand(1);
21496 // Look for a general sub with unsigned saturation first.
21497 // x >= y ? x-y : 0 --> subus x, y
21498 // x > y ? x-y : 0 --> subus x, y
21499 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21500 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21501 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21503 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21504 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21505 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21506 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21507 // If the RHS is a constant we have to reverse the const
21508 // canonicalization.
21509 // x > C-1 ? x+-C : 0 --> subus x, C
21510 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21511 CondRHSConst->getAPIntValue() ==
21512 (-OpRHSConst->getAPIntValue() - 1))
21513 return DAG.getNode(
21514 X86ISD::SUBUS, DL, VT, OpLHS,
21515 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21517 // Another special case: If C was a sign bit, the sub has been
21518 // canonicalized into a xor.
21519 // FIXME: Would it be better to use computeKnownBits to determine
21520 // whether it's safe to decanonicalize the xor?
21521 // x s< 0 ? x^C : 0 --> subus x, C
21522 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21523 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21524 OpRHSConst->getAPIntValue().isSignBit())
21525 // Note that we have to rebuild the RHS constant here to ensure we
21526 // don't rely on particular values of undef lanes.
21527 return DAG.getNode(
21528 X86ISD::SUBUS, DL, VT, OpLHS,
21529 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21534 // Try to match a min/max vector operation.
21535 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21536 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21537 unsigned Opc = ret.first;
21538 bool NeedSplit = ret.second;
21540 if (Opc && NeedSplit) {
21541 unsigned NumElems = VT.getVectorNumElements();
21542 // Extract the LHS vectors
21543 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21544 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21546 // Extract the RHS vectors
21547 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21548 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21550 // Create min/max for each subvector
21551 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21552 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21554 // Merge the result
21555 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21557 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21560 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21561 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21562 // Check if SETCC has already been promoted
21563 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21564 // Check that condition value type matches vselect operand type
21567 assert(Cond.getValueType().isVector() &&
21568 "vector select expects a vector selector!");
21570 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21571 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21573 if (!TValIsAllOnes && !FValIsAllZeros) {
21574 // Try invert the condition if true value is not all 1s and false value
21576 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21577 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21579 if (TValIsAllZeros || FValIsAllOnes) {
21580 SDValue CC = Cond.getOperand(2);
21581 ISD::CondCode NewCC =
21582 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21583 Cond.getOperand(0).getValueType().isInteger());
21584 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21585 std::swap(LHS, RHS);
21586 TValIsAllOnes = FValIsAllOnes;
21587 FValIsAllZeros = TValIsAllZeros;
21591 if (TValIsAllOnes || FValIsAllZeros) {
21594 if (TValIsAllOnes && FValIsAllZeros)
21596 else if (TValIsAllOnes)
21597 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21598 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21599 else if (FValIsAllZeros)
21600 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21601 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21603 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21607 // Try to fold this VSELECT into a MOVSS/MOVSD
21608 if (N->getOpcode() == ISD::VSELECT &&
21609 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21610 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21611 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21612 bool CanFold = false;
21613 unsigned NumElems = Cond.getNumOperands();
21617 if (isZero(Cond.getOperand(0))) {
21620 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21621 // fold (vselect <0,-1> -> (movsd A, B)
21622 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21623 CanFold = isAllOnes(Cond.getOperand(i));
21624 } else if (isAllOnes(Cond.getOperand(0))) {
21628 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21629 // fold (vselect <-1,0> -> (movsd B, A)
21630 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21631 CanFold = isZero(Cond.getOperand(i));
21635 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21636 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21637 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21640 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21641 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21642 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21643 // (v2i64 (bitcast B)))))
21645 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21646 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21647 // (v2f64 (bitcast B)))))
21649 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21650 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21651 // (v2i64 (bitcast A)))))
21653 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21654 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21655 // (v2f64 (bitcast A)))))
21657 CanFold = (isZero(Cond.getOperand(0)) &&
21658 isZero(Cond.getOperand(1)) &&
21659 isAllOnes(Cond.getOperand(2)) &&
21660 isAllOnes(Cond.getOperand(3)));
21662 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21663 isAllOnes(Cond.getOperand(1)) &&
21664 isZero(Cond.getOperand(2)) &&
21665 isZero(Cond.getOperand(3))) {
21667 std::swap(LHS, RHS);
21671 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21672 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21673 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21674 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21676 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21682 // If we know that this node is legal then we know that it is going to be
21683 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21684 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21685 // to simplify previous instructions.
21686 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21687 !DCI.isBeforeLegalize() &&
21688 // We explicitly check against v8i16 and v16i16 because, although
21689 // they're marked as Custom, they might only be legal when Cond is a
21690 // build_vector of constants. This will be taken care in a later
21692 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21693 VT != MVT::v8i16)) {
21694 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21696 // Don't optimize vector selects that map to mask-registers.
21700 // Check all uses of that condition operand to check whether it will be
21701 // consumed by non-BLEND instructions, which may depend on all bits are set
21703 for (SDNode::use_iterator I = Cond->use_begin(),
21704 E = Cond->use_end(); I != E; ++I)
21705 if (I->getOpcode() != ISD::VSELECT)
21706 // TODO: Add other opcodes eventually lowered into BLEND.
21709 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21710 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21712 APInt KnownZero, KnownOne;
21713 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21714 DCI.isBeforeLegalizeOps());
21715 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21716 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21717 DCI.CommitTargetLoweringOpt(TLO);
21720 // We should generate an X86ISD::BLENDI from a vselect if its argument
21721 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21722 // constants. This specific pattern gets generated when we split a
21723 // selector for a 512 bit vector in a machine without AVX512 (but with
21724 // 256-bit vectors), during legalization:
21726 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21728 // Iff we find this pattern and the build_vectors are built from
21729 // constants, we translate the vselect into a shuffle_vector that we
21730 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21731 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21732 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21733 if (Shuffle.getNode())
21740 // Check whether a boolean test is testing a boolean value generated by
21741 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21744 // Simplify the following patterns:
21745 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21746 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21747 // to (Op EFLAGS Cond)
21749 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21750 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21751 // to (Op EFLAGS !Cond)
21753 // where Op could be BRCOND or CMOV.
21755 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21756 // Quit if not CMP and SUB with its value result used.
21757 if (Cmp.getOpcode() != X86ISD::CMP &&
21758 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21761 // Quit if not used as a boolean value.
21762 if (CC != X86::COND_E && CC != X86::COND_NE)
21765 // Check CMP operands. One of them should be 0 or 1 and the other should be
21766 // an SetCC or extended from it.
21767 SDValue Op1 = Cmp.getOperand(0);
21768 SDValue Op2 = Cmp.getOperand(1);
21771 const ConstantSDNode* C = nullptr;
21772 bool needOppositeCond = (CC == X86::COND_E);
21773 bool checkAgainstTrue = false; // Is it a comparison against 1?
21775 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21777 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21779 else // Quit if all operands are not constants.
21782 if (C->getZExtValue() == 1) {
21783 needOppositeCond = !needOppositeCond;
21784 checkAgainstTrue = true;
21785 } else if (C->getZExtValue() != 0)
21786 // Quit if the constant is neither 0 or 1.
21789 bool truncatedToBoolWithAnd = false;
21790 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21791 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21792 SetCC.getOpcode() == ISD::TRUNCATE ||
21793 SetCC.getOpcode() == ISD::AND) {
21794 if (SetCC.getOpcode() == ISD::AND) {
21796 ConstantSDNode *CS;
21797 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21798 CS->getZExtValue() == 1)
21800 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21801 CS->getZExtValue() == 1)
21805 SetCC = SetCC.getOperand(OpIdx);
21806 truncatedToBoolWithAnd = true;
21808 SetCC = SetCC.getOperand(0);
21811 switch (SetCC.getOpcode()) {
21812 case X86ISD::SETCC_CARRY:
21813 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21814 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21815 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21816 // truncated to i1 using 'and'.
21817 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21819 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21820 "Invalid use of SETCC_CARRY!");
21822 case X86ISD::SETCC:
21823 // Set the condition code or opposite one if necessary.
21824 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21825 if (needOppositeCond)
21826 CC = X86::GetOppositeBranchCondition(CC);
21827 return SetCC.getOperand(1);
21828 case X86ISD::CMOV: {
21829 // Check whether false/true value has canonical one, i.e. 0 or 1.
21830 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21831 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21832 // Quit if true value is not a constant.
21835 // Quit if false value is not a constant.
21837 SDValue Op = SetCC.getOperand(0);
21838 // Skip 'zext' or 'trunc' node.
21839 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21840 Op.getOpcode() == ISD::TRUNCATE)
21841 Op = Op.getOperand(0);
21842 // A special case for rdrand/rdseed, where 0 is set if false cond is
21844 if ((Op.getOpcode() != X86ISD::RDRAND &&
21845 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21848 // Quit if false value is not the constant 0 or 1.
21849 bool FValIsFalse = true;
21850 if (FVal && FVal->getZExtValue() != 0) {
21851 if (FVal->getZExtValue() != 1)
21853 // If FVal is 1, opposite cond is needed.
21854 needOppositeCond = !needOppositeCond;
21855 FValIsFalse = false;
21857 // Quit if TVal is not the constant opposite of FVal.
21858 if (FValIsFalse && TVal->getZExtValue() != 1)
21860 if (!FValIsFalse && TVal->getZExtValue() != 0)
21862 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21863 if (needOppositeCond)
21864 CC = X86::GetOppositeBranchCondition(CC);
21865 return SetCC.getOperand(3);
21872 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21873 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21874 TargetLowering::DAGCombinerInfo &DCI,
21875 const X86Subtarget *Subtarget) {
21878 // If the flag operand isn't dead, don't touch this CMOV.
21879 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21882 SDValue FalseOp = N->getOperand(0);
21883 SDValue TrueOp = N->getOperand(1);
21884 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21885 SDValue Cond = N->getOperand(3);
21887 if (CC == X86::COND_E || CC == X86::COND_NE) {
21888 switch (Cond.getOpcode()) {
21892 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21893 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21894 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21900 Flags = checkBoolTestSetCCCombine(Cond, CC);
21901 if (Flags.getNode() &&
21902 // Extra check as FCMOV only supports a subset of X86 cond.
21903 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21904 SDValue Ops[] = { FalseOp, TrueOp,
21905 DAG.getConstant(CC, MVT::i8), Flags };
21906 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21909 // If this is a select between two integer constants, try to do some
21910 // optimizations. Note that the operands are ordered the opposite of SELECT
21912 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21913 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21914 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21915 // larger than FalseC (the false value).
21916 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21917 CC = X86::GetOppositeBranchCondition(CC);
21918 std::swap(TrueC, FalseC);
21919 std::swap(TrueOp, FalseOp);
21922 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21923 // This is efficient for any integer data type (including i8/i16) and
21925 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21926 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21927 DAG.getConstant(CC, MVT::i8), Cond);
21929 // Zero extend the condition if needed.
21930 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21932 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21933 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21934 DAG.getConstant(ShAmt, MVT::i8));
21935 if (N->getNumValues() == 2) // Dead flag value?
21936 return DCI.CombineTo(N, Cond, SDValue());
21940 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21941 // for any integer data type, including i8/i16.
21942 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21943 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21944 DAG.getConstant(CC, MVT::i8), Cond);
21946 // Zero extend the condition if needed.
21947 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21948 FalseC->getValueType(0), Cond);
21949 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21950 SDValue(FalseC, 0));
21952 if (N->getNumValues() == 2) // Dead flag value?
21953 return DCI.CombineTo(N, Cond, SDValue());
21957 // Optimize cases that will turn into an LEA instruction. This requires
21958 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21959 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21960 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21961 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21963 bool isFastMultiplier = false;
21965 switch ((unsigned char)Diff) {
21967 case 1: // result = add base, cond
21968 case 2: // result = lea base( , cond*2)
21969 case 3: // result = lea base(cond, cond*2)
21970 case 4: // result = lea base( , cond*4)
21971 case 5: // result = lea base(cond, cond*4)
21972 case 8: // result = lea base( , cond*8)
21973 case 9: // result = lea base(cond, cond*8)
21974 isFastMultiplier = true;
21979 if (isFastMultiplier) {
21980 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21981 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21982 DAG.getConstant(CC, MVT::i8), Cond);
21983 // Zero extend the condition if needed.
21984 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21986 // Scale the condition by the difference.
21988 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21989 DAG.getConstant(Diff, Cond.getValueType()));
21991 // Add the base if non-zero.
21992 if (FalseC->getAPIntValue() != 0)
21993 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21994 SDValue(FalseC, 0));
21995 if (N->getNumValues() == 2) // Dead flag value?
21996 return DCI.CombineTo(N, Cond, SDValue());
22003 // Handle these cases:
22004 // (select (x != c), e, c) -> select (x != c), e, x),
22005 // (select (x == c), c, e) -> select (x == c), x, e)
22006 // where the c is an integer constant, and the "select" is the combination
22007 // of CMOV and CMP.
22009 // The rationale for this change is that the conditional-move from a constant
22010 // needs two instructions, however, conditional-move from a register needs
22011 // only one instruction.
22013 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22014 // some instruction-combining opportunities. This opt needs to be
22015 // postponed as late as possible.
22017 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22018 // the DCI.xxxx conditions are provided to postpone the optimization as
22019 // late as possible.
22021 ConstantSDNode *CmpAgainst = nullptr;
22022 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22023 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22024 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22026 if (CC == X86::COND_NE &&
22027 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22028 CC = X86::GetOppositeBranchCondition(CC);
22029 std::swap(TrueOp, FalseOp);
22032 if (CC == X86::COND_E &&
22033 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22034 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22035 DAG.getConstant(CC, MVT::i8), Cond };
22036 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22044 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22045 const X86Subtarget *Subtarget) {
22046 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22048 default: return SDValue();
22049 // SSE/AVX/AVX2 blend intrinsics.
22050 case Intrinsic::x86_avx2_pblendvb:
22051 case Intrinsic::x86_avx2_pblendw:
22052 case Intrinsic::x86_avx2_pblendd_128:
22053 case Intrinsic::x86_avx2_pblendd_256:
22054 // Don't try to simplify this intrinsic if we don't have AVX2.
22055 if (!Subtarget->hasAVX2())
22058 case Intrinsic::x86_avx_blend_pd_256:
22059 case Intrinsic::x86_avx_blend_ps_256:
22060 case Intrinsic::x86_avx_blendv_pd_256:
22061 case Intrinsic::x86_avx_blendv_ps_256:
22062 // Don't try to simplify this intrinsic if we don't have AVX.
22063 if (!Subtarget->hasAVX())
22066 case Intrinsic::x86_sse41_pblendw:
22067 case Intrinsic::x86_sse41_blendpd:
22068 case Intrinsic::x86_sse41_blendps:
22069 case Intrinsic::x86_sse41_blendvps:
22070 case Intrinsic::x86_sse41_blendvpd:
22071 case Intrinsic::x86_sse41_pblendvb: {
22072 SDValue Op0 = N->getOperand(1);
22073 SDValue Op1 = N->getOperand(2);
22074 SDValue Mask = N->getOperand(3);
22076 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22077 if (!Subtarget->hasSSE41())
22080 // fold (blend A, A, Mask) -> A
22083 // fold (blend A, B, allZeros) -> A
22084 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22086 // fold (blend A, B, allOnes) -> B
22087 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22090 // Simplify the case where the mask is a constant i32 value.
22091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22092 if (C->isNullValue())
22094 if (C->isAllOnesValue())
22101 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22102 case Intrinsic::x86_sse2_psrai_w:
22103 case Intrinsic::x86_sse2_psrai_d:
22104 case Intrinsic::x86_avx2_psrai_w:
22105 case Intrinsic::x86_avx2_psrai_d:
22106 case Intrinsic::x86_sse2_psra_w:
22107 case Intrinsic::x86_sse2_psra_d:
22108 case Intrinsic::x86_avx2_psra_w:
22109 case Intrinsic::x86_avx2_psra_d: {
22110 SDValue Op0 = N->getOperand(1);
22111 SDValue Op1 = N->getOperand(2);
22112 EVT VT = Op0.getValueType();
22113 assert(VT.isVector() && "Expected a vector type!");
22115 if (isa<BuildVectorSDNode>(Op1))
22116 Op1 = Op1.getOperand(0);
22118 if (!isa<ConstantSDNode>(Op1))
22121 EVT SVT = VT.getVectorElementType();
22122 unsigned SVTBits = SVT.getSizeInBits();
22124 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22125 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22126 uint64_t ShAmt = C.getZExtValue();
22128 // Don't try to convert this shift into a ISD::SRA if the shift
22129 // count is bigger than or equal to the element size.
22130 if (ShAmt >= SVTBits)
22133 // Trivial case: if the shift count is zero, then fold this
22134 // into the first operand.
22138 // Replace this packed shift intrinsic with a target independent
22140 SDValue Splat = DAG.getConstant(C, VT);
22141 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22146 /// PerformMulCombine - Optimize a single multiply with constant into two
22147 /// in order to implement it with two cheaper instructions, e.g.
22148 /// LEA + SHL, LEA + LEA.
22149 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22150 TargetLowering::DAGCombinerInfo &DCI) {
22151 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22154 EVT VT = N->getValueType(0);
22155 if (VT != MVT::i64)
22158 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22161 uint64_t MulAmt = C->getZExtValue();
22162 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22165 uint64_t MulAmt1 = 0;
22166 uint64_t MulAmt2 = 0;
22167 if ((MulAmt % 9) == 0) {
22169 MulAmt2 = MulAmt / 9;
22170 } else if ((MulAmt % 5) == 0) {
22172 MulAmt2 = MulAmt / 5;
22173 } else if ((MulAmt % 3) == 0) {
22175 MulAmt2 = MulAmt / 3;
22178 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22181 if (isPowerOf2_64(MulAmt2) &&
22182 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22183 // If second multiplifer is pow2, issue it first. We want the multiply by
22184 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22186 std::swap(MulAmt1, MulAmt2);
22189 if (isPowerOf2_64(MulAmt1))
22190 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22191 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22193 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22194 DAG.getConstant(MulAmt1, VT));
22196 if (isPowerOf2_64(MulAmt2))
22197 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22198 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22200 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22201 DAG.getConstant(MulAmt2, VT));
22203 // Do not add new nodes to DAG combiner worklist.
22204 DCI.CombineTo(N, NewMul, false);
22209 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22210 SDValue N0 = N->getOperand(0);
22211 SDValue N1 = N->getOperand(1);
22212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22213 EVT VT = N0.getValueType();
22215 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22216 // since the result of setcc_c is all zero's or all ones.
22217 if (VT.isInteger() && !VT.isVector() &&
22218 N1C && N0.getOpcode() == ISD::AND &&
22219 N0.getOperand(1).getOpcode() == ISD::Constant) {
22220 SDValue N00 = N0.getOperand(0);
22221 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22222 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22223 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22224 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22225 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22226 APInt ShAmt = N1C->getAPIntValue();
22227 Mask = Mask.shl(ShAmt);
22229 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22230 N00, DAG.getConstant(Mask, VT));
22234 // Hardware support for vector shifts is sparse which makes us scalarize the
22235 // vector operations in many cases. Also, on sandybridge ADD is faster than
22237 // (shl V, 1) -> add V,V
22238 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22239 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22240 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22241 // We shift all of the values by one. In many cases we do not have
22242 // hardware support for this operation. This is better expressed as an ADD
22244 if (N1SplatC->getZExtValue() == 1)
22245 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22251 /// \brief Returns a vector of 0s if the node in input is a vector logical
22252 /// shift by a constant amount which is known to be bigger than or equal
22253 /// to the vector element size in bits.
22254 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22255 const X86Subtarget *Subtarget) {
22256 EVT VT = N->getValueType(0);
22258 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22259 (!Subtarget->hasInt256() ||
22260 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22263 SDValue Amt = N->getOperand(1);
22265 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22266 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22267 APInt ShiftAmt = AmtSplat->getAPIntValue();
22268 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22270 // SSE2/AVX2 logical shifts always return a vector of 0s
22271 // if the shift amount is bigger than or equal to
22272 // the element size. The constant shift amount will be
22273 // encoded as a 8-bit immediate.
22274 if (ShiftAmt.trunc(8).uge(MaxAmount))
22275 return getZeroVector(VT, Subtarget, DAG, DL);
22281 /// PerformShiftCombine - Combine shifts.
22282 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22283 TargetLowering::DAGCombinerInfo &DCI,
22284 const X86Subtarget *Subtarget) {
22285 if (N->getOpcode() == ISD::SHL) {
22286 SDValue V = PerformSHLCombine(N, DAG);
22287 if (V.getNode()) return V;
22290 if (N->getOpcode() != ISD::SRA) {
22291 // Try to fold this logical shift into a zero vector.
22292 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22293 if (V.getNode()) return V;
22299 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22300 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22301 // and friends. Likewise for OR -> CMPNEQSS.
22302 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22303 TargetLowering::DAGCombinerInfo &DCI,
22304 const X86Subtarget *Subtarget) {
22307 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22308 // we're requiring SSE2 for both.
22309 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22310 SDValue N0 = N->getOperand(0);
22311 SDValue N1 = N->getOperand(1);
22312 SDValue CMP0 = N0->getOperand(1);
22313 SDValue CMP1 = N1->getOperand(1);
22316 // The SETCCs should both refer to the same CMP.
22317 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22320 SDValue CMP00 = CMP0->getOperand(0);
22321 SDValue CMP01 = CMP0->getOperand(1);
22322 EVT VT = CMP00.getValueType();
22324 if (VT == MVT::f32 || VT == MVT::f64) {
22325 bool ExpectingFlags = false;
22326 // Check for any users that want flags:
22327 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22328 !ExpectingFlags && UI != UE; ++UI)
22329 switch (UI->getOpcode()) {
22334 ExpectingFlags = true;
22336 case ISD::CopyToReg:
22337 case ISD::SIGN_EXTEND:
22338 case ISD::ZERO_EXTEND:
22339 case ISD::ANY_EXTEND:
22343 if (!ExpectingFlags) {
22344 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22345 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22347 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22348 X86::CondCode tmp = cc0;
22353 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22354 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22355 // FIXME: need symbolic constants for these magic numbers.
22356 // See X86ATTInstPrinter.cpp:printSSECC().
22357 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22358 if (Subtarget->hasAVX512()) {
22359 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22360 CMP01, DAG.getConstant(x86cc, MVT::i8));
22361 if (N->getValueType(0) != MVT::i1)
22362 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22366 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22367 CMP00.getValueType(), CMP00, CMP01,
22368 DAG.getConstant(x86cc, MVT::i8));
22370 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22371 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22373 if (is64BitFP && !Subtarget->is64Bit()) {
22374 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22375 // 64-bit integer, since that's not a legal type. Since
22376 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22377 // bits, but can do this little dance to extract the lowest 32 bits
22378 // and work with those going forward.
22379 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22381 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22383 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22384 Vector32, DAG.getIntPtrConstant(0));
22388 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22389 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22390 DAG.getConstant(1, IntVT));
22391 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22392 return OneBitOfTruth;
22400 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22401 /// so it can be folded inside ANDNP.
22402 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22403 EVT VT = N->getValueType(0);
22405 // Match direct AllOnes for 128 and 256-bit vectors
22406 if (ISD::isBuildVectorAllOnes(N))
22409 // Look through a bit convert.
22410 if (N->getOpcode() == ISD::BITCAST)
22411 N = N->getOperand(0).getNode();
22413 // Sometimes the operand may come from a insert_subvector building a 256-bit
22415 if (VT.is256BitVector() &&
22416 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22417 SDValue V1 = N->getOperand(0);
22418 SDValue V2 = N->getOperand(1);
22420 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22421 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22422 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22423 ISD::isBuildVectorAllOnes(V2.getNode()))
22430 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22431 // register. In most cases we actually compare or select YMM-sized registers
22432 // and mixing the two types creates horrible code. This method optimizes
22433 // some of the transition sequences.
22434 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22435 TargetLowering::DAGCombinerInfo &DCI,
22436 const X86Subtarget *Subtarget) {
22437 EVT VT = N->getValueType(0);
22438 if (!VT.is256BitVector())
22441 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22442 N->getOpcode() == ISD::ZERO_EXTEND ||
22443 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22445 SDValue Narrow = N->getOperand(0);
22446 EVT NarrowVT = Narrow->getValueType(0);
22447 if (!NarrowVT.is128BitVector())
22450 if (Narrow->getOpcode() != ISD::XOR &&
22451 Narrow->getOpcode() != ISD::AND &&
22452 Narrow->getOpcode() != ISD::OR)
22455 SDValue N0 = Narrow->getOperand(0);
22456 SDValue N1 = Narrow->getOperand(1);
22459 // The Left side has to be a trunc.
22460 if (N0.getOpcode() != ISD::TRUNCATE)
22463 // The type of the truncated inputs.
22464 EVT WideVT = N0->getOperand(0)->getValueType(0);
22468 // The right side has to be a 'trunc' or a constant vector.
22469 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22470 ConstantSDNode *RHSConstSplat = nullptr;
22471 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22472 RHSConstSplat = RHSBV->getConstantSplatNode();
22473 if (!RHSTrunc && !RHSConstSplat)
22476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22478 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22481 // Set N0 and N1 to hold the inputs to the new wide operation.
22482 N0 = N0->getOperand(0);
22483 if (RHSConstSplat) {
22484 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22485 SDValue(RHSConstSplat, 0));
22486 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22487 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22488 } else if (RHSTrunc) {
22489 N1 = N1->getOperand(0);
22492 // Generate the wide operation.
22493 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22494 unsigned Opcode = N->getOpcode();
22496 case ISD::ANY_EXTEND:
22498 case ISD::ZERO_EXTEND: {
22499 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22500 APInt Mask = APInt::getAllOnesValue(InBits);
22501 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22502 return DAG.getNode(ISD::AND, DL, VT,
22503 Op, DAG.getConstant(Mask, VT));
22505 case ISD::SIGN_EXTEND:
22506 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22507 Op, DAG.getValueType(NarrowVT));
22509 llvm_unreachable("Unexpected opcode");
22513 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22514 TargetLowering::DAGCombinerInfo &DCI,
22515 const X86Subtarget *Subtarget) {
22516 EVT VT = N->getValueType(0);
22517 if (DCI.isBeforeLegalizeOps())
22520 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22524 // Create BEXTR instructions
22525 // BEXTR is ((X >> imm) & (2**size-1))
22526 if (VT == MVT::i32 || VT == MVT::i64) {
22527 SDValue N0 = N->getOperand(0);
22528 SDValue N1 = N->getOperand(1);
22531 // Check for BEXTR.
22532 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22533 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22534 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22535 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22536 if (MaskNode && ShiftNode) {
22537 uint64_t Mask = MaskNode->getZExtValue();
22538 uint64_t Shift = ShiftNode->getZExtValue();
22539 if (isMask_64(Mask)) {
22540 uint64_t MaskSize = CountPopulation_64(Mask);
22541 if (Shift + MaskSize <= VT.getSizeInBits())
22542 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22543 DAG.getConstant(Shift | (MaskSize << 8), VT));
22551 // Want to form ANDNP nodes:
22552 // 1) In the hopes of then easily combining them with OR and AND nodes
22553 // to form PBLEND/PSIGN.
22554 // 2) To match ANDN packed intrinsics
22555 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22558 SDValue N0 = N->getOperand(0);
22559 SDValue N1 = N->getOperand(1);
22562 // Check LHS for vnot
22563 if (N0.getOpcode() == ISD::XOR &&
22564 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22565 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22566 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22568 // Check RHS for vnot
22569 if (N1.getOpcode() == ISD::XOR &&
22570 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22571 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22572 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22577 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22578 TargetLowering::DAGCombinerInfo &DCI,
22579 const X86Subtarget *Subtarget) {
22580 if (DCI.isBeforeLegalizeOps())
22583 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22587 SDValue N0 = N->getOperand(0);
22588 SDValue N1 = N->getOperand(1);
22589 EVT VT = N->getValueType(0);
22591 // look for psign/blend
22592 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22593 if (!Subtarget->hasSSSE3() ||
22594 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22597 // Canonicalize pandn to RHS
22598 if (N0.getOpcode() == X86ISD::ANDNP)
22600 // or (and (m, y), (pandn m, x))
22601 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22602 SDValue Mask = N1.getOperand(0);
22603 SDValue X = N1.getOperand(1);
22605 if (N0.getOperand(0) == Mask)
22606 Y = N0.getOperand(1);
22607 if (N0.getOperand(1) == Mask)
22608 Y = N0.getOperand(0);
22610 // Check to see if the mask appeared in both the AND and ANDNP and
22614 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22615 // Look through mask bitcast.
22616 if (Mask.getOpcode() == ISD::BITCAST)
22617 Mask = Mask.getOperand(0);
22618 if (X.getOpcode() == ISD::BITCAST)
22619 X = X.getOperand(0);
22620 if (Y.getOpcode() == ISD::BITCAST)
22621 Y = Y.getOperand(0);
22623 EVT MaskVT = Mask.getValueType();
22625 // Validate that the Mask operand is a vector sra node.
22626 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22627 // there is no psrai.b
22628 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22629 unsigned SraAmt = ~0;
22630 if (Mask.getOpcode() == ISD::SRA) {
22631 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22632 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22633 SraAmt = AmtConst->getZExtValue();
22634 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22635 SDValue SraC = Mask.getOperand(1);
22636 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22638 if ((SraAmt + 1) != EltBits)
22643 // Now we know we at least have a plendvb with the mask val. See if
22644 // we can form a psignb/w/d.
22645 // psign = x.type == y.type == mask.type && y = sub(0, x);
22646 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22647 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22648 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22649 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22650 "Unsupported VT for PSIGN");
22651 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22652 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22654 // PBLENDVB only available on SSE 4.1
22655 if (!Subtarget->hasSSE41())
22658 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22660 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22661 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22662 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22663 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22664 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22668 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22671 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22672 MachineFunction &MF = DAG.getMachineFunction();
22673 bool OptForSize = MF.getFunction()->getAttributes().
22674 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22676 // SHLD/SHRD instructions have lower register pressure, but on some
22677 // platforms they have higher latency than the equivalent
22678 // series of shifts/or that would otherwise be generated.
22679 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22680 // have higher latencies and we are not optimizing for size.
22681 if (!OptForSize && Subtarget->isSHLDSlow())
22684 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22686 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22688 if (!N0.hasOneUse() || !N1.hasOneUse())
22691 SDValue ShAmt0 = N0.getOperand(1);
22692 if (ShAmt0.getValueType() != MVT::i8)
22694 SDValue ShAmt1 = N1.getOperand(1);
22695 if (ShAmt1.getValueType() != MVT::i8)
22697 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22698 ShAmt0 = ShAmt0.getOperand(0);
22699 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22700 ShAmt1 = ShAmt1.getOperand(0);
22703 unsigned Opc = X86ISD::SHLD;
22704 SDValue Op0 = N0.getOperand(0);
22705 SDValue Op1 = N1.getOperand(0);
22706 if (ShAmt0.getOpcode() == ISD::SUB) {
22707 Opc = X86ISD::SHRD;
22708 std::swap(Op0, Op1);
22709 std::swap(ShAmt0, ShAmt1);
22712 unsigned Bits = VT.getSizeInBits();
22713 if (ShAmt1.getOpcode() == ISD::SUB) {
22714 SDValue Sum = ShAmt1.getOperand(0);
22715 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22716 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22717 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22718 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22719 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22720 return DAG.getNode(Opc, DL, VT,
22722 DAG.getNode(ISD::TRUNCATE, DL,
22725 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22726 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22728 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22729 return DAG.getNode(Opc, DL, VT,
22730 N0.getOperand(0), N1.getOperand(0),
22731 DAG.getNode(ISD::TRUNCATE, DL,
22738 // Generate NEG and CMOV for integer abs.
22739 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22740 EVT VT = N->getValueType(0);
22742 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22743 // 8-bit integer abs to NEG and CMOV.
22744 if (VT.isInteger() && VT.getSizeInBits() == 8)
22747 SDValue N0 = N->getOperand(0);
22748 SDValue N1 = N->getOperand(1);
22751 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22752 // and change it to SUB and CMOV.
22753 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22754 N0.getOpcode() == ISD::ADD &&
22755 N0.getOperand(1) == N1 &&
22756 N1.getOpcode() == ISD::SRA &&
22757 N1.getOperand(0) == N0.getOperand(0))
22758 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22759 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22760 // Generate SUB & CMOV.
22761 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22762 DAG.getConstant(0, VT), N0.getOperand(0));
22764 SDValue Ops[] = { N0.getOperand(0), Neg,
22765 DAG.getConstant(X86::COND_GE, MVT::i8),
22766 SDValue(Neg.getNode(), 1) };
22767 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22772 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22773 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22774 TargetLowering::DAGCombinerInfo &DCI,
22775 const X86Subtarget *Subtarget) {
22776 if (DCI.isBeforeLegalizeOps())
22779 if (Subtarget->hasCMov()) {
22780 SDValue RV = performIntegerAbsCombine(N, DAG);
22788 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22789 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22790 TargetLowering::DAGCombinerInfo &DCI,
22791 const X86Subtarget *Subtarget) {
22792 LoadSDNode *Ld = cast<LoadSDNode>(N);
22793 EVT RegVT = Ld->getValueType(0);
22794 EVT MemVT = Ld->getMemoryVT();
22796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22798 // On Sandybridge unaligned 256bit loads are inefficient.
22799 ISD::LoadExtType Ext = Ld->getExtensionType();
22800 unsigned Alignment = Ld->getAlignment();
22801 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22802 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22803 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22804 unsigned NumElems = RegVT.getVectorNumElements();
22808 SDValue Ptr = Ld->getBasePtr();
22809 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22811 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22813 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22814 Ld->getPointerInfo(), Ld->isVolatile(),
22815 Ld->isNonTemporal(), Ld->isInvariant(),
22817 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22818 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22819 Ld->getPointerInfo(), Ld->isVolatile(),
22820 Ld->isNonTemporal(), Ld->isInvariant(),
22821 std::min(16U, Alignment));
22822 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22824 Load2.getValue(1));
22826 SDValue NewVec = DAG.getUNDEF(RegVT);
22827 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22828 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22829 return DCI.CombineTo(N, NewVec, TF, true);
22835 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22836 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22837 const X86Subtarget *Subtarget) {
22838 StoreSDNode *St = cast<StoreSDNode>(N);
22839 EVT VT = St->getValue().getValueType();
22840 EVT StVT = St->getMemoryVT();
22842 SDValue StoredVal = St->getOperand(1);
22843 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22845 // If we are saving a concatenation of two XMM registers, perform two stores.
22846 // On Sandy Bridge, 256-bit memory operations are executed by two
22847 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22848 // memory operation.
22849 unsigned Alignment = St->getAlignment();
22850 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22851 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22852 StVT == VT && !IsAligned) {
22853 unsigned NumElems = VT.getVectorNumElements();
22857 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22858 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22860 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22861 SDValue Ptr0 = St->getBasePtr();
22862 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22864 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22865 St->getPointerInfo(), St->isVolatile(),
22866 St->isNonTemporal(), Alignment);
22867 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22868 St->getPointerInfo(), St->isVolatile(),
22869 St->isNonTemporal(),
22870 std::min(16U, Alignment));
22871 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22874 // Optimize trunc store (of multiple scalars) to shuffle and store.
22875 // First, pack all of the elements in one place. Next, store to memory
22876 // in fewer chunks.
22877 if (St->isTruncatingStore() && VT.isVector()) {
22878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22879 unsigned NumElems = VT.getVectorNumElements();
22880 assert(StVT != VT && "Cannot truncate to the same type");
22881 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22882 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22884 // From, To sizes and ElemCount must be pow of two
22885 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22886 // We are going to use the original vector elt for storing.
22887 // Accumulated smaller vector elements must be a multiple of the store size.
22888 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22890 unsigned SizeRatio = FromSz / ToSz;
22892 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22894 // Create a type on which we perform the shuffle
22895 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22896 StVT.getScalarType(), NumElems*SizeRatio);
22898 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22900 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22901 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22902 for (unsigned i = 0; i != NumElems; ++i)
22903 ShuffleVec[i] = i * SizeRatio;
22905 // Can't shuffle using an illegal type.
22906 if (!TLI.isTypeLegal(WideVecVT))
22909 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22910 DAG.getUNDEF(WideVecVT),
22912 // At this point all of the data is stored at the bottom of the
22913 // register. We now need to save it to mem.
22915 // Find the largest store unit
22916 MVT StoreType = MVT::i8;
22917 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22918 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22919 MVT Tp = (MVT::SimpleValueType)tp;
22920 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22924 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22925 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22926 (64 <= NumElems * ToSz))
22927 StoreType = MVT::f64;
22929 // Bitcast the original vector into a vector of store-size units
22930 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22931 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22932 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22933 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22934 SmallVector<SDValue, 8> Chains;
22935 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22936 TLI.getPointerTy());
22937 SDValue Ptr = St->getBasePtr();
22939 // Perform one or more big stores into memory.
22940 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22941 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22942 StoreType, ShuffWide,
22943 DAG.getIntPtrConstant(i));
22944 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22945 St->getPointerInfo(), St->isVolatile(),
22946 St->isNonTemporal(), St->getAlignment());
22947 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22948 Chains.push_back(Ch);
22951 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22954 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22955 // the FP state in cases where an emms may be missing.
22956 // A preferable solution to the general problem is to figure out the right
22957 // places to insert EMMS. This qualifies as a quick hack.
22959 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22960 if (VT.getSizeInBits() != 64)
22963 const Function *F = DAG.getMachineFunction().getFunction();
22964 bool NoImplicitFloatOps = F->getAttributes().
22965 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22966 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22967 && Subtarget->hasSSE2();
22968 if ((VT.isVector() ||
22969 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22970 isa<LoadSDNode>(St->getValue()) &&
22971 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22972 St->getChain().hasOneUse() && !St->isVolatile()) {
22973 SDNode* LdVal = St->getValue().getNode();
22974 LoadSDNode *Ld = nullptr;
22975 int TokenFactorIndex = -1;
22976 SmallVector<SDValue, 8> Ops;
22977 SDNode* ChainVal = St->getChain().getNode();
22978 // Must be a store of a load. We currently handle two cases: the load
22979 // is a direct child, and it's under an intervening TokenFactor. It is
22980 // possible to dig deeper under nested TokenFactors.
22981 if (ChainVal == LdVal)
22982 Ld = cast<LoadSDNode>(St->getChain());
22983 else if (St->getValue().hasOneUse() &&
22984 ChainVal->getOpcode() == ISD::TokenFactor) {
22985 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22986 if (ChainVal->getOperand(i).getNode() == LdVal) {
22987 TokenFactorIndex = i;
22988 Ld = cast<LoadSDNode>(St->getValue());
22990 Ops.push_back(ChainVal->getOperand(i));
22994 if (!Ld || !ISD::isNormalLoad(Ld))
22997 // If this is not the MMX case, i.e. we are just turning i64 load/store
22998 // into f64 load/store, avoid the transformation if there are multiple
22999 // uses of the loaded value.
23000 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23005 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23006 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23008 if (Subtarget->is64Bit() || F64IsLegal) {
23009 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23010 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23011 Ld->getPointerInfo(), Ld->isVolatile(),
23012 Ld->isNonTemporal(), Ld->isInvariant(),
23013 Ld->getAlignment());
23014 SDValue NewChain = NewLd.getValue(1);
23015 if (TokenFactorIndex != -1) {
23016 Ops.push_back(NewChain);
23017 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23019 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23020 St->getPointerInfo(),
23021 St->isVolatile(), St->isNonTemporal(),
23022 St->getAlignment());
23025 // Otherwise, lower to two pairs of 32-bit loads / stores.
23026 SDValue LoAddr = Ld->getBasePtr();
23027 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23028 DAG.getConstant(4, MVT::i32));
23030 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23031 Ld->getPointerInfo(),
23032 Ld->isVolatile(), Ld->isNonTemporal(),
23033 Ld->isInvariant(), Ld->getAlignment());
23034 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23035 Ld->getPointerInfo().getWithOffset(4),
23036 Ld->isVolatile(), Ld->isNonTemporal(),
23038 MinAlign(Ld->getAlignment(), 4));
23040 SDValue NewChain = LoLd.getValue(1);
23041 if (TokenFactorIndex != -1) {
23042 Ops.push_back(LoLd);
23043 Ops.push_back(HiLd);
23044 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23047 LoAddr = St->getBasePtr();
23048 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23049 DAG.getConstant(4, MVT::i32));
23051 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23052 St->getPointerInfo(),
23053 St->isVolatile(), St->isNonTemporal(),
23054 St->getAlignment());
23055 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23056 St->getPointerInfo().getWithOffset(4),
23058 St->isNonTemporal(),
23059 MinAlign(St->getAlignment(), 4));
23060 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23065 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23066 /// and return the operands for the horizontal operation in LHS and RHS. A
23067 /// horizontal operation performs the binary operation on successive elements
23068 /// of its first operand, then on successive elements of its second operand,
23069 /// returning the resulting values in a vector. For example, if
23070 /// A = < float a0, float a1, float a2, float a3 >
23072 /// B = < float b0, float b1, float b2, float b3 >
23073 /// then the result of doing a horizontal operation on A and B is
23074 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23075 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23076 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23077 /// set to A, RHS to B, and the routine returns 'true'.
23078 /// Note that the binary operation should have the property that if one of the
23079 /// operands is UNDEF then the result is UNDEF.
23080 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23081 // Look for the following pattern: if
23082 // A = < float a0, float a1, float a2, float a3 >
23083 // B = < float b0, float b1, float b2, float b3 >
23085 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23086 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23087 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23088 // which is A horizontal-op B.
23090 // At least one of the operands should be a vector shuffle.
23091 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23092 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23095 MVT VT = LHS.getSimpleValueType();
23097 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23098 "Unsupported vector type for horizontal add/sub");
23100 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23101 // operate independently on 128-bit lanes.
23102 unsigned NumElts = VT.getVectorNumElements();
23103 unsigned NumLanes = VT.getSizeInBits()/128;
23104 unsigned NumLaneElts = NumElts / NumLanes;
23105 assert((NumLaneElts % 2 == 0) &&
23106 "Vector type should have an even number of elements in each lane");
23107 unsigned HalfLaneElts = NumLaneElts/2;
23109 // View LHS in the form
23110 // LHS = VECTOR_SHUFFLE A, B, LMask
23111 // If LHS is not a shuffle then pretend it is the shuffle
23112 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23113 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23116 SmallVector<int, 16> LMask(NumElts);
23117 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23118 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23119 A = LHS.getOperand(0);
23120 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23121 B = LHS.getOperand(1);
23122 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23123 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23125 if (LHS.getOpcode() != ISD::UNDEF)
23127 for (unsigned i = 0; i != NumElts; ++i)
23131 // Likewise, view RHS in the form
23132 // RHS = VECTOR_SHUFFLE C, D, RMask
23134 SmallVector<int, 16> RMask(NumElts);
23135 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23136 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23137 C = RHS.getOperand(0);
23138 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23139 D = RHS.getOperand(1);
23140 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23141 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23143 if (RHS.getOpcode() != ISD::UNDEF)
23145 for (unsigned i = 0; i != NumElts; ++i)
23149 // Check that the shuffles are both shuffling the same vectors.
23150 if (!(A == C && B == D) && !(A == D && B == C))
23153 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23154 if (!A.getNode() && !B.getNode())
23157 // If A and B occur in reverse order in RHS, then "swap" them (which means
23158 // rewriting the mask).
23160 CommuteVectorShuffleMask(RMask, NumElts);
23162 // At this point LHS and RHS are equivalent to
23163 // LHS = VECTOR_SHUFFLE A, B, LMask
23164 // RHS = VECTOR_SHUFFLE A, B, RMask
23165 // Check that the masks correspond to performing a horizontal operation.
23166 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23167 for (unsigned i = 0; i != NumLaneElts; ++i) {
23168 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23170 // Ignore any UNDEF components.
23171 if (LIdx < 0 || RIdx < 0 ||
23172 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23173 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23176 // Check that successive elements are being operated on. If not, this is
23177 // not a horizontal operation.
23178 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23179 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23180 if (!(LIdx == Index && RIdx == Index + 1) &&
23181 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23186 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23187 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23191 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23192 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23193 const X86Subtarget *Subtarget) {
23194 EVT VT = N->getValueType(0);
23195 SDValue LHS = N->getOperand(0);
23196 SDValue RHS = N->getOperand(1);
23198 // Try to synthesize horizontal adds from adds of shuffles.
23199 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23200 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23201 isHorizontalBinOp(LHS, RHS, true))
23202 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23206 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23207 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23208 const X86Subtarget *Subtarget) {
23209 EVT VT = N->getValueType(0);
23210 SDValue LHS = N->getOperand(0);
23211 SDValue RHS = N->getOperand(1);
23213 // Try to synthesize horizontal subs from subs of shuffles.
23214 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23215 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23216 isHorizontalBinOp(LHS, RHS, false))
23217 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23221 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23222 /// X86ISD::FXOR nodes.
23223 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23224 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23225 // F[X]OR(0.0, x) -> x
23226 // F[X]OR(x, 0.0) -> x
23227 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23228 if (C->getValueAPF().isPosZero())
23229 return N->getOperand(1);
23230 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23231 if (C->getValueAPF().isPosZero())
23232 return N->getOperand(0);
23236 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23237 /// X86ISD::FMAX nodes.
23238 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23239 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23241 // Only perform optimizations if UnsafeMath is used.
23242 if (!DAG.getTarget().Options.UnsafeFPMath)
23245 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23246 // into FMINC and FMAXC, which are Commutative operations.
23247 unsigned NewOp = 0;
23248 switch (N->getOpcode()) {
23249 default: llvm_unreachable("unknown opcode");
23250 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23251 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23254 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23255 N->getOperand(0), N->getOperand(1));
23258 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23259 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23260 // FAND(0.0, x) -> 0.0
23261 // FAND(x, 0.0) -> 0.0
23262 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23263 if (C->getValueAPF().isPosZero())
23264 return N->getOperand(0);
23265 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23266 if (C->getValueAPF().isPosZero())
23267 return N->getOperand(1);
23271 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23272 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23273 // FANDN(x, 0.0) -> 0.0
23274 // FANDN(0.0, x) -> x
23275 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23276 if (C->getValueAPF().isPosZero())
23277 return N->getOperand(1);
23278 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23279 if (C->getValueAPF().isPosZero())
23280 return N->getOperand(1);
23284 static SDValue PerformBTCombine(SDNode *N,
23286 TargetLowering::DAGCombinerInfo &DCI) {
23287 // BT ignores high bits in the bit index operand.
23288 SDValue Op1 = N->getOperand(1);
23289 if (Op1.hasOneUse()) {
23290 unsigned BitWidth = Op1.getValueSizeInBits();
23291 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23292 APInt KnownZero, KnownOne;
23293 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23294 !DCI.isBeforeLegalizeOps());
23295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23296 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23297 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23298 DCI.CommitTargetLoweringOpt(TLO);
23303 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23304 SDValue Op = N->getOperand(0);
23305 if (Op.getOpcode() == ISD::BITCAST)
23306 Op = Op.getOperand(0);
23307 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23308 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23309 VT.getVectorElementType().getSizeInBits() ==
23310 OpVT.getVectorElementType().getSizeInBits()) {
23311 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23316 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23317 const X86Subtarget *Subtarget) {
23318 EVT VT = N->getValueType(0);
23319 if (!VT.isVector())
23322 SDValue N0 = N->getOperand(0);
23323 SDValue N1 = N->getOperand(1);
23324 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23327 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23328 // both SSE and AVX2 since there is no sign-extended shift right
23329 // operation on a vector with 64-bit elements.
23330 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23331 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23332 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23333 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23334 SDValue N00 = N0.getOperand(0);
23336 // EXTLOAD has a better solution on AVX2,
23337 // it may be replaced with X86ISD::VSEXT node.
23338 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23339 if (!ISD::isNormalLoad(N00.getNode()))
23342 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23343 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23345 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23351 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23352 TargetLowering::DAGCombinerInfo &DCI,
23353 const X86Subtarget *Subtarget) {
23354 if (!DCI.isBeforeLegalizeOps())
23357 if (!Subtarget->hasFp256())
23360 EVT VT = N->getValueType(0);
23361 if (VT.isVector() && VT.getSizeInBits() == 256) {
23362 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23370 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23371 const X86Subtarget* Subtarget) {
23373 EVT VT = N->getValueType(0);
23375 // Let legalize expand this if it isn't a legal type yet.
23376 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23379 EVT ScalarVT = VT.getScalarType();
23380 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23381 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23384 SDValue A = N->getOperand(0);
23385 SDValue B = N->getOperand(1);
23386 SDValue C = N->getOperand(2);
23388 bool NegA = (A.getOpcode() == ISD::FNEG);
23389 bool NegB = (B.getOpcode() == ISD::FNEG);
23390 bool NegC = (C.getOpcode() == ISD::FNEG);
23392 // Negative multiplication when NegA xor NegB
23393 bool NegMul = (NegA != NegB);
23395 A = A.getOperand(0);
23397 B = B.getOperand(0);
23399 C = C.getOperand(0);
23403 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23405 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23407 return DAG.getNode(Opcode, dl, VT, A, B, C);
23410 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23411 TargetLowering::DAGCombinerInfo &DCI,
23412 const X86Subtarget *Subtarget) {
23413 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23414 // (and (i32 x86isd::setcc_carry), 1)
23415 // This eliminates the zext. This transformation is necessary because
23416 // ISD::SETCC is always legalized to i8.
23418 SDValue N0 = N->getOperand(0);
23419 EVT VT = N->getValueType(0);
23421 if (N0.getOpcode() == ISD::AND &&
23423 N0.getOperand(0).hasOneUse()) {
23424 SDValue N00 = N0.getOperand(0);
23425 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23427 if (!C || C->getZExtValue() != 1)
23429 return DAG.getNode(ISD::AND, dl, VT,
23430 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23431 N00.getOperand(0), N00.getOperand(1)),
23432 DAG.getConstant(1, VT));
23436 if (N0.getOpcode() == ISD::TRUNCATE &&
23438 N0.getOperand(0).hasOneUse()) {
23439 SDValue N00 = N0.getOperand(0);
23440 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23441 return DAG.getNode(ISD::AND, dl, VT,
23442 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23443 N00.getOperand(0), N00.getOperand(1)),
23444 DAG.getConstant(1, VT));
23447 if (VT.is256BitVector()) {
23448 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23456 // Optimize x == -y --> x+y == 0
23457 // x != -y --> x+y != 0
23458 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23459 const X86Subtarget* Subtarget) {
23460 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23461 SDValue LHS = N->getOperand(0);
23462 SDValue RHS = N->getOperand(1);
23463 EVT VT = N->getValueType(0);
23466 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23468 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23469 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23470 LHS.getValueType(), RHS, LHS.getOperand(1));
23471 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23472 addV, DAG.getConstant(0, addV.getValueType()), CC);
23474 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23476 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23477 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23478 RHS.getValueType(), LHS, RHS.getOperand(1));
23479 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23480 addV, DAG.getConstant(0, addV.getValueType()), CC);
23483 if (VT.getScalarType() == MVT::i1) {
23484 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23485 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23486 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23487 if (!IsSEXT0 && !IsVZero0)
23489 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23490 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23491 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23493 if (!IsSEXT1 && !IsVZero1)
23496 if (IsSEXT0 && IsVZero1) {
23497 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23498 if (CC == ISD::SETEQ)
23499 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23500 return LHS.getOperand(0);
23502 if (IsSEXT1 && IsVZero0) {
23503 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23504 if (CC == ISD::SETEQ)
23505 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23506 return RHS.getOperand(0);
23513 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23514 const X86Subtarget *Subtarget) {
23516 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23517 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23518 "X86insertps is only defined for v4x32");
23520 SDValue Ld = N->getOperand(1);
23521 if (MayFoldLoad(Ld)) {
23522 // Extract the countS bits from the immediate so we can get the proper
23523 // address when narrowing the vector load to a specific element.
23524 // When the second source op is a memory address, interps doesn't use
23525 // countS and just gets an f32 from that address.
23526 unsigned DestIndex =
23527 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23528 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23532 // Create this as a scalar to vector to match the instruction pattern.
23533 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23534 // countS bits are ignored when loading from memory on insertps, which
23535 // means we don't need to explicitly set them to 0.
23536 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23537 LoadScalarToVector, N->getOperand(2));
23540 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23541 // as "sbb reg,reg", since it can be extended without zext and produces
23542 // an all-ones bit which is more useful than 0/1 in some cases.
23543 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23546 return DAG.getNode(ISD::AND, DL, VT,
23547 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23548 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23549 DAG.getConstant(1, VT));
23550 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23551 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23552 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23553 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23556 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23557 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23558 TargetLowering::DAGCombinerInfo &DCI,
23559 const X86Subtarget *Subtarget) {
23561 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23562 SDValue EFLAGS = N->getOperand(1);
23564 if (CC == X86::COND_A) {
23565 // Try to convert COND_A into COND_B in an attempt to facilitate
23566 // materializing "setb reg".
23568 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23569 // cannot take an immediate as its first operand.
23571 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23572 EFLAGS.getValueType().isInteger() &&
23573 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23574 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23575 EFLAGS.getNode()->getVTList(),
23576 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23577 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23578 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23582 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23583 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23585 if (CC == X86::COND_B)
23586 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23590 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23591 if (Flags.getNode()) {
23592 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23593 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23599 // Optimize branch condition evaluation.
23601 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23602 TargetLowering::DAGCombinerInfo &DCI,
23603 const X86Subtarget *Subtarget) {
23605 SDValue Chain = N->getOperand(0);
23606 SDValue Dest = N->getOperand(1);
23607 SDValue EFLAGS = N->getOperand(3);
23608 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23612 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23613 if (Flags.getNode()) {
23614 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23615 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23622 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23623 SelectionDAG &DAG) {
23624 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23625 // optimize away operation when it's from a constant.
23627 // The general transformation is:
23628 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23629 // AND(VECTOR_CMP(x,y), constant2)
23630 // constant2 = UNARYOP(constant)
23632 // Early exit if this isn't a vector operation, the operand of the
23633 // unary operation isn't a bitwise AND, or if the sizes of the operations
23634 // aren't the same.
23635 EVT VT = N->getValueType(0);
23636 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23637 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23638 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23641 // Now check that the other operand of the AND is a constant. We could
23642 // make the transformation for non-constant splats as well, but it's unclear
23643 // that would be a benefit as it would not eliminate any operations, just
23644 // perform one more step in scalar code before moving to the vector unit.
23645 if (BuildVectorSDNode *BV =
23646 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23647 // Bail out if the vector isn't a constant.
23648 if (!BV->isConstant())
23651 // Everything checks out. Build up the new and improved node.
23653 EVT IntVT = BV->getValueType(0);
23654 // Create a new constant of the appropriate type for the transformed
23656 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23657 // The AND node needs bitcasts to/from an integer vector type around it.
23658 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23659 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23660 N->getOperand(0)->getOperand(0), MaskConst);
23661 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23668 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23669 const X86TargetLowering *XTLI) {
23670 // First try to optimize away the conversion entirely when it's
23671 // conditionally from a constant. Vectors only.
23672 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23673 if (Res != SDValue())
23676 // Now move on to more general possibilities.
23677 SDValue Op0 = N->getOperand(0);
23678 EVT InVT = Op0->getValueType(0);
23680 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23681 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23683 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23684 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23685 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23688 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23689 // a 32-bit target where SSE doesn't support i64->FP operations.
23690 if (Op0.getOpcode() == ISD::LOAD) {
23691 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23692 EVT VT = Ld->getValueType(0);
23693 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23694 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23695 !XTLI->getSubtarget()->is64Bit() &&
23697 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23698 Ld->getChain(), Op0, DAG);
23699 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23706 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23707 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23708 X86TargetLowering::DAGCombinerInfo &DCI) {
23709 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23710 // the result is either zero or one (depending on the input carry bit).
23711 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23712 if (X86::isZeroNode(N->getOperand(0)) &&
23713 X86::isZeroNode(N->getOperand(1)) &&
23714 // We don't have a good way to replace an EFLAGS use, so only do this when
23716 SDValue(N, 1).use_empty()) {
23718 EVT VT = N->getValueType(0);
23719 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23720 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23721 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23722 DAG.getConstant(X86::COND_B,MVT::i8),
23724 DAG.getConstant(1, VT));
23725 return DCI.CombineTo(N, Res1, CarryOut);
23731 // fold (add Y, (sete X, 0)) -> adc 0, Y
23732 // (add Y, (setne X, 0)) -> sbb -1, Y
23733 // (sub (sete X, 0), Y) -> sbb 0, Y
23734 // (sub (setne X, 0), Y) -> adc -1, Y
23735 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23738 // Look through ZExts.
23739 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23740 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23743 SDValue SetCC = Ext.getOperand(0);
23744 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23747 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23748 if (CC != X86::COND_E && CC != X86::COND_NE)
23751 SDValue Cmp = SetCC.getOperand(1);
23752 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23753 !X86::isZeroNode(Cmp.getOperand(1)) ||
23754 !Cmp.getOperand(0).getValueType().isInteger())
23757 SDValue CmpOp0 = Cmp.getOperand(0);
23758 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23759 DAG.getConstant(1, CmpOp0.getValueType()));
23761 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23762 if (CC == X86::COND_NE)
23763 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23764 DL, OtherVal.getValueType(), OtherVal,
23765 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23766 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23767 DL, OtherVal.getValueType(), OtherVal,
23768 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23771 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23772 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23773 const X86Subtarget *Subtarget) {
23774 EVT VT = N->getValueType(0);
23775 SDValue Op0 = N->getOperand(0);
23776 SDValue Op1 = N->getOperand(1);
23778 // Try to synthesize horizontal adds from adds of shuffles.
23779 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23780 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23781 isHorizontalBinOp(Op0, Op1, true))
23782 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23784 return OptimizeConditionalInDecrement(N, DAG);
23787 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23788 const X86Subtarget *Subtarget) {
23789 SDValue Op0 = N->getOperand(0);
23790 SDValue Op1 = N->getOperand(1);
23792 // X86 can't encode an immediate LHS of a sub. See if we can push the
23793 // negation into a preceding instruction.
23794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23795 // If the RHS of the sub is a XOR with one use and a constant, invert the
23796 // immediate. Then add one to the LHS of the sub so we can turn
23797 // X-Y -> X+~Y+1, saving one register.
23798 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23799 isa<ConstantSDNode>(Op1.getOperand(1))) {
23800 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23801 EVT VT = Op0.getValueType();
23802 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23804 DAG.getConstant(~XorC, VT));
23805 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23806 DAG.getConstant(C->getAPIntValue()+1, VT));
23810 // Try to synthesize horizontal adds from adds of shuffles.
23811 EVT VT = N->getValueType(0);
23812 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23813 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23814 isHorizontalBinOp(Op0, Op1, true))
23815 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23817 return OptimizeConditionalInDecrement(N, DAG);
23820 /// performVZEXTCombine - Performs build vector combines
23821 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23822 TargetLowering::DAGCombinerInfo &DCI,
23823 const X86Subtarget *Subtarget) {
23824 // (vzext (bitcast (vzext (x)) -> (vzext x)
23825 SDValue In = N->getOperand(0);
23826 while (In.getOpcode() == ISD::BITCAST)
23827 In = In.getOperand(0);
23829 if (In.getOpcode() != X86ISD::VZEXT)
23832 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23836 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23837 DAGCombinerInfo &DCI) const {
23838 SelectionDAG &DAG = DCI.DAG;
23839 switch (N->getOpcode()) {
23841 case ISD::EXTRACT_VECTOR_ELT:
23842 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23844 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23845 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23846 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23847 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23848 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23849 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23852 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23853 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23854 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23855 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23856 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23857 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23858 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23859 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23860 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23862 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23864 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23865 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23866 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23867 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23868 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23869 case ISD::ANY_EXTEND:
23870 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23871 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23872 case ISD::SIGN_EXTEND_INREG:
23873 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23874 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23875 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23876 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23877 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23878 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23879 case X86ISD::SHUFP: // Handle all target specific shuffles
23880 case X86ISD::PALIGNR:
23881 case X86ISD::UNPCKH:
23882 case X86ISD::UNPCKL:
23883 case X86ISD::MOVHLPS:
23884 case X86ISD::MOVLHPS:
23885 case X86ISD::PSHUFB:
23886 case X86ISD::PSHUFD:
23887 case X86ISD::PSHUFHW:
23888 case X86ISD::PSHUFLW:
23889 case X86ISD::MOVSS:
23890 case X86ISD::MOVSD:
23891 case X86ISD::VPERMILPI:
23892 case X86ISD::VPERM2X128:
23893 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23894 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23895 case ISD::INTRINSIC_WO_CHAIN:
23896 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23897 case X86ISD::INSERTPS:
23898 return PerformINSERTPSCombine(N, DAG, Subtarget);
23899 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23905 /// isTypeDesirableForOp - Return true if the target has native support for
23906 /// the specified value type and it is 'desirable' to use the type for the
23907 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23908 /// instruction encodings are longer and some i16 instructions are slow.
23909 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23910 if (!isTypeLegal(VT))
23912 if (VT != MVT::i16)
23919 case ISD::SIGN_EXTEND:
23920 case ISD::ZERO_EXTEND:
23921 case ISD::ANY_EXTEND:
23934 /// IsDesirableToPromoteOp - This method query the target whether it is
23935 /// beneficial for dag combiner to promote the specified node. If true, it
23936 /// should return the desired promotion type by reference.
23937 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23938 EVT VT = Op.getValueType();
23939 if (VT != MVT::i16)
23942 bool Promote = false;
23943 bool Commute = false;
23944 switch (Op.getOpcode()) {
23947 LoadSDNode *LD = cast<LoadSDNode>(Op);
23948 // If the non-extending load has a single use and it's not live out, then it
23949 // might be folded.
23950 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23951 Op.hasOneUse()*/) {
23952 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23953 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23954 // The only case where we'd want to promote LOAD (rather then it being
23955 // promoted as an operand is when it's only use is liveout.
23956 if (UI->getOpcode() != ISD::CopyToReg)
23963 case ISD::SIGN_EXTEND:
23964 case ISD::ZERO_EXTEND:
23965 case ISD::ANY_EXTEND:
23970 SDValue N0 = Op.getOperand(0);
23971 // Look out for (store (shl (load), x)).
23972 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23985 SDValue N0 = Op.getOperand(0);
23986 SDValue N1 = Op.getOperand(1);
23987 if (!Commute && MayFoldLoad(N1))
23989 // Avoid disabling potential load folding opportunities.
23990 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23992 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24002 //===----------------------------------------------------------------------===//
24003 // X86 Inline Assembly Support
24004 //===----------------------------------------------------------------------===//
24007 // Helper to match a string separated by whitespace.
24008 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24009 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24011 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24012 StringRef piece(*args[i]);
24013 if (!s.startswith(piece)) // Check if the piece matches.
24016 s = s.substr(piece.size());
24017 StringRef::size_type pos = s.find_first_not_of(" \t");
24018 if (pos == 0) // We matched a prefix.
24026 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24029 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24031 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24032 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24033 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24034 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24036 if (AsmPieces.size() == 3)
24038 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24045 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24046 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24048 std::string AsmStr = IA->getAsmString();
24050 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24051 if (!Ty || Ty->getBitWidth() % 16 != 0)
24054 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24055 SmallVector<StringRef, 4> AsmPieces;
24056 SplitString(AsmStr, AsmPieces, ";\n");
24058 switch (AsmPieces.size()) {
24059 default: return false;
24061 // FIXME: this should verify that we are targeting a 486 or better. If not,
24062 // we will turn this bswap into something that will be lowered to logical
24063 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24064 // lower so don't worry about this.
24066 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24067 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24068 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24069 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24070 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24071 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24072 // No need to check constraints, nothing other than the equivalent of
24073 // "=r,0" would be valid here.
24074 return IntrinsicLowering::LowerToByteSwap(CI);
24077 // rorw $$8, ${0:w} --> llvm.bswap.i16
24078 if (CI->getType()->isIntegerTy(16) &&
24079 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24080 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24081 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24083 const std::string &ConstraintsStr = IA->getConstraintString();
24084 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24085 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24086 if (clobbersFlagRegisters(AsmPieces))
24087 return IntrinsicLowering::LowerToByteSwap(CI);
24091 if (CI->getType()->isIntegerTy(32) &&
24092 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24093 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24094 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24095 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24097 const std::string &ConstraintsStr = IA->getConstraintString();
24098 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24099 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24100 if (clobbersFlagRegisters(AsmPieces))
24101 return IntrinsicLowering::LowerToByteSwap(CI);
24104 if (CI->getType()->isIntegerTy(64)) {
24105 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24106 if (Constraints.size() >= 2 &&
24107 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24108 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24109 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24110 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24111 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24112 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24113 return IntrinsicLowering::LowerToByteSwap(CI);
24121 /// getConstraintType - Given a constraint letter, return the type of
24122 /// constraint it is for this target.
24123 X86TargetLowering::ConstraintType
24124 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24125 if (Constraint.size() == 1) {
24126 switch (Constraint[0]) {
24137 return C_RegisterClass;
24161 return TargetLowering::getConstraintType(Constraint);
24164 /// Examine constraint type and operand type and determine a weight value.
24165 /// This object must already have been set up with the operand type
24166 /// and the current alternative constraint selected.
24167 TargetLowering::ConstraintWeight
24168 X86TargetLowering::getSingleConstraintMatchWeight(
24169 AsmOperandInfo &info, const char *constraint) const {
24170 ConstraintWeight weight = CW_Invalid;
24171 Value *CallOperandVal = info.CallOperandVal;
24172 // If we don't have a value, we can't do a match,
24173 // but allow it at the lowest weight.
24174 if (!CallOperandVal)
24176 Type *type = CallOperandVal->getType();
24177 // Look at the constraint type.
24178 switch (*constraint) {
24180 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24191 if (CallOperandVal->getType()->isIntegerTy())
24192 weight = CW_SpecificReg;
24197 if (type->isFloatingPointTy())
24198 weight = CW_SpecificReg;
24201 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24202 weight = CW_SpecificReg;
24206 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24207 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24208 weight = CW_Register;
24211 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24212 if (C->getZExtValue() <= 31)
24213 weight = CW_Constant;
24217 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24218 if (C->getZExtValue() <= 63)
24219 weight = CW_Constant;
24223 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24224 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24225 weight = CW_Constant;
24229 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24230 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24231 weight = CW_Constant;
24235 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24236 if (C->getZExtValue() <= 3)
24237 weight = CW_Constant;
24241 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24242 if (C->getZExtValue() <= 0xff)
24243 weight = CW_Constant;
24248 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24249 weight = CW_Constant;
24253 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24254 if ((C->getSExtValue() >= -0x80000000LL) &&
24255 (C->getSExtValue() <= 0x7fffffffLL))
24256 weight = CW_Constant;
24260 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24261 if (C->getZExtValue() <= 0xffffffff)
24262 weight = CW_Constant;
24269 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24270 /// with another that has more specific requirements based on the type of the
24271 /// corresponding operand.
24272 const char *X86TargetLowering::
24273 LowerXConstraint(EVT ConstraintVT) const {
24274 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24275 // 'f' like normal targets.
24276 if (ConstraintVT.isFloatingPoint()) {
24277 if (Subtarget->hasSSE2())
24279 if (Subtarget->hasSSE1())
24283 return TargetLowering::LowerXConstraint(ConstraintVT);
24286 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24287 /// vector. If it is invalid, don't add anything to Ops.
24288 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24289 std::string &Constraint,
24290 std::vector<SDValue>&Ops,
24291 SelectionDAG &DAG) const {
24294 // Only support length 1 constraints for now.
24295 if (Constraint.length() > 1) return;
24297 char ConstraintLetter = Constraint[0];
24298 switch (ConstraintLetter) {
24301 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24302 if (C->getZExtValue() <= 31) {
24303 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24309 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24310 if (C->getZExtValue() <= 63) {
24311 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24318 if (isInt<8>(C->getSExtValue())) {
24319 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24326 if (C->getZExtValue() <= 255) {
24327 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24333 // 32-bit signed value
24334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24335 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24336 C->getSExtValue())) {
24337 // Widen to 64 bits here to get it sign extended.
24338 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24341 // FIXME gcc accepts some relocatable values here too, but only in certain
24342 // memory models; it's complicated.
24347 // 32-bit unsigned value
24348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24349 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24350 C->getZExtValue())) {
24351 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24355 // FIXME gcc accepts some relocatable values here too, but only in certain
24356 // memory models; it's complicated.
24360 // Literal immediates are always ok.
24361 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24362 // Widen to 64 bits here to get it sign extended.
24363 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24367 // In any sort of PIC mode addresses need to be computed at runtime by
24368 // adding in a register or some sort of table lookup. These can't
24369 // be used as immediates.
24370 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24373 // If we are in non-pic codegen mode, we allow the address of a global (with
24374 // an optional displacement) to be used with 'i'.
24375 GlobalAddressSDNode *GA = nullptr;
24376 int64_t Offset = 0;
24378 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24380 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24381 Offset += GA->getOffset();
24383 } else if (Op.getOpcode() == ISD::ADD) {
24384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24385 Offset += C->getZExtValue();
24386 Op = Op.getOperand(0);
24389 } else if (Op.getOpcode() == ISD::SUB) {
24390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24391 Offset += -C->getZExtValue();
24392 Op = Op.getOperand(0);
24397 // Otherwise, this isn't something we can handle, reject it.
24401 const GlobalValue *GV = GA->getGlobal();
24402 // If we require an extra load to get this address, as in PIC mode, we
24403 // can't accept it.
24404 if (isGlobalStubReference(
24405 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24408 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24409 GA->getValueType(0), Offset);
24414 if (Result.getNode()) {
24415 Ops.push_back(Result);
24418 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24421 std::pair<unsigned, const TargetRegisterClass*>
24422 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24424 // First, see if this is a constraint that directly corresponds to an LLVM
24426 if (Constraint.size() == 1) {
24427 // GCC Constraint Letters
24428 switch (Constraint[0]) {
24430 // TODO: Slight differences here in allocation order and leaving
24431 // RIP in the class. Do they matter any more here than they do
24432 // in the normal allocation?
24433 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24434 if (Subtarget->is64Bit()) {
24435 if (VT == MVT::i32 || VT == MVT::f32)
24436 return std::make_pair(0U, &X86::GR32RegClass);
24437 if (VT == MVT::i16)
24438 return std::make_pair(0U, &X86::GR16RegClass);
24439 if (VT == MVT::i8 || VT == MVT::i1)
24440 return std::make_pair(0U, &X86::GR8RegClass);
24441 if (VT == MVT::i64 || VT == MVT::f64)
24442 return std::make_pair(0U, &X86::GR64RegClass);
24445 // 32-bit fallthrough
24446 case 'Q': // Q_REGS
24447 if (VT == MVT::i32 || VT == MVT::f32)
24448 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24449 if (VT == MVT::i16)
24450 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24451 if (VT == MVT::i8 || VT == MVT::i1)
24452 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24453 if (VT == MVT::i64)
24454 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24456 case 'r': // GENERAL_REGS
24457 case 'l': // INDEX_REGS
24458 if (VT == MVT::i8 || VT == MVT::i1)
24459 return std::make_pair(0U, &X86::GR8RegClass);
24460 if (VT == MVT::i16)
24461 return std::make_pair(0U, &X86::GR16RegClass);
24462 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24463 return std::make_pair(0U, &X86::GR32RegClass);
24464 return std::make_pair(0U, &X86::GR64RegClass);
24465 case 'R': // LEGACY_REGS
24466 if (VT == MVT::i8 || VT == MVT::i1)
24467 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24468 if (VT == MVT::i16)
24469 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24470 if (VT == MVT::i32 || !Subtarget->is64Bit())
24471 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24472 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24473 case 'f': // FP Stack registers.
24474 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24475 // value to the correct fpstack register class.
24476 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24477 return std::make_pair(0U, &X86::RFP32RegClass);
24478 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24479 return std::make_pair(0U, &X86::RFP64RegClass);
24480 return std::make_pair(0U, &X86::RFP80RegClass);
24481 case 'y': // MMX_REGS if MMX allowed.
24482 if (!Subtarget->hasMMX()) break;
24483 return std::make_pair(0U, &X86::VR64RegClass);
24484 case 'Y': // SSE_REGS if SSE2 allowed
24485 if (!Subtarget->hasSSE2()) break;
24487 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24488 if (!Subtarget->hasSSE1()) break;
24490 switch (VT.SimpleTy) {
24492 // Scalar SSE types.
24495 return std::make_pair(0U, &X86::FR32RegClass);
24498 return std::make_pair(0U, &X86::FR64RegClass);
24506 return std::make_pair(0U, &X86::VR128RegClass);
24514 return std::make_pair(0U, &X86::VR256RegClass);
24519 return std::make_pair(0U, &X86::VR512RegClass);
24525 // Use the default implementation in TargetLowering to convert the register
24526 // constraint into a member of a register class.
24527 std::pair<unsigned, const TargetRegisterClass*> Res;
24528 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24530 // Not found as a standard register?
24532 // Map st(0) -> st(7) -> ST0
24533 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24534 tolower(Constraint[1]) == 's' &&
24535 tolower(Constraint[2]) == 't' &&
24536 Constraint[3] == '(' &&
24537 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24538 Constraint[5] == ')' &&
24539 Constraint[6] == '}') {
24541 Res.first = X86::FP0+Constraint[4]-'0';
24542 Res.second = &X86::RFP80RegClass;
24546 // GCC allows "st(0)" to be called just plain "st".
24547 if (StringRef("{st}").equals_lower(Constraint)) {
24548 Res.first = X86::FP0;
24549 Res.second = &X86::RFP80RegClass;
24554 if (StringRef("{flags}").equals_lower(Constraint)) {
24555 Res.first = X86::EFLAGS;
24556 Res.second = &X86::CCRRegClass;
24560 // 'A' means EAX + EDX.
24561 if (Constraint == "A") {
24562 Res.first = X86::EAX;
24563 Res.second = &X86::GR32_ADRegClass;
24569 // Otherwise, check to see if this is a register class of the wrong value
24570 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24571 // turn into {ax},{dx}.
24572 if (Res.second->hasType(VT))
24573 return Res; // Correct type already, nothing to do.
24575 // All of the single-register GCC register classes map their values onto
24576 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24577 // really want an 8-bit or 32-bit register, map to the appropriate register
24578 // class and return the appropriate register.
24579 if (Res.second == &X86::GR16RegClass) {
24580 if (VT == MVT::i8 || VT == MVT::i1) {
24581 unsigned DestReg = 0;
24582 switch (Res.first) {
24584 case X86::AX: DestReg = X86::AL; break;
24585 case X86::DX: DestReg = X86::DL; break;
24586 case X86::CX: DestReg = X86::CL; break;
24587 case X86::BX: DestReg = X86::BL; break;
24590 Res.first = DestReg;
24591 Res.second = &X86::GR8RegClass;
24593 } else if (VT == MVT::i32 || VT == MVT::f32) {
24594 unsigned DestReg = 0;
24595 switch (Res.first) {
24597 case X86::AX: DestReg = X86::EAX; break;
24598 case X86::DX: DestReg = X86::EDX; break;
24599 case X86::CX: DestReg = X86::ECX; break;
24600 case X86::BX: DestReg = X86::EBX; break;
24601 case X86::SI: DestReg = X86::ESI; break;
24602 case X86::DI: DestReg = X86::EDI; break;
24603 case X86::BP: DestReg = X86::EBP; break;
24604 case X86::SP: DestReg = X86::ESP; break;
24607 Res.first = DestReg;
24608 Res.second = &X86::GR32RegClass;
24610 } else if (VT == MVT::i64 || VT == MVT::f64) {
24611 unsigned DestReg = 0;
24612 switch (Res.first) {
24614 case X86::AX: DestReg = X86::RAX; break;
24615 case X86::DX: DestReg = X86::RDX; break;
24616 case X86::CX: DestReg = X86::RCX; break;
24617 case X86::BX: DestReg = X86::RBX; break;
24618 case X86::SI: DestReg = X86::RSI; break;
24619 case X86::DI: DestReg = X86::RDI; break;
24620 case X86::BP: DestReg = X86::RBP; break;
24621 case X86::SP: DestReg = X86::RSP; break;
24624 Res.first = DestReg;
24625 Res.second = &X86::GR64RegClass;
24628 } else if (Res.second == &X86::FR32RegClass ||
24629 Res.second == &X86::FR64RegClass ||
24630 Res.second == &X86::VR128RegClass ||
24631 Res.second == &X86::VR256RegClass ||
24632 Res.second == &X86::FR32XRegClass ||
24633 Res.second == &X86::FR64XRegClass ||
24634 Res.second == &X86::VR128XRegClass ||
24635 Res.second == &X86::VR256XRegClass ||
24636 Res.second == &X86::VR512RegClass) {
24637 // Handle references to XMM physical registers that got mapped into the
24638 // wrong class. This can happen with constraints like {xmm0} where the
24639 // target independent register mapper will just pick the first match it can
24640 // find, ignoring the required type.
24642 if (VT == MVT::f32 || VT == MVT::i32)
24643 Res.second = &X86::FR32RegClass;
24644 else if (VT == MVT::f64 || VT == MVT::i64)
24645 Res.second = &X86::FR64RegClass;
24646 else if (X86::VR128RegClass.hasType(VT))
24647 Res.second = &X86::VR128RegClass;
24648 else if (X86::VR256RegClass.hasType(VT))
24649 Res.second = &X86::VR256RegClass;
24650 else if (X86::VR512RegClass.hasType(VT))
24651 Res.second = &X86::VR512RegClass;
24657 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24659 // Scaling factors are not free at all.
24660 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24661 // will take 2 allocations in the out of order engine instead of 1
24662 // for plain addressing mode, i.e. inst (reg1).
24664 // vaddps (%rsi,%drx), %ymm0, %ymm1
24665 // Requires two allocations (one for the load, one for the computation)
24667 // vaddps (%rsi), %ymm0, %ymm1
24668 // Requires just 1 allocation, i.e., freeing allocations for other operations
24669 // and having less micro operations to execute.
24671 // For some X86 architectures, this is even worse because for instance for
24672 // stores, the complex addressing mode forces the instruction to use the
24673 // "load" ports instead of the dedicated "store" port.
24674 // E.g., on Haswell:
24675 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24676 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24677 if (isLegalAddressingMode(AM, Ty))
24678 // Scale represents reg2 * scale, thus account for 1
24679 // as soon as we use a second register.
24680 return AM.Scale != 0;
24684 bool X86TargetLowering::isTargetFTOL() const {
24685 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();