1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit boundary. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
171 SelectionDAG &DAG,SDLoc dl) {
172 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
176 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
177 SelectionDAG &DAG, SDLoc dl) {
178 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
179 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
182 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
183 /// instructions. This is used because creating CONCAT_VECTOR nodes of
184 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
185 /// large BUILD_VECTORS.
186 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
189 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
193 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
194 unsigned NumElems, SelectionDAG &DAG,
196 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
197 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
200 // FIXME: This should stop caching the target machine as soon as
201 // we can remove resetOperationActions et al.
202 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
203 : TargetLowering(TM) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
223 FirstTimeThrough = false;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird. It always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit, since we have so many registers, use the ILP scheduler.
237 // For 32-bit, use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2.
250 if (TM.getOptLevel() >= CodeGenOpt::Default) {
251 if (Subtarget->hasSlowDivide32())
252 addBypassSlowDiv(32, 8);
253 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
254 addBypassSlowDiv(64, 16);
257 if (Subtarget->isTargetKnownWindowsMSVC()) {
258 // Setup Windows compiler runtime calls.
259 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
260 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
261 setLibcallName(RTLIB::SREM_I64, "_allrem");
262 setLibcallName(RTLIB::UREM_I64, "_aullrem");
263 setLibcallName(RTLIB::MUL_I64, "_allmul");
264 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
270 // The _ftol2 runtime function has an unusual calling conv, which
271 // is modeled by a special pseudo-instruction.
272 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
278 if (Subtarget->isTargetDarwin()) {
279 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
280 setUseUnderscoreSetJmp(false);
281 setUseUnderscoreLongJmp(false);
282 } else if (Subtarget->isTargetWindowsGNU()) {
283 // MS runtime is weird: it exports _setjmp, but longjmp!
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(false);
287 setUseUnderscoreSetJmp(true);
288 setUseUnderscoreLongJmp(true);
291 // Set up the register classes.
292 addRegisterClass(MVT::i8, &X86::GR8RegClass);
293 addRegisterClass(MVT::i16, &X86::GR16RegClass);
294 addRegisterClass(MVT::i32, &X86::GR32RegClass);
295 if (Subtarget->is64Bit())
296 addRegisterClass(MVT::i64, &X86::GR64RegClass);
298 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
300 // We don't accept any truncstore of integer registers.
301 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
308 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
310 // SETOEQ and SETUNE require checking two conditions.
311 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
318 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
320 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
321 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
324 if (Subtarget->is64Bit()) {
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
327 } else if (!TM.Options.UseSoftFloat) {
328 // We have an algorithm for SSE2->double, and we turn this into a
329 // 64-bit FILD followed by conditional FADD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
331 // We have an algorithm for SSE2, and we turn this into a 64-bit
332 // FILD for other targets.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
336 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
338 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
339 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
341 if (!TM.Options.UseSoftFloat) {
342 // SSE has no i16 to fp conversion, only i32
343 if (X86ScalarSSEf32) {
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 // f32 and f64 cases are Legal, f80 case is not
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
356 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
357 // are Legal, f80 is custom lowered.
358 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
361 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
363 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
366 if (X86ScalarSSEf32) {
367 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
368 // f32 and f64 cases are Legal, f80 case is not
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
371 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
375 // Handle FP_TO_UINT by promoting the destination to a larger signed
377 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
378 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
384 } else if (!TM.Options.UseSoftFloat) {
385 // Since AVX is a superset of SSE3, only check for SSE here.
386 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
387 // Expand FP_TO_UINT into a select.
388 // FIXME: We would like to use a Custom expander here eventually to do
389 // the optimal thing for SSE vs. the default expansion in the legalizer.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
392 // With SSE3 we can use fisttpll to convert to a signed i64; without
393 // SSE, we're stuck with a fistpll.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
397 if (isTargetFTOL()) {
398 // Use the _ftol2 runtime function, which has a pseudo-instruction
399 // to handle its weird calling convention.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
403 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
404 if (!X86ScalarSSEf64) {
405 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
406 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
409 // Without SSE, i64->f64 goes through memory.
410 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
414 // Scalar integer divide and remainder are lowered to use operations that
415 // produce two results, to match the available instructions. This exposes
416 // the two-result form to trivial CSE, which is able to combine x/y and x%y
417 // into a single instruction.
419 // Scalar integer multiply-high is also lowered to use two-result
420 // operations, to match the available instructions. However, plain multiply
421 // (low) operations are left as Legal, as there are single-result
422 // instructions for this in x86. Using the two-result multiply instructions
423 // when both high and low results are needed must be arranged by dagcombine.
424 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
426 setOperationAction(ISD::MULHS, VT, Expand);
427 setOperationAction(ISD::MULHU, VT, Expand);
428 setOperationAction(ISD::SDIV, VT, Expand);
429 setOperationAction(ISD::UDIV, VT, Expand);
430 setOperationAction(ISD::SREM, VT, Expand);
431 setOperationAction(ISD::UREM, VT, Expand);
433 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
434 setOperationAction(ISD::ADDC, VT, Custom);
435 setOperationAction(ISD::ADDE, VT, Custom);
436 setOperationAction(ISD::SUBC, VT, Custom);
437 setOperationAction(ISD::SUBE, VT, Custom);
440 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
441 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
442 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
443 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
461 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
462 setOperationAction(ISD::FREM , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f64 , Expand);
464 setOperationAction(ISD::FREM , MVT::f80 , Expand);
465 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
467 // Promote the i8 variants and force them on up to i32 which has a shorter
469 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
473 if (Subtarget->hasBMI()) {
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
476 if (Subtarget->is64Bit())
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
479 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
480 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
485 if (Subtarget->hasLZCNT()) {
486 // When promoting the i8 variants, force them to i32 for a shorter
488 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
497 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
503 if (Subtarget->is64Bit()) {
504 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
509 // Special handling for half-precision floating point conversions.
510 // If we don't have F16C support, then lower half float conversions
511 // into library calls.
512 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
513 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
514 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
517 // There's never any support for operations beyond MVT::f32.
518 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
519 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
520 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
808 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
809 MVT VT = (MVT::SimpleValueType)i;
810 setOperationAction(ISD::ADD , VT, Expand);
811 setOperationAction(ISD::SUB , VT, Expand);
812 setOperationAction(ISD::FADD, VT, Expand);
813 setOperationAction(ISD::FNEG, VT, Expand);
814 setOperationAction(ISD::FSUB, VT, Expand);
815 setOperationAction(ISD::MUL , VT, Expand);
816 setOperationAction(ISD::FMUL, VT, Expand);
817 setOperationAction(ISD::SDIV, VT, Expand);
818 setOperationAction(ISD::UDIV, VT, Expand);
819 setOperationAction(ISD::FDIV, VT, Expand);
820 setOperationAction(ISD::SREM, VT, Expand);
821 setOperationAction(ISD::UREM, VT, Expand);
822 setOperationAction(ISD::LOAD, VT, Expand);
823 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
827 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::FABS, VT, Expand);
829 setOperationAction(ISD::FSIN, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FCOS, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FREM, VT, Expand);
834 setOperationAction(ISD::FMA, VT, Expand);
835 setOperationAction(ISD::FPOWI, VT, Expand);
836 setOperationAction(ISD::FSQRT, VT, Expand);
837 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
838 setOperationAction(ISD::FFLOOR, VT, Expand);
839 setOperationAction(ISD::FCEIL, VT, Expand);
840 setOperationAction(ISD::FTRUNC, VT, Expand);
841 setOperationAction(ISD::FRINT, VT, Expand);
842 setOperationAction(ISD::FNEARBYINT, VT, Expand);
843 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHS, VT, Expand);
845 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHU, VT, Expand);
847 setOperationAction(ISD::SDIVREM, VT, Expand);
848 setOperationAction(ISD::UDIVREM, VT, Expand);
849 setOperationAction(ISD::FPOW, VT, Expand);
850 setOperationAction(ISD::CTPOP, VT, Expand);
851 setOperationAction(ISD::CTTZ, VT, Expand);
852 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::CTLZ, VT, Expand);
854 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::SHL, VT, Expand);
856 setOperationAction(ISD::SRA, VT, Expand);
857 setOperationAction(ISD::SRL, VT, Expand);
858 setOperationAction(ISD::ROTL, VT, Expand);
859 setOperationAction(ISD::ROTR, VT, Expand);
860 setOperationAction(ISD::BSWAP, VT, Expand);
861 setOperationAction(ISD::SETCC, VT, Expand);
862 setOperationAction(ISD::FLOG, VT, Expand);
863 setOperationAction(ISD::FLOG2, VT, Expand);
864 setOperationAction(ISD::FLOG10, VT, Expand);
865 setOperationAction(ISD::FEXP, VT, Expand);
866 setOperationAction(ISD::FEXP2, VT, Expand);
867 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
868 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
869 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
870 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
872 setOperationAction(ISD::TRUNCATE, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
874 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
875 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
876 setOperationAction(ISD::VSELECT, VT, Expand);
877 setOperationAction(ISD::SELECT_CC, VT, Expand);
878 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
879 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
880 setTruncStoreAction(VT,
881 (MVT::SimpleValueType)InnerVT, Expand);
882 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
883 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
885 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
886 // we have to deal with them whether we ask for Expansion or not. Setting
887 // Expand causes its own optimisation problems though, so leave them legal.
888 if (VT.getVectorElementType() == MVT::i1)
889 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
892 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
893 // with -msoft-float, disable use of MMX as well.
894 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
895 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
896 // No operations on x86mmx supported, everything uses intrinsics.
899 // MMX-sized vectors (other than x86mmx) are expected to be expanded
900 // into smaller operations.
901 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
902 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
903 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
904 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
905 setOperationAction(ISD::AND, MVT::v8i8, Expand);
906 setOperationAction(ISD::AND, MVT::v4i16, Expand);
907 setOperationAction(ISD::AND, MVT::v2i32, Expand);
908 setOperationAction(ISD::AND, MVT::v1i64, Expand);
909 setOperationAction(ISD::OR, MVT::v8i8, Expand);
910 setOperationAction(ISD::OR, MVT::v4i16, Expand);
911 setOperationAction(ISD::OR, MVT::v2i32, Expand);
912 setOperationAction(ISD::OR, MVT::v1i64, Expand);
913 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
914 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
915 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
916 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
922 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
923 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
924 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
925 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
931 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
932 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
934 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
936 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
937 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
938 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
940 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
941 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
942 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
943 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
945 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
946 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
949 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
950 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
952 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
953 // registers cannot be used even for integer operations.
954 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
955 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
956 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
957 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
959 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
960 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
961 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
962 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
963 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
964 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
965 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
966 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
968 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
970 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
972 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
974 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
976 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
977 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
978 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
979 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
980 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
982 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
984 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
985 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
996 // Do not attempt to custom lower non-power-of-2 vectors
997 if (!isPowerOf2_32(VT.getVectorNumElements()))
999 // Do not attempt to custom lower non-128-bit vectors
1000 if (!VT.is128BitVector())
1002 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1003 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1007 // We support custom legalizing of sext and anyext loads for specific
1008 // memory vector types which we can load as a scalar (or sequence of
1009 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1010 // loads these must work with a single scalar load.
1011 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1021 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1023 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1025 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1026 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1028 if (Subtarget->is64Bit()) {
1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1030 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1033 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1034 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1035 MVT VT = (MVT::SimpleValueType)i;
1037 // Do not attempt to promote non-128-bit vectors
1038 if (!VT.is128BitVector())
1041 setOperationAction(ISD::AND, VT, Promote);
1042 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1043 setOperationAction(ISD::OR, VT, Promote);
1044 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1045 setOperationAction(ISD::XOR, VT, Promote);
1046 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1047 setOperationAction(ISD::LOAD, VT, Promote);
1048 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1049 setOperationAction(ISD::SELECT, VT, Promote);
1050 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1053 // Custom lower v2i64 and v2f64 selects.
1054 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1055 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1056 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1060 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1062 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1064 // As there is no 64-bit GPR available, we need build a special custom
1065 // sequence to convert from v2i32 to v2f32.
1066 if (!Subtarget->is64Bit())
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1069 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1072 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1074 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1075 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1079 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1080 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1102 // FIXME: Do we need to handle scalar-to-vector here?
1103 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1105 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1110 // There is no BLENDI for byte vectors. We don't need to custom lower
1111 // some vselects for now.
1112 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1114 // SSE41 brings specific instructions for doing vector sign extend even in
1115 // cases where we don't have SRA.
1116 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1216 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1223 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1230 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1248 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1252 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1253 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::f64, Legal);
1261 if (Subtarget->hasInt256()) {
1262 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1263 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1264 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1265 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1267 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1268 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1269 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1270 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1272 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1273 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1274 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1275 // Don't lower v32i8 because there is no 128-bit byte mul
1277 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1278 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1280 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1282 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1283 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1285 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1286 // when we have a 256bit-wide blend with immediate.
1287 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1289 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1290 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1292 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1294 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1295 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1296 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1297 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1299 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1300 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1301 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1302 // Don't lower v32i8 because there is no 128-bit byte mul
1305 // In the customized shift lowering, the legal cases in AVX2 will be
1307 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1311 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1313 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1315 // Custom lower several nodes for 256-bit types.
1316 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1317 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1318 MVT VT = (MVT::SimpleValueType)i;
1320 // Extract subvector is special because the value type
1321 // (result) is 128-bit but the source is 256-bit wide.
1322 if (VT.is128BitVector())
1323 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1325 // Do not attempt to custom lower other non-256-bit vectors
1326 if (!VT.is256BitVector())
1329 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1334 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1335 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1338 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1339 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1340 MVT VT = (MVT::SimpleValueType)i;
1342 // Do not attempt to promote non-256-bit vectors
1343 if (!VT.is256BitVector())
1346 setOperationAction(ISD::AND, VT, Promote);
1347 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1348 setOperationAction(ISD::OR, VT, Promote);
1349 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1350 setOperationAction(ISD::XOR, VT, Promote);
1351 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1352 setOperationAction(ISD::LOAD, VT, Promote);
1353 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1354 setOperationAction(ISD::SELECT, VT, Promote);
1355 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1359 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1360 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1361 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1365 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1366 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1367 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1369 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1370 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1371 setOperationAction(ISD::XOR, MVT::i1, Legal);
1372 setOperationAction(ISD::OR, MVT::i1, Legal);
1373 setOperationAction(ISD::AND, MVT::i1, Legal);
1374 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1375 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1381 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1388 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1389 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1394 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1397 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1398 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1401 if (Subtarget->is64Bit()) {
1402 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1411 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1416 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1420 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1428 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1436 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1443 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1444 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1446 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1448 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1450 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1454 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1458 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1459 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1461 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1462 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1464 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1466 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1469 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1470 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1472 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1473 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1475 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1476 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1477 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1479 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1480 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1482 if (Subtarget->hasCDI()) {
1483 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1484 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 // Custom lower several nodes.
1488 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1489 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1490 MVT VT = (MVT::SimpleValueType)i;
1492 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1493 // Extract subvector is special because the value type
1494 // (result) is 256/128-bit but the source is 512-bit wide.
1495 if (VT.is128BitVector() || VT.is256BitVector())
1496 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1498 if (VT.getVectorElementType() == MVT::i1)
1499 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1501 // Do not attempt to custom lower other non-512-bit vectors
1502 if (!VT.is512BitVector())
1505 if ( EltSize >= 32) {
1506 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1507 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1508 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1509 setOperationAction(ISD::VSELECT, VT, Legal);
1510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1512 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1516 MVT VT = (MVT::SimpleValueType)i;
1518 // Do not attempt to promote non-256-bit vectors.
1519 if (!VT.is512BitVector())
1522 setOperationAction(ISD::SELECT, VT, Promote);
1523 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1527 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1528 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1529 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1532 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1535 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1536 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1537 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1539 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1540 const MVT VT = (MVT::SimpleValueType)i;
1542 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 // Do not attempt to promote non-256-bit vectors.
1545 if (!VT.is512BitVector())
1549 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1550 setOperationAction(ISD::VSELECT, VT, Legal);
1555 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1556 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1557 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1559 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1560 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1561 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1564 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1565 // of this type with custom code.
1566 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1567 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1568 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1572 // We want to custom lower some of our intrinsics.
1573 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1574 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1576 if (!Subtarget->is64Bit())
1577 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1579 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1580 // handle type legalization for these operations here.
1582 // FIXME: We really should do custom legalization for addition and
1583 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1584 // than generic legalization for 64-bit multiplication-with-overflow, though.
1585 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1586 // Add/Sub/Mul with overflow operations are custom lowered.
1588 setOperationAction(ISD::SADDO, VT, Custom);
1589 setOperationAction(ISD::UADDO, VT, Custom);
1590 setOperationAction(ISD::SSUBO, VT, Custom);
1591 setOperationAction(ISD::USUBO, VT, Custom);
1592 setOperationAction(ISD::SMULO, VT, Custom);
1593 setOperationAction(ISD::UMULO, VT, Custom);
1597 if (!Subtarget->is64Bit()) {
1598 // These libcalls are not available in 32-bit.
1599 setLibcallName(RTLIB::SHL_I128, nullptr);
1600 setLibcallName(RTLIB::SRL_I128, nullptr);
1601 setLibcallName(RTLIB::SRA_I128, nullptr);
1604 // Combine sin / cos into one node or libcall if possible.
1605 if (Subtarget->hasSinCos()) {
1606 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1607 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1608 if (Subtarget->isTargetDarwin()) {
1609 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1610 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1611 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1612 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1616 if (Subtarget->isTargetWin64()) {
1617 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1618 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1619 setOperationAction(ISD::SREM, MVT::i128, Custom);
1620 setOperationAction(ISD::UREM, MVT::i128, Custom);
1621 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1625 // We have target-specific dag combine patterns for the following nodes:
1626 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1627 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1628 setTargetDAGCombine(ISD::VSELECT);
1629 setTargetDAGCombine(ISD::SELECT);
1630 setTargetDAGCombine(ISD::SHL);
1631 setTargetDAGCombine(ISD::SRA);
1632 setTargetDAGCombine(ISD::SRL);
1633 setTargetDAGCombine(ISD::OR);
1634 setTargetDAGCombine(ISD::AND);
1635 setTargetDAGCombine(ISD::ADD);
1636 setTargetDAGCombine(ISD::FADD);
1637 setTargetDAGCombine(ISD::FSUB);
1638 setTargetDAGCombine(ISD::FMA);
1639 setTargetDAGCombine(ISD::SUB);
1640 setTargetDAGCombine(ISD::LOAD);
1641 setTargetDAGCombine(ISD::STORE);
1642 setTargetDAGCombine(ISD::ZERO_EXTEND);
1643 setTargetDAGCombine(ISD::ANY_EXTEND);
1644 setTargetDAGCombine(ISD::SIGN_EXTEND);
1645 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1646 setTargetDAGCombine(ISD::TRUNCATE);
1647 setTargetDAGCombine(ISD::SINT_TO_FP);
1648 setTargetDAGCombine(ISD::SETCC);
1649 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1650 setTargetDAGCombine(ISD::BUILD_VECTOR);
1651 if (Subtarget->is64Bit())
1652 setTargetDAGCombine(ISD::MUL);
1653 setTargetDAGCombine(ISD::XOR);
1655 computeRegisterProperties();
1657 // On Darwin, -Os means optimize for size without hurting performance,
1658 // do not reduce the limit.
1659 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1660 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1661 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1662 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1663 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1664 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 setPrefLoopAlignment(4); // 2^4 bytes.
1667 // Predictable cmov don't hurt on atom because it's in-order.
1668 PredictableSelectIsExpensive = !Subtarget->isAtom();
1670 setPrefFunctionAlignment(4); // 2^4 bytes.
1672 verifyIntrinsicTables();
1675 // This has so far only been implemented for 64-bit MachO.
1676 bool X86TargetLowering::useLoadStackGuardNode() const {
1677 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1678 Subtarget->is64Bit();
1681 TargetLoweringBase::LegalizeTypeAction
1682 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1683 if (ExperimentalVectorWideningLegalization &&
1684 VT.getVectorNumElements() != 1 &&
1685 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1686 return TypeWidenVector;
1688 return TargetLoweringBase::getPreferredVectorAction(VT);
1691 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1693 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1695 const unsigned NumElts = VT.getVectorNumElements();
1696 const EVT EltVT = VT.getVectorElementType();
1697 if (VT.is512BitVector()) {
1698 if (Subtarget->hasAVX512())
1699 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1700 EltVT == MVT::f32 || EltVT == MVT::f64)
1702 case 8: return MVT::v8i1;
1703 case 16: return MVT::v16i1;
1705 if (Subtarget->hasBWI())
1706 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1708 case 32: return MVT::v32i1;
1709 case 64: return MVT::v64i1;
1713 if (VT.is256BitVector() || VT.is128BitVector()) {
1714 if (Subtarget->hasVLX())
1715 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1716 EltVT == MVT::f32 || EltVT == MVT::f64)
1718 case 2: return MVT::v2i1;
1719 case 4: return MVT::v4i1;
1720 case 8: return MVT::v8i1;
1722 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1723 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1725 case 8: return MVT::v8i1;
1726 case 16: return MVT::v16i1;
1727 case 32: return MVT::v32i1;
1731 return VT.changeVectorElementTypeToInteger();
1734 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1735 /// the desired ByVal argument alignment.
1736 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1739 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1740 if (VTy->getBitWidth() == 128)
1742 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1743 unsigned EltAlign = 0;
1744 getMaxByValAlign(ATy->getElementType(), EltAlign);
1745 if (EltAlign > MaxAlign)
1746 MaxAlign = EltAlign;
1747 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1748 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(STy->getElementType(i), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1759 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1760 /// function arguments in the caller parameter area. For X86, aggregates
1761 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1762 /// are at 4-byte boundaries.
1763 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1764 if (Subtarget->is64Bit()) {
1765 // Max of 8 and alignment of type.
1766 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1773 if (Subtarget->hasSSE1())
1774 getMaxByValAlign(Ty, Align);
1778 /// getOptimalMemOpType - Returns the target specific optimal type for load
1779 /// and store operations as a result of memset, memcpy, and memmove
1780 /// lowering. If DstAlign is zero that means it's safe to destination
1781 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1782 /// means there isn't a need to check it against alignment requirement,
1783 /// probably because the source does not need to be loaded. If 'IsMemset' is
1784 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1785 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1786 /// source is constant so it does not need to be loaded.
1787 /// It returns EVT::Other if the type should be determined using generic
1788 /// target-independent logic.
1790 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1791 unsigned DstAlign, unsigned SrcAlign,
1792 bool IsMemset, bool ZeroMemset,
1794 MachineFunction &MF) const {
1795 const Function *F = MF.getFunction();
1796 if ((!IsMemset || ZeroMemset) &&
1797 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1798 Attribute::NoImplicitFloat)) {
1800 (Subtarget->isUnalignedMemAccessFast() ||
1801 ((DstAlign == 0 || DstAlign >= 16) &&
1802 (SrcAlign == 0 || SrcAlign >= 16)))) {
1804 if (Subtarget->hasInt256())
1806 if (Subtarget->hasFp256())
1809 if (Subtarget->hasSSE2())
1811 if (Subtarget->hasSSE1())
1813 } else if (!MemcpyStrSrc && Size >= 8 &&
1814 !Subtarget->is64Bit() &&
1815 Subtarget->hasSSE2()) {
1816 // Do not use f64 to lower memcpy if source is string constant. It's
1817 // better to use i32 to avoid the loads.
1821 if (Subtarget->is64Bit() && Size >= 8)
1826 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1828 return X86ScalarSSEf32;
1829 else if (VT == MVT::f64)
1830 return X86ScalarSSEf64;
1835 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1840 *Fast = Subtarget->isUnalignedMemAccessFast();
1844 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1845 /// current function. The returned value is a member of the
1846 /// MachineJumpTableInfo::JTEntryKind enum.
1847 unsigned X86TargetLowering::getJumpTableEncoding() const {
1848 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1850 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1851 Subtarget->isPICStyleGOT())
1852 return MachineJumpTableInfo::EK_Custom32;
1854 // Otherwise, use the normal jump table encoding heuristics.
1855 return TargetLowering::getJumpTableEncoding();
1859 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1860 const MachineBasicBlock *MBB,
1861 unsigned uid,MCContext &Ctx) const{
1862 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1863 Subtarget->isPICStyleGOT());
1864 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1866 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1867 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1870 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1872 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1873 SelectionDAG &DAG) const {
1874 if (!Subtarget->is64Bit())
1875 // This doesn't have SDLoc associated with it, but is not really the
1876 // same as a Register.
1877 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1881 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1882 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1884 const MCExpr *X86TargetLowering::
1885 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1886 MCContext &Ctx) const {
1887 // X86-64 uses RIP relative addressing based on the jump table label.
1888 if (Subtarget->isPICStyleRIPRel())
1889 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1891 // Otherwise, the reference is relative to the PIC base.
1892 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1895 // FIXME: Why this routine is here? Move to RegInfo!
1896 std::pair<const TargetRegisterClass*, uint8_t>
1897 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1898 const TargetRegisterClass *RRC = nullptr;
1900 switch (VT.SimpleTy) {
1902 return TargetLowering::findRepresentativeClass(VT);
1903 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1904 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1907 RRC = &X86::VR64RegClass;
1909 case MVT::f32: case MVT::f64:
1910 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1911 case MVT::v4f32: case MVT::v2f64:
1912 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1914 RRC = &X86::VR128RegClass;
1917 return std::make_pair(RRC, Cost);
1920 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1921 unsigned &Offset) const {
1922 if (!Subtarget->isTargetLinux())
1925 if (Subtarget->is64Bit()) {
1926 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1928 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1940 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1941 unsigned DestAS) const {
1942 assert(SrcAS != DestAS && "Expected different address spaces!");
1944 return SrcAS < 256 && DestAS < 256;
1947 //===----------------------------------------------------------------------===//
1948 // Return Value Calling Convention Implementation
1949 //===----------------------------------------------------------------------===//
1951 #include "X86GenCallingConv.inc"
1954 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1955 MachineFunction &MF, bool isVarArg,
1956 const SmallVectorImpl<ISD::OutputArg> &Outs,
1957 LLVMContext &Context) const {
1958 SmallVector<CCValAssign, 16> RVLocs;
1959 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1960 return CCInfo.CheckReturn(Outs, RetCC_X86);
1963 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1964 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1969 X86TargetLowering::LowerReturn(SDValue Chain,
1970 CallingConv::ID CallConv, bool isVarArg,
1971 const SmallVectorImpl<ISD::OutputArg> &Outs,
1972 const SmallVectorImpl<SDValue> &OutVals,
1973 SDLoc dl, SelectionDAG &DAG) const {
1974 MachineFunction &MF = DAG.getMachineFunction();
1975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1977 SmallVector<CCValAssign, 16> RVLocs;
1978 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1979 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1982 SmallVector<SDValue, 6> RetOps;
1983 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1984 // Operand #1 = Bytes To Pop
1985 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1988 // Copy the result values into the output registers.
1989 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1990 CCValAssign &VA = RVLocs[i];
1991 assert(VA.isRegLoc() && "Can only return in registers!");
1992 SDValue ValToCopy = OutVals[i];
1993 EVT ValVT = ValToCopy.getValueType();
1995 // Promote values to the appropriate types.
1996 if (VA.getLocInfo() == CCValAssign::SExt)
1997 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1998 else if (VA.getLocInfo() == CCValAssign::ZExt)
1999 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::AExt)
2001 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::BCvt)
2003 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2005 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2006 "Unexpected FP-extend for return value.");
2008 // If this is x86-64, and we disabled SSE, we can't return FP values,
2009 // or SSE or MMX vectors.
2010 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2011 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2012 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2013 report_fatal_error("SSE register return with SSE disabled");
2015 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2016 // llvm-gcc has never done it right and no one has noticed, so this
2017 // should be OK for now.
2018 if (ValVT == MVT::f64 &&
2019 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2020 report_fatal_error("SSE2 register return with SSE2 disabled");
2022 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2023 // the RET instruction and handled by the FP Stackifier.
2024 if (VA.getLocReg() == X86::FP0 ||
2025 VA.getLocReg() == X86::FP1) {
2026 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2027 // change the value to the FP stack register class.
2028 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2029 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2030 RetOps.push_back(ValToCopy);
2031 // Don't emit a copytoreg.
2035 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2036 // which is returned in RAX / RDX.
2037 if (Subtarget->is64Bit()) {
2038 if (ValVT == MVT::x86mmx) {
2039 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2040 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2041 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2043 // If we don't have SSE2 available, convert to v4f32 so the generated
2044 // register is legal.
2045 if (!Subtarget->hasSSE2())
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2051 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2052 Flag = Chain.getValue(1);
2053 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2056 // The x86-64 ABIs require that for returning structs by value we copy
2057 // the sret argument into %rax/%eax (depending on ABI) for the return.
2058 // Win32 requires us to put the sret argument to %eax as well.
2059 // We saved the argument into a virtual register in the entry block,
2060 // so now we copy the value out and into %rax/%eax.
2061 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2062 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2063 MachineFunction &MF = DAG.getMachineFunction();
2064 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2065 unsigned Reg = FuncInfo->getSRetReturnReg();
2067 "SRetReturnReg should have been set in LowerFormalArguments().");
2068 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2071 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2072 X86::RAX : X86::EAX;
2073 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2074 Flag = Chain.getValue(1);
2076 // RAX/EAX now acts like a return value.
2077 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2080 RetOps[0] = Chain; // Update chain.
2082 // Add the flag if we have it.
2084 RetOps.push_back(Flag);
2086 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2089 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2090 if (N->getNumValues() != 1)
2092 if (!N->hasNUsesOfValue(1, 0))
2095 SDValue TCChain = Chain;
2096 SDNode *Copy = *N->use_begin();
2097 if (Copy->getOpcode() == ISD::CopyToReg) {
2098 // If the copy has a glue operand, we conservatively assume it isn't safe to
2099 // perform a tail call.
2100 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2102 TCChain = Copy->getOperand(0);
2103 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2106 bool HasRet = false;
2107 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2109 if (UI->getOpcode() != X86ISD::RET_FLAG)
2111 // If we are returning more than one value, we can definitely
2112 // not make a tail call see PR19530
2113 if (UI->getNumOperands() > 4)
2115 if (UI->getNumOperands() == 4 &&
2116 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2129 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2130 ISD::NodeType ExtendKind) const {
2132 // TODO: Is this also valid on 32-bit?
2133 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2134 ReturnMVT = MVT::i8;
2136 ReturnMVT = MVT::i32;
2138 EVT MinVT = getRegisterType(Context, ReturnMVT);
2139 return VT.bitsLT(MinVT) ? MinVT : VT;
2142 /// LowerCallResult - Lower the result values of a call into the
2143 /// appropriate copies out of appropriate physical registers.
2146 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2147 CallingConv::ID CallConv, bool isVarArg,
2148 const SmallVectorImpl<ISD::InputArg> &Ins,
2149 SDLoc dl, SelectionDAG &DAG,
2150 SmallVectorImpl<SDValue> &InVals) const {
2152 // Assign locations to each value returned by this call.
2153 SmallVector<CCValAssign, 16> RVLocs;
2154 bool Is64Bit = Subtarget->is64Bit();
2155 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2157 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2159 // Copy all of the result registers out of their specified physreg.
2160 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2161 CCValAssign &VA = RVLocs[i];
2162 EVT CopyVT = VA.getValVT();
2164 // If this is x86-64, and we disabled SSE, we can't return FP values
2165 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2166 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2167 report_fatal_error("SSE register return with SSE disabled");
2170 // If we prefer to use the value in xmm registers, copy it out as f80 and
2171 // use a truncate to move it from fp stack reg to xmm reg.
2172 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2173 isScalarFPTypeInSSEReg(VA.getValVT()))
2176 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2177 CopyVT, InFlag).getValue(1);
2178 SDValue Val = Chain.getValue(0);
2180 if (CopyVT != VA.getValVT())
2181 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2182 // This truncation won't change the value.
2183 DAG.getIntPtrConstant(1));
2185 InFlag = Chain.getValue(2);
2186 InVals.push_back(Val);
2192 //===----------------------------------------------------------------------===//
2193 // C & StdCall & Fast Calling Convention implementation
2194 //===----------------------------------------------------------------------===//
2195 // StdCall calling convention seems to be standard for many Windows' API
2196 // routines and around. It differs from C calling convention just a little:
2197 // callee should clean up the stack, not caller. Symbols should be also
2198 // decorated in some fancy way :) It doesn't support any vector arguments.
2199 // For info on fast calling convention see Fast Calling Convention (tail call)
2200 // implementation LowerX86_32FastCCCallTo.
2202 /// CallIsStructReturn - Determines whether a call uses struct return
2204 enum StructReturnType {
2209 static StructReturnType
2210 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2212 return NotStructReturn;
2214 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2215 if (!Flags.isSRet())
2216 return NotStructReturn;
2217 if (Flags.isInReg())
2218 return RegStructReturn;
2219 return StackStructReturn;
2222 /// ArgsAreStructReturn - Determines whether a function uses struct
2223 /// return semantics.
2224 static StructReturnType
2225 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2227 return NotStructReturn;
2229 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2230 if (!Flags.isSRet())
2231 return NotStructReturn;
2232 if (Flags.isInReg())
2233 return RegStructReturn;
2234 return StackStructReturn;
2237 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2238 /// by "Src" to address "Dst" with size and alignment information specified by
2239 /// the specific parameter attribute. The copy will be passed as a byval
2240 /// function parameter.
2242 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2243 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2245 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2247 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2248 /*isVolatile*/false, /*AlwaysInline=*/true,
2249 MachinePointerInfo(), MachinePointerInfo());
2252 /// IsTailCallConvention - Return true if the calling convention is one that
2253 /// supports tail call optimization.
2254 static bool IsTailCallConvention(CallingConv::ID CC) {
2255 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2256 CC == CallingConv::HiPE);
2259 /// \brief Return true if the calling convention is a C calling convention.
2260 static bool IsCCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2262 CC == CallingConv::X86_64_SysV);
2265 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2266 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2270 CallingConv::ID CalleeCC = CS.getCallingConv();
2271 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2277 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2278 /// a tailcall target by changing its ABI.
2279 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2280 bool GuaranteedTailCallOpt) {
2281 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2285 X86TargetLowering::LowerMemArgument(SDValue Chain,
2286 CallingConv::ID CallConv,
2287 const SmallVectorImpl<ISD::InputArg> &Ins,
2288 SDLoc dl, SelectionDAG &DAG,
2289 const CCValAssign &VA,
2290 MachineFrameInfo *MFI,
2292 // Create the nodes corresponding to a load from this parameter slot.
2293 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2294 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2295 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2296 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2299 // If value is passed by pointer we have address passed instead of the value
2301 if (VA.getLocInfo() == CCValAssign::Indirect)
2302 ValVT = VA.getLocVT();
2304 ValVT = VA.getValVT();
2306 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2307 // changed with more analysis.
2308 // In case of tail call optimization mark all arguments mutable. Since they
2309 // could be overwritten by lowering of arguments in case of a tail call.
2310 if (Flags.isByVal()) {
2311 unsigned Bytes = Flags.getByValSize();
2312 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2313 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2314 return DAG.getFrameIndex(FI, getPointerTy());
2316 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2317 VA.getLocMemOffset(), isImmutable);
2318 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2319 return DAG.getLoad(ValVT, dl, Chain, FIN,
2320 MachinePointerInfo::getFixedStack(FI),
2321 false, false, false, 0);
2325 // FIXME: Get this from tablegen.
2326 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2327 const X86Subtarget *Subtarget) {
2328 assert(Subtarget->is64Bit());
2330 if (Subtarget->isCallingConvWin64(CallConv)) {
2331 static const MCPhysReg GPR64ArgRegsWin64[] = {
2332 X86::RCX, X86::RDX, X86::R8, X86::R9
2334 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2337 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2338 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2343 // FIXME: Get this from tablegen.
2344 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2345 CallingConv::ID CallConv,
2346 const X86Subtarget *Subtarget) {
2347 assert(Subtarget->is64Bit());
2348 if (Subtarget->isCallingConvWin64(CallConv)) {
2349 // The XMM registers which might contain var arg parameters are shadowed
2350 // in their paired GPR. So we only need to save the GPR to their home
2352 // TODO: __vectorcall will change this.
2356 const Function *Fn = MF.getFunction();
2357 bool NoImplicitFloatOps = Fn->getAttributes().
2358 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2359 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2360 "SSE register cannot be used when SSE is disabled!");
2361 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2362 !Subtarget->hasSSE1())
2363 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2367 static const MCPhysReg XMMArgRegs64Bit[] = {
2368 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2369 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2371 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2375 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2376 CallingConv::ID CallConv,
2378 const SmallVectorImpl<ISD::InputArg> &Ins,
2381 SmallVectorImpl<SDValue> &InVals)
2383 MachineFunction &MF = DAG.getMachineFunction();
2384 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2386 const Function* Fn = MF.getFunction();
2387 if (Fn->hasExternalLinkage() &&
2388 Subtarget->isTargetCygMing() &&
2389 Fn->getName() == "main")
2390 FuncInfo->setForceFramePointer(true);
2392 MachineFrameInfo *MFI = MF.getFrameInfo();
2393 bool Is64Bit = Subtarget->is64Bit();
2394 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2396 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2397 "Var args not supported with calling convention fastcc, ghc or hipe");
2399 // Assign locations to all of the incoming arguments.
2400 SmallVector<CCValAssign, 16> ArgLocs;
2401 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2403 // Allocate shadow area for Win64
2405 CCInfo.AllocateStack(32, 8);
2407 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2409 unsigned LastVal = ~0U;
2411 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2412 CCValAssign &VA = ArgLocs[i];
2413 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2415 assert(VA.getValNo() != LastVal &&
2416 "Don't support value assigned to multiple locs yet");
2418 LastVal = VA.getValNo();
2420 if (VA.isRegLoc()) {
2421 EVT RegVT = VA.getLocVT();
2422 const TargetRegisterClass *RC;
2423 if (RegVT == MVT::i32)
2424 RC = &X86::GR32RegClass;
2425 else if (Is64Bit && RegVT == MVT::i64)
2426 RC = &X86::GR64RegClass;
2427 else if (RegVT == MVT::f32)
2428 RC = &X86::FR32RegClass;
2429 else if (RegVT == MVT::f64)
2430 RC = &X86::FR64RegClass;
2431 else if (RegVT.is512BitVector())
2432 RC = &X86::VR512RegClass;
2433 else if (RegVT.is256BitVector())
2434 RC = &X86::VR256RegClass;
2435 else if (RegVT.is128BitVector())
2436 RC = &X86::VR128RegClass;
2437 else if (RegVT == MVT::x86mmx)
2438 RC = &X86::VR64RegClass;
2439 else if (RegVT == MVT::i1)
2440 RC = &X86::VK1RegClass;
2441 else if (RegVT == MVT::v8i1)
2442 RC = &X86::VK8RegClass;
2443 else if (RegVT == MVT::v16i1)
2444 RC = &X86::VK16RegClass;
2445 else if (RegVT == MVT::v32i1)
2446 RC = &X86::VK32RegClass;
2447 else if (RegVT == MVT::v64i1)
2448 RC = &X86::VK64RegClass;
2450 llvm_unreachable("Unknown argument type!");
2452 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2453 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2455 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2456 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2458 if (VA.getLocInfo() == CCValAssign::SExt)
2459 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2460 DAG.getValueType(VA.getValVT()));
2461 else if (VA.getLocInfo() == CCValAssign::ZExt)
2462 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2463 DAG.getValueType(VA.getValVT()));
2464 else if (VA.getLocInfo() == CCValAssign::BCvt)
2465 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2467 if (VA.isExtInLoc()) {
2468 // Handle MMX values passed in XMM regs.
2469 if (RegVT.isVector())
2470 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2472 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2475 assert(VA.isMemLoc());
2476 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2479 // If value is passed via pointer - do a load.
2480 if (VA.getLocInfo() == CCValAssign::Indirect)
2481 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2482 MachinePointerInfo(), false, false, false, 0);
2484 InVals.push_back(ArgValue);
2487 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2488 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2489 // The x86-64 ABIs require that for returning structs by value we copy
2490 // the sret argument into %rax/%eax (depending on ABI) for the return.
2491 // Win32 requires us to put the sret argument to %eax as well.
2492 // Save the argument into a virtual register so that we can access it
2493 // from the return points.
2494 if (Ins[i].Flags.isSRet()) {
2495 unsigned Reg = FuncInfo->getSRetReturnReg();
2497 MVT PtrTy = getPointerTy();
2498 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2499 FuncInfo->setSRetReturnReg(Reg);
2501 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2502 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2508 unsigned StackSize = CCInfo.getNextStackOffset();
2509 // Align stack specially for tail calls.
2510 if (FuncIsMadeTailCallSafe(CallConv,
2511 MF.getTarget().Options.GuaranteedTailCallOpt))
2512 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2514 // If the function takes variable number of arguments, make a frame index for
2515 // the start of the first vararg value... for expansion of llvm.va_start. We
2516 // can skip this if there are no va_start calls.
2517 if (MFI->hasVAStart() &&
2518 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2519 CallConv != CallingConv::X86_ThisCall))) {
2520 FuncInfo->setVarArgsFrameIndex(
2521 MFI->CreateFixedObject(1, StackSize, true));
2524 // 64-bit calling conventions support varargs and register parameters, so we
2525 // have to do extra work to spill them in the prologue or forward them to
2527 if (Is64Bit && isVarArg &&
2528 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2529 // Find the first unallocated argument registers.
2530 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2531 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2532 unsigned NumIntRegs =
2533 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2534 unsigned NumXMMRegs =
2535 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2536 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2537 "SSE register cannot be used when SSE is disabled!");
2539 // Gather all the live in physical registers.
2540 SmallVector<SDValue, 6> LiveGPRs;
2541 SmallVector<SDValue, 8> LiveXMMRegs;
2543 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2544 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2546 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2548 if (!ArgXMMs.empty()) {
2549 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2550 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2551 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2552 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2553 LiveXMMRegs.push_back(
2554 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2558 // Store them to the va_list returned by va_start.
2559 if (MFI->hasVAStart()) {
2561 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2562 // Get to the caller-allocated home save location. Add 8 to account
2563 // for the return address.
2564 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2565 FuncInfo->setRegSaveFrameIndex(
2566 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2567 // Fixup to set vararg frame on shadow area (4 x i64).
2569 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2571 // For X86-64, if there are vararg parameters that are passed via
2572 // registers, then we must store them to their spots on the stack so
2573 // they may be loaded by deferencing the result of va_next.
2574 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2575 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2576 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2577 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2580 // Store the integer parameter registers.
2581 SmallVector<SDValue, 8> MemOps;
2582 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2584 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2585 for (SDValue Val : LiveGPRs) {
2586 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2587 DAG.getIntPtrConstant(Offset));
2589 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2590 MachinePointerInfo::getFixedStack(
2591 FuncInfo->getRegSaveFrameIndex(), Offset),
2593 MemOps.push_back(Store);
2597 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2598 // Now store the XMM (fp + vector) parameter registers.
2599 SmallVector<SDValue, 12> SaveXMMOps;
2600 SaveXMMOps.push_back(Chain);
2601 SaveXMMOps.push_back(ALVal);
2602 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2603 FuncInfo->getRegSaveFrameIndex()));
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getVarArgsFPOffset()));
2606 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2608 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2609 MVT::Other, SaveXMMOps));
2612 if (!MemOps.empty())
2613 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2615 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2616 // to the liveout set on a musttail call.
2617 assert(MFI->hasMustTailInVarArgFunc());
2618 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2619 typedef X86MachineFunctionInfo::Forward Forward;
2621 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2623 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2624 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2625 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2628 if (!ArgXMMs.empty()) {
2630 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2631 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2632 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2634 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2636 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2639 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2645 // Some CCs need callee pop.
2646 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2647 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2648 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2650 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2651 // If this is an sret function, the return should pop the hidden pointer.
2652 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2653 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2654 argsAreStructReturn(Ins) == StackStructReturn)
2655 FuncInfo->setBytesToPopOnReturn(4);
2659 // RegSaveFrameIndex is X86-64 only.
2660 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2661 if (CallConv == CallingConv::X86_FastCall ||
2662 CallConv == CallingConv::X86_ThisCall)
2663 // fastcc functions can't have varargs.
2664 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2667 FuncInfo->setArgumentStackSize(StackSize);
2673 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2674 SDValue StackPtr, SDValue Arg,
2675 SDLoc dl, SelectionDAG &DAG,
2676 const CCValAssign &VA,
2677 ISD::ArgFlagsTy Flags) const {
2678 unsigned LocMemOffset = VA.getLocMemOffset();
2679 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2680 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2681 if (Flags.isByVal())
2682 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2684 return DAG.getStore(Chain, dl, Arg, PtrOff,
2685 MachinePointerInfo::getStack(LocMemOffset),
2689 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2690 /// optimization is performed and it is required.
2692 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2693 SDValue &OutRetAddr, SDValue Chain,
2694 bool IsTailCall, bool Is64Bit,
2695 int FPDiff, SDLoc dl) const {
2696 // Adjust the Return address stack slot.
2697 EVT VT = getPointerTy();
2698 OutRetAddr = getReturnAddressFrameIndex(DAG);
2700 // Load the "old" Return address.
2701 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2702 false, false, false, 0);
2703 return SDValue(OutRetAddr.getNode(), 1);
2706 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2707 /// optimization is performed and it is required (FPDiff!=0).
2708 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2709 SDValue Chain, SDValue RetAddrFrIdx,
2710 EVT PtrVT, unsigned SlotSize,
2711 int FPDiff, SDLoc dl) {
2712 // Store the return address to the appropriate stack slot.
2713 if (!FPDiff) return Chain;
2714 // Calculate the new stack slot for the return address.
2715 int NewReturnAddrFI =
2716 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2718 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2719 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2720 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2726 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2727 SmallVectorImpl<SDValue> &InVals) const {
2728 SelectionDAG &DAG = CLI.DAG;
2730 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2731 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2732 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2733 SDValue Chain = CLI.Chain;
2734 SDValue Callee = CLI.Callee;
2735 CallingConv::ID CallConv = CLI.CallConv;
2736 bool &isTailCall = CLI.IsTailCall;
2737 bool isVarArg = CLI.IsVarArg;
2739 MachineFunction &MF = DAG.getMachineFunction();
2740 bool Is64Bit = Subtarget->is64Bit();
2741 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2742 StructReturnType SR = callIsStructReturn(Outs);
2743 bool IsSibcall = false;
2744 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2746 if (MF.getTarget().Options.DisableTailCalls)
2749 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2751 // Force this to be a tail call. The verifier rules are enough to ensure
2752 // that we can lower this successfully without moving the return address
2755 } else if (isTailCall) {
2756 // Check if it's really possible to do a tail call.
2757 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2758 isVarArg, SR != NotStructReturn,
2759 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2760 Outs, OutVals, Ins, DAG);
2762 // Sibcalls are automatically detected tailcalls which do not require
2764 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2771 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2772 "Var args not supported with calling convention fastcc, ghc or hipe");
2774 // Analyze operands of the call, assigning locations to each operand.
2775 SmallVector<CCValAssign, 16> ArgLocs;
2776 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2778 // Allocate shadow area for Win64
2780 CCInfo.AllocateStack(32, 8);
2782 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2784 // Get a count of how many bytes are to be pushed on the stack.
2785 unsigned NumBytes = CCInfo.getNextStackOffset();
2787 // This is a sibcall. The memory operands are available in caller's
2788 // own caller's stack.
2790 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2791 IsTailCallConvention(CallConv))
2792 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2795 if (isTailCall && !IsSibcall && !IsMustTail) {
2796 // Lower arguments at fp - stackoffset + fpdiff.
2797 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2799 FPDiff = NumBytesCallerPushed - NumBytes;
2801 // Set the delta of movement of the returnaddr stackslot.
2802 // But only set if delta is greater than previous delta.
2803 if (FPDiff < X86Info->getTCReturnAddrDelta())
2804 X86Info->setTCReturnAddrDelta(FPDiff);
2807 unsigned NumBytesToPush = NumBytes;
2808 unsigned NumBytesToPop = NumBytes;
2810 // If we have an inalloca argument, all stack space has already been allocated
2811 // for us and be right at the top of the stack. We don't support multiple
2812 // arguments passed in memory when using inalloca.
2813 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2815 if (!ArgLocs.back().isMemLoc())
2816 report_fatal_error("cannot use inalloca attribute on a register "
2818 if (ArgLocs.back().getLocMemOffset() != 0)
2819 report_fatal_error("any parameter with the inalloca attribute must be "
2820 "the only memory argument");
2824 Chain = DAG.getCALLSEQ_START(
2825 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2827 SDValue RetAddrFrIdx;
2828 // Load return address for tail calls.
2829 if (isTailCall && FPDiff)
2830 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2831 Is64Bit, FPDiff, dl);
2833 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2834 SmallVector<SDValue, 8> MemOpChains;
2837 // Walk the register/memloc assignments, inserting copies/loads. In the case
2838 // of tail call optimization arguments are handle later.
2839 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2840 DAG.getSubtarget().getRegisterInfo());
2841 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2842 // Skip inalloca arguments, they have already been written.
2843 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2844 if (Flags.isInAlloca())
2847 CCValAssign &VA = ArgLocs[i];
2848 EVT RegVT = VA.getLocVT();
2849 SDValue Arg = OutVals[i];
2850 bool isByVal = Flags.isByVal();
2852 // Promote the value if needed.
2853 switch (VA.getLocInfo()) {
2854 default: llvm_unreachable("Unknown loc info!");
2855 case CCValAssign::Full: break;
2856 case CCValAssign::SExt:
2857 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2859 case CCValAssign::ZExt:
2860 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2862 case CCValAssign::AExt:
2863 if (RegVT.is128BitVector()) {
2864 // Special case: passing MMX values in XMM registers.
2865 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2866 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2867 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2869 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2871 case CCValAssign::BCvt:
2872 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2874 case CCValAssign::Indirect: {
2875 // Store the argument.
2876 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2877 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2878 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2879 MachinePointerInfo::getFixedStack(FI),
2886 if (VA.isRegLoc()) {
2887 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2888 if (isVarArg && IsWin64) {
2889 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2890 // shadow reg if callee is a varargs function.
2891 unsigned ShadowReg = 0;
2892 switch (VA.getLocReg()) {
2893 case X86::XMM0: ShadowReg = X86::RCX; break;
2894 case X86::XMM1: ShadowReg = X86::RDX; break;
2895 case X86::XMM2: ShadowReg = X86::R8; break;
2896 case X86::XMM3: ShadowReg = X86::R9; break;
2899 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2901 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2902 assert(VA.isMemLoc());
2903 if (!StackPtr.getNode())
2904 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2906 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2907 dl, DAG, VA, Flags));
2911 if (!MemOpChains.empty())
2912 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2914 if (Subtarget->isPICStyleGOT()) {
2915 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2918 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2919 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2921 // If we are tail calling and generating PIC/GOT style code load the
2922 // address of the callee into ECX. The value in ecx is used as target of
2923 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2924 // for tail calls on PIC/GOT architectures. Normally we would just put the
2925 // address of GOT into ebx and then call target@PLT. But for tail calls
2926 // ebx would be restored (since ebx is callee saved) before jumping to the
2929 // Note: The actual moving to ECX is done further down.
2930 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2931 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2932 !G->getGlobal()->hasProtectedVisibility())
2933 Callee = LowerGlobalAddress(Callee, DAG);
2934 else if (isa<ExternalSymbolSDNode>(Callee))
2935 Callee = LowerExternalSymbol(Callee, DAG);
2939 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2940 // From AMD64 ABI document:
2941 // For calls that may call functions that use varargs or stdargs
2942 // (prototype-less calls or calls to functions containing ellipsis (...) in
2943 // the declaration) %al is used as hidden argument to specify the number
2944 // of SSE registers used. The contents of %al do not need to match exactly
2945 // the number of registers, but must be an ubound on the number of SSE
2946 // registers used and is in the range 0 - 8 inclusive.
2948 // Count the number of XMM registers allocated.
2949 static const MCPhysReg XMMArgRegs[] = {
2950 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2951 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2953 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2954 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2955 && "SSE registers cannot be used when SSE is disabled");
2957 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2958 DAG.getConstant(NumXMMRegs, MVT::i8)));
2961 if (Is64Bit && isVarArg && IsMustTail) {
2962 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2963 for (const auto &F : Forwards) {
2964 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2965 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2969 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2970 // don't need this because the eligibility check rejects calls that require
2971 // shuffling arguments passed in memory.
2972 if (!IsSibcall && isTailCall) {
2973 // Force all the incoming stack arguments to be loaded from the stack
2974 // before any new outgoing arguments are stored to the stack, because the
2975 // outgoing stack slots may alias the incoming argument stack slots, and
2976 // the alias isn't otherwise explicit. This is slightly more conservative
2977 // than necessary, because it means that each store effectively depends
2978 // on every argument instead of just those arguments it would clobber.
2979 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2981 SmallVector<SDValue, 8> MemOpChains2;
2984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2985 CCValAssign &VA = ArgLocs[i];
2988 assert(VA.isMemLoc());
2989 SDValue Arg = OutVals[i];
2990 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2991 // Skip inalloca arguments. They don't require any work.
2992 if (Flags.isInAlloca())
2994 // Create frame index.
2995 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2996 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2997 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2998 FIN = DAG.getFrameIndex(FI, getPointerTy());
3000 if (Flags.isByVal()) {
3001 // Copy relative to framepointer.
3002 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3003 if (!StackPtr.getNode())
3004 StackPtr = DAG.getCopyFromReg(Chain, dl,
3005 RegInfo->getStackRegister(),
3007 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3009 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3013 // Store relative to framepointer.
3014 MemOpChains2.push_back(
3015 DAG.getStore(ArgChain, dl, Arg, FIN,
3016 MachinePointerInfo::getFixedStack(FI),
3021 if (!MemOpChains2.empty())
3022 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3024 // Store the return address to the appropriate stack slot.
3025 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3026 getPointerTy(), RegInfo->getSlotSize(),
3030 // Build a sequence of copy-to-reg nodes chained together with token chain
3031 // and flag operands which copy the outgoing args into registers.
3033 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3034 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3035 RegsToPass[i].second, InFlag);
3036 InFlag = Chain.getValue(1);
3039 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3040 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3041 // In the 64-bit large code model, we have to make all calls
3042 // through a register, since the call instruction's 32-bit
3043 // pc-relative offset may not be large enough to hold the whole
3045 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3046 // If the callee is a GlobalAddress node (quite common, every direct call
3047 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3050 // We should use extra load for direct calls to dllimported functions in
3052 const GlobalValue *GV = G->getGlobal();
3053 if (!GV->hasDLLImportStorageClass()) {
3054 unsigned char OpFlags = 0;
3055 bool ExtraLoad = false;
3056 unsigned WrapperKind = ISD::DELETED_NODE;
3058 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3059 // external symbols most go through the PLT in PIC mode. If the symbol
3060 // has hidden or protected visibility, or if it is static or local, then
3061 // we don't need to use the PLT - we can directly call it.
3062 if (Subtarget->isTargetELF() &&
3063 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3064 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3065 OpFlags = X86II::MO_PLT;
3066 } else if (Subtarget->isPICStyleStubAny() &&
3067 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3068 (!Subtarget->getTargetTriple().isMacOSX() ||
3069 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3070 // PC-relative references to external symbols should go through $stub,
3071 // unless we're building with the leopard linker or later, which
3072 // automatically synthesizes these stubs.
3073 OpFlags = X86II::MO_DARWIN_STUB;
3074 } else if (Subtarget->isPICStyleRIPRel() &&
3075 isa<Function>(GV) &&
3076 cast<Function>(GV)->getAttributes().
3077 hasAttribute(AttributeSet::FunctionIndex,
3078 Attribute::NonLazyBind)) {
3079 // If the function is marked as non-lazy, generate an indirect call
3080 // which loads from the GOT directly. This avoids runtime overhead
3081 // at the cost of eager binding (and one extra byte of encoding).
3082 OpFlags = X86II::MO_GOTPCREL;
3083 WrapperKind = X86ISD::WrapperRIP;
3087 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3088 G->getOffset(), OpFlags);
3090 // Add a wrapper if needed.
3091 if (WrapperKind != ISD::DELETED_NODE)
3092 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3093 // Add extra indirection if needed.
3095 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3096 MachinePointerInfo::getGOT(),
3097 false, false, false, 0);
3099 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3100 unsigned char OpFlags = 0;
3102 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3103 // external symbols should go through the PLT.
3104 if (Subtarget->isTargetELF() &&
3105 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (!Subtarget->getTargetTriple().isMacOSX() ||
3109 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3110 // PC-relative references to external symbols should go through $stub,
3111 // unless we're building with the leopard linker or later, which
3112 // automatically synthesizes these stubs.
3113 OpFlags = X86II::MO_DARWIN_STUB;
3116 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3118 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3119 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3120 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3123 // Returns a chain & a flag for retval copy to use.
3124 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3125 SmallVector<SDValue, 8> Ops;
3127 if (!IsSibcall && isTailCall) {
3128 Chain = DAG.getCALLSEQ_END(Chain,
3129 DAG.getIntPtrConstant(NumBytesToPop, true),
3130 DAG.getIntPtrConstant(0, true), InFlag, dl);
3131 InFlag = Chain.getValue(1);
3134 Ops.push_back(Chain);
3135 Ops.push_back(Callee);
3138 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3140 // Add argument registers to the end of the list so that they are known live
3142 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3143 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3144 RegsToPass[i].second.getValueType()));
3146 // Add a register mask operand representing the call-preserved registers.
3147 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3148 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3149 assert(Mask && "Missing call preserved mask for calling convention");
3150 Ops.push_back(DAG.getRegisterMask(Mask));
3152 if (InFlag.getNode())
3153 Ops.push_back(InFlag);
3157 //// If this is the first return lowered for this function, add the regs
3158 //// to the liveout set for the function.
3159 // This isn't right, although it's probably harmless on x86; liveouts
3160 // should be computed from returns not tail calls. Consider a void
3161 // function making a tail call to a function returning int.
3162 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3165 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3166 InFlag = Chain.getValue(1);
3168 // Create the CALLSEQ_END node.
3169 unsigned NumBytesForCalleeToPop;
3170 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3171 DAG.getTarget().Options.GuaranteedTailCallOpt))
3172 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3173 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3174 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3175 SR == StackStructReturn)
3176 // If this is a call to a struct-return function, the callee
3177 // pops the hidden struct pointer, so we have to push it back.
3178 // This is common for Darwin/X86, Linux & Mingw32 targets.
3179 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3180 NumBytesForCalleeToPop = 4;
3182 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3184 // Returns a flag for retval copy to use.
3186 Chain = DAG.getCALLSEQ_END(Chain,
3187 DAG.getIntPtrConstant(NumBytesToPop, true),
3188 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3191 InFlag = Chain.getValue(1);
3194 // Handle result values, copying them out of physregs into vregs that we
3196 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3197 Ins, dl, DAG, InVals);
3200 //===----------------------------------------------------------------------===//
3201 // Fast Calling Convention (tail call) implementation
3202 //===----------------------------------------------------------------------===//
3204 // Like std call, callee cleans arguments, convention except that ECX is
3205 // reserved for storing the tail called function address. Only 2 registers are
3206 // free for argument passing (inreg). Tail call optimization is performed
3208 // * tailcallopt is enabled
3209 // * caller/callee are fastcc
3210 // On X86_64 architecture with GOT-style position independent code only local
3211 // (within module) calls are supported at the moment.
3212 // To keep the stack aligned according to platform abi the function
3213 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3214 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3215 // If a tail called function callee has more arguments than the caller the
3216 // caller needs to make sure that there is room to move the RETADDR to. This is
3217 // achieved by reserving an area the size of the argument delta right after the
3218 // original RETADDR, but before the saved framepointer or the spilled registers
3219 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3231 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3232 /// for a 16 byte align requirement.
3234 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3235 SelectionDAG& DAG) const {
3236 MachineFunction &MF = DAG.getMachineFunction();
3237 const TargetMachine &TM = MF.getTarget();
3238 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3239 TM.getSubtargetImpl()->getRegisterInfo());
3240 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3241 unsigned StackAlignment = TFI.getStackAlignment();
3242 uint64_t AlignMask = StackAlignment - 1;
3243 int64_t Offset = StackSize;
3244 unsigned SlotSize = RegInfo->getSlotSize();
3245 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3246 // Number smaller than 12 so just add the difference.
3247 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3249 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3250 Offset = ((~AlignMask) & Offset) + StackAlignment +
3251 (StackAlignment-SlotSize);
3256 /// MatchingStackOffset - Return true if the given stack call argument is
3257 /// already available in the same position (relatively) of the caller's
3258 /// incoming argument stack.
3260 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3261 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3262 const X86InstrInfo *TII) {
3263 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3265 if (Arg.getOpcode() == ISD::CopyFromReg) {
3266 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3267 if (!TargetRegisterInfo::isVirtualRegister(VR))
3269 MachineInstr *Def = MRI->getVRegDef(VR);
3272 if (!Flags.isByVal()) {
3273 if (!TII->isLoadFromStackSlot(Def, FI))
3276 unsigned Opcode = Def->getOpcode();
3277 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3278 Def->getOperand(1).isFI()) {
3279 FI = Def->getOperand(1).getIndex();
3280 Bytes = Flags.getByValSize();
3284 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3285 if (Flags.isByVal())
3286 // ByVal argument is passed in as a pointer but it's now being
3287 // dereferenced. e.g.
3288 // define @foo(%struct.X* %A) {
3289 // tail call @bar(%struct.X* byval %A)
3292 SDValue Ptr = Ld->getBasePtr();
3293 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3296 FI = FINode->getIndex();
3297 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3298 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3299 FI = FINode->getIndex();
3300 Bytes = Flags.getByValSize();
3304 assert(FI != INT_MAX);
3305 if (!MFI->isFixedObjectIndex(FI))
3307 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3310 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3311 /// for tail call optimization. Targets which want to do tail call
3312 /// optimization should implement this function.
3314 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3315 CallingConv::ID CalleeCC,
3317 bool isCalleeStructRet,
3318 bool isCallerStructRet,
3320 const SmallVectorImpl<ISD::OutputArg> &Outs,
3321 const SmallVectorImpl<SDValue> &OutVals,
3322 const SmallVectorImpl<ISD::InputArg> &Ins,
3323 SelectionDAG &DAG) const {
3324 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3327 // If -tailcallopt is specified, make fastcc functions tail-callable.
3328 const MachineFunction &MF = DAG.getMachineFunction();
3329 const Function *CallerF = MF.getFunction();
3331 // If the function return type is x86_fp80 and the callee return type is not,
3332 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3333 // perform a tailcall optimization here.
3334 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3337 CallingConv::ID CallerCC = CallerF->getCallingConv();
3338 bool CCMatch = CallerCC == CalleeCC;
3339 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3340 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3342 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3343 if (IsTailCallConvention(CalleeCC) && CCMatch)
3348 // Look for obvious safe cases to perform tail call optimization that do not
3349 // require ABI changes. This is what gcc calls sibcall.
3351 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3352 // emit a special epilogue.
3353 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3354 DAG.getSubtarget().getRegisterInfo());
3355 if (RegInfo->needsStackRealignment(MF))
3358 // Also avoid sibcall optimization if either caller or callee uses struct
3359 // return semantics.
3360 if (isCalleeStructRet || isCallerStructRet)
3363 // An stdcall/thiscall caller is expected to clean up its arguments; the
3364 // callee isn't going to do that.
3365 // FIXME: this is more restrictive than needed. We could produce a tailcall
3366 // when the stack adjustment matches. For example, with a thiscall that takes
3367 // only one argument.
3368 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3369 CallerCC == CallingConv::X86_ThisCall))
3372 // Do not sibcall optimize vararg calls unless all arguments are passed via
3374 if (isVarArg && !Outs.empty()) {
3376 // Optimizing for varargs on Win64 is unlikely to be safe without
3377 // additional testing.
3378 if (IsCalleeWin64 || IsCallerWin64)
3381 SmallVector<CCValAssign, 16> ArgLocs;
3382 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3385 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3387 if (!ArgLocs[i].isRegLoc())
3391 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3392 // stack. Therefore, if it's not used by the call it is not safe to optimize
3393 // this into a sibcall.
3394 bool Unused = false;
3395 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3402 SmallVector<CCValAssign, 16> RVLocs;
3403 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3405 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3406 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3407 CCValAssign &VA = RVLocs[i];
3408 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3413 // If the calling conventions do not match, then we'd better make sure the
3414 // results are returned in the same way as what the caller expects.
3416 SmallVector<CCValAssign, 16> RVLocs1;
3417 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3419 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3421 SmallVector<CCValAssign, 16> RVLocs2;
3422 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3424 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3426 if (RVLocs1.size() != RVLocs2.size())
3428 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3429 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3431 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3433 if (RVLocs1[i].isRegLoc()) {
3434 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3437 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3443 // If the callee takes no arguments then go on to check the results of the
3445 if (!Outs.empty()) {
3446 // Check if stack adjustment is needed. For now, do not do this if any
3447 // argument is passed on the stack.
3448 SmallVector<CCValAssign, 16> ArgLocs;
3449 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3452 // Allocate shadow area for Win64
3454 CCInfo.AllocateStack(32, 8);
3456 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3457 if (CCInfo.getNextStackOffset()) {
3458 MachineFunction &MF = DAG.getMachineFunction();
3459 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3462 // Check if the arguments are already laid out in the right way as
3463 // the caller's fixed stack objects.
3464 MachineFrameInfo *MFI = MF.getFrameInfo();
3465 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3466 const X86InstrInfo *TII =
3467 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3468 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3469 CCValAssign &VA = ArgLocs[i];
3470 SDValue Arg = OutVals[i];
3471 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3472 if (VA.getLocInfo() == CCValAssign::Indirect)
3474 if (!VA.isRegLoc()) {
3475 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3482 // If the tailcall address may be in a register, then make sure it's
3483 // possible to register allocate for it. In 32-bit, the call address can
3484 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3485 // callee-saved registers are restored. These happen to be the same
3486 // registers used to pass 'inreg' arguments so watch out for those.
3487 if (!Subtarget->is64Bit() &&
3488 ((!isa<GlobalAddressSDNode>(Callee) &&
3489 !isa<ExternalSymbolSDNode>(Callee)) ||
3490 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3491 unsigned NumInRegs = 0;
3492 // In PIC we need an extra register to formulate the address computation
3494 unsigned MaxInRegs =
3495 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3497 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3498 CCValAssign &VA = ArgLocs[i];
3501 unsigned Reg = VA.getLocReg();
3504 case X86::EAX: case X86::EDX: case X86::ECX:
3505 if (++NumInRegs == MaxInRegs)
3517 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3518 const TargetLibraryInfo *libInfo) const {
3519 return X86::createFastISel(funcInfo, libInfo);
3522 //===----------------------------------------------------------------------===//
3523 // Other Lowering Hooks
3524 //===----------------------------------------------------------------------===//
3526 static bool MayFoldLoad(SDValue Op) {
3527 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3530 static bool MayFoldIntoStore(SDValue Op) {
3531 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3534 static bool isTargetShuffle(unsigned Opcode) {
3536 default: return false;
3537 case X86ISD::BLENDI:
3538 case X86ISD::PSHUFB:
3539 case X86ISD::PSHUFD:
3540 case X86ISD::PSHUFHW:
3541 case X86ISD::PSHUFLW:
3543 case X86ISD::PALIGNR:
3544 case X86ISD::MOVLHPS:
3545 case X86ISD::MOVLHPD:
3546 case X86ISD::MOVHLPS:
3547 case X86ISD::MOVLPS:
3548 case X86ISD::MOVLPD:
3549 case X86ISD::MOVSHDUP:
3550 case X86ISD::MOVSLDUP:
3551 case X86ISD::MOVDDUP:
3554 case X86ISD::UNPCKL:
3555 case X86ISD::UNPCKH:
3556 case X86ISD::VPERMILPI:
3557 case X86ISD::VPERM2X128:
3558 case X86ISD::VPERMI:
3563 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3564 SDValue V1, SelectionDAG &DAG) {
3566 default: llvm_unreachable("Unknown x86 shuffle node");
3567 case X86ISD::MOVSHDUP:
3568 case X86ISD::MOVSLDUP:
3569 case X86ISD::MOVDDUP:
3570 return DAG.getNode(Opc, dl, VT, V1);
3574 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3575 SDValue V1, unsigned TargetMask,
3576 SelectionDAG &DAG) {
3578 default: llvm_unreachable("Unknown x86 shuffle node");
3579 case X86ISD::PSHUFD:
3580 case X86ISD::PSHUFHW:
3581 case X86ISD::PSHUFLW:
3582 case X86ISD::VPERMILPI:
3583 case X86ISD::VPERMI:
3584 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3588 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3589 SDValue V1, SDValue V2, unsigned TargetMask,
3590 SelectionDAG &DAG) {
3592 default: llvm_unreachable("Unknown x86 shuffle node");
3593 case X86ISD::PALIGNR:
3594 case X86ISD::VALIGN:
3596 case X86ISD::VPERM2X128:
3597 return DAG.getNode(Opc, dl, VT, V1, V2,
3598 DAG.getConstant(TargetMask, MVT::i8));
3602 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3603 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::MOVLHPS:
3607 case X86ISD::MOVLHPD:
3608 case X86ISD::MOVHLPS:
3609 case X86ISD::MOVLPS:
3610 case X86ISD::MOVLPD:
3613 case X86ISD::UNPCKL:
3614 case X86ISD::UNPCKH:
3615 return DAG.getNode(Opc, dl, VT, V1, V2);
3619 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3620 MachineFunction &MF = DAG.getMachineFunction();
3621 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3622 DAG.getSubtarget().getRegisterInfo());
3623 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3624 int ReturnAddrIndex = FuncInfo->getRAIndex();
3626 if (ReturnAddrIndex == 0) {
3627 // Set up a frame object for the return address.
3628 unsigned SlotSize = RegInfo->getSlotSize();
3629 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3632 FuncInfo->setRAIndex(ReturnAddrIndex);
3635 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3638 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3639 bool hasSymbolicDisplacement) {
3640 // Offset should fit into 32 bit immediate field.
3641 if (!isInt<32>(Offset))
3644 // If we don't have a symbolic displacement - we don't have any extra
3646 if (!hasSymbolicDisplacement)
3649 // FIXME: Some tweaks might be needed for medium code model.
3650 if (M != CodeModel::Small && M != CodeModel::Kernel)
3653 // For small code model we assume that latest object is 16MB before end of 31
3654 // bits boundary. We may also accept pretty large negative constants knowing
3655 // that all objects are in the positive half of address space.
3656 if (M == CodeModel::Small && Offset < 16*1024*1024)
3659 // For kernel code model we know that all object resist in the negative half
3660 // of 32bits address space. We may not accept negative offsets, since they may
3661 // be just off and we may accept pretty large positive ones.
3662 if (M == CodeModel::Kernel && Offset > 0)
3668 /// isCalleePop - Determines whether the callee is required to pop its
3669 /// own arguments. Callee pop is necessary to support tail calls.
3670 bool X86::isCalleePop(CallingConv::ID CallingConv,
3671 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3672 switch (CallingConv) {
3675 case CallingConv::X86_StdCall:
3676 case CallingConv::X86_FastCall:
3677 case CallingConv::X86_ThisCall:
3679 case CallingConv::Fast:
3680 case CallingConv::GHC:
3681 case CallingConv::HiPE:
3688 /// \brief Return true if the condition is an unsigned comparison operation.
3689 static bool isX86CCUnsigned(unsigned X86CC) {
3691 default: llvm_unreachable("Invalid integer condition!");
3692 case X86::COND_E: return true;
3693 case X86::COND_G: return false;
3694 case X86::COND_GE: return false;
3695 case X86::COND_L: return false;
3696 case X86::COND_LE: return false;
3697 case X86::COND_NE: return true;
3698 case X86::COND_B: return true;
3699 case X86::COND_A: return true;
3700 case X86::COND_BE: return true;
3701 case X86::COND_AE: return true;
3703 llvm_unreachable("covered switch fell through?!");
3706 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3707 /// specific condition code, returning the condition code and the LHS/RHS of the
3708 /// comparison to make.
3709 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3710 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3713 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3714 // X > -1 -> X == 0, jump !sign.
3715 RHS = DAG.getConstant(0, RHS.getValueType());
3716 return X86::COND_NS;
3718 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3719 // X < 0 -> X == 0, jump on sign.
3722 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3724 RHS = DAG.getConstant(0, RHS.getValueType());
3725 return X86::COND_LE;
3729 switch (SetCCOpcode) {
3730 default: llvm_unreachable("Invalid integer condition!");
3731 case ISD::SETEQ: return X86::COND_E;
3732 case ISD::SETGT: return X86::COND_G;
3733 case ISD::SETGE: return X86::COND_GE;
3734 case ISD::SETLT: return X86::COND_L;
3735 case ISD::SETLE: return X86::COND_LE;
3736 case ISD::SETNE: return X86::COND_NE;
3737 case ISD::SETULT: return X86::COND_B;
3738 case ISD::SETUGT: return X86::COND_A;
3739 case ISD::SETULE: return X86::COND_BE;
3740 case ISD::SETUGE: return X86::COND_AE;
3744 // First determine if it is required or is profitable to flip the operands.
3746 // If LHS is a foldable load, but RHS is not, flip the condition.
3747 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3748 !ISD::isNON_EXTLoad(RHS.getNode())) {
3749 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3750 std::swap(LHS, RHS);
3753 switch (SetCCOpcode) {
3759 std::swap(LHS, RHS);
3763 // On a floating point condition, the flags are set as follows:
3765 // 0 | 0 | 0 | X > Y
3766 // 0 | 0 | 1 | X < Y
3767 // 1 | 0 | 0 | X == Y
3768 // 1 | 1 | 1 | unordered
3769 switch (SetCCOpcode) {
3770 default: llvm_unreachable("Condcode should be pre-legalized away");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETOLT: // flipped
3775 case ISD::SETGT: return X86::COND_A;
3776 case ISD::SETOLE: // flipped
3778 case ISD::SETGE: return X86::COND_AE;
3779 case ISD::SETUGT: // flipped
3781 case ISD::SETLT: return X86::COND_B;
3782 case ISD::SETUGE: // flipped
3784 case ISD::SETLE: return X86::COND_BE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETUO: return X86::COND_P;
3788 case ISD::SETO: return X86::COND_NP;
3790 case ISD::SETUNE: return X86::COND_INVALID;
3794 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3795 /// code. Current x86 isa includes the following FP cmov instructions:
3796 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3797 static bool hasFPCMov(unsigned X86CC) {
3813 /// isFPImmLegal - Returns true if the target can instruction select the
3814 /// specified FP immediate natively. If false, the legalizer will
3815 /// materialize the FP immediate as a load from a constant pool.
3816 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3817 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3818 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 /// \brief Returns true if it is beneficial to convert a load of a constant
3825 /// to just the constant itself.
3826 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3828 assert(Ty->isIntegerTy());
3830 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3831 if (BitSize == 0 || BitSize > 64)
3836 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3837 /// the specified range (L, H].
3838 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3839 return (Val < 0) || (Val >= Low && Val < Hi);
3842 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3843 /// specified value.
3844 static bool isUndefOrEqual(int Val, int CmpVal) {
3845 return (Val < 0 || Val == CmpVal);
3848 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3849 /// from position Pos and ending in Pos+Size, falls within the specified
3850 /// sequential range (L, L+Pos]. or is undef.
3851 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3852 unsigned Pos, unsigned Size, int Low) {
3853 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3854 if (!isUndefOrEqual(Mask[i], Low))
3859 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3860 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3861 /// operand - by default will match for first operand.
3862 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3863 bool TestSecondOperand = false) {
3864 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3865 VT != MVT::v2f64 && VT != MVT::v2i64)
3868 unsigned NumElems = VT.getVectorNumElements();
3869 unsigned Lo = TestSecondOperand ? NumElems : 0;
3870 unsigned Hi = Lo + NumElems;
3872 for (unsigned i = 0; i < NumElems; ++i)
3873 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3879 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3880 /// is suitable for input to PSHUFHW.
3881 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3882 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3885 // Lower quadword copied in order or undef.
3886 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3889 // Upper quadword shuffled.
3890 for (unsigned i = 4; i != 8; ++i)
3891 if (!isUndefOrInRange(Mask[i], 4, 8))
3894 if (VT == MVT::v16i16) {
3895 // Lower quadword copied in order or undef.
3896 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3899 // Upper quadword shuffled.
3900 for (unsigned i = 12; i != 16; ++i)
3901 if (!isUndefOrInRange(Mask[i], 12, 16))
3908 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3909 /// is suitable for input to PSHUFLW.
3910 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3911 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3914 // Upper quadword copied in order.
3915 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3918 // Lower quadword shuffled.
3919 for (unsigned i = 0; i != 4; ++i)
3920 if (!isUndefOrInRange(Mask[i], 0, 4))
3923 if (VT == MVT::v16i16) {
3924 // Upper quadword copied in order.
3925 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3928 // Lower quadword shuffled.
3929 for (unsigned i = 8; i != 12; ++i)
3930 if (!isUndefOrInRange(Mask[i], 8, 12))
3937 /// \brief Return true if the mask specifies a shuffle of elements that is
3938 /// suitable for input to intralane (palignr) or interlane (valign) vector
3940 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3941 unsigned NumElts = VT.getVectorNumElements();
3942 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3943 unsigned NumLaneElts = NumElts/NumLanes;
3945 // Do not handle 64-bit element shuffles with palignr.
3946 if (NumLaneElts == 2)
3949 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3951 for (i = 0; i != NumLaneElts; ++i) {
3956 // Lane is all undef, go to next lane
3957 if (i == NumLaneElts)
3960 int Start = Mask[i+l];
3962 // Make sure its in this lane in one of the sources
3963 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3964 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3967 // If not lane 0, then we must match lane 0
3968 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3971 // Correct second source to be contiguous with first source
3972 if (Start >= (int)NumElts)
3973 Start -= NumElts - NumLaneElts;
3975 // Make sure we're shifting in the right direction.
3976 if (Start <= (int)(i+l))
3981 // Check the rest of the elements to see if they are consecutive.
3982 for (++i; i != NumLaneElts; ++i) {
3983 int Idx = Mask[i+l];
3985 // Make sure its in this lane
3986 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3987 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3990 // If not lane 0, then we must match lane 0
3991 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3994 if (Idx >= (int)NumElts)
3995 Idx -= NumElts - NumLaneElts;
3997 if (!isUndefOrEqual(Idx, Start+i))
4006 /// \brief Return true if the node specifies a shuffle of elements that is
4007 /// suitable for input to PALIGNR.
4008 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4009 const X86Subtarget *Subtarget) {
4010 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4011 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4012 VT.is512BitVector())
4013 // FIXME: Add AVX512BW.
4016 return isAlignrMask(Mask, VT, false);
4019 /// \brief Return true if the node specifies a shuffle of elements that is
4020 /// suitable for input to VALIGN.
4021 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4022 const X86Subtarget *Subtarget) {
4023 // FIXME: Add AVX512VL.
4024 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4026 return isAlignrMask(Mask, VT, true);
4029 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4030 /// the two vector operands have swapped position.
4031 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4032 unsigned NumElems) {
4033 for (unsigned i = 0; i != NumElems; ++i) {
4037 else if (idx < (int)NumElems)
4038 Mask[i] = idx + NumElems;
4040 Mask[i] = idx - NumElems;
4044 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4045 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4046 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4047 /// reverse of what x86 shuffles want.
4048 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4050 unsigned NumElems = VT.getVectorNumElements();
4051 unsigned NumLanes = VT.getSizeInBits()/128;
4052 unsigned NumLaneElems = NumElems/NumLanes;
4054 if (NumLaneElems != 2 && NumLaneElems != 4)
4057 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4058 bool symetricMaskRequired =
4059 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4061 // VSHUFPSY divides the resulting vector into 4 chunks.
4062 // The sources are also splitted into 4 chunks, and each destination
4063 // chunk must come from a different source chunk.
4065 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4066 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4068 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4069 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4071 // VSHUFPDY divides the resulting vector into 4 chunks.
4072 // The sources are also splitted into 4 chunks, and each destination
4073 // chunk must come from a different source chunk.
4075 // SRC1 => X3 X2 X1 X0
4076 // SRC2 => Y3 Y2 Y1 Y0
4078 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4080 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4081 unsigned HalfLaneElems = NumLaneElems/2;
4082 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4083 for (unsigned i = 0; i != NumLaneElems; ++i) {
4084 int Idx = Mask[i+l];
4085 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4086 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4088 // For VSHUFPSY, the mask of the second half must be the same as the
4089 // first but with the appropriate offsets. This works in the same way as
4090 // VPERMILPS works with masks.
4091 if (!symetricMaskRequired || Idx < 0)
4093 if (MaskVal[i] < 0) {
4094 MaskVal[i] = Idx - l;
4097 if ((signed)(Idx - l) != MaskVal[i])
4105 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4106 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4107 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4108 if (!VT.is128BitVector())
4111 unsigned NumElems = VT.getVectorNumElements();
4116 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4117 return isUndefOrEqual(Mask[0], 6) &&
4118 isUndefOrEqual(Mask[1], 7) &&
4119 isUndefOrEqual(Mask[2], 2) &&
4120 isUndefOrEqual(Mask[3], 3);
4123 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4124 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4126 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4127 if (!VT.is128BitVector())
4130 unsigned NumElems = VT.getVectorNumElements();
4135 return isUndefOrEqual(Mask[0], 2) &&
4136 isUndefOrEqual(Mask[1], 3) &&
4137 isUndefOrEqual(Mask[2], 2) &&
4138 isUndefOrEqual(Mask[3], 3);
4141 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4142 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4143 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4144 if (!VT.is128BitVector())
4147 unsigned NumElems = VT.getVectorNumElements();
4149 if (NumElems != 2 && NumElems != 4)
4152 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i + NumElems))
4156 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4157 if (!isUndefOrEqual(Mask[i], i))
4163 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4164 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4165 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4166 if (!VT.is128BitVector())
4169 unsigned NumElems = VT.getVectorNumElements();
4171 if (NumElems != 2 && NumElems != 4)
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i], i))
4178 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4179 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4185 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4186 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4187 /// i. e: If all but one element come from the same vector.
4188 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4189 // TODO: Deal with AVX's VINSERTPS
4190 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4193 unsigned CorrectPosV1 = 0;
4194 unsigned CorrectPosV2 = 0;
4195 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4196 if (Mask[i] == -1) {
4204 else if (Mask[i] == i + 4)
4208 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4209 // We have 3 elements (undefs count as elements from any vector) from one
4210 // vector, and one from another.
4217 // Some special combinations that can be optimized.
4220 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4221 SelectionDAG &DAG) {
4222 MVT VT = SVOp->getSimpleValueType(0);
4225 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4228 ArrayRef<int> Mask = SVOp->getMask();
4230 // These are the special masks that may be optimized.
4231 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4232 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4233 bool MatchEvenMask = true;
4234 bool MatchOddMask = true;
4235 for (int i=0; i<8; ++i) {
4236 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4237 MatchEvenMask = false;
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4239 MatchOddMask = false;
4242 if (!MatchEvenMask && !MatchOddMask)
4245 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4247 SDValue Op0 = SVOp->getOperand(0);
4248 SDValue Op1 = SVOp->getOperand(1);
4250 if (MatchEvenMask) {
4251 // Shift the second operand right to 32 bits.
4252 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4253 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4255 // Shift the first operand left to 32 bits.
4256 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4257 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4259 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4260 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4263 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4264 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4265 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4266 bool HasInt256, bool V2IsSplat = false) {
4268 assert(VT.getSizeInBits() >= 128 &&
4269 "Unsupported vector type for unpckl");
4271 unsigned NumElts = VT.getVectorNumElements();
4272 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4273 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4276 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4277 "Unsupported vector type for unpckh");
4279 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4280 unsigned NumLanes = VT.getSizeInBits()/128;
4281 unsigned NumLaneElts = NumElts/NumLanes;
4283 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4284 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4285 int BitI = Mask[l+i];
4286 int BitI1 = Mask[l+i+1];
4287 if (!isUndefOrEqual(BitI, j))
4290 if (!isUndefOrEqual(BitI1, NumElts))
4293 if (!isUndefOrEqual(BitI1, j + NumElts))
4302 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4303 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4304 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4305 bool HasInt256, bool V2IsSplat = false) {
4306 assert(VT.getSizeInBits() >= 128 &&
4307 "Unsupported vector type for unpckh");
4309 unsigned NumElts = VT.getVectorNumElements();
4310 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4311 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4314 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4315 "Unsupported vector type for unpckh");
4317 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4318 unsigned NumLanes = VT.getSizeInBits()/128;
4319 unsigned NumLaneElts = NumElts/NumLanes;
4321 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4322 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4323 int BitI = Mask[l+i];
4324 int BitI1 = Mask[l+i+1];
4325 if (!isUndefOrEqual(BitI, j))
4328 if (isUndefOrEqual(BitI1, NumElts))
4331 if (!isUndefOrEqual(BitI1, j+NumElts))
4339 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4340 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4342 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4343 unsigned NumElts = VT.getVectorNumElements();
4344 bool Is256BitVec = VT.is256BitVector();
4346 if (VT.is512BitVector())
4348 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4349 "Unsupported vector type for unpckh");
4351 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4352 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4355 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4356 // FIXME: Need a better way to get rid of this, there's no latency difference
4357 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4358 // the former later. We should also remove the "_undef" special mask.
4359 if (NumElts == 4 && Is256BitVec)
4362 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4363 // independently on 128-bit lanes.
4364 unsigned NumLanes = VT.getSizeInBits()/128;
4365 unsigned NumLaneElts = NumElts/NumLanes;
4367 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4368 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4369 int BitI = Mask[l+i];
4370 int BitI1 = Mask[l+i+1];
4372 if (!isUndefOrEqual(BitI, j))
4374 if (!isUndefOrEqual(BitI1, j))
4382 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4383 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4385 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4386 unsigned NumElts = VT.getVectorNumElements();
4388 if (VT.is512BitVector())
4391 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4392 "Unsupported vector type for unpckh");
4394 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4395 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4398 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4399 // independently on 128-bit lanes.
4400 unsigned NumLanes = VT.getSizeInBits()/128;
4401 unsigned NumLaneElts = NumElts/NumLanes;
4403 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4404 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4405 int BitI = Mask[l+i];
4406 int BitI1 = Mask[l+i+1];
4407 if (!isUndefOrEqual(BitI, j))
4409 if (!isUndefOrEqual(BitI1, j))
4416 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4417 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4418 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4419 if (!VT.is512BitVector())
4422 unsigned NumElts = VT.getVectorNumElements();
4423 unsigned HalfSize = NumElts/2;
4424 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4425 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4430 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4431 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4439 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4440 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4441 /// MOVSD, and MOVD, i.e. setting the lowest element.
4442 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4443 if (VT.getVectorElementType().getSizeInBits() < 32)
4445 if (!VT.is128BitVector())
4448 unsigned NumElts = VT.getVectorNumElements();
4450 if (!isUndefOrEqual(Mask[0], NumElts))
4453 for (unsigned i = 1; i != NumElts; ++i)
4454 if (!isUndefOrEqual(Mask[i], i))
4460 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4461 /// as permutations between 128-bit chunks or halves. As an example: this
4463 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4464 /// The first half comes from the second half of V1 and the second half from the
4465 /// the second half of V2.
4466 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4467 if (!HasFp256 || !VT.is256BitVector())
4470 // The shuffle result is divided into half A and half B. In total the two
4471 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4472 // B must come from C, D, E or F.
4473 unsigned HalfSize = VT.getVectorNumElements()/2;
4474 bool MatchA = false, MatchB = false;
4476 // Check if A comes from one of C, D, E, F.
4477 for (unsigned Half = 0; Half != 4; ++Half) {
4478 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4484 // Check if B comes from one of C, D, E, F.
4485 for (unsigned Half = 0; Half != 4; ++Half) {
4486 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4492 return MatchA && MatchB;
4495 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4496 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4497 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4498 MVT VT = SVOp->getSimpleValueType(0);
4500 unsigned HalfSize = VT.getVectorNumElements()/2;
4502 unsigned FstHalf = 0, SndHalf = 0;
4503 for (unsigned i = 0; i < HalfSize; ++i) {
4504 if (SVOp->getMaskElt(i) > 0) {
4505 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4509 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4510 if (SVOp->getMaskElt(i) > 0) {
4511 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4516 return (FstHalf | (SndHalf << 4));
4519 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4520 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4521 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4525 unsigned NumElts = VT.getVectorNumElements();
4527 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4528 for (unsigned i = 0; i != NumElts; ++i) {
4531 Imm8 |= Mask[i] << (i*2);
4536 unsigned LaneSize = 4;
4537 SmallVector<int, 4> MaskVal(LaneSize, -1);
4539 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4540 for (unsigned i = 0; i != LaneSize; ++i) {
4541 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4545 if (MaskVal[i] < 0) {
4546 MaskVal[i] = Mask[i+l] - l;
4547 Imm8 |= MaskVal[i] << (i*2);
4550 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4557 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4558 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4559 /// Note that VPERMIL mask matching is different depending whether theunderlying
4560 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4561 /// to the same elements of the low, but to the higher half of the source.
4562 /// In VPERMILPD the two lanes could be shuffled independently of each other
4563 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4564 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4565 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4566 if (VT.getSizeInBits() < 256 || EltSize < 32)
4568 bool symetricMaskRequired = (EltSize == 32);
4569 unsigned NumElts = VT.getVectorNumElements();
4571 unsigned NumLanes = VT.getSizeInBits()/128;
4572 unsigned LaneSize = NumElts/NumLanes;
4573 // 2 or 4 elements in one lane
4575 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4576 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4577 for (unsigned i = 0; i != LaneSize; ++i) {
4578 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4580 if (symetricMaskRequired) {
4581 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4582 ExpectedMaskVal[i] = Mask[i+l] - l;
4585 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4593 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4594 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4595 /// element of vector 2 and the other elements to come from vector 1 in order.
4596 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4597 bool V2IsSplat = false, bool V2IsUndef = false) {
4598 if (!VT.is128BitVector())
4601 unsigned NumOps = VT.getVectorNumElements();
4602 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4605 if (!isUndefOrEqual(Mask[0], 0))
4608 for (unsigned i = 1; i != NumOps; ++i)
4609 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4610 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4611 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4617 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4618 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4619 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4620 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4621 const X86Subtarget *Subtarget) {
4622 if (!Subtarget->hasSSE3())
4625 unsigned NumElems = VT.getVectorNumElements();
4627 if ((VT.is128BitVector() && NumElems != 4) ||
4628 (VT.is256BitVector() && NumElems != 8) ||
4629 (VT.is512BitVector() && NumElems != 16))
4632 // "i+1" is the value the indexed mask element must have
4633 for (unsigned i = 0; i != NumElems; i += 2)
4634 if (!isUndefOrEqual(Mask[i], i+1) ||
4635 !isUndefOrEqual(Mask[i+1], i+1))
4641 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4642 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4643 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4644 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4645 const X86Subtarget *Subtarget) {
4646 if (!Subtarget->hasSSE3())
4649 unsigned NumElems = VT.getVectorNumElements();
4651 if ((VT.is128BitVector() && NumElems != 4) ||
4652 (VT.is256BitVector() && NumElems != 8) ||
4653 (VT.is512BitVector() && NumElems != 16))
4656 // "i" is the value the indexed mask element must have
4657 for (unsigned i = 0; i != NumElems; i += 2)
4658 if (!isUndefOrEqual(Mask[i], i) ||
4659 !isUndefOrEqual(Mask[i+1], i))
4665 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4666 /// specifies a shuffle of elements that is suitable for input to 256-bit
4667 /// version of MOVDDUP.
4668 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4669 if (!HasFp256 || !VT.is256BitVector())
4672 unsigned NumElts = VT.getVectorNumElements();
4676 for (unsigned i = 0; i != NumElts/2; ++i)
4677 if (!isUndefOrEqual(Mask[i], 0))
4679 for (unsigned i = NumElts/2; i != NumElts; ++i)
4680 if (!isUndefOrEqual(Mask[i], NumElts/2))
4685 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4686 /// specifies a shuffle of elements that is suitable for input to 128-bit
4687 /// version of MOVDDUP.
4688 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4689 if (!VT.is128BitVector())
4692 unsigned e = VT.getVectorNumElements() / 2;
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[i], i))
4696 for (unsigned i = 0; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[e+i], i))
4702 /// isVEXTRACTIndex - Return true if the specified
4703 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4704 /// suitable for instruction that extract 128 or 256 bit vectors
4705 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4706 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4707 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4710 // The index should be aligned on a vecWidth-bit boundary.
4712 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4714 MVT VT = N->getSimpleValueType(0);
4715 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4716 bool Result = (Index * ElSize) % vecWidth == 0;
4721 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4722 /// operand specifies a subvector insert that is suitable for input to
4723 /// insertion of 128 or 256-bit subvectors
4724 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4725 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4726 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4728 // The index should be aligned on a vecWidth-bit boundary.
4730 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4732 MVT VT = N->getSimpleValueType(0);
4733 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4734 bool Result = (Index * ElSize) % vecWidth == 0;
4739 bool X86::isVINSERT128Index(SDNode *N) {
4740 return isVINSERTIndex(N, 128);
4743 bool X86::isVINSERT256Index(SDNode *N) {
4744 return isVINSERTIndex(N, 256);
4747 bool X86::isVEXTRACT128Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 128);
4751 bool X86::isVEXTRACT256Index(SDNode *N) {
4752 return isVEXTRACTIndex(N, 256);
4755 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4756 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4757 /// Handles 128-bit and 256-bit.
4758 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4759 MVT VT = N->getSimpleValueType(0);
4761 assert((VT.getSizeInBits() >= 128) &&
4762 "Unsupported vector type for PSHUF/SHUFP");
4764 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4765 // independently on 128-bit lanes.
4766 unsigned NumElts = VT.getVectorNumElements();
4767 unsigned NumLanes = VT.getSizeInBits()/128;
4768 unsigned NumLaneElts = NumElts/NumLanes;
4770 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4771 "Only supports 2, 4 or 8 elements per lane");
4773 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4775 for (unsigned i = 0; i != NumElts; ++i) {
4776 int Elt = N->getMaskElt(i);
4777 if (Elt < 0) continue;
4778 Elt &= NumLaneElts - 1;
4779 unsigned ShAmt = (i << Shift) % 8;
4780 Mask |= Elt << ShAmt;
4786 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4787 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4788 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4789 MVT VT = N->getSimpleValueType(0);
4791 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4792 "Unsupported vector type for PSHUFHW");
4794 unsigned NumElts = VT.getVectorNumElements();
4797 for (unsigned l = 0; l != NumElts; l += 8) {
4798 // 8 nodes per lane, but we only care about the last 4.
4799 for (unsigned i = 0; i < 4; ++i) {
4800 int Elt = N->getMaskElt(l+i+4);
4801 if (Elt < 0) continue;
4802 Elt &= 0x3; // only 2-bits.
4803 Mask |= Elt << (i * 2);
4810 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4811 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4812 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4813 MVT VT = N->getSimpleValueType(0);
4815 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4816 "Unsupported vector type for PSHUFHW");
4818 unsigned NumElts = VT.getVectorNumElements();
4821 for (unsigned l = 0; l != NumElts; l += 8) {
4822 // 8 nodes per lane, but we only care about the first 4.
4823 for (unsigned i = 0; i < 4; ++i) {
4824 int Elt = N->getMaskElt(l+i);
4825 if (Elt < 0) continue;
4826 Elt &= 0x3; // only 2-bits
4827 Mask |= Elt << (i * 2);
4834 /// \brief Return the appropriate immediate to shuffle the specified
4835 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4836 /// VALIGN (if Interlane is true) instructions.
4837 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4839 MVT VT = SVOp->getSimpleValueType(0);
4840 unsigned EltSize = InterLane ? 1 :
4841 VT.getVectorElementType().getSizeInBits() >> 3;
4843 unsigned NumElts = VT.getVectorNumElements();
4844 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4845 unsigned NumLaneElts = NumElts/NumLanes;
4849 for (i = 0; i != NumElts; ++i) {
4850 Val = SVOp->getMaskElt(i);
4854 if (Val >= (int)NumElts)
4855 Val -= NumElts - NumLaneElts;
4857 assert(Val - i > 0 && "PALIGNR imm should be positive");
4858 return (Val - i) * EltSize;
4861 /// \brief Return the appropriate immediate to shuffle the specified
4862 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4863 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4864 return getShuffleAlignrImmediate(SVOp, false);
4867 /// \brief Return the appropriate immediate to shuffle the specified
4868 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4869 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4870 return getShuffleAlignrImmediate(SVOp, true);
4874 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4875 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4876 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4877 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4880 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4882 MVT VecVT = N->getOperand(0).getSimpleValueType();
4883 MVT ElVT = VecVT.getVectorElementType();
4885 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4886 return Index / NumElemsPerChunk;
4889 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4890 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4891 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4892 llvm_unreachable("Illegal insert subvector for VINSERT");
4895 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4897 MVT VecVT = N->getSimpleValueType(0);
4898 MVT ElVT = VecVT.getVectorElementType();
4900 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4901 return Index / NumElemsPerChunk;
4904 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4905 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4906 /// and VINSERTI128 instructions.
4907 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4908 return getExtractVEXTRACTImmediate(N, 128);
4911 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4912 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4913 /// and VINSERTI64x4 instructions.
4914 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4915 return getExtractVEXTRACTImmediate(N, 256);
4918 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4919 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4920 /// and VINSERTI128 instructions.
4921 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4922 return getInsertVINSERTImmediate(N, 128);
4925 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4926 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4927 /// and VINSERTI64x4 instructions.
4928 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4929 return getInsertVINSERTImmediate(N, 256);
4932 /// isZero - Returns true if Elt is a constant integer zero
4933 static bool isZero(SDValue V) {
4934 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4935 return C && C->isNullValue();
4938 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4940 bool X86::isZeroNode(SDValue Elt) {
4943 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4944 return CFP->getValueAPF().isPosZero();
4948 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4949 /// match movhlps. The lower half elements should come from upper half of
4950 /// V1 (and in order), and the upper half elements should come from the upper
4951 /// half of V2 (and in order).
4952 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4953 if (!VT.is128BitVector())
4955 if (VT.getVectorNumElements() != 4)
4957 for (unsigned i = 0, e = 2; i != e; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+2))
4960 for (unsigned i = 2; i != 4; ++i)
4961 if (!isUndefOrEqual(Mask[i], i+4))
4966 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4967 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4969 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4970 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4972 N = N->getOperand(0).getNode();
4973 if (!ISD::isNON_EXTLoad(N))
4976 *LD = cast<LoadSDNode>(N);
4980 // Test whether the given value is a vector value which will be legalized
4982 static bool WillBeConstantPoolLoad(SDNode *N) {
4983 if (N->getOpcode() != ISD::BUILD_VECTOR)
4986 // Check for any non-constant elements.
4987 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4988 switch (N->getOperand(i).getNode()->getOpcode()) {
4990 case ISD::ConstantFP:
4997 // Vectors of all-zeros and all-ones are materialized with special
4998 // instructions rather than being loaded.
4999 return !ISD::isBuildVectorAllZeros(N) &&
5000 !ISD::isBuildVectorAllOnes(N);
5003 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5004 /// match movlp{s|d}. The lower half elements should come from lower half of
5005 /// V1 (and in order), and the upper half elements should come from the upper
5006 /// half of V2 (and in order). And since V1 will become the source of the
5007 /// MOVLP, it must be either a vector load or a scalar load to vector.
5008 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5009 ArrayRef<int> Mask, MVT VT) {
5010 if (!VT.is128BitVector())
5013 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5015 // Is V2 is a vector load, don't do this transformation. We will try to use
5016 // load folding shufps op.
5017 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5020 unsigned NumElems = VT.getVectorNumElements();
5022 if (NumElems != 2 && NumElems != 4)
5024 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i))
5027 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5028 if (!isUndefOrEqual(Mask[i], i+NumElems))
5033 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5034 /// to an zero vector.
5035 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5036 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5037 SDValue V1 = N->getOperand(0);
5038 SDValue V2 = N->getOperand(1);
5039 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5040 for (unsigned i = 0; i != NumElems; ++i) {
5041 int Idx = N->getMaskElt(i);
5042 if (Idx >= (int)NumElems) {
5043 unsigned Opc = V2.getOpcode();
5044 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5046 if (Opc != ISD::BUILD_VECTOR ||
5047 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5049 } else if (Idx >= 0) {
5050 unsigned Opc = V1.getOpcode();
5051 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5053 if (Opc != ISD::BUILD_VECTOR ||
5054 !X86::isZeroNode(V1.getOperand(Idx)))
5061 /// getZeroVector - Returns a vector of specified type with all zero elements.
5063 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5064 SelectionDAG &DAG, SDLoc dl) {
5065 assert(VT.isVector() && "Expected a vector type");
5067 // Always build SSE zero vectors as <4 x i32> bitcasted
5068 // to their dest type. This ensures they get CSE'd.
5070 if (VT.is128BitVector()) { // SSE
5071 if (Subtarget->hasSSE2()) { // SSE2
5072 SDValue Cst = DAG.getConstant(0, MVT::i32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5075 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5078 } else if (VT.is256BitVector()) { // AVX
5079 if (Subtarget->hasInt256()) { // AVX2
5080 SDValue Cst = DAG.getConstant(0, MVT::i32);
5081 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5082 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5084 // 256-bit logic and arithmetic instructions in AVX are all
5085 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5086 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5088 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5090 } else if (VT.is512BitVector()) { // AVX-512
5091 SDValue Cst = DAG.getConstant(0, MVT::i32);
5092 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5093 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5094 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5095 } else if (VT.getScalarType() == MVT::i1) {
5096 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5097 SDValue Cst = DAG.getConstant(0, MVT::i1);
5098 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5099 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5101 llvm_unreachable("Unexpected vector type");
5103 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5106 /// getOnesVector - Returns a vector of specified type with all bits set.
5107 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5108 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5109 /// Then bitcast to their original type, ensuring they get CSE'd.
5110 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5112 assert(VT.isVector() && "Expected a vector type");
5114 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5116 if (VT.is256BitVector()) {
5117 if (HasInt256) { // AVX2
5118 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5119 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5124 } else if (VT.is128BitVector()) {
5125 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5127 llvm_unreachable("Unexpected vector type");
5129 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5132 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5133 /// that point to V2 points to its first element.
5134 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5135 for (unsigned i = 0; i != NumElems; ++i) {
5136 if (Mask[i] > (int)NumElems) {
5142 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5143 /// operation of specified width.
5144 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5146 unsigned NumElems = VT.getVectorNumElements();
5147 SmallVector<int, 8> Mask;
5148 Mask.push_back(NumElems);
5149 for (unsigned i = 1; i != NumElems; ++i)
5151 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5154 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5155 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5157 unsigned NumElems = VT.getVectorNumElements();
5158 SmallVector<int, 8> Mask;
5159 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5161 Mask.push_back(i + NumElems);
5163 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5166 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5167 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5169 unsigned NumElems = VT.getVectorNumElements();
5170 SmallVector<int, 8> Mask;
5171 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5172 Mask.push_back(i + Half);
5173 Mask.push_back(i + NumElems + Half);
5175 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5178 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5179 // a generic shuffle instruction because the target has no such instructions.
5180 // Generate shuffles which repeat i16 and i8 several times until they can be
5181 // represented by v4f32 and then be manipulated by target suported shuffles.
5182 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5183 MVT VT = V.getSimpleValueType();
5184 int NumElems = VT.getVectorNumElements();
5187 while (NumElems > 4) {
5188 if (EltNo < NumElems/2) {
5189 V = getUnpackl(DAG, dl, VT, V, V);
5191 V = getUnpackh(DAG, dl, VT, V, V);
5192 EltNo -= NumElems/2;
5199 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5200 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5201 MVT VT = V.getSimpleValueType();
5204 if (VT.is128BitVector()) {
5205 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5206 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5207 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5209 } else if (VT.is256BitVector()) {
5210 // To use VPERMILPS to splat scalars, the second half of indicies must
5211 // refer to the higher part, which is a duplication of the lower one,
5212 // because VPERMILPS can only handle in-lane permutations.
5213 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5214 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5216 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5217 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5220 llvm_unreachable("Vector size not supported");
5222 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5225 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5226 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5227 MVT SrcVT = SV->getSimpleValueType(0);
5228 SDValue V1 = SV->getOperand(0);
5231 int EltNo = SV->getSplatIndex();
5232 int NumElems = SrcVT.getVectorNumElements();
5233 bool Is256BitVec = SrcVT.is256BitVector();
5235 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5236 "Unknown how to promote splat for type");
5238 // Extract the 128-bit part containing the splat element and update
5239 // the splat element index when it refers to the higher register.
5241 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5242 if (EltNo >= NumElems/2)
5243 EltNo -= NumElems/2;
5246 // All i16 and i8 vector types can't be used directly by a generic shuffle
5247 // instruction because the target has no such instruction. Generate shuffles
5248 // which repeat i16 and i8 several times until they fit in i32, and then can
5249 // be manipulated by target suported shuffles.
5250 MVT EltVT = SrcVT.getVectorElementType();
5251 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5252 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5254 // Recreate the 256-bit vector and place the same 128-bit vector
5255 // into the low and high part. This is necessary because we want
5256 // to use VPERM* to shuffle the vectors
5258 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5261 return getLegalSplat(DAG, V1, EltNo);
5264 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5265 /// vector of zero or undef vector. This produces a shuffle where the low
5266 /// element of V2 is swizzled into the zero/undef vector, landing at element
5267 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5268 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5270 const X86Subtarget *Subtarget,
5271 SelectionDAG &DAG) {
5272 MVT VT = V2.getSimpleValueType();
5274 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5275 unsigned NumElems = VT.getVectorNumElements();
5276 SmallVector<int, 16> MaskVec;
5277 for (unsigned i = 0; i != NumElems; ++i)
5278 // If this is the insertion idx, put the low elt of V2 here.
5279 MaskVec.push_back(i == Idx ? NumElems : i);
5280 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5283 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5284 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5285 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5286 /// shuffles which use a single input multiple times, and in those cases it will
5287 /// adjust the mask to only have indices within that single input.
5288 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5289 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5290 unsigned NumElems = VT.getVectorNumElements();
5294 bool IsFakeUnary = false;
5295 switch(N->getOpcode()) {
5296 case X86ISD::BLENDI:
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5301 ImmN = N->getOperand(N->getNumOperands()-1);
5302 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKH:
5306 DecodeUNPCKHMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::UNPCKL:
5310 DecodeUNPCKLMask(VT, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVHLPS:
5314 DecodeMOVHLPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::MOVLHPS:
5318 DecodeMOVLHPSMask(NumElems, Mask);
5319 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5321 case X86ISD::PALIGNR:
5322 ImmN = N->getOperand(N->getNumOperands()-1);
5323 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5325 case X86ISD::PSHUFD:
5326 case X86ISD::VPERMILPI:
5327 ImmN = N->getOperand(N->getNumOperands()-1);
5328 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 case X86ISD::PSHUFHW:
5332 ImmN = N->getOperand(N->getNumOperands()-1);
5333 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5336 case X86ISD::PSHUFLW:
5337 ImmN = N->getOperand(N->getNumOperands()-1);
5338 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5341 case X86ISD::PSHUFB: {
5343 SDValue MaskNode = N->getOperand(1);
5344 while (MaskNode->getOpcode() == ISD::BITCAST)
5345 MaskNode = MaskNode->getOperand(0);
5347 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5348 // If we have a build-vector, then things are easy.
5349 EVT VT = MaskNode.getValueType();
5350 assert(VT.isVector() &&
5351 "Can't produce a non-vector with a build_vector!");
5352 if (!VT.isInteger())
5355 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5357 SmallVector<uint64_t, 32> RawMask;
5358 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5359 SDValue Op = MaskNode->getOperand(i);
5360 if (Op->getOpcode() == ISD::UNDEF) {
5361 RawMask.push_back((uint64_t)SM_SentinelUndef);
5364 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5367 APInt MaskElement = CN->getAPIntValue();
5369 // We now have to decode the element which could be any integer size and
5370 // extract each byte of it.
5371 for (int j = 0; j < NumBytesPerElement; ++j) {
5372 // Note that this is x86 and so always little endian: the low byte is
5373 // the first byte of the mask.
5374 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5375 MaskElement = MaskElement.lshr(8);
5378 DecodePSHUFBMask(RawMask, Mask);
5382 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5386 SDValue Ptr = MaskLoad->getBasePtr();
5387 if (Ptr->getOpcode() == X86ISD::Wrapper)
5388 Ptr = Ptr->getOperand(0);
5390 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5391 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5394 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5395 // FIXME: Support AVX-512 here.
5396 Type *Ty = C->getType();
5397 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5398 Ty->getVectorNumElements() != 32))
5401 DecodePSHUFBMask(C, Mask);
5407 case X86ISD::VPERMI:
5408 ImmN = N->getOperand(N->getNumOperands()-1);
5409 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5413 case X86ISD::MOVSD: {
5414 // The index 0 always comes from the first element of the second source,
5415 // this is why MOVSS and MOVSD are used in the first place. The other
5416 // elements come from the other positions of the first source vector
5417 Mask.push_back(NumElems);
5418 for (unsigned i = 1; i != NumElems; ++i) {
5423 case X86ISD::VPERM2X128:
5424 ImmN = N->getOperand(N->getNumOperands()-1);
5425 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5426 if (Mask.empty()) return false;
5428 case X86ISD::MOVSLDUP:
5429 DecodeMOVSLDUPMask(VT, Mask);
5431 case X86ISD::MOVSHDUP:
5432 DecodeMOVSHDUPMask(VT, Mask);
5434 case X86ISD::MOVDDUP:
5435 case X86ISD::MOVLHPD:
5436 case X86ISD::MOVLPD:
5437 case X86ISD::MOVLPS:
5438 // Not yet implemented
5440 default: llvm_unreachable("unknown target shuffle node");
5443 // If we have a fake unary shuffle, the shuffle mask is spread across two
5444 // inputs that are actually the same node. Re-map the mask to always point
5445 // into the first input.
5448 if (M >= (int)Mask.size())
5454 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5455 /// element of the result of the vector shuffle.
5456 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5459 return SDValue(); // Limit search depth.
5461 SDValue V = SDValue(N, 0);
5462 EVT VT = V.getValueType();
5463 unsigned Opcode = V.getOpcode();
5465 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5466 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5467 int Elt = SV->getMaskElt(Index);
5470 return DAG.getUNDEF(VT.getVectorElementType());
5472 unsigned NumElems = VT.getVectorNumElements();
5473 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5474 : SV->getOperand(1);
5475 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5478 // Recurse into target specific vector shuffles to find scalars.
5479 if (isTargetShuffle(Opcode)) {
5480 MVT ShufVT = V.getSimpleValueType();
5481 unsigned NumElems = ShufVT.getVectorNumElements();
5482 SmallVector<int, 16> ShuffleMask;
5485 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5488 int Elt = ShuffleMask[Index];
5490 return DAG.getUNDEF(ShufVT.getVectorElementType());
5492 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5494 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5498 // Actual nodes that may contain scalar elements
5499 if (Opcode == ISD::BITCAST) {
5500 V = V.getOperand(0);
5501 EVT SrcVT = V.getValueType();
5502 unsigned NumElems = VT.getVectorNumElements();
5504 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5508 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5509 return (Index == 0) ? V.getOperand(0)
5510 : DAG.getUNDEF(VT.getVectorElementType());
5512 if (V.getOpcode() == ISD::BUILD_VECTOR)
5513 return V.getOperand(Index);
5518 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5519 /// shuffle operation which come from a consecutively from a zero. The
5520 /// search can start in two different directions, from left or right.
5521 /// We count undefs as zeros until PreferredNum is reached.
5522 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5523 unsigned NumElems, bool ZerosFromLeft,
5525 unsigned PreferredNum = -1U) {
5526 unsigned NumZeros = 0;
5527 for (unsigned i = 0; i != NumElems; ++i) {
5528 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5529 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5533 if (X86::isZeroNode(Elt))
5535 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5536 NumZeros = std::min(NumZeros + 1, PreferredNum);
5544 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5545 /// correspond consecutively to elements from one of the vector operands,
5546 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5548 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5549 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5550 unsigned NumElems, unsigned &OpNum) {
5551 bool SeenV1 = false;
5552 bool SeenV2 = false;
5554 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5555 int Idx = SVOp->getMaskElt(i);
5556 // Ignore undef indicies
5560 if (Idx < (int)NumElems)
5565 // Only accept consecutive elements from the same vector
5566 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5570 OpNum = SeenV1 ? 0 : 1;
5574 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5575 /// logical left shift of a vector.
5576 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5577 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5579 SVOp->getSimpleValueType(0).getVectorNumElements();
5580 unsigned NumZeros = getNumOfConsecutiveZeros(
5581 SVOp, NumElems, false /* check zeros from right */, DAG,
5582 SVOp->getMaskElt(0));
5588 // Considering the elements in the mask that are not consecutive zeros,
5589 // check if they consecutively come from only one of the source vectors.
5591 // V1 = {X, A, B, C} 0
5593 // vector_shuffle V1, V2 <1, 2, 3, X>
5595 if (!isShuffleMaskConsecutive(SVOp,
5596 0, // Mask Start Index
5597 NumElems-NumZeros, // Mask End Index(exclusive)
5598 NumZeros, // Where to start looking in the src vector
5599 NumElems, // Number of elements in vector
5600 OpSrc)) // Which source operand ?
5605 ShVal = SVOp->getOperand(OpSrc);
5609 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5610 /// logical left shift of a vector.
5611 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5612 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5614 SVOp->getSimpleValueType(0).getVectorNumElements();
5615 unsigned NumZeros = getNumOfConsecutiveZeros(
5616 SVOp, NumElems, true /* check zeros from left */, DAG,
5617 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5623 // Considering the elements in the mask that are not consecutive zeros,
5624 // check if they consecutively come from only one of the source vectors.
5626 // 0 { A, B, X, X } = V2
5628 // vector_shuffle V1, V2 <X, X, 4, 5>
5630 if (!isShuffleMaskConsecutive(SVOp,
5631 NumZeros, // Mask Start Index
5632 NumElems, // Mask End Index(exclusive)
5633 0, // Where to start looking in the src vector
5634 NumElems, // Number of elements in vector
5635 OpSrc)) // Which source operand ?
5640 ShVal = SVOp->getOperand(OpSrc);
5644 /// isVectorShift - Returns true if the shuffle can be implemented as a
5645 /// logical left or right shift of a vector.
5646 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5647 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5648 // Although the logic below support any bitwidth size, there are no
5649 // shift instructions which handle more than 128-bit vectors.
5650 if (!SVOp->getSimpleValueType(0).is128BitVector())
5653 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5654 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5660 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5662 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5663 unsigned NumNonZero, unsigned NumZero,
5665 const X86Subtarget* Subtarget,
5666 const TargetLowering &TLI) {
5673 for (unsigned i = 0; i < 16; ++i) {
5674 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5675 if (ThisIsNonZero && First) {
5677 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5679 V = DAG.getUNDEF(MVT::v8i16);
5684 SDValue ThisElt, LastElt;
5685 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5686 if (LastIsNonZero) {
5687 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5688 MVT::i16, Op.getOperand(i-1));
5690 if (ThisIsNonZero) {
5691 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5692 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5693 ThisElt, DAG.getConstant(8, MVT::i8));
5695 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5699 if (ThisElt.getNode())
5700 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5701 DAG.getIntPtrConstant(i/2));
5705 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5708 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5710 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5711 unsigned NumNonZero, unsigned NumZero,
5713 const X86Subtarget* Subtarget,
5714 const TargetLowering &TLI) {
5721 for (unsigned i = 0; i < 8; ++i) {
5722 bool isNonZero = (NonZeros & (1 << i)) != 0;
5726 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5728 V = DAG.getUNDEF(MVT::v8i16);
5731 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5732 MVT::v8i16, V, Op.getOperand(i),
5733 DAG.getIntPtrConstant(i));
5740 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5741 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5742 const X86Subtarget *Subtarget,
5743 const TargetLowering &TLI) {
5744 // Find all zeroable elements.
5746 for (int i=0; i < 4; ++i) {
5747 SDValue Elt = Op->getOperand(i);
5748 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5750 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5751 [](bool M) { return !M; }) > 1 &&
5752 "We expect at least two non-zero elements!");
5754 // We only know how to deal with build_vector nodes where elements are either
5755 // zeroable or extract_vector_elt with constant index.
5756 SDValue FirstNonZero;
5757 unsigned FirstNonZeroIdx;
5758 for (unsigned i=0; i < 4; ++i) {
5761 SDValue Elt = Op->getOperand(i);
5762 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5763 !isa<ConstantSDNode>(Elt.getOperand(1)))
5765 // Make sure that this node is extracting from a 128-bit vector.
5766 MVT VT = Elt.getOperand(0).getSimpleValueType();
5767 if (!VT.is128BitVector())
5769 if (!FirstNonZero.getNode()) {
5771 FirstNonZeroIdx = i;
5775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5776 SDValue V1 = FirstNonZero.getOperand(0);
5777 MVT VT = V1.getSimpleValueType();
5779 // See if this build_vector can be lowered as a blend with zero.
5781 unsigned EltMaskIdx, EltIdx;
5783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5784 if (Zeroable[EltIdx]) {
5785 // The zero vector will be on the right hand side.
5786 Mask[EltIdx] = EltIdx+4;
5790 Elt = Op->getOperand(EltIdx);
5791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5795 Mask[EltIdx] = EltIdx;
5799 // Let the shuffle legalizer deal with blend operations.
5800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5801 if (V1.getSimpleValueType() != VT)
5802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5806 // See if we can lower this build_vector to a INSERTPS.
5807 if (!Subtarget->hasSSE41())
5810 SDValue V2 = Elt.getOperand(0);
5811 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5814 bool CanFold = true;
5815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5819 SDValue Current = Op->getOperand(i);
5820 SDValue SrcVector = Current->getOperand(0);
5823 CanFold = SrcVector == V1 &&
5824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5830 assert(V1.getNode() && "Expected at least two non-zero elements!");
5831 if (V1.getSimpleValueType() != MVT::v4f32)
5832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5833 if (V2.getSimpleValueType() != MVT::v4f32)
5834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5836 // Ok, we can emit an INSERTPS instruction.
5838 for (int i = 0; i < 4; ++i)
5842 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5843 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5844 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5845 DAG.getIntPtrConstant(InsertPSMask));
5846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5849 /// getVShift - Return a vector logical shift node.
5851 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5852 unsigned NumBits, SelectionDAG &DAG,
5853 const TargetLowering &TLI, SDLoc dl) {
5854 assert(VT.is128BitVector() && "Unknown type for VShift");
5855 EVT ShVT = MVT::v2i64;
5856 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5857 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 DAG.getNode(Opc, dl, ShVT, SrcOp,
5860 DAG.getConstant(NumBits,
5861 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5865 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5867 // Check if the scalar load can be widened into a vector load. And if
5868 // the address is "base + cst" see if the cst can be "absorbed" into
5869 // the shuffle mask.
5870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5871 SDValue Ptr = LD->getBasePtr();
5872 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5874 EVT PVT = LD->getValueType(0);
5875 if (PVT != MVT::i32 && PVT != MVT::f32)
5880 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5881 FI = FINode->getIndex();
5883 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5884 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5885 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5886 Offset = Ptr.getConstantOperandVal(1);
5887 Ptr = Ptr.getOperand(0);
5892 // FIXME: 256-bit vector instructions don't require a strict alignment,
5893 // improve this code to support it better.
5894 unsigned RequiredAlign = VT.getSizeInBits()/8;
5895 SDValue Chain = LD->getChain();
5896 // Make sure the stack object alignment is at least 16 or 32.
5897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5898 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5899 if (MFI->isFixedObjectIndex(FI)) {
5900 // Can't change the alignment. FIXME: It's possible to compute
5901 // the exact stack offset and reference FI + adjust offset instead.
5902 // If someone *really* cares about this. That's the way to implement it.
5905 MFI->setObjectAlignment(FI, RequiredAlign);
5909 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5910 // Ptr + (Offset & ~15).
5913 if ((Offset % RequiredAlign) & 3)
5915 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5917 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5918 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5920 int EltNo = (Offset - StartOffset) >> 2;
5921 unsigned NumElems = VT.getVectorNumElements();
5923 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5924 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5925 LD->getPointerInfo().getWithOffset(StartOffset),
5926 false, false, false, 0);
5928 SmallVector<int, 8> Mask;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 Mask.push_back(EltNo);
5932 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5938 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5939 /// vector of type 'VT', see if the elements can be replaced by a single large
5940 /// load which has the same value as a build_vector whose operands are 'elts'.
5942 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5944 /// FIXME: we'd also like to handle the case where the last elements are zero
5945 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5946 /// There's even a handy isZeroNode for that purpose.
5947 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5948 SDLoc &DL, SelectionDAG &DAG,
5949 bool isAfterLegalize) {
5950 EVT EltVT = VT.getVectorElementType();
5951 unsigned NumElems = Elts.size();
5953 LoadSDNode *LDBase = nullptr;
5954 unsigned LastLoadedElt = -1U;
5956 // For each element in the initializer, see if we've found a load or an undef.
5957 // If we don't find an initial load element, or later load elements are
5958 // non-consecutive, bail out.
5959 for (unsigned i = 0; i < NumElems; ++i) {
5960 SDValue Elt = Elts[i];
5962 if (!Elt.getNode() ||
5963 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5966 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5968 LDBase = cast<LoadSDNode>(Elt.getNode());
5972 if (Elt.getOpcode() == ISD::UNDEF)
5975 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5976 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5981 // If we have found an entire vector of loads and undefs, then return a large
5982 // load of the entire vector width starting at the base pointer. If we found
5983 // consecutive loads for the low half, generate a vzext_load node.
5984 if (LastLoadedElt == NumElems - 1) {
5986 if (isAfterLegalize &&
5987 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5990 SDValue NewLd = SDValue();
5992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5993 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5994 LDBase->getPointerInfo(),
5995 LDBase->isVolatile(), LDBase->isNonTemporal(),
5996 LDBase->isInvariant(), 0);
5997 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5998 LDBase->getPointerInfo(),
5999 LDBase->isVolatile(), LDBase->isNonTemporal(),
6000 LDBase->isInvariant(), LDBase->getAlignment());
6002 if (LDBase->hasAnyUseOfValue(1)) {
6003 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6005 SDValue(NewLd.getNode(), 1));
6006 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6007 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6008 SDValue(NewLd.getNode(), 1));
6013 if (NumElems == 4 && LastLoadedElt == 1 &&
6014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6018 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6019 LDBase->getPointerInfo(),
6020 LDBase->getAlignment(),
6021 false/*isVolatile*/, true/*ReadMem*/,
6024 // Make sure the newly-created LOAD is in the same position as LDBase in
6025 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6026 // update uses of LDBase's output chain to use the TokenFactor.
6027 if (LDBase->hasAnyUseOfValue(1)) {
6028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6029 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6032 SDValue(ResNode.getNode(), 1));
6035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6040 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6041 /// to generate a splat value for the following cases:
6042 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6043 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6044 /// a scalar load, or a constant.
6045 /// The VBROADCAST node is returned when a pattern is found,
6046 /// or SDValue() otherwise.
6047 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6048 SelectionDAG &DAG) {
6049 // VBROADCAST requires AVX.
6050 // TODO: Splats could be generated for non-AVX CPUs using SSE
6051 // instructions, but there's less potential gain for only 128-bit vectors.
6052 if (!Subtarget->hasAVX())
6055 MVT VT = Op.getSimpleValueType();
6058 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6059 "Unsupported vector type for broadcast.");
6064 switch (Op.getOpcode()) {
6066 // Unknown pattern found.
6069 case ISD::BUILD_VECTOR: {
6070 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6071 BitVector UndefElements;
6072 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6074 // We need a splat of a single value to use broadcast, and it doesn't
6075 // make any sense if the value is only in one element of the vector.
6076 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6080 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6081 Ld.getOpcode() == ISD::ConstantFP);
6083 // Make sure that all of the users of a non-constant load are from the
6084 // BUILD_VECTOR node.
6085 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6090 case ISD::VECTOR_SHUFFLE: {
6091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6093 // Shuffles must have a splat mask where the first element is
6095 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6098 SDValue Sc = Op.getOperand(0);
6099 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6100 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6102 if (!Subtarget->hasInt256())
6105 // Use the register form of the broadcast instruction available on AVX2.
6106 if (VT.getSizeInBits() >= 256)
6107 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6111 Ld = Sc.getOperand(0);
6112 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6113 Ld.getOpcode() == ISD::ConstantFP);
6115 // The scalar_to_vector node and the suspected
6116 // load node must have exactly one user.
6117 // Constants may have multiple users.
6119 // AVX-512 has register version of the broadcast
6120 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6121 Ld.getValueType().getSizeInBits() >= 32;
6122 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6129 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6130 bool IsGE256 = (VT.getSizeInBits() >= 256);
6132 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6133 // instruction to save 8 or more bytes of constant pool data.
6134 // TODO: If multiple splats are generated to load the same constant,
6135 // it may be detrimental to overall size. There needs to be a way to detect
6136 // that condition to know if this is truly a size win.
6137 const Function *F = DAG.getMachineFunction().getFunction();
6138 bool OptForSize = F->getAttributes().
6139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6141 // Handle broadcasting a single constant scalar from the constant pool
6143 // On Sandybridge (no AVX2), it is still better to load a constant vector
6144 // from the constant pool and not to broadcast it from a scalar.
6145 // But override that restriction when optimizing for size.
6146 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6147 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6148 EVT CVT = Ld.getValueType();
6149 assert(!CVT.isVector() && "Must not broadcast a vector type");
6151 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6152 // For size optimization, also splat v2f64 and v2i64, and for size opt
6153 // with AVX2, also splat i8 and i16.
6154 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6155 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6156 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6157 const Constant *C = nullptr;
6158 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6159 C = CI->getConstantIntValue();
6160 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6161 C = CF->getConstantFPValue();
6163 assert(C && "Invalid constant type");
6165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6167 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6168 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6169 MachinePointerInfo::getConstantPool(),
6170 false, false, false, Alignment);
6172 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6176 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6178 // Handle AVX2 in-register broadcasts.
6179 if (!IsLoad && Subtarget->hasInt256() &&
6180 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6183 // The scalar source must be a normal load.
6187 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6191 // double since there is no vbroadcastsd xmm
6192 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6193 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // Unsupported broadcast.
6201 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6202 /// underlying vector and index.
6204 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6206 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6208 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6209 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6212 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6214 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6216 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6217 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6220 // In this case the vector is the extract_subvector expression and the index
6221 // is 2, as specified by the shuffle.
6222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6223 SDValue ShuffleVec = SVOp->getOperand(0);
6224 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6225 assert(ShuffleVecVT.getVectorElementType() ==
6226 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6228 int ShuffleIdx = SVOp->getMaskElt(Idx);
6229 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6230 ExtractedFromVec = ShuffleVec;
6236 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6237 MVT VT = Op.getSimpleValueType();
6239 // Skip if insert_vec_elt is not supported.
6240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6241 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6245 unsigned NumElems = Op.getNumOperands();
6249 SmallVector<unsigned, 4> InsertIndices;
6250 SmallVector<int, 8> Mask(NumElems, -1);
6252 for (unsigned i = 0; i != NumElems; ++i) {
6253 unsigned Opc = Op.getOperand(i).getOpcode();
6255 if (Opc == ISD::UNDEF)
6258 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6259 // Quit if more than 1 elements need inserting.
6260 if (InsertIndices.size() > 1)
6263 InsertIndices.push_back(i);
6267 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6268 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6269 // Quit if non-constant index.
6270 if (!isa<ConstantSDNode>(ExtIdx))
6272 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6274 // Quit if extracted from vector of different type.
6275 if (ExtractedFromVec.getValueType() != VT)
6278 if (!VecIn1.getNode())
6279 VecIn1 = ExtractedFromVec;
6280 else if (VecIn1 != ExtractedFromVec) {
6281 if (!VecIn2.getNode())
6282 VecIn2 = ExtractedFromVec;
6283 else if (VecIn2 != ExtractedFromVec)
6284 // Quit if more than 2 vectors to shuffle
6288 if (ExtractedFromVec == VecIn1)
6290 else if (ExtractedFromVec == VecIn2)
6291 Mask[i] = Idx + NumElems;
6294 if (!VecIn1.getNode())
6297 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6298 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6299 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6300 unsigned Idx = InsertIndices[i];
6301 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6302 DAG.getIntPtrConstant(Idx));
6308 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6310 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6312 MVT VT = Op.getSimpleValueType();
6313 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6314 "Unexpected type in LowerBUILD_VECTORvXi1!");
6317 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6318 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6319 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6320 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6323 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6324 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6325 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6326 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6329 bool AllContants = true;
6330 uint64_t Immediate = 0;
6331 int NonConstIdx = -1;
6332 bool IsSplat = true;
6333 unsigned NumNonConsts = 0;
6334 unsigned NumConsts = 0;
6335 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6336 SDValue In = Op.getOperand(idx);
6337 if (In.getOpcode() == ISD::UNDEF)
6339 if (!isa<ConstantSDNode>(In)) {
6340 AllContants = false;
6345 if (cast<ConstantSDNode>(In)->getZExtValue())
6346 Immediate |= (1ULL << idx);
6348 if (In != Op.getOperand(0))
6353 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6354 DAG.getConstant(Immediate, MVT::i16));
6355 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6356 DAG.getIntPtrConstant(0));
6359 if (NumNonConsts == 1 && NonConstIdx != 0) {
6362 SDValue VecAsImm = DAG.getConstant(Immediate,
6363 MVT::getIntegerVT(VT.getSizeInBits()));
6364 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6367 DstVec = DAG.getUNDEF(VT);
6368 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6369 Op.getOperand(NonConstIdx),
6370 DAG.getIntPtrConstant(NonConstIdx));
6372 if (!IsSplat && (NonConstIdx != 0))
6373 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6374 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6377 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6378 DAG.getConstant(-1, SelectVT),
6379 DAG.getConstant(0, SelectVT));
6381 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6382 DAG.getConstant((Immediate | 1), SelectVT),
6383 DAG.getConstant(Immediate, SelectVT));
6384 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6387 /// \brief Return true if \p N implements a horizontal binop and return the
6388 /// operands for the horizontal binop into V0 and V1.
6390 /// This is a helper function of PerformBUILD_VECTORCombine.
6391 /// This function checks that the build_vector \p N in input implements a
6392 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6393 /// operation to match.
6394 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6395 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6396 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6399 /// This function only analyzes elements of \p N whose indices are
6400 /// in range [BaseIdx, LastIdx).
6401 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6403 unsigned BaseIdx, unsigned LastIdx,
6404 SDValue &V0, SDValue &V1) {
6405 EVT VT = N->getValueType(0);
6407 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6408 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6409 "Invalid Vector in input!");
6411 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6412 bool CanFold = true;
6413 unsigned ExpectedVExtractIdx = BaseIdx;
6414 unsigned NumElts = LastIdx - BaseIdx;
6415 V0 = DAG.getUNDEF(VT);
6416 V1 = DAG.getUNDEF(VT);
6418 // Check if N implements a horizontal binop.
6419 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6420 SDValue Op = N->getOperand(i + BaseIdx);
6423 if (Op->getOpcode() == ISD::UNDEF) {
6424 // Update the expected vector extract index.
6425 if (i * 2 == NumElts)
6426 ExpectedVExtractIdx = BaseIdx;
6427 ExpectedVExtractIdx += 2;
6431 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6436 SDValue Op0 = Op.getOperand(0);
6437 SDValue Op1 = Op.getOperand(1);
6439 // Try to match the following pattern:
6440 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6441 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6442 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op0.getOperand(0) == Op1.getOperand(0) &&
6444 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6445 isa<ConstantSDNode>(Op1.getOperand(1)));
6449 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6450 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6452 if (i * 2 < NumElts) {
6453 if (V0.getOpcode() == ISD::UNDEF)
6454 V0 = Op0.getOperand(0);
6456 if (V1.getOpcode() == ISD::UNDEF)
6457 V1 = Op0.getOperand(0);
6458 if (i * 2 == NumElts)
6459 ExpectedVExtractIdx = BaseIdx;
6462 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6463 if (I0 == ExpectedVExtractIdx)
6464 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6465 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6466 // Try to match the following dag sequence:
6467 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6468 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6472 ExpectedVExtractIdx += 2;
6478 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6479 /// a concat_vector.
6481 /// This is a helper function of PerformBUILD_VECTORCombine.
6482 /// This function expects two 256-bit vectors called V0 and V1.
6483 /// At first, each vector is split into two separate 128-bit vectors.
6484 /// Then, the resulting 128-bit vectors are used to implement two
6485 /// horizontal binary operations.
6487 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6489 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6490 /// the two new horizontal binop.
6491 /// When Mode is set, the first horizontal binop dag node would take as input
6492 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6493 /// horizontal binop dag node would take as input the lower 128-bit of V1
6494 /// and the upper 128-bit of V1.
6496 /// HADD V0_LO, V0_HI
6497 /// HADD V1_LO, V1_HI
6499 /// Otherwise, the first horizontal binop dag node takes as input the lower
6500 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6501 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6503 /// HADD V0_LO, V1_LO
6504 /// HADD V0_HI, V1_HI
6506 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6507 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6508 /// the upper 128-bits of the result.
6509 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6510 SDLoc DL, SelectionDAG &DAG,
6511 unsigned X86Opcode, bool Mode,
6512 bool isUndefLO, bool isUndefHI) {
6513 EVT VT = V0.getValueType();
6514 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6515 "Invalid nodes in input!");
6517 unsigned NumElts = VT.getVectorNumElements();
6518 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6519 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6520 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6521 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6522 EVT NewVT = V0_LO.getValueType();
6524 SDValue LO = DAG.getUNDEF(NewVT);
6525 SDValue HI = DAG.getUNDEF(NewVT);
6528 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6529 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6530 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6531 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6532 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6534 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6535 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6536 V1_LO->getOpcode() != ISD::UNDEF))
6537 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6539 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6540 V1_HI->getOpcode() != ISD::UNDEF))
6541 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6544 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6547 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6548 /// sequence of 'vadd + vsub + blendi'.
6549 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6550 const X86Subtarget *Subtarget) {
6552 EVT VT = BV->getValueType(0);
6553 unsigned NumElts = VT.getVectorNumElements();
6554 SDValue InVec0 = DAG.getUNDEF(VT);
6555 SDValue InVec1 = DAG.getUNDEF(VT);
6557 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6558 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6560 // Odd-numbered elements in the input build vector are obtained from
6561 // adding two integer/float elements.
6562 // Even-numbered elements in the input build vector are obtained from
6563 // subtracting two integer/float elements.
6564 unsigned ExpectedOpcode = ISD::FSUB;
6565 unsigned NextExpectedOpcode = ISD::FADD;
6566 bool AddFound = false;
6567 bool SubFound = false;
6569 for (unsigned i = 0, e = NumElts; i != e; i++) {
6570 SDValue Op = BV->getOperand(i);
6572 // Skip 'undef' values.
6573 unsigned Opcode = Op.getOpcode();
6574 if (Opcode == ISD::UNDEF) {
6575 std::swap(ExpectedOpcode, NextExpectedOpcode);
6579 // Early exit if we found an unexpected opcode.
6580 if (Opcode != ExpectedOpcode)
6583 SDValue Op0 = Op.getOperand(0);
6584 SDValue Op1 = Op.getOperand(1);
6586 // Try to match the following pattern:
6587 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6588 // Early exit if we cannot match that sequence.
6589 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6590 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6592 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6593 Op0.getOperand(1) != Op1.getOperand(1))
6596 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6600 // We found a valid add/sub node. Update the information accordingly.
6606 // Update InVec0 and InVec1.
6607 if (InVec0.getOpcode() == ISD::UNDEF)
6608 InVec0 = Op0.getOperand(0);
6609 if (InVec1.getOpcode() == ISD::UNDEF)
6610 InVec1 = Op1.getOperand(0);
6612 // Make sure that operands in input to each add/sub node always
6613 // come from a same pair of vectors.
6614 if (InVec0 != Op0.getOperand(0)) {
6615 if (ExpectedOpcode == ISD::FSUB)
6618 // FADD is commutable. Try to commute the operands
6619 // and then test again.
6620 std::swap(Op0, Op1);
6621 if (InVec0 != Op0.getOperand(0))
6625 if (InVec1 != Op1.getOperand(0))
6628 // Update the pair of expected opcodes.
6629 std::swap(ExpectedOpcode, NextExpectedOpcode);
6632 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6633 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6634 InVec1.getOpcode() != ISD::UNDEF)
6635 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6640 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6641 const X86Subtarget *Subtarget) {
6643 EVT VT = N->getValueType(0);
6644 unsigned NumElts = VT.getVectorNumElements();
6645 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6646 SDValue InVec0, InVec1;
6648 // Try to match an ADDSUB.
6649 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6650 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6651 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6652 if (Value.getNode())
6656 // Try to match horizontal ADD/SUB.
6657 unsigned NumUndefsLO = 0;
6658 unsigned NumUndefsHI = 0;
6659 unsigned Half = NumElts/2;
6661 // Count the number of UNDEF operands in the build_vector in input.
6662 for (unsigned i = 0, e = Half; i != e; ++i)
6663 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6666 for (unsigned i = Half, e = NumElts; i != e; ++i)
6667 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6670 // Early exit if this is either a build_vector of all UNDEFs or all the
6671 // operands but one are UNDEF.
6672 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6675 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6676 // Try to match an SSE3 float HADD/HSUB.
6677 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6678 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6680 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6681 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6682 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6683 // Try to match an SSSE3 integer HADD/HSUB.
6684 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6685 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6687 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6688 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6691 if (!Subtarget->hasAVX())
6694 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6695 // Try to match an AVX horizontal add/sub of packed single/double
6696 // precision floating point values from 256-bit vectors.
6697 SDValue InVec2, InVec3;
6698 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6699 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6700 ((InVec0.getOpcode() == ISD::UNDEF ||
6701 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6702 ((InVec1.getOpcode() == ISD::UNDEF ||
6703 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6704 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6706 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6707 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6708 ((InVec0.getOpcode() == ISD::UNDEF ||
6709 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6710 ((InVec1.getOpcode() == ISD::UNDEF ||
6711 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6712 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6713 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6714 // Try to match an AVX2 horizontal add/sub of signed integers.
6715 SDValue InVec2, InVec3;
6717 bool CanFold = true;
6719 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6720 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6721 ((InVec0.getOpcode() == ISD::UNDEF ||
6722 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6723 ((InVec1.getOpcode() == ISD::UNDEF ||
6724 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6725 X86Opcode = X86ISD::HADD;
6726 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6727 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6728 ((InVec0.getOpcode() == ISD::UNDEF ||
6729 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6730 ((InVec1.getOpcode() == ISD::UNDEF ||
6731 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6732 X86Opcode = X86ISD::HSUB;
6737 // Fold this build_vector into a single horizontal add/sub.
6738 // Do this only if the target has AVX2.
6739 if (Subtarget->hasAVX2())
6740 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6742 // Do not try to expand this build_vector into a pair of horizontal
6743 // add/sub if we can emit a pair of scalar add/sub.
6744 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6747 // Convert this build_vector into a pair of horizontal binop followed by
6749 bool isUndefLO = NumUndefsLO == Half;
6750 bool isUndefHI = NumUndefsHI == Half;
6751 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6752 isUndefLO, isUndefHI);
6756 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6757 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6759 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6760 X86Opcode = X86ISD::HADD;
6761 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6762 X86Opcode = X86ISD::HSUB;
6763 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6764 X86Opcode = X86ISD::FHADD;
6765 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6766 X86Opcode = X86ISD::FHSUB;
6770 // Don't try to expand this build_vector into a pair of horizontal add/sub
6771 // if we can simply emit a pair of scalar add/sub.
6772 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6775 // Convert this build_vector into two horizontal add/sub followed by
6777 bool isUndefLO = NumUndefsLO == Half;
6778 bool isUndefHI = NumUndefsHI == Half;
6779 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6780 isUndefLO, isUndefHI);
6787 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6790 MVT VT = Op.getSimpleValueType();
6791 MVT ExtVT = VT.getVectorElementType();
6792 unsigned NumElems = Op.getNumOperands();
6794 // Generate vectors for predicate vectors.
6795 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6796 return LowerBUILD_VECTORvXi1(Op, DAG);
6798 // Vectors containing all zeros can be matched by pxor and xorps later
6799 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6800 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6801 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6802 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6805 return getZeroVector(VT, Subtarget, DAG, dl);
6808 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6809 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6810 // vpcmpeqd on 256-bit vectors.
6811 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6812 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6815 if (!VT.is512BitVector())
6816 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6819 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6820 if (Broadcast.getNode())
6823 unsigned EVTBits = ExtVT.getSizeInBits();
6825 unsigned NumZero = 0;
6826 unsigned NumNonZero = 0;
6827 unsigned NonZeros = 0;
6828 bool IsAllConstants = true;
6829 SmallSet<SDValue, 8> Values;
6830 for (unsigned i = 0; i < NumElems; ++i) {
6831 SDValue Elt = Op.getOperand(i);
6832 if (Elt.getOpcode() == ISD::UNDEF)
6835 if (Elt.getOpcode() != ISD::Constant &&
6836 Elt.getOpcode() != ISD::ConstantFP)
6837 IsAllConstants = false;
6838 if (X86::isZeroNode(Elt))
6841 NonZeros |= (1 << i);
6846 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6847 if (NumNonZero == 0)
6848 return DAG.getUNDEF(VT);
6850 // Special case for single non-zero, non-undef, element.
6851 if (NumNonZero == 1) {
6852 unsigned Idx = countTrailingZeros(NonZeros);
6853 SDValue Item = Op.getOperand(Idx);
6855 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6856 // the value are obviously zero, truncate the value to i32 and do the
6857 // insertion that way. Only do this if the value is non-constant or if the
6858 // value is a constant being inserted into element 0. It is cheaper to do
6859 // a constant pool load than it is to do a movd + shuffle.
6860 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6861 (!IsAllConstants || Idx == 0)) {
6862 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6864 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6865 EVT VecVT = MVT::v4i32;
6866 unsigned VecElts = 4;
6868 // Truncate the value (which may itself be a constant) to i32, and
6869 // convert it to a vector with movd (S2V+shuffle to zero extend).
6870 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6871 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6873 // If using the new shuffle lowering, just directly insert this.
6874 if (ExperimentalVectorShuffleLowering)
6876 ISD::BITCAST, dl, VT,
6877 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6879 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6881 // Now we have our 32-bit value zero extended in the low element of
6882 // a vector. If Idx != 0, swizzle it into place.
6884 SmallVector<int, 4> Mask;
6885 Mask.push_back(Idx);
6886 for (unsigned i = 1; i != VecElts; ++i)
6888 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6891 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6895 // If we have a constant or non-constant insertion into the low element of
6896 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6897 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6898 // depending on what the source datatype is.
6901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6903 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6904 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6905 if (VT.is256BitVector() || VT.is512BitVector()) {
6906 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6907 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6908 Item, DAG.getIntPtrConstant(0));
6910 assert(VT.is128BitVector() && "Expected an SSE value type!");
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6912 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6913 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6916 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6917 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6918 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6919 if (VT.is256BitVector()) {
6920 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6921 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6923 assert(VT.is128BitVector() && "Expected an SSE value type!");
6924 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6926 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6930 // Is it a vector logical left shift?
6931 if (NumElems == 2 && Idx == 1 &&
6932 X86::isZeroNode(Op.getOperand(0)) &&
6933 !X86::isZeroNode(Op.getOperand(1))) {
6934 unsigned NumBits = VT.getSizeInBits();
6935 return getVShift(true, VT,
6936 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6937 VT, Op.getOperand(1)),
6938 NumBits/2, DAG, *this, dl);
6941 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6944 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6945 // is a non-constant being inserted into an element other than the low one,
6946 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6947 // movd/movss) to move this into the low element, then shuffle it into
6949 if (EVTBits == 32) {
6950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6952 // If using the new shuffle lowering, just directly insert this.
6953 if (ExperimentalVectorShuffleLowering)
6954 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6956 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6957 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6958 SmallVector<int, 8> MaskVec;
6959 for (unsigned i = 0; i != NumElems; ++i)
6960 MaskVec.push_back(i == Idx ? 0 : 1);
6961 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6965 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6966 if (Values.size() == 1) {
6967 if (EVTBits == 32) {
6968 // Instead of a shuffle like this:
6969 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6970 // Check if it's possible to issue this instead.
6971 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue Item = Op.getOperand(Idx);
6974 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6975 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6980 // A vector full of immediates; various special cases are already
6981 // handled, so this is best done with a single constant-pool load.
6985 // For AVX-length vectors, build the individual 128-bit pieces and use
6986 // shuffles to put them in place.
6987 if (VT.is256BitVector() || VT.is512BitVector()) {
6988 SmallVector<SDValue, 64> V;
6989 for (unsigned i = 0; i != NumElems; ++i)
6990 V.push_back(Op.getOperand(i));
6992 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6994 // Build both the lower and upper subvector.
6995 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6996 makeArrayRef(&V[0], NumElems/2));
6997 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6998 makeArrayRef(&V[NumElems / 2], NumElems/2));
7000 // Recreate the wider vector with the lower and upper part.
7001 if (VT.is256BitVector())
7002 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7003 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7006 // Let legalizer expand 2-wide build_vectors.
7007 if (EVTBits == 64) {
7008 if (NumNonZero == 1) {
7009 // One half is zero or undef.
7010 unsigned Idx = countTrailingZeros(NonZeros);
7011 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7012 Op.getOperand(Idx));
7013 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7018 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7019 if (EVTBits == 8 && NumElems == 16) {
7020 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7022 if (V.getNode()) return V;
7025 if (EVTBits == 16 && NumElems == 8) {
7026 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7028 if (V.getNode()) return V;
7031 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7032 if (EVTBits == 32 && NumElems == 4) {
7033 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7038 // If element VT is == 32 bits, turn it into a number of shuffles.
7039 SmallVector<SDValue, 8> V(NumElems);
7040 if (NumElems == 4 && NumZero > 0) {
7041 for (unsigned i = 0; i < 4; ++i) {
7042 bool isZero = !(NonZeros & (1 << i));
7044 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 for (unsigned i = 0; i < 2; ++i) {
7050 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7053 V[i] = V[i*2]; // Must be a zero vector.
7056 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7059 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7062 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7067 bool Reverse1 = (NonZeros & 0x3) == 2;
7068 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7072 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7073 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7075 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7078 if (Values.size() > 1 && VT.is128BitVector()) {
7079 // Check for a build vector of consecutive loads.
7080 for (unsigned i = 0; i < NumElems; ++i)
7081 V[i] = Op.getOperand(i);
7083 // Check for elements which are consecutive loads.
7084 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7088 // Check for a build vector from mostly shuffle plus few inserting.
7089 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7093 // For SSE 4.1, use insertps to put the high elements into the low element.
7094 if (getSubtarget()->hasSSE41()) {
7096 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7097 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7099 Result = DAG.getUNDEF(VT);
7101 for (unsigned i = 1; i < NumElems; ++i) {
7102 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7103 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7104 Op.getOperand(i), DAG.getIntPtrConstant(i));
7109 // Otherwise, expand into a number of unpckl*, start by extending each of
7110 // our (non-undef) elements to the full vector width with the element in the
7111 // bottom slot of the vector (which generates no code for SSE).
7112 for (unsigned i = 0; i < NumElems; ++i) {
7113 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7114 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7116 V[i] = DAG.getUNDEF(VT);
7119 // Next, we iteratively mix elements, e.g. for v4f32:
7120 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7121 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7122 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7123 unsigned EltStride = NumElems >> 1;
7124 while (EltStride != 0) {
7125 for (unsigned i = 0; i < EltStride; ++i) {
7126 // If V[i+EltStride] is undef and this is the first round of mixing,
7127 // then it is safe to just drop this shuffle: V[i] is already in the
7128 // right place, the one element (since it's the first round) being
7129 // inserted as undef can be dropped. This isn't safe for successive
7130 // rounds because they will permute elements within both vectors.
7131 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7132 EltStride == NumElems/2)
7135 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7144 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7145 // to create 256-bit vectors from two other 128-bit ones.
7146 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7148 MVT ResVT = Op.getSimpleValueType();
7150 assert((ResVT.is256BitVector() ||
7151 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7153 SDValue V1 = Op.getOperand(0);
7154 SDValue V2 = Op.getOperand(1);
7155 unsigned NumElems = ResVT.getVectorNumElements();
7156 if(ResVT.is256BitVector())
7157 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7159 if (Op.getNumOperands() == 4) {
7160 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7161 ResVT.getVectorNumElements()/2);
7162 SDValue V3 = Op.getOperand(2);
7163 SDValue V4 = Op.getOperand(3);
7164 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7165 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7167 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7170 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7171 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7172 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7173 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7174 Op.getNumOperands() == 4)));
7176 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7177 // from two other 128-bit ones.
7179 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7180 return LowerAVXCONCAT_VECTORS(Op, DAG);
7184 //===----------------------------------------------------------------------===//
7185 // Vector shuffle lowering
7187 // This is an experimental code path for lowering vector shuffles on x86. It is
7188 // designed to handle arbitrary vector shuffles and blends, gracefully
7189 // degrading performance as necessary. It works hard to recognize idiomatic
7190 // shuffles and lower them to optimal instruction patterns without leaving
7191 // a framework that allows reasonably efficient handling of all vector shuffle
7193 //===----------------------------------------------------------------------===//
7195 /// \brief Tiny helper function to identify a no-op mask.
7197 /// This is a somewhat boring predicate function. It checks whether the mask
7198 /// array input, which is assumed to be a single-input shuffle mask of the kind
7199 /// used by the X86 shuffle instructions (not a fully general
7200 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7201 /// in-place shuffle are 'no-op's.
7202 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7203 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7204 if (Mask[i] != -1 && Mask[i] != i)
7209 /// \brief Helper function to classify a mask as a single-input mask.
7211 /// This isn't a generic single-input test because in the vector shuffle
7212 /// lowering we canonicalize single inputs to be the first input operand. This
7213 /// means we can more quickly test for a single input by only checking whether
7214 /// an input from the second operand exists. We also assume that the size of
7215 /// mask corresponds to the size of the input vectors which isn't true in the
7216 /// fully general case.
7217 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7219 if (M >= (int)Mask.size())
7224 /// \brief Test whether there are elements crossing 128-bit lanes in this
7227 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7228 /// and we routinely test for these.
7229 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7230 int LaneSize = 128 / VT.getScalarSizeInBits();
7231 int Size = Mask.size();
7232 for (int i = 0; i < Size; ++i)
7233 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7238 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7240 /// This checks a shuffle mask to see if it is performing the same
7241 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7242 /// that it is also not lane-crossing. It may however involve a blend from the
7243 /// same lane of a second vector.
7245 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7246 /// non-trivial to compute in the face of undef lanes. The representation is
7247 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7248 /// entries from both V1 and V2 inputs to the wider mask.
7250 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7251 SmallVectorImpl<int> &RepeatedMask) {
7252 int LaneSize = 128 / VT.getScalarSizeInBits();
7253 RepeatedMask.resize(LaneSize, -1);
7254 int Size = Mask.size();
7255 for (int i = 0; i < Size; ++i) {
7258 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7259 // This entry crosses lanes, so there is no way to model this shuffle.
7262 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7263 if (RepeatedMask[i % LaneSize] == -1)
7264 // This is the first non-undef entry in this slot of a 128-bit lane.
7265 RepeatedMask[i % LaneSize] =
7266 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7267 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7268 // Found a mismatch with the repeated mask.
7274 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7275 // 2013 will allow us to use it as a non-type template parameter.
7278 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7280 /// See its documentation for details.
7281 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7282 if (Mask.size() != Args.size())
7284 for (int i = 0, e = Mask.size(); i < e; ++i) {
7285 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7286 if (Mask[i] != -1 && Mask[i] != *Args[i])
7294 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7297 /// This is a fast way to test a shuffle mask against a fixed pattern:
7299 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7301 /// It returns true if the mask is exactly as wide as the argument list, and
7302 /// each element of the mask is either -1 (signifying undef) or the value given
7303 /// in the argument.
7304 static const VariadicFunction1<
7305 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7307 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7309 /// This helper function produces an 8-bit shuffle immediate corresponding to
7310 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7311 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7314 /// NB: We rely heavily on "undef" masks preserving the input lane.
7315 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7316 SelectionDAG &DAG) {
7317 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7318 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7319 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7320 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7321 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7324 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7325 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7326 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7327 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7328 return DAG.getConstant(Imm, MVT::i8);
7331 /// \brief Try to emit a blend instruction for a shuffle.
7333 /// This doesn't do any checks for the availability of instructions for blending
7334 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7335 /// be matched in the backend with the type given. What it does check for is
7336 /// that the shuffle mask is in fact a blend.
7337 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7338 SDValue V2, ArrayRef<int> Mask,
7339 const X86Subtarget *Subtarget,
7340 SelectionDAG &DAG) {
7342 unsigned BlendMask = 0;
7343 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7344 if (Mask[i] >= Size) {
7345 if (Mask[i] != i + Size)
7346 return SDValue(); // Shuffled V2 input!
7347 BlendMask |= 1u << i;
7350 if (Mask[i] >= 0 && Mask[i] != i)
7351 return SDValue(); // Shuffled V1 input!
7353 switch (VT.SimpleTy) {
7358 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7359 DAG.getConstant(BlendMask, MVT::i8));
7363 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7368 // that instruction.
7369 if (Subtarget->hasAVX2()) {
7370 // Scale the blend by the number of 32-bit dwords per element.
7371 int Scale = VT.getScalarSizeInBits() / 32;
7373 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7374 if (Mask[i] >= Size)
7375 for (int j = 0; j < Scale; ++j)
7376 BlendMask |= 1u << (i * Scale + j);
7378 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7379 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7380 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7381 return DAG.getNode(ISD::BITCAST, DL, VT,
7382 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7383 DAG.getConstant(BlendMask, MVT::i8)));
7387 // For integer shuffles we need to expand the mask and cast the inputs to
7388 // v8i16s prior to blending.
7389 int Scale = 8 / VT.getVectorNumElements();
7391 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7392 if (Mask[i] >= Size)
7393 for (int j = 0; j < Scale; ++j)
7394 BlendMask |= 1u << (i * Scale + j);
7396 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7397 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7398 return DAG.getNode(ISD::BITCAST, DL, VT,
7399 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7400 DAG.getConstant(BlendMask, MVT::i8)));
7404 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7405 SmallVector<int, 8> RepeatedMask;
7406 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7407 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7408 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7410 for (int i = 0; i < 8; ++i)
7411 if (RepeatedMask[i] >= 16)
7412 BlendMask |= 1u << i;
7413 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7414 DAG.getConstant(BlendMask, MVT::i8));
7419 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7420 // Scale the blend by the number of bytes per element.
7421 int Scale = VT.getScalarSizeInBits() / 8;
7422 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7424 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7425 // mix of LLVM's code generator and the x86 backend. We tell the code
7426 // generator that boolean values in the elements of an x86 vector register
7427 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7428 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7429 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7430 // of the element (the remaining are ignored) and 0 in that high bit would
7431 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7432 // the LLVM model for boolean values in vector elements gets the relevant
7433 // bit set, it is set backwards and over constrained relative to x86's
7435 SDValue VSELECTMask[32];
7436 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7437 for (int j = 0; j < Scale; ++j)
7438 VSELECTMask[Scale * i + j] =
7439 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7440 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7442 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7443 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7445 ISD::BITCAST, DL, VT,
7446 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7447 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7452 llvm_unreachable("Not a supported integer vector type!");
7456 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7457 /// unblended shuffles followed by an unshuffled blend.
7459 /// This matches the extremely common pattern for handling combined
7460 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7462 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7466 SelectionDAG &DAG) {
7467 // Shuffle the input elements into the desired positions in V1 and V2 and
7468 // blend them together.
7469 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7470 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7471 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7472 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7473 if (Mask[i] >= 0 && Mask[i] < Size) {
7474 V1Mask[i] = Mask[i];
7476 } else if (Mask[i] >= Size) {
7477 V2Mask[i] = Mask[i] - Size;
7478 BlendMask[i] = i + Size;
7481 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7482 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7483 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7486 /// \brief Try to lower a vector shuffle as a byte rotation.
7488 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7489 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7490 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7491 /// try to generically lower a vector shuffle through such an pattern. It
7492 /// does not check for the profitability of lowering either as PALIGNR or
7493 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7494 /// This matches shuffle vectors that look like:
7496 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7498 /// Essentially it concatenates V1 and V2, shifts right by some number of
7499 /// elements, and takes the low elements as the result. Note that while this is
7500 /// specified as a *right shift* because x86 is little-endian, it is a *left
7501 /// rotate* of the vector lanes.
7503 /// Note that this only handles 128-bit vector widths currently.
7504 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7507 const X86Subtarget *Subtarget,
7508 SelectionDAG &DAG) {
7509 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7511 // We need to detect various ways of spelling a rotation:
7512 // [11, 12, 13, 14, 15, 0, 1, 2]
7513 // [-1, 12, 13, 14, -1, -1, 1, -1]
7514 // [-1, -1, -1, -1, -1, -1, 1, 2]
7515 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7516 // [-1, 4, 5, 6, -1, -1, 9, -1]
7517 // [-1, 4, 5, 6, -1, -1, -1, -1]
7520 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7523 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7525 // Based on the mod-Size value of this mask element determine where
7526 // a rotated vector would have started.
7527 int StartIdx = i - (Mask[i] % Size);
7529 // The identity rotation isn't interesting, stop.
7532 // If we found the tail of a vector the rotation must be the missing
7533 // front. If we found the head of a vector, it must be how much of the head.
7534 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7537 Rotation = CandidateRotation;
7538 else if (Rotation != CandidateRotation)
7539 // The rotations don't match, so we can't match this mask.
7542 // Compute which value this mask is pointing at.
7543 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7545 // Compute which of the two target values this index should be assigned to.
7546 // This reflects whether the high elements are remaining or the low elements
7548 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7550 // Either set up this value if we've not encountered it before, or check
7551 // that it remains consistent.
7554 else if (TargetV != MaskV)
7555 // This may be a rotation, but it pulls from the inputs in some
7556 // unsupported interleaving.
7560 // Check that we successfully analyzed the mask, and normalize the results.
7561 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7562 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7568 assert(VT.getSizeInBits() == 128 &&
7569 "Rotate-based lowering only supports 128-bit lowering!");
7570 assert(Mask.size() <= 16 &&
7571 "Can shuffle at most 16 bytes in a 128-bit vector!");
7573 // The actual rotate instruction rotates bytes, so we need to scale the
7574 // rotation based on how many bytes are in the vector.
7575 int Scale = 16 / Mask.size();
7577 // SSSE3 targets can use the palignr instruction
7578 if (Subtarget->hasSSSE3()) {
7579 // Cast the inputs to v16i8 to match PALIGNR.
7580 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7581 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7583 return DAG.getNode(ISD::BITCAST, DL, VT,
7584 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7585 DAG.getConstant(Rotation * Scale, MVT::i8)));
7588 // Default SSE2 implementation
7589 int LoByteShift = 16 - Rotation * Scale;
7590 int HiByteShift = Rotation * Scale;
7592 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7593 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7594 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7596 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7597 DAG.getConstant(8 * LoByteShift, MVT::i8));
7598 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7599 DAG.getConstant(8 * HiByteShift, MVT::i8));
7600 return DAG.getNode(ISD::BITCAST, DL, VT,
7601 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7604 /// \brief Compute whether each element of a shuffle is zeroable.
7606 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7607 /// Either it is an undef element in the shuffle mask, the element of the input
7608 /// referenced is undef, or the element of the input referenced is known to be
7609 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7610 /// as many lanes with this technique as possible to simplify the remaining
7612 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7613 SDValue V1, SDValue V2) {
7614 SmallBitVector Zeroable(Mask.size(), false);
7616 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7617 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7619 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7621 // Handle the easy cases.
7622 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7627 // If this is an index into a build_vector node, dig out the input value and
7629 SDValue V = M < Size ? V1 : V2;
7630 if (V.getOpcode() != ISD::BUILD_VECTOR)
7633 SDValue Input = V.getOperand(M % Size);
7634 // The UNDEF opcode check really should be dead code here, but not quite
7635 // worth asserting on (it isn't invalid, just unexpected).
7636 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7643 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7645 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7646 /// byte-shift instructions. The mask must consist of a shifted sequential
7647 /// shuffle from one of the input vectors and zeroable elements for the
7648 /// remaining 'shifted in' elements.
7650 /// Note that this only handles 128-bit vector widths currently.
7651 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7652 SDValue V2, ArrayRef<int> Mask,
7653 SelectionDAG &DAG) {
7654 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7656 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7658 int Size = Mask.size();
7659 int Scale = 16 / Size;
7661 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7662 ArrayRef<int> Mask) {
7663 for (int i = StartIndex; i < EndIndex; i++) {
7666 if (i + Base != Mask[i] - MaskOffset)
7672 for (int Shift = 1; Shift < Size; Shift++) {
7673 int ByteShift = Shift * Scale;
7675 // PSRLDQ : (little-endian) right byte shift
7676 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7677 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7678 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7679 bool ZeroableRight = true;
7680 for (int i = Size - Shift; i < Size; i++) {
7681 ZeroableRight &= Zeroable[i];
7684 if (ZeroableRight) {
7685 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7686 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7688 if (ValidShiftRight1 || ValidShiftRight2) {
7689 // Cast the inputs to v2i64 to match PSRLDQ.
7690 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7691 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7692 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7693 DAG.getConstant(ByteShift * 8, MVT::i8));
7694 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7698 // PSLLDQ : (little-endian) left byte shift
7699 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7700 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7701 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7702 bool ZeroableLeft = true;
7703 for (int i = 0; i < Shift; i++) {
7704 ZeroableLeft &= Zeroable[i];
7708 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7709 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7711 if (ValidShiftLeft1 || ValidShiftLeft2) {
7712 // Cast the inputs to v2i64 to match PSLLDQ.
7713 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7714 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7715 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7716 DAG.getConstant(ByteShift * 8, MVT::i8));
7717 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7725 /// \brief Lower a vector shuffle as a zero or any extension.
7727 /// Given a specific number of elements, element bit width, and extension
7728 /// stride, produce either a zero or any extension based on the available
7729 /// features of the subtarget.
7730 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7731 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7732 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7733 assert(Scale > 1 && "Need a scale to extend.");
7734 int EltBits = VT.getSizeInBits() / NumElements;
7735 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7736 "Only 8, 16, and 32 bit elements can be extended.");
7737 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7739 // Found a valid zext mask! Try various lowering strategies based on the
7740 // input type and available ISA extensions.
7741 if (Subtarget->hasSSE41()) {
7742 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7743 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7744 NumElements / Scale);
7745 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7746 return DAG.getNode(ISD::BITCAST, DL, VT,
7747 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7750 // For any extends we can cheat for larger element sizes and use shuffle
7751 // instructions that can fold with a load and/or copy.
7752 if (AnyExt && EltBits == 32) {
7753 int PSHUFDMask[4] = {0, -1, 1, -1};
7755 ISD::BITCAST, DL, VT,
7756 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7757 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7758 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7760 if (AnyExt && EltBits == 16 && Scale > 2) {
7761 int PSHUFDMask[4] = {0, -1, 0, -1};
7762 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7763 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7764 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7765 int PSHUFHWMask[4] = {1, -1, -1, -1};
7767 ISD::BITCAST, DL, VT,
7768 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7769 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7770 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7773 // If this would require more than 2 unpack instructions to expand, use
7774 // pshufb when available. We can only use more than 2 unpack instructions
7775 // when zero extending i8 elements which also makes it easier to use pshufb.
7776 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7777 assert(NumElements == 16 && "Unexpected byte vector width!");
7778 SDValue PSHUFBMask[16];
7779 for (int i = 0; i < 16; ++i)
7781 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7782 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7783 return DAG.getNode(ISD::BITCAST, DL, VT,
7784 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7785 DAG.getNode(ISD::BUILD_VECTOR, DL,
7786 MVT::v16i8, PSHUFBMask)));
7789 // Otherwise emit a sequence of unpacks.
7791 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7792 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7793 : getZeroVector(InputVT, Subtarget, DAG, DL);
7794 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7795 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7799 } while (Scale > 1);
7800 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7803 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7805 /// This routine will try to do everything in its power to cleverly lower
7806 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7807 /// check for the profitability of this lowering, it tries to aggressively
7808 /// match this pattern. It will use all of the micro-architectural details it
7809 /// can to emit an efficient lowering. It handles both blends with all-zero
7810 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7811 /// masking out later).
7813 /// The reason we have dedicated lowering for zext-style shuffles is that they
7814 /// are both incredibly common and often quite performance sensitive.
7815 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7816 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7817 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7818 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7820 int Bits = VT.getSizeInBits();
7821 int NumElements = Mask.size();
7823 // Define a helper function to check a particular ext-scale and lower to it if
7825 auto Lower = [&](int Scale) -> SDValue {
7828 for (int i = 0; i < NumElements; ++i) {
7830 continue; // Valid anywhere but doesn't tell us anything.
7831 if (i % Scale != 0) {
7832 // Each of the extend elements needs to be zeroable.
7836 // We no lorger are in the anyext case.
7841 // Each of the base elements needs to be consecutive indices into the
7842 // same input vector.
7843 SDValue V = Mask[i] < NumElements ? V1 : V2;
7846 else if (InputV != V)
7847 return SDValue(); // Flip-flopping inputs.
7849 if (Mask[i] % NumElements != i / Scale)
7850 return SDValue(); // Non-consecutive strided elemenst.
7853 // If we fail to find an input, we have a zero-shuffle which should always
7854 // have already been handled.
7855 // FIXME: Maybe handle this here in case during blending we end up with one?
7859 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7860 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7863 // The widest scale possible for extending is to a 64-bit integer.
7864 assert(Bits % 64 == 0 &&
7865 "The number of bits in a vector must be divisible by 64 on x86!");
7866 int NumExtElements = Bits / 64;
7868 // Each iteration, try extending the elements half as much, but into twice as
7870 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7871 assert(NumElements % NumExtElements == 0 &&
7872 "The input vector size must be divisble by the extended size.");
7873 if (SDValue V = Lower(NumElements / NumExtElements))
7877 // No viable ext lowering found.
7881 /// \brief Try to get a scalar value for a specific element of a vector.
7883 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7884 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7885 SelectionDAG &DAG) {
7886 MVT VT = V.getSimpleValueType();
7887 MVT EltVT = VT.getVectorElementType();
7888 while (V.getOpcode() == ISD::BITCAST)
7889 V = V.getOperand(0);
7890 // If the bitcasts shift the element size, we can't extract an equivalent
7892 MVT NewVT = V.getSimpleValueType();
7893 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7896 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7897 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7898 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7903 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7905 /// This is particularly important because the set of instructions varies
7906 /// significantly based on whether the operand is a load or not.
7907 static bool isShuffleFoldableLoad(SDValue V) {
7908 while (V.getOpcode() == ISD::BITCAST)
7909 V = V.getOperand(0);
7911 return ISD::isNON_EXTLoad(V.getNode());
7914 /// \brief Try to lower insertion of a single element into a zero vector.
7916 /// This is a common pattern that we have especially efficient patterns to lower
7917 /// across all subtarget feature sets.
7918 static SDValue lowerVectorShuffleAsElementInsertion(
7919 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7920 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7921 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7923 MVT EltVT = VT.getVectorElementType();
7925 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7926 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7928 bool IsV1Zeroable = true;
7929 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7930 if (i != V2Index && !Zeroable[i]) {
7931 IsV1Zeroable = false;
7935 // Check for a single input from a SCALAR_TO_VECTOR node.
7936 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7937 // all the smarts here sunk into that routine. However, the current
7938 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7939 // vector shuffle lowering is dead.
7940 if (SDValue V2S = getScalarValueForVectorElement(
7941 V2, Mask[V2Index] - Mask.size(), DAG)) {
7942 // We need to zext the scalar if it is smaller than an i32.
7943 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7944 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7945 // Using zext to expand a narrow element won't work for non-zero
7950 // Zero-extend directly to i32.
7952 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7954 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7955 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7956 EltVT == MVT::i16) {
7957 // Either not inserting from the low element of the input or the input
7958 // element size is too small to use VZEXT_MOVL to clear the high bits.
7962 if (!IsV1Zeroable) {
7963 // If V1 can't be treated as a zero vector we have fewer options to lower
7964 // this. We can't support integer vectors or non-zero targets cheaply, and
7965 // the V1 elements can't be permuted in any way.
7966 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7967 if (!VT.isFloatingPoint() || V2Index != 0)
7969 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7970 V1Mask[V2Index] = -1;
7971 if (!isNoopShuffleMask(V1Mask))
7973 // This is essentially a special case blend operation, but if we have
7974 // general purpose blend operations, they are always faster. Bail and let
7975 // the rest of the lowering handle these as blends.
7976 if (Subtarget->hasSSE41())
7979 // Otherwise, use MOVSD or MOVSS.
7980 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7981 "Only two types of floating point element types to handle!");
7982 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7986 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7988 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7991 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7992 // the desired position. Otherwise it is more efficient to do a vector
7993 // shift left. We know that we can do a vector shift left because all
7994 // the inputs are zero.
7995 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7996 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7997 V2Shuffle[V2Index] = 0;
7998 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8000 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8002 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8004 V2Index * EltVT.getSizeInBits(),
8005 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8006 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8012 /// \brief Try to lower broadcast of a single element.
8014 /// For convenience, this code also bundles all of the subtarget feature set
8015 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8016 /// a convenient way to factor it out.
8017 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8019 const X86Subtarget *Subtarget,
8020 SelectionDAG &DAG) {
8021 if (!Subtarget->hasAVX())
8023 if (VT.isInteger() && !Subtarget->hasAVX2())
8026 // Check that the mask is a broadcast.
8027 int BroadcastIdx = -1;
8029 if (M >= 0 && BroadcastIdx == -1)
8031 else if (M >= 0 && M != BroadcastIdx)
8034 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8035 "a sorted mask where the broadcast "
8038 // Go up the chain of (vector) values to try and find a scalar load that
8039 // we can combine with the broadcast.
8041 switch (V.getOpcode()) {
8042 case ISD::CONCAT_VECTORS: {
8043 int OperandSize = Mask.size() / V.getNumOperands();
8044 V = V.getOperand(BroadcastIdx / OperandSize);
8045 BroadcastIdx %= OperandSize;
8049 case ISD::INSERT_SUBVECTOR: {
8050 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8051 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8055 int BeginIdx = (int)ConstantIdx->getZExtValue();
8057 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8058 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8059 BroadcastIdx -= BeginIdx;
8070 // Check if this is a broadcast of a scalar. We special case lowering
8071 // for scalars so that we can more effectively fold with loads.
8072 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8073 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8074 V = V.getOperand(BroadcastIdx);
8076 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8078 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8080 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8081 // We can't broadcast from a vector register w/o AVX2, and we can only
8082 // broadcast from the zero-element of a vector register.
8086 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8089 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8091 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8092 /// support for floating point shuffles but not integer shuffles. These
8093 /// instructions will incur a domain crossing penalty on some chips though so
8094 /// it is better to avoid lowering through this for integer vectors where
8096 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8097 const X86Subtarget *Subtarget,
8098 SelectionDAG &DAG) {
8100 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8101 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8102 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8104 ArrayRef<int> Mask = SVOp->getMask();
8105 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8107 if (isSingleInputShuffleMask(Mask)) {
8108 // Straight shuffle of a single input vector. Simulate this by using the
8109 // single input as both of the "inputs" to this instruction..
8110 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8112 if (Subtarget->hasAVX()) {
8113 // If we have AVX, we can use VPERMILPS which will allow folding a load
8114 // into the shuffle.
8115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8116 DAG.getConstant(SHUFPDMask, MVT::i8));
8119 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8120 DAG.getConstant(SHUFPDMask, MVT::i8));
8122 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8123 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8125 // Use dedicated unpack instructions for masks that match their pattern.
8126 if (isShuffleEquivalent(Mask, 0, 2))
8127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8128 if (isShuffleEquivalent(Mask, 1, 3))
8129 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8131 // If we have a single input, insert that into V1 if we can do so cheaply.
8132 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8133 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8134 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8136 // Try inverting the insertion since for v2 masks it is easy to do and we
8137 // can't reliably sort the mask one way or the other.
8138 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8139 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8140 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8141 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8145 // Try to use one of the special instruction patterns to handle two common
8146 // blend patterns if a zero-blend above didn't work.
8147 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8148 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8149 // We can either use a special instruction to load over the low double or
8150 // to move just the low double.
8152 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8154 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8156 if (Subtarget->hasSSE41())
8157 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8161 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8162 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8163 DAG.getConstant(SHUFPDMask, MVT::i8));
8166 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8168 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8169 /// the integer unit to minimize domain crossing penalties. However, for blends
8170 /// it falls back to the floating point shuffle operation with appropriate bit
8172 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8173 const X86Subtarget *Subtarget,
8174 SelectionDAG &DAG) {
8176 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8177 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8178 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8180 ArrayRef<int> Mask = SVOp->getMask();
8181 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8183 if (isSingleInputShuffleMask(Mask)) {
8184 // Check for being able to broadcast a single element.
8185 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8186 Mask, Subtarget, DAG))
8189 // Straight shuffle of a single input vector. For everything from SSE2
8190 // onward this has a single fast instruction with no scary immediates.
8191 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8192 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8193 int WidenedMask[4] = {
8194 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8195 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8197 ISD::BITCAST, DL, MVT::v2i64,
8198 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8199 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8202 // Try to use byte shift instructions.
8203 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8204 DL, MVT::v2i64, V1, V2, Mask, DAG))
8207 // If we have a single input from V2 insert that into V1 if we can do so
8209 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8210 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8211 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8213 // Try inverting the insertion since for v2 masks it is easy to do and we
8214 // can't reliably sort the mask one way or the other.
8215 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8216 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8217 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8218 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8222 // Use dedicated unpack instructions for masks that match their pattern.
8223 if (isShuffleEquivalent(Mask, 0, 2))
8224 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8225 if (isShuffleEquivalent(Mask, 1, 3))
8226 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8228 if (Subtarget->hasSSE41())
8229 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8233 // Try to use byte rotation instructions.
8234 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8235 if (Subtarget->hasSSSE3())
8236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8237 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8240 // We implement this with SHUFPD which is pretty lame because it will likely
8241 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8242 // However, all the alternatives are still more cycles and newer chips don't
8243 // have this problem. It would be really nice if x86 had better shuffles here.
8244 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8245 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8246 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8247 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8250 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8252 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8253 /// It makes no assumptions about whether this is the *best* lowering, it simply
8255 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8256 ArrayRef<int> Mask, SDValue V1,
8257 SDValue V2, SelectionDAG &DAG) {
8258 SDValue LowV = V1, HighV = V2;
8259 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8262 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8264 if (NumV2Elements == 1) {
8266 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8269 // Compute the index adjacent to V2Index and in the same half by toggling
8271 int V2AdjIndex = V2Index ^ 1;
8273 if (Mask[V2AdjIndex] == -1) {
8274 // Handles all the cases where we have a single V2 element and an undef.
8275 // This will only ever happen in the high lanes because we commute the
8276 // vector otherwise.
8278 std::swap(LowV, HighV);
8279 NewMask[V2Index] -= 4;
8281 // Handle the case where the V2 element ends up adjacent to a V1 element.
8282 // To make this work, blend them together as the first step.
8283 int V1Index = V2AdjIndex;
8284 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8285 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8286 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8288 // Now proceed to reconstruct the final blend as we have the necessary
8289 // high or low half formed.
8296 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8297 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8299 } else if (NumV2Elements == 2) {
8300 if (Mask[0] < 4 && Mask[1] < 4) {
8301 // Handle the easy case where we have V1 in the low lanes and V2 in the
8305 } else if (Mask[2] < 4 && Mask[3] < 4) {
8306 // We also handle the reversed case because this utility may get called
8307 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8308 // arrange things in the right direction.
8314 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8315 // trying to place elements directly, just blend them and set up the final
8316 // shuffle to place them.
8318 // The first two blend mask elements are for V1, the second two are for
8320 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8321 Mask[2] < 4 ? Mask[2] : Mask[3],
8322 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8323 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8324 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8325 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8327 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8330 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8331 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8332 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8333 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8336 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8337 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8340 /// \brief Lower 4-lane 32-bit floating point shuffles.
8342 /// Uses instructions exclusively from the floating point unit to minimize
8343 /// domain crossing penalties, as these are sufficient to implement all v4f32
8345 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8346 const X86Subtarget *Subtarget,
8347 SelectionDAG &DAG) {
8349 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8350 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8351 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8353 ArrayRef<int> Mask = SVOp->getMask();
8354 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8357 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8359 if (NumV2Elements == 0) {
8360 // Check for being able to broadcast a single element.
8361 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8362 Mask, Subtarget, DAG))
8365 if (Subtarget->hasAVX()) {
8366 // If we have AVX, we can use VPERMILPS which will allow folding a load
8367 // into the shuffle.
8368 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8369 getV4X86ShuffleImm8ForMask(Mask, DAG));
8372 // Otherwise, use a straight shuffle of a single input vector. We pass the
8373 // input vector to both operands to simulate this with a SHUFPS.
8374 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8375 getV4X86ShuffleImm8ForMask(Mask, DAG));
8378 // Use dedicated unpack instructions for masks that match their pattern.
8379 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8380 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8381 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8382 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8384 // There are special ways we can lower some single-element blends. However, we
8385 // have custom ways we can lower more complex single-element blends below that
8386 // we defer to if both this and BLENDPS fail to match, so restrict this to
8387 // when the V2 input is targeting element 0 of the mask -- that is the fast
8389 if (NumV2Elements == 1 && Mask[0] >= 4)
8390 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8391 Mask, Subtarget, DAG))
8394 if (Subtarget->hasSSE41())
8395 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8399 // Check for whether we can use INSERTPS to perform the blend. We only use
8400 // INSERTPS when the V1 elements are already in the correct locations
8401 // because otherwise we can just always use two SHUFPS instructions which
8402 // are much smaller to encode than a SHUFPS and an INSERTPS.
8403 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8405 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8408 // When using INSERTPS we can zero any lane of the destination. Collect
8409 // the zero inputs into a mask and drop them from the lanes of V1 which
8410 // actually need to be present as inputs to the INSERTPS.
8411 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8413 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8414 bool InsertNeedsShuffle = false;
8416 for (int i = 0; i < 4; ++i)
8420 } else if (Mask[i] != i) {
8421 InsertNeedsShuffle = true;
8426 // We don't want to use INSERTPS or other insertion techniques if it will
8427 // require shuffling anyways.
8428 if (!InsertNeedsShuffle) {
8429 // If all of V1 is zeroable, replace it with undef.
8430 if ((ZMask | 1 << V2Index) == 0xF)
8431 V1 = DAG.getUNDEF(MVT::v4f32);
8433 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8434 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8436 // Insert the V2 element into the desired position.
8437 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8438 DAG.getConstant(InsertPSMask, MVT::i8));
8442 // Otherwise fall back to a SHUFPS lowering strategy.
8443 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8446 /// \brief Lower 4-lane i32 vector shuffles.
8448 /// We try to handle these with integer-domain shuffles where we can, but for
8449 /// blends we use the floating point domain blend instructions.
8450 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8451 const X86Subtarget *Subtarget,
8452 SelectionDAG &DAG) {
8454 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8455 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8456 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8458 ArrayRef<int> Mask = SVOp->getMask();
8459 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8461 // Whenever we can lower this as a zext, that instruction is strictly faster
8462 // than any alternative. It also allows us to fold memory operands into the
8463 // shuffle in many cases.
8464 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8465 Mask, Subtarget, DAG))
8469 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8471 if (NumV2Elements == 0) {
8472 // Check for being able to broadcast a single element.
8473 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8474 Mask, Subtarget, DAG))
8477 // Straight shuffle of a single input vector. For everything from SSE2
8478 // onward this has a single fast instruction with no scary immediates.
8479 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8480 // but we aren't actually going to use the UNPCK instruction because doing
8481 // so prevents folding a load into this instruction or making a copy.
8482 const int UnpackLoMask[] = {0, 0, 1, 1};
8483 const int UnpackHiMask[] = {2, 2, 3, 3};
8484 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8485 Mask = UnpackLoMask;
8486 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8487 Mask = UnpackHiMask;
8489 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8490 getV4X86ShuffleImm8ForMask(Mask, DAG));
8493 // Try to use byte shift instructions.
8494 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8495 DL, MVT::v4i32, V1, V2, Mask, DAG))
8498 // There are special ways we can lower some single-element blends.
8499 if (NumV2Elements == 1)
8500 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8501 Mask, Subtarget, DAG))
8504 // Use dedicated unpack instructions for masks that match their pattern.
8505 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8506 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8507 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8508 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8510 if (Subtarget->hasSSE41())
8511 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8515 // Try to use byte rotation instructions.
8516 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8517 if (Subtarget->hasSSSE3())
8518 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8519 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8522 // We implement this with SHUFPS because it can blend from two vectors.
8523 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8524 // up the inputs, bypassing domain shift penalties that we would encur if we
8525 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8527 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8528 DAG.getVectorShuffle(
8530 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8534 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8535 /// shuffle lowering, and the most complex part.
8537 /// The lowering strategy is to try to form pairs of input lanes which are
8538 /// targeted at the same half of the final vector, and then use a dword shuffle
8539 /// to place them onto the right half, and finally unpack the paired lanes into
8540 /// their final position.
8542 /// The exact breakdown of how to form these dword pairs and align them on the
8543 /// correct sides is really tricky. See the comments within the function for
8544 /// more of the details.
8545 static SDValue lowerV8I16SingleInputVectorShuffle(
8546 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8547 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8548 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8549 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8550 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8552 SmallVector<int, 4> LoInputs;
8553 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8554 [](int M) { return M >= 0; });
8555 std::sort(LoInputs.begin(), LoInputs.end());
8556 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8557 SmallVector<int, 4> HiInputs;
8558 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8559 [](int M) { return M >= 0; });
8560 std::sort(HiInputs.begin(), HiInputs.end());
8561 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8563 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8564 int NumHToL = LoInputs.size() - NumLToL;
8566 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8567 int NumHToH = HiInputs.size() - NumLToH;
8568 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8569 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8570 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8571 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8573 // Check for being able to broadcast a single element.
8574 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8575 Mask, Subtarget, DAG))
8578 // Try to use byte shift instructions.
8579 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8580 DL, MVT::v8i16, V, V, Mask, DAG))
8583 // Use dedicated unpack instructions for masks that match their pattern.
8584 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8585 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8586 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8587 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8589 // Try to use byte rotation instructions.
8590 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8591 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8594 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8595 // such inputs we can swap two of the dwords across the half mark and end up
8596 // with <=2 inputs to each half in each half. Once there, we can fall through
8597 // to the generic code below. For example:
8599 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8600 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8602 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8603 // and an existing 2-into-2 on the other half. In this case we may have to
8604 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8605 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8606 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8607 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8608 // half than the one we target for fixing) will be fixed when we re-enter this
8609 // path. We will also combine away any sequence of PSHUFD instructions that
8610 // result into a single instruction. Here is an example of the tricky case:
8612 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8613 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8615 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8617 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8618 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8620 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8621 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8623 // The result is fine to be handled by the generic logic.
8624 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8625 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8626 int AOffset, int BOffset) {
8627 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8628 "Must call this with A having 3 or 1 inputs from the A half.");
8629 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8630 "Must call this with B having 1 or 3 inputs from the B half.");
8631 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8632 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8634 // Compute the index of dword with only one word among the three inputs in
8635 // a half by taking the sum of the half with three inputs and subtracting
8636 // the sum of the actual three inputs. The difference is the remaining
8639 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8640 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8641 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8642 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8643 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8644 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8645 int TripleNonInputIdx =
8646 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8647 TripleDWord = TripleNonInputIdx / 2;
8649 // We use xor with one to compute the adjacent DWord to whichever one the
8651 OneInputDWord = (OneInput / 2) ^ 1;
8653 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8654 // and BToA inputs. If there is also such a problem with the BToB and AToB
8655 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8656 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8657 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8658 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8659 // Compute how many inputs will be flipped by swapping these DWords. We
8661 // to balance this to ensure we don't form a 3-1 shuffle in the other
8663 int NumFlippedAToBInputs =
8664 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8666 int NumFlippedBToBInputs =
8667 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8669 if ((NumFlippedAToBInputs == 1 &&
8670 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8671 (NumFlippedBToBInputs == 1 &&
8672 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8673 // We choose whether to fix the A half or B half based on whether that
8674 // half has zero flipped inputs. At zero, we may not be able to fix it
8675 // with that half. We also bias towards fixing the B half because that
8676 // will more commonly be the high half, and we have to bias one way.
8677 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8678 ArrayRef<int> Inputs) {
8679 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8680 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8681 PinnedIdx ^ 1) != Inputs.end();
8682 // Determine whether the free index is in the flipped dword or the
8683 // unflipped dword based on where the pinned index is. We use this bit
8684 // in an xor to conditionally select the adjacent dword.
8685 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8686 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8687 FixFreeIdx) != Inputs.end();
8688 if (IsFixIdxInput == IsFixFreeIdxInput)
8690 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8691 FixFreeIdx) != Inputs.end();
8692 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8693 "We need to be changing the number of flipped inputs!");
8694 int PSHUFHalfMask[] = {0, 1, 2, 3};
8695 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8696 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8698 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8701 if (M != -1 && M == FixIdx)
8703 else if (M != -1 && M == FixFreeIdx)
8706 if (NumFlippedBToBInputs != 0) {
8708 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8709 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8711 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8713 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8714 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8719 int PSHUFDMask[] = {0, 1, 2, 3};
8720 PSHUFDMask[ADWord] = BDWord;
8721 PSHUFDMask[BDWord] = ADWord;
8722 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8723 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8724 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8725 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8727 // Adjust the mask to match the new locations of A and B.
8729 if (M != -1 && M/2 == ADWord)
8730 M = 2 * BDWord + M % 2;
8731 else if (M != -1 && M/2 == BDWord)
8732 M = 2 * ADWord + M % 2;
8734 // Recurse back into this routine to re-compute state now that this isn't
8735 // a 3 and 1 problem.
8736 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8739 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8740 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8741 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8742 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8744 // At this point there are at most two inputs to the low and high halves from
8745 // each half. That means the inputs can always be grouped into dwords and
8746 // those dwords can then be moved to the correct half with a dword shuffle.
8747 // We use at most one low and one high word shuffle to collect these paired
8748 // inputs into dwords, and finally a dword shuffle to place them.
8749 int PSHUFLMask[4] = {-1, -1, -1, -1};
8750 int PSHUFHMask[4] = {-1, -1, -1, -1};
8751 int PSHUFDMask[4] = {-1, -1, -1, -1};
8753 // First fix the masks for all the inputs that are staying in their
8754 // original halves. This will then dictate the targets of the cross-half
8756 auto fixInPlaceInputs =
8757 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8758 MutableArrayRef<int> SourceHalfMask,
8759 MutableArrayRef<int> HalfMask, int HalfOffset) {
8760 if (InPlaceInputs.empty())
8762 if (InPlaceInputs.size() == 1) {
8763 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8764 InPlaceInputs[0] - HalfOffset;
8765 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8768 if (IncomingInputs.empty()) {
8769 // Just fix all of the in place inputs.
8770 for (int Input : InPlaceInputs) {
8771 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8772 PSHUFDMask[Input / 2] = Input / 2;
8777 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8778 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8779 InPlaceInputs[0] - HalfOffset;
8780 // Put the second input next to the first so that they are packed into
8781 // a dword. We find the adjacent index by toggling the low bit.
8782 int AdjIndex = InPlaceInputs[0] ^ 1;
8783 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8784 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8785 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8787 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8788 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8790 // Now gather the cross-half inputs and place them into a free dword of
8791 // their target half.
8792 // FIXME: This operation could almost certainly be simplified dramatically to
8793 // look more like the 3-1 fixing operation.
8794 auto moveInputsToRightHalf = [&PSHUFDMask](
8795 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8796 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8797 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8799 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8800 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8802 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8804 int LowWord = Word & ~1;
8805 int HighWord = Word | 1;
8806 return isWordClobbered(SourceHalfMask, LowWord) ||
8807 isWordClobbered(SourceHalfMask, HighWord);
8810 if (IncomingInputs.empty())
8813 if (ExistingInputs.empty()) {
8814 // Map any dwords with inputs from them into the right half.
8815 for (int Input : IncomingInputs) {
8816 // If the source half mask maps over the inputs, turn those into
8817 // swaps and use the swapped lane.
8818 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8819 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8820 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8821 Input - SourceOffset;
8822 // We have to swap the uses in our half mask in one sweep.
8823 for (int &M : HalfMask)
8824 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8826 else if (M == Input)
8827 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8829 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8830 Input - SourceOffset &&
8831 "Previous placement doesn't match!");
8833 // Note that this correctly re-maps both when we do a swap and when
8834 // we observe the other side of the swap above. We rely on that to
8835 // avoid swapping the members of the input list directly.
8836 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8839 // Map the input's dword into the correct half.
8840 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8841 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8843 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8845 "Previous placement doesn't match!");
8848 // And just directly shift any other-half mask elements to be same-half
8849 // as we will have mirrored the dword containing the element into the
8850 // same position within that half.
8851 for (int &M : HalfMask)
8852 if (M >= SourceOffset && M < SourceOffset + 4) {
8853 M = M - SourceOffset + DestOffset;
8854 assert(M >= 0 && "This should never wrap below zero!");
8859 // Ensure we have the input in a viable dword of its current half. This
8860 // is particularly tricky because the original position may be clobbered
8861 // by inputs being moved and *staying* in that half.
8862 if (IncomingInputs.size() == 1) {
8863 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8864 int InputFixed = std::find(std::begin(SourceHalfMask),
8865 std::end(SourceHalfMask), -1) -
8866 std::begin(SourceHalfMask) + SourceOffset;
8867 SourceHalfMask[InputFixed - SourceOffset] =
8868 IncomingInputs[0] - SourceOffset;
8869 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8871 IncomingInputs[0] = InputFixed;
8873 } else if (IncomingInputs.size() == 2) {
8874 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8875 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8876 // We have two non-adjacent or clobbered inputs we need to extract from
8877 // the source half. To do this, we need to map them into some adjacent
8878 // dword slot in the source mask.
8879 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8880 IncomingInputs[1] - SourceOffset};
8882 // If there is a free slot in the source half mask adjacent to one of
8883 // the inputs, place the other input in it. We use (Index XOR 1) to
8884 // compute an adjacent index.
8885 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8886 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8887 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8888 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8889 InputsFixed[1] = InputsFixed[0] ^ 1;
8890 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8891 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8892 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8893 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8894 InputsFixed[0] = InputsFixed[1] ^ 1;
8895 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8896 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8897 // The two inputs are in the same DWord but it is clobbered and the
8898 // adjacent DWord isn't used at all. Move both inputs to the free
8900 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8902 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8903 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8905 // The only way we hit this point is if there is no clobbering
8906 // (because there are no off-half inputs to this half) and there is no
8907 // free slot adjacent to one of the inputs. In this case, we have to
8908 // swap an input with a non-input.
8909 for (int i = 0; i < 4; ++i)
8910 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8911 "We can't handle any clobbers here!");
8912 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8913 "Cannot have adjacent inputs here!");
8915 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8916 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8918 // We also have to update the final source mask in this case because
8919 // it may need to undo the above swap.
8920 for (int &M : FinalSourceHalfMask)
8921 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8922 M = InputsFixed[1] + SourceOffset;
8923 else if (M == InputsFixed[1] + SourceOffset)
8924 M = (InputsFixed[0] ^ 1) + SourceOffset;
8926 InputsFixed[1] = InputsFixed[0] ^ 1;
8929 // Point everything at the fixed inputs.
8930 for (int &M : HalfMask)
8931 if (M == IncomingInputs[0])
8932 M = InputsFixed[0] + SourceOffset;
8933 else if (M == IncomingInputs[1])
8934 M = InputsFixed[1] + SourceOffset;
8936 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8937 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8940 llvm_unreachable("Unhandled input size!");
8943 // Now hoist the DWord down to the right half.
8944 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8945 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8946 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8947 for (int &M : HalfMask)
8948 for (int Input : IncomingInputs)
8950 M = FreeDWord * 2 + Input % 2;
8952 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8953 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8954 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8955 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8957 // Now enact all the shuffles we've computed to move the inputs into their
8959 if (!isNoopShuffleMask(PSHUFLMask))
8960 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8961 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8962 if (!isNoopShuffleMask(PSHUFHMask))
8963 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8964 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8965 if (!isNoopShuffleMask(PSHUFDMask))
8966 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8967 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8968 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8969 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8971 // At this point, each half should contain all its inputs, and we can then
8972 // just shuffle them into their final position.
8973 assert(std::count_if(LoMask.begin(), LoMask.end(),
8974 [](int M) { return M >= 4; }) == 0 &&
8975 "Failed to lift all the high half inputs to the low mask!");
8976 assert(std::count_if(HiMask.begin(), HiMask.end(),
8977 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8978 "Failed to lift all the low half inputs to the high mask!");
8980 // Do a half shuffle for the low mask.
8981 if (!isNoopShuffleMask(LoMask))
8982 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8983 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8985 // Do a half shuffle with the high mask after shifting its values down.
8986 for (int &M : HiMask)
8989 if (!isNoopShuffleMask(HiMask))
8990 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8991 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8996 /// \brief Detect whether the mask pattern should be lowered through
8999 /// This essentially tests whether viewing the mask as an interleaving of two
9000 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9001 /// lowering it through interleaving is a significantly better strategy.
9002 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9003 int NumEvenInputs[2] = {0, 0};
9004 int NumOddInputs[2] = {0, 0};
9005 int NumLoInputs[2] = {0, 0};
9006 int NumHiInputs[2] = {0, 0};
9007 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9011 int InputIdx = Mask[i] >= Size;
9014 ++NumLoInputs[InputIdx];
9016 ++NumHiInputs[InputIdx];
9019 ++NumEvenInputs[InputIdx];
9021 ++NumOddInputs[InputIdx];
9024 // The minimum number of cross-input results for both the interleaved and
9025 // split cases. If interleaving results in fewer cross-input results, return
9027 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9028 NumEvenInputs[0] + NumOddInputs[1]);
9029 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9030 NumLoInputs[0] + NumHiInputs[1]);
9031 return InterleavedCrosses < SplitCrosses;
9034 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9036 /// This strategy only works when the inputs from each vector fit into a single
9037 /// half of that vector, and generally there are not so many inputs as to leave
9038 /// the in-place shuffles required highly constrained (and thus expensive). It
9039 /// shifts all the inputs into a single side of both input vectors and then
9040 /// uses an unpack to interleave these inputs in a single vector. At that
9041 /// point, we will fall back on the generic single input shuffle lowering.
9042 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9044 MutableArrayRef<int> Mask,
9045 const X86Subtarget *Subtarget,
9046 SelectionDAG &DAG) {
9047 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9048 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9050 for (int i = 0; i < 8; ++i)
9051 if (Mask[i] >= 0 && Mask[i] < 4)
9052 LoV1Inputs.push_back(i);
9053 else if (Mask[i] >= 4 && Mask[i] < 8)
9054 HiV1Inputs.push_back(i);
9055 else if (Mask[i] >= 8 && Mask[i] < 12)
9056 LoV2Inputs.push_back(i);
9057 else if (Mask[i] >= 12)
9058 HiV2Inputs.push_back(i);
9060 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9061 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9064 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9065 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9068 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9069 HiV1Inputs.size() + HiV2Inputs.size();
9071 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9072 ArrayRef<int> HiInputs, bool MoveToLo,
9074 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9075 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9076 if (BadInputs.empty())
9079 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9080 int MoveOffset = MoveToLo ? 0 : 4;
9082 if (GoodInputs.empty()) {
9083 for (int BadInput : BadInputs) {
9084 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9085 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9088 if (GoodInputs.size() == 2) {
9089 // If the low inputs are spread across two dwords, pack them into
9091 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9092 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9093 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9094 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9096 // Otherwise pin the good inputs.
9097 for (int GoodInput : GoodInputs)
9098 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9101 if (BadInputs.size() == 2) {
9102 // If we have two bad inputs then there may be either one or two good
9103 // inputs fixed in place. Find a fixed input, and then find the *other*
9104 // two adjacent indices by using modular arithmetic.
9106 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9107 [](int M) { return M >= 0; }) -
9108 std::begin(MoveMask);
9110 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9111 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9112 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9113 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9114 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9115 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9116 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9118 assert(BadInputs.size() == 1 && "All sizes handled");
9119 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9120 std::end(MoveMask), -1) -
9121 std::begin(MoveMask);
9122 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9123 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9127 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9130 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9132 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9135 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9136 // cross-half traffic in the final shuffle.
9138 // Munge the mask to be a single-input mask after the unpack merges the
9142 M = 2 * (M % 4) + (M / 8);
9144 return DAG.getVectorShuffle(
9145 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9146 DL, MVT::v8i16, V1, V2),
9147 DAG.getUNDEF(MVT::v8i16), Mask);
9150 /// \brief Generic lowering of 8-lane i16 shuffles.
9152 /// This handles both single-input shuffles and combined shuffle/blends with
9153 /// two inputs. The single input shuffles are immediately delegated to
9154 /// a dedicated lowering routine.
9156 /// The blends are lowered in one of three fundamental ways. If there are few
9157 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9158 /// of the input is significantly cheaper when lowered as an interleaving of
9159 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9160 /// halves of the inputs separately (making them have relatively few inputs)
9161 /// and then concatenate them.
9162 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9163 const X86Subtarget *Subtarget,
9164 SelectionDAG &DAG) {
9166 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9167 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9168 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9170 ArrayRef<int> OrigMask = SVOp->getMask();
9171 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9172 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9173 MutableArrayRef<int> Mask(MaskStorage);
9175 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9177 // Whenever we can lower this as a zext, that instruction is strictly faster
9178 // than any alternative.
9179 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9180 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9183 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9184 auto isV2 = [](int M) { return M >= 8; };
9186 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9187 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9189 if (NumV2Inputs == 0)
9190 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9192 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9193 "to be V1-input shuffles.");
9195 // Try to use byte shift instructions.
9196 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9197 DL, MVT::v8i16, V1, V2, Mask, DAG))
9200 // There are special ways we can lower some single-element blends.
9201 if (NumV2Inputs == 1)
9202 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9203 Mask, Subtarget, DAG))
9206 // Use dedicated unpack instructions for masks that match their pattern.
9207 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9208 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9209 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9210 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9212 if (Subtarget->hasSSE41())
9213 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9217 // Try to use byte rotation instructions.
9218 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9219 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9222 if (NumV1Inputs + NumV2Inputs <= 4)
9223 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9225 // Check whether an interleaving lowering is likely to be more efficient.
9226 // This isn't perfect but it is a strong heuristic that tends to work well on
9227 // the kinds of shuffles that show up in practice.
9229 // FIXME: Handle 1x, 2x, and 4x interleaving.
9230 if (shouldLowerAsInterleaving(Mask)) {
9231 // FIXME: Figure out whether we should pack these into the low or high
9234 int EMask[8], OMask[8];
9235 for (int i = 0; i < 4; ++i) {
9236 EMask[i] = Mask[2*i];
9237 OMask[i] = Mask[2*i + 1];
9242 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9243 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9248 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9249 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9251 for (int i = 0; i < 4; ++i) {
9252 LoBlendMask[i] = Mask[i];
9253 HiBlendMask[i] = Mask[i + 4];
9256 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9257 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9258 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9259 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9261 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9262 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9265 /// \brief Check whether a compaction lowering can be done by dropping even
9266 /// elements and compute how many times even elements must be dropped.
9268 /// This handles shuffles which take every Nth element where N is a power of
9269 /// two. Example shuffle masks:
9271 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9273 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9274 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9275 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9276 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9278 /// Any of these lanes can of course be undef.
9280 /// This routine only supports N <= 3.
9281 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9284 /// \returns N above, or the number of times even elements must be dropped if
9285 /// there is such a number. Otherwise returns zero.
9286 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9287 // Figure out whether we're looping over two inputs or just one.
9288 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9290 // The modulus for the shuffle vector entries is based on whether this is
9291 // a single input or not.
9292 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9293 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9294 "We should only be called with masks with a power-of-2 size!");
9296 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9298 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9299 // and 2^3 simultaneously. This is because we may have ambiguity with
9300 // partially undef inputs.
9301 bool ViableForN[3] = {true, true, true};
9303 for (int i = 0, e = Mask.size(); i < e; ++i) {
9304 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9309 bool IsAnyViable = false;
9310 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9311 if (ViableForN[j]) {
9314 // The shuffle mask must be equal to (i * 2^N) % M.
9315 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9318 ViableForN[j] = false;
9320 // Early exit if we exhaust the possible powers of two.
9325 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9329 // Return 0 as there is no viable power of two.
9333 /// \brief Generic lowering of v16i8 shuffles.
9335 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9336 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9337 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9338 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9340 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9341 const X86Subtarget *Subtarget,
9342 SelectionDAG &DAG) {
9344 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9345 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9346 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9348 ArrayRef<int> OrigMask = SVOp->getMask();
9349 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9351 // Try to use byte shift instructions.
9352 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9353 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9356 // Try to use byte rotation instructions.
9357 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9358 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9361 // Try to use a zext lowering.
9362 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9363 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9366 int MaskStorage[16] = {
9367 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9368 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9369 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9370 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9371 MutableArrayRef<int> Mask(MaskStorage);
9372 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9373 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9376 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9378 // For single-input shuffles, there are some nicer lowering tricks we can use.
9379 if (NumV2Elements == 0) {
9380 // Check for being able to broadcast a single element.
9381 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9382 Mask, Subtarget, DAG))
9385 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9386 // Notably, this handles splat and partial-splat shuffles more efficiently.
9387 // However, it only makes sense if the pre-duplication shuffle simplifies
9388 // things significantly. Currently, this means we need to be able to
9389 // express the pre-duplication shuffle as an i16 shuffle.
9391 // FIXME: We should check for other patterns which can be widened into an
9392 // i16 shuffle as well.
9393 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9394 for (int i = 0; i < 16; i += 2)
9395 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9400 auto tryToWidenViaDuplication = [&]() -> SDValue {
9401 if (!canWidenViaDuplication(Mask))
9403 SmallVector<int, 4> LoInputs;
9404 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9405 [](int M) { return M >= 0 && M < 8; });
9406 std::sort(LoInputs.begin(), LoInputs.end());
9407 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9409 SmallVector<int, 4> HiInputs;
9410 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9411 [](int M) { return M >= 8; });
9412 std::sort(HiInputs.begin(), HiInputs.end());
9413 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9416 bool TargetLo = LoInputs.size() >= HiInputs.size();
9417 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9418 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9420 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 SmallDenseMap<int, int, 8> LaneMap;
9422 for (int I : InPlaceInputs) {
9423 PreDupI16Shuffle[I/2] = I/2;
9426 int j = TargetLo ? 0 : 4, je = j + 4;
9427 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9428 // Check if j is already a shuffle of this input. This happens when
9429 // there are two adjacent bytes after we move the low one.
9430 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9431 // If we haven't yet mapped the input, search for a slot into which
9433 while (j < je && PreDupI16Shuffle[j] != -1)
9437 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9440 // Map this input with the i16 shuffle.
9441 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9444 // Update the lane map based on the mapping we ended up with.
9445 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9448 ISD::BITCAST, DL, MVT::v16i8,
9449 DAG.getVectorShuffle(MVT::v8i16, DL,
9450 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9451 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9453 // Unpack the bytes to form the i16s that will be shuffled into place.
9454 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9455 MVT::v16i8, V1, V1);
9457 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9458 for (int i = 0; i < 16; ++i)
9459 if (Mask[i] != -1) {
9460 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9461 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9462 if (PostDupI16Shuffle[i / 2] == -1)
9463 PostDupI16Shuffle[i / 2] = MappedMask;
9465 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9466 "Conflicting entrties in the original shuffle!");
9469 ISD::BITCAST, DL, MVT::v16i8,
9470 DAG.getVectorShuffle(MVT::v8i16, DL,
9471 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9472 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9474 if (SDValue V = tryToWidenViaDuplication())
9478 // Check whether an interleaving lowering is likely to be more efficient.
9479 // This isn't perfect but it is a strong heuristic that tends to work well on
9480 // the kinds of shuffles that show up in practice.
9482 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9483 if (shouldLowerAsInterleaving(Mask)) {
9484 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9485 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9487 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9488 return (M >= 8 && M < 16) || M >= 24;
9490 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9491 -1, -1, -1, -1, -1, -1, -1, -1};
9492 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9493 -1, -1, -1, -1, -1, -1, -1, -1};
9494 bool UnpackLo = NumLoHalf >= NumHiHalf;
9495 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9496 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9497 for (int i = 0; i < 8; ++i) {
9498 TargetEMask[i] = Mask[2 * i];
9499 TargetOMask[i] = Mask[2 * i + 1];
9502 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9503 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9505 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9506 MVT::v16i8, Evens, Odds);
9509 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9510 // with PSHUFB. It is important to do this before we attempt to generate any
9511 // blends but after all of the single-input lowerings. If the single input
9512 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9513 // want to preserve that and we can DAG combine any longer sequences into
9514 // a PSHUFB in the end. But once we start blending from multiple inputs,
9515 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9516 // and there are *very* few patterns that would actually be faster than the
9517 // PSHUFB approach because of its ability to zero lanes.
9519 // FIXME: The only exceptions to the above are blends which are exact
9520 // interleavings with direct instructions supporting them. We currently don't
9521 // handle those well here.
9522 if (Subtarget->hasSSSE3()) {
9525 for (int i = 0; i < 16; ++i)
9526 if (Mask[i] == -1) {
9527 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9529 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9531 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9533 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9534 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9535 if (isSingleInputShuffleMask(Mask))
9536 return V1; // Single inputs are easy.
9538 // Otherwise, blend the two.
9539 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9541 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9544 // There are special ways we can lower some single-element blends.
9545 if (NumV2Elements == 1)
9546 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9547 Mask, Subtarget, DAG))
9550 // Check whether a compaction lowering can be done. This handles shuffles
9551 // which take every Nth element for some even N. See the helper function for
9554 // We special case these as they can be particularly efficiently handled with
9555 // the PACKUSB instruction on x86 and they show up in common patterns of
9556 // rearranging bytes to truncate wide elements.
9557 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9558 // NumEvenDrops is the power of two stride of the elements. Another way of
9559 // thinking about it is that we need to drop the even elements this many
9560 // times to get the original input.
9561 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9563 // First we need to zero all the dropped bytes.
9564 assert(NumEvenDrops <= 3 &&
9565 "No support for dropping even elements more than 3 times.");
9566 // We use the mask type to pick which bytes are preserved based on how many
9567 // elements are dropped.
9568 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9569 SDValue ByteClearMask =
9570 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9571 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9572 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9574 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9576 // Now pack things back together.
9577 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9578 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9579 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9580 for (int i = 1; i < NumEvenDrops; ++i) {
9581 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9582 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9588 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9589 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9593 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9594 MutableArrayRef<int> V1HalfBlendMask,
9595 MutableArrayRef<int> V2HalfBlendMask) {
9596 for (int i = 0; i < 8; ++i)
9597 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9598 V1HalfBlendMask[i] = HalfMask[i];
9600 } else if (HalfMask[i] >= 16) {
9601 V2HalfBlendMask[i] = HalfMask[i] - 16;
9602 HalfMask[i] = i + 8;
9605 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9606 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9608 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9610 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9611 MutableArrayRef<int> HiBlendMask) {
9613 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9614 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9616 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9617 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9618 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9619 [](int M) { return M >= 0 && M % 2 == 1; })) {
9620 // Use a mask to drop the high bytes.
9621 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9622 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9623 DAG.getConstant(0x00FF, MVT::v8i16));
9625 // This will be a single vector shuffle instead of a blend so nuke V2.
9626 V2 = DAG.getUNDEF(MVT::v8i16);
9628 // Squash the masks to point directly into V1.
9629 for (int &M : LoBlendMask)
9632 for (int &M : HiBlendMask)
9636 // Otherwise just unpack the low half of V into V1 and the high half into
9637 // V2 so that we can blend them as i16s.
9638 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9639 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9640 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9641 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9644 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9645 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9646 return std::make_pair(BlendedLo, BlendedHi);
9648 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9649 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9650 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9652 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9653 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9655 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9658 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9660 /// This routine breaks down the specific type of 128-bit shuffle and
9661 /// dispatches to the lowering routines accordingly.
9662 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9663 MVT VT, const X86Subtarget *Subtarget,
9664 SelectionDAG &DAG) {
9665 switch (VT.SimpleTy) {
9667 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9669 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9671 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9673 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9675 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9677 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9680 llvm_unreachable("Unimplemented!");
9684 /// \brief Helper function to test whether a shuffle mask could be
9685 /// simplified by widening the elements being shuffled.
9687 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9688 /// leaves it in an unspecified state.
9690 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9691 /// shuffle masks. The latter have the special property of a '-2' representing
9692 /// a zero-ed lane of a vector.
9693 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9694 SmallVectorImpl<int> &WidenedMask) {
9695 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9696 // If both elements are undef, its trivial.
9697 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9698 WidenedMask.push_back(SM_SentinelUndef);
9702 // Check for an undef mask and a mask value properly aligned to fit with
9703 // a pair of values. If we find such a case, use the non-undef mask's value.
9704 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9705 WidenedMask.push_back(Mask[i + 1] / 2);
9708 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9709 WidenedMask.push_back(Mask[i] / 2);
9713 // When zeroing, we need to spread the zeroing across both lanes to widen.
9714 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9715 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9716 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9717 WidenedMask.push_back(SM_SentinelZero);
9723 // Finally check if the two mask values are adjacent and aligned with
9725 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9726 WidenedMask.push_back(Mask[i] / 2);
9730 // Otherwise we can't safely widen the elements used in this shuffle.
9733 assert(WidenedMask.size() == Mask.size() / 2 &&
9734 "Incorrect size of mask after widening the elements!");
9739 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9741 /// This routine just extracts two subvectors, shuffles them independently, and
9742 /// then concatenates them back together. This should work effectively with all
9743 /// AVX vector shuffle types.
9744 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9745 SDValue V2, ArrayRef<int> Mask,
9746 SelectionDAG &DAG) {
9747 assert(VT.getSizeInBits() >= 256 &&
9748 "Only for 256-bit or wider vector shuffles!");
9749 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9750 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9752 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9753 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9755 int NumElements = VT.getVectorNumElements();
9756 int SplitNumElements = NumElements / 2;
9757 MVT ScalarVT = VT.getScalarType();
9758 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9760 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9761 DAG.getIntPtrConstant(0));
9762 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9763 DAG.getIntPtrConstant(SplitNumElements));
9764 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9765 DAG.getIntPtrConstant(0));
9766 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9767 DAG.getIntPtrConstant(SplitNumElements));
9769 // Now create two 4-way blends of these half-width vectors.
9770 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9771 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9772 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9773 for (int i = 0; i < SplitNumElements; ++i) {
9774 int M = HalfMask[i];
9775 if (M >= NumElements) {
9776 if (M >= NumElements + SplitNumElements)
9780 V2BlendMask.push_back(M - NumElements);
9781 V1BlendMask.push_back(-1);
9782 BlendMask.push_back(SplitNumElements + i);
9783 } else if (M >= 0) {
9784 if (M >= SplitNumElements)
9788 V2BlendMask.push_back(-1);
9789 V1BlendMask.push_back(M);
9790 BlendMask.push_back(i);
9792 V2BlendMask.push_back(-1);
9793 V1BlendMask.push_back(-1);
9794 BlendMask.push_back(-1);
9798 // Because the lowering happens after all combining takes place, we need to
9799 // manually combine these blend masks as much as possible so that we create
9800 // a minimal number of high-level vector shuffle nodes.
9802 // First try just blending the halves of V1 or V2.
9803 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9804 return DAG.getUNDEF(SplitVT);
9805 if (!UseLoV2 && !UseHiV2)
9806 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9807 if (!UseLoV1 && !UseHiV1)
9808 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9810 SDValue V1Blend, V2Blend;
9811 if (UseLoV1 && UseHiV1) {
9813 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9815 // We only use half of V1 so map the usage down into the final blend mask.
9816 V1Blend = UseLoV1 ? LoV1 : HiV1;
9817 for (int i = 0; i < SplitNumElements; ++i)
9818 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9819 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9821 if (UseLoV2 && UseHiV2) {
9823 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9825 // We only use half of V2 so map the usage down into the final blend mask.
9826 V2Blend = UseLoV2 ? LoV2 : HiV2;
9827 for (int i = 0; i < SplitNumElements; ++i)
9828 if (BlendMask[i] >= SplitNumElements)
9829 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9831 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9833 SDValue Lo = HalfBlend(LoMask);
9834 SDValue Hi = HalfBlend(HiMask);
9835 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9838 /// \brief Either split a vector in halves or decompose the shuffles and the
9841 /// This is provided as a good fallback for many lowerings of non-single-input
9842 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9843 /// between splitting the shuffle into 128-bit components and stitching those
9844 /// back together vs. extracting the single-input shuffles and blending those
9846 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9847 SDValue V2, ArrayRef<int> Mask,
9848 SelectionDAG &DAG) {
9849 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9850 "lower single-input shuffles as it "
9851 "could then recurse on itself.");
9852 int Size = Mask.size();
9854 // If this can be modeled as a broadcast of two elements followed by a blend,
9855 // prefer that lowering. This is especially important because broadcasts can
9856 // often fold with memory operands.
9857 auto DoBothBroadcast = [&] {
9858 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9861 if (V2BroadcastIdx == -1)
9862 V2BroadcastIdx = M - Size;
9863 else if (M - Size != V2BroadcastIdx)
9865 } else if (M >= 0) {
9866 if (V1BroadcastIdx == -1)
9868 else if (M != V1BroadcastIdx)
9873 if (DoBothBroadcast())
9874 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9877 // If the inputs all stem from a single 128-bit lane of each input, then we
9878 // split them rather than blending because the split will decompose to
9879 // unusually few instructions.
9880 int LaneCount = VT.getSizeInBits() / 128;
9881 int LaneSize = Size / LaneCount;
9882 SmallBitVector LaneInputs[2];
9883 LaneInputs[0].resize(LaneCount, false);
9884 LaneInputs[1].resize(LaneCount, false);
9885 for (int i = 0; i < Size; ++i)
9887 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9888 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9889 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9891 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9892 // that the decomposed single-input shuffles don't end up here.
9893 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9896 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9897 /// a permutation and blend of those lanes.
9899 /// This essentially blends the out-of-lane inputs to each lane into the lane
9900 /// from a permuted copy of the vector. This lowering strategy results in four
9901 /// instructions in the worst case for a single-input cross lane shuffle which
9902 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9903 /// of. Special cases for each particular shuffle pattern should be handled
9904 /// prior to trying this lowering.
9905 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9906 SDValue V1, SDValue V2,
9908 SelectionDAG &DAG) {
9909 // FIXME: This should probably be generalized for 512-bit vectors as well.
9910 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9911 int LaneSize = Mask.size() / 2;
9913 // If there are only inputs from one 128-bit lane, splitting will in fact be
9914 // less expensive. The flags track wether the given lane contains an element
9915 // that crosses to another lane.
9916 bool LaneCrossing[2] = {false, false};
9917 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9918 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9919 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9920 if (!LaneCrossing[0] || !LaneCrossing[1])
9921 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9923 if (isSingleInputShuffleMask(Mask)) {
9924 SmallVector<int, 32> FlippedBlendMask;
9925 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9926 FlippedBlendMask.push_back(
9927 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9929 : Mask[i] % LaneSize +
9930 (i / LaneSize) * LaneSize + Size));
9932 // Flip the vector, and blend the results which should now be in-lane. The
9933 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9934 // 5 for the high source. The value 3 selects the high half of source 2 and
9935 // the value 2 selects the low half of source 2. We only use source 2 to
9936 // allow folding it into a memory operand.
9937 unsigned PERMMask = 3 | 2 << 4;
9938 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9939 V1, DAG.getConstant(PERMMask, MVT::i8));
9940 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9943 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9944 // will be handled by the above logic and a blend of the results, much like
9945 // other patterns in AVX.
9946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9949 /// \brief Handle lowering 2-lane 128-bit shuffles.
9950 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9951 SDValue V2, ArrayRef<int> Mask,
9952 const X86Subtarget *Subtarget,
9953 SelectionDAG &DAG) {
9954 // Blends are faster and handle all the non-lane-crossing cases.
9955 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9959 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9960 VT.getVectorNumElements() / 2);
9961 // Check for patterns which can be matched with a single insert of a 128-bit
9963 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9964 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9965 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9966 DAG.getIntPtrConstant(0));
9967 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9968 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9969 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9971 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9972 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9973 DAG.getIntPtrConstant(0));
9974 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9975 DAG.getIntPtrConstant(2));
9976 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9979 // Otherwise form a 128-bit permutation.
9980 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9981 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9982 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9983 DAG.getConstant(PermMask, MVT::i8));
9986 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9987 /// shuffling each lane.
9989 /// This will only succeed when the result of fixing the 128-bit lanes results
9990 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9991 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9992 /// the lane crosses early and then use simpler shuffles within each lane.
9994 /// FIXME: It might be worthwhile at some point to support this without
9995 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9996 /// in x86 only floating point has interesting non-repeating shuffles, and even
9997 /// those are still *marginally* more expensive.
9998 static SDValue lowerVectorShuffleByMerging128BitLanes(
9999 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10000 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10001 assert(!isSingleInputShuffleMask(Mask) &&
10002 "This is only useful with multiple inputs.");
10004 int Size = Mask.size();
10005 int LaneSize = 128 / VT.getScalarSizeInBits();
10006 int NumLanes = Size / LaneSize;
10007 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10009 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10010 // check whether the in-128-bit lane shuffles share a repeating pattern.
10011 SmallVector<int, 4> Lanes;
10012 Lanes.resize(NumLanes, -1);
10013 SmallVector<int, 4> InLaneMask;
10014 InLaneMask.resize(LaneSize, -1);
10015 for (int i = 0; i < Size; ++i) {
10019 int j = i / LaneSize;
10021 if (Lanes[j] < 0) {
10022 // First entry we've seen for this lane.
10023 Lanes[j] = Mask[i] / LaneSize;
10024 } else if (Lanes[j] != Mask[i] / LaneSize) {
10025 // This doesn't match the lane selected previously!
10029 // Check that within each lane we have a consistent shuffle mask.
10030 int k = i % LaneSize;
10031 if (InLaneMask[k] < 0) {
10032 InLaneMask[k] = Mask[i] % LaneSize;
10033 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10034 // This doesn't fit a repeating in-lane mask.
10039 // First shuffle the lanes into place.
10040 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10041 VT.getSizeInBits() / 64);
10042 SmallVector<int, 8> LaneMask;
10043 LaneMask.resize(NumLanes * 2, -1);
10044 for (int i = 0; i < NumLanes; ++i)
10045 if (Lanes[i] >= 0) {
10046 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10047 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10050 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10051 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10052 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10054 // Cast it back to the type we actually want.
10055 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10057 // Now do a simple shuffle that isn't lane crossing.
10058 SmallVector<int, 8> NewMask;
10059 NewMask.resize(Size, -1);
10060 for (int i = 0; i < Size; ++i)
10062 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10063 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10064 "Must not introduce lane crosses at this point!");
10066 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10069 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10072 /// This returns true if the elements from a particular input are already in the
10073 /// slot required by the given mask and require no permutation.
10074 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10075 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10076 int Size = Mask.size();
10077 for (int i = 0; i < Size; ++i)
10078 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10084 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10086 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10087 /// isn't available.
10088 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10089 const X86Subtarget *Subtarget,
10090 SelectionDAG &DAG) {
10092 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10093 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10095 ArrayRef<int> Mask = SVOp->getMask();
10096 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10098 SmallVector<int, 4> WidenedMask;
10099 if (canWidenShuffleElements(Mask, WidenedMask))
10100 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10103 if (isSingleInputShuffleMask(Mask)) {
10104 // Check for being able to broadcast a single element.
10105 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10106 Mask, Subtarget, DAG))
10109 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10110 // Non-half-crossing single input shuffles can be lowerid with an
10111 // interleaved permutation.
10112 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10113 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10114 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10115 DAG.getConstant(VPERMILPMask, MVT::i8));
10118 // With AVX2 we have direct support for this permutation.
10119 if (Subtarget->hasAVX2())
10120 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10121 getV4X86ShuffleImm8ForMask(Mask, DAG));
10123 // Otherwise, fall back.
10124 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10128 // X86 has dedicated unpack instructions that can handle specific blend
10129 // operations: UNPCKH and UNPCKL.
10130 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10131 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10132 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10133 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10135 // If we have a single input to the zero element, insert that into V1 if we
10136 // can do so cheaply.
10137 int NumV2Elements =
10138 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10139 if (NumV2Elements == 1 && Mask[0] >= 4)
10140 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10141 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10144 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10148 // Check if the blend happens to exactly fit that of SHUFPD.
10149 if ((Mask[0] == -1 || Mask[0] < 2) &&
10150 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10151 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10152 (Mask[3] == -1 || Mask[3] >= 6)) {
10153 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10154 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10155 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10156 DAG.getConstant(SHUFPDMask, MVT::i8));
10158 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10159 (Mask[1] == -1 || Mask[1] < 2) &&
10160 (Mask[2] == -1 || Mask[2] >= 6) &&
10161 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10162 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10163 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10164 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10165 DAG.getConstant(SHUFPDMask, MVT::i8));
10168 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10169 // shuffle. However, if we have AVX2 and either inputs are already in place,
10170 // we will be able to shuffle even across lanes the other input in a single
10171 // instruction so skip this pattern.
10172 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10173 isShuffleMaskInputInPlace(1, Mask))))
10174 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10175 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10178 // If we have AVX2 then we always want to lower with a blend because an v4 we
10179 // can fully permute the elements.
10180 if (Subtarget->hasAVX2())
10181 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10184 // Otherwise fall back on generic lowering.
10185 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10188 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10190 /// This routine is only called when we have AVX2 and thus a reasonable
10191 /// instruction set for v4i64 shuffling..
10192 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10193 const X86Subtarget *Subtarget,
10194 SelectionDAG &DAG) {
10196 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10197 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10198 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10199 ArrayRef<int> Mask = SVOp->getMask();
10200 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10201 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10203 SmallVector<int, 4> WidenedMask;
10204 if (canWidenShuffleElements(Mask, WidenedMask))
10205 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10208 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10212 // Check for being able to broadcast a single element.
10213 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10214 Mask, Subtarget, DAG))
10217 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10218 // use lower latency instructions that will operate on both 128-bit lanes.
10219 SmallVector<int, 2> RepeatedMask;
10220 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10221 if (isSingleInputShuffleMask(Mask)) {
10222 int PSHUFDMask[] = {-1, -1, -1, -1};
10223 for (int i = 0; i < 2; ++i)
10224 if (RepeatedMask[i] >= 0) {
10225 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10226 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10228 return DAG.getNode(
10229 ISD::BITCAST, DL, MVT::v4i64,
10230 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10231 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10232 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10235 // Use dedicated unpack instructions for masks that match their pattern.
10236 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10237 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10238 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10239 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10242 // AVX2 provides a direct instruction for permuting a single input across
10244 if (isSingleInputShuffleMask(Mask))
10245 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10246 getV4X86ShuffleImm8ForMask(Mask, DAG));
10248 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10249 // shuffle. However, if we have AVX2 and either inputs are already in place,
10250 // we will be able to shuffle even across lanes the other input in a single
10251 // instruction so skip this pattern.
10252 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10253 isShuffleMaskInputInPlace(1, Mask))))
10254 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10255 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10258 // Otherwise fall back on generic blend lowering.
10259 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10263 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10265 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10266 /// isn't available.
10267 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10268 const X86Subtarget *Subtarget,
10269 SelectionDAG &DAG) {
10271 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10272 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10273 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10274 ArrayRef<int> Mask = SVOp->getMask();
10275 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10277 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10281 // Check for being able to broadcast a single element.
10282 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10283 Mask, Subtarget, DAG))
10286 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10287 // options to efficiently lower the shuffle.
10288 SmallVector<int, 4> RepeatedMask;
10289 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10290 assert(RepeatedMask.size() == 4 &&
10291 "Repeated masks must be half the mask width!");
10292 if (isSingleInputShuffleMask(Mask))
10293 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10294 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10296 // Use dedicated unpack instructions for masks that match their pattern.
10297 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10298 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10299 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10300 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10302 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10303 // have already handled any direct blends. We also need to squash the
10304 // repeated mask into a simulated v4f32 mask.
10305 for (int i = 0; i < 4; ++i)
10306 if (RepeatedMask[i] >= 8)
10307 RepeatedMask[i] -= 4;
10308 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10311 // If we have a single input shuffle with different shuffle patterns in the
10312 // two 128-bit lanes use the variable mask to VPERMILPS.
10313 if (isSingleInputShuffleMask(Mask)) {
10314 SDValue VPermMask[8];
10315 for (int i = 0; i < 8; ++i)
10316 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10317 : DAG.getConstant(Mask[i], MVT::i32);
10318 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10319 return DAG.getNode(
10320 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10321 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10323 if (Subtarget->hasAVX2())
10324 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10325 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10326 DAG.getNode(ISD::BUILD_VECTOR, DL,
10327 MVT::v8i32, VPermMask)),
10330 // Otherwise, fall back.
10331 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10335 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10337 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10338 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10341 // If we have AVX2 then we always want to lower with a blend because at v8 we
10342 // can fully permute the elements.
10343 if (Subtarget->hasAVX2())
10344 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10347 // Otherwise fall back on generic lowering.
10348 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10351 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10353 /// This routine is only called when we have AVX2 and thus a reasonable
10354 /// instruction set for v8i32 shuffling..
10355 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10356 const X86Subtarget *Subtarget,
10357 SelectionDAG &DAG) {
10359 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10360 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10361 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10362 ArrayRef<int> Mask = SVOp->getMask();
10363 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10364 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10366 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10370 // Check for being able to broadcast a single element.
10371 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10372 Mask, Subtarget, DAG))
10375 // If the shuffle mask is repeated in each 128-bit lane we can use more
10376 // efficient instructions that mirror the shuffles across the two 128-bit
10378 SmallVector<int, 4> RepeatedMask;
10379 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10380 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10381 if (isSingleInputShuffleMask(Mask))
10382 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10383 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10385 // Use dedicated unpack instructions for masks that match their pattern.
10386 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10387 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10388 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10389 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10392 // If the shuffle patterns aren't repeated but it is a single input, directly
10393 // generate a cross-lane VPERMD instruction.
10394 if (isSingleInputShuffleMask(Mask)) {
10395 SDValue VPermMask[8];
10396 for (int i = 0; i < 8; ++i)
10397 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10398 : DAG.getConstant(Mask[i], MVT::i32);
10399 return DAG.getNode(
10400 X86ISD::VPERMV, DL, MVT::v8i32,
10401 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10404 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10406 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10407 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10410 // Otherwise fall back on generic blend lowering.
10411 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10415 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10417 /// This routine is only called when we have AVX2 and thus a reasonable
10418 /// instruction set for v16i16 shuffling..
10419 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10420 const X86Subtarget *Subtarget,
10421 SelectionDAG &DAG) {
10423 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10424 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10426 ArrayRef<int> Mask = SVOp->getMask();
10427 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10428 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10430 // Check for being able to broadcast a single element.
10431 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10432 Mask, Subtarget, DAG))
10435 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10439 // Use dedicated unpack instructions for masks that match their pattern.
10440 if (isShuffleEquivalent(Mask,
10441 // First 128-bit lane:
10442 0, 16, 1, 17, 2, 18, 3, 19,
10443 // Second 128-bit lane:
10444 8, 24, 9, 25, 10, 26, 11, 27))
10445 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10446 if (isShuffleEquivalent(Mask,
10447 // First 128-bit lane:
10448 4, 20, 5, 21, 6, 22, 7, 23,
10449 // Second 128-bit lane:
10450 12, 28, 13, 29, 14, 30, 15, 31))
10451 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10453 if (isSingleInputShuffleMask(Mask)) {
10454 // There are no generalized cross-lane shuffle operations available on i16
10456 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10457 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10460 SDValue PSHUFBMask[32];
10461 for (int i = 0; i < 16; ++i) {
10462 if (Mask[i] == -1) {
10463 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10467 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10468 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10469 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10470 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10472 return DAG.getNode(
10473 ISD::BITCAST, DL, MVT::v16i16,
10475 X86ISD::PSHUFB, DL, MVT::v32i8,
10476 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10477 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10480 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10482 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10483 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10486 // Otherwise fall back on generic lowering.
10487 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10490 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10492 /// This routine is only called when we have AVX2 and thus a reasonable
10493 /// instruction set for v32i8 shuffling..
10494 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10495 const X86Subtarget *Subtarget,
10496 SelectionDAG &DAG) {
10498 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10499 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10500 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10501 ArrayRef<int> Mask = SVOp->getMask();
10502 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10503 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10505 // Check for being able to broadcast a single element.
10506 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10507 Mask, Subtarget, DAG))
10510 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10514 // Use dedicated unpack instructions for masks that match their pattern.
10515 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10517 if (isShuffleEquivalent(
10519 // First 128-bit lane:
10520 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10521 // Second 128-bit lane:
10522 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10523 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10524 if (isShuffleEquivalent(
10526 // First 128-bit lane:
10527 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10528 // Second 128-bit lane:
10529 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10530 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10532 if (isSingleInputShuffleMask(Mask)) {
10533 // There are no generalized cross-lane shuffle operations available on i8
10535 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10536 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10539 SDValue PSHUFBMask[32];
10540 for (int i = 0; i < 32; ++i)
10543 ? DAG.getUNDEF(MVT::i8)
10544 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10546 return DAG.getNode(
10547 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10548 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10551 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10553 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10554 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10557 // Otherwise fall back on generic lowering.
10558 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10561 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10563 /// This routine either breaks down the specific type of a 256-bit x86 vector
10564 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10565 /// together based on the available instructions.
10566 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10567 MVT VT, const X86Subtarget *Subtarget,
10568 SelectionDAG &DAG) {
10570 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10571 ArrayRef<int> Mask = SVOp->getMask();
10573 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10574 // check for those subtargets here and avoid much of the subtarget querying in
10575 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10576 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10577 // floating point types there eventually, just immediately cast everything to
10578 // a float and operate entirely in that domain.
10579 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10580 int ElementBits = VT.getScalarSizeInBits();
10581 if (ElementBits < 32)
10582 // No floating point type available, decompose into 128-bit vectors.
10583 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10585 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10586 VT.getVectorNumElements());
10587 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10588 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10589 return DAG.getNode(ISD::BITCAST, DL, VT,
10590 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10593 switch (VT.SimpleTy) {
10595 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10597 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10599 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10601 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10603 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10605 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10608 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10612 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10613 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10614 const X86Subtarget *Subtarget,
10615 SelectionDAG &DAG) {
10617 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10618 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10619 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10620 ArrayRef<int> Mask = SVOp->getMask();
10621 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10623 // FIXME: Implement direct support for this type!
10624 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10627 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10628 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10629 const X86Subtarget *Subtarget,
10630 SelectionDAG &DAG) {
10632 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10633 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10634 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10635 ArrayRef<int> Mask = SVOp->getMask();
10636 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10638 // FIXME: Implement direct support for this type!
10639 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10642 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10643 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10644 const X86Subtarget *Subtarget,
10645 SelectionDAG &DAG) {
10647 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10648 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10650 ArrayRef<int> Mask = SVOp->getMask();
10651 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10653 // FIXME: Implement direct support for this type!
10654 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10657 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10658 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10663 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10665 ArrayRef<int> Mask = SVOp->getMask();
10666 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10668 // FIXME: Implement direct support for this type!
10669 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10672 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10673 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10674 const X86Subtarget *Subtarget,
10675 SelectionDAG &DAG) {
10677 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10678 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10680 ArrayRef<int> Mask = SVOp->getMask();
10681 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10682 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10684 // FIXME: Implement direct support for this type!
10685 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10688 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10689 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10690 const X86Subtarget *Subtarget,
10691 SelectionDAG &DAG) {
10693 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10694 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10695 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10696 ArrayRef<int> Mask = SVOp->getMask();
10697 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10698 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10700 // FIXME: Implement direct support for this type!
10701 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10704 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10706 /// This routine either breaks down the specific type of a 512-bit x86 vector
10707 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10708 /// together based on the available instructions.
10709 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10710 MVT VT, const X86Subtarget *Subtarget,
10711 SelectionDAG &DAG) {
10713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10714 ArrayRef<int> Mask = SVOp->getMask();
10715 assert(Subtarget->hasAVX512() &&
10716 "Cannot lower 512-bit vectors w/ basic ISA!");
10718 // Check for being able to broadcast a single element.
10719 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10720 Mask, Subtarget, DAG))
10723 // Dispatch to each element type for lowering. If we don't have supprot for
10724 // specific element type shuffles at 512 bits, immediately split them and
10725 // lower them. Each lowering routine of a given type is allowed to assume that
10726 // the requisite ISA extensions for that element type are available.
10727 switch (VT.SimpleTy) {
10729 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10731 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10733 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10735 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10737 if (Subtarget->hasBWI())
10738 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10741 if (Subtarget->hasBWI())
10742 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10746 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10749 // Otherwise fall back on splitting.
10750 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10753 /// \brief Top-level lowering for x86 vector shuffles.
10755 /// This handles decomposition, canonicalization, and lowering of all x86
10756 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10757 /// above in helper routines. The canonicalization attempts to widen shuffles
10758 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10759 /// s.t. only one of the two inputs needs to be tested, etc.
10760 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10761 SelectionDAG &DAG) {
10762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10763 ArrayRef<int> Mask = SVOp->getMask();
10764 SDValue V1 = Op.getOperand(0);
10765 SDValue V2 = Op.getOperand(1);
10766 MVT VT = Op.getSimpleValueType();
10767 int NumElements = VT.getVectorNumElements();
10770 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10772 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10773 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10774 if (V1IsUndef && V2IsUndef)
10775 return DAG.getUNDEF(VT);
10777 // When we create a shuffle node we put the UNDEF node to second operand,
10778 // but in some cases the first operand may be transformed to UNDEF.
10779 // In this case we should just commute the node.
10781 return DAG.getCommutedVectorShuffle(*SVOp);
10783 // Check for non-undef masks pointing at an undef vector and make the masks
10784 // undef as well. This makes it easier to match the shuffle based solely on
10788 if (M >= NumElements) {
10789 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10790 for (int &M : NewMask)
10791 if (M >= NumElements)
10793 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10796 // Try to collapse shuffles into using a vector type with fewer elements but
10797 // wider element types. We cap this to not form integers or floating point
10798 // elements wider than 64 bits, but it might be interesting to form i128
10799 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10800 SmallVector<int, 16> WidenedMask;
10801 if (VT.getScalarSizeInBits() < 64 &&
10802 canWidenShuffleElements(Mask, WidenedMask)) {
10803 MVT NewEltVT = VT.isFloatingPoint()
10804 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10805 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10806 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10807 // Make sure that the new vector type is legal. For example, v2f64 isn't
10809 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10810 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10811 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10812 return DAG.getNode(ISD::BITCAST, dl, VT,
10813 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10817 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10818 for (int M : SVOp->getMask())
10820 ++NumUndefElements;
10821 else if (M < NumElements)
10826 // Commute the shuffle as needed such that more elements come from V1 than
10827 // V2. This allows us to match the shuffle pattern strictly on how many
10828 // elements come from V1 without handling the symmetric cases.
10829 if (NumV2Elements > NumV1Elements)
10830 return DAG.getCommutedVectorShuffle(*SVOp);
10832 // When the number of V1 and V2 elements are the same, try to minimize the
10833 // number of uses of V2 in the low half of the vector. When that is tied,
10834 // ensure that the sum of indices for V1 is equal to or lower than the sum
10835 // indices for V2. When those are equal, try to ensure that the number of odd
10836 // indices for V1 is lower than the number of odd indices for V2.
10837 if (NumV1Elements == NumV2Elements) {
10838 int LowV1Elements = 0, LowV2Elements = 0;
10839 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10840 if (M >= NumElements)
10844 if (LowV2Elements > LowV1Elements) {
10845 return DAG.getCommutedVectorShuffle(*SVOp);
10846 } else if (LowV2Elements == LowV1Elements) {
10847 int SumV1Indices = 0, SumV2Indices = 0;
10848 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10849 if (SVOp->getMask()[i] >= NumElements)
10851 else if (SVOp->getMask()[i] >= 0)
10853 if (SumV2Indices < SumV1Indices) {
10854 return DAG.getCommutedVectorShuffle(*SVOp);
10855 } else if (SumV2Indices == SumV1Indices) {
10856 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10857 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10858 if (SVOp->getMask()[i] >= NumElements)
10859 NumV2OddIndices += i % 2;
10860 else if (SVOp->getMask()[i] >= 0)
10861 NumV1OddIndices += i % 2;
10862 if (NumV2OddIndices < NumV1OddIndices)
10863 return DAG.getCommutedVectorShuffle(*SVOp);
10868 // For each vector width, delegate to a specialized lowering routine.
10869 if (VT.getSizeInBits() == 128)
10870 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10872 if (VT.getSizeInBits() == 256)
10873 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10875 // Force AVX-512 vectors to be scalarized for now.
10876 // FIXME: Implement AVX-512 support!
10877 if (VT.getSizeInBits() == 512)
10878 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10880 llvm_unreachable("Unimplemented!");
10884 //===----------------------------------------------------------------------===//
10885 // Legacy vector shuffle lowering
10887 // This code is the legacy code handling vector shuffles until the above
10888 // replaces its functionality and performance.
10889 //===----------------------------------------------------------------------===//
10891 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10892 bool hasInt256, unsigned *MaskOut = nullptr) {
10893 MVT EltVT = VT.getVectorElementType();
10895 // There is no blend with immediate in AVX-512.
10896 if (VT.is512BitVector())
10899 if (!hasSSE41 || EltVT == MVT::i8)
10901 if (!hasInt256 && VT == MVT::v16i16)
10904 unsigned MaskValue = 0;
10905 unsigned NumElems = VT.getVectorNumElements();
10906 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10907 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10908 unsigned NumElemsInLane = NumElems / NumLanes;
10910 // Blend for v16i16 should be symetric for the both lanes.
10911 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10913 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10914 int EltIdx = MaskVals[i];
10916 if ((EltIdx < 0 || EltIdx == (int)i) &&
10917 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10920 if (((unsigned)EltIdx == (i + NumElems)) &&
10921 (SndLaneEltIdx < 0 ||
10922 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10923 MaskValue |= (1 << i);
10929 *MaskOut = MaskValue;
10933 // Try to lower a shuffle node into a simple blend instruction.
10934 // This function assumes isBlendMask returns true for this
10935 // SuffleVectorSDNode
10936 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10937 unsigned MaskValue,
10938 const X86Subtarget *Subtarget,
10939 SelectionDAG &DAG) {
10940 MVT VT = SVOp->getSimpleValueType(0);
10941 MVT EltVT = VT.getVectorElementType();
10942 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10943 Subtarget->hasInt256() && "Trying to lower a "
10944 "VECTOR_SHUFFLE to a Blend but "
10945 "with the wrong mask"));
10946 SDValue V1 = SVOp->getOperand(0);
10947 SDValue V2 = SVOp->getOperand(1);
10949 unsigned NumElems = VT.getVectorNumElements();
10951 // Convert i32 vectors to floating point if it is not AVX2.
10952 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10954 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10955 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10957 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10958 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10961 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10962 DAG.getConstant(MaskValue, MVT::i32));
10963 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10966 /// In vector type \p VT, return true if the element at index \p InputIdx
10967 /// falls on a different 128-bit lane than \p OutputIdx.
10968 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10969 unsigned OutputIdx) {
10970 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10971 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10974 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10975 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10976 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10977 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10979 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10980 SelectionDAG &DAG) {
10981 MVT VT = V1.getSimpleValueType();
10982 assert(VT.is128BitVector() || VT.is256BitVector());
10984 MVT EltVT = VT.getVectorElementType();
10985 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10986 unsigned NumElts = VT.getVectorNumElements();
10988 SmallVector<SDValue, 32> PshufbMask;
10989 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10990 int InputIdx = MaskVals[OutputIdx];
10991 unsigned InputByteIdx;
10993 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10994 InputByteIdx = 0x80;
10996 // Cross lane is not allowed.
10997 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10999 InputByteIdx = InputIdx * EltSizeInBytes;
11000 // Index is an byte offset within the 128-bit lane.
11001 InputByteIdx &= 0xf;
11004 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11005 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11006 if (InputByteIdx != 0x80)
11011 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11013 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11014 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11015 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11018 // v8i16 shuffles - Prefer shuffles in the following order:
11019 // 1. [all] pshuflw, pshufhw, optional move
11020 // 2. [ssse3] 1 x pshufb
11021 // 3. [ssse3] 2 x pshufb + 1 x por
11022 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11024 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11025 SelectionDAG &DAG) {
11026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11027 SDValue V1 = SVOp->getOperand(0);
11028 SDValue V2 = SVOp->getOperand(1);
11030 SmallVector<int, 8> MaskVals;
11032 // Determine if more than 1 of the words in each of the low and high quadwords
11033 // of the result come from the same quadword of one of the two inputs. Undef
11034 // mask values count as coming from any quadword, for better codegen.
11036 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11037 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11038 unsigned LoQuad[] = { 0, 0, 0, 0 };
11039 unsigned HiQuad[] = { 0, 0, 0, 0 };
11040 // Indices of quads used.
11041 std::bitset<4> InputQuads;
11042 for (unsigned i = 0; i < 8; ++i) {
11043 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11044 int EltIdx = SVOp->getMaskElt(i);
11045 MaskVals.push_back(EltIdx);
11053 ++Quad[EltIdx / 4];
11054 InputQuads.set(EltIdx / 4);
11057 int BestLoQuad = -1;
11058 unsigned MaxQuad = 1;
11059 for (unsigned i = 0; i < 4; ++i) {
11060 if (LoQuad[i] > MaxQuad) {
11062 MaxQuad = LoQuad[i];
11066 int BestHiQuad = -1;
11068 for (unsigned i = 0; i < 4; ++i) {
11069 if (HiQuad[i] > MaxQuad) {
11071 MaxQuad = HiQuad[i];
11075 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11076 // of the two input vectors, shuffle them into one input vector so only a
11077 // single pshufb instruction is necessary. If there are more than 2 input
11078 // quads, disable the next transformation since it does not help SSSE3.
11079 bool V1Used = InputQuads[0] || InputQuads[1];
11080 bool V2Used = InputQuads[2] || InputQuads[3];
11081 if (Subtarget->hasSSSE3()) {
11082 if (InputQuads.count() == 2 && V1Used && V2Used) {
11083 BestLoQuad = InputQuads[0] ? 0 : 1;
11084 BestHiQuad = InputQuads[2] ? 2 : 3;
11086 if (InputQuads.count() > 2) {
11092 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11093 // the shuffle mask. If a quad is scored as -1, that means that it contains
11094 // words from all 4 input quadwords.
11096 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11098 BestLoQuad < 0 ? 0 : BestLoQuad,
11099 BestHiQuad < 0 ? 1 : BestHiQuad
11101 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11102 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11103 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11104 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11106 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11107 // source words for the shuffle, to aid later transformations.
11108 bool AllWordsInNewV = true;
11109 bool InOrder[2] = { true, true };
11110 for (unsigned i = 0; i != 8; ++i) {
11111 int idx = MaskVals[i];
11113 InOrder[i/4] = false;
11114 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11116 AllWordsInNewV = false;
11120 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11121 if (AllWordsInNewV) {
11122 for (int i = 0; i != 8; ++i) {
11123 int idx = MaskVals[i];
11126 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11127 if ((idx != i) && idx < 4)
11129 if ((idx != i) && idx > 3)
11138 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11139 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11140 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11141 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11142 unsigned TargetMask = 0;
11143 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11144 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11145 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11146 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11147 getShufflePSHUFLWImmediate(SVOp);
11148 V1 = NewV.getOperand(0);
11149 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11153 // Promote splats to a larger type which usually leads to more efficient code.
11154 // FIXME: Is this true if pshufb is available?
11155 if (SVOp->isSplat())
11156 return PromoteSplat(SVOp, DAG);
11158 // If we have SSSE3, and all words of the result are from 1 input vector,
11159 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11160 // is present, fall back to case 4.
11161 if (Subtarget->hasSSSE3()) {
11162 SmallVector<SDValue,16> pshufbMask;
11164 // If we have elements from both input vectors, set the high bit of the
11165 // shuffle mask element to zero out elements that come from V2 in the V1
11166 // mask, and elements that come from V1 in the V2 mask, so that the two
11167 // results can be OR'd together.
11168 bool TwoInputs = V1Used && V2Used;
11169 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11171 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11173 // Calculate the shuffle mask for the second input, shuffle it, and
11174 // OR it with the first shuffled input.
11175 CommuteVectorShuffleMask(MaskVals, 8);
11176 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11177 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11178 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11181 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11182 // and update MaskVals with new element order.
11183 std::bitset<8> InOrder;
11184 if (BestLoQuad >= 0) {
11185 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11186 for (int i = 0; i != 4; ++i) {
11187 int idx = MaskVals[i];
11190 } else if ((idx / 4) == BestLoQuad) {
11191 MaskV[i] = idx & 3;
11195 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11198 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11200 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11201 NewV.getOperand(0),
11202 getShufflePSHUFLWImmediate(SVOp), DAG);
11206 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11207 // and update MaskVals with the new element order.
11208 if (BestHiQuad >= 0) {
11209 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11210 for (unsigned i = 4; i != 8; ++i) {
11211 int idx = MaskVals[i];
11214 } else if ((idx / 4) == BestHiQuad) {
11215 MaskV[i] = (idx & 3) + 4;
11219 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11222 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11224 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11225 NewV.getOperand(0),
11226 getShufflePSHUFHWImmediate(SVOp), DAG);
11230 // In case BestHi & BestLo were both -1, which means each quadword has a word
11231 // from each of the four input quadwords, calculate the InOrder bitvector now
11232 // before falling through to the insert/extract cleanup.
11233 if (BestLoQuad == -1 && BestHiQuad == -1) {
11235 for (int i = 0; i != 8; ++i)
11236 if (MaskVals[i] < 0 || MaskVals[i] == i)
11240 // The other elements are put in the right place using pextrw and pinsrw.
11241 for (unsigned i = 0; i != 8; ++i) {
11244 int EltIdx = MaskVals[i];
11247 SDValue ExtOp = (EltIdx < 8) ?
11248 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11249 DAG.getIntPtrConstant(EltIdx)) :
11250 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11251 DAG.getIntPtrConstant(EltIdx - 8));
11252 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11253 DAG.getIntPtrConstant(i));
11258 /// \brief v16i16 shuffles
11260 /// FIXME: We only support generation of a single pshufb currently. We can
11261 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11262 /// well (e.g 2 x pshufb + 1 x por).
11264 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11265 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11266 SDValue V1 = SVOp->getOperand(0);
11267 SDValue V2 = SVOp->getOperand(1);
11270 if (V2.getOpcode() != ISD::UNDEF)
11273 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11274 return getPSHUFB(MaskVals, V1, dl, DAG);
11277 // v16i8 shuffles - Prefer shuffles in the following order:
11278 // 1. [ssse3] 1 x pshufb
11279 // 2. [ssse3] 2 x pshufb + 1 x por
11280 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11281 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11282 const X86Subtarget* Subtarget,
11283 SelectionDAG &DAG) {
11284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11285 SDValue V1 = SVOp->getOperand(0);
11286 SDValue V2 = SVOp->getOperand(1);
11288 ArrayRef<int> MaskVals = SVOp->getMask();
11290 // Promote splats to a larger type which usually leads to more efficient code.
11291 // FIXME: Is this true if pshufb is available?
11292 if (SVOp->isSplat())
11293 return PromoteSplat(SVOp, DAG);
11295 // If we have SSSE3, case 1 is generated when all result bytes come from
11296 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11297 // present, fall back to case 3.
11299 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11300 if (Subtarget->hasSSSE3()) {
11301 SmallVector<SDValue,16> pshufbMask;
11303 // If all result elements are from one input vector, then only translate
11304 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11306 // Otherwise, we have elements from both input vectors, and must zero out
11307 // elements that come from V2 in the first mask, and V1 in the second mask
11308 // so that we can OR them together.
11309 for (unsigned i = 0; i != 16; ++i) {
11310 int EltIdx = MaskVals[i];
11311 if (EltIdx < 0 || EltIdx >= 16)
11313 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11315 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11316 DAG.getNode(ISD::BUILD_VECTOR, dl,
11317 MVT::v16i8, pshufbMask));
11319 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11320 // the 2nd operand if it's undefined or zero.
11321 if (V2.getOpcode() == ISD::UNDEF ||
11322 ISD::isBuildVectorAllZeros(V2.getNode()))
11325 // Calculate the shuffle mask for the second input, shuffle it, and
11326 // OR it with the first shuffled input.
11327 pshufbMask.clear();
11328 for (unsigned i = 0; i != 16; ++i) {
11329 int EltIdx = MaskVals[i];
11330 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11331 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11333 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11334 DAG.getNode(ISD::BUILD_VECTOR, dl,
11335 MVT::v16i8, pshufbMask));
11336 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11339 // No SSSE3 - Calculate in place words and then fix all out of place words
11340 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11341 // the 16 different words that comprise the two doublequadword input vectors.
11342 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11343 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11345 for (int i = 0; i != 8; ++i) {
11346 int Elt0 = MaskVals[i*2];
11347 int Elt1 = MaskVals[i*2+1];
11349 // This word of the result is all undef, skip it.
11350 if (Elt0 < 0 && Elt1 < 0)
11353 // This word of the result is already in the correct place, skip it.
11354 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11357 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11358 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11361 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11362 // using a single extract together, load it and store it.
11363 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11364 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11365 DAG.getIntPtrConstant(Elt1 / 2));
11366 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11367 DAG.getIntPtrConstant(i));
11371 // If Elt1 is defined, extract it from the appropriate source. If the
11372 // source byte is not also odd, shift the extracted word left 8 bits
11373 // otherwise clear the bottom 8 bits if we need to do an or.
11375 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11376 DAG.getIntPtrConstant(Elt1 / 2));
11377 if ((Elt1 & 1) == 0)
11378 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11380 TLI.getShiftAmountTy(InsElt.getValueType())));
11381 else if (Elt0 >= 0)
11382 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11383 DAG.getConstant(0xFF00, MVT::i16));
11385 // If Elt0 is defined, extract it from the appropriate source. If the
11386 // source byte is not also even, shift the extracted word right 8 bits. If
11387 // Elt1 was also defined, OR the extracted values together before
11388 // inserting them in the result.
11390 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11391 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11392 if ((Elt0 & 1) != 0)
11393 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11395 TLI.getShiftAmountTy(InsElt0.getValueType())));
11396 else if (Elt1 >= 0)
11397 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11398 DAG.getConstant(0x00FF, MVT::i16));
11399 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11402 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11403 DAG.getIntPtrConstant(i));
11405 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11408 // v32i8 shuffles - Translate to VPSHUFB if possible.
11410 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11411 const X86Subtarget *Subtarget,
11412 SelectionDAG &DAG) {
11413 MVT VT = SVOp->getSimpleValueType(0);
11414 SDValue V1 = SVOp->getOperand(0);
11415 SDValue V2 = SVOp->getOperand(1);
11417 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11419 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11420 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11421 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11423 // VPSHUFB may be generated if
11424 // (1) one of input vector is undefined or zeroinitializer.
11425 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11426 // And (2) the mask indexes don't cross the 128-bit lane.
11427 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11428 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11431 if (V1IsAllZero && !V2IsAllZero) {
11432 CommuteVectorShuffleMask(MaskVals, 32);
11435 return getPSHUFB(MaskVals, V1, dl, DAG);
11438 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11439 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11440 /// done when every pair / quad of shuffle mask elements point to elements in
11441 /// the right sequence. e.g.
11442 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11444 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11445 SelectionDAG &DAG) {
11446 MVT VT = SVOp->getSimpleValueType(0);
11448 unsigned NumElems = VT.getVectorNumElements();
11451 switch (VT.SimpleTy) {
11452 default: llvm_unreachable("Unexpected!");
11455 return SDValue(SVOp, 0);
11456 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11457 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11458 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11459 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11460 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11461 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11464 SmallVector<int, 8> MaskVec;
11465 for (unsigned i = 0; i != NumElems; i += Scale) {
11467 for (unsigned j = 0; j != Scale; ++j) {
11468 int EltIdx = SVOp->getMaskElt(i+j);
11472 StartIdx = (EltIdx / Scale);
11473 if (EltIdx != (int)(StartIdx*Scale + j))
11476 MaskVec.push_back(StartIdx);
11479 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11480 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11481 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11484 /// getVZextMovL - Return a zero-extending vector move low node.
11486 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11487 SDValue SrcOp, SelectionDAG &DAG,
11488 const X86Subtarget *Subtarget, SDLoc dl) {
11489 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11490 LoadSDNode *LD = nullptr;
11491 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11492 LD = dyn_cast<LoadSDNode>(SrcOp);
11494 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11496 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11497 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11498 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11499 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11500 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11502 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11503 return DAG.getNode(ISD::BITCAST, dl, VT,
11504 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11505 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11507 SrcOp.getOperand(0)
11513 return DAG.getNode(ISD::BITCAST, dl, VT,
11514 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11515 DAG.getNode(ISD::BITCAST, dl,
11519 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11520 /// which could not be matched by any known target speficic shuffle
11522 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11524 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11525 if (NewOp.getNode())
11528 MVT VT = SVOp->getSimpleValueType(0);
11530 unsigned NumElems = VT.getVectorNumElements();
11531 unsigned NumLaneElems = NumElems / 2;
11534 MVT EltVT = VT.getVectorElementType();
11535 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11538 SmallVector<int, 16> Mask;
11539 for (unsigned l = 0; l < 2; ++l) {
11540 // Build a shuffle mask for the output, discovering on the fly which
11541 // input vectors to use as shuffle operands (recorded in InputUsed).
11542 // If building a suitable shuffle vector proves too hard, then bail
11543 // out with UseBuildVector set.
11544 bool UseBuildVector = false;
11545 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11546 unsigned LaneStart = l * NumLaneElems;
11547 for (unsigned i = 0; i != NumLaneElems; ++i) {
11548 // The mask element. This indexes into the input.
11549 int Idx = SVOp->getMaskElt(i+LaneStart);
11551 // the mask element does not index into any input vector.
11552 Mask.push_back(-1);
11556 // The input vector this mask element indexes into.
11557 int Input = Idx / NumLaneElems;
11559 // Turn the index into an offset from the start of the input vector.
11560 Idx -= Input * NumLaneElems;
11562 // Find or create a shuffle vector operand to hold this input.
11564 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11565 if (InputUsed[OpNo] == Input)
11566 // This input vector is already an operand.
11568 if (InputUsed[OpNo] < 0) {
11569 // Create a new operand for this input vector.
11570 InputUsed[OpNo] = Input;
11575 if (OpNo >= array_lengthof(InputUsed)) {
11576 // More than two input vectors used! Give up on trying to create a
11577 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11578 UseBuildVector = true;
11582 // Add the mask index for the new shuffle vector.
11583 Mask.push_back(Idx + OpNo * NumLaneElems);
11586 if (UseBuildVector) {
11587 SmallVector<SDValue, 16> SVOps;
11588 for (unsigned i = 0; i != NumLaneElems; ++i) {
11589 // The mask element. This indexes into the input.
11590 int Idx = SVOp->getMaskElt(i+LaneStart);
11592 SVOps.push_back(DAG.getUNDEF(EltVT));
11596 // The input vector this mask element indexes into.
11597 int Input = Idx / NumElems;
11599 // Turn the index into an offset from the start of the input vector.
11600 Idx -= Input * NumElems;
11602 // Extract the vector element by hand.
11603 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11604 SVOp->getOperand(Input),
11605 DAG.getIntPtrConstant(Idx)));
11608 // Construct the output using a BUILD_VECTOR.
11609 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11610 } else if (InputUsed[0] < 0) {
11611 // No input vectors were used! The result is undefined.
11612 Output[l] = DAG.getUNDEF(NVT);
11614 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11615 (InputUsed[0] % 2) * NumLaneElems,
11617 // If only one input was used, use an undefined vector for the other.
11618 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11619 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11620 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11621 // At least one input vector was used. Create a new shuffle vector.
11622 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11628 // Concatenate the result back
11629 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11632 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11633 /// 4 elements, and match them with several different shuffle types.
11635 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11636 SDValue V1 = SVOp->getOperand(0);
11637 SDValue V2 = SVOp->getOperand(1);
11639 MVT VT = SVOp->getSimpleValueType(0);
11641 assert(VT.is128BitVector() && "Unsupported vector size");
11643 std::pair<int, int> Locs[4];
11644 int Mask1[] = { -1, -1, -1, -1 };
11645 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11647 unsigned NumHi = 0;
11648 unsigned NumLo = 0;
11649 for (unsigned i = 0; i != 4; ++i) {
11650 int Idx = PermMask[i];
11652 Locs[i] = std::make_pair(-1, -1);
11654 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11656 Locs[i] = std::make_pair(0, NumLo);
11657 Mask1[NumLo] = Idx;
11660 Locs[i] = std::make_pair(1, NumHi);
11662 Mask1[2+NumHi] = Idx;
11668 if (NumLo <= 2 && NumHi <= 2) {
11669 // If no more than two elements come from either vector. This can be
11670 // implemented with two shuffles. First shuffle gather the elements.
11671 // The second shuffle, which takes the first shuffle as both of its
11672 // vector operands, put the elements into the right order.
11673 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11675 int Mask2[] = { -1, -1, -1, -1 };
11677 for (unsigned i = 0; i != 4; ++i)
11678 if (Locs[i].first != -1) {
11679 unsigned Idx = (i < 2) ? 0 : 4;
11680 Idx += Locs[i].first * 2 + Locs[i].second;
11684 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11687 if (NumLo == 3 || NumHi == 3) {
11688 // Otherwise, we must have three elements from one vector, call it X, and
11689 // one element from the other, call it Y. First, use a shufps to build an
11690 // intermediate vector with the one element from Y and the element from X
11691 // that will be in the same half in the final destination (the indexes don't
11692 // matter). Then, use a shufps to build the final vector, taking the half
11693 // containing the element from Y from the intermediate, and the other half
11696 // Normalize it so the 3 elements come from V1.
11697 CommuteVectorShuffleMask(PermMask, 4);
11701 // Find the element from V2.
11703 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11704 int Val = PermMask[HiIndex];
11711 Mask1[0] = PermMask[HiIndex];
11713 Mask1[2] = PermMask[HiIndex^1];
11715 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11717 if (HiIndex >= 2) {
11718 Mask1[0] = PermMask[0];
11719 Mask1[1] = PermMask[1];
11720 Mask1[2] = HiIndex & 1 ? 6 : 4;
11721 Mask1[3] = HiIndex & 1 ? 4 : 6;
11722 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11725 Mask1[0] = HiIndex & 1 ? 2 : 0;
11726 Mask1[1] = HiIndex & 1 ? 0 : 2;
11727 Mask1[2] = PermMask[2];
11728 Mask1[3] = PermMask[3];
11733 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11736 // Break it into (shuffle shuffle_hi, shuffle_lo).
11737 int LoMask[] = { -1, -1, -1, -1 };
11738 int HiMask[] = { -1, -1, -1, -1 };
11740 int *MaskPtr = LoMask;
11741 unsigned MaskIdx = 0;
11742 unsigned LoIdx = 0;
11743 unsigned HiIdx = 2;
11744 for (unsigned i = 0; i != 4; ++i) {
11751 int Idx = PermMask[i];
11753 Locs[i] = std::make_pair(-1, -1);
11754 } else if (Idx < 4) {
11755 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11756 MaskPtr[LoIdx] = Idx;
11759 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11760 MaskPtr[HiIdx] = Idx;
11765 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11766 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11767 int MaskOps[] = { -1, -1, -1, -1 };
11768 for (unsigned i = 0; i != 4; ++i)
11769 if (Locs[i].first != -1)
11770 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11771 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11774 static bool MayFoldVectorLoad(SDValue V) {
11775 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11776 V = V.getOperand(0);
11778 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11779 V = V.getOperand(0);
11780 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11781 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11782 // BUILD_VECTOR (load), undef
11783 V = V.getOperand(0);
11785 return MayFoldLoad(V);
11789 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11790 MVT VT = Op.getSimpleValueType();
11792 // Canonizalize to v2f64.
11793 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11794 return DAG.getNode(ISD::BITCAST, dl, VT,
11795 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11800 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11802 SDValue V1 = Op.getOperand(0);
11803 SDValue V2 = Op.getOperand(1);
11804 MVT VT = Op.getSimpleValueType();
11806 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11808 if (HasSSE2 && VT == MVT::v2f64)
11809 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11811 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11812 return DAG.getNode(ISD::BITCAST, dl, VT,
11813 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11814 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11815 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11819 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11820 SDValue V1 = Op.getOperand(0);
11821 SDValue V2 = Op.getOperand(1);
11822 MVT VT = Op.getSimpleValueType();
11824 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11825 "unsupported shuffle type");
11827 if (V2.getOpcode() == ISD::UNDEF)
11831 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11835 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11836 SDValue V1 = Op.getOperand(0);
11837 SDValue V2 = Op.getOperand(1);
11838 MVT VT = Op.getSimpleValueType();
11839 unsigned NumElems = VT.getVectorNumElements();
11841 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11842 // operand of these instructions is only memory, so check if there's a
11843 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11845 bool CanFoldLoad = false;
11847 // Trivial case, when V2 comes from a load.
11848 if (MayFoldVectorLoad(V2))
11849 CanFoldLoad = true;
11851 // When V1 is a load, it can be folded later into a store in isel, example:
11852 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11854 // (MOVLPSmr addr:$src1, VR128:$src2)
11855 // So, recognize this potential and also use MOVLPS or MOVLPD
11856 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11857 CanFoldLoad = true;
11859 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11861 if (HasSSE2 && NumElems == 2)
11862 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11865 // If we don't care about the second element, proceed to use movss.
11866 if (SVOp->getMaskElt(1) != -1)
11867 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11870 // movl and movlp will both match v2i64, but v2i64 is never matched by
11871 // movl earlier because we make it strict to avoid messing with the movlp load
11872 // folding logic (see the code above getMOVLP call). Match it here then,
11873 // this is horrible, but will stay like this until we move all shuffle
11874 // matching to x86 specific nodes. Note that for the 1st condition all
11875 // types are matched with movsd.
11877 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11878 // as to remove this logic from here, as much as possible
11879 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11880 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11881 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11884 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11886 // Invert the operand order and use SHUFPS to match it.
11887 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11888 getShuffleSHUFImmediate(SVOp), DAG);
11891 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11892 SelectionDAG &DAG) {
11894 MVT VT = Load->getSimpleValueType(0);
11895 MVT EVT = VT.getVectorElementType();
11896 SDValue Addr = Load->getOperand(1);
11897 SDValue NewAddr = DAG.getNode(
11898 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11899 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11902 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11903 DAG.getMachineFunction().getMachineMemOperand(
11904 Load->getMemOperand(), 0, EVT.getStoreSize()));
11908 // It is only safe to call this function if isINSERTPSMask is true for
11909 // this shufflevector mask.
11910 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11911 SelectionDAG &DAG) {
11912 // Generate an insertps instruction when inserting an f32 from memory onto a
11913 // v4f32 or when copying a member from one v4f32 to another.
11914 // We also use it for transferring i32 from one register to another,
11915 // since it simply copies the same bits.
11916 // If we're transferring an i32 from memory to a specific element in a
11917 // register, we output a generic DAG that will match the PINSRD
11919 MVT VT = SVOp->getSimpleValueType(0);
11920 MVT EVT = VT.getVectorElementType();
11921 SDValue V1 = SVOp->getOperand(0);
11922 SDValue V2 = SVOp->getOperand(1);
11923 auto Mask = SVOp->getMask();
11924 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11925 "unsupported vector type for insertps/pinsrd");
11927 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11928 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11929 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11933 unsigned DestIndex;
11937 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11940 // If we have 1 element from each vector, we have to check if we're
11941 // changing V1's element's place. If so, we're done. Otherwise, we
11942 // should assume we're changing V2's element's place and behave
11944 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11945 assert(DestIndex <= INT32_MAX && "truncated destination index");
11946 if (FromV1 == FromV2 &&
11947 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11951 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11954 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11955 "More than one element from V1 and from V2, or no elements from one "
11956 "of the vectors. This case should not have returned true from "
11961 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11964 // Get an index into the source vector in the range [0,4) (the mask is
11965 // in the range [0,8) because it can address V1 and V2)
11966 unsigned SrcIndex = Mask[DestIndex] % 4;
11967 if (MayFoldLoad(From)) {
11968 // Trivial case, when From comes from a load and is only used by the
11969 // shuffle. Make it use insertps from the vector that we need from that
11972 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11973 if (!NewLoad.getNode())
11976 if (EVT == MVT::f32) {
11977 // Create this as a scalar to vector to match the instruction pattern.
11978 SDValue LoadScalarToVector =
11979 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11980 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11981 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11983 } else { // EVT == MVT::i32
11984 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11985 // instruction, to match the PINSRD instruction, which loads an i32 to a
11986 // certain vector element.
11987 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11988 DAG.getConstant(DestIndex, MVT::i32));
11992 // Vector-element-to-vector
11993 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11994 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11997 // Reduce a vector shuffle to zext.
11998 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11999 SelectionDAG &DAG) {
12000 // PMOVZX is only available from SSE41.
12001 if (!Subtarget->hasSSE41())
12004 MVT VT = Op.getSimpleValueType();
12006 // Only AVX2 support 256-bit vector integer extending.
12007 if (!Subtarget->hasInt256() && VT.is256BitVector())
12010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12012 SDValue V1 = Op.getOperand(0);
12013 SDValue V2 = Op.getOperand(1);
12014 unsigned NumElems = VT.getVectorNumElements();
12016 // Extending is an unary operation and the element type of the source vector
12017 // won't be equal to or larger than i64.
12018 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12019 VT.getVectorElementType() == MVT::i64)
12022 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12023 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12024 while ((1U << Shift) < NumElems) {
12025 if (SVOp->getMaskElt(1U << Shift) == 1)
12028 // The maximal ratio is 8, i.e. from i8 to i64.
12033 // Check the shuffle mask.
12034 unsigned Mask = (1U << Shift) - 1;
12035 for (unsigned i = 0; i != NumElems; ++i) {
12036 int EltIdx = SVOp->getMaskElt(i);
12037 if ((i & Mask) != 0 && EltIdx != -1)
12039 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12043 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12044 MVT NeVT = MVT::getIntegerVT(NBits);
12045 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12047 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12050 return DAG.getNode(ISD::BITCAST, DL, VT,
12051 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12054 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12055 SelectionDAG &DAG) {
12056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12057 MVT VT = Op.getSimpleValueType();
12059 SDValue V1 = Op.getOperand(0);
12060 SDValue V2 = Op.getOperand(1);
12062 if (isZeroShuffle(SVOp))
12063 return getZeroVector(VT, Subtarget, DAG, dl);
12065 // Handle splat operations
12066 if (SVOp->isSplat()) {
12067 // Use vbroadcast whenever the splat comes from a foldable load
12068 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12069 if (Broadcast.getNode())
12073 // Check integer expanding shuffles.
12074 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12075 if (NewOp.getNode())
12078 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12080 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12081 VT == MVT::v32i8) {
12082 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12083 if (NewOp.getNode())
12084 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12085 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12086 // FIXME: Figure out a cleaner way to do this.
12087 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12088 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12089 if (NewOp.getNode()) {
12090 MVT NewVT = NewOp.getSimpleValueType();
12091 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12092 NewVT, true, false))
12093 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12096 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12097 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12098 if (NewOp.getNode()) {
12099 MVT NewVT = NewOp.getSimpleValueType();
12100 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12101 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12110 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12111 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12112 SDValue V1 = Op.getOperand(0);
12113 SDValue V2 = Op.getOperand(1);
12114 MVT VT = Op.getSimpleValueType();
12116 unsigned NumElems = VT.getVectorNumElements();
12117 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12118 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12119 bool V1IsSplat = false;
12120 bool V2IsSplat = false;
12121 bool HasSSE2 = Subtarget->hasSSE2();
12122 bool HasFp256 = Subtarget->hasFp256();
12123 bool HasInt256 = Subtarget->hasInt256();
12124 MachineFunction &MF = DAG.getMachineFunction();
12125 bool OptForSize = MF.getFunction()->getAttributes().
12126 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12128 // Check if we should use the experimental vector shuffle lowering. If so,
12129 // delegate completely to that code path.
12130 if (ExperimentalVectorShuffleLowering)
12131 return lowerVectorShuffle(Op, Subtarget, DAG);
12133 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12135 if (V1IsUndef && V2IsUndef)
12136 return DAG.getUNDEF(VT);
12138 // When we create a shuffle node we put the UNDEF node to second operand,
12139 // but in some cases the first operand may be transformed to UNDEF.
12140 // In this case we should just commute the node.
12142 return DAG.getCommutedVectorShuffle(*SVOp);
12144 // Vector shuffle lowering takes 3 steps:
12146 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12147 // narrowing and commutation of operands should be handled.
12148 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12150 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12151 // so the shuffle can be broken into other shuffles and the legalizer can
12152 // try the lowering again.
12154 // The general idea is that no vector_shuffle operation should be left to
12155 // be matched during isel, all of them must be converted to a target specific
12158 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12159 // narrowing and commutation of operands should be handled. The actual code
12160 // doesn't include all of those, work in progress...
12161 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12162 if (NewOp.getNode())
12165 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12167 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12168 // unpckh_undef). Only use pshufd if speed is more important than size.
12169 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12170 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12171 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12172 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12174 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12175 V2IsUndef && MayFoldVectorLoad(V1))
12176 return getMOVDDup(Op, dl, V1, DAG);
12178 if (isMOVHLPS_v_undef_Mask(M, VT))
12179 return getMOVHighToLow(Op, dl, DAG);
12181 // Use to match splats
12182 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12183 (VT == MVT::v2f64 || VT == MVT::v2i64))
12184 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12186 if (isPSHUFDMask(M, VT)) {
12187 // The actual implementation will match the mask in the if above and then
12188 // during isel it can match several different instructions, not only pshufd
12189 // as its name says, sad but true, emulate the behavior for now...
12190 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12191 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12193 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12195 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12196 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12198 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12199 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12202 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12206 if (isPALIGNRMask(M, VT, Subtarget))
12207 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12208 getShufflePALIGNRImmediate(SVOp),
12211 if (isVALIGNMask(M, VT, Subtarget))
12212 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12213 getShuffleVALIGNImmediate(SVOp),
12216 // Check if this can be converted into a logical shift.
12217 bool isLeft = false;
12218 unsigned ShAmt = 0;
12220 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12221 if (isShift && ShVal.hasOneUse()) {
12222 // If the shifted value has multiple uses, it may be cheaper to use
12223 // v_set0 + movlhps or movhlps, etc.
12224 MVT EltVT = VT.getVectorElementType();
12225 ShAmt *= EltVT.getSizeInBits();
12226 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12229 if (isMOVLMask(M, VT)) {
12230 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12231 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12232 if (!isMOVLPMask(M, VT)) {
12233 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12234 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12236 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12237 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12241 // FIXME: fold these into legal mask.
12242 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12243 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12245 if (isMOVHLPSMask(M, VT))
12246 return getMOVHighToLow(Op, dl, DAG);
12248 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12249 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12251 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12252 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12254 if (isMOVLPMask(M, VT))
12255 return getMOVLP(Op, dl, DAG, HasSSE2);
12257 if (ShouldXformToMOVHLPS(M, VT) ||
12258 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12259 return DAG.getCommutedVectorShuffle(*SVOp);
12262 // No better options. Use a vshldq / vsrldq.
12263 MVT EltVT = VT.getVectorElementType();
12264 ShAmt *= EltVT.getSizeInBits();
12265 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12268 bool Commuted = false;
12269 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12270 // 1,1,1,1 -> v8i16 though.
12271 BitVector UndefElements;
12272 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12273 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12275 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12276 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12279 // Canonicalize the splat or undef, if present, to be on the RHS.
12280 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12281 CommuteVectorShuffleMask(M, NumElems);
12283 std::swap(V1IsSplat, V2IsSplat);
12287 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12288 // Shuffling low element of v1 into undef, just return v1.
12291 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12292 // the instruction selector will not match, so get a canonical MOVL with
12293 // swapped operands to undo the commute.
12294 return getMOVL(DAG, dl, VT, V2, V1);
12297 if (isUNPCKLMask(M, VT, HasInt256))
12298 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12300 if (isUNPCKHMask(M, VT, HasInt256))
12301 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12304 // Normalize mask so all entries that point to V2 points to its first
12305 // element then try to match unpck{h|l} again. If match, return a
12306 // new vector_shuffle with the corrected mask.p
12307 SmallVector<int, 8> NewMask(M.begin(), M.end());
12308 NormalizeMask(NewMask, NumElems);
12309 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12310 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12311 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12312 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12316 // Commute is back and try unpck* again.
12317 // FIXME: this seems wrong.
12318 CommuteVectorShuffleMask(M, NumElems);
12320 std::swap(V1IsSplat, V2IsSplat);
12322 if (isUNPCKLMask(M, VT, HasInt256))
12323 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12325 if (isUNPCKHMask(M, VT, HasInt256))
12326 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12329 // Normalize the node to match x86 shuffle ops if needed
12330 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12331 return DAG.getCommutedVectorShuffle(*SVOp);
12333 // The checks below are all present in isShuffleMaskLegal, but they are
12334 // inlined here right now to enable us to directly emit target specific
12335 // nodes, and remove one by one until they don't return Op anymore.
12337 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12338 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12339 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12340 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12343 if (isPSHUFHWMask(M, VT, HasInt256))
12344 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12345 getShufflePSHUFHWImmediate(SVOp),
12348 if (isPSHUFLWMask(M, VT, HasInt256))
12349 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12350 getShufflePSHUFLWImmediate(SVOp),
12353 unsigned MaskValue;
12354 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12356 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12358 if (isSHUFPMask(M, VT))
12359 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12360 getShuffleSHUFImmediate(SVOp), DAG);
12362 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12363 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12364 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12365 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12367 //===--------------------------------------------------------------------===//
12368 // Generate target specific nodes for 128 or 256-bit shuffles only
12369 // supported in the AVX instruction set.
12372 // Handle VMOVDDUPY permutations
12373 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12374 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12376 // Handle VPERMILPS/D* permutations
12377 if (isVPERMILPMask(M, VT)) {
12378 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12379 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12380 getShuffleSHUFImmediate(SVOp), DAG);
12381 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12382 getShuffleSHUFImmediate(SVOp), DAG);
12386 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12387 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12388 Idx*(NumElems/2), DAG, dl);
12390 // Handle VPERM2F128/VPERM2I128 permutations
12391 if (isVPERM2X128Mask(M, VT, HasFp256))
12392 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12393 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12395 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12396 return getINSERTPS(SVOp, dl, DAG);
12399 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12400 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12402 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12403 VT.is512BitVector()) {
12404 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12405 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12406 SmallVector<SDValue, 16> permclMask;
12407 for (unsigned i = 0; i != NumElems; ++i) {
12408 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12411 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12413 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12414 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12415 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12416 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12417 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12420 //===--------------------------------------------------------------------===//
12421 // Since no target specific shuffle was selected for this generic one,
12422 // lower it into other known shuffles. FIXME: this isn't true yet, but
12423 // this is the plan.
12426 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12427 if (VT == MVT::v8i16) {
12428 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12429 if (NewOp.getNode())
12433 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12434 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12435 if (NewOp.getNode())
12439 if (VT == MVT::v16i8) {
12440 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12441 if (NewOp.getNode())
12445 if (VT == MVT::v32i8) {
12446 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12447 if (NewOp.getNode())
12451 // Handle all 128-bit wide vectors with 4 elements, and match them with
12452 // several different shuffle types.
12453 if (NumElems == 4 && VT.is128BitVector())
12454 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12456 // Handle general 256-bit shuffles
12457 if (VT.is256BitVector())
12458 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12463 // This function assumes its argument is a BUILD_VECTOR of constants or
12464 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12466 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12467 unsigned &MaskValue) {
12469 unsigned NumElems = BuildVector->getNumOperands();
12470 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12471 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12472 unsigned NumElemsInLane = NumElems / NumLanes;
12474 // Blend for v16i16 should be symetric for the both lanes.
12475 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12476 SDValue EltCond = BuildVector->getOperand(i);
12477 SDValue SndLaneEltCond =
12478 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12480 int Lane1Cond = -1, Lane2Cond = -1;
12481 if (isa<ConstantSDNode>(EltCond))
12482 Lane1Cond = !isZero(EltCond);
12483 if (isa<ConstantSDNode>(SndLaneEltCond))
12484 Lane2Cond = !isZero(SndLaneEltCond);
12486 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12487 // Lane1Cond != 0, means we want the first argument.
12488 // Lane1Cond == 0, means we want the second argument.
12489 // The encoding of this argument is 0 for the first argument, 1
12490 // for the second. Therefore, invert the condition.
12491 MaskValue |= !Lane1Cond << i;
12492 else if (Lane1Cond < 0)
12493 MaskValue |= !Lane2Cond << i;
12500 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12502 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12503 SelectionDAG &DAG) {
12504 SDValue Cond = Op.getOperand(0);
12505 SDValue LHS = Op.getOperand(1);
12506 SDValue RHS = Op.getOperand(2);
12508 MVT VT = Op.getSimpleValueType();
12509 MVT EltVT = VT.getVectorElementType();
12510 unsigned NumElems = VT.getVectorNumElements();
12512 // There is no blend with immediate in AVX-512.
12513 if (VT.is512BitVector())
12516 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12518 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12521 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12524 // Check the mask for BLEND and build the value.
12525 unsigned MaskValue = 0;
12526 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12529 // Convert i32 vectors to floating point if it is not AVX2.
12530 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12532 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12533 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12535 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12536 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12539 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12540 DAG.getConstant(MaskValue, MVT::i32));
12541 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12544 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12545 // A vselect where all conditions and data are constants can be optimized into
12546 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12547 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12548 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12549 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12552 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12553 if (BlendOp.getNode())
12556 // Some types for vselect were previously set to Expand, not Legal or
12557 // Custom. Return an empty SDValue so we fall-through to Expand, after
12558 // the Custom lowering phase.
12559 MVT VT = Op.getSimpleValueType();
12560 switch (VT.SimpleTy) {
12565 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12570 // We couldn't create a "Blend with immediate" node.
12571 // This node should still be legal, but we'll have to emit a blendv*
12576 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12577 MVT VT = Op.getSimpleValueType();
12580 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12583 if (VT.getSizeInBits() == 8) {
12584 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12585 Op.getOperand(0), Op.getOperand(1));
12586 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12587 DAG.getValueType(VT));
12588 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12591 if (VT.getSizeInBits() == 16) {
12592 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12593 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12595 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12596 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12597 DAG.getNode(ISD::BITCAST, dl,
12600 Op.getOperand(1)));
12601 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12602 Op.getOperand(0), Op.getOperand(1));
12603 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12604 DAG.getValueType(VT));
12605 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12608 if (VT == MVT::f32) {
12609 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12610 // the result back to FR32 register. It's only worth matching if the
12611 // result has a single use which is a store or a bitcast to i32. And in
12612 // the case of a store, it's not worth it if the index is a constant 0,
12613 // because a MOVSSmr can be used instead, which is smaller and faster.
12614 if (!Op.hasOneUse())
12616 SDNode *User = *Op.getNode()->use_begin();
12617 if ((User->getOpcode() != ISD::STORE ||
12618 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12619 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12620 (User->getOpcode() != ISD::BITCAST ||
12621 User->getValueType(0) != MVT::i32))
12623 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12624 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12627 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12630 if (VT == MVT::i32 || VT == MVT::i64) {
12631 // ExtractPS/pextrq works with constant index.
12632 if (isa<ConstantSDNode>(Op.getOperand(1)))
12638 /// Extract one bit from mask vector, like v16i1 or v8i1.
12639 /// AVX-512 feature.
12641 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12642 SDValue Vec = Op.getOperand(0);
12644 MVT VecVT = Vec.getSimpleValueType();
12645 SDValue Idx = Op.getOperand(1);
12646 MVT EltVT = Op.getSimpleValueType();
12648 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12650 // variable index can't be handled in mask registers,
12651 // extend vector to VR512
12652 if (!isa<ConstantSDNode>(Idx)) {
12653 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12654 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12655 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12656 ExtVT.getVectorElementType(), Ext, Idx);
12657 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12660 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12661 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12662 unsigned MaxSift = rc->getSize()*8 - 1;
12663 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12664 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12665 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12666 DAG.getConstant(MaxSift, MVT::i8));
12667 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12668 DAG.getIntPtrConstant(0));
12672 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12673 SelectionDAG &DAG) const {
12675 SDValue Vec = Op.getOperand(0);
12676 MVT VecVT = Vec.getSimpleValueType();
12677 SDValue Idx = Op.getOperand(1);
12679 if (Op.getSimpleValueType() == MVT::i1)
12680 return ExtractBitFromMaskVector(Op, DAG);
12682 if (!isa<ConstantSDNode>(Idx)) {
12683 if (VecVT.is512BitVector() ||
12684 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12685 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12688 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12689 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12690 MaskEltVT.getSizeInBits());
12692 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12693 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12694 getZeroVector(MaskVT, Subtarget, DAG, dl),
12695 Idx, DAG.getConstant(0, getPointerTy()));
12696 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12697 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12698 Perm, DAG.getConstant(0, getPointerTy()));
12703 // If this is a 256-bit vector result, first extract the 128-bit vector and
12704 // then extract the element from the 128-bit vector.
12705 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12707 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12708 // Get the 128-bit vector.
12709 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12710 MVT EltVT = VecVT.getVectorElementType();
12712 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12714 //if (IdxVal >= NumElems/2)
12715 // IdxVal -= NumElems/2;
12716 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12717 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12718 DAG.getConstant(IdxVal, MVT::i32));
12721 assert(VecVT.is128BitVector() && "Unexpected vector length");
12723 if (Subtarget->hasSSE41()) {
12724 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12729 MVT VT = Op.getSimpleValueType();
12730 // TODO: handle v16i8.
12731 if (VT.getSizeInBits() == 16) {
12732 SDValue Vec = Op.getOperand(0);
12733 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12735 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12736 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12737 DAG.getNode(ISD::BITCAST, dl,
12739 Op.getOperand(1)));
12740 // Transform it so it match pextrw which produces a 32-bit result.
12741 MVT EltVT = MVT::i32;
12742 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12743 Op.getOperand(0), Op.getOperand(1));
12744 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12745 DAG.getValueType(VT));
12746 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12749 if (VT.getSizeInBits() == 32) {
12750 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12754 // SHUFPS the element to the lowest double word, then movss.
12755 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12756 MVT VVT = Op.getOperand(0).getSimpleValueType();
12757 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12758 DAG.getUNDEF(VVT), Mask);
12759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12760 DAG.getIntPtrConstant(0));
12763 if (VT.getSizeInBits() == 64) {
12764 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12765 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12766 // to match extract_elt for f64.
12767 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12771 // UNPCKHPD the element to the lowest double word, then movsd.
12772 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12773 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12774 int Mask[2] = { 1, -1 };
12775 MVT VVT = Op.getOperand(0).getSimpleValueType();
12776 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12777 DAG.getUNDEF(VVT), Mask);
12778 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12779 DAG.getIntPtrConstant(0));
12785 /// Insert one bit to mask vector, like v16i1 or v8i1.
12786 /// AVX-512 feature.
12788 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12790 SDValue Vec = Op.getOperand(0);
12791 SDValue Elt = Op.getOperand(1);
12792 SDValue Idx = Op.getOperand(2);
12793 MVT VecVT = Vec.getSimpleValueType();
12795 if (!isa<ConstantSDNode>(Idx)) {
12796 // Non constant index. Extend source and destination,
12797 // insert element and then truncate the result.
12798 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12799 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12800 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12801 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12802 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12803 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12806 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12807 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12808 if (Vec.getOpcode() == ISD::UNDEF)
12809 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12810 DAG.getConstant(IdxVal, MVT::i8));
12811 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12812 unsigned MaxSift = rc->getSize()*8 - 1;
12813 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12814 DAG.getConstant(MaxSift, MVT::i8));
12815 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12816 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12817 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12820 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12821 SelectionDAG &DAG) const {
12822 MVT VT = Op.getSimpleValueType();
12823 MVT EltVT = VT.getVectorElementType();
12825 if (EltVT == MVT::i1)
12826 return InsertBitToMaskVector(Op, DAG);
12829 SDValue N0 = Op.getOperand(0);
12830 SDValue N1 = Op.getOperand(1);
12831 SDValue N2 = Op.getOperand(2);
12832 if (!isa<ConstantSDNode>(N2))
12834 auto *N2C = cast<ConstantSDNode>(N2);
12835 unsigned IdxVal = N2C->getZExtValue();
12837 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12838 // into that, and then insert the subvector back into the result.
12839 if (VT.is256BitVector() || VT.is512BitVector()) {
12840 // Get the desired 128-bit vector half.
12841 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12843 // Insert the element into the desired half.
12844 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12845 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12847 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12848 DAG.getConstant(IdxIn128, MVT::i32));
12850 // Insert the changed part back to the 256-bit vector
12851 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12853 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12855 if (Subtarget->hasSSE41()) {
12856 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12858 if (VT == MVT::v8i16) {
12859 Opc = X86ISD::PINSRW;
12861 assert(VT == MVT::v16i8);
12862 Opc = X86ISD::PINSRB;
12865 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12867 if (N1.getValueType() != MVT::i32)
12868 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12869 if (N2.getValueType() != MVT::i32)
12870 N2 = DAG.getIntPtrConstant(IdxVal);
12871 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12874 if (EltVT == MVT::f32) {
12875 // Bits [7:6] of the constant are the source select. This will always be
12876 // zero here. The DAG Combiner may combine an extract_elt index into
12878 // bits. For example (insert (extract, 3), 2) could be matched by
12880 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12881 // Bits [5:4] of the constant are the destination select. This is the
12882 // value of the incoming immediate.
12883 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12884 // combine either bitwise AND or insert of float 0.0 to set these bits.
12885 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12886 // Create this as a scalar to vector..
12887 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12888 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12891 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12892 // PINSR* works with constant index.
12897 if (EltVT == MVT::i8)
12900 if (EltVT.getSizeInBits() == 16) {
12901 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12902 // as its second argument.
12903 if (N1.getValueType() != MVT::i32)
12904 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12905 if (N2.getValueType() != MVT::i32)
12906 N2 = DAG.getIntPtrConstant(IdxVal);
12907 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12912 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12914 MVT OpVT = Op.getSimpleValueType();
12916 // If this is a 256-bit vector result, first insert into a 128-bit
12917 // vector and then insert into the 256-bit vector.
12918 if (!OpVT.is128BitVector()) {
12919 // Insert into a 128-bit vector.
12920 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12921 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12922 OpVT.getVectorNumElements() / SizeFactor);
12924 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12926 // Insert the 128-bit vector.
12927 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12930 if (OpVT == MVT::v1i64 &&
12931 Op.getOperand(0).getValueType() == MVT::i64)
12932 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12934 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12935 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12936 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12940 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12941 // a simple subregister reference or explicit instructions to grab
12942 // upper bits of a vector.
12943 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12944 SelectionDAG &DAG) {
12946 SDValue In = Op.getOperand(0);
12947 SDValue Idx = Op.getOperand(1);
12948 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12949 MVT ResVT = Op.getSimpleValueType();
12950 MVT InVT = In.getSimpleValueType();
12952 if (Subtarget->hasFp256()) {
12953 if (ResVT.is128BitVector() &&
12954 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12955 isa<ConstantSDNode>(Idx)) {
12956 return Extract128BitVector(In, IdxVal, DAG, dl);
12958 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12959 isa<ConstantSDNode>(Idx)) {
12960 return Extract256BitVector(In, IdxVal, DAG, dl);
12966 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12967 // simple superregister reference or explicit instructions to insert
12968 // the upper bits of a vector.
12969 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12970 SelectionDAG &DAG) {
12971 if (Subtarget->hasFp256()) {
12972 SDLoc dl(Op.getNode());
12973 SDValue Vec = Op.getNode()->getOperand(0);
12974 SDValue SubVec = Op.getNode()->getOperand(1);
12975 SDValue Idx = Op.getNode()->getOperand(2);
12977 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12978 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12979 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12980 isa<ConstantSDNode>(Idx)) {
12981 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12982 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12985 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12986 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12987 isa<ConstantSDNode>(Idx)) {
12988 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12989 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12995 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12996 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12997 // one of the above mentioned nodes. It has to be wrapped because otherwise
12998 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12999 // be used to form addressing mode. These wrapped nodes will be selected
13002 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13003 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13005 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13006 // global base reg.
13007 unsigned char OpFlag = 0;
13008 unsigned WrapperKind = X86ISD::Wrapper;
13009 CodeModel::Model M = DAG.getTarget().getCodeModel();
13011 if (Subtarget->isPICStyleRIPRel() &&
13012 (M == CodeModel::Small || M == CodeModel::Kernel))
13013 WrapperKind = X86ISD::WrapperRIP;
13014 else if (Subtarget->isPICStyleGOT())
13015 OpFlag = X86II::MO_GOTOFF;
13016 else if (Subtarget->isPICStyleStubPIC())
13017 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13019 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13020 CP->getAlignment(),
13021 CP->getOffset(), OpFlag);
13023 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13024 // With PIC, the address is actually $g + Offset.
13026 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13027 DAG.getNode(X86ISD::GlobalBaseReg,
13028 SDLoc(), getPointerTy()),
13035 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13036 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13038 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13039 // global base reg.
13040 unsigned char OpFlag = 0;
13041 unsigned WrapperKind = X86ISD::Wrapper;
13042 CodeModel::Model M = DAG.getTarget().getCodeModel();
13044 if (Subtarget->isPICStyleRIPRel() &&
13045 (M == CodeModel::Small || M == CodeModel::Kernel))
13046 WrapperKind = X86ISD::WrapperRIP;
13047 else if (Subtarget->isPICStyleGOT())
13048 OpFlag = X86II::MO_GOTOFF;
13049 else if (Subtarget->isPICStyleStubPIC())
13050 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13052 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13055 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13057 // With PIC, the address is actually $g + Offset.
13059 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13060 DAG.getNode(X86ISD::GlobalBaseReg,
13061 SDLoc(), getPointerTy()),
13068 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13069 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13071 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13072 // global base reg.
13073 unsigned char OpFlag = 0;
13074 unsigned WrapperKind = X86ISD::Wrapper;
13075 CodeModel::Model M = DAG.getTarget().getCodeModel();
13077 if (Subtarget->isPICStyleRIPRel() &&
13078 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13079 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13080 OpFlag = X86II::MO_GOTPCREL;
13081 WrapperKind = X86ISD::WrapperRIP;
13082 } else if (Subtarget->isPICStyleGOT()) {
13083 OpFlag = X86II::MO_GOT;
13084 } else if (Subtarget->isPICStyleStubPIC()) {
13085 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13086 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13087 OpFlag = X86II::MO_DARWIN_NONLAZY;
13090 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13093 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13095 // With PIC, the address is actually $g + Offset.
13096 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13097 !Subtarget->is64Bit()) {
13098 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13099 DAG.getNode(X86ISD::GlobalBaseReg,
13100 SDLoc(), getPointerTy()),
13104 // For symbols that require a load from a stub to get the address, emit the
13106 if (isGlobalStubReference(OpFlag))
13107 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13108 MachinePointerInfo::getGOT(), false, false, false, 0);
13114 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13115 // Create the TargetBlockAddressAddress node.
13116 unsigned char OpFlags =
13117 Subtarget->ClassifyBlockAddressReference();
13118 CodeModel::Model M = DAG.getTarget().getCodeModel();
13119 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13120 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13122 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13125 if (Subtarget->isPICStyleRIPRel() &&
13126 (M == CodeModel::Small || M == CodeModel::Kernel))
13127 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13129 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13131 // With PIC, the address is actually $g + Offset.
13132 if (isGlobalRelativeToPICBase(OpFlags)) {
13133 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13134 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13142 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13143 int64_t Offset, SelectionDAG &DAG) const {
13144 // Create the TargetGlobalAddress node, folding in the constant
13145 // offset if it is legal.
13146 unsigned char OpFlags =
13147 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13148 CodeModel::Model M = DAG.getTarget().getCodeModel();
13150 if (OpFlags == X86II::MO_NO_FLAG &&
13151 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13152 // A direct static reference to a global.
13153 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13156 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13159 if (Subtarget->isPICStyleRIPRel() &&
13160 (M == CodeModel::Small || M == CodeModel::Kernel))
13161 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13163 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13165 // With PIC, the address is actually $g + Offset.
13166 if (isGlobalRelativeToPICBase(OpFlags)) {
13167 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13168 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13172 // For globals that require a load from a stub to get the address, emit the
13174 if (isGlobalStubReference(OpFlags))
13175 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13176 MachinePointerInfo::getGOT(), false, false, false, 0);
13178 // If there was a non-zero offset that we didn't fold, create an explicit
13179 // addition for it.
13181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13182 DAG.getConstant(Offset, getPointerTy()));
13188 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13189 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13190 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13191 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13195 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13196 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13197 unsigned char OperandFlags, bool LocalDynamic = false) {
13198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13199 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13201 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13202 GA->getValueType(0),
13206 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13210 SDValue Ops[] = { Chain, TGA, *InFlag };
13211 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13213 SDValue Ops[] = { Chain, TGA };
13214 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13217 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13218 MFI->setAdjustsStack(true);
13219 MFI->setHasCalls(true);
13221 SDValue Flag = Chain.getValue(1);
13222 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13225 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13227 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13230 SDLoc dl(GA); // ? function entry point might be better
13231 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13232 DAG.getNode(X86ISD::GlobalBaseReg,
13233 SDLoc(), PtrVT), InFlag);
13234 InFlag = Chain.getValue(1);
13236 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13239 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13241 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13243 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13244 X86::RAX, X86II::MO_TLSGD);
13247 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13253 // Get the start address of the TLS block for this module.
13254 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13255 .getInfo<X86MachineFunctionInfo>();
13256 MFI->incNumLocalDynamicTLSAccesses();
13260 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13261 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13264 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13265 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13266 InFlag = Chain.getValue(1);
13267 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13268 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13271 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13275 unsigned char OperandFlags = X86II::MO_DTPOFF;
13276 unsigned WrapperKind = X86ISD::Wrapper;
13277 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13278 GA->getValueType(0),
13279 GA->getOffset(), OperandFlags);
13280 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13282 // Add x@dtpoff with the base.
13283 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13286 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13287 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13288 const EVT PtrVT, TLSModel::Model model,
13289 bool is64Bit, bool isPIC) {
13292 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13293 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13294 is64Bit ? 257 : 256));
13296 SDValue ThreadPointer =
13297 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13298 MachinePointerInfo(Ptr), false, false, false, 0);
13300 unsigned char OperandFlags = 0;
13301 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13303 unsigned WrapperKind = X86ISD::Wrapper;
13304 if (model == TLSModel::LocalExec) {
13305 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13306 } else if (model == TLSModel::InitialExec) {
13308 OperandFlags = X86II::MO_GOTTPOFF;
13309 WrapperKind = X86ISD::WrapperRIP;
13311 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13314 llvm_unreachable("Unexpected model");
13317 // emit "addl x@ntpoff,%eax" (local exec)
13318 // or "addl x@indntpoff,%eax" (initial exec)
13319 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13321 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13322 GA->getOffset(), OperandFlags);
13323 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13325 if (model == TLSModel::InitialExec) {
13326 if (isPIC && !is64Bit) {
13327 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13328 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13332 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13333 MachinePointerInfo::getGOT(), false, false, false, 0);
13336 // The address of the thread local variable is the add of the thread
13337 // pointer with the offset of the variable.
13338 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13342 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13344 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13345 const GlobalValue *GV = GA->getGlobal();
13347 if (Subtarget->isTargetELF()) {
13348 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13351 case TLSModel::GeneralDynamic:
13352 if (Subtarget->is64Bit())
13353 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13354 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13355 case TLSModel::LocalDynamic:
13356 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13357 Subtarget->is64Bit());
13358 case TLSModel::InitialExec:
13359 case TLSModel::LocalExec:
13360 return LowerToTLSExecModel(
13361 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13362 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13364 llvm_unreachable("Unknown TLS model.");
13367 if (Subtarget->isTargetDarwin()) {
13368 // Darwin only has one model of TLS. Lower to that.
13369 unsigned char OpFlag = 0;
13370 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13371 X86ISD::WrapperRIP : X86ISD::Wrapper;
13373 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13374 // global base reg.
13375 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13376 !Subtarget->is64Bit();
13378 OpFlag = X86II::MO_TLVP_PIC_BASE;
13380 OpFlag = X86II::MO_TLVP;
13382 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13383 GA->getValueType(0),
13384 GA->getOffset(), OpFlag);
13385 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13387 // With PIC32, the address is actually $g + Offset.
13389 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13390 DAG.getNode(X86ISD::GlobalBaseReg,
13391 SDLoc(), getPointerTy()),
13394 // Lowering the machine isd will make sure everything is in the right
13396 SDValue Chain = DAG.getEntryNode();
13397 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13398 SDValue Args[] = { Chain, Offset };
13399 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13401 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13402 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13403 MFI->setAdjustsStack(true);
13405 // And our return value (tls address) is in the standard call return value
13407 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13408 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13409 Chain.getValue(1));
13412 if (Subtarget->isTargetKnownWindowsMSVC() ||
13413 Subtarget->isTargetWindowsGNU()) {
13414 // Just use the implicit TLS architecture
13415 // Need to generate someting similar to:
13416 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13418 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13419 // mov rcx, qword [rdx+rcx*8]
13420 // mov eax, .tls$:tlsvar
13421 // [rax+rcx] contains the address
13422 // Windows 64bit: gs:0x58
13423 // Windows 32bit: fs:__tls_array
13426 SDValue Chain = DAG.getEntryNode();
13428 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13429 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13430 // use its literal value of 0x2C.
13431 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13432 ? Type::getInt8PtrTy(*DAG.getContext(),
13434 : Type::getInt32PtrTy(*DAG.getContext(),
13438 Subtarget->is64Bit()
13439 ? DAG.getIntPtrConstant(0x58)
13440 : (Subtarget->isTargetWindowsGNU()
13441 ? DAG.getIntPtrConstant(0x2C)
13442 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13444 SDValue ThreadPointer =
13445 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13446 MachinePointerInfo(Ptr), false, false, false, 0);
13448 // Load the _tls_index variable
13449 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13450 if (Subtarget->is64Bit())
13451 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13452 IDX, MachinePointerInfo(), MVT::i32,
13453 false, false, false, 0);
13455 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13456 false, false, false, 0);
13458 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13460 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13462 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13463 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13464 false, false, false, 0);
13466 // Get the offset of start of .tls section
13467 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13468 GA->getValueType(0),
13469 GA->getOffset(), X86II::MO_SECREL);
13470 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13472 // The address of the thread local variable is the add of the thread
13473 // pointer with the offset of the variable.
13474 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13477 llvm_unreachable("TLS not implemented for this target.");
13480 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13481 /// and take a 2 x i32 value to shift plus a shift amount.
13482 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13483 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13484 MVT VT = Op.getSimpleValueType();
13485 unsigned VTBits = VT.getSizeInBits();
13487 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13488 SDValue ShOpLo = Op.getOperand(0);
13489 SDValue ShOpHi = Op.getOperand(1);
13490 SDValue ShAmt = Op.getOperand(2);
13491 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13492 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13494 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13495 DAG.getConstant(VTBits - 1, MVT::i8));
13496 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13497 DAG.getConstant(VTBits - 1, MVT::i8))
13498 : DAG.getConstant(0, VT);
13500 SDValue Tmp2, Tmp3;
13501 if (Op.getOpcode() == ISD::SHL_PARTS) {
13502 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13503 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13505 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13506 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13509 // If the shift amount is larger or equal than the width of a part we can't
13510 // rely on the results of shld/shrd. Insert a test and select the appropriate
13511 // values for large shift amounts.
13512 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13513 DAG.getConstant(VTBits, MVT::i8));
13514 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13515 AndNode, DAG.getConstant(0, MVT::i8));
13518 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13519 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13520 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13522 if (Op.getOpcode() == ISD::SHL_PARTS) {
13523 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13524 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13526 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13527 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13530 SDValue Ops[2] = { Lo, Hi };
13531 return DAG.getMergeValues(Ops, dl);
13534 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13535 SelectionDAG &DAG) const {
13536 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13539 if (SrcVT.isVector()) {
13540 if (SrcVT.getVectorElementType() == MVT::i1) {
13541 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13542 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13543 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13544 Op.getOperand(0)));
13549 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13550 "Unknown SINT_TO_FP to lower!");
13552 // These are really Legal; return the operand so the caller accepts it as
13554 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13556 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13557 Subtarget->is64Bit()) {
13561 unsigned Size = SrcVT.getSizeInBits()/8;
13562 MachineFunction &MF = DAG.getMachineFunction();
13563 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13564 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13565 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13567 MachinePointerInfo::getFixedStack(SSFI),
13569 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13572 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13574 SelectionDAG &DAG) const {
13578 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13580 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13582 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13584 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13586 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13587 MachineMemOperand *MMO;
13589 int SSFI = FI->getIndex();
13591 DAG.getMachineFunction()
13592 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13593 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13595 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13596 StackSlot = StackSlot.getOperand(1);
13598 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13599 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13601 Tys, Ops, SrcVT, MMO);
13604 Chain = Result.getValue(1);
13605 SDValue InFlag = Result.getValue(2);
13607 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13608 // shouldn't be necessary except that RFP cannot be live across
13609 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13610 MachineFunction &MF = DAG.getMachineFunction();
13611 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13612 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13613 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13614 Tys = DAG.getVTList(MVT::Other);
13616 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13618 MachineMemOperand *MMO =
13619 DAG.getMachineFunction()
13620 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13621 MachineMemOperand::MOStore, SSFISize, SSFISize);
13623 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13624 Ops, Op.getValueType(), MMO);
13625 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13626 MachinePointerInfo::getFixedStack(SSFI),
13627 false, false, false, 0);
13633 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13634 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13635 SelectionDAG &DAG) const {
13636 // This algorithm is not obvious. Here it is what we're trying to output:
13639 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13640 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13642 haddpd %xmm0, %xmm0
13644 pshufd $0x4e, %xmm0, %xmm1
13650 LLVMContext *Context = DAG.getContext();
13652 // Build some magic constants.
13653 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13654 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13655 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13657 SmallVector<Constant*,2> CV1;
13659 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13660 APInt(64, 0x4330000000000000ULL))));
13662 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13663 APInt(64, 0x4530000000000000ULL))));
13664 Constant *C1 = ConstantVector::get(CV1);
13665 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13667 // Load the 64-bit value into an XMM register.
13668 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13670 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13671 MachinePointerInfo::getConstantPool(),
13672 false, false, false, 16);
13673 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13674 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13677 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13678 MachinePointerInfo::getConstantPool(),
13679 false, false, false, 16);
13680 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13681 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13684 if (Subtarget->hasSSE3()) {
13685 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13686 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13688 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13689 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13691 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13692 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13696 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13697 DAG.getIntPtrConstant(0));
13700 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13701 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13702 SelectionDAG &DAG) const {
13704 // FP constant to bias correct the final result.
13705 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13708 // Load the 32-bit value into an XMM register.
13709 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13712 // Zero out the upper parts of the register.
13713 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13715 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13716 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13717 DAG.getIntPtrConstant(0));
13719 // Or the load with the bias.
13720 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13721 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13722 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13723 MVT::v2f64, Load)),
13724 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13725 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13726 MVT::v2f64, Bias)));
13727 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13728 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13729 DAG.getIntPtrConstant(0));
13731 // Subtract the bias.
13732 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13734 // Handle final rounding.
13735 EVT DestVT = Op.getValueType();
13737 if (DestVT.bitsLT(MVT::f64))
13738 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13739 DAG.getIntPtrConstant(0));
13740 if (DestVT.bitsGT(MVT::f64))
13741 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13743 // Handle final rounding.
13747 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13748 const X86Subtarget &Subtarget) {
13749 // The algorithm is the following:
13750 // #ifdef __SSE4_1__
13751 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13752 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13753 // (uint4) 0x53000000, 0xaa);
13755 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13756 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13758 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13759 // return (float4) lo + fhi;
13762 SDValue V = Op->getOperand(0);
13763 EVT VecIntVT = V.getValueType();
13764 bool Is128 = VecIntVT == MVT::v4i32;
13765 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13766 // If we convert to something else than the supported type, e.g., to v4f64,
13768 if (VecFloatVT != Op->getValueType(0))
13771 unsigned NumElts = VecIntVT.getVectorNumElements();
13772 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13773 "Unsupported custom type");
13774 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13776 // In the #idef/#else code, we have in common:
13777 // - The vector of constants:
13783 // Create the splat vector for 0x4b000000.
13784 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13785 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13786 CstLow, CstLow, CstLow, CstLow};
13787 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13788 makeArrayRef(&CstLowArray[0], NumElts));
13789 // Create the splat vector for 0x53000000.
13790 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13791 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13792 CstHigh, CstHigh, CstHigh, CstHigh};
13793 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13794 makeArrayRef(&CstHighArray[0], NumElts));
13796 // Create the right shift.
13797 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13798 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13799 CstShift, CstShift, CstShift, CstShift};
13800 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13801 makeArrayRef(&CstShiftArray[0], NumElts));
13802 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13805 if (Subtarget.hasSSE41()) {
13806 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13807 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13808 SDValue VecCstLowBitcast =
13809 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13810 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13811 // Low will be bitcasted right away, so do not bother bitcasting back to its
13813 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13814 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13815 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13816 // (uint4) 0x53000000, 0xaa);
13817 SDValue VecCstHighBitcast =
13818 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13819 SDValue VecShiftBitcast =
13820 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13821 // High will be bitcasted right away, so do not bother bitcasting back to
13822 // its original type.
13823 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13824 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13826 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13827 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13828 CstMask, CstMask, CstMask);
13829 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13830 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13831 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13833 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13834 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13837 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13838 SDValue CstFAdd = DAG.getConstantFP(
13839 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13840 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13841 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13842 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13843 makeArrayRef(&CstFAddArray[0], NumElts));
13845 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13846 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13848 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13849 // return (float4) lo + fhi;
13850 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13851 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13854 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13855 SelectionDAG &DAG) const {
13856 SDValue N0 = Op.getOperand(0);
13857 MVT SVT = N0.getSimpleValueType();
13860 switch (SVT.SimpleTy) {
13862 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13867 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13868 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13869 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13873 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13875 llvm_unreachable(nullptr);
13878 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13879 SelectionDAG &DAG) const {
13880 SDValue N0 = Op.getOperand(0);
13883 if (Op.getValueType().isVector())
13884 return lowerUINT_TO_FP_vec(Op, DAG);
13886 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13887 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13888 // the optimization here.
13889 if (DAG.SignBitIsZero(N0))
13890 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13892 MVT SrcVT = N0.getSimpleValueType();
13893 MVT DstVT = Op.getSimpleValueType();
13894 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13895 return LowerUINT_TO_FP_i64(Op, DAG);
13896 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13897 return LowerUINT_TO_FP_i32(Op, DAG);
13898 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13901 // Make a 64-bit buffer, and use it to build an FILD.
13902 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13903 if (SrcVT == MVT::i32) {
13904 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13905 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13906 getPointerTy(), StackSlot, WordOff);
13907 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13908 StackSlot, MachinePointerInfo(),
13910 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13911 OffsetSlot, MachinePointerInfo(),
13913 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13917 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13918 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13919 StackSlot, MachinePointerInfo(),
13921 // For i64 source, we need to add the appropriate power of 2 if the input
13922 // was negative. This is the same as the optimization in
13923 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13924 // we must be careful to do the computation in x87 extended precision, not
13925 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13926 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13927 MachineMemOperand *MMO =
13928 DAG.getMachineFunction()
13929 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13930 MachineMemOperand::MOLoad, 8, 8);
13932 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13933 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13934 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13937 APInt FF(32, 0x5F800000ULL);
13939 // Check whether the sign bit is set.
13940 SDValue SignSet = DAG.getSetCC(dl,
13941 getSetCCResultType(*DAG.getContext(), MVT::i64),
13942 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13945 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13946 SDValue FudgePtr = DAG.getConstantPool(
13947 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13950 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13951 SDValue Zero = DAG.getIntPtrConstant(0);
13952 SDValue Four = DAG.getIntPtrConstant(4);
13953 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13955 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13957 // Load the value out, extending it from f32 to f80.
13958 // FIXME: Avoid the extend by constructing the right constant pool?
13959 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13960 FudgePtr, MachinePointerInfo::getConstantPool(),
13961 MVT::f32, false, false, false, 4);
13962 // Extend everything to 80 bits to force it to be done on x87.
13963 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13964 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13967 std::pair<SDValue,SDValue>
13968 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13969 bool IsSigned, bool IsReplace) const {
13972 EVT DstTy = Op.getValueType();
13974 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13975 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13979 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13980 DstTy.getSimpleVT() >= MVT::i16 &&
13981 "Unknown FP_TO_INT to lower!");
13983 // These are really Legal.
13984 if (DstTy == MVT::i32 &&
13985 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13986 return std::make_pair(SDValue(), SDValue());
13987 if (Subtarget->is64Bit() &&
13988 DstTy == MVT::i64 &&
13989 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13990 return std::make_pair(SDValue(), SDValue());
13992 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13993 // stack slot, or into the FTOL runtime function.
13994 MachineFunction &MF = DAG.getMachineFunction();
13995 unsigned MemSize = DstTy.getSizeInBits()/8;
13996 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13997 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14000 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14001 Opc = X86ISD::WIN_FTOL;
14003 switch (DstTy.getSimpleVT().SimpleTy) {
14004 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14005 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14006 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14007 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14010 SDValue Chain = DAG.getEntryNode();
14011 SDValue Value = Op.getOperand(0);
14012 EVT TheVT = Op.getOperand(0).getValueType();
14013 // FIXME This causes a redundant load/store if the SSE-class value is already
14014 // in memory, such as if it is on the callstack.
14015 if (isScalarFPTypeInSSEReg(TheVT)) {
14016 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14017 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14018 MachinePointerInfo::getFixedStack(SSFI),
14020 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14022 Chain, StackSlot, DAG.getValueType(TheVT)
14025 MachineMemOperand *MMO =
14026 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14027 MachineMemOperand::MOLoad, MemSize, MemSize);
14028 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14029 Chain = Value.getValue(1);
14030 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14031 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14034 MachineMemOperand *MMO =
14035 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14036 MachineMemOperand::MOStore, MemSize, MemSize);
14038 if (Opc != X86ISD::WIN_FTOL) {
14039 // Build the FP_TO_INT*_IN_MEM
14040 SDValue Ops[] = { Chain, Value, StackSlot };
14041 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14043 return std::make_pair(FIST, StackSlot);
14045 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14046 DAG.getVTList(MVT::Other, MVT::Glue),
14048 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14049 MVT::i32, ftol.getValue(1));
14050 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14051 MVT::i32, eax.getValue(2));
14052 SDValue Ops[] = { eax, edx };
14053 SDValue pair = IsReplace
14054 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14055 : DAG.getMergeValues(Ops, DL);
14056 return std::make_pair(pair, SDValue());
14060 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14061 const X86Subtarget *Subtarget) {
14062 MVT VT = Op->getSimpleValueType(0);
14063 SDValue In = Op->getOperand(0);
14064 MVT InVT = In.getSimpleValueType();
14067 // Optimize vectors in AVX mode:
14070 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14071 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14072 // Concat upper and lower parts.
14075 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14076 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14077 // Concat upper and lower parts.
14080 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14081 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14082 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14085 if (Subtarget->hasInt256())
14086 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14088 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14089 SDValue Undef = DAG.getUNDEF(InVT);
14090 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14091 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14092 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14094 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14095 VT.getVectorNumElements()/2);
14097 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14098 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14100 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14103 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14104 SelectionDAG &DAG) {
14105 MVT VT = Op->getSimpleValueType(0);
14106 SDValue In = Op->getOperand(0);
14107 MVT InVT = In.getSimpleValueType();
14109 unsigned int NumElts = VT.getVectorNumElements();
14110 if (NumElts != 8 && NumElts != 16)
14113 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14114 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14116 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14118 // Now we have only mask extension
14119 assert(InVT.getVectorElementType() == MVT::i1);
14120 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14121 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14122 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14123 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14124 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14125 MachinePointerInfo::getConstantPool(),
14126 false, false, false, Alignment);
14128 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14129 if (VT.is512BitVector())
14131 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14134 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14135 SelectionDAG &DAG) {
14136 if (Subtarget->hasFp256()) {
14137 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14145 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14146 SelectionDAG &DAG) {
14148 MVT VT = Op.getSimpleValueType();
14149 SDValue In = Op.getOperand(0);
14150 MVT SVT = In.getSimpleValueType();
14152 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14153 return LowerZERO_EXTEND_AVX512(Op, DAG);
14155 if (Subtarget->hasFp256()) {
14156 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14161 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14162 VT.getVectorNumElements() != SVT.getVectorNumElements());
14166 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14168 MVT VT = Op.getSimpleValueType();
14169 SDValue In = Op.getOperand(0);
14170 MVT InVT = In.getSimpleValueType();
14172 if (VT == MVT::i1) {
14173 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14174 "Invalid scalar TRUNCATE operation");
14175 if (InVT.getSizeInBits() >= 32)
14177 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14178 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14180 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14181 "Invalid TRUNCATE operation");
14183 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14184 if (VT.getVectorElementType().getSizeInBits() >=8)
14185 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14187 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14188 unsigned NumElts = InVT.getVectorNumElements();
14189 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14190 if (InVT.getSizeInBits() < 512) {
14191 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14192 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14196 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14197 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14198 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14199 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14200 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14201 MachinePointerInfo::getConstantPool(),
14202 false, false, false, Alignment);
14203 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14204 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14205 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14208 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14209 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14210 if (Subtarget->hasInt256()) {
14211 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14212 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14213 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14215 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14216 DAG.getIntPtrConstant(0));
14219 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14220 DAG.getIntPtrConstant(0));
14221 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14222 DAG.getIntPtrConstant(2));
14223 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14224 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14225 static const int ShufMask[] = {0, 2, 4, 6};
14226 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14229 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14230 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14231 if (Subtarget->hasInt256()) {
14232 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14234 SmallVector<SDValue,32> pshufbMask;
14235 for (unsigned i = 0; i < 2; ++i) {
14236 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14237 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14238 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14239 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14240 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14241 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14242 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14243 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14244 for (unsigned j = 0; j < 8; ++j)
14245 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14247 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14248 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14249 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14251 static const int ShufMask[] = {0, 2, -1, -1};
14252 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14254 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14255 DAG.getIntPtrConstant(0));
14256 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14259 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14260 DAG.getIntPtrConstant(0));
14262 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14263 DAG.getIntPtrConstant(4));
14265 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14266 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14268 // The PSHUFB mask:
14269 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14270 -1, -1, -1, -1, -1, -1, -1, -1};
14272 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14273 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14274 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14276 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14277 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14279 // The MOVLHPS Mask:
14280 static const int ShufMask2[] = {0, 1, 4, 5};
14281 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14282 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14285 // Handle truncation of V256 to V128 using shuffles.
14286 if (!VT.is128BitVector() || !InVT.is256BitVector())
14289 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14291 unsigned NumElems = VT.getVectorNumElements();
14292 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14294 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14295 // Prepare truncation shuffle mask
14296 for (unsigned i = 0; i != NumElems; ++i)
14297 MaskVec[i] = i * 2;
14298 SDValue V = DAG.getVectorShuffle(NVT, DL,
14299 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14300 DAG.getUNDEF(NVT), &MaskVec[0]);
14301 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14302 DAG.getIntPtrConstant(0));
14305 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14306 SelectionDAG &DAG) const {
14307 assert(!Op.getSimpleValueType().isVector());
14309 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14310 /*IsSigned=*/ true, /*IsReplace=*/ false);
14311 SDValue FIST = Vals.first, StackSlot = Vals.second;
14312 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14313 if (!FIST.getNode()) return Op;
14315 if (StackSlot.getNode())
14316 // Load the result.
14317 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14318 FIST, StackSlot, MachinePointerInfo(),
14319 false, false, false, 0);
14321 // The node is the result.
14325 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14326 SelectionDAG &DAG) const {
14327 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14328 /*IsSigned=*/ false, /*IsReplace=*/ false);
14329 SDValue FIST = Vals.first, StackSlot = Vals.second;
14330 assert(FIST.getNode() && "Unexpected failure");
14332 if (StackSlot.getNode())
14333 // Load the result.
14334 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14335 FIST, StackSlot, MachinePointerInfo(),
14336 false, false, false, 0);
14338 // The node is the result.
14342 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14344 MVT VT = Op.getSimpleValueType();
14345 SDValue In = Op.getOperand(0);
14346 MVT SVT = In.getSimpleValueType();
14348 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14350 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14351 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14352 In, DAG.getUNDEF(SVT)));
14355 /// The only differences between FABS and FNEG are the mask and the logic op.
14356 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14357 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14358 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14359 "Wrong opcode for lowering FABS or FNEG.");
14361 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14363 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14364 // into an FNABS. We'll lower the FABS after that if it is still in use.
14366 for (SDNode *User : Op->uses())
14367 if (User->getOpcode() == ISD::FNEG)
14370 SDValue Op0 = Op.getOperand(0);
14371 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14374 MVT VT = Op.getSimpleValueType();
14375 // Assume scalar op for initialization; update for vector if needed.
14376 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14377 // generate a 16-byte vector constant and logic op even for the scalar case.
14378 // Using a 16-byte mask allows folding the load of the mask with
14379 // the logic op, so it can save (~4 bytes) on code size.
14381 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14382 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14383 // decide if we should generate a 16-byte constant mask when we only need 4 or
14384 // 8 bytes for the scalar case.
14385 if (VT.isVector()) {
14386 EltVT = VT.getVectorElementType();
14387 NumElts = VT.getVectorNumElements();
14390 unsigned EltBits = EltVT.getSizeInBits();
14391 LLVMContext *Context = DAG.getContext();
14392 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14394 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14395 Constant *C = ConstantInt::get(*Context, MaskElt);
14396 C = ConstantVector::getSplat(NumElts, C);
14397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14398 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14399 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14400 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14401 MachinePointerInfo::getConstantPool(),
14402 false, false, false, Alignment);
14404 if (VT.isVector()) {
14405 // For a vector, cast operands to a vector type, perform the logic op,
14406 // and cast the result back to the original value type.
14407 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14408 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14409 SDValue Operand = IsFNABS ?
14410 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14411 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14412 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14413 return DAG.getNode(ISD::BITCAST, dl, VT,
14414 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14417 // If not vector, then scalar.
14418 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14419 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14420 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14423 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14425 LLVMContext *Context = DAG.getContext();
14426 SDValue Op0 = Op.getOperand(0);
14427 SDValue Op1 = Op.getOperand(1);
14429 MVT VT = Op.getSimpleValueType();
14430 MVT SrcVT = Op1.getSimpleValueType();
14432 // If second operand is smaller, extend it first.
14433 if (SrcVT.bitsLT(VT)) {
14434 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14437 // And if it is bigger, shrink it first.
14438 if (SrcVT.bitsGT(VT)) {
14439 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14443 // At this point the operands and the result should have the same
14444 // type, and that won't be f80 since that is not custom lowered.
14446 // First get the sign bit of second operand.
14447 SmallVector<Constant*,4> CV;
14448 if (SrcVT == MVT::f64) {
14449 const fltSemantics &Sem = APFloat::IEEEdouble;
14450 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14451 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14453 const fltSemantics &Sem = APFloat::IEEEsingle;
14454 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14455 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14456 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14457 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14459 Constant *C = ConstantVector::get(CV);
14460 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14461 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14462 MachinePointerInfo::getConstantPool(),
14463 false, false, false, 16);
14464 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14466 // Shift sign bit right or left if the two operands have different types.
14467 if (SrcVT.bitsGT(VT)) {
14468 // Op0 is MVT::f32, Op1 is MVT::f64.
14469 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14470 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14471 DAG.getConstant(32, MVT::i32));
14472 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14473 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14474 DAG.getIntPtrConstant(0));
14477 // Clear first operand sign bit.
14479 if (VT == MVT::f64) {
14480 const fltSemantics &Sem = APFloat::IEEEdouble;
14481 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14482 APInt(64, ~(1ULL << 63)))));
14483 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14485 const fltSemantics &Sem = APFloat::IEEEsingle;
14486 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14487 APInt(32, ~(1U << 31)))));
14488 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14489 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14490 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14492 C = ConstantVector::get(CV);
14493 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14494 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14495 MachinePointerInfo::getConstantPool(),
14496 false, false, false, 16);
14497 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14499 // Or the value with the sign bit.
14500 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14503 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14504 SDValue N0 = Op.getOperand(0);
14506 MVT VT = Op.getSimpleValueType();
14508 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14509 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14510 DAG.getConstant(1, VT));
14511 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14514 // Check whether an OR'd tree is PTEST-able.
14515 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14516 SelectionDAG &DAG) {
14517 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14519 if (!Subtarget->hasSSE41())
14522 if (!Op->hasOneUse())
14525 SDNode *N = Op.getNode();
14528 SmallVector<SDValue, 8> Opnds;
14529 DenseMap<SDValue, unsigned> VecInMap;
14530 SmallVector<SDValue, 8> VecIns;
14531 EVT VT = MVT::Other;
14533 // Recognize a special case where a vector is casted into wide integer to
14535 Opnds.push_back(N->getOperand(0));
14536 Opnds.push_back(N->getOperand(1));
14538 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14539 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14540 // BFS traverse all OR'd operands.
14541 if (I->getOpcode() == ISD::OR) {
14542 Opnds.push_back(I->getOperand(0));
14543 Opnds.push_back(I->getOperand(1));
14544 // Re-evaluate the number of nodes to be traversed.
14545 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14549 // Quit if a non-EXTRACT_VECTOR_ELT
14550 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14553 // Quit if without a constant index.
14554 SDValue Idx = I->getOperand(1);
14555 if (!isa<ConstantSDNode>(Idx))
14558 SDValue ExtractedFromVec = I->getOperand(0);
14559 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14560 if (M == VecInMap.end()) {
14561 VT = ExtractedFromVec.getValueType();
14562 // Quit if not 128/256-bit vector.
14563 if (!VT.is128BitVector() && !VT.is256BitVector())
14565 // Quit if not the same type.
14566 if (VecInMap.begin() != VecInMap.end() &&
14567 VT != VecInMap.begin()->first.getValueType())
14569 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14570 VecIns.push_back(ExtractedFromVec);
14572 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14575 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14576 "Not extracted from 128-/256-bit vector.");
14578 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14580 for (DenseMap<SDValue, unsigned>::const_iterator
14581 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14582 // Quit if not all elements are used.
14583 if (I->second != FullMask)
14587 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14589 // Cast all vectors into TestVT for PTEST.
14590 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14591 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14593 // If more than one full vectors are evaluated, OR them first before PTEST.
14594 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14595 // Each iteration will OR 2 nodes and append the result until there is only
14596 // 1 node left, i.e. the final OR'd value of all vectors.
14597 SDValue LHS = VecIns[Slot];
14598 SDValue RHS = VecIns[Slot + 1];
14599 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14602 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14603 VecIns.back(), VecIns.back());
14606 /// \brief return true if \c Op has a use that doesn't just read flags.
14607 static bool hasNonFlagsUse(SDValue Op) {
14608 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14610 SDNode *User = *UI;
14611 unsigned UOpNo = UI.getOperandNo();
14612 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14613 // Look pass truncate.
14614 UOpNo = User->use_begin().getOperandNo();
14615 User = *User->use_begin();
14618 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14619 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14625 /// Emit nodes that will be selected as "test Op0,Op0", or something
14627 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14628 SelectionDAG &DAG) const {
14629 if (Op.getValueType() == MVT::i1)
14630 // KORTEST instruction should be selected
14631 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14632 DAG.getConstant(0, Op.getValueType()));
14634 // CF and OF aren't always set the way we want. Determine which
14635 // of these we need.
14636 bool NeedCF = false;
14637 bool NeedOF = false;
14640 case X86::COND_A: case X86::COND_AE:
14641 case X86::COND_B: case X86::COND_BE:
14644 case X86::COND_G: case X86::COND_GE:
14645 case X86::COND_L: case X86::COND_LE:
14646 case X86::COND_O: case X86::COND_NO: {
14647 // Check if we really need to set the
14648 // Overflow flag. If NoSignedWrap is present
14649 // that is not actually needed.
14650 switch (Op->getOpcode()) {
14655 const BinaryWithFlagsSDNode *BinNode =
14656 cast<BinaryWithFlagsSDNode>(Op.getNode());
14657 if (BinNode->hasNoSignedWrap())
14667 // See if we can use the EFLAGS value from the operand instead of
14668 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14669 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14670 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14671 // Emit a CMP with 0, which is the TEST pattern.
14672 //if (Op.getValueType() == MVT::i1)
14673 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14674 // DAG.getConstant(0, MVT::i1));
14675 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14676 DAG.getConstant(0, Op.getValueType()));
14678 unsigned Opcode = 0;
14679 unsigned NumOperands = 0;
14681 // Truncate operations may prevent the merge of the SETCC instruction
14682 // and the arithmetic instruction before it. Attempt to truncate the operands
14683 // of the arithmetic instruction and use a reduced bit-width instruction.
14684 bool NeedTruncation = false;
14685 SDValue ArithOp = Op;
14686 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14687 SDValue Arith = Op->getOperand(0);
14688 // Both the trunc and the arithmetic op need to have one user each.
14689 if (Arith->hasOneUse())
14690 switch (Arith.getOpcode()) {
14697 NeedTruncation = true;
14703 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14704 // which may be the result of a CAST. We use the variable 'Op', which is the
14705 // non-casted variable when we check for possible users.
14706 switch (ArithOp.getOpcode()) {
14708 // Due to an isel shortcoming, be conservative if this add is likely to be
14709 // selected as part of a load-modify-store instruction. When the root node
14710 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14711 // uses of other nodes in the match, such as the ADD in this case. This
14712 // leads to the ADD being left around and reselected, with the result being
14713 // two adds in the output. Alas, even if none our users are stores, that
14714 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14715 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14716 // climbing the DAG back to the root, and it doesn't seem to be worth the
14718 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14719 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14720 if (UI->getOpcode() != ISD::CopyToReg &&
14721 UI->getOpcode() != ISD::SETCC &&
14722 UI->getOpcode() != ISD::STORE)
14725 if (ConstantSDNode *C =
14726 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14727 // An add of one will be selected as an INC.
14728 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14729 Opcode = X86ISD::INC;
14734 // An add of negative one (subtract of one) will be selected as a DEC.
14735 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14736 Opcode = X86ISD::DEC;
14742 // Otherwise use a regular EFLAGS-setting add.
14743 Opcode = X86ISD::ADD;
14748 // If we have a constant logical shift that's only used in a comparison
14749 // against zero turn it into an equivalent AND. This allows turning it into
14750 // a TEST instruction later.
14751 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14752 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14753 EVT VT = Op.getValueType();
14754 unsigned BitWidth = VT.getSizeInBits();
14755 unsigned ShAmt = Op->getConstantOperandVal(1);
14756 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14758 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14759 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14760 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14761 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14763 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14764 DAG.getConstant(Mask, VT));
14765 DAG.ReplaceAllUsesWith(Op, New);
14771 // If the primary and result isn't used, don't bother using X86ISD::AND,
14772 // because a TEST instruction will be better.
14773 if (!hasNonFlagsUse(Op))
14779 // Due to the ISEL shortcoming noted above, be conservative if this op is
14780 // likely to be selected as part of a load-modify-store instruction.
14781 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14782 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14783 if (UI->getOpcode() == ISD::STORE)
14786 // Otherwise use a regular EFLAGS-setting instruction.
14787 switch (ArithOp.getOpcode()) {
14788 default: llvm_unreachable("unexpected operator!");
14789 case ISD::SUB: Opcode = X86ISD::SUB; break;
14790 case ISD::XOR: Opcode = X86ISD::XOR; break;
14791 case ISD::AND: Opcode = X86ISD::AND; break;
14793 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14794 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14795 if (EFLAGS.getNode())
14798 Opcode = X86ISD::OR;
14812 return SDValue(Op.getNode(), 1);
14818 // If we found that truncation is beneficial, perform the truncation and
14820 if (NeedTruncation) {
14821 EVT VT = Op.getValueType();
14822 SDValue WideVal = Op->getOperand(0);
14823 EVT WideVT = WideVal.getValueType();
14824 unsigned ConvertedOp = 0;
14825 // Use a target machine opcode to prevent further DAGCombine
14826 // optimizations that may separate the arithmetic operations
14827 // from the setcc node.
14828 switch (WideVal.getOpcode()) {
14830 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14831 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14832 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14833 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14834 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14838 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14839 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14840 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14841 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14842 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14848 // Emit a CMP with 0, which is the TEST pattern.
14849 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14850 DAG.getConstant(0, Op.getValueType()));
14852 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14853 SmallVector<SDValue, 4> Ops;
14854 for (unsigned i = 0; i != NumOperands; ++i)
14855 Ops.push_back(Op.getOperand(i));
14857 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14858 DAG.ReplaceAllUsesWith(Op, New);
14859 return SDValue(New.getNode(), 1);
14862 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14864 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14865 SDLoc dl, SelectionDAG &DAG) const {
14866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14867 if (C->getAPIntValue() == 0)
14868 return EmitTest(Op0, X86CC, dl, DAG);
14870 if (Op0.getValueType() == MVT::i1)
14871 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14874 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14875 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14876 // Do the comparison at i32 if it's smaller, besides the Atom case.
14877 // This avoids subregister aliasing issues. Keep the smaller reference
14878 // if we're optimizing for size, however, as that'll allow better folding
14879 // of memory operations.
14880 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14881 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14882 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14883 !Subtarget->isAtom()) {
14884 unsigned ExtendOp =
14885 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14886 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14887 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14889 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14890 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14891 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14893 return SDValue(Sub.getNode(), 1);
14895 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14898 /// Convert a comparison if required by the subtarget.
14899 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14900 SelectionDAG &DAG) const {
14901 // If the subtarget does not support the FUCOMI instruction, floating-point
14902 // comparisons have to be converted.
14903 if (Subtarget->hasCMov() ||
14904 Cmp.getOpcode() != X86ISD::CMP ||
14905 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14906 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14909 // The instruction selector will select an FUCOM instruction instead of
14910 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14911 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14912 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14914 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14915 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14916 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14917 DAG.getConstant(8, MVT::i8));
14918 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14919 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14922 /// The minimum architected relative accuracy is 2^-12. We need one
14923 /// Newton-Raphson step to have a good float result (24 bits of precision).
14924 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14925 DAGCombinerInfo &DCI,
14926 unsigned &RefinementSteps,
14927 bool &UseOneConstNR) const {
14928 // FIXME: We should use instruction latency models to calculate the cost of
14929 // each potential sequence, but this is very hard to do reliably because
14930 // at least Intel's Core* chips have variable timing based on the number of
14931 // significant digits in the divisor and/or sqrt operand.
14932 if (!Subtarget->useSqrtEst())
14935 EVT VT = Op.getValueType();
14937 // SSE1 has rsqrtss and rsqrtps.
14938 // TODO: Add support for AVX512 (v16f32).
14939 // It is likely not profitable to do this for f64 because a double-precision
14940 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14941 // instructions: convert to single, rsqrtss, convert back to double, refine
14942 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14943 // along with FMA, this could be a throughput win.
14944 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14945 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14946 RefinementSteps = 1;
14947 UseOneConstNR = false;
14948 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14953 /// The minimum architected relative accuracy is 2^-12. We need one
14954 /// Newton-Raphson step to have a good float result (24 bits of precision).
14955 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14956 DAGCombinerInfo &DCI,
14957 unsigned &RefinementSteps) const {
14958 // FIXME: We should use instruction latency models to calculate the cost of
14959 // each potential sequence, but this is very hard to do reliably because
14960 // at least Intel's Core* chips have variable timing based on the number of
14961 // significant digits in the divisor.
14962 if (!Subtarget->useReciprocalEst())
14965 EVT VT = Op.getValueType();
14967 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14968 // TODO: Add support for AVX512 (v16f32).
14969 // It is likely not profitable to do this for f64 because a double-precision
14970 // reciprocal estimate with refinement on x86 prior to FMA requires
14971 // 15 instructions: convert to single, rcpss, convert back to double, refine
14972 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14973 // along with FMA, this could be a throughput win.
14974 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14975 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14976 RefinementSteps = ReciprocalEstimateRefinementSteps;
14977 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14982 static bool isAllOnes(SDValue V) {
14983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14984 return C && C->isAllOnesValue();
14987 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14988 /// if it's possible.
14989 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14990 SDLoc dl, SelectionDAG &DAG) const {
14991 SDValue Op0 = And.getOperand(0);
14992 SDValue Op1 = And.getOperand(1);
14993 if (Op0.getOpcode() == ISD::TRUNCATE)
14994 Op0 = Op0.getOperand(0);
14995 if (Op1.getOpcode() == ISD::TRUNCATE)
14996 Op1 = Op1.getOperand(0);
14999 if (Op1.getOpcode() == ISD::SHL)
15000 std::swap(Op0, Op1);
15001 if (Op0.getOpcode() == ISD::SHL) {
15002 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15003 if (And00C->getZExtValue() == 1) {
15004 // If we looked past a truncate, check that it's only truncating away
15006 unsigned BitWidth = Op0.getValueSizeInBits();
15007 unsigned AndBitWidth = And.getValueSizeInBits();
15008 if (BitWidth > AndBitWidth) {
15010 DAG.computeKnownBits(Op0, Zeros, Ones);
15011 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15015 RHS = Op0.getOperand(1);
15017 } else if (Op1.getOpcode() == ISD::Constant) {
15018 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15019 uint64_t AndRHSVal = AndRHS->getZExtValue();
15020 SDValue AndLHS = Op0;
15022 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15023 LHS = AndLHS.getOperand(0);
15024 RHS = AndLHS.getOperand(1);
15027 // Use BT if the immediate can't be encoded in a TEST instruction.
15028 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15030 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15034 if (LHS.getNode()) {
15035 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15036 // instruction. Since the shift amount is in-range-or-undefined, we know
15037 // that doing a bittest on the i32 value is ok. We extend to i32 because
15038 // the encoding for the i16 version is larger than the i32 version.
15039 // Also promote i16 to i32 for performance / code size reason.
15040 if (LHS.getValueType() == MVT::i8 ||
15041 LHS.getValueType() == MVT::i16)
15042 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15044 // If the operand types disagree, extend the shift amount to match. Since
15045 // BT ignores high bits (like shifts) we can use anyextend.
15046 if (LHS.getValueType() != RHS.getValueType())
15047 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15049 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15050 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15051 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15052 DAG.getConstant(Cond, MVT::i8), BT);
15058 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15060 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15065 // SSE Condition code mapping:
15074 switch (SetCCOpcode) {
15075 default: llvm_unreachable("Unexpected SETCC condition");
15077 case ISD::SETEQ: SSECC = 0; break;
15079 case ISD::SETGT: Swap = true; // Fallthrough
15081 case ISD::SETOLT: SSECC = 1; break;
15083 case ISD::SETGE: Swap = true; // Fallthrough
15085 case ISD::SETOLE: SSECC = 2; break;
15086 case ISD::SETUO: SSECC = 3; break;
15088 case ISD::SETNE: SSECC = 4; break;
15089 case ISD::SETULE: Swap = true; // Fallthrough
15090 case ISD::SETUGE: SSECC = 5; break;
15091 case ISD::SETULT: Swap = true; // Fallthrough
15092 case ISD::SETUGT: SSECC = 6; break;
15093 case ISD::SETO: SSECC = 7; break;
15095 case ISD::SETONE: SSECC = 8; break;
15098 std::swap(Op0, Op1);
15103 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15104 // ones, and then concatenate the result back.
15105 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15106 MVT VT = Op.getSimpleValueType();
15108 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15109 "Unsupported value type for operation");
15111 unsigned NumElems = VT.getVectorNumElements();
15113 SDValue CC = Op.getOperand(2);
15115 // Extract the LHS vectors
15116 SDValue LHS = Op.getOperand(0);
15117 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15118 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15120 // Extract the RHS vectors
15121 SDValue RHS = Op.getOperand(1);
15122 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15123 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15125 // Issue the operation on the smaller types and concatenate the result back
15126 MVT EltVT = VT.getVectorElementType();
15127 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15128 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15129 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15130 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15133 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15134 const X86Subtarget *Subtarget) {
15135 SDValue Op0 = Op.getOperand(0);
15136 SDValue Op1 = Op.getOperand(1);
15137 SDValue CC = Op.getOperand(2);
15138 MVT VT = Op.getSimpleValueType();
15141 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15142 Op.getValueType().getScalarType() == MVT::i1 &&
15143 "Cannot set masked compare for this operation");
15145 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15147 bool Unsigned = false;
15150 switch (SetCCOpcode) {
15151 default: llvm_unreachable("Unexpected SETCC condition");
15152 case ISD::SETNE: SSECC = 4; break;
15153 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15154 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15155 case ISD::SETLT: Swap = true; //fall-through
15156 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15157 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15158 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15159 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15160 case ISD::SETULE: Unsigned = true; //fall-through
15161 case ISD::SETLE: SSECC = 2; break;
15165 std::swap(Op0, Op1);
15167 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15168 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15169 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15170 DAG.getConstant(SSECC, MVT::i8));
15173 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15174 /// operand \p Op1. If non-trivial (for example because it's not constant)
15175 /// return an empty value.
15176 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15178 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15182 MVT VT = Op1.getSimpleValueType();
15183 MVT EVT = VT.getVectorElementType();
15184 unsigned n = VT.getVectorNumElements();
15185 SmallVector<SDValue, 8> ULTOp1;
15187 for (unsigned i = 0; i < n; ++i) {
15188 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15189 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15192 // Avoid underflow.
15193 APInt Val = Elt->getAPIntValue();
15197 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15200 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15203 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15204 SelectionDAG &DAG) {
15205 SDValue Op0 = Op.getOperand(0);
15206 SDValue Op1 = Op.getOperand(1);
15207 SDValue CC = Op.getOperand(2);
15208 MVT VT = Op.getSimpleValueType();
15209 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15210 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15215 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15216 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15219 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15220 unsigned Opc = X86ISD::CMPP;
15221 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15222 assert(VT.getVectorNumElements() <= 16);
15223 Opc = X86ISD::CMPM;
15225 // In the two special cases we can't handle, emit two comparisons.
15228 unsigned CombineOpc;
15229 if (SetCCOpcode == ISD::SETUEQ) {
15230 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15232 assert(SetCCOpcode == ISD::SETONE);
15233 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15236 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15237 DAG.getConstant(CC0, MVT::i8));
15238 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15239 DAG.getConstant(CC1, MVT::i8));
15240 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15242 // Handle all other FP comparisons here.
15243 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15244 DAG.getConstant(SSECC, MVT::i8));
15247 // Break 256-bit integer vector compare into smaller ones.
15248 if (VT.is256BitVector() && !Subtarget->hasInt256())
15249 return Lower256IntVSETCC(Op, DAG);
15251 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15252 EVT OpVT = Op1.getValueType();
15253 if (Subtarget->hasAVX512()) {
15254 if (Op1.getValueType().is512BitVector() ||
15255 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15256 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15257 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15259 // In AVX-512 architecture setcc returns mask with i1 elements,
15260 // But there is no compare instruction for i8 and i16 elements in KNL.
15261 // We are not talking about 512-bit operands in this case, these
15262 // types are illegal.
15264 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15265 OpVT.getVectorElementType().getSizeInBits() >= 8))
15266 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15267 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15270 // We are handling one of the integer comparisons here. Since SSE only has
15271 // GT and EQ comparisons for integer, swapping operands and multiple
15272 // operations may be required for some comparisons.
15274 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15275 bool Subus = false;
15277 switch (SetCCOpcode) {
15278 default: llvm_unreachable("Unexpected SETCC condition");
15279 case ISD::SETNE: Invert = true;
15280 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15281 case ISD::SETLT: Swap = true;
15282 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15283 case ISD::SETGE: Swap = true;
15284 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15285 Invert = true; break;
15286 case ISD::SETULT: Swap = true;
15287 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15288 FlipSigns = true; break;
15289 case ISD::SETUGE: Swap = true;
15290 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15291 FlipSigns = true; Invert = true; break;
15294 // Special case: Use min/max operations for SETULE/SETUGE
15295 MVT VET = VT.getVectorElementType();
15297 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15298 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15301 switch (SetCCOpcode) {
15303 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15304 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15307 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15310 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15311 if (!MinMax && hasSubus) {
15312 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15314 // t = psubus Op0, Op1
15315 // pcmpeq t, <0..0>
15316 switch (SetCCOpcode) {
15318 case ISD::SETULT: {
15319 // If the comparison is against a constant we can turn this into a
15320 // setule. With psubus, setule does not require a swap. This is
15321 // beneficial because the constant in the register is no longer
15322 // destructed as the destination so it can be hoisted out of a loop.
15323 // Only do this pre-AVX since vpcmp* is no longer destructive.
15324 if (Subtarget->hasAVX())
15326 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15327 if (ULEOp1.getNode()) {
15329 Subus = true; Invert = false; Swap = false;
15333 // Psubus is better than flip-sign because it requires no inversion.
15334 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15335 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15339 Opc = X86ISD::SUBUS;
15345 std::swap(Op0, Op1);
15347 // Check that the operation in question is available (most are plain SSE2,
15348 // but PCMPGTQ and PCMPEQQ have different requirements).
15349 if (VT == MVT::v2i64) {
15350 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15351 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15353 // First cast everything to the right type.
15354 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15355 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15357 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15358 // bits of the inputs before performing those operations. The lower
15359 // compare is always unsigned.
15362 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15364 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15365 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15366 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15367 Sign, Zero, Sign, Zero);
15369 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15370 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15372 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15373 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15374 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15376 // Create masks for only the low parts/high parts of the 64 bit integers.
15377 static const int MaskHi[] = { 1, 1, 3, 3 };
15378 static const int MaskLo[] = { 0, 0, 2, 2 };
15379 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15380 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15381 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15383 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15384 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15387 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15389 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15392 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15393 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15394 // pcmpeqd + pshufd + pand.
15395 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15397 // First cast everything to the right type.
15398 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15399 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15402 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15404 // Make sure the lower and upper halves are both all-ones.
15405 static const int Mask[] = { 1, 0, 3, 2 };
15406 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15407 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15410 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15412 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15416 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15417 // bits of the inputs before performing those operations.
15419 EVT EltVT = VT.getVectorElementType();
15420 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15421 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15422 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15425 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15427 // If the logical-not of the result is required, perform that now.
15429 Result = DAG.getNOT(dl, Result, VT);
15432 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15435 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15436 getZeroVector(VT, Subtarget, DAG, dl));
15441 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15443 MVT VT = Op.getSimpleValueType();
15445 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15447 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15448 && "SetCC type must be 8-bit or 1-bit integer");
15449 SDValue Op0 = Op.getOperand(0);
15450 SDValue Op1 = Op.getOperand(1);
15452 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15454 // Optimize to BT if possible.
15455 // Lower (X & (1 << N)) == 0 to BT(X, N).
15456 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15457 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15458 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15459 Op1.getOpcode() == ISD::Constant &&
15460 cast<ConstantSDNode>(Op1)->isNullValue() &&
15461 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15462 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15463 if (NewSetCC.getNode())
15467 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15469 if (Op1.getOpcode() == ISD::Constant &&
15470 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15471 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15472 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15474 // If the input is a setcc, then reuse the input setcc or use a new one with
15475 // the inverted condition.
15476 if (Op0.getOpcode() == X86ISD::SETCC) {
15477 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15478 bool Invert = (CC == ISD::SETNE) ^
15479 cast<ConstantSDNode>(Op1)->isNullValue();
15483 CCode = X86::GetOppositeBranchCondition(CCode);
15484 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15485 DAG.getConstant(CCode, MVT::i8),
15486 Op0.getOperand(1));
15488 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15492 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15493 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15494 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15496 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15497 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15500 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15501 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15502 if (X86CC == X86::COND_INVALID)
15505 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15506 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15507 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15508 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15510 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15514 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15515 static bool isX86LogicalCmp(SDValue Op) {
15516 unsigned Opc = Op.getNode()->getOpcode();
15517 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15518 Opc == X86ISD::SAHF)
15520 if (Op.getResNo() == 1 &&
15521 (Opc == X86ISD::ADD ||
15522 Opc == X86ISD::SUB ||
15523 Opc == X86ISD::ADC ||
15524 Opc == X86ISD::SBB ||
15525 Opc == X86ISD::SMUL ||
15526 Opc == X86ISD::UMUL ||
15527 Opc == X86ISD::INC ||
15528 Opc == X86ISD::DEC ||
15529 Opc == X86ISD::OR ||
15530 Opc == X86ISD::XOR ||
15531 Opc == X86ISD::AND))
15534 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15540 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15541 if (V.getOpcode() != ISD::TRUNCATE)
15544 SDValue VOp0 = V.getOperand(0);
15545 unsigned InBits = VOp0.getValueSizeInBits();
15546 unsigned Bits = V.getValueSizeInBits();
15547 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15550 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15551 bool addTest = true;
15552 SDValue Cond = Op.getOperand(0);
15553 SDValue Op1 = Op.getOperand(1);
15554 SDValue Op2 = Op.getOperand(2);
15556 EVT VT = Op1.getValueType();
15559 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15560 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15561 // sequence later on.
15562 if (Cond.getOpcode() == ISD::SETCC &&
15563 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15564 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15565 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15566 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15567 int SSECC = translateX86FSETCC(
15568 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15571 if (Subtarget->hasAVX512()) {
15572 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15573 DAG.getConstant(SSECC, MVT::i8));
15574 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15576 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15577 DAG.getConstant(SSECC, MVT::i8));
15578 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15579 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15580 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15584 if (Cond.getOpcode() == ISD::SETCC) {
15585 SDValue NewCond = LowerSETCC(Cond, DAG);
15586 if (NewCond.getNode())
15590 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15591 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15592 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15593 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15594 if (Cond.getOpcode() == X86ISD::SETCC &&
15595 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15596 isZero(Cond.getOperand(1).getOperand(1))) {
15597 SDValue Cmp = Cond.getOperand(1);
15599 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15601 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15602 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15603 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15605 SDValue CmpOp0 = Cmp.getOperand(0);
15606 // Apply further optimizations for special cases
15607 // (select (x != 0), -1, 0) -> neg & sbb
15608 // (select (x == 0), 0, -1) -> neg & sbb
15609 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15610 if (YC->isNullValue() &&
15611 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15612 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15613 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15614 DAG.getConstant(0, CmpOp0.getValueType()),
15616 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15617 DAG.getConstant(X86::COND_B, MVT::i8),
15618 SDValue(Neg.getNode(), 1));
15622 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15623 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15624 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15626 SDValue Res = // Res = 0 or -1.
15627 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15628 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15630 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15631 Res = DAG.getNOT(DL, Res, Res.getValueType());
15633 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15634 if (!N2C || !N2C->isNullValue())
15635 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15640 // Look past (and (setcc_carry (cmp ...)), 1).
15641 if (Cond.getOpcode() == ISD::AND &&
15642 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15643 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15644 if (C && C->getAPIntValue() == 1)
15645 Cond = Cond.getOperand(0);
15648 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15649 // setting operand in place of the X86ISD::SETCC.
15650 unsigned CondOpcode = Cond.getOpcode();
15651 if (CondOpcode == X86ISD::SETCC ||
15652 CondOpcode == X86ISD::SETCC_CARRY) {
15653 CC = Cond.getOperand(0);
15655 SDValue Cmp = Cond.getOperand(1);
15656 unsigned Opc = Cmp.getOpcode();
15657 MVT VT = Op.getSimpleValueType();
15659 bool IllegalFPCMov = false;
15660 if (VT.isFloatingPoint() && !VT.isVector() &&
15661 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15662 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15664 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15665 Opc == X86ISD::BT) { // FIXME
15669 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15670 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15671 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15672 Cond.getOperand(0).getValueType() != MVT::i8)) {
15673 SDValue LHS = Cond.getOperand(0);
15674 SDValue RHS = Cond.getOperand(1);
15675 unsigned X86Opcode;
15678 switch (CondOpcode) {
15679 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15680 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15681 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15682 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15683 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15684 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15685 default: llvm_unreachable("unexpected overflowing operator");
15687 if (CondOpcode == ISD::UMULO)
15688 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15691 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15693 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15695 if (CondOpcode == ISD::UMULO)
15696 Cond = X86Op.getValue(2);
15698 Cond = X86Op.getValue(1);
15700 CC = DAG.getConstant(X86Cond, MVT::i8);
15705 // Look pass the truncate if the high bits are known zero.
15706 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15707 Cond = Cond.getOperand(0);
15709 // We know the result of AND is compared against zero. Try to match
15711 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15712 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15713 if (NewSetCC.getNode()) {
15714 CC = NewSetCC.getOperand(0);
15715 Cond = NewSetCC.getOperand(1);
15722 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15723 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15726 // a < b ? -1 : 0 -> RES = ~setcc_carry
15727 // a < b ? 0 : -1 -> RES = setcc_carry
15728 // a >= b ? -1 : 0 -> RES = setcc_carry
15729 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15730 if (Cond.getOpcode() == X86ISD::SUB) {
15731 Cond = ConvertCmpIfNecessary(Cond, DAG);
15732 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15734 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15735 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15736 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15737 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15738 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15739 return DAG.getNOT(DL, Res, Res.getValueType());
15744 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15745 // widen the cmov and push the truncate through. This avoids introducing a new
15746 // branch during isel and doesn't add any extensions.
15747 if (Op.getValueType() == MVT::i8 &&
15748 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15749 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15750 if (T1.getValueType() == T2.getValueType() &&
15751 // Blacklist CopyFromReg to avoid partial register stalls.
15752 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15753 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15754 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15755 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15759 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15760 // condition is true.
15761 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15762 SDValue Ops[] = { Op2, Op1, CC, Cond };
15763 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15766 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15767 SelectionDAG &DAG) {
15768 MVT VT = Op->getSimpleValueType(0);
15769 SDValue In = Op->getOperand(0);
15770 MVT InVT = In.getSimpleValueType();
15771 MVT VTElt = VT.getVectorElementType();
15772 MVT InVTElt = InVT.getVectorElementType();
15776 if ((InVTElt == MVT::i1) &&
15777 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15778 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15780 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15781 VTElt.getSizeInBits() <= 16)) ||
15783 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15784 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15786 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15787 VTElt.getSizeInBits() >= 32))))
15788 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15790 unsigned int NumElts = VT.getVectorNumElements();
15792 if (NumElts != 8 && NumElts != 16)
15795 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15796 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15797 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15798 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15802 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15804 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15805 Constant *C = ConstantInt::get(*DAG.getContext(),
15806 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15808 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15809 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15810 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15811 MachinePointerInfo::getConstantPool(),
15812 false, false, false, Alignment);
15813 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15814 if (VT.is512BitVector())
15816 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15819 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15820 SelectionDAG &DAG) {
15821 MVT VT = Op->getSimpleValueType(0);
15822 SDValue In = Op->getOperand(0);
15823 MVT InVT = In.getSimpleValueType();
15826 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15827 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15829 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15830 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15831 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15834 if (Subtarget->hasInt256())
15835 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15837 // Optimize vectors in AVX mode
15838 // Sign extend v8i16 to v8i32 and
15841 // Divide input vector into two parts
15842 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15843 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15844 // concat the vectors to original VT
15846 unsigned NumElems = InVT.getVectorNumElements();
15847 SDValue Undef = DAG.getUNDEF(InVT);
15849 SmallVector<int,8> ShufMask1(NumElems, -1);
15850 for (unsigned i = 0; i != NumElems/2; ++i)
15853 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15855 SmallVector<int,8> ShufMask2(NumElems, -1);
15856 for (unsigned i = 0; i != NumElems/2; ++i)
15857 ShufMask2[i] = i + NumElems/2;
15859 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15861 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15862 VT.getVectorNumElements()/2);
15864 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15865 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15867 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15870 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15871 // may emit an illegal shuffle but the expansion is still better than scalar
15872 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15873 // we'll emit a shuffle and a arithmetic shift.
15874 // TODO: It is possible to support ZExt by zeroing the undef values during
15875 // the shuffle phase or after the shuffle.
15876 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15877 SelectionDAG &DAG) {
15878 MVT RegVT = Op.getSimpleValueType();
15879 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15880 assert(RegVT.isInteger() &&
15881 "We only custom lower integer vector sext loads.");
15883 // Nothing useful we can do without SSE2 shuffles.
15884 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15886 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15888 EVT MemVT = Ld->getMemoryVT();
15889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15890 unsigned RegSz = RegVT.getSizeInBits();
15892 ISD::LoadExtType Ext = Ld->getExtensionType();
15894 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15895 && "Only anyext and sext are currently implemented.");
15896 assert(MemVT != RegVT && "Cannot extend to the same type");
15897 assert(MemVT.isVector() && "Must load a vector from memory");
15899 unsigned NumElems = RegVT.getVectorNumElements();
15900 unsigned MemSz = MemVT.getSizeInBits();
15901 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15903 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15904 // The only way in which we have a legal 256-bit vector result but not the
15905 // integer 256-bit operations needed to directly lower a sextload is if we
15906 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15907 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15908 // correctly legalized. We do this late to allow the canonical form of
15909 // sextload to persist throughout the rest of the DAG combiner -- it wants
15910 // to fold together any extensions it can, and so will fuse a sign_extend
15911 // of an sextload into a sextload targeting a wider value.
15913 if (MemSz == 128) {
15914 // Just switch this to a normal load.
15915 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15916 "it must be a legal 128-bit vector "
15918 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15919 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15920 Ld->isInvariant(), Ld->getAlignment());
15922 assert(MemSz < 128 &&
15923 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15924 // Do an sext load to a 128-bit vector type. We want to use the same
15925 // number of elements, but elements half as wide. This will end up being
15926 // recursively lowered by this routine, but will succeed as we definitely
15927 // have all the necessary features if we're using AVX1.
15929 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15930 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15932 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15933 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15934 Ld->isNonTemporal(), Ld->isInvariant(),
15935 Ld->getAlignment());
15938 // Replace chain users with the new chain.
15939 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15940 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15942 // Finally, do a normal sign-extend to the desired register.
15943 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15946 // All sizes must be a power of two.
15947 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15948 "Non-power-of-two elements are not custom lowered!");
15950 // Attempt to load the original value using scalar loads.
15951 // Find the largest scalar type that divides the total loaded size.
15952 MVT SclrLoadTy = MVT::i8;
15953 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15954 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15955 MVT Tp = (MVT::SimpleValueType)tp;
15956 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15961 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15962 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15964 SclrLoadTy = MVT::f64;
15966 // Calculate the number of scalar loads that we need to perform
15967 // in order to load our vector from memory.
15968 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15970 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15971 "Can only lower sext loads with a single scalar load!");
15973 unsigned loadRegZize = RegSz;
15974 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15977 // Represent our vector as a sequence of elements which are the
15978 // largest scalar that we can load.
15979 EVT LoadUnitVecVT = EVT::getVectorVT(
15980 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15982 // Represent the data using the same element type that is stored in
15983 // memory. In practice, we ''widen'' MemVT.
15985 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15986 loadRegZize / MemVT.getScalarType().getSizeInBits());
15988 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15989 "Invalid vector type");
15991 // We can't shuffle using an illegal type.
15992 assert(TLI.isTypeLegal(WideVecVT) &&
15993 "We only lower types that form legal widened vector types");
15995 SmallVector<SDValue, 8> Chains;
15996 SDValue Ptr = Ld->getBasePtr();
15997 SDValue Increment =
15998 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15999 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16001 for (unsigned i = 0; i < NumLoads; ++i) {
16002 // Perform a single load.
16003 SDValue ScalarLoad =
16004 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16005 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16006 Ld->getAlignment());
16007 Chains.push_back(ScalarLoad.getValue(1));
16008 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16009 // another round of DAGCombining.
16011 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16013 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16014 ScalarLoad, DAG.getIntPtrConstant(i));
16016 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16019 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16021 // Bitcast the loaded value to a vector of the original element type, in
16022 // the size of the target vector type.
16023 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16024 unsigned SizeRatio = RegSz / MemSz;
16026 if (Ext == ISD::SEXTLOAD) {
16027 // If we have SSE4.1, we can directly emit a VSEXT node.
16028 if (Subtarget->hasSSE41()) {
16029 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16030 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16034 // Otherwise we'll shuffle the small elements in the high bits of the
16035 // larger type and perform an arithmetic shift. If the shift is not legal
16036 // it's better to scalarize.
16037 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16038 "We can't implement a sext load without an arithmetic right shift!");
16040 // Redistribute the loaded elements into the different locations.
16041 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16042 for (unsigned i = 0; i != NumElems; ++i)
16043 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16045 SDValue Shuff = DAG.getVectorShuffle(
16046 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16048 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16050 // Build the arithmetic shift.
16051 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16052 MemVT.getVectorElementType().getSizeInBits();
16054 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16056 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16060 // Redistribute the loaded elements into the different locations.
16061 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16062 for (unsigned i = 0; i != NumElems; ++i)
16063 ShuffleVec[i * SizeRatio] = i;
16065 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16066 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16068 // Bitcast to the requested type.
16069 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16070 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16074 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16075 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16076 // from the AND / OR.
16077 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16078 Opc = Op.getOpcode();
16079 if (Opc != ISD::OR && Opc != ISD::AND)
16081 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16082 Op.getOperand(0).hasOneUse() &&
16083 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16084 Op.getOperand(1).hasOneUse());
16087 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16088 // 1 and that the SETCC node has a single use.
16089 static bool isXor1OfSetCC(SDValue Op) {
16090 if (Op.getOpcode() != ISD::XOR)
16092 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16093 if (N1C && N1C->getAPIntValue() == 1) {
16094 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16095 Op.getOperand(0).hasOneUse();
16100 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16101 bool addTest = true;
16102 SDValue Chain = Op.getOperand(0);
16103 SDValue Cond = Op.getOperand(1);
16104 SDValue Dest = Op.getOperand(2);
16107 bool Inverted = false;
16109 if (Cond.getOpcode() == ISD::SETCC) {
16110 // Check for setcc([su]{add,sub,mul}o == 0).
16111 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16112 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16113 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16114 Cond.getOperand(0).getResNo() == 1 &&
16115 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16116 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16117 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16118 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16119 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16120 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16122 Cond = Cond.getOperand(0);
16124 SDValue NewCond = LowerSETCC(Cond, DAG);
16125 if (NewCond.getNode())
16130 // FIXME: LowerXALUO doesn't handle these!!
16131 else if (Cond.getOpcode() == X86ISD::ADD ||
16132 Cond.getOpcode() == X86ISD::SUB ||
16133 Cond.getOpcode() == X86ISD::SMUL ||
16134 Cond.getOpcode() == X86ISD::UMUL)
16135 Cond = LowerXALUO(Cond, DAG);
16138 // Look pass (and (setcc_carry (cmp ...)), 1).
16139 if (Cond.getOpcode() == ISD::AND &&
16140 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16141 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16142 if (C && C->getAPIntValue() == 1)
16143 Cond = Cond.getOperand(0);
16146 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16147 // setting operand in place of the X86ISD::SETCC.
16148 unsigned CondOpcode = Cond.getOpcode();
16149 if (CondOpcode == X86ISD::SETCC ||
16150 CondOpcode == X86ISD::SETCC_CARRY) {
16151 CC = Cond.getOperand(0);
16153 SDValue Cmp = Cond.getOperand(1);
16154 unsigned Opc = Cmp.getOpcode();
16155 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16156 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16160 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16164 // These can only come from an arithmetic instruction with overflow,
16165 // e.g. SADDO, UADDO.
16166 Cond = Cond.getNode()->getOperand(1);
16172 CondOpcode = Cond.getOpcode();
16173 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16174 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16175 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16176 Cond.getOperand(0).getValueType() != MVT::i8)) {
16177 SDValue LHS = Cond.getOperand(0);
16178 SDValue RHS = Cond.getOperand(1);
16179 unsigned X86Opcode;
16182 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16183 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16185 switch (CondOpcode) {
16186 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16190 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16193 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16194 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16198 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16201 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16202 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16203 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16204 default: llvm_unreachable("unexpected overflowing operator");
16207 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16208 if (CondOpcode == ISD::UMULO)
16209 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16212 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16214 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16216 if (CondOpcode == ISD::UMULO)
16217 Cond = X86Op.getValue(2);
16219 Cond = X86Op.getValue(1);
16221 CC = DAG.getConstant(X86Cond, MVT::i8);
16225 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16226 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16227 if (CondOpc == ISD::OR) {
16228 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16229 // two branches instead of an explicit OR instruction with a
16231 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16232 isX86LogicalCmp(Cmp)) {
16233 CC = Cond.getOperand(0).getOperand(0);
16234 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16235 Chain, Dest, CC, Cmp);
16236 CC = Cond.getOperand(1).getOperand(0);
16240 } else { // ISD::AND
16241 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16242 // two branches instead of an explicit AND instruction with a
16243 // separate test. However, we only do this if this block doesn't
16244 // have a fall-through edge, because this requires an explicit
16245 // jmp when the condition is false.
16246 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16247 isX86LogicalCmp(Cmp) &&
16248 Op.getNode()->hasOneUse()) {
16249 X86::CondCode CCode =
16250 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16251 CCode = X86::GetOppositeBranchCondition(CCode);
16252 CC = DAG.getConstant(CCode, MVT::i8);
16253 SDNode *User = *Op.getNode()->use_begin();
16254 // Look for an unconditional branch following this conditional branch.
16255 // We need this because we need to reverse the successors in order
16256 // to implement FCMP_OEQ.
16257 if (User->getOpcode() == ISD::BR) {
16258 SDValue FalseBB = User->getOperand(1);
16260 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16261 assert(NewBR == User);
16265 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16266 Chain, Dest, CC, Cmp);
16267 X86::CondCode CCode =
16268 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16269 CCode = X86::GetOppositeBranchCondition(CCode);
16270 CC = DAG.getConstant(CCode, MVT::i8);
16276 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16277 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16278 // It should be transformed during dag combiner except when the condition
16279 // is set by a arithmetics with overflow node.
16280 X86::CondCode CCode =
16281 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16282 CCode = X86::GetOppositeBranchCondition(CCode);
16283 CC = DAG.getConstant(CCode, MVT::i8);
16284 Cond = Cond.getOperand(0).getOperand(1);
16286 } else if (Cond.getOpcode() == ISD::SETCC &&
16287 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16288 // For FCMP_OEQ, we can emit
16289 // two branches instead of an explicit AND instruction with a
16290 // separate test. However, we only do this if this block doesn't
16291 // have a fall-through edge, because this requires an explicit
16292 // jmp when the condition is false.
16293 if (Op.getNode()->hasOneUse()) {
16294 SDNode *User = *Op.getNode()->use_begin();
16295 // Look for an unconditional branch following this conditional branch.
16296 // We need this because we need to reverse the successors in order
16297 // to implement FCMP_OEQ.
16298 if (User->getOpcode() == ISD::BR) {
16299 SDValue FalseBB = User->getOperand(1);
16301 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16302 assert(NewBR == User);
16306 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16307 Cond.getOperand(0), Cond.getOperand(1));
16308 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16309 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16310 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16311 Chain, Dest, CC, Cmp);
16312 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16317 } else if (Cond.getOpcode() == ISD::SETCC &&
16318 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16319 // For FCMP_UNE, we can emit
16320 // two branches instead of an explicit AND instruction with a
16321 // separate test. However, we only do this if this block doesn't
16322 // have a fall-through edge, because this requires an explicit
16323 // jmp when the condition is false.
16324 if (Op.getNode()->hasOneUse()) {
16325 SDNode *User = *Op.getNode()->use_begin();
16326 // Look for an unconditional branch following this conditional branch.
16327 // We need this because we need to reverse the successors in order
16328 // to implement FCMP_UNE.
16329 if (User->getOpcode() == ISD::BR) {
16330 SDValue FalseBB = User->getOperand(1);
16332 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16333 assert(NewBR == User);
16336 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16337 Cond.getOperand(0), Cond.getOperand(1));
16338 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16339 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16340 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16341 Chain, Dest, CC, Cmp);
16342 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16352 // Look pass the truncate if the high bits are known zero.
16353 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16354 Cond = Cond.getOperand(0);
16356 // We know the result of AND is compared against zero. Try to match
16358 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16359 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16360 if (NewSetCC.getNode()) {
16361 CC = NewSetCC.getOperand(0);
16362 Cond = NewSetCC.getOperand(1);
16369 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16370 CC = DAG.getConstant(X86Cond, MVT::i8);
16371 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16373 Cond = ConvertCmpIfNecessary(Cond, DAG);
16374 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16375 Chain, Dest, CC, Cond);
16378 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16379 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16380 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16381 // that the guard pages used by the OS virtual memory manager are allocated in
16382 // correct sequence.
16384 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16385 SelectionDAG &DAG) const {
16386 MachineFunction &MF = DAG.getMachineFunction();
16387 bool SplitStack = MF.shouldSplitStack();
16388 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16394 SDNode* Node = Op.getNode();
16396 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16397 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16398 " not tell us which reg is the stack pointer!");
16399 EVT VT = Node->getValueType(0);
16400 SDValue Tmp1 = SDValue(Node, 0);
16401 SDValue Tmp2 = SDValue(Node, 1);
16402 SDValue Tmp3 = Node->getOperand(2);
16403 SDValue Chain = Tmp1.getOperand(0);
16405 // Chain the dynamic stack allocation so that it doesn't modify the stack
16406 // pointer when other instructions are using the stack.
16407 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16410 SDValue Size = Tmp2.getOperand(1);
16411 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16412 Chain = SP.getValue(1);
16413 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16414 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16415 unsigned StackAlign = TFI.getStackAlignment();
16416 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16417 if (Align > StackAlign)
16418 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16419 DAG.getConstant(-(uint64_t)Align, VT));
16420 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16422 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16423 DAG.getIntPtrConstant(0, true), SDValue(),
16426 SDValue Ops[2] = { Tmp1, Tmp2 };
16427 return DAG.getMergeValues(Ops, dl);
16431 SDValue Chain = Op.getOperand(0);
16432 SDValue Size = Op.getOperand(1);
16433 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16434 EVT VT = Op.getNode()->getValueType(0);
16436 bool Is64Bit = Subtarget->is64Bit();
16437 EVT SPTy = getPointerTy();
16440 MachineRegisterInfo &MRI = MF.getRegInfo();
16443 // The 64 bit implementation of segmented stacks needs to clobber both r10
16444 // r11. This makes it impossible to use it along with nested parameters.
16445 const Function *F = MF.getFunction();
16447 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16449 if (I->hasNestAttr())
16450 report_fatal_error("Cannot use segmented stacks with functions that "
16451 "have nested arguments.");
16454 const TargetRegisterClass *AddrRegClass =
16455 getRegClassFor(getPointerTy());
16456 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16457 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16458 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16459 DAG.getRegister(Vreg, SPTy));
16460 SDValue Ops1[2] = { Value, Chain };
16461 return DAG.getMergeValues(Ops1, dl);
16464 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16466 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16467 Flag = Chain.getValue(1);
16468 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16470 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16472 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16473 DAG.getSubtarget().getRegisterInfo());
16474 unsigned SPReg = RegInfo->getStackRegister();
16475 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16476 Chain = SP.getValue(1);
16479 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16480 DAG.getConstant(-(uint64_t)Align, VT));
16481 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16484 SDValue Ops1[2] = { SP, Chain };
16485 return DAG.getMergeValues(Ops1, dl);
16489 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16490 MachineFunction &MF = DAG.getMachineFunction();
16491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16493 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16496 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16497 // vastart just stores the address of the VarArgsFrameIndex slot into the
16498 // memory location argument.
16499 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16501 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16502 MachinePointerInfo(SV), false, false, 0);
16506 // gp_offset (0 - 6 * 8)
16507 // fp_offset (48 - 48 + 8 * 16)
16508 // overflow_arg_area (point to parameters coming in memory).
16510 SmallVector<SDValue, 8> MemOps;
16511 SDValue FIN = Op.getOperand(1);
16513 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16514 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16516 FIN, MachinePointerInfo(SV), false, false, 0);
16517 MemOps.push_back(Store);
16520 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16521 FIN, DAG.getIntPtrConstant(4));
16522 Store = DAG.getStore(Op.getOperand(0), DL,
16523 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16525 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16526 MemOps.push_back(Store);
16528 // Store ptr to overflow_arg_area
16529 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16530 FIN, DAG.getIntPtrConstant(4));
16531 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16533 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16534 MachinePointerInfo(SV, 8),
16536 MemOps.push_back(Store);
16538 // Store ptr to reg_save_area.
16539 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16540 FIN, DAG.getIntPtrConstant(8));
16541 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16543 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16544 MachinePointerInfo(SV, 16), false, false, 0);
16545 MemOps.push_back(Store);
16546 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16549 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16550 assert(Subtarget->is64Bit() &&
16551 "LowerVAARG only handles 64-bit va_arg!");
16552 assert((Subtarget->isTargetLinux() ||
16553 Subtarget->isTargetDarwin()) &&
16554 "Unhandled target in LowerVAARG");
16555 assert(Op.getNode()->getNumOperands() == 4);
16556 SDValue Chain = Op.getOperand(0);
16557 SDValue SrcPtr = Op.getOperand(1);
16558 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16559 unsigned Align = Op.getConstantOperandVal(3);
16562 EVT ArgVT = Op.getNode()->getValueType(0);
16563 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16564 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16567 // Decide which area this value should be read from.
16568 // TODO: Implement the AMD64 ABI in its entirety. This simple
16569 // selection mechanism works only for the basic types.
16570 if (ArgVT == MVT::f80) {
16571 llvm_unreachable("va_arg for f80 not yet implemented");
16572 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16573 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16574 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16575 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16577 llvm_unreachable("Unhandled argument type in LowerVAARG");
16580 if (ArgMode == 2) {
16581 // Sanity Check: Make sure using fp_offset makes sense.
16582 assert(!DAG.getTarget().Options.UseSoftFloat &&
16583 !(DAG.getMachineFunction()
16584 .getFunction()->getAttributes()
16585 .hasAttribute(AttributeSet::FunctionIndex,
16586 Attribute::NoImplicitFloat)) &&
16587 Subtarget->hasSSE1());
16590 // Insert VAARG_64 node into the DAG
16591 // VAARG_64 returns two values: Variable Argument Address, Chain
16592 SmallVector<SDValue, 11> InstOps;
16593 InstOps.push_back(Chain);
16594 InstOps.push_back(SrcPtr);
16595 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16596 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16597 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16598 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16599 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16600 VTs, InstOps, MVT::i64,
16601 MachinePointerInfo(SV),
16603 /*Volatile=*/false,
16605 /*WriteMem=*/true);
16606 Chain = VAARG.getValue(1);
16608 // Load the next argument and return it
16609 return DAG.getLoad(ArgVT, dl,
16612 MachinePointerInfo(),
16613 false, false, false, 0);
16616 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16617 SelectionDAG &DAG) {
16618 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16619 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16620 SDValue Chain = Op.getOperand(0);
16621 SDValue DstPtr = Op.getOperand(1);
16622 SDValue SrcPtr = Op.getOperand(2);
16623 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16624 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16627 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16628 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16630 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16633 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16634 // amount is a constant. Takes immediate version of shift as input.
16635 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16636 SDValue SrcOp, uint64_t ShiftAmt,
16637 SelectionDAG &DAG) {
16638 MVT ElementType = VT.getVectorElementType();
16640 // Fold this packed shift into its first operand if ShiftAmt is 0.
16644 // Check for ShiftAmt >= element width
16645 if (ShiftAmt >= ElementType.getSizeInBits()) {
16646 if (Opc == X86ISD::VSRAI)
16647 ShiftAmt = ElementType.getSizeInBits() - 1;
16649 return DAG.getConstant(0, VT);
16652 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16653 && "Unknown target vector shift-by-constant node");
16655 // Fold this packed vector shift into a build vector if SrcOp is a
16656 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16657 if (VT == SrcOp.getSimpleValueType() &&
16658 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16659 SmallVector<SDValue, 8> Elts;
16660 unsigned NumElts = SrcOp->getNumOperands();
16661 ConstantSDNode *ND;
16664 default: llvm_unreachable(nullptr);
16665 case X86ISD::VSHLI:
16666 for (unsigned i=0; i!=NumElts; ++i) {
16667 SDValue CurrentOp = SrcOp->getOperand(i);
16668 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16669 Elts.push_back(CurrentOp);
16672 ND = cast<ConstantSDNode>(CurrentOp);
16673 const APInt &C = ND->getAPIntValue();
16674 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16677 case X86ISD::VSRLI:
16678 for (unsigned i=0; i!=NumElts; ++i) {
16679 SDValue CurrentOp = SrcOp->getOperand(i);
16680 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16681 Elts.push_back(CurrentOp);
16684 ND = cast<ConstantSDNode>(CurrentOp);
16685 const APInt &C = ND->getAPIntValue();
16686 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16689 case X86ISD::VSRAI:
16690 for (unsigned i=0; i!=NumElts; ++i) {
16691 SDValue CurrentOp = SrcOp->getOperand(i);
16692 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16693 Elts.push_back(CurrentOp);
16696 ND = cast<ConstantSDNode>(CurrentOp);
16697 const APInt &C = ND->getAPIntValue();
16698 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16703 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16706 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16709 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16710 // may or may not be a constant. Takes immediate version of shift as input.
16711 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16712 SDValue SrcOp, SDValue ShAmt,
16713 SelectionDAG &DAG) {
16714 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16716 // Catch shift-by-constant.
16717 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16718 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16719 CShAmt->getZExtValue(), DAG);
16721 // Change opcode to non-immediate version
16723 default: llvm_unreachable("Unknown target vector shift node");
16724 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16725 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16726 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16729 // Need to build a vector containing shift amount
16730 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16733 ShOps[1] = DAG.getConstant(0, MVT::i32);
16734 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16735 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16737 // The return type has to be a 128-bit type with the same element
16738 // type as the input type.
16739 MVT EltVT = VT.getVectorElementType();
16740 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16742 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16743 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16746 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16747 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16748 /// necessary casting for \p Mask when lowering masking intrinsics.
16749 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16750 SDValue PreservedSrc,
16751 const X86Subtarget *Subtarget,
16752 SelectionDAG &DAG) {
16753 EVT VT = Op.getValueType();
16754 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16755 MVT::i1, VT.getVectorNumElements());
16756 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16757 Mask.getValueType().getSizeInBits());
16760 assert(MaskVT.isSimple() && "invalid mask type");
16762 if (isAllOnes(Mask))
16765 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16766 // are extracted by EXTRACT_SUBVECTOR.
16767 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16768 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16769 DAG.getIntPtrConstant(0));
16771 switch (Op.getOpcode()) {
16773 case X86ISD::PCMPEQM:
16774 case X86ISD::PCMPGTM:
16776 case X86ISD::CMPMU:
16777 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16779 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16780 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16781 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16784 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16785 SDValue PreservedSrc,
16786 const X86Subtarget *Subtarget,
16787 SelectionDAG &DAG) {
16788 if (isAllOnes(Mask))
16791 EVT VT = Op.getValueType();
16793 // The mask should be of type MVT::i1
16794 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16796 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16797 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16798 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16801 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16803 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16804 case Intrinsic::x86_fma_vfmadd_ps:
16805 case Intrinsic::x86_fma_vfmadd_pd:
16806 case Intrinsic::x86_fma_vfmadd_ps_256:
16807 case Intrinsic::x86_fma_vfmadd_pd_256:
16808 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16809 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16810 return X86ISD::FMADD;
16811 case Intrinsic::x86_fma_vfmsub_ps:
16812 case Intrinsic::x86_fma_vfmsub_pd:
16813 case Intrinsic::x86_fma_vfmsub_ps_256:
16814 case Intrinsic::x86_fma_vfmsub_pd_256:
16815 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16816 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16817 return X86ISD::FMSUB;
16818 case Intrinsic::x86_fma_vfnmadd_ps:
16819 case Intrinsic::x86_fma_vfnmadd_pd:
16820 case Intrinsic::x86_fma_vfnmadd_ps_256:
16821 case Intrinsic::x86_fma_vfnmadd_pd_256:
16822 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16823 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16824 return X86ISD::FNMADD;
16825 case Intrinsic::x86_fma_vfnmsub_ps:
16826 case Intrinsic::x86_fma_vfnmsub_pd:
16827 case Intrinsic::x86_fma_vfnmsub_ps_256:
16828 case Intrinsic::x86_fma_vfnmsub_pd_256:
16829 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16830 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16831 return X86ISD::FNMSUB;
16832 case Intrinsic::x86_fma_vfmaddsub_ps:
16833 case Intrinsic::x86_fma_vfmaddsub_pd:
16834 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16835 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16836 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16837 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16838 return X86ISD::FMADDSUB;
16839 case Intrinsic::x86_fma_vfmsubadd_ps:
16840 case Intrinsic::x86_fma_vfmsubadd_pd:
16841 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16842 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16843 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16844 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16845 return X86ISD::FMSUBADD;
16849 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16850 SelectionDAG &DAG) {
16852 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16853 EVT VT = Op.getValueType();
16854 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16856 switch(IntrData->Type) {
16857 case INTR_TYPE_1OP:
16858 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16859 case INTR_TYPE_2OP:
16860 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16862 case INTR_TYPE_3OP:
16863 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16864 Op.getOperand(2), Op.getOperand(3));
16865 case INTR_TYPE_1OP_MASK_RM: {
16866 SDValue Src = Op.getOperand(1);
16867 SDValue Src0 = Op.getOperand(2);
16868 SDValue Mask = Op.getOperand(3);
16869 SDValue RoundingMode = Op.getOperand(4);
16870 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16872 Mask, Src0, Subtarget, DAG);
16874 case INTR_TYPE_SCALAR_MASK_RM: {
16875 SDValue Src1 = Op.getOperand(1);
16876 SDValue Src2 = Op.getOperand(2);
16877 SDValue Src0 = Op.getOperand(3);
16878 SDValue Mask = Op.getOperand(4);
16879 SDValue RoundingMode = Op.getOperand(5);
16880 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16882 Mask, Src0, Subtarget, DAG);
16884 case INTR_TYPE_2OP_MASK: {
16885 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16887 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16890 case CMP_MASK_CC: {
16891 // Comparison intrinsics with masks.
16892 // Example of transformation:
16893 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16894 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16896 // (v8i1 (insert_subvector undef,
16897 // (v2i1 (and (PCMPEQM %a, %b),
16898 // (extract_subvector
16899 // (v8i1 (bitcast %mask)), 0))), 0))))
16900 EVT VT = Op.getOperand(1).getValueType();
16901 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16902 VT.getVectorNumElements());
16903 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16904 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16905 Mask.getValueType().getSizeInBits());
16907 if (IntrData->Type == CMP_MASK_CC) {
16908 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16909 Op.getOperand(2), Op.getOperand(3));
16911 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16912 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16915 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16916 DAG.getTargetConstant(0, MaskVT),
16918 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16919 DAG.getUNDEF(BitcastVT), CmpMask,
16920 DAG.getIntPtrConstant(0));
16921 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16923 case COMI: { // Comparison intrinsics
16924 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16925 SDValue LHS = Op.getOperand(1);
16926 SDValue RHS = Op.getOperand(2);
16927 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16928 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16929 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16930 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16931 DAG.getConstant(X86CC, MVT::i8), Cond);
16932 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16935 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16936 Op.getOperand(1), Op.getOperand(2), DAG);
16938 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16939 Op.getOperand(1), Op.getOperand(2), DAG),
16940 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16947 default: return SDValue(); // Don't custom lower most intrinsics.
16949 // Arithmetic intrinsics.
16950 case Intrinsic::x86_sse2_pmulu_dq:
16951 case Intrinsic::x86_avx2_pmulu_dq:
16952 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16953 Op.getOperand(1), Op.getOperand(2));
16955 case Intrinsic::x86_sse41_pmuldq:
16956 case Intrinsic::x86_avx2_pmul_dq:
16957 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16958 Op.getOperand(1), Op.getOperand(2));
16960 case Intrinsic::x86_sse2_pmulhu_w:
16961 case Intrinsic::x86_avx2_pmulhu_w:
16962 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16963 Op.getOperand(1), Op.getOperand(2));
16965 case Intrinsic::x86_sse2_pmulh_w:
16966 case Intrinsic::x86_avx2_pmulh_w:
16967 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16968 Op.getOperand(1), Op.getOperand(2));
16970 // SSE/SSE2/AVX floating point max/min intrinsics.
16971 case Intrinsic::x86_sse_max_ps:
16972 case Intrinsic::x86_sse2_max_pd:
16973 case Intrinsic::x86_avx_max_ps_256:
16974 case Intrinsic::x86_avx_max_pd_256:
16975 case Intrinsic::x86_sse_min_ps:
16976 case Intrinsic::x86_sse2_min_pd:
16977 case Intrinsic::x86_avx_min_ps_256:
16978 case Intrinsic::x86_avx_min_pd_256: {
16981 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16982 case Intrinsic::x86_sse_max_ps:
16983 case Intrinsic::x86_sse2_max_pd:
16984 case Intrinsic::x86_avx_max_ps_256:
16985 case Intrinsic::x86_avx_max_pd_256:
16986 Opcode = X86ISD::FMAX;
16988 case Intrinsic::x86_sse_min_ps:
16989 case Intrinsic::x86_sse2_min_pd:
16990 case Intrinsic::x86_avx_min_ps_256:
16991 case Intrinsic::x86_avx_min_pd_256:
16992 Opcode = X86ISD::FMIN;
16995 return DAG.getNode(Opcode, dl, Op.getValueType(),
16996 Op.getOperand(1), Op.getOperand(2));
16999 // AVX2 variable shift intrinsics
17000 case Intrinsic::x86_avx2_psllv_d:
17001 case Intrinsic::x86_avx2_psllv_q:
17002 case Intrinsic::x86_avx2_psllv_d_256:
17003 case Intrinsic::x86_avx2_psllv_q_256:
17004 case Intrinsic::x86_avx2_psrlv_d:
17005 case Intrinsic::x86_avx2_psrlv_q:
17006 case Intrinsic::x86_avx2_psrlv_d_256:
17007 case Intrinsic::x86_avx2_psrlv_q_256:
17008 case Intrinsic::x86_avx2_psrav_d:
17009 case Intrinsic::x86_avx2_psrav_d_256: {
17012 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17013 case Intrinsic::x86_avx2_psllv_d:
17014 case Intrinsic::x86_avx2_psllv_q:
17015 case Intrinsic::x86_avx2_psllv_d_256:
17016 case Intrinsic::x86_avx2_psllv_q_256:
17019 case Intrinsic::x86_avx2_psrlv_d:
17020 case Intrinsic::x86_avx2_psrlv_q:
17021 case Intrinsic::x86_avx2_psrlv_d_256:
17022 case Intrinsic::x86_avx2_psrlv_q_256:
17025 case Intrinsic::x86_avx2_psrav_d:
17026 case Intrinsic::x86_avx2_psrav_d_256:
17030 return DAG.getNode(Opcode, dl, Op.getValueType(),
17031 Op.getOperand(1), Op.getOperand(2));
17034 case Intrinsic::x86_sse2_packssdw_128:
17035 case Intrinsic::x86_sse2_packsswb_128:
17036 case Intrinsic::x86_avx2_packssdw:
17037 case Intrinsic::x86_avx2_packsswb:
17038 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17039 Op.getOperand(1), Op.getOperand(2));
17041 case Intrinsic::x86_sse2_packuswb_128:
17042 case Intrinsic::x86_sse41_packusdw:
17043 case Intrinsic::x86_avx2_packuswb:
17044 case Intrinsic::x86_avx2_packusdw:
17045 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17046 Op.getOperand(1), Op.getOperand(2));
17048 case Intrinsic::x86_ssse3_pshuf_b_128:
17049 case Intrinsic::x86_avx2_pshuf_b:
17050 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17051 Op.getOperand(1), Op.getOperand(2));
17053 case Intrinsic::x86_sse2_pshuf_d:
17054 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17055 Op.getOperand(1), Op.getOperand(2));
17057 case Intrinsic::x86_sse2_pshufl_w:
17058 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17059 Op.getOperand(1), Op.getOperand(2));
17061 case Intrinsic::x86_sse2_pshufh_w:
17062 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17063 Op.getOperand(1), Op.getOperand(2));
17065 case Intrinsic::x86_ssse3_psign_b_128:
17066 case Intrinsic::x86_ssse3_psign_w_128:
17067 case Intrinsic::x86_ssse3_psign_d_128:
17068 case Intrinsic::x86_avx2_psign_b:
17069 case Intrinsic::x86_avx2_psign_w:
17070 case Intrinsic::x86_avx2_psign_d:
17071 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17072 Op.getOperand(1), Op.getOperand(2));
17074 case Intrinsic::x86_avx2_permd:
17075 case Intrinsic::x86_avx2_permps:
17076 // Operands intentionally swapped. Mask is last operand to intrinsic,
17077 // but second operand for node/instruction.
17078 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17079 Op.getOperand(2), Op.getOperand(1));
17081 case Intrinsic::x86_avx512_mask_valign_q_512:
17082 case Intrinsic::x86_avx512_mask_valign_d_512:
17083 // Vector source operands are swapped.
17084 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17085 Op.getValueType(), Op.getOperand(2),
17088 Op.getOperand(5), Op.getOperand(4),
17091 // ptest and testp intrinsics. The intrinsic these come from are designed to
17092 // return an integer value, not just an instruction so lower it to the ptest
17093 // or testp pattern and a setcc for the result.
17094 case Intrinsic::x86_sse41_ptestz:
17095 case Intrinsic::x86_sse41_ptestc:
17096 case Intrinsic::x86_sse41_ptestnzc:
17097 case Intrinsic::x86_avx_ptestz_256:
17098 case Intrinsic::x86_avx_ptestc_256:
17099 case Intrinsic::x86_avx_ptestnzc_256:
17100 case Intrinsic::x86_avx_vtestz_ps:
17101 case Intrinsic::x86_avx_vtestc_ps:
17102 case Intrinsic::x86_avx_vtestnzc_ps:
17103 case Intrinsic::x86_avx_vtestz_pd:
17104 case Intrinsic::x86_avx_vtestc_pd:
17105 case Intrinsic::x86_avx_vtestnzc_pd:
17106 case Intrinsic::x86_avx_vtestz_ps_256:
17107 case Intrinsic::x86_avx_vtestc_ps_256:
17108 case Intrinsic::x86_avx_vtestnzc_ps_256:
17109 case Intrinsic::x86_avx_vtestz_pd_256:
17110 case Intrinsic::x86_avx_vtestc_pd_256:
17111 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17112 bool IsTestPacked = false;
17115 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17116 case Intrinsic::x86_avx_vtestz_ps:
17117 case Intrinsic::x86_avx_vtestz_pd:
17118 case Intrinsic::x86_avx_vtestz_ps_256:
17119 case Intrinsic::x86_avx_vtestz_pd_256:
17120 IsTestPacked = true; // Fallthrough
17121 case Intrinsic::x86_sse41_ptestz:
17122 case Intrinsic::x86_avx_ptestz_256:
17124 X86CC = X86::COND_E;
17126 case Intrinsic::x86_avx_vtestc_ps:
17127 case Intrinsic::x86_avx_vtestc_pd:
17128 case Intrinsic::x86_avx_vtestc_ps_256:
17129 case Intrinsic::x86_avx_vtestc_pd_256:
17130 IsTestPacked = true; // Fallthrough
17131 case Intrinsic::x86_sse41_ptestc:
17132 case Intrinsic::x86_avx_ptestc_256:
17134 X86CC = X86::COND_B;
17136 case Intrinsic::x86_avx_vtestnzc_ps:
17137 case Intrinsic::x86_avx_vtestnzc_pd:
17138 case Intrinsic::x86_avx_vtestnzc_ps_256:
17139 case Intrinsic::x86_avx_vtestnzc_pd_256:
17140 IsTestPacked = true; // Fallthrough
17141 case Intrinsic::x86_sse41_ptestnzc:
17142 case Intrinsic::x86_avx_ptestnzc_256:
17144 X86CC = X86::COND_A;
17148 SDValue LHS = Op.getOperand(1);
17149 SDValue RHS = Op.getOperand(2);
17150 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17151 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17152 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17153 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17154 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17156 case Intrinsic::x86_avx512_kortestz_w:
17157 case Intrinsic::x86_avx512_kortestc_w: {
17158 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17159 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17160 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17161 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17162 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17163 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17164 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17167 case Intrinsic::x86_sse42_pcmpistria128:
17168 case Intrinsic::x86_sse42_pcmpestria128:
17169 case Intrinsic::x86_sse42_pcmpistric128:
17170 case Intrinsic::x86_sse42_pcmpestric128:
17171 case Intrinsic::x86_sse42_pcmpistrio128:
17172 case Intrinsic::x86_sse42_pcmpestrio128:
17173 case Intrinsic::x86_sse42_pcmpistris128:
17174 case Intrinsic::x86_sse42_pcmpestris128:
17175 case Intrinsic::x86_sse42_pcmpistriz128:
17176 case Intrinsic::x86_sse42_pcmpestriz128: {
17180 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17181 case Intrinsic::x86_sse42_pcmpistria128:
17182 Opcode = X86ISD::PCMPISTRI;
17183 X86CC = X86::COND_A;
17185 case Intrinsic::x86_sse42_pcmpestria128:
17186 Opcode = X86ISD::PCMPESTRI;
17187 X86CC = X86::COND_A;
17189 case Intrinsic::x86_sse42_pcmpistric128:
17190 Opcode = X86ISD::PCMPISTRI;
17191 X86CC = X86::COND_B;
17193 case Intrinsic::x86_sse42_pcmpestric128:
17194 Opcode = X86ISD::PCMPESTRI;
17195 X86CC = X86::COND_B;
17197 case Intrinsic::x86_sse42_pcmpistrio128:
17198 Opcode = X86ISD::PCMPISTRI;
17199 X86CC = X86::COND_O;
17201 case Intrinsic::x86_sse42_pcmpestrio128:
17202 Opcode = X86ISD::PCMPESTRI;
17203 X86CC = X86::COND_O;
17205 case Intrinsic::x86_sse42_pcmpistris128:
17206 Opcode = X86ISD::PCMPISTRI;
17207 X86CC = X86::COND_S;
17209 case Intrinsic::x86_sse42_pcmpestris128:
17210 Opcode = X86ISD::PCMPESTRI;
17211 X86CC = X86::COND_S;
17213 case Intrinsic::x86_sse42_pcmpistriz128:
17214 Opcode = X86ISD::PCMPISTRI;
17215 X86CC = X86::COND_E;
17217 case Intrinsic::x86_sse42_pcmpestriz128:
17218 Opcode = X86ISD::PCMPESTRI;
17219 X86CC = X86::COND_E;
17222 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17223 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17224 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17225 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17226 DAG.getConstant(X86CC, MVT::i8),
17227 SDValue(PCMP.getNode(), 1));
17228 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17231 case Intrinsic::x86_sse42_pcmpistri128:
17232 case Intrinsic::x86_sse42_pcmpestri128: {
17234 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17235 Opcode = X86ISD::PCMPISTRI;
17237 Opcode = X86ISD::PCMPESTRI;
17239 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17240 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17241 return DAG.getNode(Opcode, dl, VTs, NewOps);
17244 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17245 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17246 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17247 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17248 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17249 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17250 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17251 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17252 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17253 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17254 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17255 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17256 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17257 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17258 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17259 dl, Op.getValueType(),
17263 Op.getOperand(4), Op.getOperand(1),
17269 case Intrinsic::x86_fma_vfmadd_ps:
17270 case Intrinsic::x86_fma_vfmadd_pd:
17271 case Intrinsic::x86_fma_vfmsub_ps:
17272 case Intrinsic::x86_fma_vfmsub_pd:
17273 case Intrinsic::x86_fma_vfnmadd_ps:
17274 case Intrinsic::x86_fma_vfnmadd_pd:
17275 case Intrinsic::x86_fma_vfnmsub_ps:
17276 case Intrinsic::x86_fma_vfnmsub_pd:
17277 case Intrinsic::x86_fma_vfmaddsub_ps:
17278 case Intrinsic::x86_fma_vfmaddsub_pd:
17279 case Intrinsic::x86_fma_vfmsubadd_ps:
17280 case Intrinsic::x86_fma_vfmsubadd_pd:
17281 case Intrinsic::x86_fma_vfmadd_ps_256:
17282 case Intrinsic::x86_fma_vfmadd_pd_256:
17283 case Intrinsic::x86_fma_vfmsub_ps_256:
17284 case Intrinsic::x86_fma_vfmsub_pd_256:
17285 case Intrinsic::x86_fma_vfnmadd_ps_256:
17286 case Intrinsic::x86_fma_vfnmadd_pd_256:
17287 case Intrinsic::x86_fma_vfnmsub_ps_256:
17288 case Intrinsic::x86_fma_vfnmsub_pd_256:
17289 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17290 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17291 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17292 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17293 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17294 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17298 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17299 SDValue Src, SDValue Mask, SDValue Base,
17300 SDValue Index, SDValue ScaleOp, SDValue Chain,
17301 const X86Subtarget * Subtarget) {
17303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17304 assert(C && "Invalid scale type");
17305 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17306 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17307 Index.getSimpleValueType().getVectorNumElements());
17309 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17311 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17313 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17314 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17315 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17316 SDValue Segment = DAG.getRegister(0, MVT::i32);
17317 if (Src.getOpcode() == ISD::UNDEF)
17318 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17319 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17320 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17321 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17322 return DAG.getMergeValues(RetOps, dl);
17325 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17326 SDValue Src, SDValue Mask, SDValue Base,
17327 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17329 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17330 assert(C && "Invalid scale type");
17331 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17332 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17333 SDValue Segment = DAG.getRegister(0, MVT::i32);
17334 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17335 Index.getSimpleValueType().getVectorNumElements());
17337 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17339 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17341 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17342 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17343 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17344 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17345 return SDValue(Res, 1);
17348 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17349 SDValue Mask, SDValue Base, SDValue Index,
17350 SDValue ScaleOp, SDValue Chain) {
17352 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17353 assert(C && "Invalid scale type");
17354 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17355 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17356 SDValue Segment = DAG.getRegister(0, MVT::i32);
17358 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17360 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17362 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17364 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17365 //SDVTList VTs = DAG.getVTList(MVT::Other);
17366 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17367 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17368 return SDValue(Res, 0);
17371 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17372 // read performance monitor counters (x86_rdpmc).
17373 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17374 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17375 SmallVectorImpl<SDValue> &Results) {
17376 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17377 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17380 // The ECX register is used to select the index of the performance counter
17382 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17384 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17386 // Reads the content of a 64-bit performance counter and returns it in the
17387 // registers EDX:EAX.
17388 if (Subtarget->is64Bit()) {
17389 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17390 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17393 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17394 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17397 Chain = HI.getValue(1);
17399 if (Subtarget->is64Bit()) {
17400 // The EAX register is loaded with the low-order 32 bits. The EDX register
17401 // is loaded with the supported high-order bits of the counter.
17402 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17403 DAG.getConstant(32, MVT::i8));
17404 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17405 Results.push_back(Chain);
17409 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17410 SDValue Ops[] = { LO, HI };
17411 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17412 Results.push_back(Pair);
17413 Results.push_back(Chain);
17416 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17417 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17418 // also used to custom lower READCYCLECOUNTER nodes.
17419 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17420 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17421 SmallVectorImpl<SDValue> &Results) {
17422 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17423 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17426 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17427 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17428 // and the EAX register is loaded with the low-order 32 bits.
17429 if (Subtarget->is64Bit()) {
17430 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17431 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17434 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17435 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17438 SDValue Chain = HI.getValue(1);
17440 if (Opcode == X86ISD::RDTSCP_DAG) {
17441 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17443 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17444 // the ECX register. Add 'ecx' explicitly to the chain.
17445 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17447 // Explicitly store the content of ECX at the location passed in input
17448 // to the 'rdtscp' intrinsic.
17449 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17450 MachinePointerInfo(), false, false, 0);
17453 if (Subtarget->is64Bit()) {
17454 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17455 // the EAX register is loaded with the low-order 32 bits.
17456 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17457 DAG.getConstant(32, MVT::i8));
17458 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17459 Results.push_back(Chain);
17463 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17464 SDValue Ops[] = { LO, HI };
17465 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17466 Results.push_back(Pair);
17467 Results.push_back(Chain);
17470 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17471 SelectionDAG &DAG) {
17472 SmallVector<SDValue, 2> Results;
17474 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17476 return DAG.getMergeValues(Results, DL);
17480 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17481 SelectionDAG &DAG) {
17482 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17484 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17489 switch(IntrData->Type) {
17491 llvm_unreachable("Unknown Intrinsic Type");
17495 // Emit the node with the right value type.
17496 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17497 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17499 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17500 // Otherwise return the value from Rand, which is always 0, casted to i32.
17501 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17502 DAG.getConstant(1, Op->getValueType(1)),
17503 DAG.getConstant(X86::COND_B, MVT::i32),
17504 SDValue(Result.getNode(), 1) };
17505 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17506 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17509 // Return { result, isValid, chain }.
17510 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17511 SDValue(Result.getNode(), 2));
17514 //gather(v1, mask, index, base, scale);
17515 SDValue Chain = Op.getOperand(0);
17516 SDValue Src = Op.getOperand(2);
17517 SDValue Base = Op.getOperand(3);
17518 SDValue Index = Op.getOperand(4);
17519 SDValue Mask = Op.getOperand(5);
17520 SDValue Scale = Op.getOperand(6);
17521 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17525 //scatter(base, mask, index, v1, scale);
17526 SDValue Chain = Op.getOperand(0);
17527 SDValue Base = Op.getOperand(2);
17528 SDValue Mask = Op.getOperand(3);
17529 SDValue Index = Op.getOperand(4);
17530 SDValue Src = Op.getOperand(5);
17531 SDValue Scale = Op.getOperand(6);
17532 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17535 SDValue Hint = Op.getOperand(6);
17537 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17538 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17539 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17540 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17541 SDValue Chain = Op.getOperand(0);
17542 SDValue Mask = Op.getOperand(2);
17543 SDValue Index = Op.getOperand(3);
17544 SDValue Base = Op.getOperand(4);
17545 SDValue Scale = Op.getOperand(5);
17546 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17548 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17550 SmallVector<SDValue, 2> Results;
17551 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17552 return DAG.getMergeValues(Results, dl);
17554 // Read Performance Monitoring Counters.
17556 SmallVector<SDValue, 2> Results;
17557 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17558 return DAG.getMergeValues(Results, dl);
17560 // XTEST intrinsics.
17562 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17563 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17564 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17565 DAG.getConstant(X86::COND_NE, MVT::i8),
17567 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17568 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17569 Ret, SDValue(InTrans.getNode(), 1));
17573 SmallVector<SDValue, 2> Results;
17574 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17575 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17576 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17577 DAG.getConstant(-1, MVT::i8));
17578 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17579 Op.getOperand(4), GenCF.getValue(1));
17580 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17581 Op.getOperand(5), MachinePointerInfo(),
17583 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17584 DAG.getConstant(X86::COND_B, MVT::i8),
17586 Results.push_back(SetCC);
17587 Results.push_back(Store);
17588 return DAG.getMergeValues(Results, dl);
17593 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17594 SelectionDAG &DAG) const {
17595 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17596 MFI->setReturnAddressIsTaken(true);
17598 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17601 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17603 EVT PtrVT = getPointerTy();
17606 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17607 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17608 DAG.getSubtarget().getRegisterInfo());
17609 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17610 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17611 DAG.getNode(ISD::ADD, dl, PtrVT,
17612 FrameAddr, Offset),
17613 MachinePointerInfo(), false, false, false, 0);
17616 // Just load the return address.
17617 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17618 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17619 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17622 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17623 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17624 MFI->setFrameAddressIsTaken(true);
17626 EVT VT = Op.getValueType();
17627 SDLoc dl(Op); // FIXME probably not meaningful
17628 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17629 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17630 DAG.getSubtarget().getRegisterInfo());
17631 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17632 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17633 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17634 "Invalid Frame Register!");
17635 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17637 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17638 MachinePointerInfo(),
17639 false, false, false, 0);
17643 // FIXME? Maybe this could be a TableGen attribute on some registers and
17644 // this table could be generated automatically from RegInfo.
17645 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17647 unsigned Reg = StringSwitch<unsigned>(RegName)
17648 .Case("esp", X86::ESP)
17649 .Case("rsp", X86::RSP)
17653 report_fatal_error("Invalid register name global variable");
17656 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17657 SelectionDAG &DAG) const {
17658 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17659 DAG.getSubtarget().getRegisterInfo());
17660 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17663 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17664 SDValue Chain = Op.getOperand(0);
17665 SDValue Offset = Op.getOperand(1);
17666 SDValue Handler = Op.getOperand(2);
17669 EVT PtrVT = getPointerTy();
17670 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17671 DAG.getSubtarget().getRegisterInfo());
17672 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17673 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17674 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17675 "Invalid Frame Register!");
17676 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17677 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17679 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17680 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17681 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17682 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17684 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17686 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17687 DAG.getRegister(StoreAddrReg, PtrVT));
17690 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17691 SelectionDAG &DAG) const {
17693 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17694 DAG.getVTList(MVT::i32, MVT::Other),
17695 Op.getOperand(0), Op.getOperand(1));
17698 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17699 SelectionDAG &DAG) const {
17701 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17702 Op.getOperand(0), Op.getOperand(1));
17705 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17706 return Op.getOperand(0);
17709 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17710 SelectionDAG &DAG) const {
17711 SDValue Root = Op.getOperand(0);
17712 SDValue Trmp = Op.getOperand(1); // trampoline
17713 SDValue FPtr = Op.getOperand(2); // nested function
17714 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17717 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17718 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17720 if (Subtarget->is64Bit()) {
17721 SDValue OutChains[6];
17723 // Large code-model.
17724 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17725 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17727 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17728 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17730 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17732 // Load the pointer to the nested function into R11.
17733 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17734 SDValue Addr = Trmp;
17735 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17736 Addr, MachinePointerInfo(TrmpAddr),
17739 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17740 DAG.getConstant(2, MVT::i64));
17741 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17742 MachinePointerInfo(TrmpAddr, 2),
17745 // Load the 'nest' parameter value into R10.
17746 // R10 is specified in X86CallingConv.td
17747 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17748 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17749 DAG.getConstant(10, MVT::i64));
17750 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17751 Addr, MachinePointerInfo(TrmpAddr, 10),
17754 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17755 DAG.getConstant(12, MVT::i64));
17756 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17757 MachinePointerInfo(TrmpAddr, 12),
17760 // Jump to the nested function.
17761 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17762 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17763 DAG.getConstant(20, MVT::i64));
17764 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17765 Addr, MachinePointerInfo(TrmpAddr, 20),
17768 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17770 DAG.getConstant(22, MVT::i64));
17771 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17772 MachinePointerInfo(TrmpAddr, 22),
17775 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17777 const Function *Func =
17778 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17779 CallingConv::ID CC = Func->getCallingConv();
17784 llvm_unreachable("Unsupported calling convention");
17785 case CallingConv::C:
17786 case CallingConv::X86_StdCall: {
17787 // Pass 'nest' parameter in ECX.
17788 // Must be kept in sync with X86CallingConv.td
17789 NestReg = X86::ECX;
17791 // Check that ECX wasn't needed by an 'inreg' parameter.
17792 FunctionType *FTy = Func->getFunctionType();
17793 const AttributeSet &Attrs = Func->getAttributes();
17795 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17796 unsigned InRegCount = 0;
17799 for (FunctionType::param_iterator I = FTy->param_begin(),
17800 E = FTy->param_end(); I != E; ++I, ++Idx)
17801 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17802 // FIXME: should only count parameters that are lowered to integers.
17803 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17805 if (InRegCount > 2) {
17806 report_fatal_error("Nest register in use - reduce number of inreg"
17812 case CallingConv::X86_FastCall:
17813 case CallingConv::X86_ThisCall:
17814 case CallingConv::Fast:
17815 // Pass 'nest' parameter in EAX.
17816 // Must be kept in sync with X86CallingConv.td
17817 NestReg = X86::EAX;
17821 SDValue OutChains[4];
17822 SDValue Addr, Disp;
17824 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17825 DAG.getConstant(10, MVT::i32));
17826 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17828 // This is storing the opcode for MOV32ri.
17829 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17830 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17831 OutChains[0] = DAG.getStore(Root, dl,
17832 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17833 Trmp, MachinePointerInfo(TrmpAddr),
17836 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17837 DAG.getConstant(1, MVT::i32));
17838 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17839 MachinePointerInfo(TrmpAddr, 1),
17842 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17844 DAG.getConstant(5, MVT::i32));
17845 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17846 MachinePointerInfo(TrmpAddr, 5),
17849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17850 DAG.getConstant(6, MVT::i32));
17851 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17852 MachinePointerInfo(TrmpAddr, 6),
17855 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17859 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17860 SelectionDAG &DAG) const {
17862 The rounding mode is in bits 11:10 of FPSR, and has the following
17864 00 Round to nearest
17869 FLT_ROUNDS, on the other hand, expects the following:
17876 To perform the conversion, we do:
17877 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17880 MachineFunction &MF = DAG.getMachineFunction();
17881 const TargetMachine &TM = MF.getTarget();
17882 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17883 unsigned StackAlignment = TFI.getStackAlignment();
17884 MVT VT = Op.getSimpleValueType();
17887 // Save FP Control Word to stack slot
17888 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17889 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17891 MachineMemOperand *MMO =
17892 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17893 MachineMemOperand::MOStore, 2, 2);
17895 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17896 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17897 DAG.getVTList(MVT::Other),
17898 Ops, MVT::i16, MMO);
17900 // Load FP Control Word from stack slot
17901 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17902 MachinePointerInfo(), false, false, false, 0);
17904 // Transform as necessary
17906 DAG.getNode(ISD::SRL, DL, MVT::i16,
17907 DAG.getNode(ISD::AND, DL, MVT::i16,
17908 CWD, DAG.getConstant(0x800, MVT::i16)),
17909 DAG.getConstant(11, MVT::i8));
17911 DAG.getNode(ISD::SRL, DL, MVT::i16,
17912 DAG.getNode(ISD::AND, DL, MVT::i16,
17913 CWD, DAG.getConstant(0x400, MVT::i16)),
17914 DAG.getConstant(9, MVT::i8));
17917 DAG.getNode(ISD::AND, DL, MVT::i16,
17918 DAG.getNode(ISD::ADD, DL, MVT::i16,
17919 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17920 DAG.getConstant(1, MVT::i16)),
17921 DAG.getConstant(3, MVT::i16));
17923 return DAG.getNode((VT.getSizeInBits() < 16 ?
17924 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17927 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17928 MVT VT = Op.getSimpleValueType();
17930 unsigned NumBits = VT.getSizeInBits();
17933 Op = Op.getOperand(0);
17934 if (VT == MVT::i8) {
17935 // Zero extend to i32 since there is not an i8 bsr.
17937 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17940 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17941 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17942 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17944 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17947 DAG.getConstant(NumBits+NumBits-1, OpVT),
17948 DAG.getConstant(X86::COND_E, MVT::i8),
17951 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17953 // Finally xor with NumBits-1.
17954 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17957 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17961 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17962 MVT VT = Op.getSimpleValueType();
17964 unsigned NumBits = VT.getSizeInBits();
17967 Op = Op.getOperand(0);
17968 if (VT == MVT::i8) {
17969 // Zero extend to i32 since there is not an i8 bsr.
17971 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17974 // Issue a bsr (scan bits in reverse).
17975 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17976 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17978 // And xor with NumBits-1.
17979 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17982 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17986 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17987 MVT VT = Op.getSimpleValueType();
17988 unsigned NumBits = VT.getSizeInBits();
17990 Op = Op.getOperand(0);
17992 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17993 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17994 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17996 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17999 DAG.getConstant(NumBits, VT),
18000 DAG.getConstant(X86::COND_E, MVT::i8),
18003 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18006 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18007 // ones, and then concatenate the result back.
18008 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18009 MVT VT = Op.getSimpleValueType();
18011 assert(VT.is256BitVector() && VT.isInteger() &&
18012 "Unsupported value type for operation");
18014 unsigned NumElems = VT.getVectorNumElements();
18017 // Extract the LHS vectors
18018 SDValue LHS = Op.getOperand(0);
18019 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18020 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18022 // Extract the RHS vectors
18023 SDValue RHS = Op.getOperand(1);
18024 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18025 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18027 MVT EltVT = VT.getVectorElementType();
18028 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18030 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18031 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18032 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18035 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18036 assert(Op.getSimpleValueType().is256BitVector() &&
18037 Op.getSimpleValueType().isInteger() &&
18038 "Only handle AVX 256-bit vector integer operation");
18039 return Lower256IntArith(Op, DAG);
18042 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18043 assert(Op.getSimpleValueType().is256BitVector() &&
18044 Op.getSimpleValueType().isInteger() &&
18045 "Only handle AVX 256-bit vector integer operation");
18046 return Lower256IntArith(Op, DAG);
18049 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18050 SelectionDAG &DAG) {
18052 MVT VT = Op.getSimpleValueType();
18054 // Decompose 256-bit ops into smaller 128-bit ops.
18055 if (VT.is256BitVector() && !Subtarget->hasInt256())
18056 return Lower256IntArith(Op, DAG);
18058 SDValue A = Op.getOperand(0);
18059 SDValue B = Op.getOperand(1);
18061 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18062 if (VT == MVT::v4i32) {
18063 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18064 "Should not custom lower when pmuldq is available!");
18066 // Extract the odd parts.
18067 static const int UnpackMask[] = { 1, -1, 3, -1 };
18068 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18069 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18071 // Multiply the even parts.
18072 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18073 // Now multiply odd parts.
18074 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18076 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18077 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18079 // Merge the two vectors back together with a shuffle. This expands into 2
18081 static const int ShufMask[] = { 0, 4, 2, 6 };
18082 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18085 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18086 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18088 // Ahi = psrlqi(a, 32);
18089 // Bhi = psrlqi(b, 32);
18091 // AloBlo = pmuludq(a, b);
18092 // AloBhi = pmuludq(a, Bhi);
18093 // AhiBlo = pmuludq(Ahi, b);
18095 // AloBhi = psllqi(AloBhi, 32);
18096 // AhiBlo = psllqi(AhiBlo, 32);
18097 // return AloBlo + AloBhi + AhiBlo;
18099 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18100 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18102 // Bit cast to 32-bit vectors for MULUDQ
18103 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18104 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18105 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18106 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18107 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18108 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18110 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18111 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18112 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18114 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18115 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18117 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18118 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18121 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18122 assert(Subtarget->isTargetWin64() && "Unexpected target");
18123 EVT VT = Op.getValueType();
18124 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18125 "Unexpected return type for lowering");
18129 switch (Op->getOpcode()) {
18130 default: llvm_unreachable("Unexpected request for libcall!");
18131 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18132 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18133 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18134 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18135 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18136 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18140 SDValue InChain = DAG.getEntryNode();
18142 TargetLowering::ArgListTy Args;
18143 TargetLowering::ArgListEntry Entry;
18144 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18145 EVT ArgVT = Op->getOperand(i).getValueType();
18146 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18147 "Unexpected argument type for lowering");
18148 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18149 Entry.Node = StackPtr;
18150 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18152 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18153 Entry.Ty = PointerType::get(ArgTy,0);
18154 Entry.isSExt = false;
18155 Entry.isZExt = false;
18156 Args.push_back(Entry);
18159 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18162 TargetLowering::CallLoweringInfo CLI(DAG);
18163 CLI.setDebugLoc(dl).setChain(InChain)
18164 .setCallee(getLibcallCallingConv(LC),
18165 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18166 Callee, std::move(Args), 0)
18167 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18169 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18170 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18173 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18174 SelectionDAG &DAG) {
18175 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18176 EVT VT = Op0.getValueType();
18179 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18180 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18182 // PMULxD operations multiply each even value (starting at 0) of LHS with
18183 // the related value of RHS and produce a widen result.
18184 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18185 // => <2 x i64> <ae|cg>
18187 // In other word, to have all the results, we need to perform two PMULxD:
18188 // 1. one with the even values.
18189 // 2. one with the odd values.
18190 // To achieve #2, with need to place the odd values at an even position.
18192 // Place the odd value at an even position (basically, shift all values 1
18193 // step to the left):
18194 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18195 // <a|b|c|d> => <b|undef|d|undef>
18196 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18197 // <e|f|g|h> => <f|undef|h|undef>
18198 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18200 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18202 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18203 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18205 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18206 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18207 // => <2 x i64> <ae|cg>
18208 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18209 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18210 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18211 // => <2 x i64> <bf|dh>
18212 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18213 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18215 // Shuffle it back into the right order.
18216 SDValue Highs, Lows;
18217 if (VT == MVT::v8i32) {
18218 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18219 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18220 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18221 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18223 const int HighMask[] = {1, 5, 3, 7};
18224 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18225 const int LowMask[] = {0, 4, 2, 6};
18226 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18229 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18230 // unsigned multiply.
18231 if (IsSigned && !Subtarget->hasSSE41()) {
18233 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18234 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18235 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18236 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18237 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18239 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18240 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18243 // The first result of MUL_LOHI is actually the low value, followed by the
18245 SDValue Ops[] = {Lows, Highs};
18246 return DAG.getMergeValues(Ops, dl);
18249 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18250 const X86Subtarget *Subtarget) {
18251 MVT VT = Op.getSimpleValueType();
18253 SDValue R = Op.getOperand(0);
18254 SDValue Amt = Op.getOperand(1);
18256 // Optimize shl/srl/sra with constant shift amount.
18257 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18258 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18259 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18261 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18262 (Subtarget->hasInt256() &&
18263 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18264 (Subtarget->hasAVX512() &&
18265 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18266 if (Op.getOpcode() == ISD::SHL)
18267 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18269 if (Op.getOpcode() == ISD::SRL)
18270 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18272 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18273 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18277 if (VT == MVT::v16i8) {
18278 if (Op.getOpcode() == ISD::SHL) {
18279 // Make a large shift.
18280 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18281 MVT::v8i16, R, ShiftAmt,
18283 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18284 // Zero out the rightmost bits.
18285 SmallVector<SDValue, 16> V(16,
18286 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18288 return DAG.getNode(ISD::AND, dl, VT, SHL,
18289 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18291 if (Op.getOpcode() == ISD::SRL) {
18292 // Make a large shift.
18293 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18294 MVT::v8i16, R, ShiftAmt,
18296 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18297 // Zero out the leftmost bits.
18298 SmallVector<SDValue, 16> V(16,
18299 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18301 return DAG.getNode(ISD::AND, dl, VT, SRL,
18302 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18304 if (Op.getOpcode() == ISD::SRA) {
18305 if (ShiftAmt == 7) {
18306 // R s>> 7 === R s< 0
18307 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18308 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18311 // R s>> a === ((R u>> a) ^ m) - m
18312 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18313 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18315 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18316 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18317 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18320 llvm_unreachable("Unknown shift opcode.");
18323 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18324 if (Op.getOpcode() == ISD::SHL) {
18325 // Make a large shift.
18326 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18327 MVT::v16i16, R, ShiftAmt,
18329 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18330 // Zero out the rightmost bits.
18331 SmallVector<SDValue, 32> V(32,
18332 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18334 return DAG.getNode(ISD::AND, dl, VT, SHL,
18335 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18337 if (Op.getOpcode() == ISD::SRL) {
18338 // Make a large shift.
18339 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18340 MVT::v16i16, R, ShiftAmt,
18342 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18343 // Zero out the leftmost bits.
18344 SmallVector<SDValue, 32> V(32,
18345 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18347 return DAG.getNode(ISD::AND, dl, VT, SRL,
18348 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18350 if (Op.getOpcode() == ISD::SRA) {
18351 if (ShiftAmt == 7) {
18352 // R s>> 7 === R s< 0
18353 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18354 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18357 // R s>> a === ((R u>> a) ^ m) - m
18358 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18359 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18361 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18362 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18363 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18366 llvm_unreachable("Unknown shift opcode.");
18371 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18372 if (!Subtarget->is64Bit() &&
18373 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18374 Amt.getOpcode() == ISD::BITCAST &&
18375 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18376 Amt = Amt.getOperand(0);
18377 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18378 VT.getVectorNumElements();
18379 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18380 uint64_t ShiftAmt = 0;
18381 for (unsigned i = 0; i != Ratio; ++i) {
18382 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18386 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18388 // Check remaining shift amounts.
18389 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18390 uint64_t ShAmt = 0;
18391 for (unsigned j = 0; j != Ratio; ++j) {
18392 ConstantSDNode *C =
18393 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18397 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18399 if (ShAmt != ShiftAmt)
18402 switch (Op.getOpcode()) {
18404 llvm_unreachable("Unknown shift opcode!");
18406 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18409 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18412 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18420 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18421 const X86Subtarget* Subtarget) {
18422 MVT VT = Op.getSimpleValueType();
18424 SDValue R = Op.getOperand(0);
18425 SDValue Amt = Op.getOperand(1);
18427 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18428 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18429 (Subtarget->hasInt256() &&
18430 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18431 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18432 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18434 EVT EltVT = VT.getVectorElementType();
18436 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18437 unsigned NumElts = VT.getVectorNumElements();
18439 for (i = 0; i != NumElts; ++i) {
18440 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18444 for (j = i; j != NumElts; ++j) {
18445 SDValue Arg = Amt.getOperand(j);
18446 if (Arg.getOpcode() == ISD::UNDEF) continue;
18447 if (Arg != Amt.getOperand(i))
18450 if (i != NumElts && j == NumElts)
18451 BaseShAmt = Amt.getOperand(i);
18453 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18454 Amt = Amt.getOperand(0);
18455 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18456 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18457 SDValue InVec = Amt.getOperand(0);
18458 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18459 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18461 for (; i != NumElts; ++i) {
18462 SDValue Arg = InVec.getOperand(i);
18463 if (Arg.getOpcode() == ISD::UNDEF) continue;
18467 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18468 if (ConstantSDNode *C =
18469 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18470 unsigned SplatIdx =
18471 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18472 if (C->getZExtValue() == SplatIdx)
18473 BaseShAmt = InVec.getOperand(1);
18476 if (!BaseShAmt.getNode())
18477 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18478 DAG.getIntPtrConstant(0));
18482 if (BaseShAmt.getNode()) {
18483 if (EltVT.bitsGT(MVT::i32))
18484 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18485 else if (EltVT.bitsLT(MVT::i32))
18486 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18488 switch (Op.getOpcode()) {
18490 llvm_unreachable("Unknown shift opcode!");
18492 switch (VT.SimpleTy) {
18493 default: return SDValue();
18502 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18505 switch (VT.SimpleTy) {
18506 default: return SDValue();
18513 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18516 switch (VT.SimpleTy) {
18517 default: return SDValue();
18526 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18532 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18533 if (!Subtarget->is64Bit() &&
18534 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18535 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18536 Amt.getOpcode() == ISD::BITCAST &&
18537 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18538 Amt = Amt.getOperand(0);
18539 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18540 VT.getVectorNumElements();
18541 std::vector<SDValue> Vals(Ratio);
18542 for (unsigned i = 0; i != Ratio; ++i)
18543 Vals[i] = Amt.getOperand(i);
18544 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18545 for (unsigned j = 0; j != Ratio; ++j)
18546 if (Vals[j] != Amt.getOperand(i + j))
18549 switch (Op.getOpcode()) {
18551 llvm_unreachable("Unknown shift opcode!");
18553 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18555 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18557 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18564 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18565 SelectionDAG &DAG) {
18566 MVT VT = Op.getSimpleValueType();
18568 SDValue R = Op.getOperand(0);
18569 SDValue Amt = Op.getOperand(1);
18572 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18573 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18575 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18579 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18583 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18585 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18586 if (Subtarget->hasInt256()) {
18587 if (Op.getOpcode() == ISD::SRL &&
18588 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18589 VT == MVT::v4i64 || VT == MVT::v8i32))
18591 if (Op.getOpcode() == ISD::SHL &&
18592 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18593 VT == MVT::v4i64 || VT == MVT::v8i32))
18595 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18599 // If possible, lower this packed shift into a vector multiply instead of
18600 // expanding it into a sequence of scalar shifts.
18601 // Do this only if the vector shift count is a constant build_vector.
18602 if (Op.getOpcode() == ISD::SHL &&
18603 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18604 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18605 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18606 SmallVector<SDValue, 8> Elts;
18607 EVT SVT = VT.getScalarType();
18608 unsigned SVTBits = SVT.getSizeInBits();
18609 const APInt &One = APInt(SVTBits, 1);
18610 unsigned NumElems = VT.getVectorNumElements();
18612 for (unsigned i=0; i !=NumElems; ++i) {
18613 SDValue Op = Amt->getOperand(i);
18614 if (Op->getOpcode() == ISD::UNDEF) {
18615 Elts.push_back(Op);
18619 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18620 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18621 uint64_t ShAmt = C.getZExtValue();
18622 if (ShAmt >= SVTBits) {
18623 Elts.push_back(DAG.getUNDEF(SVT));
18626 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18628 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18629 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18632 // Lower SHL with variable shift amount.
18633 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18634 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18636 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18637 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18638 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18639 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18642 // If possible, lower this shift as a sequence of two shifts by
18643 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18645 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18647 // Could be rewritten as:
18648 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18650 // The advantage is that the two shifts from the example would be
18651 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18652 // the vector shift into four scalar shifts plus four pairs of vector
18654 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18655 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18656 unsigned TargetOpcode = X86ISD::MOVSS;
18657 bool CanBeSimplified;
18658 // The splat value for the first packed shift (the 'X' from the example).
18659 SDValue Amt1 = Amt->getOperand(0);
18660 // The splat value for the second packed shift (the 'Y' from the example).
18661 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18662 Amt->getOperand(2);
18664 // See if it is possible to replace this node with a sequence of
18665 // two shifts followed by a MOVSS/MOVSD
18666 if (VT == MVT::v4i32) {
18667 // Check if it is legal to use a MOVSS.
18668 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18669 Amt2 == Amt->getOperand(3);
18670 if (!CanBeSimplified) {
18671 // Otherwise, check if we can still simplify this node using a MOVSD.
18672 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18673 Amt->getOperand(2) == Amt->getOperand(3);
18674 TargetOpcode = X86ISD::MOVSD;
18675 Amt2 = Amt->getOperand(2);
18678 // Do similar checks for the case where the machine value type
18680 CanBeSimplified = Amt1 == Amt->getOperand(1);
18681 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18682 CanBeSimplified = Amt2 == Amt->getOperand(i);
18684 if (!CanBeSimplified) {
18685 TargetOpcode = X86ISD::MOVSD;
18686 CanBeSimplified = true;
18687 Amt2 = Amt->getOperand(4);
18688 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18689 CanBeSimplified = Amt1 == Amt->getOperand(i);
18690 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18691 CanBeSimplified = Amt2 == Amt->getOperand(j);
18695 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18696 isa<ConstantSDNode>(Amt2)) {
18697 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18698 EVT CastVT = MVT::v4i32;
18700 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18701 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18703 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18704 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18705 if (TargetOpcode == X86ISD::MOVSD)
18706 CastVT = MVT::v2i64;
18707 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18708 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18709 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18711 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18715 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18716 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18719 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18720 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18722 // Turn 'a' into a mask suitable for VSELECT
18723 SDValue VSelM = DAG.getConstant(0x80, VT);
18724 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18725 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18727 SDValue CM1 = DAG.getConstant(0x0f, VT);
18728 SDValue CM2 = DAG.getConstant(0x3f, VT);
18730 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18731 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18732 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18733 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18734 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18737 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18738 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18739 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18741 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18742 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18743 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18744 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18745 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18748 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18749 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18750 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18752 // return VSELECT(r, r+r, a);
18753 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18754 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18758 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18759 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18760 // solution better.
18761 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18762 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18764 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18765 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18766 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18767 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18768 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18771 // Decompose 256-bit shifts into smaller 128-bit shifts.
18772 if (VT.is256BitVector()) {
18773 unsigned NumElems = VT.getVectorNumElements();
18774 MVT EltVT = VT.getVectorElementType();
18775 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18777 // Extract the two vectors
18778 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18779 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18781 // Recreate the shift amount vectors
18782 SDValue Amt1, Amt2;
18783 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18784 // Constant shift amount
18785 SmallVector<SDValue, 4> Amt1Csts;
18786 SmallVector<SDValue, 4> Amt2Csts;
18787 for (unsigned i = 0; i != NumElems/2; ++i)
18788 Amt1Csts.push_back(Amt->getOperand(i));
18789 for (unsigned i = NumElems/2; i != NumElems; ++i)
18790 Amt2Csts.push_back(Amt->getOperand(i));
18792 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18793 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18795 // Variable shift amount
18796 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18797 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18800 // Issue new vector shifts for the smaller types
18801 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18802 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18804 // Concatenate the result back
18805 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18811 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18812 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18813 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18814 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18815 // has only one use.
18816 SDNode *N = Op.getNode();
18817 SDValue LHS = N->getOperand(0);
18818 SDValue RHS = N->getOperand(1);
18819 unsigned BaseOp = 0;
18822 switch (Op.getOpcode()) {
18823 default: llvm_unreachable("Unknown ovf instruction!");
18825 // A subtract of one will be selected as a INC. Note that INC doesn't
18826 // set CF, so we can't do this for UADDO.
18827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18829 BaseOp = X86ISD::INC;
18830 Cond = X86::COND_O;
18833 BaseOp = X86ISD::ADD;
18834 Cond = X86::COND_O;
18837 BaseOp = X86ISD::ADD;
18838 Cond = X86::COND_B;
18841 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18842 // set CF, so we can't do this for USUBO.
18843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18845 BaseOp = X86ISD::DEC;
18846 Cond = X86::COND_O;
18849 BaseOp = X86ISD::SUB;
18850 Cond = X86::COND_O;
18853 BaseOp = X86ISD::SUB;
18854 Cond = X86::COND_B;
18857 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18858 Cond = X86::COND_O;
18860 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18861 if (N->getValueType(0) == MVT::i8) {
18862 BaseOp = X86ISD::UMUL8;
18863 Cond = X86::COND_O;
18866 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18868 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18871 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18872 DAG.getConstant(X86::COND_O, MVT::i32),
18873 SDValue(Sum.getNode(), 2));
18875 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18879 // Also sets EFLAGS.
18880 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18881 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18884 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18885 DAG.getConstant(Cond, MVT::i32),
18886 SDValue(Sum.getNode(), 1));
18888 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18891 // Sign extension of the low part of vector elements. This may be used either
18892 // when sign extend instructions are not available or if the vector element
18893 // sizes already match the sign-extended size. If the vector elements are in
18894 // their pre-extended size and sign extend instructions are available, that will
18895 // be handled by LowerSIGN_EXTEND.
18896 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18897 SelectionDAG &DAG) const {
18899 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18900 MVT VT = Op.getSimpleValueType();
18902 if (!Subtarget->hasSSE2() || !VT.isVector())
18905 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18906 ExtraVT.getScalarType().getSizeInBits();
18908 switch (VT.SimpleTy) {
18909 default: return SDValue();
18912 if (!Subtarget->hasFp256())
18914 if (!Subtarget->hasInt256()) {
18915 // needs to be split
18916 unsigned NumElems = VT.getVectorNumElements();
18918 // Extract the LHS vectors
18919 SDValue LHS = Op.getOperand(0);
18920 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18921 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18923 MVT EltVT = VT.getVectorElementType();
18924 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18926 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18927 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18928 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18930 SDValue Extra = DAG.getValueType(ExtraVT);
18932 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18933 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18940 SDValue Op0 = Op.getOperand(0);
18942 // This is a sign extension of some low part of vector elements without
18943 // changing the size of the vector elements themselves:
18944 // Shift-Left + Shift-Right-Algebraic.
18945 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18947 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18953 /// Returns true if the operand type is exactly twice the native width, and
18954 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18955 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18956 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18957 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18958 const X86Subtarget &Subtarget =
18959 getTargetMachine().getSubtarget<X86Subtarget>();
18960 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18963 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18964 else if (OpWidth == 128)
18965 return Subtarget.hasCmpxchg16b();
18970 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18971 return needsCmpXchgNb(SI->getValueOperand()->getType());
18974 // Note: this turns large loads into lock cmpxchg8b/16b.
18975 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18976 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18977 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18978 return needsCmpXchgNb(PTy->getElementType());
18981 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18982 const X86Subtarget &Subtarget =
18983 getTargetMachine().getSubtarget<X86Subtarget>();
18984 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18985 const Type *MemType = AI->getType();
18987 // If the operand is too big, we must see if cmpxchg8/16b is available
18988 // and default to library calls otherwise.
18989 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18990 return needsCmpXchgNb(MemType);
18992 AtomicRMWInst::BinOp Op = AI->getOperation();
18995 llvm_unreachable("Unknown atomic operation");
18996 case AtomicRMWInst::Xchg:
18997 case AtomicRMWInst::Add:
18998 case AtomicRMWInst::Sub:
18999 // It's better to use xadd, xsub or xchg for these in all cases.
19001 case AtomicRMWInst::Or:
19002 case AtomicRMWInst::And:
19003 case AtomicRMWInst::Xor:
19004 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19005 // prefix to a normal instruction for these operations.
19006 return !AI->use_empty();
19007 case AtomicRMWInst::Nand:
19008 case AtomicRMWInst::Max:
19009 case AtomicRMWInst::Min:
19010 case AtomicRMWInst::UMax:
19011 case AtomicRMWInst::UMin:
19012 // These always require a non-trivial set of data operations on x86. We must
19013 // use a cmpxchg loop.
19018 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19019 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19020 // no-sse2). There isn't any reason to disable it if the target processor
19022 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19026 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19027 const X86Subtarget &Subtarget =
19028 getTargetMachine().getSubtarget<X86Subtarget>();
19029 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19030 const Type *MemType = AI->getType();
19031 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19032 // there is no benefit in turning such RMWs into loads, and it is actually
19033 // harmful as it introduces a mfence.
19034 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19037 auto Builder = IRBuilder<>(AI);
19038 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19039 auto SynchScope = AI->getSynchScope();
19040 // We must restrict the ordering to avoid generating loads with Release or
19041 // ReleaseAcquire orderings.
19042 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19043 auto Ptr = AI->getPointerOperand();
19045 // Before the load we need a fence. Here is an example lifted from
19046 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19049 // x.store(1, relaxed);
19050 // r1 = y.fetch_add(0, release);
19052 // y.fetch_add(42, acquire);
19053 // r2 = x.load(relaxed);
19054 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19055 // lowered to just a load without a fence. A mfence flushes the store buffer,
19056 // making the optimization clearly correct.
19057 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19058 // otherwise, we might be able to be more agressive on relaxed idempotent
19059 // rmw. In practice, they do not look useful, so we don't try to be
19060 // especially clever.
19061 if (SynchScope == SingleThread) {
19062 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19063 // the IR level, so we must wrap it in an intrinsic.
19065 } else if (hasMFENCE(Subtarget)) {
19066 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19067 Intrinsic::x86_sse2_mfence);
19068 Builder.CreateCall(MFence);
19070 // FIXME: it might make sense to use a locked operation here but on a
19071 // different cache-line to prevent cache-line bouncing. In practice it
19072 // is probably a small win, and x86 processors without mfence are rare
19073 // enough that we do not bother.
19077 // Finally we can emit the atomic load.
19078 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19079 AI->getType()->getPrimitiveSizeInBits());
19080 Loaded->setAtomic(Order, SynchScope);
19081 AI->replaceAllUsesWith(Loaded);
19082 AI->eraseFromParent();
19086 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19087 SelectionDAG &DAG) {
19089 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19090 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19091 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19092 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19094 // The only fence that needs an instruction is a sequentially-consistent
19095 // cross-thread fence.
19096 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19097 if (hasMFENCE(*Subtarget))
19098 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19100 SDValue Chain = Op.getOperand(0);
19101 SDValue Zero = DAG.getConstant(0, MVT::i32);
19103 DAG.getRegister(X86::ESP, MVT::i32), // Base
19104 DAG.getTargetConstant(1, MVT::i8), // Scale
19105 DAG.getRegister(0, MVT::i32), // Index
19106 DAG.getTargetConstant(0, MVT::i32), // Disp
19107 DAG.getRegister(0, MVT::i32), // Segment.
19111 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19112 return SDValue(Res, 0);
19115 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19116 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19119 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19120 SelectionDAG &DAG) {
19121 MVT T = Op.getSimpleValueType();
19125 switch(T.SimpleTy) {
19126 default: llvm_unreachable("Invalid value type!");
19127 case MVT::i8: Reg = X86::AL; size = 1; break;
19128 case MVT::i16: Reg = X86::AX; size = 2; break;
19129 case MVT::i32: Reg = X86::EAX; size = 4; break;
19131 assert(Subtarget->is64Bit() && "Node not type legal!");
19132 Reg = X86::RAX; size = 8;
19135 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19136 Op.getOperand(2), SDValue());
19137 SDValue Ops[] = { cpIn.getValue(0),
19140 DAG.getTargetConstant(size, MVT::i8),
19141 cpIn.getValue(1) };
19142 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19143 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19144 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19148 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19149 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19150 MVT::i32, cpOut.getValue(2));
19151 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19152 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19154 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19155 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19156 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19160 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19161 SelectionDAG &DAG) {
19162 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19163 MVT DstVT = Op.getSimpleValueType();
19165 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19166 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19167 if (DstVT != MVT::f64)
19168 // This conversion needs to be expanded.
19171 SDValue InVec = Op->getOperand(0);
19173 unsigned NumElts = SrcVT.getVectorNumElements();
19174 EVT SVT = SrcVT.getVectorElementType();
19176 // Widen the vector in input in the case of MVT::v2i32.
19177 // Example: from MVT::v2i32 to MVT::v4i32.
19178 SmallVector<SDValue, 16> Elts;
19179 for (unsigned i = 0, e = NumElts; i != e; ++i)
19180 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19181 DAG.getIntPtrConstant(i)));
19183 // Explicitly mark the extra elements as Undef.
19184 SDValue Undef = DAG.getUNDEF(SVT);
19185 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19186 Elts.push_back(Undef);
19188 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19189 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19190 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19191 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19192 DAG.getIntPtrConstant(0));
19195 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19196 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19197 assert((DstVT == MVT::i64 ||
19198 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19199 "Unexpected custom BITCAST");
19200 // i64 <=> MMX conversions are Legal.
19201 if (SrcVT==MVT::i64 && DstVT.isVector())
19203 if (DstVT==MVT::i64 && SrcVT.isVector())
19205 // MMX <=> MMX conversions are Legal.
19206 if (SrcVT.isVector() && DstVT.isVector())
19208 // All other conversions need to be expanded.
19212 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19213 SDNode *Node = Op.getNode();
19215 EVT T = Node->getValueType(0);
19216 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19217 DAG.getConstant(0, T), Node->getOperand(2));
19218 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19219 cast<AtomicSDNode>(Node)->getMemoryVT(),
19220 Node->getOperand(0),
19221 Node->getOperand(1), negOp,
19222 cast<AtomicSDNode>(Node)->getMemOperand(),
19223 cast<AtomicSDNode>(Node)->getOrdering(),
19224 cast<AtomicSDNode>(Node)->getSynchScope());
19227 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19228 SDNode *Node = Op.getNode();
19230 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19232 // Convert seq_cst store -> xchg
19233 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19234 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19235 // (The only way to get a 16-byte store is cmpxchg16b)
19236 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19237 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19238 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19239 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19240 cast<AtomicSDNode>(Node)->getMemoryVT(),
19241 Node->getOperand(0),
19242 Node->getOperand(1), Node->getOperand(2),
19243 cast<AtomicSDNode>(Node)->getMemOperand(),
19244 cast<AtomicSDNode>(Node)->getOrdering(),
19245 cast<AtomicSDNode>(Node)->getSynchScope());
19246 return Swap.getValue(1);
19248 // Other atomic stores have a simple pattern.
19252 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19253 EVT VT = Op.getNode()->getSimpleValueType(0);
19255 // Let legalize expand this if it isn't a legal type yet.
19256 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19259 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19262 bool ExtraOp = false;
19263 switch (Op.getOpcode()) {
19264 default: llvm_unreachable("Invalid code");
19265 case ISD::ADDC: Opc = X86ISD::ADD; break;
19266 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19267 case ISD::SUBC: Opc = X86ISD::SUB; break;
19268 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19272 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19274 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19275 Op.getOperand(1), Op.getOperand(2));
19278 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19279 SelectionDAG &DAG) {
19280 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19282 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19283 // which returns the values as { float, float } (in XMM0) or
19284 // { double, double } (which is returned in XMM0, XMM1).
19286 SDValue Arg = Op.getOperand(0);
19287 EVT ArgVT = Arg.getValueType();
19288 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19290 TargetLowering::ArgListTy Args;
19291 TargetLowering::ArgListEntry Entry;
19295 Entry.isSExt = false;
19296 Entry.isZExt = false;
19297 Args.push_back(Entry);
19299 bool isF64 = ArgVT == MVT::f64;
19300 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19301 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19302 // the results are returned via SRet in memory.
19303 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19305 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19307 Type *RetTy = isF64
19308 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19309 : (Type*)VectorType::get(ArgTy, 4);
19311 TargetLowering::CallLoweringInfo CLI(DAG);
19312 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19313 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19315 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19318 // Returned in xmm0 and xmm1.
19319 return CallResult.first;
19321 // Returned in bits 0:31 and 32:64 xmm0.
19322 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19323 CallResult.first, DAG.getIntPtrConstant(0));
19324 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19325 CallResult.first, DAG.getIntPtrConstant(1));
19326 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19327 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19330 /// LowerOperation - Provide custom lowering hooks for some operations.
19332 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19333 switch (Op.getOpcode()) {
19334 default: llvm_unreachable("Should not custom lower this!");
19335 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19336 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19337 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19338 return LowerCMP_SWAP(Op, Subtarget, DAG);
19339 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19340 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19341 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19342 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19343 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19344 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19345 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19346 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19347 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19348 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19349 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19350 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19351 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19352 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19353 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19354 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19355 case ISD::SHL_PARTS:
19356 case ISD::SRA_PARTS:
19357 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19358 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19359 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19360 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19361 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19362 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19363 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19364 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19365 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19366 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19367 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19369 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19370 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19371 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19372 case ISD::SETCC: return LowerSETCC(Op, DAG);
19373 case ISD::SELECT: return LowerSELECT(Op, DAG);
19374 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19375 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19376 case ISD::VASTART: return LowerVASTART(Op, DAG);
19377 case ISD::VAARG: return LowerVAARG(Op, DAG);
19378 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19379 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19380 case ISD::INTRINSIC_VOID:
19381 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19382 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19383 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19384 case ISD::FRAME_TO_ARGS_OFFSET:
19385 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19386 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19387 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19388 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19389 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19390 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19391 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19392 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19393 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19394 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19395 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19396 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19397 case ISD::UMUL_LOHI:
19398 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19401 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19407 case ISD::UMULO: return LowerXALUO(Op, DAG);
19408 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19409 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19413 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19414 case ISD::ADD: return LowerADD(Op, DAG);
19415 case ISD::SUB: return LowerSUB(Op, DAG);
19416 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19420 /// ReplaceNodeResults - Replace a node with an illegal result type
19421 /// with a new node built out of custom code.
19422 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19423 SmallVectorImpl<SDValue>&Results,
19424 SelectionDAG &DAG) const {
19426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19427 switch (N->getOpcode()) {
19429 llvm_unreachable("Do not know how to custom type legalize this operation!");
19430 case ISD::SIGN_EXTEND_INREG:
19435 // We don't want to expand or promote these.
19442 case ISD::UDIVREM: {
19443 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19444 Results.push_back(V);
19447 case ISD::FP_TO_SINT:
19448 case ISD::FP_TO_UINT: {
19449 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19451 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19454 std::pair<SDValue,SDValue> Vals =
19455 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19456 SDValue FIST = Vals.first, StackSlot = Vals.second;
19457 if (FIST.getNode()) {
19458 EVT VT = N->getValueType(0);
19459 // Return a load from the stack slot.
19460 if (StackSlot.getNode())
19461 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19462 MachinePointerInfo(),
19463 false, false, false, 0));
19465 Results.push_back(FIST);
19469 case ISD::UINT_TO_FP: {
19470 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19471 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19472 N->getValueType(0) != MVT::v2f32)
19474 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19476 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19478 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19479 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19480 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19481 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19482 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19483 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19486 case ISD::FP_ROUND: {
19487 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19489 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19490 Results.push_back(V);
19493 case ISD::INTRINSIC_W_CHAIN: {
19494 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19496 default : llvm_unreachable("Do not know how to custom type "
19497 "legalize this intrinsic operation!");
19498 case Intrinsic::x86_rdtsc:
19499 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19501 case Intrinsic::x86_rdtscp:
19502 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19504 case Intrinsic::x86_rdpmc:
19505 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19508 case ISD::READCYCLECOUNTER: {
19509 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19512 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19513 EVT T = N->getValueType(0);
19514 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19515 bool Regs64bit = T == MVT::i128;
19516 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19517 SDValue cpInL, cpInH;
19518 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19519 DAG.getConstant(0, HalfT));
19520 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19521 DAG.getConstant(1, HalfT));
19522 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19523 Regs64bit ? X86::RAX : X86::EAX,
19525 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19526 Regs64bit ? X86::RDX : X86::EDX,
19527 cpInH, cpInL.getValue(1));
19528 SDValue swapInL, swapInH;
19529 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19530 DAG.getConstant(0, HalfT));
19531 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19532 DAG.getConstant(1, HalfT));
19533 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19534 Regs64bit ? X86::RBX : X86::EBX,
19535 swapInL, cpInH.getValue(1));
19536 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19537 Regs64bit ? X86::RCX : X86::ECX,
19538 swapInH, swapInL.getValue(1));
19539 SDValue Ops[] = { swapInH.getValue(0),
19541 swapInH.getValue(1) };
19542 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19543 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19544 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19545 X86ISD::LCMPXCHG8_DAG;
19546 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19547 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19548 Regs64bit ? X86::RAX : X86::EAX,
19549 HalfT, Result.getValue(1));
19550 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19551 Regs64bit ? X86::RDX : X86::EDX,
19552 HalfT, cpOutL.getValue(2));
19553 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19555 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19556 MVT::i32, cpOutH.getValue(2));
19558 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19559 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19560 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19562 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19563 Results.push_back(Success);
19564 Results.push_back(EFLAGS.getValue(1));
19567 case ISD::ATOMIC_SWAP:
19568 case ISD::ATOMIC_LOAD_ADD:
19569 case ISD::ATOMIC_LOAD_SUB:
19570 case ISD::ATOMIC_LOAD_AND:
19571 case ISD::ATOMIC_LOAD_OR:
19572 case ISD::ATOMIC_LOAD_XOR:
19573 case ISD::ATOMIC_LOAD_NAND:
19574 case ISD::ATOMIC_LOAD_MIN:
19575 case ISD::ATOMIC_LOAD_MAX:
19576 case ISD::ATOMIC_LOAD_UMIN:
19577 case ISD::ATOMIC_LOAD_UMAX:
19578 case ISD::ATOMIC_LOAD: {
19579 // Delegate to generic TypeLegalization. Situations we can really handle
19580 // should have already been dealt with by AtomicExpandPass.cpp.
19583 case ISD::BITCAST: {
19584 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19585 EVT DstVT = N->getValueType(0);
19586 EVT SrcVT = N->getOperand(0)->getValueType(0);
19588 if (SrcVT != MVT::f64 ||
19589 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19592 unsigned NumElts = DstVT.getVectorNumElements();
19593 EVT SVT = DstVT.getVectorElementType();
19594 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19595 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19596 MVT::v2f64, N->getOperand(0));
19597 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19599 if (ExperimentalVectorWideningLegalization) {
19600 // If we are legalizing vectors by widening, we already have the desired
19601 // legal vector type, just return it.
19602 Results.push_back(ToVecInt);
19606 SmallVector<SDValue, 8> Elts;
19607 for (unsigned i = 0, e = NumElts; i != e; ++i)
19608 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19609 ToVecInt, DAG.getIntPtrConstant(i)));
19611 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19616 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19618 default: return nullptr;
19619 case X86ISD::BSF: return "X86ISD::BSF";
19620 case X86ISD::BSR: return "X86ISD::BSR";
19621 case X86ISD::SHLD: return "X86ISD::SHLD";
19622 case X86ISD::SHRD: return "X86ISD::SHRD";
19623 case X86ISD::FAND: return "X86ISD::FAND";
19624 case X86ISD::FANDN: return "X86ISD::FANDN";
19625 case X86ISD::FOR: return "X86ISD::FOR";
19626 case X86ISD::FXOR: return "X86ISD::FXOR";
19627 case X86ISD::FSRL: return "X86ISD::FSRL";
19628 case X86ISD::FILD: return "X86ISD::FILD";
19629 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19630 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19631 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19632 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19633 case X86ISD::FLD: return "X86ISD::FLD";
19634 case X86ISD::FST: return "X86ISD::FST";
19635 case X86ISD::CALL: return "X86ISD::CALL";
19636 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19637 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19638 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19639 case X86ISD::BT: return "X86ISD::BT";
19640 case X86ISD::CMP: return "X86ISD::CMP";
19641 case X86ISD::COMI: return "X86ISD::COMI";
19642 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19643 case X86ISD::CMPM: return "X86ISD::CMPM";
19644 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19645 case X86ISD::SETCC: return "X86ISD::SETCC";
19646 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19647 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19648 case X86ISD::CMOV: return "X86ISD::CMOV";
19649 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19650 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19651 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19652 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19653 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19654 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19655 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19656 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19657 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19658 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19659 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19660 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19661 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19662 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19663 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19664 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19665 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19666 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19667 case X86ISD::HADD: return "X86ISD::HADD";
19668 case X86ISD::HSUB: return "X86ISD::HSUB";
19669 case X86ISD::FHADD: return "X86ISD::FHADD";
19670 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19671 case X86ISD::UMAX: return "X86ISD::UMAX";
19672 case X86ISD::UMIN: return "X86ISD::UMIN";
19673 case X86ISD::SMAX: return "X86ISD::SMAX";
19674 case X86ISD::SMIN: return "X86ISD::SMIN";
19675 case X86ISD::FMAX: return "X86ISD::FMAX";
19676 case X86ISD::FMIN: return "X86ISD::FMIN";
19677 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19678 case X86ISD::FMINC: return "X86ISD::FMINC";
19679 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19680 case X86ISD::FRCP: return "X86ISD::FRCP";
19681 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19682 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19683 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19684 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19685 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19686 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19687 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19688 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19689 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19690 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19691 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19692 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19693 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19694 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19695 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19696 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19697 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19698 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19699 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19700 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19701 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19702 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19703 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19704 case X86ISD::VSHL: return "X86ISD::VSHL";
19705 case X86ISD::VSRL: return "X86ISD::VSRL";
19706 case X86ISD::VSRA: return "X86ISD::VSRA";
19707 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19708 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19709 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19710 case X86ISD::CMPP: return "X86ISD::CMPP";
19711 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19712 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19713 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19714 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19715 case X86ISD::ADD: return "X86ISD::ADD";
19716 case X86ISD::SUB: return "X86ISD::SUB";
19717 case X86ISD::ADC: return "X86ISD::ADC";
19718 case X86ISD::SBB: return "X86ISD::SBB";
19719 case X86ISD::SMUL: return "X86ISD::SMUL";
19720 case X86ISD::UMUL: return "X86ISD::UMUL";
19721 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19722 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19723 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19724 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19725 case X86ISD::INC: return "X86ISD::INC";
19726 case X86ISD::DEC: return "X86ISD::DEC";
19727 case X86ISD::OR: return "X86ISD::OR";
19728 case X86ISD::XOR: return "X86ISD::XOR";
19729 case X86ISD::AND: return "X86ISD::AND";
19730 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19731 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19732 case X86ISD::PTEST: return "X86ISD::PTEST";
19733 case X86ISD::TESTP: return "X86ISD::TESTP";
19734 case X86ISD::TESTM: return "X86ISD::TESTM";
19735 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19736 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19737 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19738 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19739 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19740 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19741 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19742 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19743 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19744 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19745 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19746 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19747 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19748 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19749 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19750 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19751 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19752 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19753 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19754 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19755 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19756 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19757 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19758 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19759 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19760 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19761 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19762 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19763 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19764 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19765 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19766 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19767 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19768 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19769 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19770 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19771 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19772 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19773 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19774 case X86ISD::SAHF: return "X86ISD::SAHF";
19775 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19776 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19777 case X86ISD::FMADD: return "X86ISD::FMADD";
19778 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19779 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19780 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19781 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19782 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19783 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19784 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19785 case X86ISD::XTEST: return "X86ISD::XTEST";
19789 // isLegalAddressingMode - Return true if the addressing mode represented
19790 // by AM is legal for this target, for a load/store of the specified type.
19791 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19793 // X86 supports extremely general addressing modes.
19794 CodeModel::Model M = getTargetMachine().getCodeModel();
19795 Reloc::Model R = getTargetMachine().getRelocationModel();
19797 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19798 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19803 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19805 // If a reference to this global requires an extra load, we can't fold it.
19806 if (isGlobalStubReference(GVFlags))
19809 // If BaseGV requires a register for the PIC base, we cannot also have a
19810 // BaseReg specified.
19811 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19814 // If lower 4G is not available, then we must use rip-relative addressing.
19815 if ((M != CodeModel::Small || R != Reloc::Static) &&
19816 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19820 switch (AM.Scale) {
19826 // These scales always work.
19831 // These scales are formed with basereg+scalereg. Only accept if there is
19836 default: // Other stuff never works.
19843 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19844 unsigned Bits = Ty->getScalarSizeInBits();
19846 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19847 // particularly cheaper than those without.
19851 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19852 // variable shifts just as cheap as scalar ones.
19853 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19856 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19857 // fully general vector.
19861 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19862 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19864 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19865 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19866 return NumBits1 > NumBits2;
19869 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19870 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19873 if (!isTypeLegal(EVT::getEVT(Ty1)))
19876 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19878 // Assuming the caller doesn't have a zeroext or signext return parameter,
19879 // truncation all the way down to i1 is valid.
19883 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19884 return isInt<32>(Imm);
19887 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19888 // Can also use sub to handle negated immediates.
19889 return isInt<32>(Imm);
19892 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19893 if (!VT1.isInteger() || !VT2.isInteger())
19895 unsigned NumBits1 = VT1.getSizeInBits();
19896 unsigned NumBits2 = VT2.getSizeInBits();
19897 return NumBits1 > NumBits2;
19900 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19901 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19902 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19905 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19906 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19907 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19910 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19911 EVT VT1 = Val.getValueType();
19912 if (isZExtFree(VT1, VT2))
19915 if (Val.getOpcode() != ISD::LOAD)
19918 if (!VT1.isSimple() || !VT1.isInteger() ||
19919 !VT2.isSimple() || !VT2.isInteger())
19922 switch (VT1.getSimpleVT().SimpleTy) {
19927 // X86 has 8, 16, and 32-bit zero-extending loads.
19935 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19936 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19939 VT = VT.getScalarType();
19941 if (!VT.isSimple())
19944 switch (VT.getSimpleVT().SimpleTy) {
19955 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19956 // i16 instructions are longer (0x66 prefix) and potentially slower.
19957 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19960 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19961 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19962 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19963 /// are assumed to be legal.
19965 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19967 if (!VT.isSimple())
19970 MVT SVT = VT.getSimpleVT();
19972 // Very little shuffling can be done for 64-bit vectors right now.
19973 if (VT.getSizeInBits() == 64)
19976 // If this is a single-input shuffle with no 128 bit lane crossings we can
19977 // lower it into pshufb.
19978 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19979 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19980 bool isLegal = true;
19981 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19982 if (M[I] >= (int)SVT.getVectorNumElements() ||
19983 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19992 // FIXME: blends, shifts.
19993 return (SVT.getVectorNumElements() == 2 ||
19994 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19995 isMOVLMask(M, SVT) ||
19996 isCommutedMOVLMask(M, SVT) ||
19997 isMOVHLPSMask(M, SVT) ||
19998 isSHUFPMask(M, SVT) ||
19999 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20000 isPSHUFDMask(M, SVT) ||
20001 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20002 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20003 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20004 isPALIGNRMask(M, SVT, Subtarget) ||
20005 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20006 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20007 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20008 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20009 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20010 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20014 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20016 if (!VT.isSimple())
20019 MVT SVT = VT.getSimpleVT();
20020 unsigned NumElts = SVT.getVectorNumElements();
20021 // FIXME: This collection of masks seems suspect.
20024 if (NumElts == 4 && SVT.is128BitVector()) {
20025 return (isMOVLMask(Mask, SVT) ||
20026 isCommutedMOVLMask(Mask, SVT, true) ||
20027 isSHUFPMask(Mask, SVT) ||
20028 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20029 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20030 Subtarget->hasInt256()));
20035 //===----------------------------------------------------------------------===//
20036 // X86 Scheduler Hooks
20037 //===----------------------------------------------------------------------===//
20039 /// Utility function to emit xbegin specifying the start of an RTM region.
20040 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20041 const TargetInstrInfo *TII) {
20042 DebugLoc DL = MI->getDebugLoc();
20044 const BasicBlock *BB = MBB->getBasicBlock();
20045 MachineFunction::iterator I = MBB;
20048 // For the v = xbegin(), we generate
20059 MachineBasicBlock *thisMBB = MBB;
20060 MachineFunction *MF = MBB->getParent();
20061 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20062 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20063 MF->insert(I, mainMBB);
20064 MF->insert(I, sinkMBB);
20066 // Transfer the remainder of BB and its successor edges to sinkMBB.
20067 sinkMBB->splice(sinkMBB->begin(), MBB,
20068 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20069 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20073 // # fallthrough to mainMBB
20074 // # abortion to sinkMBB
20075 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20076 thisMBB->addSuccessor(mainMBB);
20077 thisMBB->addSuccessor(sinkMBB);
20081 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20082 mainMBB->addSuccessor(sinkMBB);
20085 // EAX is live into the sinkMBB
20086 sinkMBB->addLiveIn(X86::EAX);
20087 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20088 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20091 MI->eraseFromParent();
20095 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20096 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20097 // in the .td file.
20098 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20099 const TargetInstrInfo *TII) {
20101 switch (MI->getOpcode()) {
20102 default: llvm_unreachable("illegal opcode!");
20103 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20104 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20105 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20106 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20107 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20108 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20109 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20110 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20113 DebugLoc dl = MI->getDebugLoc();
20114 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20116 unsigned NumArgs = MI->getNumOperands();
20117 for (unsigned i = 1; i < NumArgs; ++i) {
20118 MachineOperand &Op = MI->getOperand(i);
20119 if (!(Op.isReg() && Op.isImplicit()))
20120 MIB.addOperand(Op);
20122 if (MI->hasOneMemOperand())
20123 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20125 BuildMI(*BB, MI, dl,
20126 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20127 .addReg(X86::XMM0);
20129 MI->eraseFromParent();
20133 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20134 // defs in an instruction pattern
20135 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20136 const TargetInstrInfo *TII) {
20138 switch (MI->getOpcode()) {
20139 default: llvm_unreachable("illegal opcode!");
20140 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20141 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20142 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20143 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20144 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20145 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20146 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20147 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20150 DebugLoc dl = MI->getDebugLoc();
20151 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20153 unsigned NumArgs = MI->getNumOperands(); // remove the results
20154 for (unsigned i = 1; i < NumArgs; ++i) {
20155 MachineOperand &Op = MI->getOperand(i);
20156 if (!(Op.isReg() && Op.isImplicit()))
20157 MIB.addOperand(Op);
20159 if (MI->hasOneMemOperand())
20160 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20162 BuildMI(*BB, MI, dl,
20163 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20166 MI->eraseFromParent();
20170 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20171 const TargetInstrInfo *TII,
20172 const X86Subtarget* Subtarget) {
20173 DebugLoc dl = MI->getDebugLoc();
20175 // Address into RAX/EAX, other two args into ECX, EDX.
20176 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20177 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20178 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20179 for (int i = 0; i < X86::AddrNumOperands; ++i)
20180 MIB.addOperand(MI->getOperand(i));
20182 unsigned ValOps = X86::AddrNumOperands;
20183 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20184 .addReg(MI->getOperand(ValOps).getReg());
20185 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20186 .addReg(MI->getOperand(ValOps+1).getReg());
20188 // The instruction doesn't actually take any operands though.
20189 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20191 MI->eraseFromParent(); // The pseudo is gone now.
20195 MachineBasicBlock *
20196 X86TargetLowering::EmitVAARG64WithCustomInserter(
20198 MachineBasicBlock *MBB) const {
20199 // Emit va_arg instruction on X86-64.
20201 // Operands to this pseudo-instruction:
20202 // 0 ) Output : destination address (reg)
20203 // 1-5) Input : va_list address (addr, i64mem)
20204 // 6 ) ArgSize : Size (in bytes) of vararg type
20205 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20206 // 8 ) Align : Alignment of type
20207 // 9 ) EFLAGS (implicit-def)
20209 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20210 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20212 unsigned DestReg = MI->getOperand(0).getReg();
20213 MachineOperand &Base = MI->getOperand(1);
20214 MachineOperand &Scale = MI->getOperand(2);
20215 MachineOperand &Index = MI->getOperand(3);
20216 MachineOperand &Disp = MI->getOperand(4);
20217 MachineOperand &Segment = MI->getOperand(5);
20218 unsigned ArgSize = MI->getOperand(6).getImm();
20219 unsigned ArgMode = MI->getOperand(7).getImm();
20220 unsigned Align = MI->getOperand(8).getImm();
20222 // Memory Reference
20223 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20224 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20225 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20227 // Machine Information
20228 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20229 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20230 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20231 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20232 DebugLoc DL = MI->getDebugLoc();
20234 // struct va_list {
20237 // i64 overflow_area (address)
20238 // i64 reg_save_area (address)
20240 // sizeof(va_list) = 24
20241 // alignment(va_list) = 8
20243 unsigned TotalNumIntRegs = 6;
20244 unsigned TotalNumXMMRegs = 8;
20245 bool UseGPOffset = (ArgMode == 1);
20246 bool UseFPOffset = (ArgMode == 2);
20247 unsigned MaxOffset = TotalNumIntRegs * 8 +
20248 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20250 /* Align ArgSize to a multiple of 8 */
20251 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20252 bool NeedsAlign = (Align > 8);
20254 MachineBasicBlock *thisMBB = MBB;
20255 MachineBasicBlock *overflowMBB;
20256 MachineBasicBlock *offsetMBB;
20257 MachineBasicBlock *endMBB;
20259 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20260 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20261 unsigned OffsetReg = 0;
20263 if (!UseGPOffset && !UseFPOffset) {
20264 // If we only pull from the overflow region, we don't create a branch.
20265 // We don't need to alter control flow.
20266 OffsetDestReg = 0; // unused
20267 OverflowDestReg = DestReg;
20269 offsetMBB = nullptr;
20270 overflowMBB = thisMBB;
20273 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20274 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20275 // If not, pull from overflow_area. (branch to overflowMBB)
20280 // offsetMBB overflowMBB
20285 // Registers for the PHI in endMBB
20286 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20287 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20289 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20290 MachineFunction *MF = MBB->getParent();
20291 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20292 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20293 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20295 MachineFunction::iterator MBBIter = MBB;
20298 // Insert the new basic blocks
20299 MF->insert(MBBIter, offsetMBB);
20300 MF->insert(MBBIter, overflowMBB);
20301 MF->insert(MBBIter, endMBB);
20303 // Transfer the remainder of MBB and its successor edges to endMBB.
20304 endMBB->splice(endMBB->begin(), thisMBB,
20305 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20306 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20308 // Make offsetMBB and overflowMBB successors of thisMBB
20309 thisMBB->addSuccessor(offsetMBB);
20310 thisMBB->addSuccessor(overflowMBB);
20312 // endMBB is a successor of both offsetMBB and overflowMBB
20313 offsetMBB->addSuccessor(endMBB);
20314 overflowMBB->addSuccessor(endMBB);
20316 // Load the offset value into a register
20317 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20318 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20322 .addDisp(Disp, UseFPOffset ? 4 : 0)
20323 .addOperand(Segment)
20324 .setMemRefs(MMOBegin, MMOEnd);
20326 // Check if there is enough room left to pull this argument.
20327 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20329 .addImm(MaxOffset + 8 - ArgSizeA8);
20331 // Branch to "overflowMBB" if offset >= max
20332 // Fall through to "offsetMBB" otherwise
20333 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20334 .addMBB(overflowMBB);
20337 // In offsetMBB, emit code to use the reg_save_area.
20339 assert(OffsetReg != 0);
20341 // Read the reg_save_area address.
20342 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20343 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20348 .addOperand(Segment)
20349 .setMemRefs(MMOBegin, MMOEnd);
20351 // Zero-extend the offset
20352 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20353 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20356 .addImm(X86::sub_32bit);
20358 // Add the offset to the reg_save_area to get the final address.
20359 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20360 .addReg(OffsetReg64)
20361 .addReg(RegSaveReg);
20363 // Compute the offset for the next argument
20364 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20365 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20367 .addImm(UseFPOffset ? 16 : 8);
20369 // Store it back into the va_list.
20370 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20374 .addDisp(Disp, UseFPOffset ? 4 : 0)
20375 .addOperand(Segment)
20376 .addReg(NextOffsetReg)
20377 .setMemRefs(MMOBegin, MMOEnd);
20380 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20385 // Emit code to use overflow area
20388 // Load the overflow_area address into a register.
20389 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20390 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20395 .addOperand(Segment)
20396 .setMemRefs(MMOBegin, MMOEnd);
20398 // If we need to align it, do so. Otherwise, just copy the address
20399 // to OverflowDestReg.
20401 // Align the overflow address
20402 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20403 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20405 // aligned_addr = (addr + (align-1)) & ~(align-1)
20406 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20407 .addReg(OverflowAddrReg)
20410 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20412 .addImm(~(uint64_t)(Align-1));
20414 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20415 .addReg(OverflowAddrReg);
20418 // Compute the next overflow address after this argument.
20419 // (the overflow address should be kept 8-byte aligned)
20420 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20421 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20422 .addReg(OverflowDestReg)
20423 .addImm(ArgSizeA8);
20425 // Store the new overflow address.
20426 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20431 .addOperand(Segment)
20432 .addReg(NextAddrReg)
20433 .setMemRefs(MMOBegin, MMOEnd);
20435 // If we branched, emit the PHI to the front of endMBB.
20437 BuildMI(*endMBB, endMBB->begin(), DL,
20438 TII->get(X86::PHI), DestReg)
20439 .addReg(OffsetDestReg).addMBB(offsetMBB)
20440 .addReg(OverflowDestReg).addMBB(overflowMBB);
20443 // Erase the pseudo instruction
20444 MI->eraseFromParent();
20449 MachineBasicBlock *
20450 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20452 MachineBasicBlock *MBB) const {
20453 // Emit code to save XMM registers to the stack. The ABI says that the
20454 // number of registers to save is given in %al, so it's theoretically
20455 // possible to do an indirect jump trick to avoid saving all of them,
20456 // however this code takes a simpler approach and just executes all
20457 // of the stores if %al is non-zero. It's less code, and it's probably
20458 // easier on the hardware branch predictor, and stores aren't all that
20459 // expensive anyway.
20461 // Create the new basic blocks. One block contains all the XMM stores,
20462 // and one block is the final destination regardless of whether any
20463 // stores were performed.
20464 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20465 MachineFunction *F = MBB->getParent();
20466 MachineFunction::iterator MBBIter = MBB;
20468 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20469 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20470 F->insert(MBBIter, XMMSaveMBB);
20471 F->insert(MBBIter, EndMBB);
20473 // Transfer the remainder of MBB and its successor edges to EndMBB.
20474 EndMBB->splice(EndMBB->begin(), MBB,
20475 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20476 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20478 // The original block will now fall through to the XMM save block.
20479 MBB->addSuccessor(XMMSaveMBB);
20480 // The XMMSaveMBB will fall through to the end block.
20481 XMMSaveMBB->addSuccessor(EndMBB);
20483 // Now add the instructions.
20484 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20485 DebugLoc DL = MI->getDebugLoc();
20487 unsigned CountReg = MI->getOperand(0).getReg();
20488 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20489 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20491 if (!Subtarget->isTargetWin64()) {
20492 // If %al is 0, branch around the XMM save block.
20493 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20494 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20495 MBB->addSuccessor(EndMBB);
20498 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20499 // that was just emitted, but clearly shouldn't be "saved".
20500 assert((MI->getNumOperands() <= 3 ||
20501 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20502 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20503 && "Expected last argument to be EFLAGS");
20504 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20505 // In the XMM save block, save all the XMM argument registers.
20506 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20507 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20508 MachineMemOperand *MMO =
20509 F->getMachineMemOperand(
20510 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20511 MachineMemOperand::MOStore,
20512 /*Size=*/16, /*Align=*/16);
20513 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20514 .addFrameIndex(RegSaveFrameIndex)
20515 .addImm(/*Scale=*/1)
20516 .addReg(/*IndexReg=*/0)
20517 .addImm(/*Disp=*/Offset)
20518 .addReg(/*Segment=*/0)
20519 .addReg(MI->getOperand(i).getReg())
20520 .addMemOperand(MMO);
20523 MI->eraseFromParent(); // The pseudo instruction is gone now.
20528 // The EFLAGS operand of SelectItr might be missing a kill marker
20529 // because there were multiple uses of EFLAGS, and ISel didn't know
20530 // which to mark. Figure out whether SelectItr should have had a
20531 // kill marker, and set it if it should. Returns the correct kill
20533 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20534 MachineBasicBlock* BB,
20535 const TargetRegisterInfo* TRI) {
20536 // Scan forward through BB for a use/def of EFLAGS.
20537 MachineBasicBlock::iterator miI(std::next(SelectItr));
20538 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20539 const MachineInstr& mi = *miI;
20540 if (mi.readsRegister(X86::EFLAGS))
20542 if (mi.definesRegister(X86::EFLAGS))
20543 break; // Should have kill-flag - update below.
20546 // If we hit the end of the block, check whether EFLAGS is live into a
20548 if (miI == BB->end()) {
20549 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20550 sEnd = BB->succ_end();
20551 sItr != sEnd; ++sItr) {
20552 MachineBasicBlock* succ = *sItr;
20553 if (succ->isLiveIn(X86::EFLAGS))
20558 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20559 // out. SelectMI should have a kill flag on EFLAGS.
20560 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20564 MachineBasicBlock *
20565 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20566 MachineBasicBlock *BB) const {
20567 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20568 DebugLoc DL = MI->getDebugLoc();
20570 // To "insert" a SELECT_CC instruction, we actually have to insert the
20571 // diamond control-flow pattern. The incoming instruction knows the
20572 // destination vreg to set, the condition code register to branch on, the
20573 // true/false values to select between, and a branch opcode to use.
20574 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20575 MachineFunction::iterator It = BB;
20581 // cmpTY ccX, r1, r2
20583 // fallthrough --> copy0MBB
20584 MachineBasicBlock *thisMBB = BB;
20585 MachineFunction *F = BB->getParent();
20586 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20587 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20588 F->insert(It, copy0MBB);
20589 F->insert(It, sinkMBB);
20591 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20592 // live into the sink and copy blocks.
20593 const TargetRegisterInfo *TRI =
20594 BB->getParent()->getSubtarget().getRegisterInfo();
20595 if (!MI->killsRegister(X86::EFLAGS) &&
20596 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20597 copy0MBB->addLiveIn(X86::EFLAGS);
20598 sinkMBB->addLiveIn(X86::EFLAGS);
20601 // Transfer the remainder of BB and its successor edges to sinkMBB.
20602 sinkMBB->splice(sinkMBB->begin(), BB,
20603 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20604 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20606 // Add the true and fallthrough blocks as its successors.
20607 BB->addSuccessor(copy0MBB);
20608 BB->addSuccessor(sinkMBB);
20610 // Create the conditional branch instruction.
20612 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20613 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20616 // %FalseValue = ...
20617 // # fallthrough to sinkMBB
20618 copy0MBB->addSuccessor(sinkMBB);
20621 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20623 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20624 TII->get(X86::PHI), MI->getOperand(0).getReg())
20625 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20626 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20628 MI->eraseFromParent(); // The pseudo instruction is gone now.
20632 MachineBasicBlock *
20633 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20634 MachineBasicBlock *BB) const {
20635 MachineFunction *MF = BB->getParent();
20636 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20637 DebugLoc DL = MI->getDebugLoc();
20638 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20640 assert(MF->shouldSplitStack());
20642 const bool Is64Bit = Subtarget->is64Bit();
20643 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20645 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20646 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20649 // ... [Till the alloca]
20650 // If stacklet is not large enough, jump to mallocMBB
20653 // Allocate by subtracting from RSP
20654 // Jump to continueMBB
20657 // Allocate by call to runtime
20661 // [rest of original BB]
20664 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20665 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20666 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20668 MachineRegisterInfo &MRI = MF->getRegInfo();
20669 const TargetRegisterClass *AddrRegClass =
20670 getRegClassFor(getPointerTy());
20672 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20673 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20674 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20675 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20676 sizeVReg = MI->getOperand(1).getReg(),
20677 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20679 MachineFunction::iterator MBBIter = BB;
20682 MF->insert(MBBIter, bumpMBB);
20683 MF->insert(MBBIter, mallocMBB);
20684 MF->insert(MBBIter, continueMBB);
20686 continueMBB->splice(continueMBB->begin(), BB,
20687 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20688 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20690 // Add code to the main basic block to check if the stack limit has been hit,
20691 // and if so, jump to mallocMBB otherwise to bumpMBB.
20692 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20693 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20694 .addReg(tmpSPVReg).addReg(sizeVReg);
20695 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20696 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20697 .addReg(SPLimitVReg);
20698 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20700 // bumpMBB simply decreases the stack pointer, since we know the current
20701 // stacklet has enough space.
20702 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20703 .addReg(SPLimitVReg);
20704 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20705 .addReg(SPLimitVReg);
20706 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20708 // Calls into a routine in libgcc to allocate more space from the heap.
20709 const uint32_t *RegMask = MF->getTarget()
20710 .getSubtargetImpl()
20711 ->getRegisterInfo()
20712 ->getCallPreservedMask(CallingConv::C);
20714 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20716 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20717 .addExternalSymbol("__morestack_allocate_stack_space")
20718 .addRegMask(RegMask)
20719 .addReg(X86::RDI, RegState::Implicit)
20720 .addReg(X86::RAX, RegState::ImplicitDefine);
20721 } else if (Is64Bit) {
20722 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20724 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20725 .addExternalSymbol("__morestack_allocate_stack_space")
20726 .addRegMask(RegMask)
20727 .addReg(X86::EDI, RegState::Implicit)
20728 .addReg(X86::EAX, RegState::ImplicitDefine);
20730 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20732 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20733 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20734 .addExternalSymbol("__morestack_allocate_stack_space")
20735 .addRegMask(RegMask)
20736 .addReg(X86::EAX, RegState::ImplicitDefine);
20740 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20743 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20744 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20745 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20747 // Set up the CFG correctly.
20748 BB->addSuccessor(bumpMBB);
20749 BB->addSuccessor(mallocMBB);
20750 mallocMBB->addSuccessor(continueMBB);
20751 bumpMBB->addSuccessor(continueMBB);
20753 // Take care of the PHI nodes.
20754 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20755 MI->getOperand(0).getReg())
20756 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20757 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20759 // Delete the original pseudo instruction.
20760 MI->eraseFromParent();
20763 return continueMBB;
20766 MachineBasicBlock *
20767 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20768 MachineBasicBlock *BB) const {
20769 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20770 DebugLoc DL = MI->getDebugLoc();
20772 assert(!Subtarget->isTargetMacho());
20774 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20775 // non-trivial part is impdef of ESP.
20777 if (Subtarget->isTargetWin64()) {
20778 if (Subtarget->isTargetCygMing()) {
20779 // ___chkstk(Mingw64):
20780 // Clobbers R10, R11, RAX and EFLAGS.
20782 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20783 .addExternalSymbol("___chkstk")
20784 .addReg(X86::RAX, RegState::Implicit)
20785 .addReg(X86::RSP, RegState::Implicit)
20786 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20787 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20788 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20790 // __chkstk(MSVCRT): does not update stack pointer.
20791 // Clobbers R10, R11 and EFLAGS.
20792 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20793 .addExternalSymbol("__chkstk")
20794 .addReg(X86::RAX, RegState::Implicit)
20795 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20796 // RAX has the offset to be subtracted from RSP.
20797 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20802 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20803 Subtarget->isTargetWindowsItanium())
20807 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20808 .addExternalSymbol(StackProbeSymbol)
20809 .addReg(X86::EAX, RegState::Implicit)
20810 .addReg(X86::ESP, RegState::Implicit)
20811 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20812 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20813 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20816 MI->eraseFromParent(); // The pseudo instruction is gone now.
20820 MachineBasicBlock *
20821 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20822 MachineBasicBlock *BB) const {
20823 // This is pretty easy. We're taking the value that we received from
20824 // our load from the relocation, sticking it in either RDI (x86-64)
20825 // or EAX and doing an indirect call. The return value will then
20826 // be in the normal return register.
20827 MachineFunction *F = BB->getParent();
20828 const X86InstrInfo *TII =
20829 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20830 DebugLoc DL = MI->getDebugLoc();
20832 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20833 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20835 // Get a register mask for the lowered call.
20836 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20837 // proper register mask.
20838 const uint32_t *RegMask = F->getTarget()
20839 .getSubtargetImpl()
20840 ->getRegisterInfo()
20841 ->getCallPreservedMask(CallingConv::C);
20842 if (Subtarget->is64Bit()) {
20843 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20844 TII->get(X86::MOV64rm), X86::RDI)
20846 .addImm(0).addReg(0)
20847 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20848 MI->getOperand(3).getTargetFlags())
20850 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20851 addDirectMem(MIB, X86::RDI);
20852 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20853 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20854 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20855 TII->get(X86::MOV32rm), X86::EAX)
20857 .addImm(0).addReg(0)
20858 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20859 MI->getOperand(3).getTargetFlags())
20861 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20862 addDirectMem(MIB, X86::EAX);
20863 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20865 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20866 TII->get(X86::MOV32rm), X86::EAX)
20867 .addReg(TII->getGlobalBaseReg(F))
20868 .addImm(0).addReg(0)
20869 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20870 MI->getOperand(3).getTargetFlags())
20872 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20873 addDirectMem(MIB, X86::EAX);
20874 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20877 MI->eraseFromParent(); // The pseudo instruction is gone now.
20881 MachineBasicBlock *
20882 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20883 MachineBasicBlock *MBB) const {
20884 DebugLoc DL = MI->getDebugLoc();
20885 MachineFunction *MF = MBB->getParent();
20886 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20887 MachineRegisterInfo &MRI = MF->getRegInfo();
20889 const BasicBlock *BB = MBB->getBasicBlock();
20890 MachineFunction::iterator I = MBB;
20893 // Memory Reference
20894 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20895 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20898 unsigned MemOpndSlot = 0;
20900 unsigned CurOp = 0;
20902 DstReg = MI->getOperand(CurOp++).getReg();
20903 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20904 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20905 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20906 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20908 MemOpndSlot = CurOp;
20910 MVT PVT = getPointerTy();
20911 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20912 "Invalid Pointer Size!");
20914 // For v = setjmp(buf), we generate
20917 // buf[LabelOffset] = restoreMBB
20918 // SjLjSetup restoreMBB
20924 // v = phi(main, restore)
20927 // if base pointer being used, load it from frame
20930 MachineBasicBlock *thisMBB = MBB;
20931 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20932 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20933 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20934 MF->insert(I, mainMBB);
20935 MF->insert(I, sinkMBB);
20936 MF->push_back(restoreMBB);
20938 MachineInstrBuilder MIB;
20940 // Transfer the remainder of BB and its successor edges to sinkMBB.
20941 sinkMBB->splice(sinkMBB->begin(), MBB,
20942 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20943 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20946 unsigned PtrStoreOpc = 0;
20947 unsigned LabelReg = 0;
20948 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20949 Reloc::Model RM = MF->getTarget().getRelocationModel();
20950 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20951 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20953 // Prepare IP either in reg or imm.
20954 if (!UseImmLabel) {
20955 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20956 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20957 LabelReg = MRI.createVirtualRegister(PtrRC);
20958 if (Subtarget->is64Bit()) {
20959 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20963 .addMBB(restoreMBB)
20966 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20967 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20968 .addReg(XII->getGlobalBaseReg(MF))
20971 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20975 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20977 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20978 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20979 if (i == X86::AddrDisp)
20980 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20982 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20985 MIB.addReg(LabelReg);
20987 MIB.addMBB(restoreMBB);
20988 MIB.setMemRefs(MMOBegin, MMOEnd);
20990 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20991 .addMBB(restoreMBB);
20993 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20994 MF->getSubtarget().getRegisterInfo());
20995 MIB.addRegMask(RegInfo->getNoPreservedMask());
20996 thisMBB->addSuccessor(mainMBB);
20997 thisMBB->addSuccessor(restoreMBB);
21001 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21002 mainMBB->addSuccessor(sinkMBB);
21005 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21006 TII->get(X86::PHI), DstReg)
21007 .addReg(mainDstReg).addMBB(mainMBB)
21008 .addReg(restoreDstReg).addMBB(restoreMBB);
21011 if (RegInfo->hasBasePointer(*MF)) {
21012 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21013 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21014 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21015 X86FI->setRestoreBasePointer(MF);
21016 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21017 unsigned BasePtr = RegInfo->getBaseRegister();
21018 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21019 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21020 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21021 .setMIFlag(MachineInstr::FrameSetup);
21023 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21024 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21025 restoreMBB->addSuccessor(sinkMBB);
21027 MI->eraseFromParent();
21031 MachineBasicBlock *
21032 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21033 MachineBasicBlock *MBB) const {
21034 DebugLoc DL = MI->getDebugLoc();
21035 MachineFunction *MF = MBB->getParent();
21036 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21037 MachineRegisterInfo &MRI = MF->getRegInfo();
21039 // Memory Reference
21040 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21041 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21043 MVT PVT = getPointerTy();
21044 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21045 "Invalid Pointer Size!");
21047 const TargetRegisterClass *RC =
21048 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21049 unsigned Tmp = MRI.createVirtualRegister(RC);
21050 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21051 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21052 MF->getSubtarget().getRegisterInfo());
21053 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21054 unsigned SP = RegInfo->getStackRegister();
21056 MachineInstrBuilder MIB;
21058 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21059 const int64_t SPOffset = 2 * PVT.getStoreSize();
21061 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21062 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21065 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21066 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21067 MIB.addOperand(MI->getOperand(i));
21068 MIB.setMemRefs(MMOBegin, MMOEnd);
21070 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21071 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21072 if (i == X86::AddrDisp)
21073 MIB.addDisp(MI->getOperand(i), LabelOffset);
21075 MIB.addOperand(MI->getOperand(i));
21077 MIB.setMemRefs(MMOBegin, MMOEnd);
21079 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21080 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21081 if (i == X86::AddrDisp)
21082 MIB.addDisp(MI->getOperand(i), SPOffset);
21084 MIB.addOperand(MI->getOperand(i));
21086 MIB.setMemRefs(MMOBegin, MMOEnd);
21088 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21090 MI->eraseFromParent();
21094 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21095 // accumulator loops. Writing back to the accumulator allows the coalescer
21096 // to remove extra copies in the loop.
21097 MachineBasicBlock *
21098 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21099 MachineBasicBlock *MBB) const {
21100 MachineOperand &AddendOp = MI->getOperand(3);
21102 // Bail out early if the addend isn't a register - we can't switch these.
21103 if (!AddendOp.isReg())
21106 MachineFunction &MF = *MBB->getParent();
21107 MachineRegisterInfo &MRI = MF.getRegInfo();
21109 // Check whether the addend is defined by a PHI:
21110 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21111 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21112 if (!AddendDef.isPHI())
21115 // Look for the following pattern:
21117 // %addend = phi [%entry, 0], [%loop, %result]
21119 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21123 // %addend = phi [%entry, 0], [%loop, %result]
21125 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21127 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21128 assert(AddendDef.getOperand(i).isReg());
21129 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21130 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21131 if (&PHISrcInst == MI) {
21132 // Found a matching instruction.
21133 unsigned NewFMAOpc = 0;
21134 switch (MI->getOpcode()) {
21135 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21136 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21137 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21138 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21139 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21140 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21141 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21142 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21143 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21144 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21145 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21146 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21147 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21148 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21149 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21150 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21151 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21152 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21153 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21154 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21156 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21157 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21158 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21159 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21160 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21161 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21162 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21163 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21164 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21165 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21166 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21167 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21168 default: llvm_unreachable("Unrecognized FMA variant.");
21171 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21172 MachineInstrBuilder MIB =
21173 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21174 .addOperand(MI->getOperand(0))
21175 .addOperand(MI->getOperand(3))
21176 .addOperand(MI->getOperand(2))
21177 .addOperand(MI->getOperand(1));
21178 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21179 MI->eraseFromParent();
21186 MachineBasicBlock *
21187 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21188 MachineBasicBlock *BB) const {
21189 switch (MI->getOpcode()) {
21190 default: llvm_unreachable("Unexpected instr type to insert");
21191 case X86::TAILJMPd64:
21192 case X86::TAILJMPr64:
21193 case X86::TAILJMPm64:
21194 llvm_unreachable("TAILJMP64 would not be touched here.");
21195 case X86::TCRETURNdi64:
21196 case X86::TCRETURNri64:
21197 case X86::TCRETURNmi64:
21199 case X86::WIN_ALLOCA:
21200 return EmitLoweredWinAlloca(MI, BB);
21201 case X86::SEG_ALLOCA_32:
21202 case X86::SEG_ALLOCA_64:
21203 return EmitLoweredSegAlloca(MI, BB);
21204 case X86::TLSCall_32:
21205 case X86::TLSCall_64:
21206 return EmitLoweredTLSCall(MI, BB);
21207 case X86::CMOV_GR8:
21208 case X86::CMOV_FR32:
21209 case X86::CMOV_FR64:
21210 case X86::CMOV_V4F32:
21211 case X86::CMOV_V2F64:
21212 case X86::CMOV_V2I64:
21213 case X86::CMOV_V8F32:
21214 case X86::CMOV_V4F64:
21215 case X86::CMOV_V4I64:
21216 case X86::CMOV_V16F32:
21217 case X86::CMOV_V8F64:
21218 case X86::CMOV_V8I64:
21219 case X86::CMOV_GR16:
21220 case X86::CMOV_GR32:
21221 case X86::CMOV_RFP32:
21222 case X86::CMOV_RFP64:
21223 case X86::CMOV_RFP80:
21224 return EmitLoweredSelect(MI, BB);
21226 case X86::FP32_TO_INT16_IN_MEM:
21227 case X86::FP32_TO_INT32_IN_MEM:
21228 case X86::FP32_TO_INT64_IN_MEM:
21229 case X86::FP64_TO_INT16_IN_MEM:
21230 case X86::FP64_TO_INT32_IN_MEM:
21231 case X86::FP64_TO_INT64_IN_MEM:
21232 case X86::FP80_TO_INT16_IN_MEM:
21233 case X86::FP80_TO_INT32_IN_MEM:
21234 case X86::FP80_TO_INT64_IN_MEM: {
21235 MachineFunction *F = BB->getParent();
21236 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21237 DebugLoc DL = MI->getDebugLoc();
21239 // Change the floating point control register to use "round towards zero"
21240 // mode when truncating to an integer value.
21241 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21242 addFrameReference(BuildMI(*BB, MI, DL,
21243 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21245 // Load the old value of the high byte of the control word...
21247 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21248 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21251 // Set the high part to be round to zero...
21252 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21255 // Reload the modified control word now...
21256 addFrameReference(BuildMI(*BB, MI, DL,
21257 TII->get(X86::FLDCW16m)), CWFrameIdx);
21259 // Restore the memory image of control word to original value
21260 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21263 // Get the X86 opcode to use.
21265 switch (MI->getOpcode()) {
21266 default: llvm_unreachable("illegal opcode!");
21267 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21268 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21269 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21270 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21271 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21272 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21273 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21274 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21275 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21279 MachineOperand &Op = MI->getOperand(0);
21281 AM.BaseType = X86AddressMode::RegBase;
21282 AM.Base.Reg = Op.getReg();
21284 AM.BaseType = X86AddressMode::FrameIndexBase;
21285 AM.Base.FrameIndex = Op.getIndex();
21287 Op = MI->getOperand(1);
21289 AM.Scale = Op.getImm();
21290 Op = MI->getOperand(2);
21292 AM.IndexReg = Op.getImm();
21293 Op = MI->getOperand(3);
21294 if (Op.isGlobal()) {
21295 AM.GV = Op.getGlobal();
21297 AM.Disp = Op.getImm();
21299 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21300 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21302 // Reload the original control word now.
21303 addFrameReference(BuildMI(*BB, MI, DL,
21304 TII->get(X86::FLDCW16m)), CWFrameIdx);
21306 MI->eraseFromParent(); // The pseudo instruction is gone now.
21309 // String/text processing lowering.
21310 case X86::PCMPISTRM128REG:
21311 case X86::VPCMPISTRM128REG:
21312 case X86::PCMPISTRM128MEM:
21313 case X86::VPCMPISTRM128MEM:
21314 case X86::PCMPESTRM128REG:
21315 case X86::VPCMPESTRM128REG:
21316 case X86::PCMPESTRM128MEM:
21317 case X86::VPCMPESTRM128MEM:
21318 assert(Subtarget->hasSSE42() &&
21319 "Target must have SSE4.2 or AVX features enabled");
21320 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21322 // String/text processing lowering.
21323 case X86::PCMPISTRIREG:
21324 case X86::VPCMPISTRIREG:
21325 case X86::PCMPISTRIMEM:
21326 case X86::VPCMPISTRIMEM:
21327 case X86::PCMPESTRIREG:
21328 case X86::VPCMPESTRIREG:
21329 case X86::PCMPESTRIMEM:
21330 case X86::VPCMPESTRIMEM:
21331 assert(Subtarget->hasSSE42() &&
21332 "Target must have SSE4.2 or AVX features enabled");
21333 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21335 // Thread synchronization.
21337 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21342 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21344 case X86::VASTART_SAVE_XMM_REGS:
21345 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21347 case X86::VAARG_64:
21348 return EmitVAARG64WithCustomInserter(MI, BB);
21350 case X86::EH_SjLj_SetJmp32:
21351 case X86::EH_SjLj_SetJmp64:
21352 return emitEHSjLjSetJmp(MI, BB);
21354 case X86::EH_SjLj_LongJmp32:
21355 case X86::EH_SjLj_LongJmp64:
21356 return emitEHSjLjLongJmp(MI, BB);
21358 case TargetOpcode::STATEPOINT:
21359 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21360 // this point in the process. We diverge later.
21361 return emitPatchPoint(MI, BB);
21363 case TargetOpcode::STACKMAP:
21364 case TargetOpcode::PATCHPOINT:
21365 return emitPatchPoint(MI, BB);
21367 case X86::VFMADDPDr213r:
21368 case X86::VFMADDPSr213r:
21369 case X86::VFMADDSDr213r:
21370 case X86::VFMADDSSr213r:
21371 case X86::VFMSUBPDr213r:
21372 case X86::VFMSUBPSr213r:
21373 case X86::VFMSUBSDr213r:
21374 case X86::VFMSUBSSr213r:
21375 case X86::VFNMADDPDr213r:
21376 case X86::VFNMADDPSr213r:
21377 case X86::VFNMADDSDr213r:
21378 case X86::VFNMADDSSr213r:
21379 case X86::VFNMSUBPDr213r:
21380 case X86::VFNMSUBPSr213r:
21381 case X86::VFNMSUBSDr213r:
21382 case X86::VFNMSUBSSr213r:
21383 case X86::VFMADDSUBPDr213r:
21384 case X86::VFMADDSUBPSr213r:
21385 case X86::VFMSUBADDPDr213r:
21386 case X86::VFMSUBADDPSr213r:
21387 case X86::VFMADDPDr213rY:
21388 case X86::VFMADDPSr213rY:
21389 case X86::VFMSUBPDr213rY:
21390 case X86::VFMSUBPSr213rY:
21391 case X86::VFNMADDPDr213rY:
21392 case X86::VFNMADDPSr213rY:
21393 case X86::VFNMSUBPDr213rY:
21394 case X86::VFNMSUBPSr213rY:
21395 case X86::VFMADDSUBPDr213rY:
21396 case X86::VFMADDSUBPSr213rY:
21397 case X86::VFMSUBADDPDr213rY:
21398 case X86::VFMSUBADDPSr213rY:
21399 return emitFMA3Instr(MI, BB);
21403 //===----------------------------------------------------------------------===//
21404 // X86 Optimization Hooks
21405 //===----------------------------------------------------------------------===//
21407 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21410 const SelectionDAG &DAG,
21411 unsigned Depth) const {
21412 unsigned BitWidth = KnownZero.getBitWidth();
21413 unsigned Opc = Op.getOpcode();
21414 assert((Opc >= ISD::BUILTIN_OP_END ||
21415 Opc == ISD::INTRINSIC_WO_CHAIN ||
21416 Opc == ISD::INTRINSIC_W_CHAIN ||
21417 Opc == ISD::INTRINSIC_VOID) &&
21418 "Should use MaskedValueIsZero if you don't know whether Op"
21419 " is a target node!");
21421 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21435 // These nodes' second result is a boolean.
21436 if (Op.getResNo() == 0)
21439 case X86ISD::SETCC:
21440 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21442 case ISD::INTRINSIC_WO_CHAIN: {
21443 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21444 unsigned NumLoBits = 0;
21447 case Intrinsic::x86_sse_movmsk_ps:
21448 case Intrinsic::x86_avx_movmsk_ps_256:
21449 case Intrinsic::x86_sse2_movmsk_pd:
21450 case Intrinsic::x86_avx_movmsk_pd_256:
21451 case Intrinsic::x86_mmx_pmovmskb:
21452 case Intrinsic::x86_sse2_pmovmskb_128:
21453 case Intrinsic::x86_avx2_pmovmskb: {
21454 // High bits of movmskp{s|d}, pmovmskb are known zero.
21456 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21457 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21458 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21459 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21460 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21461 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21462 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21463 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21465 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21474 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21476 const SelectionDAG &,
21477 unsigned Depth) const {
21478 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21479 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21480 return Op.getValueType().getScalarType().getSizeInBits();
21486 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21487 /// node is a GlobalAddress + offset.
21488 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21489 const GlobalValue* &GA,
21490 int64_t &Offset) const {
21491 if (N->getOpcode() == X86ISD::Wrapper) {
21492 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21493 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21494 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21498 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21501 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21502 /// same as extracting the high 128-bit part of 256-bit vector and then
21503 /// inserting the result into the low part of a new 256-bit vector
21504 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21505 EVT VT = SVOp->getValueType(0);
21506 unsigned NumElems = VT.getVectorNumElements();
21508 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21509 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21510 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21511 SVOp->getMaskElt(j) >= 0)
21517 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21518 /// same as extracting the low 128-bit part of 256-bit vector and then
21519 /// inserting the result into the high part of a new 256-bit vector
21520 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21521 EVT VT = SVOp->getValueType(0);
21522 unsigned NumElems = VT.getVectorNumElements();
21524 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21525 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21526 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21527 SVOp->getMaskElt(j) >= 0)
21533 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21534 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21535 TargetLowering::DAGCombinerInfo &DCI,
21536 const X86Subtarget* Subtarget) {
21538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21539 SDValue V1 = SVOp->getOperand(0);
21540 SDValue V2 = SVOp->getOperand(1);
21541 EVT VT = SVOp->getValueType(0);
21542 unsigned NumElems = VT.getVectorNumElements();
21544 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21545 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21549 // V UNDEF BUILD_VECTOR UNDEF
21551 // CONCAT_VECTOR CONCAT_VECTOR
21554 // RESULT: V + zero extended
21556 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21557 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21558 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21561 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21564 // To match the shuffle mask, the first half of the mask should
21565 // be exactly the first vector, and all the rest a splat with the
21566 // first element of the second one.
21567 for (unsigned i = 0; i != NumElems/2; ++i)
21568 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21569 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21572 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21573 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21574 if (Ld->hasNUsesOfValue(1, 0)) {
21575 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21576 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21578 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21580 Ld->getPointerInfo(),
21581 Ld->getAlignment(),
21582 false/*isVolatile*/, true/*ReadMem*/,
21583 false/*WriteMem*/);
21585 // Make sure the newly-created LOAD is in the same position as Ld in
21586 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21587 // and update uses of Ld's output chain to use the TokenFactor.
21588 if (Ld->hasAnyUseOfValue(1)) {
21589 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21590 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21591 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21592 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21593 SDValue(ResNode.getNode(), 1));
21596 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21600 // Emit a zeroed vector and insert the desired subvector on its
21602 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21603 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21604 return DCI.CombineTo(N, InsV);
21607 //===--------------------------------------------------------------------===//
21608 // Combine some shuffles into subvector extracts and inserts:
21611 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21612 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21613 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21614 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21615 return DCI.CombineTo(N, InsV);
21618 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21619 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21620 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21621 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21622 return DCI.CombineTo(N, InsV);
21628 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21631 /// This is the leaf of the recursive combinine below. When we have found some
21632 /// chain of single-use x86 shuffle instructions and accumulated the combined
21633 /// shuffle mask represented by them, this will try to pattern match that mask
21634 /// into either a single instruction if there is a special purpose instruction
21635 /// for this operation, or into a PSHUFB instruction which is a fully general
21636 /// instruction but should only be used to replace chains over a certain depth.
21637 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21638 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21639 TargetLowering::DAGCombinerInfo &DCI,
21640 const X86Subtarget *Subtarget) {
21641 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21643 // Find the operand that enters the chain. Note that multiple uses are OK
21644 // here, we're not going to remove the operand we find.
21645 SDValue Input = Op.getOperand(0);
21646 while (Input.getOpcode() == ISD::BITCAST)
21647 Input = Input.getOperand(0);
21649 MVT VT = Input.getSimpleValueType();
21650 MVT RootVT = Root.getSimpleValueType();
21653 // Just remove no-op shuffle masks.
21654 if (Mask.size() == 1) {
21655 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21660 // Use the float domain if the operand type is a floating point type.
21661 bool FloatDomain = VT.isFloatingPoint();
21663 // For floating point shuffles, we don't have free copies in the shuffle
21664 // instructions or the ability to load as part of the instruction, so
21665 // canonicalize their shuffles to UNPCK or MOV variants.
21667 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21668 // vectors because it can have a load folded into it that UNPCK cannot. This
21669 // doesn't preclude something switching to the shorter encoding post-RA.
21671 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21672 bool Lo = Mask.equals(0, 0);
21675 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21676 // is no slower than UNPCKLPD but has the option to fold the input operand
21677 // into even an unaligned memory load.
21678 if (Lo && Subtarget->hasSSE3()) {
21679 Shuffle = X86ISD::MOVDDUP;
21680 ShuffleVT = MVT::v2f64;
21682 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21683 // than the UNPCK variants.
21684 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21685 ShuffleVT = MVT::v4f32;
21687 if (Depth == 1 && Root->getOpcode() == Shuffle)
21688 return false; // Nothing to do!
21689 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21690 DCI.AddToWorklist(Op.getNode());
21691 if (Shuffle == X86ISD::MOVDDUP)
21692 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21694 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21695 DCI.AddToWorklist(Op.getNode());
21696 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21700 if (Subtarget->hasSSE3() &&
21701 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21702 bool Lo = Mask.equals(0, 0, 2, 2);
21703 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21704 MVT ShuffleVT = MVT::v4f32;
21705 if (Depth == 1 && Root->getOpcode() == Shuffle)
21706 return false; // Nothing to do!
21707 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21708 DCI.AddToWorklist(Op.getNode());
21709 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21710 DCI.AddToWorklist(Op.getNode());
21711 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21715 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21716 bool Lo = Mask.equals(0, 0, 1, 1);
21717 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21718 MVT ShuffleVT = MVT::v4f32;
21719 if (Depth == 1 && Root->getOpcode() == Shuffle)
21720 return false; // Nothing to do!
21721 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21722 DCI.AddToWorklist(Op.getNode());
21723 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21724 DCI.AddToWorklist(Op.getNode());
21725 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21731 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21732 // variants as none of these have single-instruction variants that are
21733 // superior to the UNPCK formulation.
21734 if (!FloatDomain &&
21735 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21736 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21737 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21738 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21740 bool Lo = Mask[0] == 0;
21741 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21742 if (Depth == 1 && Root->getOpcode() == Shuffle)
21743 return false; // Nothing to do!
21745 switch (Mask.size()) {
21747 ShuffleVT = MVT::v8i16;
21750 ShuffleVT = MVT::v16i8;
21753 llvm_unreachable("Impossible mask size!");
21755 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21756 DCI.AddToWorklist(Op.getNode());
21757 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21758 DCI.AddToWorklist(Op.getNode());
21759 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21764 // Don't try to re-form single instruction chains under any circumstances now
21765 // that we've done encoding canonicalization for them.
21769 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21770 // can replace them with a single PSHUFB instruction profitably. Intel's
21771 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21772 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21773 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21774 SmallVector<SDValue, 16> PSHUFBMask;
21775 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21776 int Ratio = 16 / Mask.size();
21777 for (unsigned i = 0; i < 16; ++i) {
21778 if (Mask[i / Ratio] == SM_SentinelUndef) {
21779 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21782 int M = Mask[i / Ratio] != SM_SentinelZero
21783 ? Ratio * Mask[i / Ratio] + i % Ratio
21785 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21787 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21788 DCI.AddToWorklist(Op.getNode());
21789 SDValue PSHUFBMaskOp =
21790 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21791 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21792 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21793 DCI.AddToWorklist(Op.getNode());
21794 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21799 // Failed to find any combines.
21803 /// \brief Fully generic combining of x86 shuffle instructions.
21805 /// This should be the last combine run over the x86 shuffle instructions. Once
21806 /// they have been fully optimized, this will recursively consider all chains
21807 /// of single-use shuffle instructions, build a generic model of the cumulative
21808 /// shuffle operation, and check for simpler instructions which implement this
21809 /// operation. We use this primarily for two purposes:
21811 /// 1) Collapse generic shuffles to specialized single instructions when
21812 /// equivalent. In most cases, this is just an encoding size win, but
21813 /// sometimes we will collapse multiple generic shuffles into a single
21814 /// special-purpose shuffle.
21815 /// 2) Look for sequences of shuffle instructions with 3 or more total
21816 /// instructions, and replace them with the slightly more expensive SSSE3
21817 /// PSHUFB instruction if available. We do this as the last combining step
21818 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21819 /// a suitable short sequence of other instructions. The PHUFB will either
21820 /// use a register or have to read from memory and so is slightly (but only
21821 /// slightly) more expensive than the other shuffle instructions.
21823 /// Because this is inherently a quadratic operation (for each shuffle in
21824 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21825 /// This should never be an issue in practice as the shuffle lowering doesn't
21826 /// produce sequences of more than 8 instructions.
21828 /// FIXME: We will currently miss some cases where the redundant shuffling
21829 /// would simplify under the threshold for PSHUFB formation because of
21830 /// combine-ordering. To fix this, we should do the redundant instruction
21831 /// combining in this recursive walk.
21832 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21833 ArrayRef<int> RootMask,
21834 int Depth, bool HasPSHUFB,
21836 TargetLowering::DAGCombinerInfo &DCI,
21837 const X86Subtarget *Subtarget) {
21838 // Bound the depth of our recursive combine because this is ultimately
21839 // quadratic in nature.
21843 // Directly rip through bitcasts to find the underlying operand.
21844 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21845 Op = Op.getOperand(0);
21847 MVT VT = Op.getSimpleValueType();
21848 if (!VT.isVector())
21849 return false; // Bail if we hit a non-vector.
21850 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21851 // version should be added.
21852 if (VT.getSizeInBits() != 128)
21855 assert(Root.getSimpleValueType().isVector() &&
21856 "Shuffles operate on vector types!");
21857 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21858 "Can only combine shuffles of the same vector register size.");
21860 if (!isTargetShuffle(Op.getOpcode()))
21862 SmallVector<int, 16> OpMask;
21864 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21865 // We only can combine unary shuffles which we can decode the mask for.
21866 if (!HaveMask || !IsUnary)
21869 assert(VT.getVectorNumElements() == OpMask.size() &&
21870 "Different mask size from vector size!");
21871 assert(((RootMask.size() > OpMask.size() &&
21872 RootMask.size() % OpMask.size() == 0) ||
21873 (OpMask.size() > RootMask.size() &&
21874 OpMask.size() % RootMask.size() == 0) ||
21875 OpMask.size() == RootMask.size()) &&
21876 "The smaller number of elements must divide the larger.");
21877 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21878 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21879 assert(((RootRatio == 1 && OpRatio == 1) ||
21880 (RootRatio == 1) != (OpRatio == 1)) &&
21881 "Must not have a ratio for both incoming and op masks!");
21883 SmallVector<int, 16> Mask;
21884 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21886 // Merge this shuffle operation's mask into our accumulated mask. Note that
21887 // this shuffle's mask will be the first applied to the input, followed by the
21888 // root mask to get us all the way to the root value arrangement. The reason
21889 // for this order is that we are recursing up the operation chain.
21890 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21891 int RootIdx = i / RootRatio;
21892 if (RootMask[RootIdx] < 0) {
21893 // This is a zero or undef lane, we're done.
21894 Mask.push_back(RootMask[RootIdx]);
21898 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21899 int OpIdx = RootMaskedIdx / OpRatio;
21900 if (OpMask[OpIdx] < 0) {
21901 // The incoming lanes are zero or undef, it doesn't matter which ones we
21903 Mask.push_back(OpMask[OpIdx]);
21907 // Ok, we have non-zero lanes, map them through.
21908 Mask.push_back(OpMask[OpIdx] * OpRatio +
21909 RootMaskedIdx % OpRatio);
21912 // See if we can recurse into the operand to combine more things.
21913 switch (Op.getOpcode()) {
21914 case X86ISD::PSHUFB:
21916 case X86ISD::PSHUFD:
21917 case X86ISD::PSHUFHW:
21918 case X86ISD::PSHUFLW:
21919 if (Op.getOperand(0).hasOneUse() &&
21920 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21921 HasPSHUFB, DAG, DCI, Subtarget))
21925 case X86ISD::UNPCKL:
21926 case X86ISD::UNPCKH:
21927 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21928 // We can't check for single use, we have to check that this shuffle is the only user.
21929 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21930 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21931 HasPSHUFB, DAG, DCI, Subtarget))
21936 // Minor canonicalization of the accumulated shuffle mask to make it easier
21937 // to match below. All this does is detect masks with squential pairs of
21938 // elements, and shrink them to the half-width mask. It does this in a loop
21939 // so it will reduce the size of the mask to the minimal width mask which
21940 // performs an equivalent shuffle.
21941 SmallVector<int, 16> WidenedMask;
21942 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21943 Mask = std::move(WidenedMask);
21944 WidenedMask.clear();
21947 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21951 /// \brief Get the PSHUF-style mask from PSHUF node.
21953 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21954 /// PSHUF-style masks that can be reused with such instructions.
21955 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21956 SmallVector<int, 4> Mask;
21958 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21962 switch (N.getOpcode()) {
21963 case X86ISD::PSHUFD:
21965 case X86ISD::PSHUFLW:
21968 case X86ISD::PSHUFHW:
21969 Mask.erase(Mask.begin(), Mask.begin() + 4);
21970 for (int &M : Mask)
21974 llvm_unreachable("No valid shuffle instruction found!");
21978 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21980 /// We walk up the chain and look for a combinable shuffle, skipping over
21981 /// shuffles that we could hoist this shuffle's transformation past without
21982 /// altering anything.
21984 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21986 TargetLowering::DAGCombinerInfo &DCI) {
21987 assert(N.getOpcode() == X86ISD::PSHUFD &&
21988 "Called with something other than an x86 128-bit half shuffle!");
21991 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21992 // of the shuffles in the chain so that we can form a fresh chain to replace
21994 SmallVector<SDValue, 8> Chain;
21995 SDValue V = N.getOperand(0);
21996 for (; V.hasOneUse(); V = V.getOperand(0)) {
21997 switch (V.getOpcode()) {
21999 return SDValue(); // Nothing combined!
22002 // Skip bitcasts as we always know the type for the target specific
22006 case X86ISD::PSHUFD:
22007 // Found another dword shuffle.
22010 case X86ISD::PSHUFLW:
22011 // Check that the low words (being shuffled) are the identity in the
22012 // dword shuffle, and the high words are self-contained.
22013 if (Mask[0] != 0 || Mask[1] != 1 ||
22014 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22017 Chain.push_back(V);
22020 case X86ISD::PSHUFHW:
22021 // Check that the high words (being shuffled) are the identity in the
22022 // dword shuffle, and the low words are self-contained.
22023 if (Mask[2] != 2 || Mask[3] != 3 ||
22024 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22027 Chain.push_back(V);
22030 case X86ISD::UNPCKL:
22031 case X86ISD::UNPCKH:
22032 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22033 // shuffle into a preceding word shuffle.
22034 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22037 // Search for a half-shuffle which we can combine with.
22038 unsigned CombineOp =
22039 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22040 if (V.getOperand(0) != V.getOperand(1) ||
22041 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22043 Chain.push_back(V);
22044 V = V.getOperand(0);
22046 switch (V.getOpcode()) {
22048 return SDValue(); // Nothing to combine.
22050 case X86ISD::PSHUFLW:
22051 case X86ISD::PSHUFHW:
22052 if (V.getOpcode() == CombineOp)
22055 Chain.push_back(V);
22059 V = V.getOperand(0);
22063 } while (V.hasOneUse());
22066 // Break out of the loop if we break out of the switch.
22070 if (!V.hasOneUse())
22071 // We fell out of the loop without finding a viable combining instruction.
22074 // Merge this node's mask and our incoming mask.
22075 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22076 for (int &M : Mask)
22078 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22079 getV4X86ShuffleImm8ForMask(Mask, DAG));
22081 // Rebuild the chain around this new shuffle.
22082 while (!Chain.empty()) {
22083 SDValue W = Chain.pop_back_val();
22085 if (V.getValueType() != W.getOperand(0).getValueType())
22086 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22088 switch (W.getOpcode()) {
22090 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22092 case X86ISD::UNPCKL:
22093 case X86ISD::UNPCKH:
22094 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22097 case X86ISD::PSHUFD:
22098 case X86ISD::PSHUFLW:
22099 case X86ISD::PSHUFHW:
22100 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22104 if (V.getValueType() != N.getValueType())
22105 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22107 // Return the new chain to replace N.
22111 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22113 /// We walk up the chain, skipping shuffles of the other half and looking
22114 /// through shuffles which switch halves trying to find a shuffle of the same
22115 /// pair of dwords.
22116 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22118 TargetLowering::DAGCombinerInfo &DCI) {
22120 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22121 "Called with something other than an x86 128-bit half shuffle!");
22123 unsigned CombineOpcode = N.getOpcode();
22125 // Walk up a single-use chain looking for a combinable shuffle.
22126 SDValue V = N.getOperand(0);
22127 for (; V.hasOneUse(); V = V.getOperand(0)) {
22128 switch (V.getOpcode()) {
22130 return false; // Nothing combined!
22133 // Skip bitcasts as we always know the type for the target specific
22137 case X86ISD::PSHUFLW:
22138 case X86ISD::PSHUFHW:
22139 if (V.getOpcode() == CombineOpcode)
22142 // Other-half shuffles are no-ops.
22145 // Break out of the loop if we break out of the switch.
22149 if (!V.hasOneUse())
22150 // We fell out of the loop without finding a viable combining instruction.
22153 // Combine away the bottom node as its shuffle will be accumulated into
22154 // a preceding shuffle.
22155 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22157 // Record the old value.
22160 // Merge this node's mask and our incoming mask (adjusted to account for all
22161 // the pshufd instructions encountered).
22162 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22163 for (int &M : Mask)
22165 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22166 getV4X86ShuffleImm8ForMask(Mask, DAG));
22168 // Check that the shuffles didn't cancel each other out. If not, we need to
22169 // combine to the new one.
22171 // Replace the combinable shuffle with the combined one, updating all users
22172 // so that we re-evaluate the chain here.
22173 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22178 /// \brief Try to combine x86 target specific shuffles.
22179 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22180 TargetLowering::DAGCombinerInfo &DCI,
22181 const X86Subtarget *Subtarget) {
22183 MVT VT = N.getSimpleValueType();
22184 SmallVector<int, 4> Mask;
22186 switch (N.getOpcode()) {
22187 case X86ISD::PSHUFD:
22188 case X86ISD::PSHUFLW:
22189 case X86ISD::PSHUFHW:
22190 Mask = getPSHUFShuffleMask(N);
22191 assert(Mask.size() == 4);
22197 // Nuke no-op shuffles that show up after combining.
22198 if (isNoopShuffleMask(Mask))
22199 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22201 // Look for simplifications involving one or two shuffle instructions.
22202 SDValue V = N.getOperand(0);
22203 switch (N.getOpcode()) {
22206 case X86ISD::PSHUFLW:
22207 case X86ISD::PSHUFHW:
22208 assert(VT == MVT::v8i16);
22211 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22212 return SDValue(); // We combined away this shuffle, so we're done.
22214 // See if this reduces to a PSHUFD which is no more expensive and can
22215 // combine with more operations. Note that it has to at least flip the
22216 // dwords as otherwise it would have been removed as a no-op.
22217 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22218 int DMask[] = {0, 1, 2, 3};
22219 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22220 DMask[DOffset + 0] = DOffset + 1;
22221 DMask[DOffset + 1] = DOffset + 0;
22222 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22223 DCI.AddToWorklist(V.getNode());
22224 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22225 getV4X86ShuffleImm8ForMask(DMask, DAG));
22226 DCI.AddToWorklist(V.getNode());
22227 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22230 // Look for shuffle patterns which can be implemented as a single unpack.
22231 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22232 // only works when we have a PSHUFD followed by two half-shuffles.
22233 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22234 (V.getOpcode() == X86ISD::PSHUFLW ||
22235 V.getOpcode() == X86ISD::PSHUFHW) &&
22236 V.getOpcode() != N.getOpcode() &&
22238 SDValue D = V.getOperand(0);
22239 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22240 D = D.getOperand(0);
22241 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22242 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22243 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22244 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22245 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22247 for (int i = 0; i < 4; ++i) {
22248 WordMask[i + NOffset] = Mask[i] + NOffset;
22249 WordMask[i + VOffset] = VMask[i] + VOffset;
22251 // Map the word mask through the DWord mask.
22253 for (int i = 0; i < 8; ++i)
22254 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22255 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22256 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22257 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22258 std::begin(UnpackLoMask)) ||
22259 std::equal(std::begin(MappedMask), std::end(MappedMask),
22260 std::begin(UnpackHiMask))) {
22261 // We can replace all three shuffles with an unpack.
22262 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22263 DCI.AddToWorklist(V.getNode());
22264 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22266 DL, MVT::v8i16, V, V);
22273 case X86ISD::PSHUFD:
22274 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22283 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22285 /// We combine this directly on the abstract vector shuffle nodes so it is
22286 /// easier to generically match. We also insert dummy vector shuffle nodes for
22287 /// the operands which explicitly discard the lanes which are unused by this
22288 /// operation to try to flow through the rest of the combiner the fact that
22289 /// they're unused.
22290 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22292 EVT VT = N->getValueType(0);
22294 // We only handle target-independent shuffles.
22295 // FIXME: It would be easy and harmless to use the target shuffle mask
22296 // extraction tool to support more.
22297 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22300 auto *SVN = cast<ShuffleVectorSDNode>(N);
22301 ArrayRef<int> Mask = SVN->getMask();
22302 SDValue V1 = N->getOperand(0);
22303 SDValue V2 = N->getOperand(1);
22305 // We require the first shuffle operand to be the SUB node, and the second to
22306 // be the ADD node.
22307 // FIXME: We should support the commuted patterns.
22308 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22311 // If there are other uses of these operations we can't fold them.
22312 if (!V1->hasOneUse() || !V2->hasOneUse())
22315 // Ensure that both operations have the same operands. Note that we can
22316 // commute the FADD operands.
22317 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22318 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22319 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22322 // We're looking for blends between FADD and FSUB nodes. We insist on these
22323 // nodes being lined up in a specific expected pattern.
22324 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22325 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22326 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22329 // Only specific types are legal at this point, assert so we notice if and
22330 // when these change.
22331 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22332 VT == MVT::v4f64) &&
22333 "Unknown vector type encountered!");
22335 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22338 /// PerformShuffleCombine - Performs several different shuffle combines.
22339 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22340 TargetLowering::DAGCombinerInfo &DCI,
22341 const X86Subtarget *Subtarget) {
22343 SDValue N0 = N->getOperand(0);
22344 SDValue N1 = N->getOperand(1);
22345 EVT VT = N->getValueType(0);
22347 // Don't create instructions with illegal types after legalize types has run.
22348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22349 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22352 // If we have legalized the vector types, look for blends of FADD and FSUB
22353 // nodes that we can fuse into an ADDSUB node.
22354 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22355 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22358 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22359 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22360 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22361 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22363 // During Type Legalization, when promoting illegal vector types,
22364 // the backend might introduce new shuffle dag nodes and bitcasts.
22366 // This code performs the following transformation:
22367 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22368 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22370 // We do this only if both the bitcast and the BINOP dag nodes have
22371 // one use. Also, perform this transformation only if the new binary
22372 // operation is legal. This is to avoid introducing dag nodes that
22373 // potentially need to be further expanded (or custom lowered) into a
22374 // less optimal sequence of dag nodes.
22375 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22376 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22377 N0.getOpcode() == ISD::BITCAST) {
22378 SDValue BC0 = N0.getOperand(0);
22379 EVT SVT = BC0.getValueType();
22380 unsigned Opcode = BC0.getOpcode();
22381 unsigned NumElts = VT.getVectorNumElements();
22383 if (BC0.hasOneUse() && SVT.isVector() &&
22384 SVT.getVectorNumElements() * 2 == NumElts &&
22385 TLI.isOperationLegal(Opcode, VT)) {
22386 bool CanFold = false;
22398 unsigned SVTNumElts = SVT.getVectorNumElements();
22399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22400 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22401 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22402 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22403 CanFold = SVOp->getMaskElt(i) < 0;
22406 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22407 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22408 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22409 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22414 // Only handle 128 wide vector from here on.
22415 if (!VT.is128BitVector())
22418 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22419 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22420 // consecutive, non-overlapping, and in the right order.
22421 SmallVector<SDValue, 16> Elts;
22422 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22423 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22425 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22429 if (isTargetShuffle(N->getOpcode())) {
22431 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22432 if (Shuffle.getNode())
22435 // Try recursively combining arbitrary sequences of x86 shuffle
22436 // instructions into higher-order shuffles. We do this after combining
22437 // specific PSHUF instruction sequences into their minimal form so that we
22438 // can evaluate how many specialized shuffle instructions are involved in
22439 // a particular chain.
22440 SmallVector<int, 1> NonceMask; // Just a placeholder.
22441 NonceMask.push_back(0);
22442 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22443 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22445 return SDValue(); // This routine will use CombineTo to replace N.
22451 /// PerformTruncateCombine - Converts truncate operation to
22452 /// a sequence of vector shuffle operations.
22453 /// It is possible when we truncate 256-bit vector to 128-bit vector
22454 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22455 TargetLowering::DAGCombinerInfo &DCI,
22456 const X86Subtarget *Subtarget) {
22460 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22461 /// specific shuffle of a load can be folded into a single element load.
22462 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22463 /// shuffles have been custom lowered so we need to handle those here.
22464 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22465 TargetLowering::DAGCombinerInfo &DCI) {
22466 if (DCI.isBeforeLegalizeOps())
22469 SDValue InVec = N->getOperand(0);
22470 SDValue EltNo = N->getOperand(1);
22472 if (!isa<ConstantSDNode>(EltNo))
22475 EVT OriginalVT = InVec.getValueType();
22477 if (InVec.getOpcode() == ISD::BITCAST) {
22478 // Don't duplicate a load with other uses.
22479 if (!InVec.hasOneUse())
22481 EVT BCVT = InVec.getOperand(0).getValueType();
22482 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22484 InVec = InVec.getOperand(0);
22487 EVT CurrentVT = InVec.getValueType();
22489 if (!isTargetShuffle(InVec.getOpcode()))
22492 // Don't duplicate a load with other uses.
22493 if (!InVec.hasOneUse())
22496 SmallVector<int, 16> ShuffleMask;
22498 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22499 ShuffleMask, UnaryShuffle))
22502 // Select the input vector, guarding against out of range extract vector.
22503 unsigned NumElems = CurrentVT.getVectorNumElements();
22504 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22505 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22506 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22507 : InVec.getOperand(1);
22509 // If inputs to shuffle are the same for both ops, then allow 2 uses
22510 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22512 if (LdNode.getOpcode() == ISD::BITCAST) {
22513 // Don't duplicate a load with other uses.
22514 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22517 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22518 LdNode = LdNode.getOperand(0);
22521 if (!ISD::isNormalLoad(LdNode.getNode()))
22524 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22526 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22529 EVT EltVT = N->getValueType(0);
22530 // If there's a bitcast before the shuffle, check if the load type and
22531 // alignment is valid.
22532 unsigned Align = LN0->getAlignment();
22533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22534 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22535 EltVT.getTypeForEVT(*DAG.getContext()));
22537 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22540 // All checks match so transform back to vector_shuffle so that DAG combiner
22541 // can finish the job
22544 // Create shuffle node taking into account the case that its a unary shuffle
22545 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22546 : InVec.getOperand(1);
22547 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22548 InVec.getOperand(0), Shuffle,
22550 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22551 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22555 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22556 /// generation and convert it from being a bunch of shuffles and extracts
22557 /// to a simple store and scalar loads to extract the elements.
22558 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22559 TargetLowering::DAGCombinerInfo &DCI) {
22560 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22561 if (NewOp.getNode())
22564 SDValue InputVector = N->getOperand(0);
22566 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22567 // from mmx to v2i32 has a single usage.
22568 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22569 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22570 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22571 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22572 N->getValueType(0),
22573 InputVector.getNode()->getOperand(0));
22575 // Only operate on vectors of 4 elements, where the alternative shuffling
22576 // gets to be more expensive.
22577 if (InputVector.getValueType() != MVT::v4i32)
22580 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22581 // single use which is a sign-extend or zero-extend, and all elements are
22583 SmallVector<SDNode *, 4> Uses;
22584 unsigned ExtractedElements = 0;
22585 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22586 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22587 if (UI.getUse().getResNo() != InputVector.getResNo())
22590 SDNode *Extract = *UI;
22591 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22594 if (Extract->getValueType(0) != MVT::i32)
22596 if (!Extract->hasOneUse())
22598 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22599 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22601 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22604 // Record which element was extracted.
22605 ExtractedElements |=
22606 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22608 Uses.push_back(Extract);
22611 // If not all the elements were used, this may not be worthwhile.
22612 if (ExtractedElements != 15)
22615 // Ok, we've now decided to do the transformation.
22616 SDLoc dl(InputVector);
22618 // Store the value to a temporary stack slot.
22619 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22620 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22621 MachinePointerInfo(), false, false, 0);
22623 // Replace each use (extract) with a load of the appropriate element.
22624 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22625 UE = Uses.end(); UI != UE; ++UI) {
22626 SDNode *Extract = *UI;
22628 // cOMpute the element's address.
22629 SDValue Idx = Extract->getOperand(1);
22631 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22632 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22634 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22636 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22637 StackPtr, OffsetVal);
22639 // Load the scalar.
22640 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22641 ScalarAddr, MachinePointerInfo(),
22642 false, false, false, 0);
22644 // Replace the exact with the load.
22645 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22648 // The replacement was made in place; don't return anything.
22652 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22653 static std::pair<unsigned, bool>
22654 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22655 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22656 if (!VT.isVector())
22657 return std::make_pair(0, false);
22659 bool NeedSplit = false;
22660 switch (VT.getSimpleVT().SimpleTy) {
22661 default: return std::make_pair(0, false);
22665 if (!Subtarget->hasAVX2())
22667 if (!Subtarget->hasAVX())
22668 return std::make_pair(0, false);
22673 if (!Subtarget->hasSSE2())
22674 return std::make_pair(0, false);
22677 // SSE2 has only a small subset of the operations.
22678 bool hasUnsigned = Subtarget->hasSSE41() ||
22679 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22680 bool hasSigned = Subtarget->hasSSE41() ||
22681 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22683 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22686 // Check for x CC y ? x : y.
22687 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22688 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22693 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22696 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22699 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22702 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22704 // Check for x CC y ? y : x -- a min/max with reversed arms.
22705 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22706 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22711 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22714 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22717 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22720 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22724 return std::make_pair(Opc, NeedSplit);
22728 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22729 const X86Subtarget *Subtarget) {
22731 SDValue Cond = N->getOperand(0);
22732 SDValue LHS = N->getOperand(1);
22733 SDValue RHS = N->getOperand(2);
22735 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22736 SDValue CondSrc = Cond->getOperand(0);
22737 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22738 Cond = CondSrc->getOperand(0);
22741 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22744 // A vselect where all conditions and data are constants can be optimized into
22745 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22746 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22747 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22750 unsigned MaskValue = 0;
22751 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22754 MVT VT = N->getSimpleValueType(0);
22755 unsigned NumElems = VT.getVectorNumElements();
22756 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22757 for (unsigned i = 0; i < NumElems; ++i) {
22758 // Be sure we emit undef where we can.
22759 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22760 ShuffleMask[i] = -1;
22762 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22766 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22768 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22771 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22773 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22774 TargetLowering::DAGCombinerInfo &DCI,
22775 const X86Subtarget *Subtarget) {
22777 SDValue Cond = N->getOperand(0);
22778 // Get the LHS/RHS of the select.
22779 SDValue LHS = N->getOperand(1);
22780 SDValue RHS = N->getOperand(2);
22781 EVT VT = LHS.getValueType();
22782 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22784 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22785 // instructions match the semantics of the common C idiom x<y?x:y but not
22786 // x<=y?x:y, because of how they handle negative zero (which can be
22787 // ignored in unsafe-math mode).
22788 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22789 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22790 (Subtarget->hasSSE2() ||
22791 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22792 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22794 unsigned Opcode = 0;
22795 // Check for x CC y ? x : y.
22796 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22797 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22801 // Converting this to a min would handle NaNs incorrectly, and swapping
22802 // the operands would cause it to handle comparisons between positive
22803 // and negative zero incorrectly.
22804 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22805 if (!DAG.getTarget().Options.UnsafeFPMath &&
22806 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22808 std::swap(LHS, RHS);
22810 Opcode = X86ISD::FMIN;
22813 // Converting this to a min would handle comparisons between positive
22814 // and negative zero incorrectly.
22815 if (!DAG.getTarget().Options.UnsafeFPMath &&
22816 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22818 Opcode = X86ISD::FMIN;
22821 // Converting this to a min would handle both negative zeros and NaNs
22822 // incorrectly, but we can swap the operands to fix both.
22823 std::swap(LHS, RHS);
22827 Opcode = X86ISD::FMIN;
22831 // Converting this to a max would handle comparisons between positive
22832 // and negative zero incorrectly.
22833 if (!DAG.getTarget().Options.UnsafeFPMath &&
22834 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22836 Opcode = X86ISD::FMAX;
22839 // Converting this to a max would handle NaNs incorrectly, and swapping
22840 // the operands would cause it to handle comparisons between positive
22841 // and negative zero incorrectly.
22842 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22843 if (!DAG.getTarget().Options.UnsafeFPMath &&
22844 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22846 std::swap(LHS, RHS);
22848 Opcode = X86ISD::FMAX;
22851 // Converting this to a max would handle both negative zeros and NaNs
22852 // incorrectly, but we can swap the operands to fix both.
22853 std::swap(LHS, RHS);
22857 Opcode = X86ISD::FMAX;
22860 // Check for x CC y ? y : x -- a min/max with reversed arms.
22861 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22862 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22866 // Converting this to a min would handle comparisons between positive
22867 // and negative zero incorrectly, and swapping the operands would
22868 // cause it to handle NaNs incorrectly.
22869 if (!DAG.getTarget().Options.UnsafeFPMath &&
22870 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22871 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22873 std::swap(LHS, RHS);
22875 Opcode = X86ISD::FMIN;
22878 // Converting this to a min would handle NaNs incorrectly.
22879 if (!DAG.getTarget().Options.UnsafeFPMath &&
22880 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22882 Opcode = X86ISD::FMIN;
22885 // Converting this to a min would handle both negative zeros and NaNs
22886 // incorrectly, but we can swap the operands to fix both.
22887 std::swap(LHS, RHS);
22891 Opcode = X86ISD::FMIN;
22895 // Converting this to a max would handle NaNs incorrectly.
22896 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22898 Opcode = X86ISD::FMAX;
22901 // Converting this to a max would handle comparisons between positive
22902 // and negative zero incorrectly, and swapping the operands would
22903 // cause it to handle NaNs incorrectly.
22904 if (!DAG.getTarget().Options.UnsafeFPMath &&
22905 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22906 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22908 std::swap(LHS, RHS);
22910 Opcode = X86ISD::FMAX;
22913 // Converting this to a max would handle both negative zeros and NaNs
22914 // incorrectly, but we can swap the operands to fix both.
22915 std::swap(LHS, RHS);
22919 Opcode = X86ISD::FMAX;
22925 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22928 EVT CondVT = Cond.getValueType();
22929 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22930 CondVT.getVectorElementType() == MVT::i1) {
22931 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22932 // lowering on KNL. In this case we convert it to
22933 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22934 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22935 // Since SKX these selects have a proper lowering.
22936 EVT OpVT = LHS.getValueType();
22937 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22938 (OpVT.getVectorElementType() == MVT::i8 ||
22939 OpVT.getVectorElementType() == MVT::i16) &&
22940 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22941 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22942 DCI.AddToWorklist(Cond.getNode());
22943 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22946 // If this is a select between two integer constants, try to do some
22948 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22949 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22950 // Don't do this for crazy integer types.
22951 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22952 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22953 // so that TrueC (the true value) is larger than FalseC.
22954 bool NeedsCondInvert = false;
22956 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22957 // Efficiently invertible.
22958 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22959 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22960 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22961 NeedsCondInvert = true;
22962 std::swap(TrueC, FalseC);
22965 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22966 if (FalseC->getAPIntValue() == 0 &&
22967 TrueC->getAPIntValue().isPowerOf2()) {
22968 if (NeedsCondInvert) // Invert the condition if needed.
22969 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22970 DAG.getConstant(1, Cond.getValueType()));
22972 // Zero extend the condition if needed.
22973 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22975 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22976 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22977 DAG.getConstant(ShAmt, MVT::i8));
22980 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22981 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22982 if (NeedsCondInvert) // Invert the condition if needed.
22983 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22984 DAG.getConstant(1, Cond.getValueType()));
22986 // Zero extend the condition if needed.
22987 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22988 FalseC->getValueType(0), Cond);
22989 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22990 SDValue(FalseC, 0));
22993 // Optimize cases that will turn into an LEA instruction. This requires
22994 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22995 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22996 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22997 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22999 bool isFastMultiplier = false;
23001 switch ((unsigned char)Diff) {
23003 case 1: // result = add base, cond
23004 case 2: // result = lea base( , cond*2)
23005 case 3: // result = lea base(cond, cond*2)
23006 case 4: // result = lea base( , cond*4)
23007 case 5: // result = lea base(cond, cond*4)
23008 case 8: // result = lea base( , cond*8)
23009 case 9: // result = lea base(cond, cond*8)
23010 isFastMultiplier = true;
23015 if (isFastMultiplier) {
23016 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23017 if (NeedsCondInvert) // Invert the condition if needed.
23018 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23019 DAG.getConstant(1, Cond.getValueType()));
23021 // Zero extend the condition if needed.
23022 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23024 // Scale the condition by the difference.
23026 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23027 DAG.getConstant(Diff, Cond.getValueType()));
23029 // Add the base if non-zero.
23030 if (FalseC->getAPIntValue() != 0)
23031 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23032 SDValue(FalseC, 0));
23039 // Canonicalize max and min:
23040 // (x > y) ? x : y -> (x >= y) ? x : y
23041 // (x < y) ? x : y -> (x <= y) ? x : y
23042 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23043 // the need for an extra compare
23044 // against zero. e.g.
23045 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23047 // testl %edi, %edi
23049 // cmovgl %edi, %eax
23053 // cmovsl %eax, %edi
23054 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23055 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23056 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23057 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23062 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23063 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23064 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23065 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23070 // Early exit check
23071 if (!TLI.isTypeLegal(VT))
23074 // Match VSELECTs into subs with unsigned saturation.
23075 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23076 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23077 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23078 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23079 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23081 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23082 // left side invert the predicate to simplify logic below.
23084 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23086 CC = ISD::getSetCCInverse(CC, true);
23087 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23091 if (Other.getNode() && Other->getNumOperands() == 2 &&
23092 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23093 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23094 SDValue CondRHS = Cond->getOperand(1);
23096 // Look for a general sub with unsigned saturation first.
23097 // x >= y ? x-y : 0 --> subus x, y
23098 // x > y ? x-y : 0 --> subus x, y
23099 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23100 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23101 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23103 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23104 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23105 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23106 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23107 // If the RHS is a constant we have to reverse the const
23108 // canonicalization.
23109 // x > C-1 ? x+-C : 0 --> subus x, C
23110 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23111 CondRHSConst->getAPIntValue() ==
23112 (-OpRHSConst->getAPIntValue() - 1))
23113 return DAG.getNode(
23114 X86ISD::SUBUS, DL, VT, OpLHS,
23115 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23117 // Another special case: If C was a sign bit, the sub has been
23118 // canonicalized into a xor.
23119 // FIXME: Would it be better to use computeKnownBits to determine
23120 // whether it's safe to decanonicalize the xor?
23121 // x s< 0 ? x^C : 0 --> subus x, C
23122 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23123 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23124 OpRHSConst->getAPIntValue().isSignBit())
23125 // Note that we have to rebuild the RHS constant here to ensure we
23126 // don't rely on particular values of undef lanes.
23127 return DAG.getNode(
23128 X86ISD::SUBUS, DL, VT, OpLHS,
23129 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23134 // Try to match a min/max vector operation.
23135 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23136 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23137 unsigned Opc = ret.first;
23138 bool NeedSplit = ret.second;
23140 if (Opc && NeedSplit) {
23141 unsigned NumElems = VT.getVectorNumElements();
23142 // Extract the LHS vectors
23143 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23144 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23146 // Extract the RHS vectors
23147 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23148 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23150 // Create min/max for each subvector
23151 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23152 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23154 // Merge the result
23155 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23157 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23160 // Simplify vector selection if condition value type matches vselect
23162 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23163 assert(Cond.getValueType().isVector() &&
23164 "vector select expects a vector selector!");
23166 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23167 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23169 // Try invert the condition if true value is not all 1s and false value
23171 if (!TValIsAllOnes && !FValIsAllZeros &&
23172 // Check if the selector will be produced by CMPP*/PCMP*
23173 Cond.getOpcode() == ISD::SETCC &&
23174 // Check if SETCC has already been promoted
23175 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23176 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23177 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23179 if (TValIsAllZeros || FValIsAllOnes) {
23180 SDValue CC = Cond.getOperand(2);
23181 ISD::CondCode NewCC =
23182 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23183 Cond.getOperand(0).getValueType().isInteger());
23184 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23185 std::swap(LHS, RHS);
23186 TValIsAllOnes = FValIsAllOnes;
23187 FValIsAllZeros = TValIsAllZeros;
23191 if (TValIsAllOnes || FValIsAllZeros) {
23194 if (TValIsAllOnes && FValIsAllZeros)
23196 else if (TValIsAllOnes)
23197 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23198 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23199 else if (FValIsAllZeros)
23200 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23201 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23203 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23207 // If we know that this node is legal then we know that it is going to be
23208 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23209 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23210 // to simplify previous instructions.
23211 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23212 !DCI.isBeforeLegalize() &&
23213 // We explicitly check against v8i16 and v16i16 because, although
23214 // they're marked as Custom, they might only be legal when Cond is a
23215 // build_vector of constants. This will be taken care in a later
23217 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23218 VT != MVT::v8i16) &&
23219 // Don't optimize vector of constants. Those are handled by
23220 // the generic code and all the bits must be properly set for
23221 // the generic optimizer.
23222 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23223 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23225 // Don't optimize vector selects that map to mask-registers.
23229 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23230 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23232 APInt KnownZero, KnownOne;
23233 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23234 DCI.isBeforeLegalizeOps());
23235 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23236 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23238 // If we changed the computation somewhere in the DAG, this change
23239 // will affect all users of Cond.
23240 // Make sure it is fine and update all the nodes so that we do not
23241 // use the generic VSELECT anymore. Otherwise, we may perform
23242 // wrong optimizations as we messed up with the actual expectation
23243 // for the vector boolean values.
23244 if (Cond != TLO.Old) {
23245 // Check all uses of that condition operand to check whether it will be
23246 // consumed by non-BLEND instructions, which may depend on all bits are
23248 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23250 if (I->getOpcode() != ISD::VSELECT)
23251 // TODO: Add other opcodes eventually lowered into BLEND.
23254 // Update all the users of the condition, before committing the change,
23255 // so that the VSELECT optimizations that expect the correct vector
23256 // boolean value will not be triggered.
23257 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23259 DAG.ReplaceAllUsesOfValueWith(
23261 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23262 Cond, I->getOperand(1), I->getOperand(2)));
23263 DCI.CommitTargetLoweringOpt(TLO);
23266 // At this point, only Cond is changed. Change the condition
23267 // just for N to keep the opportunity to optimize all other
23268 // users their own way.
23269 DAG.ReplaceAllUsesOfValueWith(
23271 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23272 TLO.New, N->getOperand(1), N->getOperand(2)));
23277 // We should generate an X86ISD::BLENDI from a vselect if its argument
23278 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23279 // constants. This specific pattern gets generated when we split a
23280 // selector for a 512 bit vector in a machine without AVX512 (but with
23281 // 256-bit vectors), during legalization:
23283 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23285 // Iff we find this pattern and the build_vectors are built from
23286 // constants, we translate the vselect into a shuffle_vector that we
23287 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23288 if ((N->getOpcode() == ISD::VSELECT ||
23289 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23290 !DCI.isBeforeLegalize()) {
23291 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23292 if (Shuffle.getNode())
23299 // Check whether a boolean test is testing a boolean value generated by
23300 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23303 // Simplify the following patterns:
23304 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23305 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23306 // to (Op EFLAGS Cond)
23308 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23309 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23310 // to (Op EFLAGS !Cond)
23312 // where Op could be BRCOND or CMOV.
23314 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23315 // Quit if not CMP and SUB with its value result used.
23316 if (Cmp.getOpcode() != X86ISD::CMP &&
23317 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23320 // Quit if not used as a boolean value.
23321 if (CC != X86::COND_E && CC != X86::COND_NE)
23324 // Check CMP operands. One of them should be 0 or 1 and the other should be
23325 // an SetCC or extended from it.
23326 SDValue Op1 = Cmp.getOperand(0);
23327 SDValue Op2 = Cmp.getOperand(1);
23330 const ConstantSDNode* C = nullptr;
23331 bool needOppositeCond = (CC == X86::COND_E);
23332 bool checkAgainstTrue = false; // Is it a comparison against 1?
23334 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23336 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23338 else // Quit if all operands are not constants.
23341 if (C->getZExtValue() == 1) {
23342 needOppositeCond = !needOppositeCond;
23343 checkAgainstTrue = true;
23344 } else if (C->getZExtValue() != 0)
23345 // Quit if the constant is neither 0 or 1.
23348 bool truncatedToBoolWithAnd = false;
23349 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23350 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23351 SetCC.getOpcode() == ISD::TRUNCATE ||
23352 SetCC.getOpcode() == ISD::AND) {
23353 if (SetCC.getOpcode() == ISD::AND) {
23355 ConstantSDNode *CS;
23356 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23357 CS->getZExtValue() == 1)
23359 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23360 CS->getZExtValue() == 1)
23364 SetCC = SetCC.getOperand(OpIdx);
23365 truncatedToBoolWithAnd = true;
23367 SetCC = SetCC.getOperand(0);
23370 switch (SetCC.getOpcode()) {
23371 case X86ISD::SETCC_CARRY:
23372 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23373 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23374 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23375 // truncated to i1 using 'and'.
23376 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23378 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23379 "Invalid use of SETCC_CARRY!");
23381 case X86ISD::SETCC:
23382 // Set the condition code or opposite one if necessary.
23383 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23384 if (needOppositeCond)
23385 CC = X86::GetOppositeBranchCondition(CC);
23386 return SetCC.getOperand(1);
23387 case X86ISD::CMOV: {
23388 // Check whether false/true value has canonical one, i.e. 0 or 1.
23389 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23390 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23391 // Quit if true value is not a constant.
23394 // Quit if false value is not a constant.
23396 SDValue Op = SetCC.getOperand(0);
23397 // Skip 'zext' or 'trunc' node.
23398 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23399 Op.getOpcode() == ISD::TRUNCATE)
23400 Op = Op.getOperand(0);
23401 // A special case for rdrand/rdseed, where 0 is set if false cond is
23403 if ((Op.getOpcode() != X86ISD::RDRAND &&
23404 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23407 // Quit if false value is not the constant 0 or 1.
23408 bool FValIsFalse = true;
23409 if (FVal && FVal->getZExtValue() != 0) {
23410 if (FVal->getZExtValue() != 1)
23412 // If FVal is 1, opposite cond is needed.
23413 needOppositeCond = !needOppositeCond;
23414 FValIsFalse = false;
23416 // Quit if TVal is not the constant opposite of FVal.
23417 if (FValIsFalse && TVal->getZExtValue() != 1)
23419 if (!FValIsFalse && TVal->getZExtValue() != 0)
23421 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23422 if (needOppositeCond)
23423 CC = X86::GetOppositeBranchCondition(CC);
23424 return SetCC.getOperand(3);
23431 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23432 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23433 TargetLowering::DAGCombinerInfo &DCI,
23434 const X86Subtarget *Subtarget) {
23437 // If the flag operand isn't dead, don't touch this CMOV.
23438 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23441 SDValue FalseOp = N->getOperand(0);
23442 SDValue TrueOp = N->getOperand(1);
23443 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23444 SDValue Cond = N->getOperand(3);
23446 if (CC == X86::COND_E || CC == X86::COND_NE) {
23447 switch (Cond.getOpcode()) {
23451 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23452 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23453 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23459 Flags = checkBoolTestSetCCCombine(Cond, CC);
23460 if (Flags.getNode() &&
23461 // Extra check as FCMOV only supports a subset of X86 cond.
23462 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23463 SDValue Ops[] = { FalseOp, TrueOp,
23464 DAG.getConstant(CC, MVT::i8), Flags };
23465 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23468 // If this is a select between two integer constants, try to do some
23469 // optimizations. Note that the operands are ordered the opposite of SELECT
23471 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23472 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23473 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23474 // larger than FalseC (the false value).
23475 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23476 CC = X86::GetOppositeBranchCondition(CC);
23477 std::swap(TrueC, FalseC);
23478 std::swap(TrueOp, FalseOp);
23481 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23482 // This is efficient for any integer data type (including i8/i16) and
23484 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23485 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23486 DAG.getConstant(CC, MVT::i8), Cond);
23488 // Zero extend the condition if needed.
23489 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23491 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23492 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23493 DAG.getConstant(ShAmt, MVT::i8));
23494 if (N->getNumValues() == 2) // Dead flag value?
23495 return DCI.CombineTo(N, Cond, SDValue());
23499 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23500 // for any integer data type, including i8/i16.
23501 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23502 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23503 DAG.getConstant(CC, MVT::i8), Cond);
23505 // Zero extend the condition if needed.
23506 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23507 FalseC->getValueType(0), Cond);
23508 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23509 SDValue(FalseC, 0));
23511 if (N->getNumValues() == 2) // Dead flag value?
23512 return DCI.CombineTo(N, Cond, SDValue());
23516 // Optimize cases that will turn into an LEA instruction. This requires
23517 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23518 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23519 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23520 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23522 bool isFastMultiplier = false;
23524 switch ((unsigned char)Diff) {
23526 case 1: // result = add base, cond
23527 case 2: // result = lea base( , cond*2)
23528 case 3: // result = lea base(cond, cond*2)
23529 case 4: // result = lea base( , cond*4)
23530 case 5: // result = lea base(cond, cond*4)
23531 case 8: // result = lea base( , cond*8)
23532 case 9: // result = lea base(cond, cond*8)
23533 isFastMultiplier = true;
23538 if (isFastMultiplier) {
23539 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23540 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23541 DAG.getConstant(CC, MVT::i8), Cond);
23542 // Zero extend the condition if needed.
23543 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23545 // Scale the condition by the difference.
23547 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23548 DAG.getConstant(Diff, Cond.getValueType()));
23550 // Add the base if non-zero.
23551 if (FalseC->getAPIntValue() != 0)
23552 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23553 SDValue(FalseC, 0));
23554 if (N->getNumValues() == 2) // Dead flag value?
23555 return DCI.CombineTo(N, Cond, SDValue());
23562 // Handle these cases:
23563 // (select (x != c), e, c) -> select (x != c), e, x),
23564 // (select (x == c), c, e) -> select (x == c), x, e)
23565 // where the c is an integer constant, and the "select" is the combination
23566 // of CMOV and CMP.
23568 // The rationale for this change is that the conditional-move from a constant
23569 // needs two instructions, however, conditional-move from a register needs
23570 // only one instruction.
23572 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23573 // some instruction-combining opportunities. This opt needs to be
23574 // postponed as late as possible.
23576 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23577 // the DCI.xxxx conditions are provided to postpone the optimization as
23578 // late as possible.
23580 ConstantSDNode *CmpAgainst = nullptr;
23581 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23582 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23583 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23585 if (CC == X86::COND_NE &&
23586 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23587 CC = X86::GetOppositeBranchCondition(CC);
23588 std::swap(TrueOp, FalseOp);
23591 if (CC == X86::COND_E &&
23592 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23593 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23594 DAG.getConstant(CC, MVT::i8), Cond };
23595 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23603 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23604 const X86Subtarget *Subtarget) {
23605 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23607 default: return SDValue();
23608 // SSE/AVX/AVX2 blend intrinsics.
23609 case Intrinsic::x86_avx2_pblendvb:
23610 case Intrinsic::x86_avx2_pblendw:
23611 case Intrinsic::x86_avx2_pblendd_128:
23612 case Intrinsic::x86_avx2_pblendd_256:
23613 // Don't try to simplify this intrinsic if we don't have AVX2.
23614 if (!Subtarget->hasAVX2())
23617 case Intrinsic::x86_avx_blend_pd_256:
23618 case Intrinsic::x86_avx_blend_ps_256:
23619 case Intrinsic::x86_avx_blendv_pd_256:
23620 case Intrinsic::x86_avx_blendv_ps_256:
23621 // Don't try to simplify this intrinsic if we don't have AVX.
23622 if (!Subtarget->hasAVX())
23625 case Intrinsic::x86_sse41_pblendw:
23626 case Intrinsic::x86_sse41_blendpd:
23627 case Intrinsic::x86_sse41_blendps:
23628 case Intrinsic::x86_sse41_blendvps:
23629 case Intrinsic::x86_sse41_blendvpd:
23630 case Intrinsic::x86_sse41_pblendvb: {
23631 SDValue Op0 = N->getOperand(1);
23632 SDValue Op1 = N->getOperand(2);
23633 SDValue Mask = N->getOperand(3);
23635 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23636 if (!Subtarget->hasSSE41())
23639 // fold (blend A, A, Mask) -> A
23642 // fold (blend A, B, allZeros) -> A
23643 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23645 // fold (blend A, B, allOnes) -> B
23646 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23649 // Simplify the case where the mask is a constant i32 value.
23650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23651 if (C->isNullValue())
23653 if (C->isAllOnesValue())
23660 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23661 case Intrinsic::x86_sse2_psrai_w:
23662 case Intrinsic::x86_sse2_psrai_d:
23663 case Intrinsic::x86_avx2_psrai_w:
23664 case Intrinsic::x86_avx2_psrai_d:
23665 case Intrinsic::x86_sse2_psra_w:
23666 case Intrinsic::x86_sse2_psra_d:
23667 case Intrinsic::x86_avx2_psra_w:
23668 case Intrinsic::x86_avx2_psra_d: {
23669 SDValue Op0 = N->getOperand(1);
23670 SDValue Op1 = N->getOperand(2);
23671 EVT VT = Op0.getValueType();
23672 assert(VT.isVector() && "Expected a vector type!");
23674 if (isa<BuildVectorSDNode>(Op1))
23675 Op1 = Op1.getOperand(0);
23677 if (!isa<ConstantSDNode>(Op1))
23680 EVT SVT = VT.getVectorElementType();
23681 unsigned SVTBits = SVT.getSizeInBits();
23683 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23684 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23685 uint64_t ShAmt = C.getZExtValue();
23687 // Don't try to convert this shift into a ISD::SRA if the shift
23688 // count is bigger than or equal to the element size.
23689 if (ShAmt >= SVTBits)
23692 // Trivial case: if the shift count is zero, then fold this
23693 // into the first operand.
23697 // Replace this packed shift intrinsic with a target independent
23699 SDValue Splat = DAG.getConstant(C, VT);
23700 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23705 /// PerformMulCombine - Optimize a single multiply with constant into two
23706 /// in order to implement it with two cheaper instructions, e.g.
23707 /// LEA + SHL, LEA + LEA.
23708 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23709 TargetLowering::DAGCombinerInfo &DCI) {
23710 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23713 EVT VT = N->getValueType(0);
23714 if (VT != MVT::i64)
23717 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23720 uint64_t MulAmt = C->getZExtValue();
23721 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23724 uint64_t MulAmt1 = 0;
23725 uint64_t MulAmt2 = 0;
23726 if ((MulAmt % 9) == 0) {
23728 MulAmt2 = MulAmt / 9;
23729 } else if ((MulAmt % 5) == 0) {
23731 MulAmt2 = MulAmt / 5;
23732 } else if ((MulAmt % 3) == 0) {
23734 MulAmt2 = MulAmt / 3;
23737 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23740 if (isPowerOf2_64(MulAmt2) &&
23741 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23742 // If second multiplifer is pow2, issue it first. We want the multiply by
23743 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23745 std::swap(MulAmt1, MulAmt2);
23748 if (isPowerOf2_64(MulAmt1))
23749 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23750 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23752 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23753 DAG.getConstant(MulAmt1, VT));
23755 if (isPowerOf2_64(MulAmt2))
23756 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23757 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23759 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23760 DAG.getConstant(MulAmt2, VT));
23762 // Do not add new nodes to DAG combiner worklist.
23763 DCI.CombineTo(N, NewMul, false);
23768 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23769 SDValue N0 = N->getOperand(0);
23770 SDValue N1 = N->getOperand(1);
23771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23772 EVT VT = N0.getValueType();
23774 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23775 // since the result of setcc_c is all zero's or all ones.
23776 if (VT.isInteger() && !VT.isVector() &&
23777 N1C && N0.getOpcode() == ISD::AND &&
23778 N0.getOperand(1).getOpcode() == ISD::Constant) {
23779 SDValue N00 = N0.getOperand(0);
23780 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23781 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23782 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23783 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23784 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23785 APInt ShAmt = N1C->getAPIntValue();
23786 Mask = Mask.shl(ShAmt);
23788 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23789 N00, DAG.getConstant(Mask, VT));
23793 // Hardware support for vector shifts is sparse which makes us scalarize the
23794 // vector operations in many cases. Also, on sandybridge ADD is faster than
23796 // (shl V, 1) -> add V,V
23797 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23798 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23799 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23800 // We shift all of the values by one. In many cases we do not have
23801 // hardware support for this operation. This is better expressed as an ADD
23803 if (N1SplatC->getZExtValue() == 1)
23804 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23810 /// \brief Returns a vector of 0s if the node in input is a vector logical
23811 /// shift by a constant amount which is known to be bigger than or equal
23812 /// to the vector element size in bits.
23813 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23814 const X86Subtarget *Subtarget) {
23815 EVT VT = N->getValueType(0);
23817 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23818 (!Subtarget->hasInt256() ||
23819 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23822 SDValue Amt = N->getOperand(1);
23824 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23825 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23826 APInt ShiftAmt = AmtSplat->getAPIntValue();
23827 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23829 // SSE2/AVX2 logical shifts always return a vector of 0s
23830 // if the shift amount is bigger than or equal to
23831 // the element size. The constant shift amount will be
23832 // encoded as a 8-bit immediate.
23833 if (ShiftAmt.trunc(8).uge(MaxAmount))
23834 return getZeroVector(VT, Subtarget, DAG, DL);
23840 /// PerformShiftCombine - Combine shifts.
23841 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23842 TargetLowering::DAGCombinerInfo &DCI,
23843 const X86Subtarget *Subtarget) {
23844 if (N->getOpcode() == ISD::SHL) {
23845 SDValue V = PerformSHLCombine(N, DAG);
23846 if (V.getNode()) return V;
23849 if (N->getOpcode() != ISD::SRA) {
23850 // Try to fold this logical shift into a zero vector.
23851 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23852 if (V.getNode()) return V;
23858 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23859 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23860 // and friends. Likewise for OR -> CMPNEQSS.
23861 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23862 TargetLowering::DAGCombinerInfo &DCI,
23863 const X86Subtarget *Subtarget) {
23866 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23867 // we're requiring SSE2 for both.
23868 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23869 SDValue N0 = N->getOperand(0);
23870 SDValue N1 = N->getOperand(1);
23871 SDValue CMP0 = N0->getOperand(1);
23872 SDValue CMP1 = N1->getOperand(1);
23875 // The SETCCs should both refer to the same CMP.
23876 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23879 SDValue CMP00 = CMP0->getOperand(0);
23880 SDValue CMP01 = CMP0->getOperand(1);
23881 EVT VT = CMP00.getValueType();
23883 if (VT == MVT::f32 || VT == MVT::f64) {
23884 bool ExpectingFlags = false;
23885 // Check for any users that want flags:
23886 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23887 !ExpectingFlags && UI != UE; ++UI)
23888 switch (UI->getOpcode()) {
23893 ExpectingFlags = true;
23895 case ISD::CopyToReg:
23896 case ISD::SIGN_EXTEND:
23897 case ISD::ZERO_EXTEND:
23898 case ISD::ANY_EXTEND:
23902 if (!ExpectingFlags) {
23903 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23904 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23906 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23907 X86::CondCode tmp = cc0;
23912 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23913 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23914 // FIXME: need symbolic constants for these magic numbers.
23915 // See X86ATTInstPrinter.cpp:printSSECC().
23916 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23917 if (Subtarget->hasAVX512()) {
23918 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23919 CMP01, DAG.getConstant(x86cc, MVT::i8));
23920 if (N->getValueType(0) != MVT::i1)
23921 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23925 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23926 CMP00.getValueType(), CMP00, CMP01,
23927 DAG.getConstant(x86cc, MVT::i8));
23929 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23930 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23932 if (is64BitFP && !Subtarget->is64Bit()) {
23933 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23934 // 64-bit integer, since that's not a legal type. Since
23935 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23936 // bits, but can do this little dance to extract the lowest 32 bits
23937 // and work with those going forward.
23938 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23940 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23942 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23943 Vector32, DAG.getIntPtrConstant(0));
23947 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23948 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23949 DAG.getConstant(1, IntVT));
23950 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23951 return OneBitOfTruth;
23959 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23960 /// so it can be folded inside ANDNP.
23961 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23962 EVT VT = N->getValueType(0);
23964 // Match direct AllOnes for 128 and 256-bit vectors
23965 if (ISD::isBuildVectorAllOnes(N))
23968 // Look through a bit convert.
23969 if (N->getOpcode() == ISD::BITCAST)
23970 N = N->getOperand(0).getNode();
23972 // Sometimes the operand may come from a insert_subvector building a 256-bit
23974 if (VT.is256BitVector() &&
23975 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23976 SDValue V1 = N->getOperand(0);
23977 SDValue V2 = N->getOperand(1);
23979 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23980 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23981 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23982 ISD::isBuildVectorAllOnes(V2.getNode()))
23989 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23990 // register. In most cases we actually compare or select YMM-sized registers
23991 // and mixing the two types creates horrible code. This method optimizes
23992 // some of the transition sequences.
23993 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23994 TargetLowering::DAGCombinerInfo &DCI,
23995 const X86Subtarget *Subtarget) {
23996 EVT VT = N->getValueType(0);
23997 if (!VT.is256BitVector())
24000 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24001 N->getOpcode() == ISD::ZERO_EXTEND ||
24002 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24004 SDValue Narrow = N->getOperand(0);
24005 EVT NarrowVT = Narrow->getValueType(0);
24006 if (!NarrowVT.is128BitVector())
24009 if (Narrow->getOpcode() != ISD::XOR &&
24010 Narrow->getOpcode() != ISD::AND &&
24011 Narrow->getOpcode() != ISD::OR)
24014 SDValue N0 = Narrow->getOperand(0);
24015 SDValue N1 = Narrow->getOperand(1);
24018 // The Left side has to be a trunc.
24019 if (N0.getOpcode() != ISD::TRUNCATE)
24022 // The type of the truncated inputs.
24023 EVT WideVT = N0->getOperand(0)->getValueType(0);
24027 // The right side has to be a 'trunc' or a constant vector.
24028 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24029 ConstantSDNode *RHSConstSplat = nullptr;
24030 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24031 RHSConstSplat = RHSBV->getConstantSplatNode();
24032 if (!RHSTrunc && !RHSConstSplat)
24035 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24037 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24040 // Set N0 and N1 to hold the inputs to the new wide operation.
24041 N0 = N0->getOperand(0);
24042 if (RHSConstSplat) {
24043 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24044 SDValue(RHSConstSplat, 0));
24045 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24046 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24047 } else if (RHSTrunc) {
24048 N1 = N1->getOperand(0);
24051 // Generate the wide operation.
24052 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24053 unsigned Opcode = N->getOpcode();
24055 case ISD::ANY_EXTEND:
24057 case ISD::ZERO_EXTEND: {
24058 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24059 APInt Mask = APInt::getAllOnesValue(InBits);
24060 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24061 return DAG.getNode(ISD::AND, DL, VT,
24062 Op, DAG.getConstant(Mask, VT));
24064 case ISD::SIGN_EXTEND:
24065 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24066 Op, DAG.getValueType(NarrowVT));
24068 llvm_unreachable("Unexpected opcode");
24072 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24073 TargetLowering::DAGCombinerInfo &DCI,
24074 const X86Subtarget *Subtarget) {
24075 EVT VT = N->getValueType(0);
24076 if (DCI.isBeforeLegalizeOps())
24079 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24083 // Create BEXTR instructions
24084 // BEXTR is ((X >> imm) & (2**size-1))
24085 if (VT == MVT::i32 || VT == MVT::i64) {
24086 SDValue N0 = N->getOperand(0);
24087 SDValue N1 = N->getOperand(1);
24090 // Check for BEXTR.
24091 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24092 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24093 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24094 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24095 if (MaskNode && ShiftNode) {
24096 uint64_t Mask = MaskNode->getZExtValue();
24097 uint64_t Shift = ShiftNode->getZExtValue();
24098 if (isMask_64(Mask)) {
24099 uint64_t MaskSize = CountPopulation_64(Mask);
24100 if (Shift + MaskSize <= VT.getSizeInBits())
24101 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24102 DAG.getConstant(Shift | (MaskSize << 8), VT));
24110 // Want to form ANDNP nodes:
24111 // 1) In the hopes of then easily combining them with OR and AND nodes
24112 // to form PBLEND/PSIGN.
24113 // 2) To match ANDN packed intrinsics
24114 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24117 SDValue N0 = N->getOperand(0);
24118 SDValue N1 = N->getOperand(1);
24121 // Check LHS for vnot
24122 if (N0.getOpcode() == ISD::XOR &&
24123 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24124 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24125 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24127 // Check RHS for vnot
24128 if (N1.getOpcode() == ISD::XOR &&
24129 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24130 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24131 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24136 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24137 TargetLowering::DAGCombinerInfo &DCI,
24138 const X86Subtarget *Subtarget) {
24139 if (DCI.isBeforeLegalizeOps())
24142 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24146 SDValue N0 = N->getOperand(0);
24147 SDValue N1 = N->getOperand(1);
24148 EVT VT = N->getValueType(0);
24150 // look for psign/blend
24151 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24152 if (!Subtarget->hasSSSE3() ||
24153 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24156 // Canonicalize pandn to RHS
24157 if (N0.getOpcode() == X86ISD::ANDNP)
24159 // or (and (m, y), (pandn m, x))
24160 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24161 SDValue Mask = N1.getOperand(0);
24162 SDValue X = N1.getOperand(1);
24164 if (N0.getOperand(0) == Mask)
24165 Y = N0.getOperand(1);
24166 if (N0.getOperand(1) == Mask)
24167 Y = N0.getOperand(0);
24169 // Check to see if the mask appeared in both the AND and ANDNP and
24173 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24174 // Look through mask bitcast.
24175 if (Mask.getOpcode() == ISD::BITCAST)
24176 Mask = Mask.getOperand(0);
24177 if (X.getOpcode() == ISD::BITCAST)
24178 X = X.getOperand(0);
24179 if (Y.getOpcode() == ISD::BITCAST)
24180 Y = Y.getOperand(0);
24182 EVT MaskVT = Mask.getValueType();
24184 // Validate that the Mask operand is a vector sra node.
24185 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24186 // there is no psrai.b
24187 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24188 unsigned SraAmt = ~0;
24189 if (Mask.getOpcode() == ISD::SRA) {
24190 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24191 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24192 SraAmt = AmtConst->getZExtValue();
24193 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24194 SDValue SraC = Mask.getOperand(1);
24195 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24197 if ((SraAmt + 1) != EltBits)
24202 // Now we know we at least have a plendvb with the mask val. See if
24203 // we can form a psignb/w/d.
24204 // psign = x.type == y.type == mask.type && y = sub(0, x);
24205 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24206 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24207 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24208 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24209 "Unsupported VT for PSIGN");
24210 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24211 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24213 // PBLENDVB only available on SSE 4.1
24214 if (!Subtarget->hasSSE41())
24217 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24219 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24220 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24221 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24222 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24223 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24227 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24230 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24231 MachineFunction &MF = DAG.getMachineFunction();
24232 bool OptForSize = MF.getFunction()->getAttributes().
24233 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24235 // SHLD/SHRD instructions have lower register pressure, but on some
24236 // platforms they have higher latency than the equivalent
24237 // series of shifts/or that would otherwise be generated.
24238 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24239 // have higher latencies and we are not optimizing for size.
24240 if (!OptForSize && Subtarget->isSHLDSlow())
24243 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24245 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24247 if (!N0.hasOneUse() || !N1.hasOneUse())
24250 SDValue ShAmt0 = N0.getOperand(1);
24251 if (ShAmt0.getValueType() != MVT::i8)
24253 SDValue ShAmt1 = N1.getOperand(1);
24254 if (ShAmt1.getValueType() != MVT::i8)
24256 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24257 ShAmt0 = ShAmt0.getOperand(0);
24258 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24259 ShAmt1 = ShAmt1.getOperand(0);
24262 unsigned Opc = X86ISD::SHLD;
24263 SDValue Op0 = N0.getOperand(0);
24264 SDValue Op1 = N1.getOperand(0);
24265 if (ShAmt0.getOpcode() == ISD::SUB) {
24266 Opc = X86ISD::SHRD;
24267 std::swap(Op0, Op1);
24268 std::swap(ShAmt0, ShAmt1);
24271 unsigned Bits = VT.getSizeInBits();
24272 if (ShAmt1.getOpcode() == ISD::SUB) {
24273 SDValue Sum = ShAmt1.getOperand(0);
24274 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24275 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24276 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24277 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24278 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24279 return DAG.getNode(Opc, DL, VT,
24281 DAG.getNode(ISD::TRUNCATE, DL,
24284 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24285 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24287 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24288 return DAG.getNode(Opc, DL, VT,
24289 N0.getOperand(0), N1.getOperand(0),
24290 DAG.getNode(ISD::TRUNCATE, DL,
24297 // Generate NEG and CMOV for integer abs.
24298 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24299 EVT VT = N->getValueType(0);
24301 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24302 // 8-bit integer abs to NEG and CMOV.
24303 if (VT.isInteger() && VT.getSizeInBits() == 8)
24306 SDValue N0 = N->getOperand(0);
24307 SDValue N1 = N->getOperand(1);
24310 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24311 // and change it to SUB and CMOV.
24312 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24313 N0.getOpcode() == ISD::ADD &&
24314 N0.getOperand(1) == N1 &&
24315 N1.getOpcode() == ISD::SRA &&
24316 N1.getOperand(0) == N0.getOperand(0))
24317 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24318 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24319 // Generate SUB & CMOV.
24320 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24321 DAG.getConstant(0, VT), N0.getOperand(0));
24323 SDValue Ops[] = { N0.getOperand(0), Neg,
24324 DAG.getConstant(X86::COND_GE, MVT::i8),
24325 SDValue(Neg.getNode(), 1) };
24326 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24331 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24332 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24333 TargetLowering::DAGCombinerInfo &DCI,
24334 const X86Subtarget *Subtarget) {
24335 if (DCI.isBeforeLegalizeOps())
24338 if (Subtarget->hasCMov()) {
24339 SDValue RV = performIntegerAbsCombine(N, DAG);
24347 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24348 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24349 TargetLowering::DAGCombinerInfo &DCI,
24350 const X86Subtarget *Subtarget) {
24351 LoadSDNode *Ld = cast<LoadSDNode>(N);
24352 EVT RegVT = Ld->getValueType(0);
24353 EVT MemVT = Ld->getMemoryVT();
24355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24357 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24358 // into two 16-byte operations.
24359 ISD::LoadExtType Ext = Ld->getExtensionType();
24360 unsigned Alignment = Ld->getAlignment();
24361 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24362 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24363 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24364 unsigned NumElems = RegVT.getVectorNumElements();
24368 SDValue Ptr = Ld->getBasePtr();
24369 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24371 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24373 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24374 Ld->getPointerInfo(), Ld->isVolatile(),
24375 Ld->isNonTemporal(), Ld->isInvariant(),
24377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24378 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24379 Ld->getPointerInfo(), Ld->isVolatile(),
24380 Ld->isNonTemporal(), Ld->isInvariant(),
24381 std::min(16U, Alignment));
24382 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24384 Load2.getValue(1));
24386 SDValue NewVec = DAG.getUNDEF(RegVT);
24387 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24388 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24389 return DCI.CombineTo(N, NewVec, TF, true);
24395 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24396 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24397 const X86Subtarget *Subtarget) {
24398 StoreSDNode *St = cast<StoreSDNode>(N);
24399 EVT VT = St->getValue().getValueType();
24400 EVT StVT = St->getMemoryVT();
24402 SDValue StoredVal = St->getOperand(1);
24403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24405 // If we are saving a concatenation of two XMM registers and 32-byte stores
24406 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24407 unsigned Alignment = St->getAlignment();
24408 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24409 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24410 StVT == VT && !IsAligned) {
24411 unsigned NumElems = VT.getVectorNumElements();
24415 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24416 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24418 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24419 SDValue Ptr0 = St->getBasePtr();
24420 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24422 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24423 St->getPointerInfo(), St->isVolatile(),
24424 St->isNonTemporal(), Alignment);
24425 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24426 St->getPointerInfo(), St->isVolatile(),
24427 St->isNonTemporal(),
24428 std::min(16U, Alignment));
24429 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24432 // Optimize trunc store (of multiple scalars) to shuffle and store.
24433 // First, pack all of the elements in one place. Next, store to memory
24434 // in fewer chunks.
24435 if (St->isTruncatingStore() && VT.isVector()) {
24436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24437 unsigned NumElems = VT.getVectorNumElements();
24438 assert(StVT != VT && "Cannot truncate to the same type");
24439 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24440 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24442 // From, To sizes and ElemCount must be pow of two
24443 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24444 // We are going to use the original vector elt for storing.
24445 // Accumulated smaller vector elements must be a multiple of the store size.
24446 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24448 unsigned SizeRatio = FromSz / ToSz;
24450 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24452 // Create a type on which we perform the shuffle
24453 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24454 StVT.getScalarType(), NumElems*SizeRatio);
24456 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24458 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24459 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24460 for (unsigned i = 0; i != NumElems; ++i)
24461 ShuffleVec[i] = i * SizeRatio;
24463 // Can't shuffle using an illegal type.
24464 if (!TLI.isTypeLegal(WideVecVT))
24467 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24468 DAG.getUNDEF(WideVecVT),
24470 // At this point all of the data is stored at the bottom of the
24471 // register. We now need to save it to mem.
24473 // Find the largest store unit
24474 MVT StoreType = MVT::i8;
24475 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24476 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24477 MVT Tp = (MVT::SimpleValueType)tp;
24478 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24482 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24483 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24484 (64 <= NumElems * ToSz))
24485 StoreType = MVT::f64;
24487 // Bitcast the original vector into a vector of store-size units
24488 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24489 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24490 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24491 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24492 SmallVector<SDValue, 8> Chains;
24493 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24494 TLI.getPointerTy());
24495 SDValue Ptr = St->getBasePtr();
24497 // Perform one or more big stores into memory.
24498 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24499 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24500 StoreType, ShuffWide,
24501 DAG.getIntPtrConstant(i));
24502 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24503 St->getPointerInfo(), St->isVolatile(),
24504 St->isNonTemporal(), St->getAlignment());
24505 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24506 Chains.push_back(Ch);
24509 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24512 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24513 // the FP state in cases where an emms may be missing.
24514 // A preferable solution to the general problem is to figure out the right
24515 // places to insert EMMS. This qualifies as a quick hack.
24517 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24518 if (VT.getSizeInBits() != 64)
24521 const Function *F = DAG.getMachineFunction().getFunction();
24522 bool NoImplicitFloatOps = F->getAttributes().
24523 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24524 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24525 && Subtarget->hasSSE2();
24526 if ((VT.isVector() ||
24527 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24528 isa<LoadSDNode>(St->getValue()) &&
24529 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24530 St->getChain().hasOneUse() && !St->isVolatile()) {
24531 SDNode* LdVal = St->getValue().getNode();
24532 LoadSDNode *Ld = nullptr;
24533 int TokenFactorIndex = -1;
24534 SmallVector<SDValue, 8> Ops;
24535 SDNode* ChainVal = St->getChain().getNode();
24536 // Must be a store of a load. We currently handle two cases: the load
24537 // is a direct child, and it's under an intervening TokenFactor. It is
24538 // possible to dig deeper under nested TokenFactors.
24539 if (ChainVal == LdVal)
24540 Ld = cast<LoadSDNode>(St->getChain());
24541 else if (St->getValue().hasOneUse() &&
24542 ChainVal->getOpcode() == ISD::TokenFactor) {
24543 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24544 if (ChainVal->getOperand(i).getNode() == LdVal) {
24545 TokenFactorIndex = i;
24546 Ld = cast<LoadSDNode>(St->getValue());
24548 Ops.push_back(ChainVal->getOperand(i));
24552 if (!Ld || !ISD::isNormalLoad(Ld))
24555 // If this is not the MMX case, i.e. we are just turning i64 load/store
24556 // into f64 load/store, avoid the transformation if there are multiple
24557 // uses of the loaded value.
24558 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24563 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24564 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24566 if (Subtarget->is64Bit() || F64IsLegal) {
24567 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24568 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24569 Ld->getPointerInfo(), Ld->isVolatile(),
24570 Ld->isNonTemporal(), Ld->isInvariant(),
24571 Ld->getAlignment());
24572 SDValue NewChain = NewLd.getValue(1);
24573 if (TokenFactorIndex != -1) {
24574 Ops.push_back(NewChain);
24575 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24577 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24578 St->getPointerInfo(),
24579 St->isVolatile(), St->isNonTemporal(),
24580 St->getAlignment());
24583 // Otherwise, lower to two pairs of 32-bit loads / stores.
24584 SDValue LoAddr = Ld->getBasePtr();
24585 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24586 DAG.getConstant(4, MVT::i32));
24588 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24589 Ld->getPointerInfo(),
24590 Ld->isVolatile(), Ld->isNonTemporal(),
24591 Ld->isInvariant(), Ld->getAlignment());
24592 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24593 Ld->getPointerInfo().getWithOffset(4),
24594 Ld->isVolatile(), Ld->isNonTemporal(),
24596 MinAlign(Ld->getAlignment(), 4));
24598 SDValue NewChain = LoLd.getValue(1);
24599 if (TokenFactorIndex != -1) {
24600 Ops.push_back(LoLd);
24601 Ops.push_back(HiLd);
24602 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24605 LoAddr = St->getBasePtr();
24606 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24607 DAG.getConstant(4, MVT::i32));
24609 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24610 St->getPointerInfo(),
24611 St->isVolatile(), St->isNonTemporal(),
24612 St->getAlignment());
24613 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24614 St->getPointerInfo().getWithOffset(4),
24616 St->isNonTemporal(),
24617 MinAlign(St->getAlignment(), 4));
24618 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24623 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24624 /// and return the operands for the horizontal operation in LHS and RHS. A
24625 /// horizontal operation performs the binary operation on successive elements
24626 /// of its first operand, then on successive elements of its second operand,
24627 /// returning the resulting values in a vector. For example, if
24628 /// A = < float a0, float a1, float a2, float a3 >
24630 /// B = < float b0, float b1, float b2, float b3 >
24631 /// then the result of doing a horizontal operation on A and B is
24632 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24633 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24634 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24635 /// set to A, RHS to B, and the routine returns 'true'.
24636 /// Note that the binary operation should have the property that if one of the
24637 /// operands is UNDEF then the result is UNDEF.
24638 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24639 // Look for the following pattern: if
24640 // A = < float a0, float a1, float a2, float a3 >
24641 // B = < float b0, float b1, float b2, float b3 >
24643 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24644 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24645 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24646 // which is A horizontal-op B.
24648 // At least one of the operands should be a vector shuffle.
24649 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24650 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24653 MVT VT = LHS.getSimpleValueType();
24655 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24656 "Unsupported vector type for horizontal add/sub");
24658 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24659 // operate independently on 128-bit lanes.
24660 unsigned NumElts = VT.getVectorNumElements();
24661 unsigned NumLanes = VT.getSizeInBits()/128;
24662 unsigned NumLaneElts = NumElts / NumLanes;
24663 assert((NumLaneElts % 2 == 0) &&
24664 "Vector type should have an even number of elements in each lane");
24665 unsigned HalfLaneElts = NumLaneElts/2;
24667 // View LHS in the form
24668 // LHS = VECTOR_SHUFFLE A, B, LMask
24669 // If LHS is not a shuffle then pretend it is the shuffle
24670 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24671 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24674 SmallVector<int, 16> LMask(NumElts);
24675 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24676 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24677 A = LHS.getOperand(0);
24678 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24679 B = LHS.getOperand(1);
24680 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24681 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24683 if (LHS.getOpcode() != ISD::UNDEF)
24685 for (unsigned i = 0; i != NumElts; ++i)
24689 // Likewise, view RHS in the form
24690 // RHS = VECTOR_SHUFFLE C, D, RMask
24692 SmallVector<int, 16> RMask(NumElts);
24693 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24694 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24695 C = RHS.getOperand(0);
24696 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24697 D = RHS.getOperand(1);
24698 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24699 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24701 if (RHS.getOpcode() != ISD::UNDEF)
24703 for (unsigned i = 0; i != NumElts; ++i)
24707 // Check that the shuffles are both shuffling the same vectors.
24708 if (!(A == C && B == D) && !(A == D && B == C))
24711 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24712 if (!A.getNode() && !B.getNode())
24715 // If A and B occur in reverse order in RHS, then "swap" them (which means
24716 // rewriting the mask).
24718 CommuteVectorShuffleMask(RMask, NumElts);
24720 // At this point LHS and RHS are equivalent to
24721 // LHS = VECTOR_SHUFFLE A, B, LMask
24722 // RHS = VECTOR_SHUFFLE A, B, RMask
24723 // Check that the masks correspond to performing a horizontal operation.
24724 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24725 for (unsigned i = 0; i != NumLaneElts; ++i) {
24726 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24728 // Ignore any UNDEF components.
24729 if (LIdx < 0 || RIdx < 0 ||
24730 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24731 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24734 // Check that successive elements are being operated on. If not, this is
24735 // not a horizontal operation.
24736 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24737 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24738 if (!(LIdx == Index && RIdx == Index + 1) &&
24739 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24744 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24745 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24749 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24750 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24751 const X86Subtarget *Subtarget) {
24752 EVT VT = N->getValueType(0);
24753 SDValue LHS = N->getOperand(0);
24754 SDValue RHS = N->getOperand(1);
24756 // Try to synthesize horizontal adds from adds of shuffles.
24757 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24758 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24759 isHorizontalBinOp(LHS, RHS, true))
24760 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24764 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24765 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24766 const X86Subtarget *Subtarget) {
24767 EVT VT = N->getValueType(0);
24768 SDValue LHS = N->getOperand(0);
24769 SDValue RHS = N->getOperand(1);
24771 // Try to synthesize horizontal subs from subs of shuffles.
24772 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24773 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24774 isHorizontalBinOp(LHS, RHS, false))
24775 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24779 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24780 /// X86ISD::FXOR nodes.
24781 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24782 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24783 // F[X]OR(0.0, x) -> x
24784 // F[X]OR(x, 0.0) -> x
24785 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24786 if (C->getValueAPF().isPosZero())
24787 return N->getOperand(1);
24788 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24789 if (C->getValueAPF().isPosZero())
24790 return N->getOperand(0);
24794 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24795 /// X86ISD::FMAX nodes.
24796 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24797 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24799 // Only perform optimizations if UnsafeMath is used.
24800 if (!DAG.getTarget().Options.UnsafeFPMath)
24803 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24804 // into FMINC and FMAXC, which are Commutative operations.
24805 unsigned NewOp = 0;
24806 switch (N->getOpcode()) {
24807 default: llvm_unreachable("unknown opcode");
24808 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24809 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24812 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24813 N->getOperand(0), N->getOperand(1));
24816 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24817 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24818 // FAND(0.0, x) -> 0.0
24819 // FAND(x, 0.0) -> 0.0
24820 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24821 if (C->getValueAPF().isPosZero())
24822 return N->getOperand(0);
24823 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24824 if (C->getValueAPF().isPosZero())
24825 return N->getOperand(1);
24829 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24830 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24831 // FANDN(x, 0.0) -> 0.0
24832 // FANDN(0.0, x) -> x
24833 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24834 if (C->getValueAPF().isPosZero())
24835 return N->getOperand(1);
24836 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24837 if (C->getValueAPF().isPosZero())
24838 return N->getOperand(1);
24842 static SDValue PerformBTCombine(SDNode *N,
24844 TargetLowering::DAGCombinerInfo &DCI) {
24845 // BT ignores high bits in the bit index operand.
24846 SDValue Op1 = N->getOperand(1);
24847 if (Op1.hasOneUse()) {
24848 unsigned BitWidth = Op1.getValueSizeInBits();
24849 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24850 APInt KnownZero, KnownOne;
24851 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24852 !DCI.isBeforeLegalizeOps());
24853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24854 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24855 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24856 DCI.CommitTargetLoweringOpt(TLO);
24861 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24862 SDValue Op = N->getOperand(0);
24863 if (Op.getOpcode() == ISD::BITCAST)
24864 Op = Op.getOperand(0);
24865 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24866 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24867 VT.getVectorElementType().getSizeInBits() ==
24868 OpVT.getVectorElementType().getSizeInBits()) {
24869 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24874 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24875 const X86Subtarget *Subtarget) {
24876 EVT VT = N->getValueType(0);
24877 if (!VT.isVector())
24880 SDValue N0 = N->getOperand(0);
24881 SDValue N1 = N->getOperand(1);
24882 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24885 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24886 // both SSE and AVX2 since there is no sign-extended shift right
24887 // operation on a vector with 64-bit elements.
24888 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24889 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24890 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24891 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24892 SDValue N00 = N0.getOperand(0);
24894 // EXTLOAD has a better solution on AVX2,
24895 // it may be replaced with X86ISD::VSEXT node.
24896 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24897 if (!ISD::isNormalLoad(N00.getNode()))
24900 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24901 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24903 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24909 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24910 TargetLowering::DAGCombinerInfo &DCI,
24911 const X86Subtarget *Subtarget) {
24912 SDValue N0 = N->getOperand(0);
24913 EVT VT = N->getValueType(0);
24915 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24916 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24917 // This exposes the sext to the sdivrem lowering, so that it directly extends
24918 // from AH (which we otherwise need to do contortions to access).
24919 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24920 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24922 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24923 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24924 N0.getOperand(0), N0.getOperand(1));
24925 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24926 return R.getValue(1);
24929 if (!DCI.isBeforeLegalizeOps())
24932 if (!Subtarget->hasFp256())
24935 if (VT.isVector() && VT.getSizeInBits() == 256) {
24936 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24944 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24945 const X86Subtarget* Subtarget) {
24947 EVT VT = N->getValueType(0);
24949 // Let legalize expand this if it isn't a legal type yet.
24950 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24953 EVT ScalarVT = VT.getScalarType();
24954 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24955 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24958 SDValue A = N->getOperand(0);
24959 SDValue B = N->getOperand(1);
24960 SDValue C = N->getOperand(2);
24962 bool NegA = (A.getOpcode() == ISD::FNEG);
24963 bool NegB = (B.getOpcode() == ISD::FNEG);
24964 bool NegC = (C.getOpcode() == ISD::FNEG);
24966 // Negative multiplication when NegA xor NegB
24967 bool NegMul = (NegA != NegB);
24969 A = A.getOperand(0);
24971 B = B.getOperand(0);
24973 C = C.getOperand(0);
24977 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24979 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24981 return DAG.getNode(Opcode, dl, VT, A, B, C);
24984 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24985 TargetLowering::DAGCombinerInfo &DCI,
24986 const X86Subtarget *Subtarget) {
24987 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24988 // (and (i32 x86isd::setcc_carry), 1)
24989 // This eliminates the zext. This transformation is necessary because
24990 // ISD::SETCC is always legalized to i8.
24992 SDValue N0 = N->getOperand(0);
24993 EVT VT = N->getValueType(0);
24995 if (N0.getOpcode() == ISD::AND &&
24997 N0.getOperand(0).hasOneUse()) {
24998 SDValue N00 = N0.getOperand(0);
24999 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25000 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25001 if (!C || C->getZExtValue() != 1)
25003 return DAG.getNode(ISD::AND, dl, VT,
25004 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25005 N00.getOperand(0), N00.getOperand(1)),
25006 DAG.getConstant(1, VT));
25010 if (N0.getOpcode() == ISD::TRUNCATE &&
25012 N0.getOperand(0).hasOneUse()) {
25013 SDValue N00 = N0.getOperand(0);
25014 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25015 return DAG.getNode(ISD::AND, dl, VT,
25016 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25017 N00.getOperand(0), N00.getOperand(1)),
25018 DAG.getConstant(1, VT));
25021 if (VT.is256BitVector()) {
25022 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25027 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25028 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25029 // This exposes the zext to the udivrem lowering, so that it directly extends
25030 // from AH (which we otherwise need to do contortions to access).
25031 if (N0.getOpcode() == ISD::UDIVREM &&
25032 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25033 (VT == MVT::i32 || VT == MVT::i64)) {
25034 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25035 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25036 N0.getOperand(0), N0.getOperand(1));
25037 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25038 return R.getValue(1);
25044 // Optimize x == -y --> x+y == 0
25045 // x != -y --> x+y != 0
25046 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25047 const X86Subtarget* Subtarget) {
25048 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25049 SDValue LHS = N->getOperand(0);
25050 SDValue RHS = N->getOperand(1);
25051 EVT VT = N->getValueType(0);
25054 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25056 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25057 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25058 LHS.getValueType(), RHS, LHS.getOperand(1));
25059 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25060 addV, DAG.getConstant(0, addV.getValueType()), CC);
25062 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25064 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25065 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25066 RHS.getValueType(), LHS, RHS.getOperand(1));
25067 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25068 addV, DAG.getConstant(0, addV.getValueType()), CC);
25071 if (VT.getScalarType() == MVT::i1) {
25072 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25073 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25074 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25075 if (!IsSEXT0 && !IsVZero0)
25077 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25078 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25079 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25081 if (!IsSEXT1 && !IsVZero1)
25084 if (IsSEXT0 && IsVZero1) {
25085 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25086 if (CC == ISD::SETEQ)
25087 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25088 return LHS.getOperand(0);
25090 if (IsSEXT1 && IsVZero0) {
25091 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25092 if (CC == ISD::SETEQ)
25093 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25094 return RHS.getOperand(0);
25101 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25102 const X86Subtarget *Subtarget) {
25104 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25105 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25106 "X86insertps is only defined for v4x32");
25108 SDValue Ld = N->getOperand(1);
25109 if (MayFoldLoad(Ld)) {
25110 // Extract the countS bits from the immediate so we can get the proper
25111 // address when narrowing the vector load to a specific element.
25112 // When the second source op is a memory address, interps doesn't use
25113 // countS and just gets an f32 from that address.
25114 unsigned DestIndex =
25115 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25116 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25120 // Create this as a scalar to vector to match the instruction pattern.
25121 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25122 // countS bits are ignored when loading from memory on insertps, which
25123 // means we don't need to explicitly set them to 0.
25124 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25125 LoadScalarToVector, N->getOperand(2));
25128 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25129 // as "sbb reg,reg", since it can be extended without zext and produces
25130 // an all-ones bit which is more useful than 0/1 in some cases.
25131 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25134 return DAG.getNode(ISD::AND, DL, VT,
25135 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25136 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25137 DAG.getConstant(1, VT));
25138 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25139 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25140 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25141 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25144 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25145 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25146 TargetLowering::DAGCombinerInfo &DCI,
25147 const X86Subtarget *Subtarget) {
25149 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25150 SDValue EFLAGS = N->getOperand(1);
25152 if (CC == X86::COND_A) {
25153 // Try to convert COND_A into COND_B in an attempt to facilitate
25154 // materializing "setb reg".
25156 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25157 // cannot take an immediate as its first operand.
25159 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25160 EFLAGS.getValueType().isInteger() &&
25161 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25162 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25163 EFLAGS.getNode()->getVTList(),
25164 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25165 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25166 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25170 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25171 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25173 if (CC == X86::COND_B)
25174 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25178 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25179 if (Flags.getNode()) {
25180 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25181 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25187 // Optimize branch condition evaluation.
25189 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25190 TargetLowering::DAGCombinerInfo &DCI,
25191 const X86Subtarget *Subtarget) {
25193 SDValue Chain = N->getOperand(0);
25194 SDValue Dest = N->getOperand(1);
25195 SDValue EFLAGS = N->getOperand(3);
25196 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25200 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25201 if (Flags.getNode()) {
25202 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25203 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25210 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25211 SelectionDAG &DAG) {
25212 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25213 // optimize away operation when it's from a constant.
25215 // The general transformation is:
25216 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25217 // AND(VECTOR_CMP(x,y), constant2)
25218 // constant2 = UNARYOP(constant)
25220 // Early exit if this isn't a vector operation, the operand of the
25221 // unary operation isn't a bitwise AND, or if the sizes of the operations
25222 // aren't the same.
25223 EVT VT = N->getValueType(0);
25224 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25225 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25226 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25229 // Now check that the other operand of the AND is a constant. We could
25230 // make the transformation for non-constant splats as well, but it's unclear
25231 // that would be a benefit as it would not eliminate any operations, just
25232 // perform one more step in scalar code before moving to the vector unit.
25233 if (BuildVectorSDNode *BV =
25234 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25235 // Bail out if the vector isn't a constant.
25236 if (!BV->isConstant())
25239 // Everything checks out. Build up the new and improved node.
25241 EVT IntVT = BV->getValueType(0);
25242 // Create a new constant of the appropriate type for the transformed
25244 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25245 // The AND node needs bitcasts to/from an integer vector type around it.
25246 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25247 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25248 N->getOperand(0)->getOperand(0), MaskConst);
25249 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25256 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25257 const X86TargetLowering *XTLI) {
25258 // First try to optimize away the conversion entirely when it's
25259 // conditionally from a constant. Vectors only.
25260 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25261 if (Res != SDValue())
25264 // Now move on to more general possibilities.
25265 SDValue Op0 = N->getOperand(0);
25266 EVT InVT = Op0->getValueType(0);
25268 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25269 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25271 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25272 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25273 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25276 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25277 // a 32-bit target where SSE doesn't support i64->FP operations.
25278 if (Op0.getOpcode() == ISD::LOAD) {
25279 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25280 EVT VT = Ld->getValueType(0);
25281 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25282 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25283 !XTLI->getSubtarget()->is64Bit() &&
25285 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25286 Ld->getChain(), Op0, DAG);
25287 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25294 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25295 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25296 X86TargetLowering::DAGCombinerInfo &DCI) {
25297 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25298 // the result is either zero or one (depending on the input carry bit).
25299 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25300 if (X86::isZeroNode(N->getOperand(0)) &&
25301 X86::isZeroNode(N->getOperand(1)) &&
25302 // We don't have a good way to replace an EFLAGS use, so only do this when
25304 SDValue(N, 1).use_empty()) {
25306 EVT VT = N->getValueType(0);
25307 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25308 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25309 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25310 DAG.getConstant(X86::COND_B,MVT::i8),
25312 DAG.getConstant(1, VT));
25313 return DCI.CombineTo(N, Res1, CarryOut);
25319 // fold (add Y, (sete X, 0)) -> adc 0, Y
25320 // (add Y, (setne X, 0)) -> sbb -1, Y
25321 // (sub (sete X, 0), Y) -> sbb 0, Y
25322 // (sub (setne X, 0), Y) -> adc -1, Y
25323 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25326 // Look through ZExts.
25327 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25328 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25331 SDValue SetCC = Ext.getOperand(0);
25332 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25335 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25336 if (CC != X86::COND_E && CC != X86::COND_NE)
25339 SDValue Cmp = SetCC.getOperand(1);
25340 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25341 !X86::isZeroNode(Cmp.getOperand(1)) ||
25342 !Cmp.getOperand(0).getValueType().isInteger())
25345 SDValue CmpOp0 = Cmp.getOperand(0);
25346 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25347 DAG.getConstant(1, CmpOp0.getValueType()));
25349 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25350 if (CC == X86::COND_NE)
25351 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25352 DL, OtherVal.getValueType(), OtherVal,
25353 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25354 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25355 DL, OtherVal.getValueType(), OtherVal,
25356 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25359 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25360 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25361 const X86Subtarget *Subtarget) {
25362 EVT VT = N->getValueType(0);
25363 SDValue Op0 = N->getOperand(0);
25364 SDValue Op1 = N->getOperand(1);
25366 // Try to synthesize horizontal adds from adds of shuffles.
25367 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25368 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25369 isHorizontalBinOp(Op0, Op1, true))
25370 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25372 return OptimizeConditionalInDecrement(N, DAG);
25375 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25376 const X86Subtarget *Subtarget) {
25377 SDValue Op0 = N->getOperand(0);
25378 SDValue Op1 = N->getOperand(1);
25380 // X86 can't encode an immediate LHS of a sub. See if we can push the
25381 // negation into a preceding instruction.
25382 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25383 // If the RHS of the sub is a XOR with one use and a constant, invert the
25384 // immediate. Then add one to the LHS of the sub so we can turn
25385 // X-Y -> X+~Y+1, saving one register.
25386 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25387 isa<ConstantSDNode>(Op1.getOperand(1))) {
25388 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25389 EVT VT = Op0.getValueType();
25390 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25392 DAG.getConstant(~XorC, VT));
25393 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25394 DAG.getConstant(C->getAPIntValue()+1, VT));
25398 // Try to synthesize horizontal adds from adds of shuffles.
25399 EVT VT = N->getValueType(0);
25400 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25401 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25402 isHorizontalBinOp(Op0, Op1, true))
25403 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25405 return OptimizeConditionalInDecrement(N, DAG);
25408 /// performVZEXTCombine - Performs build vector combines
25409 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25410 TargetLowering::DAGCombinerInfo &DCI,
25411 const X86Subtarget *Subtarget) {
25413 MVT VT = N->getSimpleValueType(0);
25414 SDValue Op = N->getOperand(0);
25415 MVT OpVT = Op.getSimpleValueType();
25416 MVT OpEltVT = OpVT.getVectorElementType();
25417 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25419 // (vzext (bitcast (vzext (x)) -> (vzext x)
25421 while (V.getOpcode() == ISD::BITCAST)
25422 V = V.getOperand(0);
25424 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25425 MVT InnerVT = V.getSimpleValueType();
25426 MVT InnerEltVT = InnerVT.getVectorElementType();
25428 // If the element sizes match exactly, we can just do one larger vzext. This
25429 // is always an exact type match as vzext operates on integer types.
25430 if (OpEltVT == InnerEltVT) {
25431 assert(OpVT == InnerVT && "Types must match for vzext!");
25432 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25435 // The only other way we can combine them is if only a single element of the
25436 // inner vzext is used in the input to the outer vzext.
25437 if (InnerEltVT.getSizeInBits() < InputBits)
25440 // In this case, the inner vzext is completely dead because we're going to
25441 // only look at bits inside of the low element. Just do the outer vzext on
25442 // a bitcast of the input to the inner.
25443 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25444 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25447 // Check if we can bypass extracting and re-inserting an element of an input
25448 // vector. Essentialy:
25449 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25450 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25451 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25452 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25453 SDValue ExtractedV = V.getOperand(0);
25454 SDValue OrigV = ExtractedV.getOperand(0);
25455 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25456 if (ExtractIdx->getZExtValue() == 0) {
25457 MVT OrigVT = OrigV.getSimpleValueType();
25458 // Extract a subvector if necessary...
25459 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25460 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25461 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25462 OrigVT.getVectorNumElements() / Ratio);
25463 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25464 DAG.getIntPtrConstant(0));
25466 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25467 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25474 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25475 DAGCombinerInfo &DCI) const {
25476 SelectionDAG &DAG = DCI.DAG;
25477 switch (N->getOpcode()) {
25479 case ISD::EXTRACT_VECTOR_ELT:
25480 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25483 case X86ISD::SHRUNKBLEND:
25484 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25485 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25486 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25487 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25488 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25489 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25492 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25493 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25494 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25495 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25496 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25497 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25498 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25499 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25500 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25502 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25504 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25505 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25506 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25507 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25508 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25509 case ISD::ANY_EXTEND:
25510 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25511 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25512 case ISD::SIGN_EXTEND_INREG:
25513 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25514 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25515 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25516 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25517 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25518 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25519 case X86ISD::SHUFP: // Handle all target specific shuffles
25520 case X86ISD::PALIGNR:
25521 case X86ISD::UNPCKH:
25522 case X86ISD::UNPCKL:
25523 case X86ISD::MOVHLPS:
25524 case X86ISD::MOVLHPS:
25525 case X86ISD::PSHUFB:
25526 case X86ISD::PSHUFD:
25527 case X86ISD::PSHUFHW:
25528 case X86ISD::PSHUFLW:
25529 case X86ISD::MOVSS:
25530 case X86ISD::MOVSD:
25531 case X86ISD::VPERMILPI:
25532 case X86ISD::VPERM2X128:
25533 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25534 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25535 case ISD::INTRINSIC_WO_CHAIN:
25536 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25537 case X86ISD::INSERTPS:
25538 return PerformINSERTPSCombine(N, DAG, Subtarget);
25539 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25545 /// isTypeDesirableForOp - Return true if the target has native support for
25546 /// the specified value type and it is 'desirable' to use the type for the
25547 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25548 /// instruction encodings are longer and some i16 instructions are slow.
25549 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25550 if (!isTypeLegal(VT))
25552 if (VT != MVT::i16)
25559 case ISD::SIGN_EXTEND:
25560 case ISD::ZERO_EXTEND:
25561 case ISD::ANY_EXTEND:
25574 /// IsDesirableToPromoteOp - This method query the target whether it is
25575 /// beneficial for dag combiner to promote the specified node. If true, it
25576 /// should return the desired promotion type by reference.
25577 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25578 EVT VT = Op.getValueType();
25579 if (VT != MVT::i16)
25582 bool Promote = false;
25583 bool Commute = false;
25584 switch (Op.getOpcode()) {
25587 LoadSDNode *LD = cast<LoadSDNode>(Op);
25588 // If the non-extending load has a single use and it's not live out, then it
25589 // might be folded.
25590 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25591 Op.hasOneUse()*/) {
25592 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25593 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25594 // The only case where we'd want to promote LOAD (rather then it being
25595 // promoted as an operand is when it's only use is liveout.
25596 if (UI->getOpcode() != ISD::CopyToReg)
25603 case ISD::SIGN_EXTEND:
25604 case ISD::ZERO_EXTEND:
25605 case ISD::ANY_EXTEND:
25610 SDValue N0 = Op.getOperand(0);
25611 // Look out for (store (shl (load), x)).
25612 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25625 SDValue N0 = Op.getOperand(0);
25626 SDValue N1 = Op.getOperand(1);
25627 if (!Commute && MayFoldLoad(N1))
25629 // Avoid disabling potential load folding opportunities.
25630 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25632 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25642 //===----------------------------------------------------------------------===//
25643 // X86 Inline Assembly Support
25644 //===----------------------------------------------------------------------===//
25647 // Helper to match a string separated by whitespace.
25648 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25649 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25651 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25652 StringRef piece(*args[i]);
25653 if (!s.startswith(piece)) // Check if the piece matches.
25656 s = s.substr(piece.size());
25657 StringRef::size_type pos = s.find_first_not_of(" \t");
25658 if (pos == 0) // We matched a prefix.
25666 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25669 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25671 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25672 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25673 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25674 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25676 if (AsmPieces.size() == 3)
25678 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25685 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25686 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25688 std::string AsmStr = IA->getAsmString();
25690 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25691 if (!Ty || Ty->getBitWidth() % 16 != 0)
25694 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25695 SmallVector<StringRef, 4> AsmPieces;
25696 SplitString(AsmStr, AsmPieces, ";\n");
25698 switch (AsmPieces.size()) {
25699 default: return false;
25701 // FIXME: this should verify that we are targeting a 486 or better. If not,
25702 // we will turn this bswap into something that will be lowered to logical
25703 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25704 // lower so don't worry about this.
25706 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25707 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25708 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25709 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25710 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25711 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25712 // No need to check constraints, nothing other than the equivalent of
25713 // "=r,0" would be valid here.
25714 return IntrinsicLowering::LowerToByteSwap(CI);
25717 // rorw $$8, ${0:w} --> llvm.bswap.i16
25718 if (CI->getType()->isIntegerTy(16) &&
25719 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25720 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25721 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25723 const std::string &ConstraintsStr = IA->getConstraintString();
25724 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25725 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25726 if (clobbersFlagRegisters(AsmPieces))
25727 return IntrinsicLowering::LowerToByteSwap(CI);
25731 if (CI->getType()->isIntegerTy(32) &&
25732 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25733 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25734 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25735 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25737 const std::string &ConstraintsStr = IA->getConstraintString();
25738 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25739 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25740 if (clobbersFlagRegisters(AsmPieces))
25741 return IntrinsicLowering::LowerToByteSwap(CI);
25744 if (CI->getType()->isIntegerTy(64)) {
25745 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25746 if (Constraints.size() >= 2 &&
25747 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25748 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25749 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25750 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25751 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25752 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25753 return IntrinsicLowering::LowerToByteSwap(CI);
25761 /// getConstraintType - Given a constraint letter, return the type of
25762 /// constraint it is for this target.
25763 X86TargetLowering::ConstraintType
25764 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25765 if (Constraint.size() == 1) {
25766 switch (Constraint[0]) {
25777 return C_RegisterClass;
25801 return TargetLowering::getConstraintType(Constraint);
25804 /// Examine constraint type and operand type and determine a weight value.
25805 /// This object must already have been set up with the operand type
25806 /// and the current alternative constraint selected.
25807 TargetLowering::ConstraintWeight
25808 X86TargetLowering::getSingleConstraintMatchWeight(
25809 AsmOperandInfo &info, const char *constraint) const {
25810 ConstraintWeight weight = CW_Invalid;
25811 Value *CallOperandVal = info.CallOperandVal;
25812 // If we don't have a value, we can't do a match,
25813 // but allow it at the lowest weight.
25814 if (!CallOperandVal)
25816 Type *type = CallOperandVal->getType();
25817 // Look at the constraint type.
25818 switch (*constraint) {
25820 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25831 if (CallOperandVal->getType()->isIntegerTy())
25832 weight = CW_SpecificReg;
25837 if (type->isFloatingPointTy())
25838 weight = CW_SpecificReg;
25841 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25842 weight = CW_SpecificReg;
25846 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25847 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25848 weight = CW_Register;
25851 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25852 if (C->getZExtValue() <= 31)
25853 weight = CW_Constant;
25857 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25858 if (C->getZExtValue() <= 63)
25859 weight = CW_Constant;
25863 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25864 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25865 weight = CW_Constant;
25869 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25870 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25871 weight = CW_Constant;
25875 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25876 if (C->getZExtValue() <= 3)
25877 weight = CW_Constant;
25881 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25882 if (C->getZExtValue() <= 0xff)
25883 weight = CW_Constant;
25888 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25889 weight = CW_Constant;
25893 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25894 if ((C->getSExtValue() >= -0x80000000LL) &&
25895 (C->getSExtValue() <= 0x7fffffffLL))
25896 weight = CW_Constant;
25900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25901 if (C->getZExtValue() <= 0xffffffff)
25902 weight = CW_Constant;
25909 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25910 /// with another that has more specific requirements based on the type of the
25911 /// corresponding operand.
25912 const char *X86TargetLowering::
25913 LowerXConstraint(EVT ConstraintVT) const {
25914 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25915 // 'f' like normal targets.
25916 if (ConstraintVT.isFloatingPoint()) {
25917 if (Subtarget->hasSSE2())
25919 if (Subtarget->hasSSE1())
25923 return TargetLowering::LowerXConstraint(ConstraintVT);
25926 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25927 /// vector. If it is invalid, don't add anything to Ops.
25928 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25929 std::string &Constraint,
25930 std::vector<SDValue>&Ops,
25931 SelectionDAG &DAG) const {
25934 // Only support length 1 constraints for now.
25935 if (Constraint.length() > 1) return;
25937 char ConstraintLetter = Constraint[0];
25938 switch (ConstraintLetter) {
25941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25942 if (C->getZExtValue() <= 31) {
25943 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25950 if (C->getZExtValue() <= 63) {
25951 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25958 if (isInt<8>(C->getSExtValue())) {
25959 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25966 if (C->getZExtValue() <= 255) {
25967 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25973 // 32-bit signed value
25974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25975 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25976 C->getSExtValue())) {
25977 // Widen to 64 bits here to get it sign extended.
25978 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25981 // FIXME gcc accepts some relocatable values here too, but only in certain
25982 // memory models; it's complicated.
25987 // 32-bit unsigned value
25988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25989 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25990 C->getZExtValue())) {
25991 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25995 // FIXME gcc accepts some relocatable values here too, but only in certain
25996 // memory models; it's complicated.
26000 // Literal immediates are always ok.
26001 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26002 // Widen to 64 bits here to get it sign extended.
26003 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26007 // In any sort of PIC mode addresses need to be computed at runtime by
26008 // adding in a register or some sort of table lookup. These can't
26009 // be used as immediates.
26010 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26013 // If we are in non-pic codegen mode, we allow the address of a global (with
26014 // an optional displacement) to be used with 'i'.
26015 GlobalAddressSDNode *GA = nullptr;
26016 int64_t Offset = 0;
26018 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26020 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26021 Offset += GA->getOffset();
26023 } else if (Op.getOpcode() == ISD::ADD) {
26024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26025 Offset += C->getZExtValue();
26026 Op = Op.getOperand(0);
26029 } else if (Op.getOpcode() == ISD::SUB) {
26030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26031 Offset += -C->getZExtValue();
26032 Op = Op.getOperand(0);
26037 // Otherwise, this isn't something we can handle, reject it.
26041 const GlobalValue *GV = GA->getGlobal();
26042 // If we require an extra load to get this address, as in PIC mode, we
26043 // can't accept it.
26044 if (isGlobalStubReference(
26045 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26048 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26049 GA->getValueType(0), Offset);
26054 if (Result.getNode()) {
26055 Ops.push_back(Result);
26058 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26061 std::pair<unsigned, const TargetRegisterClass*>
26062 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26064 // First, see if this is a constraint that directly corresponds to an LLVM
26066 if (Constraint.size() == 1) {
26067 // GCC Constraint Letters
26068 switch (Constraint[0]) {
26070 // TODO: Slight differences here in allocation order and leaving
26071 // RIP in the class. Do they matter any more here than they do
26072 // in the normal allocation?
26073 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26074 if (Subtarget->is64Bit()) {
26075 if (VT == MVT::i32 || VT == MVT::f32)
26076 return std::make_pair(0U, &X86::GR32RegClass);
26077 if (VT == MVT::i16)
26078 return std::make_pair(0U, &X86::GR16RegClass);
26079 if (VT == MVT::i8 || VT == MVT::i1)
26080 return std::make_pair(0U, &X86::GR8RegClass);
26081 if (VT == MVT::i64 || VT == MVT::f64)
26082 return std::make_pair(0U, &X86::GR64RegClass);
26085 // 32-bit fallthrough
26086 case 'Q': // Q_REGS
26087 if (VT == MVT::i32 || VT == MVT::f32)
26088 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26089 if (VT == MVT::i16)
26090 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26091 if (VT == MVT::i8 || VT == MVT::i1)
26092 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26093 if (VT == MVT::i64)
26094 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26096 case 'r': // GENERAL_REGS
26097 case 'l': // INDEX_REGS
26098 if (VT == MVT::i8 || VT == MVT::i1)
26099 return std::make_pair(0U, &X86::GR8RegClass);
26100 if (VT == MVT::i16)
26101 return std::make_pair(0U, &X86::GR16RegClass);
26102 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26103 return std::make_pair(0U, &X86::GR32RegClass);
26104 return std::make_pair(0U, &X86::GR64RegClass);
26105 case 'R': // LEGACY_REGS
26106 if (VT == MVT::i8 || VT == MVT::i1)
26107 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26108 if (VT == MVT::i16)
26109 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26110 if (VT == MVT::i32 || !Subtarget->is64Bit())
26111 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26112 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26113 case 'f': // FP Stack registers.
26114 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26115 // value to the correct fpstack register class.
26116 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26117 return std::make_pair(0U, &X86::RFP32RegClass);
26118 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26119 return std::make_pair(0U, &X86::RFP64RegClass);
26120 return std::make_pair(0U, &X86::RFP80RegClass);
26121 case 'y': // MMX_REGS if MMX allowed.
26122 if (!Subtarget->hasMMX()) break;
26123 return std::make_pair(0U, &X86::VR64RegClass);
26124 case 'Y': // SSE_REGS if SSE2 allowed
26125 if (!Subtarget->hasSSE2()) break;
26127 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26128 if (!Subtarget->hasSSE1()) break;
26130 switch (VT.SimpleTy) {
26132 // Scalar SSE types.
26135 return std::make_pair(0U, &X86::FR32RegClass);
26138 return std::make_pair(0U, &X86::FR64RegClass);
26146 return std::make_pair(0U, &X86::VR128RegClass);
26154 return std::make_pair(0U, &X86::VR256RegClass);
26159 return std::make_pair(0U, &X86::VR512RegClass);
26165 // Use the default implementation in TargetLowering to convert the register
26166 // constraint into a member of a register class.
26167 std::pair<unsigned, const TargetRegisterClass*> Res;
26168 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26170 // Not found as a standard register?
26172 // Map st(0) -> st(7) -> ST0
26173 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26174 tolower(Constraint[1]) == 's' &&
26175 tolower(Constraint[2]) == 't' &&
26176 Constraint[3] == '(' &&
26177 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26178 Constraint[5] == ')' &&
26179 Constraint[6] == '}') {
26181 Res.first = X86::FP0+Constraint[4]-'0';
26182 Res.second = &X86::RFP80RegClass;
26186 // GCC allows "st(0)" to be called just plain "st".
26187 if (StringRef("{st}").equals_lower(Constraint)) {
26188 Res.first = X86::FP0;
26189 Res.second = &X86::RFP80RegClass;
26194 if (StringRef("{flags}").equals_lower(Constraint)) {
26195 Res.first = X86::EFLAGS;
26196 Res.second = &X86::CCRRegClass;
26200 // 'A' means EAX + EDX.
26201 if (Constraint == "A") {
26202 Res.first = X86::EAX;
26203 Res.second = &X86::GR32_ADRegClass;
26209 // Otherwise, check to see if this is a register class of the wrong value
26210 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26211 // turn into {ax},{dx}.
26212 if (Res.second->hasType(VT))
26213 return Res; // Correct type already, nothing to do.
26215 // All of the single-register GCC register classes map their values onto
26216 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26217 // really want an 8-bit or 32-bit register, map to the appropriate register
26218 // class and return the appropriate register.
26219 if (Res.second == &X86::GR16RegClass) {
26220 if (VT == MVT::i8 || VT == MVT::i1) {
26221 unsigned DestReg = 0;
26222 switch (Res.first) {
26224 case X86::AX: DestReg = X86::AL; break;
26225 case X86::DX: DestReg = X86::DL; break;
26226 case X86::CX: DestReg = X86::CL; break;
26227 case X86::BX: DestReg = X86::BL; break;
26230 Res.first = DestReg;
26231 Res.second = &X86::GR8RegClass;
26233 } else if (VT == MVT::i32 || VT == MVT::f32) {
26234 unsigned DestReg = 0;
26235 switch (Res.first) {
26237 case X86::AX: DestReg = X86::EAX; break;
26238 case X86::DX: DestReg = X86::EDX; break;
26239 case X86::CX: DestReg = X86::ECX; break;
26240 case X86::BX: DestReg = X86::EBX; break;
26241 case X86::SI: DestReg = X86::ESI; break;
26242 case X86::DI: DestReg = X86::EDI; break;
26243 case X86::BP: DestReg = X86::EBP; break;
26244 case X86::SP: DestReg = X86::ESP; break;
26247 Res.first = DestReg;
26248 Res.second = &X86::GR32RegClass;
26250 } else if (VT == MVT::i64 || VT == MVT::f64) {
26251 unsigned DestReg = 0;
26252 switch (Res.first) {
26254 case X86::AX: DestReg = X86::RAX; break;
26255 case X86::DX: DestReg = X86::RDX; break;
26256 case X86::CX: DestReg = X86::RCX; break;
26257 case X86::BX: DestReg = X86::RBX; break;
26258 case X86::SI: DestReg = X86::RSI; break;
26259 case X86::DI: DestReg = X86::RDI; break;
26260 case X86::BP: DestReg = X86::RBP; break;
26261 case X86::SP: DestReg = X86::RSP; break;
26264 Res.first = DestReg;
26265 Res.second = &X86::GR64RegClass;
26268 } else if (Res.second == &X86::FR32RegClass ||
26269 Res.second == &X86::FR64RegClass ||
26270 Res.second == &X86::VR128RegClass ||
26271 Res.second == &X86::VR256RegClass ||
26272 Res.second == &X86::FR32XRegClass ||
26273 Res.second == &X86::FR64XRegClass ||
26274 Res.second == &X86::VR128XRegClass ||
26275 Res.second == &X86::VR256XRegClass ||
26276 Res.second == &X86::VR512RegClass) {
26277 // Handle references to XMM physical registers that got mapped into the
26278 // wrong class. This can happen with constraints like {xmm0} where the
26279 // target independent register mapper will just pick the first match it can
26280 // find, ignoring the required type.
26282 if (VT == MVT::f32 || VT == MVT::i32)
26283 Res.second = &X86::FR32RegClass;
26284 else if (VT == MVT::f64 || VT == MVT::i64)
26285 Res.second = &X86::FR64RegClass;
26286 else if (X86::VR128RegClass.hasType(VT))
26287 Res.second = &X86::VR128RegClass;
26288 else if (X86::VR256RegClass.hasType(VT))
26289 Res.second = &X86::VR256RegClass;
26290 else if (X86::VR512RegClass.hasType(VT))
26291 Res.second = &X86::VR512RegClass;
26297 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26299 // Scaling factors are not free at all.
26300 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26301 // will take 2 allocations in the out of order engine instead of 1
26302 // for plain addressing mode, i.e. inst (reg1).
26304 // vaddps (%rsi,%drx), %ymm0, %ymm1
26305 // Requires two allocations (one for the load, one for the computation)
26307 // vaddps (%rsi), %ymm0, %ymm1
26308 // Requires just 1 allocation, i.e., freeing allocations for other operations
26309 // and having less micro operations to execute.
26311 // For some X86 architectures, this is even worse because for instance for
26312 // stores, the complex addressing mode forces the instruction to use the
26313 // "load" ports instead of the dedicated "store" port.
26314 // E.g., on Haswell:
26315 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26316 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26317 if (isLegalAddressingMode(AM, Ty))
26318 // Scale represents reg2 * scale, thus account for 1
26319 // as soon as we use a second register.
26320 return AM.Scale != 0;
26324 bool X86TargetLowering::isTargetFTOL() const {
26325 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();