1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<bool> ExperimentalVectorShuffleLegality(
75 "x86-experimental-vector-shuffle-legality", cl::init(false),
76 cl::desc("Enable experimental shuffle legality based on the experimental "
77 "shuffle lowering. Should only be used with the experimental "
81 static cl::opt<int> ReciprocalEstimateRefinementSteps(
82 "x86-recip-refinement-steps", cl::init(1),
83 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
84 "result of the hardware reciprocal estimate instruction."),
87 // Forward declarations.
88 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
91 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
92 SelectionDAG &DAG, SDLoc dl,
93 unsigned vectorWidth) {
94 assert((vectorWidth == 128 || vectorWidth == 256) &&
95 "Unsupported vector width");
96 EVT VT = Vec.getValueType();
97 EVT ElVT = VT.getVectorElementType();
98 unsigned Factor = VT.getSizeInBits()/vectorWidth;
99 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
100 VT.getVectorNumElements()/Factor);
102 // Extract from UNDEF is UNDEF.
103 if (Vec.getOpcode() == ISD::UNDEF)
104 return DAG.getUNDEF(ResultVT);
106 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
107 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
109 // This is the index of the first element of the vectorWidth-bit chunk
111 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
114 // If the input is a buildvector just emit a smaller one.
115 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
116 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
117 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
120 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
121 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
124 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
125 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
126 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
127 /// instructions or a simple subregister reference. Idx is an index in the
128 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
129 /// lowering EXTRACT_VECTOR_ELT operations easier.
130 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
131 SelectionDAG &DAG, SDLoc dl) {
132 assert((Vec.getValueType().is256BitVector() ||
133 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
137 /// Generate a DAG to grab 256-bits from a 512-bit vector.
138 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
139 SelectionDAG &DAG, SDLoc dl) {
140 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
141 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
144 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
145 unsigned IdxVal, SelectionDAG &DAG,
146 SDLoc dl, unsigned vectorWidth) {
147 assert((vectorWidth == 128 || vectorWidth == 256) &&
148 "Unsupported vector width");
149 // Inserting UNDEF is Result
150 if (Vec.getOpcode() == ISD::UNDEF)
152 EVT VT = Vec.getValueType();
153 EVT ElVT = VT.getVectorElementType();
154 EVT ResultVT = Result.getValueType();
156 // Insert the relevant vectorWidth bits.
157 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
159 // This is the index of the first element of the vectorWidth-bit chunk
161 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
164 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
165 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
168 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
169 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
170 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
171 /// simple superregister reference. Idx is an index in the 128 bits
172 /// we want. It need not be aligned to a 128-bit boundary. That makes
173 /// lowering INSERT_VECTOR_ELT operations easier.
174 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
175 SelectionDAG &DAG,SDLoc dl) {
176 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
177 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
180 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
181 SelectionDAG &DAG, SDLoc dl) {
182 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
183 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
186 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
187 /// instructions. This is used because creating CONCAT_VECTOR nodes of
188 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
189 /// large BUILD_VECTORS.
190 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
197 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
198 unsigned NumElems, SelectionDAG &DAG,
200 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
201 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
204 // FIXME: This should stop caching the target machine as soon as
205 // we can remove resetOperationActions et al.
206 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
207 : TargetLowering(TM) {
208 Subtarget = &TM.getSubtarget<X86Subtarget>();
209 X86ScalarSSEf64 = Subtarget->hasSSE2();
210 X86ScalarSSEf32 = Subtarget->hasSSE1();
211 TD = getDataLayout();
213 resetOperationActions();
216 void X86TargetLowering::resetOperationActions() {
217 const TargetMachine &TM = getTargetMachine();
218 static bool FirstTimeThrough = true;
220 // If none of the target options have changed, then we don't need to reset the
221 // operation actions.
222 if (!FirstTimeThrough && TO == TM.Options) return;
224 if (!FirstTimeThrough) {
225 // Reinitialize the actions.
227 FirstTimeThrough = false;
232 // Set up the TargetLowering object.
233 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
235 // X86 is weird. It always uses i8 for shift amounts and setcc results.
236 setBooleanContents(ZeroOrOneBooleanContent);
237 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
238 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
240 // For 64-bit, since we have so many registers, use the ILP scheduler.
241 // For 32-bit, use the register pressure specific scheduling.
242 // For Atom, always use ILP scheduling.
243 if (Subtarget->isAtom())
244 setSchedulingPreference(Sched::ILP);
245 else if (Subtarget->is64Bit())
246 setSchedulingPreference(Sched::ILP);
248 setSchedulingPreference(Sched::RegPressure);
249 const X86RegisterInfo *RegInfo =
250 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
251 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
253 // Bypass expensive divides on Atom when compiling with O2.
254 if (TM.getOptLevel() >= CodeGenOpt::Default) {
255 if (Subtarget->hasSlowDivide32())
256 addBypassSlowDiv(32, 8);
257 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
258 addBypassSlowDiv(64, 16);
261 if (Subtarget->isTargetKnownWindowsMSVC()) {
262 // Setup Windows compiler runtime calls.
263 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
264 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
265 setLibcallName(RTLIB::SREM_I64, "_allrem");
266 setLibcallName(RTLIB::UREM_I64, "_aullrem");
267 setLibcallName(RTLIB::MUL_I64, "_allmul");
268 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
271 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
272 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
274 // The _ftol2 runtime function has an unusual calling conv, which
275 // is modeled by a special pseudo-instruction.
276 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
278 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
279 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
282 if (Subtarget->isTargetDarwin()) {
283 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
284 setUseUnderscoreSetJmp(false);
285 setUseUnderscoreLongJmp(false);
286 } else if (Subtarget->isTargetWindowsGNU()) {
287 // MS runtime is weird: it exports _setjmp, but longjmp!
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(false);
291 setUseUnderscoreSetJmp(true);
292 setUseUnderscoreLongJmp(true);
295 // Set up the register classes.
296 addRegisterClass(MVT::i8, &X86::GR8RegClass);
297 addRegisterClass(MVT::i16, &X86::GR16RegClass);
298 addRegisterClass(MVT::i32, &X86::GR32RegClass);
299 if (Subtarget->is64Bit())
300 addRegisterClass(MVT::i64, &X86::GR64RegClass);
302 for (MVT VT : MVT::integer_valuetypes())
303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
305 // We don't accept any truncstore of integer registers.
306 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
307 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
308 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
309 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
310 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
311 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 // SETOEQ and SETUNE require checking two conditions.
316 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
319 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
323 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
325 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
329 if (Subtarget->is64Bit()) {
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 } else if (!TM.Options.UseSoftFloat) {
333 // We have an algorithm for SSE2->double, and we turn this into a
334 // 64-bit FILD followed by conditional FADD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 // We have an algorithm for SSE2, and we turn this into a 64-bit
337 // FILD for other targets.
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
341 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
343 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
346 if (!TM.Options.UseSoftFloat) {
347 // SSE has no i16 to fp conversion, only i32
348 if (X86ScalarSSEf32) {
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 // f32 and f64 cases are Legal, f80 case is not
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
361 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
362 // are Legal, f80 is custom lowered.
363 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
364 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
366 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
368 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
371 if (X86ScalarSSEf32) {
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
373 // f32 and f64 cases are Legal, f80 case is not
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 // Handle FP_TO_UINT by promoting the destination to a larger signed
382 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
386 if (Subtarget->is64Bit()) {
387 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
389 } else if (!TM.Options.UseSoftFloat) {
390 // Since AVX is a superset of SSE3, only check for SSE here.
391 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
392 // Expand FP_TO_UINT into a select.
393 // FIXME: We would like to use a Custom expander here eventually to do
394 // the optimal thing for SSE vs. the default expansion in the legalizer.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
397 // With SSE3 we can use fisttpll to convert to a signed i64; without
398 // SSE, we're stuck with a fistpll.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
402 if (isTargetFTOL()) {
403 // Use the _ftol2 runtime function, which has a pseudo-instruction
404 // to handle its weird calling convention.
405 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
408 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
409 if (!X86ScalarSSEf64) {
410 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
411 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
414 // Without SSE, i64->f64 goes through memory.
415 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
419 // Scalar integer divide and remainder are lowered to use operations that
420 // produce two results, to match the available instructions. This exposes
421 // the two-result form to trivial CSE, which is able to combine x/y and x%y
422 // into a single instruction.
424 // Scalar integer multiply-high is also lowered to use two-result
425 // operations, to match the available instructions. However, plain multiply
426 // (low) operations are left as Legal, as there are single-result
427 // instructions for this in x86. Using the two-result multiply instructions
428 // when both high and low results are needed must be arranged by dagcombine.
429 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
431 setOperationAction(ISD::MULHS, VT, Expand);
432 setOperationAction(ISD::MULHU, VT, Expand);
433 setOperationAction(ISD::SDIV, VT, Expand);
434 setOperationAction(ISD::UDIV, VT, Expand);
435 setOperationAction(ISD::SREM, VT, Expand);
436 setOperationAction(ISD::UREM, VT, Expand);
438 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
439 setOperationAction(ISD::ADDC, VT, Custom);
440 setOperationAction(ISD::ADDE, VT, Custom);
441 setOperationAction(ISD::SUBC, VT, Custom);
442 setOperationAction(ISD::SUBE, VT, Custom);
445 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
446 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
447 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
449 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
451 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
452 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
466 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
467 setOperationAction(ISD::FREM , MVT::f32 , Expand);
468 setOperationAction(ISD::FREM , MVT::f64 , Expand);
469 setOperationAction(ISD::FREM , MVT::f80 , Expand);
470 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
472 // Promote the i8 variants and force them on up to i32 which has a shorter
474 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
478 if (Subtarget->hasBMI()) {
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
490 if (Subtarget->hasLZCNT()) {
491 // When promoting the i8 variants, force them to i32 for a shorter
493 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
494 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
496 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
499 if (Subtarget->is64Bit())
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
502 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
508 if (Subtarget->is64Bit()) {
509 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
514 // Special handling for half-precision floating point conversions.
515 // If we don't have F16C support, then lower half float conversions
516 // into library calls.
517 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
518 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
522 // There's never any support for operations beyond MVT::f32.
523 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
524 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
525 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
526 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
528 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
529 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
530 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
531 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
532 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
535 if (Subtarget->hasPOPCNT()) {
536 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
538 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
539 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
540 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
541 if (Subtarget->is64Bit())
542 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
545 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
547 if (!Subtarget->hasMOVBE())
548 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
550 // These should be promoted to a larger select which is supported.
551 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
552 // X86 wants to expand cmov itself.
553 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
554 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
555 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
556 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
557 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
559 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
562 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
563 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
565 if (Subtarget->is64Bit()) {
566 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
569 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
570 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
571 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
572 // support continuation, user-level threading, and etc.. As a result, no
573 // other SjLj exception interfaces are implemented and please don't build
574 // your own exception handling based on them.
575 // LLVM/Clang supports zero-cost DWARF exception handling.
576 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
577 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
580 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
583 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
584 if (Subtarget->is64Bit())
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
586 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
590 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
591 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
592 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
595 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
596 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
597 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
598 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
599 if (Subtarget->is64Bit()) {
600 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
601 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
602 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
605 if (Subtarget->hasSSE1())
606 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
608 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
610 // Expand certain atomics
611 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
615 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
618 if (Subtarget->hasCmpxchg16b()) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
622 // FIXME - use subtarget debug flags
623 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
624 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
625 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
628 if (Subtarget->is64Bit()) {
629 setExceptionPointerRegister(X86::RAX);
630 setExceptionSelectorRegister(X86::RDX);
632 setExceptionPointerRegister(X86::EAX);
633 setExceptionSelectorRegister(X86::EDX);
635 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
636 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
638 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
639 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::TRAP, MVT::Other, Legal);
642 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
644 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
645 setOperationAction(ISD::VASTART , MVT::Other, Custom);
646 setOperationAction(ISD::VAEND , MVT::Other, Expand);
647 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
648 // TargetInfo::X86_64ABIBuiltinVaList
649 setOperationAction(ISD::VAARG , MVT::Other, Custom);
650 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
652 // TargetInfo::CharPtrBuiltinVaList
653 setOperationAction(ISD::VAARG , MVT::Other, Expand);
654 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
657 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
658 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
660 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
662 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
663 // f32 and f64 use SSE.
664 // Set up the FP register classes.
665 addRegisterClass(MVT::f32, &X86::FR32RegClass);
666 addRegisterClass(MVT::f64, &X86::FR64RegClass);
668 // Use ANDPD to simulate FABS.
669 setOperationAction(ISD::FABS , MVT::f64, Custom);
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f64, Custom);
674 setOperationAction(ISD::FNEG , MVT::f32, Custom);
676 // Use ANDPD and ORPD to simulate FCOPYSIGN.
677 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
678 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
680 // Lower this to FGETSIGNx86 plus an AND.
681 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
682 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
684 // We don't support sin/cos/fmod
685 setOperationAction(ISD::FSIN , MVT::f64, Expand);
686 setOperationAction(ISD::FCOS , MVT::f64, Expand);
687 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
688 setOperationAction(ISD::FSIN , MVT::f32, Expand);
689 setOperationAction(ISD::FCOS , MVT::f32, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
692 // Expand FP immediates into loads from the stack, except for the special
694 addLegalFPImmediate(APFloat(+0.0)); // xorpd
695 addLegalFPImmediate(APFloat(+0.0f)); // xorps
696 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
697 // Use SSE for f32, x87 for f64.
698 // Set up the FP register classes.
699 addRegisterClass(MVT::f32, &X86::FR32RegClass);
700 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 // Use ANDPS to simulate FABS.
703 setOperationAction(ISD::FABS , MVT::f32, Custom);
705 // Use XORP to simulate FNEG.
706 setOperationAction(ISD::FNEG , MVT::f32, Custom);
708 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
710 // Use ANDPS and ORPS to simulate FCOPYSIGN.
711 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
712 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
714 // We don't support sin/cos/fmod
715 setOperationAction(ISD::FSIN , MVT::f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::f32, Expand);
717 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
719 // Special cases we handle for FP constants.
720 addLegalFPImmediate(APFloat(+0.0f)); // xorps
721 addLegalFPImmediate(APFloat(+0.0)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 } else if (!TM.Options.UseSoftFloat) {
732 // f32 and f64 in x87.
733 // Set up the FP register classes.
734 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
735 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
737 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
738 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
739 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
742 if (!TM.Options.UnsafeFPMath) {
743 setOperationAction(ISD::FSIN , MVT::f64, Expand);
744 setOperationAction(ISD::FSIN , MVT::f32, Expand);
745 setOperationAction(ISD::FCOS , MVT::f64, Expand);
746 setOperationAction(ISD::FCOS , MVT::f32, Expand);
747 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
748 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
750 addLegalFPImmediate(APFloat(+0.0)); // FLD0
751 addLegalFPImmediate(APFloat(+1.0)); // FLD1
752 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
753 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
754 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
755 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
756 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
757 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
760 // We don't support FMA.
761 setOperationAction(ISD::FMA, MVT::f64, Expand);
762 setOperationAction(ISD::FMA, MVT::f32, Expand);
764 // Long double always uses X87.
765 if (!TM.Options.UseSoftFloat) {
766 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
767 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
768 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
770 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
771 addLegalFPImmediate(TmpFlt); // FLD0
773 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
776 APFloat TmpFlt2(+1.0);
777 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
779 addLegalFPImmediate(TmpFlt2); // FLD1
780 TmpFlt2.changeSign();
781 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
784 if (!TM.Options.UnsafeFPMath) {
785 setOperationAction(ISD::FSIN , MVT::f80, Expand);
786 setOperationAction(ISD::FCOS , MVT::f80, Expand);
787 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
790 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
791 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
792 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
793 setOperationAction(ISD::FRINT, MVT::f80, Expand);
794 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
795 setOperationAction(ISD::FMA, MVT::f80, Expand);
798 // Always use a library call for pow.
799 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
800 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
801 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
803 setOperationAction(ISD::FLOG, MVT::f80, Expand);
804 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
805 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
806 setOperationAction(ISD::FEXP, MVT::f80, Expand);
807 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
808 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
809 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (MVT VT : MVT::vector_valuetypes()) {
815 setOperationAction(ISD::ADD , VT, Expand);
816 setOperationAction(ISD::SUB , VT, Expand);
817 setOperationAction(ISD::FADD, VT, Expand);
818 setOperationAction(ISD::FNEG, VT, Expand);
819 setOperationAction(ISD::FSUB, VT, Expand);
820 setOperationAction(ISD::MUL , VT, Expand);
821 setOperationAction(ISD::FMUL, VT, Expand);
822 setOperationAction(ISD::SDIV, VT, Expand);
823 setOperationAction(ISD::UDIV, VT, Expand);
824 setOperationAction(ISD::FDIV, VT, Expand);
825 setOperationAction(ISD::SREM, VT, Expand);
826 setOperationAction(ISD::UREM, VT, Expand);
827 setOperationAction(ISD::LOAD, VT, Expand);
828 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
831 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
832 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
833 setOperationAction(ISD::FABS, VT, Expand);
834 setOperationAction(ISD::FSIN, VT, Expand);
835 setOperationAction(ISD::FSINCOS, VT, Expand);
836 setOperationAction(ISD::FCOS, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FREM, VT, Expand);
839 setOperationAction(ISD::FMA, VT, Expand);
840 setOperationAction(ISD::FPOWI, VT, Expand);
841 setOperationAction(ISD::FSQRT, VT, Expand);
842 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
843 setOperationAction(ISD::FFLOOR, VT, Expand);
844 setOperationAction(ISD::FCEIL, VT, Expand);
845 setOperationAction(ISD::FTRUNC, VT, Expand);
846 setOperationAction(ISD::FRINT, VT, Expand);
847 setOperationAction(ISD::FNEARBYINT, VT, Expand);
848 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
849 setOperationAction(ISD::MULHS, VT, Expand);
850 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHU, VT, Expand);
852 setOperationAction(ISD::SDIVREM, VT, Expand);
853 setOperationAction(ISD::UDIVREM, VT, Expand);
854 setOperationAction(ISD::FPOW, VT, Expand);
855 setOperationAction(ISD::CTPOP, VT, Expand);
856 setOperationAction(ISD::CTTZ, VT, Expand);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
858 setOperationAction(ISD::CTLZ, VT, Expand);
859 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::SHL, VT, Expand);
861 setOperationAction(ISD::SRA, VT, Expand);
862 setOperationAction(ISD::SRL, VT, Expand);
863 setOperationAction(ISD::ROTL, VT, Expand);
864 setOperationAction(ISD::ROTR, VT, Expand);
865 setOperationAction(ISD::BSWAP, VT, Expand);
866 setOperationAction(ISD::SETCC, VT, Expand);
867 setOperationAction(ISD::FLOG, VT, Expand);
868 setOperationAction(ISD::FLOG2, VT, Expand);
869 setOperationAction(ISD::FLOG10, VT, Expand);
870 setOperationAction(ISD::FEXP, VT, Expand);
871 setOperationAction(ISD::FEXP2, VT, Expand);
872 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
873 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
874 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
875 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
876 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
877 setOperationAction(ISD::TRUNCATE, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
879 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
880 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
881 setOperationAction(ISD::VSELECT, VT, Expand);
882 setOperationAction(ISD::SELECT_CC, VT, Expand);
883 for (MVT InnerVT : MVT::vector_valuetypes()) {
884 setTruncStoreAction(InnerVT, VT, Expand);
886 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
887 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
889 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
890 // types, we have to deal with them whether we ask for Expansion or not.
891 // Setting Expand causes its own optimisation problems though, so leave
893 if (VT.getVectorElementType() == MVT::i1)
894 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
898 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
899 // with -msoft-float, disable use of MMX as well.
900 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
901 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
902 // No operations on x86mmx supported, everything uses intrinsics.
905 // MMX-sized vectors (other than x86mmx) are expected to be expanded
906 // into smaller operations.
907 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
908 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
909 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
910 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
911 setOperationAction(ISD::AND, MVT::v8i8, Expand);
912 setOperationAction(ISD::AND, MVT::v4i16, Expand);
913 setOperationAction(ISD::AND, MVT::v2i32, Expand);
914 setOperationAction(ISD::AND, MVT::v1i64, Expand);
915 setOperationAction(ISD::OR, MVT::v8i8, Expand);
916 setOperationAction(ISD::OR, MVT::v4i16, Expand);
917 setOperationAction(ISD::OR, MVT::v2i32, Expand);
918 setOperationAction(ISD::OR, MVT::v1i64, Expand);
919 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
928 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
929 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
930 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
931 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
937 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
938 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
940 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
941 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
942 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
943 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
944 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
945 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
946 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
947 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
948 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
951 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
952 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Only provide customized ctpop vector bit twiddling for vector types we
1000 // know to perform better than using the popcnt instructions on each vector
1001 // element. If popcnt isn't supported, always provide the custom version.
1002 if (!Subtarget->hasPOPCNT()) {
1003 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
1004 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
1007 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1008 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1009 MVT VT = (MVT::SimpleValueType)i;
1010 // Do not attempt to custom lower non-power-of-2 vectors
1011 if (!isPowerOf2_32(VT.getVectorNumElements()))
1013 // Do not attempt to custom lower non-128-bit vectors
1014 if (!VT.is128BitVector())
1016 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1021 // We support custom legalizing of sext and anyext loads for specific
1022 // memory vector types which we can load as a scalar (or sequence of
1023 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1024 // loads these must work with a single scalar load.
1025 for (MVT VT : MVT::integer_vector_valuetypes()) {
1026 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1032 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1033 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1037 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1038 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1039 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1040 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1044 if (Subtarget->is64Bit()) {
1045 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1049 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1050 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1051 MVT VT = (MVT::SimpleValueType)i;
1053 // Do not attempt to promote non-128-bit vectors
1054 if (!VT.is128BitVector())
1057 setOperationAction(ISD::AND, VT, Promote);
1058 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1059 setOperationAction(ISD::OR, VT, Promote);
1060 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1061 setOperationAction(ISD::XOR, VT, Promote);
1062 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1063 setOperationAction(ISD::LOAD, VT, Promote);
1064 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1065 setOperationAction(ISD::SELECT, VT, Promote);
1066 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1069 // Custom lower v2i64 and v2f64 selects.
1070 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1071 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1072 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1073 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1080 // As there is no 64-bit GPR available, we need build a special custom
1081 // sequence to convert from v2i32 to v2f32.
1082 if (!Subtarget->is64Bit())
1083 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1085 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1086 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1088 for (MVT VT : MVT::fp_vector_valuetypes())
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1091 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1092 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1093 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1096 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1097 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1105 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1114 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1115 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1119 // FIXME: Do we need to handle scalar-to-vector here?
1120 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1123 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1124 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1125 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1127 // There is no BLENDI for byte vectors. We don't need to custom lower
1128 // some vselects for now.
1129 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1131 // SSE41 brings specific instructions for doing vector sign extend even in
1132 // cases where we don't have SRA.
1133 for (MVT VT : MVT::integer_vector_valuetypes()) {
1134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1139 // i8 and i16 vectors are custom because the source register and source
1140 // source memory operand types are not the same width. f32 vectors are
1141 // custom since the immediate controlling the insert encodes additional
1143 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1153 // FIXME: these should be Legal, but that's only for the case where
1154 // the index is constant. For now custom expand to deal with that.
1155 if (Subtarget->is64Bit()) {
1156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1157 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1161 if (Subtarget->hasSSE2()) {
1162 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1163 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1165 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1166 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1168 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1169 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1171 // In the customized shift lowering, the legal cases in AVX2 will be
1173 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1174 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1176 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1177 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1179 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1182 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1183 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1184 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1185 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1186 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1187 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1188 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1190 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1191 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1192 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1194 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1198 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1199 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1200 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1201 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1202 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1204 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1205 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1207 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1211 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1212 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1213 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1214 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1215 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1216 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1217 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1218 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1220 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1221 // even though v8i16 is a legal type.
1222 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1223 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1224 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1226 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1227 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1228 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1230 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1231 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1233 for (MVT VT : MVT::fp_vector_valuetypes())
1234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1236 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1242 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1243 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1245 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1246 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1247 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1251 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1254 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1255 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1257 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1259 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1261 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1262 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1263 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1264 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1265 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1266 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1267 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1268 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1269 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1270 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1272 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1273 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1274 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1276 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1277 setOperationAction(ISD::FMA, MVT::f32, Legal);
1278 setOperationAction(ISD::FMA, MVT::f64, Legal);
1281 if (Subtarget->hasInt256()) {
1282 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1283 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1284 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1285 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1287 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1288 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1289 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1290 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1292 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1293 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1294 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1295 // Don't lower v32i8 because there is no 128-bit byte mul
1297 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1299 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1300 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1302 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1303 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1305 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1306 // when we have a 256bit-wide blend with immediate.
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1309 // Only provide customized ctpop vector bit twiddling for vector types we
1310 // know to perform better than using the popcnt instructions on each
1311 // vector element. If popcnt isn't supported, always provide the custom
1313 if (!Subtarget->hasPOPCNT())
1314 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1316 // Custom CTPOP always performs better on natively supported v8i32
1317 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1319 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1320 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1321 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1322 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1324 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1325 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1326 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1327 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1329 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1331 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1332 // Don't lower v32i8 because there is no 128-bit byte mul
1335 // In the customized shift lowering, the legal cases in AVX2 will be
1337 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1338 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1340 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1341 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1343 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1345 // Custom lower several nodes for 256-bit types.
1346 for (MVT VT : MVT::vector_valuetypes()) {
1347 if (VT.getScalarSizeInBits() >= 32) {
1348 setOperationAction(ISD::MLOAD, VT, Legal);
1349 setOperationAction(ISD::MSTORE, VT, Legal);
1351 // Extract subvector is special because the value type
1352 // (result) is 128-bit but the source is 256-bit wide.
1353 if (VT.is128BitVector()) {
1354 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1356 // Do not attempt to custom lower other non-256-bit vectors
1357 if (!VT.is256BitVector())
1360 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1361 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1364 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1365 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1369 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1370 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1371 MVT VT = (MVT::SimpleValueType)i;
1373 // Do not attempt to promote non-256-bit vectors
1374 if (!VT.is256BitVector())
1377 setOperationAction(ISD::AND, VT, Promote);
1378 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1379 setOperationAction(ISD::OR, VT, Promote);
1380 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1381 setOperationAction(ISD::XOR, VT, Promote);
1382 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1383 setOperationAction(ISD::LOAD, VT, Promote);
1384 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1385 setOperationAction(ISD::SELECT, VT, Promote);
1386 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1390 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1391 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1392 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1393 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1394 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1396 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1397 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1398 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1400 for (MVT VT : MVT::fp_vector_valuetypes())
1401 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1403 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1404 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1405 setOperationAction(ISD::XOR, MVT::i1, Legal);
1406 setOperationAction(ISD::OR, MVT::i1, Legal);
1407 setOperationAction(ISD::AND, MVT::i1, Legal);
1408 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1409 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1410 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1411 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1412 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1414 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1415 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1417 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1418 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1419 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1421 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1422 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1423 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1424 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1425 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1426 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1427 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1428 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1430 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1431 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1434 if (Subtarget->is64Bit()) {
1435 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1436 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1438 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1440 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1441 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1442 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1443 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1444 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1445 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1446 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1448 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1449 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1450 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1451 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1452 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1453 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1455 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1456 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1457 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1458 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1459 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1460 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1461 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1462 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1463 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1464 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1465 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1466 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1467 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1476 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1477 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1479 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1481 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1482 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1484 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1486 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1491 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1492 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1494 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1495 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1497 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1499 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1500 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1502 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1503 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1505 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1506 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1508 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1509 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1510 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1511 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1512 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1513 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1515 if (Subtarget->hasCDI()) {
1516 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1517 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1520 // Custom lower several nodes.
1521 for (MVT VT : MVT::vector_valuetypes()) {
1522 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1523 // Extract subvector is special because the value type
1524 // (result) is 256/128-bit but the source is 512-bit wide.
1525 if (VT.is128BitVector() || VT.is256BitVector()) {
1526 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1528 if (VT.getVectorElementType() == MVT::i1)
1529 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1531 // Do not attempt to custom lower other non-512-bit vectors
1532 if (!VT.is512BitVector())
1535 if ( EltSize >= 32) {
1536 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1537 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1538 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1539 setOperationAction(ISD::VSELECT, VT, Legal);
1540 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1541 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1542 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1543 setOperationAction(ISD::MLOAD, VT, Legal);
1544 setOperationAction(ISD::MSTORE, VT, Legal);
1547 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1548 MVT VT = (MVT::SimpleValueType)i;
1550 // Do not attempt to promote non-512-bit vectors.
1551 if (!VT.is512BitVector())
1554 setOperationAction(ISD::SELECT, VT, Promote);
1555 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1559 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1560 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1561 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1563 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1564 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1566 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1567 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1568 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1569 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1570 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1571 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1572 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1573 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1574 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 const MVT VT = (MVT::SimpleValueType)i;
1579 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1581 // Do not attempt to promote non-512-bit vectors.
1582 if (!VT.is512BitVector())
1586 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1587 setOperationAction(ISD::VSELECT, VT, Legal);
1592 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1593 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1594 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1596 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1597 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1598 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1600 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1601 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1602 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1603 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1604 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1605 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1608 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1609 // of this type with custom code.
1610 for (MVT VT : MVT::vector_valuetypes())
1611 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1613 // We want to custom lower some of our intrinsics.
1614 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1615 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1616 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1617 if (!Subtarget->is64Bit())
1618 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1620 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1621 // handle type legalization for these operations here.
1623 // FIXME: We really should do custom legalization for addition and
1624 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1625 // than generic legalization for 64-bit multiplication-with-overflow, though.
1626 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1627 // Add/Sub/Mul with overflow operations are custom lowered.
1629 setOperationAction(ISD::SADDO, VT, Custom);
1630 setOperationAction(ISD::UADDO, VT, Custom);
1631 setOperationAction(ISD::SSUBO, VT, Custom);
1632 setOperationAction(ISD::USUBO, VT, Custom);
1633 setOperationAction(ISD::SMULO, VT, Custom);
1634 setOperationAction(ISD::UMULO, VT, Custom);
1638 if (!Subtarget->is64Bit()) {
1639 // These libcalls are not available in 32-bit.
1640 setLibcallName(RTLIB::SHL_I128, nullptr);
1641 setLibcallName(RTLIB::SRL_I128, nullptr);
1642 setLibcallName(RTLIB::SRA_I128, nullptr);
1645 // Combine sin / cos into one node or libcall if possible.
1646 if (Subtarget->hasSinCos()) {
1647 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1648 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1649 if (Subtarget->isTargetDarwin()) {
1650 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1651 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1652 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1653 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1657 if (Subtarget->isTargetWin64()) {
1658 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1659 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1660 setOperationAction(ISD::SREM, MVT::i128, Custom);
1661 setOperationAction(ISD::UREM, MVT::i128, Custom);
1662 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1663 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1666 // We have target-specific dag combine patterns for the following nodes:
1667 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1668 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1669 setTargetDAGCombine(ISD::VSELECT);
1670 setTargetDAGCombine(ISD::SELECT);
1671 setTargetDAGCombine(ISD::SHL);
1672 setTargetDAGCombine(ISD::SRA);
1673 setTargetDAGCombine(ISD::SRL);
1674 setTargetDAGCombine(ISD::OR);
1675 setTargetDAGCombine(ISD::AND);
1676 setTargetDAGCombine(ISD::ADD);
1677 setTargetDAGCombine(ISD::FADD);
1678 setTargetDAGCombine(ISD::FSUB);
1679 setTargetDAGCombine(ISD::FMA);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::STORE);
1683 setTargetDAGCombine(ISD::ZERO_EXTEND);
1684 setTargetDAGCombine(ISD::ANY_EXTEND);
1685 setTargetDAGCombine(ISD::SIGN_EXTEND);
1686 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1687 setTargetDAGCombine(ISD::TRUNCATE);
1688 setTargetDAGCombine(ISD::SINT_TO_FP);
1689 setTargetDAGCombine(ISD::SETCC);
1690 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1691 setTargetDAGCombine(ISD::BUILD_VECTOR);
1692 if (Subtarget->is64Bit())
1693 setTargetDAGCombine(ISD::MUL);
1694 setTargetDAGCombine(ISD::XOR);
1696 computeRegisterProperties();
1698 // On Darwin, -Os means optimize for size without hurting performance,
1699 // do not reduce the limit.
1700 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1701 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1702 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1703 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1704 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1705 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1706 setPrefLoopAlignment(4); // 2^4 bytes.
1708 // Predictable cmov don't hurt on atom because it's in-order.
1709 PredictableSelectIsExpensive = !Subtarget->isAtom();
1710 EnableExtLdPromotion = true;
1711 setPrefFunctionAlignment(4); // 2^4 bytes.
1713 verifyIntrinsicTables();
1716 // This has so far only been implemented for 64-bit MachO.
1717 bool X86TargetLowering::useLoadStackGuardNode() const {
1718 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1721 TargetLoweringBase::LegalizeTypeAction
1722 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1723 if (ExperimentalVectorWideningLegalization &&
1724 VT.getVectorNumElements() != 1 &&
1725 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1726 return TypeWidenVector;
1728 return TargetLoweringBase::getPreferredVectorAction(VT);
1731 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1733 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1735 const unsigned NumElts = VT.getVectorNumElements();
1736 const EVT EltVT = VT.getVectorElementType();
1737 if (VT.is512BitVector()) {
1738 if (Subtarget->hasAVX512())
1739 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1740 EltVT == MVT::f32 || EltVT == MVT::f64)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1745 if (Subtarget->hasBWI())
1746 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1748 case 32: return MVT::v32i1;
1749 case 64: return MVT::v64i1;
1753 if (VT.is256BitVector() || VT.is128BitVector()) {
1754 if (Subtarget->hasVLX())
1755 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1756 EltVT == MVT::f32 || EltVT == MVT::f64)
1758 case 2: return MVT::v2i1;
1759 case 4: return MVT::v4i1;
1760 case 8: return MVT::v8i1;
1762 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1763 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1765 case 8: return MVT::v8i1;
1766 case 16: return MVT::v16i1;
1767 case 32: return MVT::v32i1;
1771 return VT.changeVectorElementTypeToInteger();
1774 /// Helper for getByValTypeAlignment to determine
1775 /// the desired ByVal argument alignment.
1776 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1779 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1780 if (VTy->getBitWidth() == 128)
1782 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1783 unsigned EltAlign = 0;
1784 getMaxByValAlign(ATy->getElementType(), EltAlign);
1785 if (EltAlign > MaxAlign)
1786 MaxAlign = EltAlign;
1787 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1788 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1789 unsigned EltAlign = 0;
1790 getMaxByValAlign(STy->getElementType(i), EltAlign);
1791 if (EltAlign > MaxAlign)
1792 MaxAlign = EltAlign;
1799 /// Return the desired alignment for ByVal aggregate
1800 /// function arguments in the caller parameter area. For X86, aggregates
1801 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1802 /// are at 4-byte boundaries.
1803 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1804 if (Subtarget->is64Bit()) {
1805 // Max of 8 and alignment of type.
1806 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1813 if (Subtarget->hasSSE1())
1814 getMaxByValAlign(Ty, Align);
1818 /// Returns the target specific optimal type for load
1819 /// and store operations as a result of memset, memcpy, and memmove
1820 /// lowering. If DstAlign is zero that means it's safe to destination
1821 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1822 /// means there isn't a need to check it against alignment requirement,
1823 /// probably because the source does not need to be loaded. If 'IsMemset' is
1824 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1825 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1826 /// source is constant so it does not need to be loaded.
1827 /// It returns EVT::Other if the type should be determined using generic
1828 /// target-independent logic.
1830 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1831 unsigned DstAlign, unsigned SrcAlign,
1832 bool IsMemset, bool ZeroMemset,
1834 MachineFunction &MF) const {
1835 const Function *F = MF.getFunction();
1836 if ((!IsMemset || ZeroMemset) &&
1837 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1838 Attribute::NoImplicitFloat)) {
1840 (Subtarget->isUnalignedMemAccessFast() ||
1841 ((DstAlign == 0 || DstAlign >= 16) &&
1842 (SrcAlign == 0 || SrcAlign >= 16)))) {
1844 if (Subtarget->hasInt256())
1846 if (Subtarget->hasFp256())
1849 if (Subtarget->hasSSE2())
1851 if (Subtarget->hasSSE1())
1853 } else if (!MemcpyStrSrc && Size >= 8 &&
1854 !Subtarget->is64Bit() &&
1855 Subtarget->hasSSE2()) {
1856 // Do not use f64 to lower memcpy if source is string constant. It's
1857 // better to use i32 to avoid the loads.
1861 if (Subtarget->is64Bit() && Size >= 8)
1866 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1868 return X86ScalarSSEf32;
1869 else if (VT == MVT::f64)
1870 return X86ScalarSSEf64;
1875 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1880 *Fast = Subtarget->isUnalignedMemAccessFast();
1884 /// Return the entry encoding for a jump table in the
1885 /// current function. The returned value is a member of the
1886 /// MachineJumpTableInfo::JTEntryKind enum.
1887 unsigned X86TargetLowering::getJumpTableEncoding() const {
1888 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1890 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT())
1892 return MachineJumpTableInfo::EK_Custom32;
1894 // Otherwise, use the normal jump table encoding heuristics.
1895 return TargetLowering::getJumpTableEncoding();
1899 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1900 const MachineBasicBlock *MBB,
1901 unsigned uid,MCContext &Ctx) const{
1902 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1903 Subtarget->isPICStyleGOT());
1904 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1906 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1907 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1910 /// Returns relocation base for the given PIC jumptable.
1911 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1912 SelectionDAG &DAG) const {
1913 if (!Subtarget->is64Bit())
1914 // This doesn't have SDLoc associated with it, but is not really the
1915 // same as a Register.
1916 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1920 /// This returns the relocation base for the given PIC jumptable,
1921 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1922 const MCExpr *X86TargetLowering::
1923 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1924 MCContext &Ctx) const {
1925 // X86-64 uses RIP relative addressing based on the jump table label.
1926 if (Subtarget->isPICStyleRIPRel())
1927 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1929 // Otherwise, the reference is relative to the PIC base.
1930 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1933 // FIXME: Why this routine is here? Move to RegInfo!
1934 std::pair<const TargetRegisterClass*, uint8_t>
1935 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1936 const TargetRegisterClass *RRC = nullptr;
1938 switch (VT.SimpleTy) {
1940 return TargetLowering::findRepresentativeClass(VT);
1941 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1942 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1945 RRC = &X86::VR64RegClass;
1947 case MVT::f32: case MVT::f64:
1948 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1949 case MVT::v4f32: case MVT::v2f64:
1950 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1952 RRC = &X86::VR128RegClass;
1955 return std::make_pair(RRC, Cost);
1958 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1959 unsigned &Offset) const {
1960 if (!Subtarget->isTargetLinux())
1963 if (Subtarget->is64Bit()) {
1964 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1966 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1978 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1979 unsigned DestAS) const {
1980 assert(SrcAS != DestAS && "Expected different address spaces!");
1982 return SrcAS < 256 && DestAS < 256;
1985 //===----------------------------------------------------------------------===//
1986 // Return Value Calling Convention Implementation
1987 //===----------------------------------------------------------------------===//
1989 #include "X86GenCallingConv.inc"
1992 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1993 MachineFunction &MF, bool isVarArg,
1994 const SmallVectorImpl<ISD::OutputArg> &Outs,
1995 LLVMContext &Context) const {
1996 SmallVector<CCValAssign, 16> RVLocs;
1997 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1998 return CCInfo.CheckReturn(Outs, RetCC_X86);
2001 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2002 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2007 X86TargetLowering::LowerReturn(SDValue Chain,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::OutputArg> &Outs,
2010 const SmallVectorImpl<SDValue> &OutVals,
2011 SDLoc dl, SelectionDAG &DAG) const {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2017 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2020 SmallVector<SDValue, 6> RetOps;
2021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2022 // Operand #1 = Bytes To Pop
2023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2026 // Copy the result values into the output registers.
2027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2028 CCValAssign &VA = RVLocs[i];
2029 assert(VA.isRegLoc() && "Can only return in registers!");
2030 SDValue ValToCopy = OutVals[i];
2031 EVT ValVT = ValToCopy.getValueType();
2033 // Promote values to the appropriate types.
2034 if (VA.getLocInfo() == CCValAssign::SExt)
2035 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2036 else if (VA.getLocInfo() == CCValAssign::ZExt)
2037 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2038 else if (VA.getLocInfo() == CCValAssign::AExt)
2039 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2040 else if (VA.getLocInfo() == CCValAssign::BCvt)
2041 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2043 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2044 "Unexpected FP-extend for return value.");
2046 // If this is x86-64, and we disabled SSE, we can't return FP values,
2047 // or SSE or MMX vectors.
2048 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2049 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2051 report_fatal_error("SSE register return with SSE disabled");
2053 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2054 // llvm-gcc has never done it right and no one has noticed, so this
2055 // should be OK for now.
2056 if (ValVT == MVT::f64 &&
2057 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2058 report_fatal_error("SSE2 register return with SSE2 disabled");
2060 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2061 // the RET instruction and handled by the FP Stackifier.
2062 if (VA.getLocReg() == X86::FP0 ||
2063 VA.getLocReg() == X86::FP1) {
2064 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2065 // change the value to the FP stack register class.
2066 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2067 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2068 RetOps.push_back(ValToCopy);
2069 // Don't emit a copytoreg.
2073 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2074 // which is returned in RAX / RDX.
2075 if (Subtarget->is64Bit()) {
2076 if (ValVT == MVT::x86mmx) {
2077 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2078 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2079 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2081 // If we don't have SSE2 available, convert to v4f32 so the generated
2082 // register is legal.
2083 if (!Subtarget->hasSSE2())
2084 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2089 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2090 Flag = Chain.getValue(1);
2091 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2094 // The x86-64 ABIs require that for returning structs by value we copy
2095 // the sret argument into %rax/%eax (depending on ABI) for the return.
2096 // Win32 requires us to put the sret argument to %eax as well.
2097 // We saved the argument into a virtual register in the entry block,
2098 // so now we copy the value out and into %rax/%eax.
2099 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2100 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2101 MachineFunction &MF = DAG.getMachineFunction();
2102 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2103 unsigned Reg = FuncInfo->getSRetReturnReg();
2105 "SRetReturnReg should have been set in LowerFormalArguments().");
2106 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2109 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2110 X86::RAX : X86::EAX;
2111 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2112 Flag = Chain.getValue(1);
2114 // RAX/EAX now acts like a return value.
2115 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2118 RetOps[0] = Chain; // Update chain.
2120 // Add the flag if we have it.
2122 RetOps.push_back(Flag);
2124 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2127 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2128 if (N->getNumValues() != 1)
2130 if (!N->hasNUsesOfValue(1, 0))
2133 SDValue TCChain = Chain;
2134 SDNode *Copy = *N->use_begin();
2135 if (Copy->getOpcode() == ISD::CopyToReg) {
2136 // If the copy has a glue operand, we conservatively assume it isn't safe to
2137 // perform a tail call.
2138 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2140 TCChain = Copy->getOperand(0);
2141 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2144 bool HasRet = false;
2145 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2147 if (UI->getOpcode() != X86ISD::RET_FLAG)
2149 // If we are returning more than one value, we can definitely
2150 // not make a tail call see PR19530
2151 if (UI->getNumOperands() > 4)
2153 if (UI->getNumOperands() == 4 &&
2154 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2167 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2168 ISD::NodeType ExtendKind) const {
2170 // TODO: Is this also valid on 32-bit?
2171 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2172 ReturnMVT = MVT::i8;
2174 ReturnMVT = MVT::i32;
2176 EVT MinVT = getRegisterType(Context, ReturnMVT);
2177 return VT.bitsLT(MinVT) ? MinVT : VT;
2180 /// Lower the result values of a call into the
2181 /// appropriate copies out of appropriate physical registers.
2184 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2185 CallingConv::ID CallConv, bool isVarArg,
2186 const SmallVectorImpl<ISD::InputArg> &Ins,
2187 SDLoc dl, SelectionDAG &DAG,
2188 SmallVectorImpl<SDValue> &InVals) const {
2190 // Assign locations to each value returned by this call.
2191 SmallVector<CCValAssign, 16> RVLocs;
2192 bool Is64Bit = Subtarget->is64Bit();
2193 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2195 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2197 // Copy all of the result registers out of their specified physreg.
2198 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2199 CCValAssign &VA = RVLocs[i];
2200 EVT CopyVT = VA.getValVT();
2202 // If this is x86-64, and we disabled SSE, we can't return FP values
2203 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2204 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2205 report_fatal_error("SSE register return with SSE disabled");
2208 // If we prefer to use the value in xmm registers, copy it out as f80 and
2209 // use a truncate to move it from fp stack reg to xmm reg.
2210 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2211 isScalarFPTypeInSSEReg(VA.getValVT()))
2214 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2215 CopyVT, InFlag).getValue(1);
2216 SDValue Val = Chain.getValue(0);
2218 if (CopyVT != VA.getValVT())
2219 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2220 // This truncation won't change the value.
2221 DAG.getIntPtrConstant(1));
2223 InFlag = Chain.getValue(2);
2224 InVals.push_back(Val);
2230 //===----------------------------------------------------------------------===//
2231 // C & StdCall & Fast Calling Convention implementation
2232 //===----------------------------------------------------------------------===//
2233 // StdCall calling convention seems to be standard for many Windows' API
2234 // routines and around. It differs from C calling convention just a little:
2235 // callee should clean up the stack, not caller. Symbols should be also
2236 // decorated in some fancy way :) It doesn't support any vector arguments.
2237 // For info on fast calling convention see Fast Calling Convention (tail call)
2238 // implementation LowerX86_32FastCCCallTo.
2240 /// CallIsStructReturn - Determines whether a call uses struct return
2242 enum StructReturnType {
2247 static StructReturnType
2248 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2250 return NotStructReturn;
2252 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2253 if (!Flags.isSRet())
2254 return NotStructReturn;
2255 if (Flags.isInReg())
2256 return RegStructReturn;
2257 return StackStructReturn;
2260 /// Determines whether a function uses struct return semantics.
2261 static StructReturnType
2262 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2264 return NotStructReturn;
2266 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2267 if (!Flags.isSRet())
2268 return NotStructReturn;
2269 if (Flags.isInReg())
2270 return RegStructReturn;
2271 return StackStructReturn;
2274 /// Make a copy of an aggregate at address specified by "Src" to address
2275 /// "Dst" with size and alignment information specified by the specific
2276 /// parameter attribute. The copy will be passed as a byval function parameter.
2278 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2279 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2281 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2283 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2284 /*isVolatile*/false, /*AlwaysInline=*/true,
2285 MachinePointerInfo(), MachinePointerInfo());
2288 /// Return true if the calling convention is one that
2289 /// supports tail call optimization.
2290 static bool IsTailCallConvention(CallingConv::ID CC) {
2291 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2292 CC == CallingConv::HiPE);
2295 /// \brief Return true if the calling convention is a C calling convention.
2296 static bool IsCCallConvention(CallingConv::ID CC) {
2297 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2298 CC == CallingConv::X86_64_SysV);
2301 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2302 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2306 CallingConv::ID CalleeCC = CS.getCallingConv();
2307 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2313 /// Return true if the function is being made into
2314 /// a tailcall target by changing its ABI.
2315 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2316 bool GuaranteedTailCallOpt) {
2317 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2321 X86TargetLowering::LowerMemArgument(SDValue Chain,
2322 CallingConv::ID CallConv,
2323 const SmallVectorImpl<ISD::InputArg> &Ins,
2324 SDLoc dl, SelectionDAG &DAG,
2325 const CCValAssign &VA,
2326 MachineFrameInfo *MFI,
2328 // Create the nodes corresponding to a load from this parameter slot.
2329 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2330 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2331 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2332 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2335 // If value is passed by pointer we have address passed instead of the value
2337 if (VA.getLocInfo() == CCValAssign::Indirect)
2338 ValVT = VA.getLocVT();
2340 ValVT = VA.getValVT();
2342 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2343 // changed with more analysis.
2344 // In case of tail call optimization mark all arguments mutable. Since they
2345 // could be overwritten by lowering of arguments in case of a tail call.
2346 if (Flags.isByVal()) {
2347 unsigned Bytes = Flags.getByValSize();
2348 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2349 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2350 return DAG.getFrameIndex(FI, getPointerTy());
2352 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2353 VA.getLocMemOffset(), isImmutable);
2354 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2355 return DAG.getLoad(ValVT, dl, Chain, FIN,
2356 MachinePointerInfo::getFixedStack(FI),
2357 false, false, false, 0);
2361 // FIXME: Get this from tablegen.
2362 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2366 if (Subtarget->isCallingConvWin64(CallConv)) {
2367 static const MCPhysReg GPR64ArgRegsWin64[] = {
2368 X86::RCX, X86::RDX, X86::R8, X86::R9
2370 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2373 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2374 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2376 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2379 // FIXME: Get this from tablegen.
2380 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2381 CallingConv::ID CallConv,
2382 const X86Subtarget *Subtarget) {
2383 assert(Subtarget->is64Bit());
2384 if (Subtarget->isCallingConvWin64(CallConv)) {
2385 // The XMM registers which might contain var arg parameters are shadowed
2386 // in their paired GPR. So we only need to save the GPR to their home
2388 // TODO: __vectorcall will change this.
2392 const Function *Fn = MF.getFunction();
2393 bool NoImplicitFloatOps = Fn->getAttributes().
2394 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2395 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2398 !Subtarget->hasSSE1())
2399 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2403 static const MCPhysReg XMMArgRegs64Bit[] = {
2404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2405 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2407 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2411 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2412 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector())
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 // The x86-64 ABIs require that for returning structs by value we copy
2526 // the sret argument into %rax/%eax (depending on ABI) for the return.
2527 // Win32 requires us to put the sret argument to %eax as well.
2528 // Save the argument into a virtual register so that we can access it
2529 // from the return points.
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2544 unsigned StackSize = CCInfo.getNextStackOffset();
2545 // Align stack specially for tail calls.
2546 if (FuncIsMadeTailCallSafe(CallConv,
2547 MF.getTarget().Options.GuaranteedTailCallOpt))
2548 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2550 // If the function takes variable number of arguments, make a frame index for
2551 // the start of the first vararg value... for expansion of llvm.va_start. We
2552 // can skip this if there are no va_start calls.
2553 if (MFI->hasVAStart() &&
2554 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2555 CallConv != CallingConv::X86_ThisCall))) {
2556 FuncInfo->setVarArgsFrameIndex(
2557 MFI->CreateFixedObject(1, StackSize, true));
2560 // Figure out if XMM registers are in use.
2561 assert(!(MF.getTarget().Options.UseSoftFloat &&
2562 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2563 Attribute::NoImplicitFloat)) &&
2564 "SSE register cannot be used when SSE is disabled!");
2566 // 64-bit calling conventions support varargs and register parameters, so we
2567 // have to do extra work to spill them in the prologue.
2568 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2569 // Find the first unallocated argument registers.
2570 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2571 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2572 unsigned NumIntRegs =
2573 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2574 unsigned NumXMMRegs =
2575 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2576 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2577 "SSE register cannot be used when SSE is disabled!");
2579 // Gather all the live in physical registers.
2580 SmallVector<SDValue, 6> LiveGPRs;
2581 SmallVector<SDValue, 8> LiveXMMRegs;
2583 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2584 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2586 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2588 if (!ArgXMMs.empty()) {
2589 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2590 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2591 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2592 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2593 LiveXMMRegs.push_back(
2594 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2599 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2600 // Get to the caller-allocated home save location. Add 8 to account
2601 // for the return address.
2602 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2603 FuncInfo->setRegSaveFrameIndex(
2604 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2605 // Fixup to set vararg frame on shadow area (4 x i64).
2607 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2609 // For X86-64, if there are vararg parameters that are passed via
2610 // registers, then we must store them to their spots on the stack so
2611 // they may be loaded by deferencing the result of va_next.
2612 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2613 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2614 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2615 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2618 // Store the integer parameter registers.
2619 SmallVector<SDValue, 8> MemOps;
2620 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2622 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2623 for (SDValue Val : LiveGPRs) {
2624 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2625 DAG.getIntPtrConstant(Offset));
2627 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2628 MachinePointerInfo::getFixedStack(
2629 FuncInfo->getRegSaveFrameIndex(), Offset),
2631 MemOps.push_back(Store);
2635 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2636 // Now store the XMM (fp + vector) parameter registers.
2637 SmallVector<SDValue, 12> SaveXMMOps;
2638 SaveXMMOps.push_back(Chain);
2639 SaveXMMOps.push_back(ALVal);
2640 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2641 FuncInfo->getRegSaveFrameIndex()));
2642 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2643 FuncInfo->getVarArgsFPOffset()));
2644 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2646 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2647 MVT::Other, SaveXMMOps));
2650 if (!MemOps.empty())
2651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2654 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2655 // Find the largest legal vector type.
2656 MVT VecVT = MVT::Other;
2657 // FIXME: Only some x86_32 calling conventions support AVX512.
2658 if (Subtarget->hasAVX512() &&
2659 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2660 CallConv == CallingConv::Intel_OCL_BI)))
2661 VecVT = MVT::v16f32;
2662 else if (Subtarget->hasAVX())
2664 else if (Subtarget->hasSSE2())
2667 // We forward some GPRs and some vector types.
2668 SmallVector<MVT, 2> RegParmTypes;
2669 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2670 RegParmTypes.push_back(IntVT);
2671 if (VecVT != MVT::Other)
2672 RegParmTypes.push_back(VecVT);
2674 // Compute the set of forwarded registers. The rest are scratch.
2675 SmallVectorImpl<ForwardedRegister> &Forwards =
2676 FuncInfo->getForwardedMustTailRegParms();
2677 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2679 // Conservatively forward AL on x86_64, since it might be used for varargs.
2680 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2681 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2682 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2685 // Copy all forwards from physical to virtual registers.
2686 for (ForwardedRegister &F : Forwards) {
2687 // FIXME: Can we use a less constrained schedule?
2688 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2689 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2690 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2694 // Some CCs need callee pop.
2695 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2696 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2697 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2699 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2700 // If this is an sret function, the return should pop the hidden pointer.
2701 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2702 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2703 argsAreStructReturn(Ins) == StackStructReturn)
2704 FuncInfo->setBytesToPopOnReturn(4);
2708 // RegSaveFrameIndex is X86-64 only.
2709 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2710 if (CallConv == CallingConv::X86_FastCall ||
2711 CallConv == CallingConv::X86_ThisCall)
2712 // fastcc functions can't have varargs.
2713 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2716 FuncInfo->setArgumentStackSize(StackSize);
2722 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2723 SDValue StackPtr, SDValue Arg,
2724 SDLoc dl, SelectionDAG &DAG,
2725 const CCValAssign &VA,
2726 ISD::ArgFlagsTy Flags) const {
2727 unsigned LocMemOffset = VA.getLocMemOffset();
2728 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2729 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2730 if (Flags.isByVal())
2731 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2733 return DAG.getStore(Chain, dl, Arg, PtrOff,
2734 MachinePointerInfo::getStack(LocMemOffset),
2738 /// Emit a load of return address if tail call
2739 /// optimization is performed and it is required.
2741 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2742 SDValue &OutRetAddr, SDValue Chain,
2743 bool IsTailCall, bool Is64Bit,
2744 int FPDiff, SDLoc dl) const {
2745 // Adjust the Return address stack slot.
2746 EVT VT = getPointerTy();
2747 OutRetAddr = getReturnAddressFrameIndex(DAG);
2749 // Load the "old" Return address.
2750 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2751 false, false, false, 0);
2752 return SDValue(OutRetAddr.getNode(), 1);
2755 /// Emit a store of the return address if tail call
2756 /// optimization is performed and it is required (FPDiff!=0).
2757 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2758 SDValue Chain, SDValue RetAddrFrIdx,
2759 EVT PtrVT, unsigned SlotSize,
2760 int FPDiff, SDLoc dl) {
2761 // Store the return address to the appropriate stack slot.
2762 if (!FPDiff) return Chain;
2763 // Calculate the new stack slot for the return address.
2764 int NewReturnAddrFI =
2765 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2767 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2768 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2769 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2775 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2776 SmallVectorImpl<SDValue> &InVals) const {
2777 SelectionDAG &DAG = CLI.DAG;
2779 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2780 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2781 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2782 SDValue Chain = CLI.Chain;
2783 SDValue Callee = CLI.Callee;
2784 CallingConv::ID CallConv = CLI.CallConv;
2785 bool &isTailCall = CLI.IsTailCall;
2786 bool isVarArg = CLI.IsVarArg;
2788 MachineFunction &MF = DAG.getMachineFunction();
2789 bool Is64Bit = Subtarget->is64Bit();
2790 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2791 StructReturnType SR = callIsStructReturn(Outs);
2792 bool IsSibcall = false;
2793 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2795 if (MF.getTarget().Options.DisableTailCalls)
2798 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2800 // Force this to be a tail call. The verifier rules are enough to ensure
2801 // that we can lower this successfully without moving the return address
2804 } else if (isTailCall) {
2805 // Check if it's really possible to do a tail call.
2806 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2807 isVarArg, SR != NotStructReturn,
2808 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2809 Outs, OutVals, Ins, DAG);
2811 // Sibcalls are automatically detected tailcalls which do not require
2813 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2820 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2821 "Var args not supported with calling convention fastcc, ghc or hipe");
2823 // Analyze operands of the call, assigning locations to each operand.
2824 SmallVector<CCValAssign, 16> ArgLocs;
2825 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2827 // Allocate shadow area for Win64
2829 CCInfo.AllocateStack(32, 8);
2831 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2833 // Get a count of how many bytes are to be pushed on the stack.
2834 unsigned NumBytes = CCInfo.getNextStackOffset();
2836 // This is a sibcall. The memory operands are available in caller's
2837 // own caller's stack.
2839 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2840 IsTailCallConvention(CallConv))
2841 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2844 if (isTailCall && !IsSibcall && !IsMustTail) {
2845 // Lower arguments at fp - stackoffset + fpdiff.
2846 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2848 FPDiff = NumBytesCallerPushed - NumBytes;
2850 // Set the delta of movement of the returnaddr stackslot.
2851 // But only set if delta is greater than previous delta.
2852 if (FPDiff < X86Info->getTCReturnAddrDelta())
2853 X86Info->setTCReturnAddrDelta(FPDiff);
2856 unsigned NumBytesToPush = NumBytes;
2857 unsigned NumBytesToPop = NumBytes;
2859 // If we have an inalloca argument, all stack space has already been allocated
2860 // for us and be right at the top of the stack. We don't support multiple
2861 // arguments passed in memory when using inalloca.
2862 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2864 if (!ArgLocs.back().isMemLoc())
2865 report_fatal_error("cannot use inalloca attribute on a register "
2867 if (ArgLocs.back().getLocMemOffset() != 0)
2868 report_fatal_error("any parameter with the inalloca attribute must be "
2869 "the only memory argument");
2873 Chain = DAG.getCALLSEQ_START(
2874 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2876 SDValue RetAddrFrIdx;
2877 // Load return address for tail calls.
2878 if (isTailCall && FPDiff)
2879 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2880 Is64Bit, FPDiff, dl);
2882 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2883 SmallVector<SDValue, 8> MemOpChains;
2886 // Walk the register/memloc assignments, inserting copies/loads. In the case
2887 // of tail call optimization arguments are handle later.
2888 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2889 DAG.getSubtarget().getRegisterInfo());
2890 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2891 // Skip inalloca arguments, they have already been written.
2892 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2893 if (Flags.isInAlloca())
2896 CCValAssign &VA = ArgLocs[i];
2897 EVT RegVT = VA.getLocVT();
2898 SDValue Arg = OutVals[i];
2899 bool isByVal = Flags.isByVal();
2901 // Promote the value if needed.
2902 switch (VA.getLocInfo()) {
2903 default: llvm_unreachable("Unknown loc info!");
2904 case CCValAssign::Full: break;
2905 case CCValAssign::SExt:
2906 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2908 case CCValAssign::ZExt:
2909 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2911 case CCValAssign::AExt:
2912 if (RegVT.is128BitVector()) {
2913 // Special case: passing MMX values in XMM registers.
2914 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2915 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2916 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2918 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2920 case CCValAssign::BCvt:
2921 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2923 case CCValAssign::Indirect: {
2924 // Store the argument.
2925 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2926 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2927 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2928 MachinePointerInfo::getFixedStack(FI),
2935 if (VA.isRegLoc()) {
2936 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2937 if (isVarArg && IsWin64) {
2938 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2939 // shadow reg if callee is a varargs function.
2940 unsigned ShadowReg = 0;
2941 switch (VA.getLocReg()) {
2942 case X86::XMM0: ShadowReg = X86::RCX; break;
2943 case X86::XMM1: ShadowReg = X86::RDX; break;
2944 case X86::XMM2: ShadowReg = X86::R8; break;
2945 case X86::XMM3: ShadowReg = X86::R9; break;
2948 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2950 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2951 assert(VA.isMemLoc());
2952 if (!StackPtr.getNode())
2953 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2955 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2956 dl, DAG, VA, Flags));
2960 if (!MemOpChains.empty())
2961 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2963 if (Subtarget->isPICStyleGOT()) {
2964 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2968 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2970 // If we are tail calling and generating PIC/GOT style code load the
2971 // address of the callee into ECX. The value in ecx is used as target of
2972 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2973 // for tail calls on PIC/GOT architectures. Normally we would just put the
2974 // address of GOT into ebx and then call target@PLT. But for tail calls
2975 // ebx would be restored (since ebx is callee saved) before jumping to the
2978 // Note: The actual moving to ECX is done further down.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2981 !G->getGlobal()->hasProtectedVisibility())
2982 Callee = LowerGlobalAddress(Callee, DAG);
2983 else if (isa<ExternalSymbolSDNode>(Callee))
2984 Callee = LowerExternalSymbol(Callee, DAG);
2988 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2989 // From AMD64 ABI document:
2990 // For calls that may call functions that use varargs or stdargs
2991 // (prototype-less calls or calls to functions containing ellipsis (...) in
2992 // the declaration) %al is used as hidden argument to specify the number
2993 // of SSE registers used. The contents of %al do not need to match exactly
2994 // the number of registers, but must be an ubound on the number of SSE
2995 // registers used and is in the range 0 - 8 inclusive.
2997 // Count the number of XMM registers allocated.
2998 static const MCPhysReg XMMArgRegs[] = {
2999 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3000 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3002 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
3003 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3004 && "SSE registers cannot be used when SSE is disabled");
3006 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3007 DAG.getConstant(NumXMMRegs, MVT::i8)));
3010 if (isVarArg && IsMustTail) {
3011 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3012 for (const auto &F : Forwards) {
3013 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3014 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3018 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3019 // don't need this because the eligibility check rejects calls that require
3020 // shuffling arguments passed in memory.
3021 if (!IsSibcall && isTailCall) {
3022 // Force all the incoming stack arguments to be loaded from the stack
3023 // before any new outgoing arguments are stored to the stack, because the
3024 // outgoing stack slots may alias the incoming argument stack slots, and
3025 // the alias isn't otherwise explicit. This is slightly more conservative
3026 // than necessary, because it means that each store effectively depends
3027 // on every argument instead of just those arguments it would clobber.
3028 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3030 SmallVector<SDValue, 8> MemOpChains2;
3033 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3034 CCValAssign &VA = ArgLocs[i];
3037 assert(VA.isMemLoc());
3038 SDValue Arg = OutVals[i];
3039 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3040 // Skip inalloca arguments. They don't require any work.
3041 if (Flags.isInAlloca())
3043 // Create frame index.
3044 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3045 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3046 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3047 FIN = DAG.getFrameIndex(FI, getPointerTy());
3049 if (Flags.isByVal()) {
3050 // Copy relative to framepointer.
3051 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3052 if (!StackPtr.getNode())
3053 StackPtr = DAG.getCopyFromReg(Chain, dl,
3054 RegInfo->getStackRegister(),
3056 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3058 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3062 // Store relative to framepointer.
3063 MemOpChains2.push_back(
3064 DAG.getStore(ArgChain, dl, Arg, FIN,
3065 MachinePointerInfo::getFixedStack(FI),
3070 if (!MemOpChains2.empty())
3071 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3073 // Store the return address to the appropriate stack slot.
3074 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3075 getPointerTy(), RegInfo->getSlotSize(),
3079 // Build a sequence of copy-to-reg nodes chained together with token chain
3080 // and flag operands which copy the outgoing args into registers.
3082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3083 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3084 RegsToPass[i].second, InFlag);
3085 InFlag = Chain.getValue(1);
3088 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3089 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3090 // In the 64-bit large code model, we have to make all calls
3091 // through a register, since the call instruction's 32-bit
3092 // pc-relative offset may not be large enough to hold the whole
3094 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3095 // If the callee is a GlobalAddress node (quite common, every direct call
3096 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3098 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3100 // We should use extra load for direct calls to dllimported functions in
3102 const GlobalValue *GV = G->getGlobal();
3103 if (!GV->hasDLLImportStorageClass()) {
3104 unsigned char OpFlags = 0;
3105 bool ExtraLoad = false;
3106 unsigned WrapperKind = ISD::DELETED_NODE;
3108 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3109 // external symbols most go through the PLT in PIC mode. If the symbol
3110 // has hidden or protected visibility, or if it is static or local, then
3111 // we don't need to use the PLT - we can directly call it.
3112 if (Subtarget->isTargetELF() &&
3113 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3114 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3115 OpFlags = X86II::MO_PLT;
3116 } else if (Subtarget->isPICStyleStubAny() &&
3117 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3124 } else if (Subtarget->isPICStyleRIPRel() &&
3125 isa<Function>(GV) &&
3126 cast<Function>(GV)->getAttributes().
3127 hasAttribute(AttributeSet::FunctionIndex,
3128 Attribute::NonLazyBind)) {
3129 // If the function is marked as non-lazy, generate an indirect call
3130 // which loads from the GOT directly. This avoids runtime overhead
3131 // at the cost of eager binding (and one extra byte of encoding).
3132 OpFlags = X86II::MO_GOTPCREL;
3133 WrapperKind = X86ISD::WrapperRIP;
3137 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3138 G->getOffset(), OpFlags);
3140 // Add a wrapper if needed.
3141 if (WrapperKind != ISD::DELETED_NODE)
3142 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3143 // Add extra indirection if needed.
3145 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3146 MachinePointerInfo::getGOT(),
3147 false, false, false, 0);
3149 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3150 unsigned char OpFlags = 0;
3152 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3153 // external symbols should go through the PLT.
3154 if (Subtarget->isTargetELF() &&
3155 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3156 OpFlags = X86II::MO_PLT;
3157 } else if (Subtarget->isPICStyleStubAny() &&
3158 (!Subtarget->getTargetTriple().isMacOSX() ||
3159 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3160 // PC-relative references to external symbols should go through $stub,
3161 // unless we're building with the leopard linker or later, which
3162 // automatically synthesizes these stubs.
3163 OpFlags = X86II::MO_DARWIN_STUB;
3166 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3168 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3169 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3170 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3173 // Returns a chain & a flag for retval copy to use.
3174 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3175 SmallVector<SDValue, 8> Ops;
3177 if (!IsSibcall && isTailCall) {
3178 Chain = DAG.getCALLSEQ_END(Chain,
3179 DAG.getIntPtrConstant(NumBytesToPop, true),
3180 DAG.getIntPtrConstant(0, true), InFlag, dl);
3181 InFlag = Chain.getValue(1);
3184 Ops.push_back(Chain);
3185 Ops.push_back(Callee);
3188 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3190 // Add argument registers to the end of the list so that they are known live
3192 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3193 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3194 RegsToPass[i].second.getValueType()));
3196 // Add a register mask operand representing the call-preserved registers.
3197 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3198 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3199 assert(Mask && "Missing call preserved mask for calling convention");
3200 Ops.push_back(DAG.getRegisterMask(Mask));
3202 if (InFlag.getNode())
3203 Ops.push_back(InFlag);
3207 //// If this is the first return lowered for this function, add the regs
3208 //// to the liveout set for the function.
3209 // This isn't right, although it's probably harmless on x86; liveouts
3210 // should be computed from returns not tail calls. Consider a void
3211 // function making a tail call to a function returning int.
3212 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3215 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3216 InFlag = Chain.getValue(1);
3218 // Create the CALLSEQ_END node.
3219 unsigned NumBytesForCalleeToPop;
3220 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3221 DAG.getTarget().Options.GuaranteedTailCallOpt))
3222 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3223 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3224 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3225 SR == StackStructReturn)
3226 // If this is a call to a struct-return function, the callee
3227 // pops the hidden struct pointer, so we have to push it back.
3228 // This is common for Darwin/X86, Linux & Mingw32 targets.
3229 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3230 NumBytesForCalleeToPop = 4;
3232 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3234 // Returns a flag for retval copy to use.
3236 Chain = DAG.getCALLSEQ_END(Chain,
3237 DAG.getIntPtrConstant(NumBytesToPop, true),
3238 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3241 InFlag = Chain.getValue(1);
3244 // Handle result values, copying them out of physregs into vregs that we
3246 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3247 Ins, dl, DAG, InVals);
3250 //===----------------------------------------------------------------------===//
3251 // Fast Calling Convention (tail call) implementation
3252 //===----------------------------------------------------------------------===//
3254 // Like std call, callee cleans arguments, convention except that ECX is
3255 // reserved for storing the tail called function address. Only 2 registers are
3256 // free for argument passing (inreg). Tail call optimization is performed
3258 // * tailcallopt is enabled
3259 // * caller/callee are fastcc
3260 // On X86_64 architecture with GOT-style position independent code only local
3261 // (within module) calls are supported at the moment.
3262 // To keep the stack aligned according to platform abi the function
3263 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3264 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3265 // If a tail called function callee has more arguments than the caller the
3266 // caller needs to make sure that there is room to move the RETADDR to. This is
3267 // achieved by reserving an area the size of the argument delta right after the
3268 // original RETADDR, but before the saved framepointer or the spilled registers
3269 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3281 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3282 /// for a 16 byte align requirement.
3284 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3285 SelectionDAG& DAG) const {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 const TargetMachine &TM = MF.getTarget();
3288 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3289 TM.getSubtargetImpl()->getRegisterInfo());
3290 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3291 unsigned StackAlignment = TFI.getStackAlignment();
3292 uint64_t AlignMask = StackAlignment - 1;
3293 int64_t Offset = StackSize;
3294 unsigned SlotSize = RegInfo->getSlotSize();
3295 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3296 // Number smaller than 12 so just add the difference.
3297 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3299 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3300 Offset = ((~AlignMask) & Offset) + StackAlignment +
3301 (StackAlignment-SlotSize);
3306 /// MatchingStackOffset - Return true if the given stack call argument is
3307 /// already available in the same position (relatively) of the caller's
3308 /// incoming argument stack.
3310 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3311 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3312 const X86InstrInfo *TII) {
3313 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3315 if (Arg.getOpcode() == ISD::CopyFromReg) {
3316 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3317 if (!TargetRegisterInfo::isVirtualRegister(VR))
3319 MachineInstr *Def = MRI->getVRegDef(VR);
3322 if (!Flags.isByVal()) {
3323 if (!TII->isLoadFromStackSlot(Def, FI))
3326 unsigned Opcode = Def->getOpcode();
3327 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3328 Def->getOperand(1).isFI()) {
3329 FI = Def->getOperand(1).getIndex();
3330 Bytes = Flags.getByValSize();
3334 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3335 if (Flags.isByVal())
3336 // ByVal argument is passed in as a pointer but it's now being
3337 // dereferenced. e.g.
3338 // define @foo(%struct.X* %A) {
3339 // tail call @bar(%struct.X* byval %A)
3342 SDValue Ptr = Ld->getBasePtr();
3343 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3346 FI = FINode->getIndex();
3347 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3348 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3349 FI = FINode->getIndex();
3350 Bytes = Flags.getByValSize();
3354 assert(FI != INT_MAX);
3355 if (!MFI->isFixedObjectIndex(FI))
3357 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3361 /// for tail call optimization. Targets which want to do tail call
3362 /// optimization should implement this function.
3364 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3365 CallingConv::ID CalleeCC,
3367 bool isCalleeStructRet,
3368 bool isCallerStructRet,
3370 const SmallVectorImpl<ISD::OutputArg> &Outs,
3371 const SmallVectorImpl<SDValue> &OutVals,
3372 const SmallVectorImpl<ISD::InputArg> &Ins,
3373 SelectionDAG &DAG) const {
3374 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3377 // If -tailcallopt is specified, make fastcc functions tail-callable.
3378 const MachineFunction &MF = DAG.getMachineFunction();
3379 const Function *CallerF = MF.getFunction();
3381 // If the function return type is x86_fp80 and the callee return type is not,
3382 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3383 // perform a tailcall optimization here.
3384 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3387 CallingConv::ID CallerCC = CallerF->getCallingConv();
3388 bool CCMatch = CallerCC == CalleeCC;
3389 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3390 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3392 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3393 if (IsTailCallConvention(CalleeCC) && CCMatch)
3398 // Look for obvious safe cases to perform tail call optimization that do not
3399 // require ABI changes. This is what gcc calls sibcall.
3401 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3402 // emit a special epilogue.
3403 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3404 DAG.getSubtarget().getRegisterInfo());
3405 if (RegInfo->needsStackRealignment(MF))
3408 // Also avoid sibcall optimization if either caller or callee uses struct
3409 // return semantics.
3410 if (isCalleeStructRet || isCallerStructRet)
3413 // An stdcall/thiscall caller is expected to clean up its arguments; the
3414 // callee isn't going to do that.
3415 // FIXME: this is more restrictive than needed. We could produce a tailcall
3416 // when the stack adjustment matches. For example, with a thiscall that takes
3417 // only one argument.
3418 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3419 CallerCC == CallingConv::X86_ThisCall))
3422 // Do not sibcall optimize vararg calls unless all arguments are passed via
3424 if (isVarArg && !Outs.empty()) {
3426 // Optimizing for varargs on Win64 is unlikely to be safe without
3427 // additional testing.
3428 if (IsCalleeWin64 || IsCallerWin64)
3431 SmallVector<CCValAssign, 16> ArgLocs;
3432 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3435 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3436 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3437 if (!ArgLocs[i].isRegLoc())
3441 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3442 // stack. Therefore, if it's not used by the call it is not safe to optimize
3443 // this into a sibcall.
3444 bool Unused = false;
3445 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3452 SmallVector<CCValAssign, 16> RVLocs;
3453 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3455 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3456 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3457 CCValAssign &VA = RVLocs[i];
3458 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3463 // If the calling conventions do not match, then we'd better make sure the
3464 // results are returned in the same way as what the caller expects.
3466 SmallVector<CCValAssign, 16> RVLocs1;
3467 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3469 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3471 SmallVector<CCValAssign, 16> RVLocs2;
3472 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3474 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3476 if (RVLocs1.size() != RVLocs2.size())
3478 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3479 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3481 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3483 if (RVLocs1[i].isRegLoc()) {
3484 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3487 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3493 // If the callee takes no arguments then go on to check the results of the
3495 if (!Outs.empty()) {
3496 // Check if stack adjustment is needed. For now, do not do this if any
3497 // argument is passed on the stack.
3498 SmallVector<CCValAssign, 16> ArgLocs;
3499 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3502 // Allocate shadow area for Win64
3504 CCInfo.AllocateStack(32, 8);
3506 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3507 if (CCInfo.getNextStackOffset()) {
3508 MachineFunction &MF = DAG.getMachineFunction();
3509 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3512 // Check if the arguments are already laid out in the right way as
3513 // the caller's fixed stack objects.
3514 MachineFrameInfo *MFI = MF.getFrameInfo();
3515 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3516 const X86InstrInfo *TII =
3517 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3518 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3519 CCValAssign &VA = ArgLocs[i];
3520 SDValue Arg = OutVals[i];
3521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3522 if (VA.getLocInfo() == CCValAssign::Indirect)
3524 if (!VA.isRegLoc()) {
3525 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3532 // If the tailcall address may be in a register, then make sure it's
3533 // possible to register allocate for it. In 32-bit, the call address can
3534 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3535 // callee-saved registers are restored. These happen to be the same
3536 // registers used to pass 'inreg' arguments so watch out for those.
3537 if (!Subtarget->is64Bit() &&
3538 ((!isa<GlobalAddressSDNode>(Callee) &&
3539 !isa<ExternalSymbolSDNode>(Callee)) ||
3540 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3541 unsigned NumInRegs = 0;
3542 // In PIC we need an extra register to formulate the address computation
3544 unsigned MaxInRegs =
3545 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3547 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3548 CCValAssign &VA = ArgLocs[i];
3551 unsigned Reg = VA.getLocReg();
3554 case X86::EAX: case X86::EDX: case X86::ECX:
3555 if (++NumInRegs == MaxInRegs)
3567 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3568 const TargetLibraryInfo *libInfo) const {
3569 return X86::createFastISel(funcInfo, libInfo);
3572 //===----------------------------------------------------------------------===//
3573 // Other Lowering Hooks
3574 //===----------------------------------------------------------------------===//
3576 static bool MayFoldLoad(SDValue Op) {
3577 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3580 static bool MayFoldIntoStore(SDValue Op) {
3581 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3584 static bool isTargetShuffle(unsigned Opcode) {
3586 default: return false;
3587 case X86ISD::BLENDI:
3588 case X86ISD::PSHUFB:
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3593 case X86ISD::PALIGNR:
3594 case X86ISD::MOVLHPS:
3595 case X86ISD::MOVLHPD:
3596 case X86ISD::MOVHLPS:
3597 case X86ISD::MOVLPS:
3598 case X86ISD::MOVLPD:
3599 case X86ISD::MOVSHDUP:
3600 case X86ISD::MOVSLDUP:
3601 case X86ISD::MOVDDUP:
3604 case X86ISD::UNPCKL:
3605 case X86ISD::UNPCKH:
3606 case X86ISD::VPERMILPI:
3607 case X86ISD::VPERM2X128:
3608 case X86ISD::VPERMI:
3613 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3614 SDValue V1, SelectionDAG &DAG) {
3616 default: llvm_unreachable("Unknown x86 shuffle node");
3617 case X86ISD::MOVSHDUP:
3618 case X86ISD::MOVSLDUP:
3619 case X86ISD::MOVDDUP:
3620 return DAG.getNode(Opc, dl, VT, V1);
3624 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3625 SDValue V1, unsigned TargetMask,
3626 SelectionDAG &DAG) {
3628 default: llvm_unreachable("Unknown x86 shuffle node");
3629 case X86ISD::PSHUFD:
3630 case X86ISD::PSHUFHW:
3631 case X86ISD::PSHUFLW:
3632 case X86ISD::VPERMILPI:
3633 case X86ISD::VPERMI:
3634 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3638 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3639 SDValue V1, SDValue V2, unsigned TargetMask,
3640 SelectionDAG &DAG) {
3642 default: llvm_unreachable("Unknown x86 shuffle node");
3643 case X86ISD::PALIGNR:
3644 case X86ISD::VALIGN:
3646 case X86ISD::VPERM2X128:
3647 return DAG.getNode(Opc, dl, VT, V1, V2,
3648 DAG.getConstant(TargetMask, MVT::i8));
3652 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3653 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3655 default: llvm_unreachable("Unknown x86 shuffle node");
3656 case X86ISD::MOVLHPS:
3657 case X86ISD::MOVLHPD:
3658 case X86ISD::MOVHLPS:
3659 case X86ISD::MOVLPS:
3660 case X86ISD::MOVLPD:
3663 case X86ISD::UNPCKL:
3664 case X86ISD::UNPCKH:
3665 return DAG.getNode(Opc, dl, VT, V1, V2);
3669 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3670 MachineFunction &MF = DAG.getMachineFunction();
3671 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3672 DAG.getSubtarget().getRegisterInfo());
3673 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3674 int ReturnAddrIndex = FuncInfo->getRAIndex();
3676 if (ReturnAddrIndex == 0) {
3677 // Set up a frame object for the return address.
3678 unsigned SlotSize = RegInfo->getSlotSize();
3679 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3682 FuncInfo->setRAIndex(ReturnAddrIndex);
3685 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3688 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3689 bool hasSymbolicDisplacement) {
3690 // Offset should fit into 32 bit immediate field.
3691 if (!isInt<32>(Offset))
3694 // If we don't have a symbolic displacement - we don't have any extra
3696 if (!hasSymbolicDisplacement)
3699 // FIXME: Some tweaks might be needed for medium code model.
3700 if (M != CodeModel::Small && M != CodeModel::Kernel)
3703 // For small code model we assume that latest object is 16MB before end of 31
3704 // bits boundary. We may also accept pretty large negative constants knowing
3705 // that all objects are in the positive half of address space.
3706 if (M == CodeModel::Small && Offset < 16*1024*1024)
3709 // For kernel code model we know that all object resist in the negative half
3710 // of 32bits address space. We may not accept negative offsets, since they may
3711 // be just off and we may accept pretty large positive ones.
3712 if (M == CodeModel::Kernel && Offset >= 0)
3718 /// isCalleePop - Determines whether the callee is required to pop its
3719 /// own arguments. Callee pop is necessary to support tail calls.
3720 bool X86::isCalleePop(CallingConv::ID CallingConv,
3721 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3722 switch (CallingConv) {
3725 case CallingConv::X86_StdCall:
3726 case CallingConv::X86_FastCall:
3727 case CallingConv::X86_ThisCall:
3729 case CallingConv::Fast:
3730 case CallingConv::GHC:
3731 case CallingConv::HiPE:
3738 /// \brief Return true if the condition is an unsigned comparison operation.
3739 static bool isX86CCUnsigned(unsigned X86CC) {
3741 default: llvm_unreachable("Invalid integer condition!");
3742 case X86::COND_E: return true;
3743 case X86::COND_G: return false;
3744 case X86::COND_GE: return false;
3745 case X86::COND_L: return false;
3746 case X86::COND_LE: return false;
3747 case X86::COND_NE: return true;
3748 case X86::COND_B: return true;
3749 case X86::COND_A: return true;
3750 case X86::COND_BE: return true;
3751 case X86::COND_AE: return true;
3753 llvm_unreachable("covered switch fell through?!");
3756 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3757 /// specific condition code, returning the condition code and the LHS/RHS of the
3758 /// comparison to make.
3759 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3760 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3762 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3763 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3764 // X > -1 -> X == 0, jump !sign.
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_NS;
3768 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3769 // X < 0 -> X == 0, jump on sign.
3772 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3774 RHS = DAG.getConstant(0, RHS.getValueType());
3775 return X86::COND_LE;
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Invalid integer condition!");
3781 case ISD::SETEQ: return X86::COND_E;
3782 case ISD::SETGT: return X86::COND_G;
3783 case ISD::SETGE: return X86::COND_GE;
3784 case ISD::SETLT: return X86::COND_L;
3785 case ISD::SETLE: return X86::COND_LE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETULT: return X86::COND_B;
3788 case ISD::SETUGT: return X86::COND_A;
3789 case ISD::SETULE: return X86::COND_BE;
3790 case ISD::SETUGE: return X86::COND_AE;
3794 // First determine if it is required or is profitable to flip the operands.
3796 // If LHS is a foldable load, but RHS is not, flip the condition.
3797 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3798 !ISD::isNON_EXTLoad(RHS.getNode())) {
3799 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3800 std::swap(LHS, RHS);
3803 switch (SetCCOpcode) {
3809 std::swap(LHS, RHS);
3813 // On a floating point condition, the flags are set as follows:
3815 // 0 | 0 | 0 | X > Y
3816 // 0 | 0 | 1 | X < Y
3817 // 1 | 0 | 0 | X == Y
3818 // 1 | 1 | 1 | unordered
3819 switch (SetCCOpcode) {
3820 default: llvm_unreachable("Condcode should be pre-legalized away");
3822 case ISD::SETEQ: return X86::COND_E;
3823 case ISD::SETOLT: // flipped
3825 case ISD::SETGT: return X86::COND_A;
3826 case ISD::SETOLE: // flipped
3828 case ISD::SETGE: return X86::COND_AE;
3829 case ISD::SETUGT: // flipped
3831 case ISD::SETLT: return X86::COND_B;
3832 case ISD::SETUGE: // flipped
3834 case ISD::SETLE: return X86::COND_BE;
3836 case ISD::SETNE: return X86::COND_NE;
3837 case ISD::SETUO: return X86::COND_P;
3838 case ISD::SETO: return X86::COND_NP;
3840 case ISD::SETUNE: return X86::COND_INVALID;
3844 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3845 /// code. Current x86 isa includes the following FP cmov instructions:
3846 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3847 static bool hasFPCMov(unsigned X86CC) {
3863 /// isFPImmLegal - Returns true if the target can instruction select the
3864 /// specified FP immediate natively. If false, the legalizer will
3865 /// materialize the FP immediate as a load from a constant pool.
3866 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3867 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3868 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3874 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3875 ISD::LoadExtType ExtTy,
3877 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3878 // relocation target a movq or addq instruction: don't let the load shrink.
3879 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3880 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3881 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3882 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3886 /// \brief Returns true if it is beneficial to convert a load of a constant
3887 /// to just the constant itself.
3888 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3890 assert(Ty->isIntegerTy());
3892 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3893 if (BitSize == 0 || BitSize > 64)
3898 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3899 unsigned Index) const {
3900 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3903 return (Index == 0 || Index == ResVT.getVectorNumElements());
3906 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3907 // Speculate cttz only if we can directly use TZCNT.
3908 return Subtarget->hasBMI();
3911 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3912 // Speculate ctlz only if we can directly use LZCNT.
3913 return Subtarget->hasLZCNT();
3916 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3917 /// the specified range (L, H].
3918 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3919 return (Val < 0) || (Val >= Low && Val < Hi);
3922 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3923 /// specified value.
3924 static bool isUndefOrEqual(int Val, int CmpVal) {
3925 return (Val < 0 || Val == CmpVal);
3928 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3929 /// from position Pos and ending in Pos+Size, falls within the specified
3930 /// sequential range (Low, Low+Size]. or is undef.
3931 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3932 unsigned Pos, unsigned Size, int Low) {
3933 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3934 if (!isUndefOrEqual(Mask[i], Low))
3939 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3940 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3941 /// operand - by default will match for first operand.
3942 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3943 bool TestSecondOperand = false) {
3944 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3945 VT != MVT::v2f64 && VT != MVT::v2i64)
3948 unsigned NumElems = VT.getVectorNumElements();
3949 unsigned Lo = TestSecondOperand ? NumElems : 0;
3950 unsigned Hi = Lo + NumElems;
3952 for (unsigned i = 0; i < NumElems; ++i)
3953 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3959 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3960 /// is suitable for input to PSHUFHW.
3961 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3962 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3965 // Lower quadword copied in order or undef.
3966 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3969 // Upper quadword shuffled.
3970 for (unsigned i = 4; i != 8; ++i)
3971 if (!isUndefOrInRange(Mask[i], 4, 8))
3974 if (VT == MVT::v16i16) {
3975 // Lower quadword copied in order or undef.
3976 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3979 // Upper quadword shuffled.
3980 for (unsigned i = 12; i != 16; ++i)
3981 if (!isUndefOrInRange(Mask[i], 12, 16))
3988 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3989 /// is suitable for input to PSHUFLW.
3990 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3991 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3994 // Upper quadword copied in order.
3995 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3998 // Lower quadword shuffled.
3999 for (unsigned i = 0; i != 4; ++i)
4000 if (!isUndefOrInRange(Mask[i], 0, 4))
4003 if (VT == MVT::v16i16) {
4004 // Upper quadword copied in order.
4005 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
4008 // Lower quadword shuffled.
4009 for (unsigned i = 8; i != 12; ++i)
4010 if (!isUndefOrInRange(Mask[i], 8, 12))
4017 /// \brief Return true if the mask specifies a shuffle of elements that is
4018 /// suitable for input to intralane (palignr) or interlane (valign) vector
4020 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4021 unsigned NumElts = VT.getVectorNumElements();
4022 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4023 unsigned NumLaneElts = NumElts/NumLanes;
4025 // Do not handle 64-bit element shuffles with palignr.
4026 if (NumLaneElts == 2)
4029 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4031 for (i = 0; i != NumLaneElts; ++i) {
4036 // Lane is all undef, go to next lane
4037 if (i == NumLaneElts)
4040 int Start = Mask[i+l];
4042 // Make sure its in this lane in one of the sources
4043 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4044 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4047 // If not lane 0, then we must match lane 0
4048 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4051 // Correct second source to be contiguous with first source
4052 if (Start >= (int)NumElts)
4053 Start -= NumElts - NumLaneElts;
4055 // Make sure we're shifting in the right direction.
4056 if (Start <= (int)(i+l))
4061 // Check the rest of the elements to see if they are consecutive.
4062 for (++i; i != NumLaneElts; ++i) {
4063 int Idx = Mask[i+l];
4065 // Make sure its in this lane
4066 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4067 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4070 // If not lane 0, then we must match lane 0
4071 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4074 if (Idx >= (int)NumElts)
4075 Idx -= NumElts - NumLaneElts;
4077 if (!isUndefOrEqual(Idx, Start+i))
4086 /// \brief Return true if the node specifies a shuffle of elements that is
4087 /// suitable for input to PALIGNR.
4088 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4089 const X86Subtarget *Subtarget) {
4090 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4091 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4092 VT.is512BitVector())
4093 // FIXME: Add AVX512BW.
4096 return isAlignrMask(Mask, VT, false);
4099 /// \brief Return true if the node specifies a shuffle of elements that is
4100 /// suitable for input to VALIGN.
4101 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4102 const X86Subtarget *Subtarget) {
4103 // FIXME: Add AVX512VL.
4104 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4106 return isAlignrMask(Mask, VT, true);
4109 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4110 /// the two vector operands have swapped position.
4111 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4112 unsigned NumElems) {
4113 for (unsigned i = 0; i != NumElems; ++i) {
4117 else if (idx < (int)NumElems)
4118 Mask[i] = idx + NumElems;
4120 Mask[i] = idx - NumElems;
4124 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4125 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4126 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4127 /// reverse of what x86 shuffles want.
4128 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4130 unsigned NumElems = VT.getVectorNumElements();
4131 unsigned NumLanes = VT.getSizeInBits()/128;
4132 unsigned NumLaneElems = NumElems/NumLanes;
4134 if (NumLaneElems != 2 && NumLaneElems != 4)
4137 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4138 bool symetricMaskRequired =
4139 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4141 // VSHUFPSY divides the resulting vector into 4 chunks.
4142 // The sources are also splitted into 4 chunks, and each destination
4143 // chunk must come from a different source chunk.
4145 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4146 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4148 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4149 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4151 // VSHUFPDY divides the resulting vector into 4 chunks.
4152 // The sources are also splitted into 4 chunks, and each destination
4153 // chunk must come from a different source chunk.
4155 // SRC1 => X3 X2 X1 X0
4156 // SRC2 => Y3 Y2 Y1 Y0
4158 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4160 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4161 unsigned HalfLaneElems = NumLaneElems/2;
4162 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4163 for (unsigned i = 0; i != NumLaneElems; ++i) {
4164 int Idx = Mask[i+l];
4165 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4166 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4168 // For VSHUFPSY, the mask of the second half must be the same as the
4169 // first but with the appropriate offsets. This works in the same way as
4170 // VPERMILPS works with masks.
4171 if (!symetricMaskRequired || Idx < 0)
4173 if (MaskVal[i] < 0) {
4174 MaskVal[i] = Idx - l;
4177 if ((signed)(Idx - l) != MaskVal[i])
4185 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4186 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4187 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4188 if (!VT.is128BitVector())
4191 unsigned NumElems = VT.getVectorNumElements();
4196 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4197 return isUndefOrEqual(Mask[0], 6) &&
4198 isUndefOrEqual(Mask[1], 7) &&
4199 isUndefOrEqual(Mask[2], 2) &&
4200 isUndefOrEqual(Mask[3], 3);
4203 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4204 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4206 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4207 if (!VT.is128BitVector())
4210 unsigned NumElems = VT.getVectorNumElements();
4215 return isUndefOrEqual(Mask[0], 2) &&
4216 isUndefOrEqual(Mask[1], 3) &&
4217 isUndefOrEqual(Mask[2], 2) &&
4218 isUndefOrEqual(Mask[3], 3);
4221 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4222 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4223 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4224 if (!VT.is128BitVector())
4227 unsigned NumElems = VT.getVectorNumElements();
4229 if (NumElems != 2 && NumElems != 4)
4232 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4233 if (!isUndefOrEqual(Mask[i], i + NumElems))
4236 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4237 if (!isUndefOrEqual(Mask[i], i))
4243 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4244 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4245 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4246 if (!VT.is128BitVector())
4249 unsigned NumElems = VT.getVectorNumElements();
4251 if (NumElems != 2 && NumElems != 4)
4254 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4255 if (!isUndefOrEqual(Mask[i], i))
4258 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4259 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4265 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4267 /// i. e: If all but one element come from the same vector.
4268 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4269 // TODO: Deal with AVX's VINSERTPS
4270 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4273 unsigned CorrectPosV1 = 0;
4274 unsigned CorrectPosV2 = 0;
4275 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4276 if (Mask[i] == -1) {
4284 else if (Mask[i] == i + 4)
4288 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4289 // We have 3 elements (undefs count as elements from any vector) from one
4290 // vector, and one from another.
4297 // Some special combinations that can be optimized.
4300 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4301 SelectionDAG &DAG) {
4302 MVT VT = SVOp->getSimpleValueType(0);
4305 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4308 ArrayRef<int> Mask = SVOp->getMask();
4310 // These are the special masks that may be optimized.
4311 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4312 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4313 bool MatchEvenMask = true;
4314 bool MatchOddMask = true;
4315 for (int i=0; i<8; ++i) {
4316 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4317 MatchEvenMask = false;
4318 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4319 MatchOddMask = false;
4322 if (!MatchEvenMask && !MatchOddMask)
4325 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4327 SDValue Op0 = SVOp->getOperand(0);
4328 SDValue Op1 = SVOp->getOperand(1);
4330 if (MatchEvenMask) {
4331 // Shift the second operand right to 32 bits.
4332 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4333 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4335 // Shift the first operand left to 32 bits.
4336 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4337 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4339 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4340 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4343 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4344 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4345 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4346 bool HasInt256, bool V2IsSplat = false) {
4348 assert(VT.getSizeInBits() >= 128 &&
4349 "Unsupported vector type for unpckl");
4351 unsigned NumElts = VT.getVectorNumElements();
4352 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4353 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4356 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4357 "Unsupported vector type for unpckh");
4359 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, NumElts))
4373 if (!isUndefOrEqual(BitI1, j + NumElts))
4382 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4383 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4384 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4385 bool HasInt256, bool V2IsSplat = false) {
4386 assert(VT.getSizeInBits() >= 128 &&
4387 "Unsupported vector type for unpckh");
4389 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4395 "Unsupported vector type for unpckh");
4397 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4398 unsigned NumLanes = VT.getSizeInBits()/128;
4399 unsigned NumLaneElts = NumElts/NumLanes;
4401 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4402 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4403 int BitI = Mask[l+i];
4404 int BitI1 = Mask[l+i+1];
4405 if (!isUndefOrEqual(BitI, j))
4408 if (isUndefOrEqual(BitI1, NumElts))
4411 if (!isUndefOrEqual(BitI1, j+NumElts))
4419 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4420 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4422 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4423 unsigned NumElts = VT.getVectorNumElements();
4424 bool Is256BitVec = VT.is256BitVector();
4426 if (VT.is512BitVector())
4428 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4429 "Unsupported vector type for unpckh");
4431 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4432 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4435 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4436 // FIXME: Need a better way to get rid of this, there's no latency difference
4437 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4438 // the former later. We should also remove the "_undef" special mask.
4439 if (NumElts == 4 && Is256BitVec)
4442 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4443 // independently on 128-bit lanes.
4444 unsigned NumLanes = VT.getSizeInBits()/128;
4445 unsigned NumLaneElts = NumElts/NumLanes;
4447 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4448 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4449 int BitI = Mask[l+i];
4450 int BitI1 = Mask[l+i+1];
4452 if (!isUndefOrEqual(BitI, j))
4454 if (!isUndefOrEqual(BitI1, j))
4462 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4463 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4465 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4466 unsigned NumElts = VT.getVectorNumElements();
4468 if (VT.is512BitVector())
4471 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4472 "Unsupported vector type for unpckh");
4474 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4475 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4478 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4479 // independently on 128-bit lanes.
4480 unsigned NumLanes = VT.getSizeInBits()/128;
4481 unsigned NumLaneElts = NumElts/NumLanes;
4483 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4484 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4485 int BitI = Mask[l+i];
4486 int BitI1 = Mask[l+i+1];
4487 if (!isUndefOrEqual(BitI, j))
4489 if (!isUndefOrEqual(BitI1, j))
4496 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4497 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4498 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4499 if (!VT.is512BitVector())
4502 unsigned NumElts = VT.getVectorNumElements();
4503 unsigned HalfSize = NumElts/2;
4504 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4505 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4510 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4511 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4519 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4520 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4521 /// MOVSD, and MOVD, i.e. setting the lowest element.
4522 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4523 if (VT.getVectorElementType().getSizeInBits() < 32)
4525 if (!VT.is128BitVector())
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (!isUndefOrEqual(Mask[0], NumElts))
4533 for (unsigned i = 1; i != NumElts; ++i)
4534 if (!isUndefOrEqual(Mask[i], i))
4540 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4541 /// as permutations between 128-bit chunks or halves. As an example: this
4543 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4544 /// The first half comes from the second half of V1 and the second half from the
4545 /// the second half of V2.
4546 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4547 if (!HasFp256 || !VT.is256BitVector())
4550 // The shuffle result is divided into half A and half B. In total the two
4551 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4552 // B must come from C, D, E or F.
4553 unsigned HalfSize = VT.getVectorNumElements()/2;
4554 bool MatchA = false, MatchB = false;
4556 // Check if A comes from one of C, D, E, F.
4557 for (unsigned Half = 0; Half != 4; ++Half) {
4558 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4564 // Check if B comes from one of C, D, E, F.
4565 for (unsigned Half = 0; Half != 4; ++Half) {
4566 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4572 return MatchA && MatchB;
4575 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4576 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4577 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4578 MVT VT = SVOp->getSimpleValueType(0);
4580 unsigned HalfSize = VT.getVectorNumElements()/2;
4582 unsigned FstHalf = 0, SndHalf = 0;
4583 for (unsigned i = 0; i < HalfSize; ++i) {
4584 if (SVOp->getMaskElt(i) > 0) {
4585 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4589 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4590 if (SVOp->getMaskElt(i) > 0) {
4591 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4596 return (FstHalf | (SndHalf << 4));
4599 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4600 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4601 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4605 unsigned NumElts = VT.getVectorNumElements();
4607 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4608 for (unsigned i = 0; i != NumElts; ++i) {
4611 Imm8 |= Mask[i] << (i*2);
4616 unsigned LaneSize = 4;
4617 SmallVector<int, 4> MaskVal(LaneSize, -1);
4619 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4620 for (unsigned i = 0; i != LaneSize; ++i) {
4621 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4625 if (MaskVal[i] < 0) {
4626 MaskVal[i] = Mask[i+l] - l;
4627 Imm8 |= MaskVal[i] << (i*2);
4630 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4637 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4639 /// Note that VPERMIL mask matching is different depending whether theunderlying
4640 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4641 /// to the same elements of the low, but to the higher half of the source.
4642 /// In VPERMILPD the two lanes could be shuffled independently of each other
4643 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4644 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4645 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4646 if (VT.getSizeInBits() < 256 || EltSize < 32)
4648 bool symetricMaskRequired = (EltSize == 32);
4649 unsigned NumElts = VT.getVectorNumElements();
4651 unsigned NumLanes = VT.getSizeInBits()/128;
4652 unsigned LaneSize = NumElts/NumLanes;
4653 // 2 or 4 elements in one lane
4655 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4656 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4657 for (unsigned i = 0; i != LaneSize; ++i) {
4658 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4660 if (symetricMaskRequired) {
4661 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4662 ExpectedMaskVal[i] = Mask[i+l] - l;
4665 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4673 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4674 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4675 /// element of vector 2 and the other elements to come from vector 1 in order.
4676 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4677 bool V2IsSplat = false, bool V2IsUndef = false) {
4678 if (!VT.is128BitVector())
4681 unsigned NumOps = VT.getVectorNumElements();
4682 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4685 if (!isUndefOrEqual(Mask[0], 0))
4688 for (unsigned i = 1; i != NumOps; ++i)
4689 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4690 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4691 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4697 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4698 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4699 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4700 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4701 const X86Subtarget *Subtarget) {
4702 if (!Subtarget->hasSSE3())
4705 unsigned NumElems = VT.getVectorNumElements();
4707 if ((VT.is128BitVector() && NumElems != 4) ||
4708 (VT.is256BitVector() && NumElems != 8) ||
4709 (VT.is512BitVector() && NumElems != 16))
4712 // "i+1" is the value the indexed mask element must have
4713 for (unsigned i = 0; i != NumElems; i += 2)
4714 if (!isUndefOrEqual(Mask[i], i+1) ||
4715 !isUndefOrEqual(Mask[i+1], i+1))
4721 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4722 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4723 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4724 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4725 const X86Subtarget *Subtarget) {
4726 if (!Subtarget->hasSSE3())
4729 unsigned NumElems = VT.getVectorNumElements();
4731 if ((VT.is128BitVector() && NumElems != 4) ||
4732 (VT.is256BitVector() && NumElems != 8) ||
4733 (VT.is512BitVector() && NumElems != 16))
4736 // "i" is the value the indexed mask element must have
4737 for (unsigned i = 0; i != NumElems; i += 2)
4738 if (!isUndefOrEqual(Mask[i], i) ||
4739 !isUndefOrEqual(Mask[i+1], i))
4745 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4746 /// specifies a shuffle of elements that is suitable for input to 256-bit
4747 /// version of MOVDDUP.
4748 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4749 if (!HasFp256 || !VT.is256BitVector())
4752 unsigned NumElts = VT.getVectorNumElements();
4756 for (unsigned i = 0; i != NumElts/2; ++i)
4757 if (!isUndefOrEqual(Mask[i], 0))
4759 for (unsigned i = NumElts/2; i != NumElts; ++i)
4760 if (!isUndefOrEqual(Mask[i], NumElts/2))
4765 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4766 /// specifies a shuffle of elements that is suitable for input to 128-bit
4767 /// version of MOVDDUP.
4768 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4769 if (!VT.is128BitVector())
4772 unsigned e = VT.getVectorNumElements() / 2;
4773 for (unsigned i = 0; i != e; ++i)
4774 if (!isUndefOrEqual(Mask[i], i))
4776 for (unsigned i = 0; i != e; ++i)
4777 if (!isUndefOrEqual(Mask[e+i], i))
4782 /// isVEXTRACTIndex - Return true if the specified
4783 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4784 /// suitable for instruction that extract 128 or 256 bit vectors
4785 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4786 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4787 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4790 // The index should be aligned on a vecWidth-bit boundary.
4792 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4794 MVT VT = N->getSimpleValueType(0);
4795 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4796 bool Result = (Index * ElSize) % vecWidth == 0;
4801 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4802 /// operand specifies a subvector insert that is suitable for input to
4803 /// insertion of 128 or 256-bit subvectors
4804 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4805 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4806 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4808 // The index should be aligned on a vecWidth-bit boundary.
4810 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4812 MVT VT = N->getSimpleValueType(0);
4813 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4814 bool Result = (Index * ElSize) % vecWidth == 0;
4819 bool X86::isVINSERT128Index(SDNode *N) {
4820 return isVINSERTIndex(N, 128);
4823 bool X86::isVINSERT256Index(SDNode *N) {
4824 return isVINSERTIndex(N, 256);
4827 bool X86::isVEXTRACT128Index(SDNode *N) {
4828 return isVEXTRACTIndex(N, 128);
4831 bool X86::isVEXTRACT256Index(SDNode *N) {
4832 return isVEXTRACTIndex(N, 256);
4835 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4836 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4837 /// Handles 128-bit and 256-bit.
4838 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4839 MVT VT = N->getSimpleValueType(0);
4841 assert((VT.getSizeInBits() >= 128) &&
4842 "Unsupported vector type for PSHUF/SHUFP");
4844 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4845 // independently on 128-bit lanes.
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4850 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4851 "Only supports 2, 4 or 8 elements per lane");
4853 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4855 for (unsigned i = 0; i != NumElts; ++i) {
4856 int Elt = N->getMaskElt(i);
4857 if (Elt < 0) continue;
4858 Elt &= NumLaneElts - 1;
4859 unsigned ShAmt = (i << Shift) % 8;
4860 Mask |= Elt << ShAmt;
4866 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4867 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4868 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4869 MVT VT = N->getSimpleValueType(0);
4871 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4872 "Unsupported vector type for PSHUFHW");
4874 unsigned NumElts = VT.getVectorNumElements();
4877 for (unsigned l = 0; l != NumElts; l += 8) {
4878 // 8 nodes per lane, but we only care about the last 4.
4879 for (unsigned i = 0; i < 4; ++i) {
4880 int Elt = N->getMaskElt(l+i+4);
4881 if (Elt < 0) continue;
4882 Elt &= 0x3; // only 2-bits.
4883 Mask |= Elt << (i * 2);
4890 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4891 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4892 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4893 MVT VT = N->getSimpleValueType(0);
4895 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4896 "Unsupported vector type for PSHUFHW");
4898 unsigned NumElts = VT.getVectorNumElements();
4901 for (unsigned l = 0; l != NumElts; l += 8) {
4902 // 8 nodes per lane, but we only care about the first 4.
4903 for (unsigned i = 0; i < 4; ++i) {
4904 int Elt = N->getMaskElt(l+i);
4905 if (Elt < 0) continue;
4906 Elt &= 0x3; // only 2-bits
4907 Mask |= Elt << (i * 2);
4914 /// \brief Return the appropriate immediate to shuffle the specified
4915 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4916 /// VALIGN (if Interlane is true) instructions.
4917 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4919 MVT VT = SVOp->getSimpleValueType(0);
4920 unsigned EltSize = InterLane ? 1 :
4921 VT.getVectorElementType().getSizeInBits() >> 3;
4923 unsigned NumElts = VT.getVectorNumElements();
4924 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4925 unsigned NumLaneElts = NumElts/NumLanes;
4929 for (i = 0; i != NumElts; ++i) {
4930 Val = SVOp->getMaskElt(i);
4934 if (Val >= (int)NumElts)
4935 Val -= NumElts - NumLaneElts;
4937 assert(Val - i > 0 && "PALIGNR imm should be positive");
4938 return (Val - i) * EltSize;
4941 /// \brief Return the appropriate immediate to shuffle the specified
4942 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4943 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4944 return getShuffleAlignrImmediate(SVOp, false);
4947 /// \brief Return the appropriate immediate to shuffle the specified
4948 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4949 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4950 return getShuffleAlignrImmediate(SVOp, true);
4954 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4955 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4956 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4957 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4960 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4962 MVT VecVT = N->getOperand(0).getSimpleValueType();
4963 MVT ElVT = VecVT.getVectorElementType();
4965 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4966 return Index / NumElemsPerChunk;
4969 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4970 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4971 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4972 llvm_unreachable("Illegal insert subvector for VINSERT");
4975 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4977 MVT VecVT = N->getSimpleValueType(0);
4978 MVT ElVT = VecVT.getVectorElementType();
4980 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4981 return Index / NumElemsPerChunk;
4984 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4985 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4986 /// and VINSERTI128 instructions.
4987 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4988 return getExtractVEXTRACTImmediate(N, 128);
4991 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4993 /// and VINSERTI64x4 instructions.
4994 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4995 return getExtractVEXTRACTImmediate(N, 256);
4998 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4999 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
5000 /// and VINSERTI128 instructions.
5001 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
5002 return getInsertVINSERTImmediate(N, 128);
5005 /// getInsertVINSERT256Immediate - Return the appropriate immediate
5006 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
5007 /// and VINSERTI64x4 instructions.
5008 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5009 return getInsertVINSERTImmediate(N, 256);
5012 /// isZero - Returns true if Elt is a constant integer zero
5013 static bool isZero(SDValue V) {
5014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5015 return C && C->isNullValue();
5018 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5020 bool X86::isZeroNode(SDValue Elt) {
5023 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5024 return CFP->getValueAPF().isPosZero();
5028 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5029 /// match movhlps. The lower half elements should come from upper half of
5030 /// V1 (and in order), and the upper half elements should come from the upper
5031 /// half of V2 (and in order).
5032 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5033 if (!VT.is128BitVector())
5035 if (VT.getVectorNumElements() != 4)
5037 for (unsigned i = 0, e = 2; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+2))
5040 for (unsigned i = 2; i != 4; ++i)
5041 if (!isUndefOrEqual(Mask[i], i+4))
5046 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5047 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5049 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5050 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5052 N = N->getOperand(0).getNode();
5053 if (!ISD::isNON_EXTLoad(N))
5056 *LD = cast<LoadSDNode>(N);
5060 // Test whether the given value is a vector value which will be legalized
5062 static bool WillBeConstantPoolLoad(SDNode *N) {
5063 if (N->getOpcode() != ISD::BUILD_VECTOR)
5066 // Check for any non-constant elements.
5067 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5068 switch (N->getOperand(i).getNode()->getOpcode()) {
5070 case ISD::ConstantFP:
5077 // Vectors of all-zeros and all-ones are materialized with special
5078 // instructions rather than being loaded.
5079 return !ISD::isBuildVectorAllZeros(N) &&
5080 !ISD::isBuildVectorAllOnes(N);
5083 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5084 /// match movlp{s|d}. The lower half elements should come from lower half of
5085 /// V1 (and in order), and the upper half elements should come from the upper
5086 /// half of V2 (and in order). And since V1 will become the source of the
5087 /// MOVLP, it must be either a vector load or a scalar load to vector.
5088 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5089 ArrayRef<int> Mask, MVT VT) {
5090 if (!VT.is128BitVector())
5093 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5095 // Is V2 is a vector load, don't do this transformation. We will try to use
5096 // load folding shufps op.
5097 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5100 unsigned NumElems = VT.getVectorNumElements();
5102 if (NumElems != 2 && NumElems != 4)
5104 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5105 if (!isUndefOrEqual(Mask[i], i))
5107 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5108 if (!isUndefOrEqual(Mask[i], i+NumElems))
5113 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5114 /// to an zero vector.
5115 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5116 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5117 SDValue V1 = N->getOperand(0);
5118 SDValue V2 = N->getOperand(1);
5119 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5120 for (unsigned i = 0; i != NumElems; ++i) {
5121 int Idx = N->getMaskElt(i);
5122 if (Idx >= (int)NumElems) {
5123 unsigned Opc = V2.getOpcode();
5124 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5126 if (Opc != ISD::BUILD_VECTOR ||
5127 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5129 } else if (Idx >= 0) {
5130 unsigned Opc = V1.getOpcode();
5131 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5133 if (Opc != ISD::BUILD_VECTOR ||
5134 !X86::isZeroNode(V1.getOperand(Idx)))
5141 /// getZeroVector - Returns a vector of specified type with all zero elements.
5143 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5144 SelectionDAG &DAG, SDLoc dl) {
5145 assert(VT.isVector() && "Expected a vector type");
5147 // Always build SSE zero vectors as <4 x i32> bitcasted
5148 // to their dest type. This ensures they get CSE'd.
5150 if (VT.is128BitVector()) { // SSE
5151 if (Subtarget->hasSSE2()) { // SSE2
5152 SDValue Cst = DAG.getConstant(0, MVT::i32);
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5155 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5158 } else if (VT.is256BitVector()) { // AVX
5159 if (Subtarget->hasInt256()) { // AVX2
5160 SDValue Cst = DAG.getConstant(0, MVT::i32);
5161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5164 // 256-bit logic and arithmetic instructions in AVX are all
5165 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5166 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5167 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5168 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5170 } else if (VT.is512BitVector()) { // AVX-512
5171 SDValue Cst = DAG.getConstant(0, MVT::i32);
5172 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5173 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5175 } else if (VT.getScalarType() == MVT::i1) {
5176 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5177 SDValue Cst = DAG.getConstant(0, MVT::i1);
5178 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5179 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5181 llvm_unreachable("Unexpected vector type");
5183 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5186 /// getOnesVector - Returns a vector of specified type with all bits set.
5187 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5188 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5189 /// Then bitcast to their original type, ensuring they get CSE'd.
5190 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5192 assert(VT.isVector() && "Expected a vector type");
5194 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5196 if (VT.is256BitVector()) {
5197 if (HasInt256) { // AVX2
5198 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5199 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5201 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5202 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5204 } else if (VT.is128BitVector()) {
5205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5207 llvm_unreachable("Unexpected vector type");
5209 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5212 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5213 /// that point to V2 points to its first element.
5214 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5215 for (unsigned i = 0; i != NumElems; ++i) {
5216 if (Mask[i] > (int)NumElems) {
5222 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5223 /// operation of specified width.
5224 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5226 unsigned NumElems = VT.getVectorNumElements();
5227 SmallVector<int, 8> Mask;
5228 Mask.push_back(NumElems);
5229 for (unsigned i = 1; i != NumElems; ++i)
5231 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5234 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5235 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5237 unsigned NumElems = VT.getVectorNumElements();
5238 SmallVector<int, 8> Mask;
5239 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5241 Mask.push_back(i + NumElems);
5243 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5246 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5247 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5249 unsigned NumElems = VT.getVectorNumElements();
5250 SmallVector<int, 8> Mask;
5251 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5252 Mask.push_back(i + Half);
5253 Mask.push_back(i + NumElems + Half);
5255 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5258 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5259 // a generic shuffle instruction because the target has no such instructions.
5260 // Generate shuffles which repeat i16 and i8 several times until they can be
5261 // represented by v4f32 and then be manipulated by target suported shuffles.
5262 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5263 MVT VT = V.getSimpleValueType();
5264 int NumElems = VT.getVectorNumElements();
5267 while (NumElems > 4) {
5268 if (EltNo < NumElems/2) {
5269 V = getUnpackl(DAG, dl, VT, V, V);
5271 V = getUnpackh(DAG, dl, VT, V, V);
5272 EltNo -= NumElems/2;
5279 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5280 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5281 MVT VT = V.getSimpleValueType();
5284 if (VT.is128BitVector()) {
5285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5286 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5287 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5289 } else if (VT.is256BitVector()) {
5290 // To use VPERMILPS to splat scalars, the second half of indicies must
5291 // refer to the higher part, which is a duplication of the lower one,
5292 // because VPERMILPS can only handle in-lane permutations.
5293 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5294 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5297 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5300 llvm_unreachable("Vector size not supported");
5302 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5305 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5306 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5307 MVT SrcVT = SV->getSimpleValueType(0);
5308 SDValue V1 = SV->getOperand(0);
5311 int EltNo = SV->getSplatIndex();
5312 int NumElems = SrcVT.getVectorNumElements();
5313 bool Is256BitVec = SrcVT.is256BitVector();
5315 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5316 "Unknown how to promote splat for type");
5318 // Extract the 128-bit part containing the splat element and update
5319 // the splat element index when it refers to the higher register.
5321 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5322 if (EltNo >= NumElems/2)
5323 EltNo -= NumElems/2;
5326 // All i16 and i8 vector types can't be used directly by a generic shuffle
5327 // instruction because the target has no such instruction. Generate shuffles
5328 // which repeat i16 and i8 several times until they fit in i32, and then can
5329 // be manipulated by target suported shuffles.
5330 MVT EltVT = SrcVT.getVectorElementType();
5331 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5332 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5334 // Recreate the 256-bit vector and place the same 128-bit vector
5335 // into the low and high part. This is necessary because we want
5336 // to use VPERM* to shuffle the vectors
5338 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5341 return getLegalSplat(DAG, V1, EltNo);
5344 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5345 /// vector of zero or undef vector. This produces a shuffle where the low
5346 /// element of V2 is swizzled into the zero/undef vector, landing at element
5347 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5348 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5350 const X86Subtarget *Subtarget,
5351 SelectionDAG &DAG) {
5352 MVT VT = V2.getSimpleValueType();
5354 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5355 unsigned NumElems = VT.getVectorNumElements();
5356 SmallVector<int, 16> MaskVec;
5357 for (unsigned i = 0; i != NumElems; ++i)
5358 // If this is the insertion idx, put the low elt of V2 here.
5359 MaskVec.push_back(i == Idx ? NumElems : i);
5360 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5363 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5364 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5365 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5366 /// shuffles which use a single input multiple times, and in those cases it will
5367 /// adjust the mask to only have indices within that single input.
5368 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5369 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5370 unsigned NumElems = VT.getVectorNumElements();
5374 bool IsFakeUnary = false;
5375 switch(N->getOpcode()) {
5376 case X86ISD::BLENDI:
5377 ImmN = N->getOperand(N->getNumOperands()-1);
5378 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5383 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5385 case X86ISD::UNPCKH:
5386 DecodeUNPCKHMask(VT, Mask);
5387 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5389 case X86ISD::UNPCKL:
5390 DecodeUNPCKLMask(VT, Mask);
5391 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5393 case X86ISD::MOVHLPS:
5394 DecodeMOVHLPSMask(NumElems, Mask);
5395 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5397 case X86ISD::MOVLHPS:
5398 DecodeMOVLHPSMask(NumElems, Mask);
5399 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5401 case X86ISD::PALIGNR:
5402 ImmN = N->getOperand(N->getNumOperands()-1);
5403 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5405 case X86ISD::PSHUFD:
5406 case X86ISD::VPERMILPI:
5407 ImmN = N->getOperand(N->getNumOperands()-1);
5408 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5411 case X86ISD::PSHUFHW:
5412 ImmN = N->getOperand(N->getNumOperands()-1);
5413 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::PSHUFLW:
5417 ImmN = N->getOperand(N->getNumOperands()-1);
5418 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5421 case X86ISD::PSHUFB: {
5423 SDValue MaskNode = N->getOperand(1);
5424 while (MaskNode->getOpcode() == ISD::BITCAST)
5425 MaskNode = MaskNode->getOperand(0);
5427 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5428 // If we have a build-vector, then things are easy.
5429 EVT VT = MaskNode.getValueType();
5430 assert(VT.isVector() &&
5431 "Can't produce a non-vector with a build_vector!");
5432 if (!VT.isInteger())
5435 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5437 SmallVector<uint64_t, 32> RawMask;
5438 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5439 SDValue Op = MaskNode->getOperand(i);
5440 if (Op->getOpcode() == ISD::UNDEF) {
5441 RawMask.push_back((uint64_t)SM_SentinelUndef);
5444 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5447 APInt MaskElement = CN->getAPIntValue();
5449 // We now have to decode the element which could be any integer size and
5450 // extract each byte of it.
5451 for (int j = 0; j < NumBytesPerElement; ++j) {
5452 // Note that this is x86 and so always little endian: the low byte is
5453 // the first byte of the mask.
5454 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5455 MaskElement = MaskElement.lshr(8);
5458 DecodePSHUFBMask(RawMask, Mask);
5462 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5466 SDValue Ptr = MaskLoad->getBasePtr();
5467 if (Ptr->getOpcode() == X86ISD::Wrapper)
5468 Ptr = Ptr->getOperand(0);
5470 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5471 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5474 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5475 // FIXME: Support AVX-512 here.
5476 Type *Ty = C->getType();
5477 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5478 Ty->getVectorNumElements() != 32))
5481 DecodePSHUFBMask(C, Mask);
5487 case X86ISD::VPERMI:
5488 ImmN = N->getOperand(N->getNumOperands()-1);
5489 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5493 case X86ISD::MOVSD: {
5494 // The index 0 always comes from the first element of the second source,
5495 // this is why MOVSS and MOVSD are used in the first place. The other
5496 // elements come from the other positions of the first source vector
5497 Mask.push_back(NumElems);
5498 for (unsigned i = 1; i != NumElems; ++i) {
5503 case X86ISD::VPERM2X128:
5504 ImmN = N->getOperand(N->getNumOperands()-1);
5505 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5506 if (Mask.empty()) return false;
5508 case X86ISD::MOVSLDUP:
5509 DecodeMOVSLDUPMask(VT, Mask);
5511 case X86ISD::MOVSHDUP:
5512 DecodeMOVSHDUPMask(VT, Mask);
5514 case X86ISD::MOVDDUP:
5515 case X86ISD::MOVLHPD:
5516 case X86ISD::MOVLPD:
5517 case X86ISD::MOVLPS:
5518 // Not yet implemented
5520 default: llvm_unreachable("unknown target shuffle node");
5523 // If we have a fake unary shuffle, the shuffle mask is spread across two
5524 // inputs that are actually the same node. Re-map the mask to always point
5525 // into the first input.
5528 if (M >= (int)Mask.size())
5534 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5535 /// element of the result of the vector shuffle.
5536 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5539 return SDValue(); // Limit search depth.
5541 SDValue V = SDValue(N, 0);
5542 EVT VT = V.getValueType();
5543 unsigned Opcode = V.getOpcode();
5545 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5546 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5547 int Elt = SV->getMaskElt(Index);
5550 return DAG.getUNDEF(VT.getVectorElementType());
5552 unsigned NumElems = VT.getVectorNumElements();
5553 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5554 : SV->getOperand(1);
5555 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5558 // Recurse into target specific vector shuffles to find scalars.
5559 if (isTargetShuffle(Opcode)) {
5560 MVT ShufVT = V.getSimpleValueType();
5561 unsigned NumElems = ShufVT.getVectorNumElements();
5562 SmallVector<int, 16> ShuffleMask;
5565 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5568 int Elt = ShuffleMask[Index];
5570 return DAG.getUNDEF(ShufVT.getVectorElementType());
5572 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5574 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5578 // Actual nodes that may contain scalar elements
5579 if (Opcode == ISD::BITCAST) {
5580 V = V.getOperand(0);
5581 EVT SrcVT = V.getValueType();
5582 unsigned NumElems = VT.getVectorNumElements();
5584 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5588 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5589 return (Index == 0) ? V.getOperand(0)
5590 : DAG.getUNDEF(VT.getVectorElementType());
5592 if (V.getOpcode() == ISD::BUILD_VECTOR)
5593 return V.getOperand(Index);
5598 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5599 /// shuffle operation which come from a consecutively from a zero. The
5600 /// search can start in two different directions, from left or right.
5601 /// We count undefs as zeros until PreferredNum is reached.
5602 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5603 unsigned NumElems, bool ZerosFromLeft,
5605 unsigned PreferredNum = -1U) {
5606 unsigned NumZeros = 0;
5607 for (unsigned i = 0; i != NumElems; ++i) {
5608 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5609 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5613 if (X86::isZeroNode(Elt))
5615 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5616 NumZeros = std::min(NumZeros + 1, PreferredNum);
5624 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5625 /// correspond consecutively to elements from one of the vector operands,
5626 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5628 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5629 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5630 unsigned NumElems, unsigned &OpNum) {
5631 bool SeenV1 = false;
5632 bool SeenV2 = false;
5634 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5635 int Idx = SVOp->getMaskElt(i);
5636 // Ignore undef indicies
5640 if (Idx < (int)NumElems)
5645 // Only accept consecutive elements from the same vector
5646 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5650 OpNum = SeenV1 ? 0 : 1;
5654 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5655 /// logical left shift of a vector.
5656 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5657 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5659 SVOp->getSimpleValueType(0).getVectorNumElements();
5660 unsigned NumZeros = getNumOfConsecutiveZeros(
5661 SVOp, NumElems, false /* check zeros from right */, DAG,
5662 SVOp->getMaskElt(0));
5668 // Considering the elements in the mask that are not consecutive zeros,
5669 // check if they consecutively come from only one of the source vectors.
5671 // V1 = {X, A, B, C} 0
5673 // vector_shuffle V1, V2 <1, 2, 3, X>
5675 if (!isShuffleMaskConsecutive(SVOp,
5676 0, // Mask Start Index
5677 NumElems-NumZeros, // Mask End Index(exclusive)
5678 NumZeros, // Where to start looking in the src vector
5679 NumElems, // Number of elements in vector
5680 OpSrc)) // Which source operand ?
5685 ShVal = SVOp->getOperand(OpSrc);
5689 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5690 /// logical left shift of a vector.
5691 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5692 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5694 SVOp->getSimpleValueType(0).getVectorNumElements();
5695 unsigned NumZeros = getNumOfConsecutiveZeros(
5696 SVOp, NumElems, true /* check zeros from left */, DAG,
5697 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5703 // Considering the elements in the mask that are not consecutive zeros,
5704 // check if they consecutively come from only one of the source vectors.
5706 // 0 { A, B, X, X } = V2
5708 // vector_shuffle V1, V2 <X, X, 4, 5>
5710 if (!isShuffleMaskConsecutive(SVOp,
5711 NumZeros, // Mask Start Index
5712 NumElems, // Mask End Index(exclusive)
5713 0, // Where to start looking in the src vector
5714 NumElems, // Number of elements in vector
5715 OpSrc)) // Which source operand ?
5720 ShVal = SVOp->getOperand(OpSrc);
5724 /// isVectorShift - Returns true if the shuffle can be implemented as a
5725 /// logical left or right shift of a vector.
5726 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5727 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5728 // Although the logic below support any bitwidth size, there are no
5729 // shift instructions which handle more than 128-bit vectors.
5730 if (!SVOp->getSimpleValueType(0).is128BitVector())
5733 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5734 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5740 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5742 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5743 unsigned NumNonZero, unsigned NumZero,
5745 const X86Subtarget* Subtarget,
5746 const TargetLowering &TLI) {
5753 for (unsigned i = 0; i < 16; ++i) {
5754 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5755 if (ThisIsNonZero && First) {
5757 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5759 V = DAG.getUNDEF(MVT::v8i16);
5764 SDValue ThisElt, LastElt;
5765 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5766 if (LastIsNonZero) {
5767 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5768 MVT::i16, Op.getOperand(i-1));
5770 if (ThisIsNonZero) {
5771 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5772 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5773 ThisElt, DAG.getConstant(8, MVT::i8));
5775 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5779 if (ThisElt.getNode())
5780 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5781 DAG.getIntPtrConstant(i/2));
5785 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5788 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5790 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5791 unsigned NumNonZero, unsigned NumZero,
5793 const X86Subtarget* Subtarget,
5794 const TargetLowering &TLI) {
5801 for (unsigned i = 0; i < 8; ++i) {
5802 bool isNonZero = (NonZeros & (1 << i)) != 0;
5806 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5808 V = DAG.getUNDEF(MVT::v8i16);
5811 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5812 MVT::v8i16, V, Op.getOperand(i),
5813 DAG.getIntPtrConstant(i));
5820 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5821 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5822 const X86Subtarget *Subtarget,
5823 const TargetLowering &TLI) {
5824 // Find all zeroable elements.
5826 for (int i=0; i < 4; ++i) {
5827 SDValue Elt = Op->getOperand(i);
5828 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5830 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5831 [](bool M) { return !M; }) > 1 &&
5832 "We expect at least two non-zero elements!");
5834 // We only know how to deal with build_vector nodes where elements are either
5835 // zeroable or extract_vector_elt with constant index.
5836 SDValue FirstNonZero;
5837 unsigned FirstNonZeroIdx;
5838 for (unsigned i=0; i < 4; ++i) {
5841 SDValue Elt = Op->getOperand(i);
5842 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5843 !isa<ConstantSDNode>(Elt.getOperand(1)))
5845 // Make sure that this node is extracting from a 128-bit vector.
5846 MVT VT = Elt.getOperand(0).getSimpleValueType();
5847 if (!VT.is128BitVector())
5849 if (!FirstNonZero.getNode()) {
5851 FirstNonZeroIdx = i;
5855 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5856 SDValue V1 = FirstNonZero.getOperand(0);
5857 MVT VT = V1.getSimpleValueType();
5859 // See if this build_vector can be lowered as a blend with zero.
5861 unsigned EltMaskIdx, EltIdx;
5863 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5864 if (Zeroable[EltIdx]) {
5865 // The zero vector will be on the right hand side.
5866 Mask[EltIdx] = EltIdx+4;
5870 Elt = Op->getOperand(EltIdx);
5871 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5872 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5873 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5875 Mask[EltIdx] = EltIdx;
5879 // Let the shuffle legalizer deal with blend operations.
5880 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5881 if (V1.getSimpleValueType() != VT)
5882 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5883 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5886 // See if we can lower this build_vector to a INSERTPS.
5887 if (!Subtarget->hasSSE41())
5890 SDValue V2 = Elt.getOperand(0);
5891 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5894 bool CanFold = true;
5895 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5899 SDValue Current = Op->getOperand(i);
5900 SDValue SrcVector = Current->getOperand(0);
5903 CanFold = SrcVector == V1 &&
5904 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5910 assert(V1.getNode() && "Expected at least two non-zero elements!");
5911 if (V1.getSimpleValueType() != MVT::v4f32)
5912 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5913 if (V2.getSimpleValueType() != MVT::v4f32)
5914 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5916 // Ok, we can emit an INSERTPS instruction.
5918 for (int i = 0; i < 4; ++i)
5922 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5923 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5924 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5925 DAG.getIntPtrConstant(InsertPSMask));
5926 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5929 /// getVShift - Return a vector logical shift node.
5931 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5932 unsigned NumBits, SelectionDAG &DAG,
5933 const TargetLowering &TLI, SDLoc dl) {
5934 assert(VT.is128BitVector() && "Unknown type for VShift");
5935 EVT ShVT = MVT::v2i64;
5936 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5937 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5938 return DAG.getNode(ISD::BITCAST, dl, VT,
5939 DAG.getNode(Opc, dl, ShVT, SrcOp,
5940 DAG.getConstant(NumBits,
5941 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5945 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5947 // Check if the scalar load can be widened into a vector load. And if
5948 // the address is "base + cst" see if the cst can be "absorbed" into
5949 // the shuffle mask.
5950 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5951 SDValue Ptr = LD->getBasePtr();
5952 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5954 EVT PVT = LD->getValueType(0);
5955 if (PVT != MVT::i32 && PVT != MVT::f32)
5960 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5961 FI = FINode->getIndex();
5963 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5964 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5965 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5966 Offset = Ptr.getConstantOperandVal(1);
5967 Ptr = Ptr.getOperand(0);
5972 // FIXME: 256-bit vector instructions don't require a strict alignment,
5973 // improve this code to support it better.
5974 unsigned RequiredAlign = VT.getSizeInBits()/8;
5975 SDValue Chain = LD->getChain();
5976 // Make sure the stack object alignment is at least 16 or 32.
5977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5978 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5979 if (MFI->isFixedObjectIndex(FI)) {
5980 // Can't change the alignment. FIXME: It's possible to compute
5981 // the exact stack offset and reference FI + adjust offset instead.
5982 // If someone *really* cares about this. That's the way to implement it.
5985 MFI->setObjectAlignment(FI, RequiredAlign);
5989 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5990 // Ptr + (Offset & ~15).
5993 if ((Offset % RequiredAlign) & 3)
5995 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5997 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5998 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
6000 int EltNo = (Offset - StartOffset) >> 2;
6001 unsigned NumElems = VT.getVectorNumElements();
6003 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
6004 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
6005 LD->getPointerInfo().getWithOffset(StartOffset),
6006 false, false, false, 0);
6008 SmallVector<int, 8> Mask;
6009 for (unsigned i = 0; i != NumElems; ++i)
6010 Mask.push_back(EltNo);
6012 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6018 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6019 /// vector of type 'VT', see if the elements can be replaced by a single large
6020 /// load which has the same value as a build_vector whose operands are 'elts'.
6022 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6024 /// FIXME: we'd also like to handle the case where the last elements are zero
6025 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6026 /// There's even a handy isZeroNode for that purpose.
6027 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6028 SDLoc &DL, SelectionDAG &DAG,
6029 bool isAfterLegalize) {
6030 EVT EltVT = VT.getVectorElementType();
6031 unsigned NumElems = Elts.size();
6033 LoadSDNode *LDBase = nullptr;
6034 unsigned LastLoadedElt = -1U;
6036 // For each element in the initializer, see if we've found a load or an undef.
6037 // If we don't find an initial load element, or later load elements are
6038 // non-consecutive, bail out.
6039 for (unsigned i = 0; i < NumElems; ++i) {
6040 SDValue Elt = Elts[i];
6042 if (!Elt.getNode() ||
6043 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6046 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6048 LDBase = cast<LoadSDNode>(Elt.getNode());
6052 if (Elt.getOpcode() == ISD::UNDEF)
6055 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6056 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6061 // If we have found an entire vector of loads and undefs, then return a large
6062 // load of the entire vector width starting at the base pointer. If we found
6063 // consecutive loads for the low half, generate a vzext_load node.
6064 if (LastLoadedElt == NumElems - 1) {
6066 if (isAfterLegalize &&
6067 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6070 SDValue NewLd = SDValue();
6072 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6073 LDBase->getPointerInfo(), LDBase->isVolatile(),
6074 LDBase->isNonTemporal(), LDBase->isInvariant(),
6075 LDBase->getAlignment());
6077 if (LDBase->hasAnyUseOfValue(1)) {
6078 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6080 SDValue(NewLd.getNode(), 1));
6081 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6082 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6083 SDValue(NewLd.getNode(), 1));
6089 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6090 //of a v4i32 / v4f32. It's probably worth generalizing.
6091 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6092 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6093 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6094 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6096 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6097 LDBase->getPointerInfo(),
6098 LDBase->getAlignment(),
6099 false/*isVolatile*/, true/*ReadMem*/,
6102 // Make sure the newly-created LOAD is in the same position as LDBase in
6103 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6104 // update uses of LDBase's output chain to use the TokenFactor.
6105 if (LDBase->hasAnyUseOfValue(1)) {
6106 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6107 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6108 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6109 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6110 SDValue(ResNode.getNode(), 1));
6113 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6118 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6119 /// to generate a splat value for the following cases:
6120 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6121 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6122 /// a scalar load, or a constant.
6123 /// The VBROADCAST node is returned when a pattern is found,
6124 /// or SDValue() otherwise.
6125 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6126 SelectionDAG &DAG) {
6127 // VBROADCAST requires AVX.
6128 // TODO: Splats could be generated for non-AVX CPUs using SSE
6129 // instructions, but there's less potential gain for only 128-bit vectors.
6130 if (!Subtarget->hasAVX())
6133 MVT VT = Op.getSimpleValueType();
6136 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6137 "Unsupported vector type for broadcast.");
6142 switch (Op.getOpcode()) {
6144 // Unknown pattern found.
6147 case ISD::BUILD_VECTOR: {
6148 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6149 BitVector UndefElements;
6150 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6152 // We need a splat of a single value to use broadcast, and it doesn't
6153 // make any sense if the value is only in one element of the vector.
6154 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6158 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6159 Ld.getOpcode() == ISD::ConstantFP);
6161 // Make sure that all of the users of a non-constant load are from the
6162 // BUILD_VECTOR node.
6163 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6168 case ISD::VECTOR_SHUFFLE: {
6169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6171 // Shuffles must have a splat mask where the first element is
6173 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6176 SDValue Sc = Op.getOperand(0);
6177 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6178 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6180 if (!Subtarget->hasInt256())
6183 // Use the register form of the broadcast instruction available on AVX2.
6184 if (VT.getSizeInBits() >= 256)
6185 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6186 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6189 Ld = Sc.getOperand(0);
6190 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6191 Ld.getOpcode() == ISD::ConstantFP);
6193 // The scalar_to_vector node and the suspected
6194 // load node must have exactly one user.
6195 // Constants may have multiple users.
6197 // AVX-512 has register version of the broadcast
6198 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6199 Ld.getValueType().getSizeInBits() >= 32;
6200 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6207 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6208 bool IsGE256 = (VT.getSizeInBits() >= 256);
6210 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6211 // instruction to save 8 or more bytes of constant pool data.
6212 // TODO: If multiple splats are generated to load the same constant,
6213 // it may be detrimental to overall size. There needs to be a way to detect
6214 // that condition to know if this is truly a size win.
6215 const Function *F = DAG.getMachineFunction().getFunction();
6216 bool OptForSize = F->getAttributes().
6217 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6219 // Handle broadcasting a single constant scalar from the constant pool
6221 // On Sandybridge (no AVX2), it is still better to load a constant vector
6222 // from the constant pool and not to broadcast it from a scalar.
6223 // But override that restriction when optimizing for size.
6224 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6225 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6226 EVT CVT = Ld.getValueType();
6227 assert(!CVT.isVector() && "Must not broadcast a vector type");
6229 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6230 // For size optimization, also splat v2f64 and v2i64, and for size opt
6231 // with AVX2, also splat i8 and i16.
6232 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6233 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6234 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6235 const Constant *C = nullptr;
6236 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6237 C = CI->getConstantIntValue();
6238 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6239 C = CF->getConstantFPValue();
6241 assert(C && "Invalid constant type");
6243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6244 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6245 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6246 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6247 MachinePointerInfo::getConstantPool(),
6248 false, false, false, Alignment);
6250 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6254 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6256 // Handle AVX2 in-register broadcasts.
6257 if (!IsLoad && Subtarget->hasInt256() &&
6258 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6259 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6261 // The scalar source must be a normal load.
6265 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6266 (Subtarget->hasVLX() && ScalarSize == 64))
6267 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6269 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6270 // double since there is no vbroadcastsd xmm
6271 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6272 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6273 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6276 // Unsupported broadcast.
6280 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6281 /// underlying vector and index.
6283 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6285 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6287 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6288 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6291 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6293 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6295 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6296 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6299 // In this case the vector is the extract_subvector expression and the index
6300 // is 2, as specified by the shuffle.
6301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6302 SDValue ShuffleVec = SVOp->getOperand(0);
6303 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6304 assert(ShuffleVecVT.getVectorElementType() ==
6305 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6307 int ShuffleIdx = SVOp->getMaskElt(Idx);
6308 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6309 ExtractedFromVec = ShuffleVec;
6315 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6316 MVT VT = Op.getSimpleValueType();
6318 // Skip if insert_vec_elt is not supported.
6319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6320 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6324 unsigned NumElems = Op.getNumOperands();
6328 SmallVector<unsigned, 4> InsertIndices;
6329 SmallVector<int, 8> Mask(NumElems, -1);
6331 for (unsigned i = 0; i != NumElems; ++i) {
6332 unsigned Opc = Op.getOperand(i).getOpcode();
6334 if (Opc == ISD::UNDEF)
6337 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6338 // Quit if more than 1 elements need inserting.
6339 if (InsertIndices.size() > 1)
6342 InsertIndices.push_back(i);
6346 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6347 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6348 // Quit if non-constant index.
6349 if (!isa<ConstantSDNode>(ExtIdx))
6351 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6353 // Quit if extracted from vector of different type.
6354 if (ExtractedFromVec.getValueType() != VT)
6357 if (!VecIn1.getNode())
6358 VecIn1 = ExtractedFromVec;
6359 else if (VecIn1 != ExtractedFromVec) {
6360 if (!VecIn2.getNode())
6361 VecIn2 = ExtractedFromVec;
6362 else if (VecIn2 != ExtractedFromVec)
6363 // Quit if more than 2 vectors to shuffle
6367 if (ExtractedFromVec == VecIn1)
6369 else if (ExtractedFromVec == VecIn2)
6370 Mask[i] = Idx + NumElems;
6373 if (!VecIn1.getNode())
6376 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6377 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6378 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6379 unsigned Idx = InsertIndices[i];
6380 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6381 DAG.getIntPtrConstant(Idx));
6387 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6389 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6391 MVT VT = Op.getSimpleValueType();
6392 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6393 "Unexpected type in LowerBUILD_VECTORvXi1!");
6396 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6397 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6398 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6399 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6402 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6403 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6404 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6405 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6408 bool AllContants = true;
6409 uint64_t Immediate = 0;
6410 int NonConstIdx = -1;
6411 bool IsSplat = true;
6412 unsigned NumNonConsts = 0;
6413 unsigned NumConsts = 0;
6414 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6415 SDValue In = Op.getOperand(idx);
6416 if (In.getOpcode() == ISD::UNDEF)
6418 if (!isa<ConstantSDNode>(In)) {
6419 AllContants = false;
6424 if (cast<ConstantSDNode>(In)->getZExtValue())
6425 Immediate |= (1ULL << idx);
6427 if (In != Op.getOperand(0))
6432 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6433 DAG.getConstant(Immediate, MVT::i16));
6434 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6435 DAG.getIntPtrConstant(0));
6438 if (NumNonConsts == 1 && NonConstIdx != 0) {
6441 SDValue VecAsImm = DAG.getConstant(Immediate,
6442 MVT::getIntegerVT(VT.getSizeInBits()));
6443 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6446 DstVec = DAG.getUNDEF(VT);
6447 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6448 Op.getOperand(NonConstIdx),
6449 DAG.getIntPtrConstant(NonConstIdx));
6451 if (!IsSplat && (NonConstIdx != 0))
6452 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6453 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6456 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6457 DAG.getConstant(-1, SelectVT),
6458 DAG.getConstant(0, SelectVT));
6460 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6461 DAG.getConstant((Immediate | 1), SelectVT),
6462 DAG.getConstant(Immediate, SelectVT));
6463 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6466 /// \brief Return true if \p N implements a horizontal binop and return the
6467 /// operands for the horizontal binop into V0 and V1.
6469 /// This is a helper function of PerformBUILD_VECTORCombine.
6470 /// This function checks that the build_vector \p N in input implements a
6471 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6472 /// operation to match.
6473 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6474 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6475 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6478 /// This function only analyzes elements of \p N whose indices are
6479 /// in range [BaseIdx, LastIdx).
6480 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6482 unsigned BaseIdx, unsigned LastIdx,
6483 SDValue &V0, SDValue &V1) {
6484 EVT VT = N->getValueType(0);
6486 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6487 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6488 "Invalid Vector in input!");
6490 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6491 bool CanFold = true;
6492 unsigned ExpectedVExtractIdx = BaseIdx;
6493 unsigned NumElts = LastIdx - BaseIdx;
6494 V0 = DAG.getUNDEF(VT);
6495 V1 = DAG.getUNDEF(VT);
6497 // Check if N implements a horizontal binop.
6498 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6499 SDValue Op = N->getOperand(i + BaseIdx);
6502 if (Op->getOpcode() == ISD::UNDEF) {
6503 // Update the expected vector extract index.
6504 if (i * 2 == NumElts)
6505 ExpectedVExtractIdx = BaseIdx;
6506 ExpectedVExtractIdx += 2;
6510 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6515 SDValue Op0 = Op.getOperand(0);
6516 SDValue Op1 = Op.getOperand(1);
6518 // Try to match the following pattern:
6519 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6520 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6521 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6522 Op0.getOperand(0) == Op1.getOperand(0) &&
6523 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6524 isa<ConstantSDNode>(Op1.getOperand(1)));
6528 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6529 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6531 if (i * 2 < NumElts) {
6532 if (V0.getOpcode() == ISD::UNDEF)
6533 V0 = Op0.getOperand(0);
6535 if (V1.getOpcode() == ISD::UNDEF)
6536 V1 = Op0.getOperand(0);
6537 if (i * 2 == NumElts)
6538 ExpectedVExtractIdx = BaseIdx;
6541 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6542 if (I0 == ExpectedVExtractIdx)
6543 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6544 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6545 // Try to match the following dag sequence:
6546 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6547 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6551 ExpectedVExtractIdx += 2;
6557 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6558 /// a concat_vector.
6560 /// This is a helper function of PerformBUILD_VECTORCombine.
6561 /// This function expects two 256-bit vectors called V0 and V1.
6562 /// At first, each vector is split into two separate 128-bit vectors.
6563 /// Then, the resulting 128-bit vectors are used to implement two
6564 /// horizontal binary operations.
6566 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6568 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6569 /// the two new horizontal binop.
6570 /// When Mode is set, the first horizontal binop dag node would take as input
6571 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6572 /// horizontal binop dag node would take as input the lower 128-bit of V1
6573 /// and the upper 128-bit of V1.
6575 /// HADD V0_LO, V0_HI
6576 /// HADD V1_LO, V1_HI
6578 /// Otherwise, the first horizontal binop dag node takes as input the lower
6579 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6580 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6582 /// HADD V0_LO, V1_LO
6583 /// HADD V0_HI, V1_HI
6585 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6586 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6587 /// the upper 128-bits of the result.
6588 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6589 SDLoc DL, SelectionDAG &DAG,
6590 unsigned X86Opcode, bool Mode,
6591 bool isUndefLO, bool isUndefHI) {
6592 EVT VT = V0.getValueType();
6593 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6594 "Invalid nodes in input!");
6596 unsigned NumElts = VT.getVectorNumElements();
6597 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6598 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6599 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6600 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6601 EVT NewVT = V0_LO.getValueType();
6603 SDValue LO = DAG.getUNDEF(NewVT);
6604 SDValue HI = DAG.getUNDEF(NewVT);
6607 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6608 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6609 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6610 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6611 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6613 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6614 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6615 V1_LO->getOpcode() != ISD::UNDEF))
6616 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6618 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6619 V1_HI->getOpcode() != ISD::UNDEF))
6620 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6623 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6626 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6627 /// sequence of 'vadd + vsub + blendi'.
6628 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6629 const X86Subtarget *Subtarget) {
6631 EVT VT = BV->getValueType(0);
6632 unsigned NumElts = VT.getVectorNumElements();
6633 SDValue InVec0 = DAG.getUNDEF(VT);
6634 SDValue InVec1 = DAG.getUNDEF(VT);
6636 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6637 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6639 // Odd-numbered elements in the input build vector are obtained from
6640 // adding two integer/float elements.
6641 // Even-numbered elements in the input build vector are obtained from
6642 // subtracting two integer/float elements.
6643 unsigned ExpectedOpcode = ISD::FSUB;
6644 unsigned NextExpectedOpcode = ISD::FADD;
6645 bool AddFound = false;
6646 bool SubFound = false;
6648 for (unsigned i = 0, e = NumElts; i != e; i++) {
6649 SDValue Op = BV->getOperand(i);
6651 // Skip 'undef' values.
6652 unsigned Opcode = Op.getOpcode();
6653 if (Opcode == ISD::UNDEF) {
6654 std::swap(ExpectedOpcode, NextExpectedOpcode);
6658 // Early exit if we found an unexpected opcode.
6659 if (Opcode != ExpectedOpcode)
6662 SDValue Op0 = Op.getOperand(0);
6663 SDValue Op1 = Op.getOperand(1);
6665 // Try to match the following pattern:
6666 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6667 // Early exit if we cannot match that sequence.
6668 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6669 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6670 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6671 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6672 Op0.getOperand(1) != Op1.getOperand(1))
6675 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6679 // We found a valid add/sub node. Update the information accordingly.
6685 // Update InVec0 and InVec1.
6686 if (InVec0.getOpcode() == ISD::UNDEF)
6687 InVec0 = Op0.getOperand(0);
6688 if (InVec1.getOpcode() == ISD::UNDEF)
6689 InVec1 = Op1.getOperand(0);
6691 // Make sure that operands in input to each add/sub node always
6692 // come from a same pair of vectors.
6693 if (InVec0 != Op0.getOperand(0)) {
6694 if (ExpectedOpcode == ISD::FSUB)
6697 // FADD is commutable. Try to commute the operands
6698 // and then test again.
6699 std::swap(Op0, Op1);
6700 if (InVec0 != Op0.getOperand(0))
6704 if (InVec1 != Op1.getOperand(0))
6707 // Update the pair of expected opcodes.
6708 std::swap(ExpectedOpcode, NextExpectedOpcode);
6711 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6712 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6713 InVec1.getOpcode() != ISD::UNDEF)
6714 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6719 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6720 const X86Subtarget *Subtarget) {
6722 EVT VT = N->getValueType(0);
6723 unsigned NumElts = VT.getVectorNumElements();
6724 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6725 SDValue InVec0, InVec1;
6727 // Try to match an ADDSUB.
6728 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6729 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6730 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6731 if (Value.getNode())
6735 // Try to match horizontal ADD/SUB.
6736 unsigned NumUndefsLO = 0;
6737 unsigned NumUndefsHI = 0;
6738 unsigned Half = NumElts/2;
6740 // Count the number of UNDEF operands in the build_vector in input.
6741 for (unsigned i = 0, e = Half; i != e; ++i)
6742 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6745 for (unsigned i = Half, e = NumElts; i != e; ++i)
6746 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6749 // Early exit if this is either a build_vector of all UNDEFs or all the
6750 // operands but one are UNDEF.
6751 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6754 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6755 // Try to match an SSE3 float HADD/HSUB.
6756 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6757 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6759 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6760 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6761 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6762 // Try to match an SSSE3 integer HADD/HSUB.
6763 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6764 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6766 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6767 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6770 if (!Subtarget->hasAVX())
6773 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6774 // Try to match an AVX horizontal add/sub of packed single/double
6775 // precision floating point values from 256-bit vectors.
6776 SDValue InVec2, InVec3;
6777 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6778 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6779 ((InVec0.getOpcode() == ISD::UNDEF ||
6780 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6781 ((InVec1.getOpcode() == ISD::UNDEF ||
6782 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6783 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6785 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6786 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6787 ((InVec0.getOpcode() == ISD::UNDEF ||
6788 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6789 ((InVec1.getOpcode() == ISD::UNDEF ||
6790 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6791 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6792 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6793 // Try to match an AVX2 horizontal add/sub of signed integers.
6794 SDValue InVec2, InVec3;
6796 bool CanFold = true;
6798 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6799 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6800 ((InVec0.getOpcode() == ISD::UNDEF ||
6801 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6802 ((InVec1.getOpcode() == ISD::UNDEF ||
6803 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6804 X86Opcode = X86ISD::HADD;
6805 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6806 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6807 ((InVec0.getOpcode() == ISD::UNDEF ||
6808 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6809 ((InVec1.getOpcode() == ISD::UNDEF ||
6810 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6811 X86Opcode = X86ISD::HSUB;
6816 // Fold this build_vector into a single horizontal add/sub.
6817 // Do this only if the target has AVX2.
6818 if (Subtarget->hasAVX2())
6819 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6821 // Do not try to expand this build_vector into a pair of horizontal
6822 // add/sub if we can emit a pair of scalar add/sub.
6823 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6826 // Convert this build_vector into a pair of horizontal binop followed by
6828 bool isUndefLO = NumUndefsLO == Half;
6829 bool isUndefHI = NumUndefsHI == Half;
6830 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6831 isUndefLO, isUndefHI);
6835 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6836 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6838 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6839 X86Opcode = X86ISD::HADD;
6840 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6841 X86Opcode = X86ISD::HSUB;
6842 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6843 X86Opcode = X86ISD::FHADD;
6844 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6845 X86Opcode = X86ISD::FHSUB;
6849 // Don't try to expand this build_vector into a pair of horizontal add/sub
6850 // if we can simply emit a pair of scalar add/sub.
6851 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6854 // Convert this build_vector into two horizontal add/sub followed by
6856 bool isUndefLO = NumUndefsLO == Half;
6857 bool isUndefHI = NumUndefsHI == Half;
6858 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6859 isUndefLO, isUndefHI);
6866 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6869 MVT VT = Op.getSimpleValueType();
6870 MVT ExtVT = VT.getVectorElementType();
6871 unsigned NumElems = Op.getNumOperands();
6873 // Generate vectors for predicate vectors.
6874 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6875 return LowerBUILD_VECTORvXi1(Op, DAG);
6877 // Vectors containing all zeros can be matched by pxor and xorps later
6878 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6879 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6880 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6881 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6884 return getZeroVector(VT, Subtarget, DAG, dl);
6887 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6888 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6889 // vpcmpeqd on 256-bit vectors.
6890 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6891 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6894 if (!VT.is512BitVector())
6895 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6898 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6899 if (Broadcast.getNode())
6902 unsigned EVTBits = ExtVT.getSizeInBits();
6904 unsigned NumZero = 0;
6905 unsigned NumNonZero = 0;
6906 unsigned NonZeros = 0;
6907 bool IsAllConstants = true;
6908 SmallSet<SDValue, 8> Values;
6909 for (unsigned i = 0; i < NumElems; ++i) {
6910 SDValue Elt = Op.getOperand(i);
6911 if (Elt.getOpcode() == ISD::UNDEF)
6914 if (Elt.getOpcode() != ISD::Constant &&
6915 Elt.getOpcode() != ISD::ConstantFP)
6916 IsAllConstants = false;
6917 if (X86::isZeroNode(Elt))
6920 NonZeros |= (1 << i);
6925 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6926 if (NumNonZero == 0)
6927 return DAG.getUNDEF(VT);
6929 // Special case for single non-zero, non-undef, element.
6930 if (NumNonZero == 1) {
6931 unsigned Idx = countTrailingZeros(NonZeros);
6932 SDValue Item = Op.getOperand(Idx);
6934 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6935 // the value are obviously zero, truncate the value to i32 and do the
6936 // insertion that way. Only do this if the value is non-constant or if the
6937 // value is a constant being inserted into element 0. It is cheaper to do
6938 // a constant pool load than it is to do a movd + shuffle.
6939 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6940 (!IsAllConstants || Idx == 0)) {
6941 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6943 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6944 EVT VecVT = MVT::v4i32;
6945 unsigned VecElts = 4;
6947 // Truncate the value (which may itself be a constant) to i32, and
6948 // convert it to a vector with movd (S2V+shuffle to zero extend).
6949 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6952 // If using the new shuffle lowering, just directly insert this.
6953 if (ExperimentalVectorShuffleLowering)
6955 ISD::BITCAST, dl, VT,
6956 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6960 // Now we have our 32-bit value zero extended in the low element of
6961 // a vector. If Idx != 0, swizzle it into place.
6963 SmallVector<int, 4> Mask;
6964 Mask.push_back(Idx);
6965 for (unsigned i = 1; i != VecElts; ++i)
6967 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6970 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6974 // If we have a constant or non-constant insertion into the low element of
6975 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6976 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6977 // depending on what the source datatype is.
6980 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6982 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6983 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6984 if (VT.is256BitVector() || VT.is512BitVector()) {
6985 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6986 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6987 Item, DAG.getIntPtrConstant(0));
6989 assert(VT.is128BitVector() && "Expected an SSE value type!");
6990 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6991 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6992 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6995 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6996 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6997 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6998 if (VT.is256BitVector()) {
6999 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
7000 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
7002 assert(VT.is128BitVector() && "Expected an SSE value type!");
7003 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
7005 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7009 // Is it a vector logical left shift?
7010 if (NumElems == 2 && Idx == 1 &&
7011 X86::isZeroNode(Op.getOperand(0)) &&
7012 !X86::isZeroNode(Op.getOperand(1))) {
7013 unsigned NumBits = VT.getSizeInBits();
7014 return getVShift(true, VT,
7015 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7016 VT, Op.getOperand(1)),
7017 NumBits/2, DAG, *this, dl);
7020 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7023 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7024 // is a non-constant being inserted into an element other than the low one,
7025 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7026 // movd/movss) to move this into the low element, then shuffle it into
7028 if (EVTBits == 32) {
7029 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7031 // If using the new shuffle lowering, just directly insert this.
7032 if (ExperimentalVectorShuffleLowering)
7033 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7035 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7036 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7037 SmallVector<int, 8> MaskVec;
7038 for (unsigned i = 0; i != NumElems; ++i)
7039 MaskVec.push_back(i == Idx ? 0 : 1);
7040 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7044 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7045 if (Values.size() == 1) {
7046 if (EVTBits == 32) {
7047 // Instead of a shuffle like this:
7048 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7049 // Check if it's possible to issue this instead.
7050 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7051 unsigned Idx = countTrailingZeros(NonZeros);
7052 SDValue Item = Op.getOperand(Idx);
7053 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7054 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7059 // A vector full of immediates; various special cases are already
7060 // handled, so this is best done with a single constant-pool load.
7064 // For AVX-length vectors, see if we can use a vector load to get all of the
7065 // elements, otherwise build the individual 128-bit pieces and use
7066 // shuffles to put them in place.
7067 if (VT.is256BitVector() || VT.is512BitVector()) {
7068 SmallVector<SDValue, 64> V;
7069 for (unsigned i = 0; i != NumElems; ++i)
7070 V.push_back(Op.getOperand(i));
7072 // Check for a build vector of consecutive loads.
7073 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7076 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7078 // Build both the lower and upper subvector.
7079 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7080 makeArrayRef(&V[0], NumElems/2));
7081 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7082 makeArrayRef(&V[NumElems / 2], NumElems/2));
7084 // Recreate the wider vector with the lower and upper part.
7085 if (VT.is256BitVector())
7086 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7087 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7090 // Let legalizer expand 2-wide build_vectors.
7091 if (EVTBits == 64) {
7092 if (NumNonZero == 1) {
7093 // One half is zero or undef.
7094 unsigned Idx = countTrailingZeros(NonZeros);
7095 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7096 Op.getOperand(Idx));
7097 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7102 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7103 if (EVTBits == 8 && NumElems == 16) {
7104 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7106 if (V.getNode()) return V;
7109 if (EVTBits == 16 && NumElems == 8) {
7110 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7112 if (V.getNode()) return V;
7115 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7116 if (EVTBits == 32 && NumElems == 4) {
7117 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7122 // If element VT is == 32 bits, turn it into a number of shuffles.
7123 SmallVector<SDValue, 8> V(NumElems);
7124 if (NumElems == 4 && NumZero > 0) {
7125 for (unsigned i = 0; i < 4; ++i) {
7126 bool isZero = !(NonZeros & (1 << i));
7128 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7130 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7133 for (unsigned i = 0; i < 2; ++i) {
7134 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7137 V[i] = V[i*2]; // Must be a zero vector.
7140 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7143 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7146 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7151 bool Reverse1 = (NonZeros & 0x3) == 2;
7152 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7156 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7157 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7159 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7162 if (Values.size() > 1 && VT.is128BitVector()) {
7163 // Check for a build vector of consecutive loads.
7164 for (unsigned i = 0; i < NumElems; ++i)
7165 V[i] = Op.getOperand(i);
7167 // Check for elements which are consecutive loads.
7168 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7172 // Check for a build vector from mostly shuffle plus few inserting.
7173 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7177 // For SSE 4.1, use insertps to put the high elements into the low element.
7178 if (getSubtarget()->hasSSE41()) {
7180 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7181 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7183 Result = DAG.getUNDEF(VT);
7185 for (unsigned i = 1; i < NumElems; ++i) {
7186 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7187 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7188 Op.getOperand(i), DAG.getIntPtrConstant(i));
7193 // Otherwise, expand into a number of unpckl*, start by extending each of
7194 // our (non-undef) elements to the full vector width with the element in the
7195 // bottom slot of the vector (which generates no code for SSE).
7196 for (unsigned i = 0; i < NumElems; ++i) {
7197 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7198 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7200 V[i] = DAG.getUNDEF(VT);
7203 // Next, we iteratively mix elements, e.g. for v4f32:
7204 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7205 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7206 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7207 unsigned EltStride = NumElems >> 1;
7208 while (EltStride != 0) {
7209 for (unsigned i = 0; i < EltStride; ++i) {
7210 // If V[i+EltStride] is undef and this is the first round of mixing,
7211 // then it is safe to just drop this shuffle: V[i] is already in the
7212 // right place, the one element (since it's the first round) being
7213 // inserted as undef can be dropped. This isn't safe for successive
7214 // rounds because they will permute elements within both vectors.
7215 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7216 EltStride == NumElems/2)
7219 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7228 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7229 // to create 256-bit vectors from two other 128-bit ones.
7230 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7232 MVT ResVT = Op.getSimpleValueType();
7234 assert((ResVT.is256BitVector() ||
7235 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7237 SDValue V1 = Op.getOperand(0);
7238 SDValue V2 = Op.getOperand(1);
7239 unsigned NumElems = ResVT.getVectorNumElements();
7240 if(ResVT.is256BitVector())
7241 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7243 if (Op.getNumOperands() == 4) {
7244 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7245 ResVT.getVectorNumElements()/2);
7246 SDValue V3 = Op.getOperand(2);
7247 SDValue V4 = Op.getOperand(3);
7248 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7249 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7251 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7254 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7255 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7256 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7257 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7258 Op.getNumOperands() == 4)));
7260 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7261 // from two other 128-bit ones.
7263 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7264 return LowerAVXCONCAT_VECTORS(Op, DAG);
7268 //===----------------------------------------------------------------------===//
7269 // Vector shuffle lowering
7271 // This is an experimental code path for lowering vector shuffles on x86. It is
7272 // designed to handle arbitrary vector shuffles and blends, gracefully
7273 // degrading performance as necessary. It works hard to recognize idiomatic
7274 // shuffles and lower them to optimal instruction patterns without leaving
7275 // a framework that allows reasonably efficient handling of all vector shuffle
7277 //===----------------------------------------------------------------------===//
7279 /// \brief Tiny helper function to identify a no-op mask.
7281 /// This is a somewhat boring predicate function. It checks whether the mask
7282 /// array input, which is assumed to be a single-input shuffle mask of the kind
7283 /// used by the X86 shuffle instructions (not a fully general
7284 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7285 /// in-place shuffle are 'no-op's.
7286 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7287 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7288 if (Mask[i] != -1 && Mask[i] != i)
7293 /// \brief Helper function to classify a mask as a single-input mask.
7295 /// This isn't a generic single-input test because in the vector shuffle
7296 /// lowering we canonicalize single inputs to be the first input operand. This
7297 /// means we can more quickly test for a single input by only checking whether
7298 /// an input from the second operand exists. We also assume that the size of
7299 /// mask corresponds to the size of the input vectors which isn't true in the
7300 /// fully general case.
7301 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7303 if (M >= (int)Mask.size())
7308 /// \brief Test whether there are elements crossing 128-bit lanes in this
7311 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7312 /// and we routinely test for these.
7313 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7314 int LaneSize = 128 / VT.getScalarSizeInBits();
7315 int Size = Mask.size();
7316 for (int i = 0; i < Size; ++i)
7317 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7322 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7324 /// This checks a shuffle mask to see if it is performing the same
7325 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7326 /// that it is also not lane-crossing. It may however involve a blend from the
7327 /// same lane of a second vector.
7329 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7330 /// non-trivial to compute in the face of undef lanes. The representation is
7331 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7332 /// entries from both V1 and V2 inputs to the wider mask.
7334 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7335 SmallVectorImpl<int> &RepeatedMask) {
7336 int LaneSize = 128 / VT.getScalarSizeInBits();
7337 RepeatedMask.resize(LaneSize, -1);
7338 int Size = Mask.size();
7339 for (int i = 0; i < Size; ++i) {
7342 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7343 // This entry crosses lanes, so there is no way to model this shuffle.
7346 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7347 if (RepeatedMask[i % LaneSize] == -1)
7348 // This is the first non-undef entry in this slot of a 128-bit lane.
7349 RepeatedMask[i % LaneSize] =
7350 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7351 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7352 // Found a mismatch with the repeated mask.
7358 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7359 // 2013 will allow us to use it as a non-type template parameter.
7362 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7364 /// See its documentation for details.
7365 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7366 if (Mask.size() != Args.size())
7368 for (int i = 0, e = Mask.size(); i < e; ++i) {
7369 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7370 if (Mask[i] != -1 && Mask[i] != *Args[i])
7378 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7381 /// This is a fast way to test a shuffle mask against a fixed pattern:
7383 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7385 /// It returns true if the mask is exactly as wide as the argument list, and
7386 /// each element of the mask is either -1 (signifying undef) or the value given
7387 /// in the argument.
7388 static const VariadicFunction1<
7389 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7391 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7393 /// This helper function produces an 8-bit shuffle immediate corresponding to
7394 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7395 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7398 /// NB: We rely heavily on "undef" masks preserving the input lane.
7399 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7400 SelectionDAG &DAG) {
7401 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7402 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7403 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7404 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7405 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7408 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7409 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7410 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7411 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7412 return DAG.getConstant(Imm, MVT::i8);
7415 /// \brief Try to emit a blend instruction for a shuffle.
7417 /// This doesn't do any checks for the availability of instructions for blending
7418 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7419 /// be matched in the backend with the type given. What it does check for is
7420 /// that the shuffle mask is in fact a blend.
7421 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7422 SDValue V2, ArrayRef<int> Mask,
7423 const X86Subtarget *Subtarget,
7424 SelectionDAG &DAG) {
7426 unsigned BlendMask = 0;
7427 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7428 if (Mask[i] >= Size) {
7429 if (Mask[i] != i + Size)
7430 return SDValue(); // Shuffled V2 input!
7431 BlendMask |= 1u << i;
7434 if (Mask[i] >= 0 && Mask[i] != i)
7435 return SDValue(); // Shuffled V1 input!
7437 switch (VT.SimpleTy) {
7442 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7443 DAG.getConstant(BlendMask, MVT::i8));
7447 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7451 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7452 // that instruction.
7453 if (Subtarget->hasAVX2()) {
7454 // Scale the blend by the number of 32-bit dwords per element.
7455 int Scale = VT.getScalarSizeInBits() / 32;
7457 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7458 if (Mask[i] >= Size)
7459 for (int j = 0; j < Scale; ++j)
7460 BlendMask |= 1u << (i * Scale + j);
7462 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7463 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7464 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7465 return DAG.getNode(ISD::BITCAST, DL, VT,
7466 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7467 DAG.getConstant(BlendMask, MVT::i8)));
7471 // For integer shuffles we need to expand the mask and cast the inputs to
7472 // v8i16s prior to blending.
7473 int Scale = 8 / VT.getVectorNumElements();
7475 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7476 if (Mask[i] >= Size)
7477 for (int j = 0; j < Scale; ++j)
7478 BlendMask |= 1u << (i * Scale + j);
7480 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7481 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7482 return DAG.getNode(ISD::BITCAST, DL, VT,
7483 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7484 DAG.getConstant(BlendMask, MVT::i8)));
7488 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7489 SmallVector<int, 8> RepeatedMask;
7490 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7491 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7492 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7494 for (int i = 0; i < 8; ++i)
7495 if (RepeatedMask[i] >= 16)
7496 BlendMask |= 1u << i;
7497 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7498 DAG.getConstant(BlendMask, MVT::i8));
7503 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7504 // Scale the blend by the number of bytes per element.
7505 int Scale = VT.getScalarSizeInBits() / 8;
7506 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7508 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7509 // mix of LLVM's code generator and the x86 backend. We tell the code
7510 // generator that boolean values in the elements of an x86 vector register
7511 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7512 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7513 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7514 // of the element (the remaining are ignored) and 0 in that high bit would
7515 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7516 // the LLVM model for boolean values in vector elements gets the relevant
7517 // bit set, it is set backwards and over constrained relative to x86's
7519 SDValue VSELECTMask[32];
7520 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7521 for (int j = 0; j < Scale; ++j)
7522 VSELECTMask[Scale * i + j] =
7523 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7524 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7526 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7527 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7529 ISD::BITCAST, DL, VT,
7530 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7531 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7536 llvm_unreachable("Not a supported integer vector type!");
7540 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7541 /// unblended shuffles followed by an unshuffled blend.
7543 /// This matches the extremely common pattern for handling combined
7544 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7546 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7550 SelectionDAG &DAG) {
7551 // Shuffle the input elements into the desired positions in V1 and V2 and
7552 // blend them together.
7553 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7554 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7555 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7556 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7557 if (Mask[i] >= 0 && Mask[i] < Size) {
7558 V1Mask[i] = Mask[i];
7560 } else if (Mask[i] >= Size) {
7561 V2Mask[i] = Mask[i] - Size;
7562 BlendMask[i] = i + Size;
7565 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7566 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7567 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7570 /// \brief Try to lower a vector shuffle as a byte rotation.
7572 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7573 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7574 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7575 /// try to generically lower a vector shuffle through such an pattern. It
7576 /// does not check for the profitability of lowering either as PALIGNR or
7577 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7578 /// This matches shuffle vectors that look like:
7580 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7582 /// Essentially it concatenates V1 and V2, shifts right by some number of
7583 /// elements, and takes the low elements as the result. Note that while this is
7584 /// specified as a *right shift* because x86 is little-endian, it is a *left
7585 /// rotate* of the vector lanes.
7587 /// Note that this only handles 128-bit vector widths currently.
7588 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7591 const X86Subtarget *Subtarget,
7592 SelectionDAG &DAG) {
7593 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7595 // We need to detect various ways of spelling a rotation:
7596 // [11, 12, 13, 14, 15, 0, 1, 2]
7597 // [-1, 12, 13, 14, -1, -1, 1, -1]
7598 // [-1, -1, -1, -1, -1, -1, 1, 2]
7599 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7600 // [-1, 4, 5, 6, -1, -1, 9, -1]
7601 // [-1, 4, 5, 6, -1, -1, -1, -1]
7604 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7607 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7609 // Based on the mod-Size value of this mask element determine where
7610 // a rotated vector would have started.
7611 int StartIdx = i - (Mask[i] % Size);
7613 // The identity rotation isn't interesting, stop.
7616 // If we found the tail of a vector the rotation must be the missing
7617 // front. If we found the head of a vector, it must be how much of the head.
7618 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7621 Rotation = CandidateRotation;
7622 else if (Rotation != CandidateRotation)
7623 // The rotations don't match, so we can't match this mask.
7626 // Compute which value this mask is pointing at.
7627 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7629 // Compute which of the two target values this index should be assigned to.
7630 // This reflects whether the high elements are remaining or the low elements
7632 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7634 // Either set up this value if we've not encountered it before, or check
7635 // that it remains consistent.
7638 else if (TargetV != MaskV)
7639 // This may be a rotation, but it pulls from the inputs in some
7640 // unsupported interleaving.
7644 // Check that we successfully analyzed the mask, and normalize the results.
7645 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7646 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7652 assert(VT.getSizeInBits() == 128 &&
7653 "Rotate-based lowering only supports 128-bit lowering!");
7654 assert(Mask.size() <= 16 &&
7655 "Can shuffle at most 16 bytes in a 128-bit vector!");
7657 // The actual rotate instruction rotates bytes, so we need to scale the
7658 // rotation based on how many bytes are in the vector.
7659 int Scale = 16 / Mask.size();
7661 // SSSE3 targets can use the palignr instruction
7662 if (Subtarget->hasSSSE3()) {
7663 // Cast the inputs to v16i8 to match PALIGNR.
7664 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7665 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7667 return DAG.getNode(ISD::BITCAST, DL, VT,
7668 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7669 DAG.getConstant(Rotation * Scale, MVT::i8)));
7672 // Default SSE2 implementation
7673 int LoByteShift = 16 - Rotation * Scale;
7674 int HiByteShift = Rotation * Scale;
7676 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7677 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7678 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7680 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7681 DAG.getConstant(8 * LoByteShift, MVT::i8));
7682 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7683 DAG.getConstant(8 * HiByteShift, MVT::i8));
7684 return DAG.getNode(ISD::BITCAST, DL, VT,
7685 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7688 /// \brief Compute whether each element of a shuffle is zeroable.
7690 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7691 /// Either it is an undef element in the shuffle mask, the element of the input
7692 /// referenced is undef, or the element of the input referenced is known to be
7693 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7694 /// as many lanes with this technique as possible to simplify the remaining
7696 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7697 SDValue V1, SDValue V2) {
7698 SmallBitVector Zeroable(Mask.size(), false);
7700 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7701 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7703 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7705 // Handle the easy cases.
7706 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7711 // If this is an index into a build_vector node, dig out the input value and
7713 SDValue V = M < Size ? V1 : V2;
7714 if (V.getOpcode() != ISD::BUILD_VECTOR)
7717 SDValue Input = V.getOperand(M % Size);
7718 // The UNDEF opcode check really should be dead code here, but not quite
7719 // worth asserting on (it isn't invalid, just unexpected).
7720 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7727 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7729 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7730 /// byte-shift instructions. The mask must consist of a shifted sequential
7731 /// shuffle from one of the input vectors and zeroable elements for the
7732 /// remaining 'shifted in' elements.
7734 /// Note that this only handles 128-bit vector widths currently.
7735 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7736 SDValue V2, ArrayRef<int> Mask,
7737 SelectionDAG &DAG) {
7738 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7740 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7742 int Size = Mask.size();
7743 int Scale = 16 / Size;
7745 for (int Shift = 1; Shift < Size; Shift++) {
7746 int ByteShift = Shift * Scale;
7748 // PSRLDQ : (little-endian) right byte shift
7749 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7750 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7751 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7752 bool ZeroableRight = true;
7753 for (int i = Size - Shift; i < Size; i++) {
7754 ZeroableRight &= Zeroable[i];
7757 if (ZeroableRight) {
7758 bool ValidShiftRight1 =
7759 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7760 bool ValidShiftRight2 =
7761 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7763 if (ValidShiftRight1 || ValidShiftRight2) {
7764 // Cast the inputs to v2i64 to match PSRLDQ.
7765 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7766 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7767 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7768 DAG.getConstant(ByteShift * 8, MVT::i8));
7769 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7773 // PSLLDQ : (little-endian) left byte shift
7774 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7775 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7776 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7777 bool ZeroableLeft = true;
7778 for (int i = 0; i < Shift; i++) {
7779 ZeroableLeft &= Zeroable[i];
7783 bool ValidShiftLeft1 =
7784 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7785 bool ValidShiftLeft2 =
7786 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7788 if (ValidShiftLeft1 || ValidShiftLeft2) {
7789 // Cast the inputs to v2i64 to match PSLLDQ.
7790 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7791 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7792 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7793 DAG.getConstant(ByteShift * 8, MVT::i8));
7794 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7802 /// \brief Lower a vector shuffle as a zero or any extension.
7804 /// Given a specific number of elements, element bit width, and extension
7805 /// stride, produce either a zero or any extension based on the available
7806 /// features of the subtarget.
7807 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7808 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7809 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7810 assert(Scale > 1 && "Need a scale to extend.");
7811 int EltBits = VT.getSizeInBits() / NumElements;
7812 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7813 "Only 8, 16, and 32 bit elements can be extended.");
7814 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7816 // Found a valid zext mask! Try various lowering strategies based on the
7817 // input type and available ISA extensions.
7818 if (Subtarget->hasSSE41()) {
7819 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7820 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7821 NumElements / Scale);
7822 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7823 return DAG.getNode(ISD::BITCAST, DL, VT,
7824 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7827 // For any extends we can cheat for larger element sizes and use shuffle
7828 // instructions that can fold with a load and/or copy.
7829 if (AnyExt && EltBits == 32) {
7830 int PSHUFDMask[4] = {0, -1, 1, -1};
7832 ISD::BITCAST, DL, VT,
7833 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7834 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7835 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7837 if (AnyExt && EltBits == 16 && Scale > 2) {
7838 int PSHUFDMask[4] = {0, -1, 0, -1};
7839 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7840 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7841 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7842 int PSHUFHWMask[4] = {1, -1, -1, -1};
7844 ISD::BITCAST, DL, VT,
7845 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7846 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7847 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7850 // If this would require more than 2 unpack instructions to expand, use
7851 // pshufb when available. We can only use more than 2 unpack instructions
7852 // when zero extending i8 elements which also makes it easier to use pshufb.
7853 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7854 assert(NumElements == 16 && "Unexpected byte vector width!");
7855 SDValue PSHUFBMask[16];
7856 for (int i = 0; i < 16; ++i)
7858 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7859 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7860 return DAG.getNode(ISD::BITCAST, DL, VT,
7861 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7862 DAG.getNode(ISD::BUILD_VECTOR, DL,
7863 MVT::v16i8, PSHUFBMask)));
7866 // Otherwise emit a sequence of unpacks.
7868 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7869 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7870 : getZeroVector(InputVT, Subtarget, DAG, DL);
7871 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7872 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7876 } while (Scale > 1);
7877 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7880 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7882 /// This routine will try to do everything in its power to cleverly lower
7883 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7884 /// check for the profitability of this lowering, it tries to aggressively
7885 /// match this pattern. It will use all of the micro-architectural details it
7886 /// can to emit an efficient lowering. It handles both blends with all-zero
7887 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7888 /// masking out later).
7890 /// The reason we have dedicated lowering for zext-style shuffles is that they
7891 /// are both incredibly common and often quite performance sensitive.
7892 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7893 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7894 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7895 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7897 int Bits = VT.getSizeInBits();
7898 int NumElements = Mask.size();
7900 // Define a helper function to check a particular ext-scale and lower to it if
7902 auto Lower = [&](int Scale) -> SDValue {
7905 for (int i = 0; i < NumElements; ++i) {
7907 continue; // Valid anywhere but doesn't tell us anything.
7908 if (i % Scale != 0) {
7909 // Each of the extend elements needs to be zeroable.
7913 // We no lorger are in the anyext case.
7918 // Each of the base elements needs to be consecutive indices into the
7919 // same input vector.
7920 SDValue V = Mask[i] < NumElements ? V1 : V2;
7923 else if (InputV != V)
7924 return SDValue(); // Flip-flopping inputs.
7926 if (Mask[i] % NumElements != i / Scale)
7927 return SDValue(); // Non-consecutive strided elemenst.
7930 // If we fail to find an input, we have a zero-shuffle which should always
7931 // have already been handled.
7932 // FIXME: Maybe handle this here in case during blending we end up with one?
7936 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7937 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7940 // The widest scale possible for extending is to a 64-bit integer.
7941 assert(Bits % 64 == 0 &&
7942 "The number of bits in a vector must be divisible by 64 on x86!");
7943 int NumExtElements = Bits / 64;
7945 // Each iteration, try extending the elements half as much, but into twice as
7947 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7948 assert(NumElements % NumExtElements == 0 &&
7949 "The input vector size must be divisble by the extended size.");
7950 if (SDValue V = Lower(NumElements / NumExtElements))
7954 // No viable ext lowering found.
7958 /// \brief Try to get a scalar value for a specific element of a vector.
7960 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7961 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7962 SelectionDAG &DAG) {
7963 MVT VT = V.getSimpleValueType();
7964 MVT EltVT = VT.getVectorElementType();
7965 while (V.getOpcode() == ISD::BITCAST)
7966 V = V.getOperand(0);
7967 // If the bitcasts shift the element size, we can't extract an equivalent
7969 MVT NewVT = V.getSimpleValueType();
7970 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7973 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7974 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7975 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7980 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7982 /// This is particularly important because the set of instructions varies
7983 /// significantly based on whether the operand is a load or not.
7984 static bool isShuffleFoldableLoad(SDValue V) {
7985 while (V.getOpcode() == ISD::BITCAST)
7986 V = V.getOperand(0);
7988 return ISD::isNON_EXTLoad(V.getNode());
7991 /// \brief Try to lower insertion of a single element into a zero vector.
7993 /// This is a common pattern that we have especially efficient patterns to lower
7994 /// across all subtarget feature sets.
7995 static SDValue lowerVectorShuffleAsElementInsertion(
7996 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7997 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7998 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8000 MVT EltVT = VT.getVectorElementType();
8002 int V2Index = std::find_if(Mask.begin(), Mask.end(),
8003 [&Mask](int M) { return M >= (int)Mask.size(); }) -
8005 bool IsV1Zeroable = true;
8006 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8007 if (i != V2Index && !Zeroable[i]) {
8008 IsV1Zeroable = false;
8012 // Check for a single input from a SCALAR_TO_VECTOR node.
8013 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8014 // all the smarts here sunk into that routine. However, the current
8015 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8016 // vector shuffle lowering is dead.
8017 if (SDValue V2S = getScalarValueForVectorElement(
8018 V2, Mask[V2Index] - Mask.size(), DAG)) {
8019 // We need to zext the scalar if it is smaller than an i32.
8020 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8021 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8022 // Using zext to expand a narrow element won't work for non-zero
8027 // Zero-extend directly to i32.
8029 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8031 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8032 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8033 EltVT == MVT::i16) {
8034 // Either not inserting from the low element of the input or the input
8035 // element size is too small to use VZEXT_MOVL to clear the high bits.
8039 if (!IsV1Zeroable) {
8040 // If V1 can't be treated as a zero vector we have fewer options to lower
8041 // this. We can't support integer vectors or non-zero targets cheaply, and
8042 // the V1 elements can't be permuted in any way.
8043 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8044 if (!VT.isFloatingPoint() || V2Index != 0)
8046 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8047 V1Mask[V2Index] = -1;
8048 if (!isNoopShuffleMask(V1Mask))
8050 // This is essentially a special case blend operation, but if we have
8051 // general purpose blend operations, they are always faster. Bail and let
8052 // the rest of the lowering handle these as blends.
8053 if (Subtarget->hasSSE41())
8056 // Otherwise, use MOVSD or MOVSS.
8057 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8058 "Only two types of floating point element types to handle!");
8059 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8063 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8065 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8068 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8069 // the desired position. Otherwise it is more efficient to do a vector
8070 // shift left. We know that we can do a vector shift left because all
8071 // the inputs are zero.
8072 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8073 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8074 V2Shuffle[V2Index] = 0;
8075 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8077 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8079 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8081 V2Index * EltVT.getSizeInBits(),
8082 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8083 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8089 /// \brief Try to lower broadcast of a single element.
8091 /// For convenience, this code also bundles all of the subtarget feature set
8092 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8093 /// a convenient way to factor it out.
8094 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8096 const X86Subtarget *Subtarget,
8097 SelectionDAG &DAG) {
8098 if (!Subtarget->hasAVX())
8100 if (VT.isInteger() && !Subtarget->hasAVX2())
8103 // Check that the mask is a broadcast.
8104 int BroadcastIdx = -1;
8106 if (M >= 0 && BroadcastIdx == -1)
8108 else if (M >= 0 && M != BroadcastIdx)
8111 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8112 "a sorted mask where the broadcast "
8115 // Go up the chain of (vector) values to try and find a scalar load that
8116 // we can combine with the broadcast.
8118 switch (V.getOpcode()) {
8119 case ISD::CONCAT_VECTORS: {
8120 int OperandSize = Mask.size() / V.getNumOperands();
8121 V = V.getOperand(BroadcastIdx / OperandSize);
8122 BroadcastIdx %= OperandSize;
8126 case ISD::INSERT_SUBVECTOR: {
8127 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8128 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8132 int BeginIdx = (int)ConstantIdx->getZExtValue();
8134 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8135 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8136 BroadcastIdx -= BeginIdx;
8147 // Check if this is a broadcast of a scalar. We special case lowering
8148 // for scalars so that we can more effectively fold with loads.
8149 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8150 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8151 V = V.getOperand(BroadcastIdx);
8153 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8155 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8157 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8158 // We can't broadcast from a vector register w/o AVX2, and we can only
8159 // broadcast from the zero-element of a vector register.
8163 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8166 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8168 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8169 /// support for floating point shuffles but not integer shuffles. These
8170 /// instructions will incur a domain crossing penalty on some chips though so
8171 /// it is better to avoid lowering through this for integer vectors where
8173 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Straight shuffle of a single input vector. Simulate this by using the
8186 // single input as both of the "inputs" to this instruction..
8187 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8189 if (Subtarget->hasAVX()) {
8190 // If we have AVX, we can use VPERMILPS which will allow folding a load
8191 // into the shuffle.
8192 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8193 DAG.getConstant(SHUFPDMask, MVT::i8));
8196 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8197 DAG.getConstant(SHUFPDMask, MVT::i8));
8199 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8200 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8202 // Use dedicated unpack instructions for masks that match their pattern.
8203 if (isShuffleEquivalent(Mask, 0, 2))
8204 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8205 if (isShuffleEquivalent(Mask, 1, 3))
8206 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8208 // If we have a single input, insert that into V1 if we can do so cheaply.
8209 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8210 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8211 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8213 // Try inverting the insertion since for v2 masks it is easy to do and we
8214 // can't reliably sort the mask one way or the other.
8215 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8216 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8217 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8218 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8222 // Try to use one of the special instruction patterns to handle two common
8223 // blend patterns if a zero-blend above didn't work.
8224 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8225 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8226 // We can either use a special instruction to load over the low double or
8227 // to move just the low double.
8229 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8231 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8233 if (Subtarget->hasSSE41())
8234 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8238 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8239 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8240 DAG.getConstant(SHUFPDMask, MVT::i8));
8243 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8245 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8246 /// the integer unit to minimize domain crossing penalties. However, for blends
8247 /// it falls back to the floating point shuffle operation with appropriate bit
8249 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8250 const X86Subtarget *Subtarget,
8251 SelectionDAG &DAG) {
8253 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8254 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8255 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8256 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8257 ArrayRef<int> Mask = SVOp->getMask();
8258 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8260 if (isSingleInputShuffleMask(Mask)) {
8261 // Check for being able to broadcast a single element.
8262 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8263 Mask, Subtarget, DAG))
8266 // Straight shuffle of a single input vector. For everything from SSE2
8267 // onward this has a single fast instruction with no scary immediates.
8268 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8269 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8270 int WidenedMask[4] = {
8271 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8272 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8274 ISD::BITCAST, DL, MVT::v2i64,
8275 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8276 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8279 // Try to use byte shift instructions.
8280 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8281 DL, MVT::v2i64, V1, V2, Mask, DAG))
8284 // If we have a single input from V2 insert that into V1 if we can do so
8286 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8287 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8288 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8290 // Try inverting the insertion since for v2 masks it is easy to do and we
8291 // can't reliably sort the mask one way or the other.
8292 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8293 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8294 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8295 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8299 // Use dedicated unpack instructions for masks that match their pattern.
8300 if (isShuffleEquivalent(Mask, 0, 2))
8301 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8302 if (isShuffleEquivalent(Mask, 1, 3))
8303 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8305 if (Subtarget->hasSSE41())
8306 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8310 // Try to use byte rotation instructions.
8311 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8312 if (Subtarget->hasSSSE3())
8313 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8314 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8317 // We implement this with SHUFPD which is pretty lame because it will likely
8318 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8319 // However, all the alternatives are still more cycles and newer chips don't
8320 // have this problem. It would be really nice if x86 had better shuffles here.
8321 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8322 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8323 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8324 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8327 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8329 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8330 /// It makes no assumptions about whether this is the *best* lowering, it simply
8332 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8333 ArrayRef<int> Mask, SDValue V1,
8334 SDValue V2, SelectionDAG &DAG) {
8335 SDValue LowV = V1, HighV = V2;
8336 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8339 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8341 if (NumV2Elements == 1) {
8343 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8346 // Compute the index adjacent to V2Index and in the same half by toggling
8348 int V2AdjIndex = V2Index ^ 1;
8350 if (Mask[V2AdjIndex] == -1) {
8351 // Handles all the cases where we have a single V2 element and an undef.
8352 // This will only ever happen in the high lanes because we commute the
8353 // vector otherwise.
8355 std::swap(LowV, HighV);
8356 NewMask[V2Index] -= 4;
8358 // Handle the case where the V2 element ends up adjacent to a V1 element.
8359 // To make this work, blend them together as the first step.
8360 int V1Index = V2AdjIndex;
8361 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8362 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8363 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8365 // Now proceed to reconstruct the final blend as we have the necessary
8366 // high or low half formed.
8373 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8374 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8376 } else if (NumV2Elements == 2) {
8377 if (Mask[0] < 4 && Mask[1] < 4) {
8378 // Handle the easy case where we have V1 in the low lanes and V2 in the
8382 } else if (Mask[2] < 4 && Mask[3] < 4) {
8383 // We also handle the reversed case because this utility may get called
8384 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8385 // arrange things in the right direction.
8391 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8392 // trying to place elements directly, just blend them and set up the final
8393 // shuffle to place them.
8395 // The first two blend mask elements are for V1, the second two are for
8397 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8398 Mask[2] < 4 ? Mask[2] : Mask[3],
8399 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8400 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8401 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8402 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8404 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8407 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8408 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8409 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8410 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8413 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8414 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8417 /// \brief Lower 4-lane 32-bit floating point shuffles.
8419 /// Uses instructions exclusively from the floating point unit to minimize
8420 /// domain crossing penalties, as these are sufficient to implement all v4f32
8422 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8423 const X86Subtarget *Subtarget,
8424 SelectionDAG &DAG) {
8426 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8427 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8428 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8430 ArrayRef<int> Mask = SVOp->getMask();
8431 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8434 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8436 if (NumV2Elements == 0) {
8437 // Check for being able to broadcast a single element.
8438 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8439 Mask, Subtarget, DAG))
8442 if (Subtarget->hasAVX()) {
8443 // If we have AVX, we can use VPERMILPS which will allow folding a load
8444 // into the shuffle.
8445 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8446 getV4X86ShuffleImm8ForMask(Mask, DAG));
8449 // Otherwise, use a straight shuffle of a single input vector. We pass the
8450 // input vector to both operands to simulate this with a SHUFPS.
8451 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8452 getV4X86ShuffleImm8ForMask(Mask, DAG));
8455 // Use dedicated unpack instructions for masks that match their pattern.
8456 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8457 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8458 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8459 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8461 // There are special ways we can lower some single-element blends. However, we
8462 // have custom ways we can lower more complex single-element blends below that
8463 // we defer to if both this and BLENDPS fail to match, so restrict this to
8464 // when the V2 input is targeting element 0 of the mask -- that is the fast
8466 if (NumV2Elements == 1 && Mask[0] >= 4)
8467 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8468 Mask, Subtarget, DAG))
8471 if (Subtarget->hasSSE41())
8472 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8476 // Check for whether we can use INSERTPS to perform the blend. We only use
8477 // INSERTPS when the V1 elements are already in the correct locations
8478 // because otherwise we can just always use two SHUFPS instructions which
8479 // are much smaller to encode than a SHUFPS and an INSERTPS.
8480 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8482 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8485 // When using INSERTPS we can zero any lane of the destination. Collect
8486 // the zero inputs into a mask and drop them from the lanes of V1 which
8487 // actually need to be present as inputs to the INSERTPS.
8488 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8490 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8491 bool InsertNeedsShuffle = false;
8493 for (int i = 0; i < 4; ++i)
8497 } else if (Mask[i] != i) {
8498 InsertNeedsShuffle = true;
8503 // We don't want to use INSERTPS or other insertion techniques if it will
8504 // require shuffling anyways.
8505 if (!InsertNeedsShuffle) {
8506 // If all of V1 is zeroable, replace it with undef.
8507 if ((ZMask | 1 << V2Index) == 0xF)
8508 V1 = DAG.getUNDEF(MVT::v4f32);
8510 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8511 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8513 // Insert the V2 element into the desired position.
8514 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8515 DAG.getConstant(InsertPSMask, MVT::i8));
8519 // Otherwise fall back to a SHUFPS lowering strategy.
8520 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8523 /// \brief Lower 4-lane i32 vector shuffles.
8525 /// We try to handle these with integer-domain shuffles where we can, but for
8526 /// blends we use the floating point domain blend instructions.
8527 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8528 const X86Subtarget *Subtarget,
8529 SelectionDAG &DAG) {
8531 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8532 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8533 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8534 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8535 ArrayRef<int> Mask = SVOp->getMask();
8536 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8538 // Whenever we can lower this as a zext, that instruction is strictly faster
8539 // than any alternative. It also allows us to fold memory operands into the
8540 // shuffle in many cases.
8541 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8542 Mask, Subtarget, DAG))
8546 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8548 if (NumV2Elements == 0) {
8549 // Check for being able to broadcast a single element.
8550 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8551 Mask, Subtarget, DAG))
8554 // Straight shuffle of a single input vector. For everything from SSE2
8555 // onward this has a single fast instruction with no scary immediates.
8556 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8557 // but we aren't actually going to use the UNPCK instruction because doing
8558 // so prevents folding a load into this instruction or making a copy.
8559 const int UnpackLoMask[] = {0, 0, 1, 1};
8560 const int UnpackHiMask[] = {2, 2, 3, 3};
8561 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8562 Mask = UnpackLoMask;
8563 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8564 Mask = UnpackHiMask;
8566 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8567 getV4X86ShuffleImm8ForMask(Mask, DAG));
8570 // Try to use byte shift instructions.
8571 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8572 DL, MVT::v4i32, V1, V2, Mask, DAG))
8575 // There are special ways we can lower some single-element blends.
8576 if (NumV2Elements == 1)
8577 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8578 Mask, Subtarget, DAG))
8581 // Use dedicated unpack instructions for masks that match their pattern.
8582 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8583 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8584 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8585 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8587 if (Subtarget->hasSSE41())
8588 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8592 // Try to use byte rotation instructions.
8593 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8594 if (Subtarget->hasSSSE3())
8595 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8596 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8599 // We implement this with SHUFPS because it can blend from two vectors.
8600 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8601 // up the inputs, bypassing domain shift penalties that we would encur if we
8602 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8604 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8605 DAG.getVectorShuffle(
8607 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8608 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8611 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8612 /// shuffle lowering, and the most complex part.
8614 /// The lowering strategy is to try to form pairs of input lanes which are
8615 /// targeted at the same half of the final vector, and then use a dword shuffle
8616 /// to place them onto the right half, and finally unpack the paired lanes into
8617 /// their final position.
8619 /// The exact breakdown of how to form these dword pairs and align them on the
8620 /// correct sides is really tricky. See the comments within the function for
8621 /// more of the details.
8622 static SDValue lowerV8I16SingleInputVectorShuffle(
8623 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8624 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8625 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8626 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8627 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8629 SmallVector<int, 4> LoInputs;
8630 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8631 [](int M) { return M >= 0; });
8632 std::sort(LoInputs.begin(), LoInputs.end());
8633 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8634 SmallVector<int, 4> HiInputs;
8635 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8636 [](int M) { return M >= 0; });
8637 std::sort(HiInputs.begin(), HiInputs.end());
8638 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8640 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8641 int NumHToL = LoInputs.size() - NumLToL;
8643 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8644 int NumHToH = HiInputs.size() - NumLToH;
8645 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8646 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8647 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8648 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8650 // Check for being able to broadcast a single element.
8651 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8652 Mask, Subtarget, DAG))
8655 // Try to use byte shift instructions.
8656 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8657 DL, MVT::v8i16, V, V, Mask, DAG))
8660 // Use dedicated unpack instructions for masks that match their pattern.
8661 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8662 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8663 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8664 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8666 // Try to use byte rotation instructions.
8667 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8668 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8671 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8672 // such inputs we can swap two of the dwords across the half mark and end up
8673 // with <=2 inputs to each half in each half. Once there, we can fall through
8674 // to the generic code below. For example:
8676 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8677 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8679 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8680 // and an existing 2-into-2 on the other half. In this case we may have to
8681 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8682 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8683 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8684 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8685 // half than the one we target for fixing) will be fixed when we re-enter this
8686 // path. We will also combine away any sequence of PSHUFD instructions that
8687 // result into a single instruction. Here is an example of the tricky case:
8689 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8690 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8692 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8694 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8695 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8697 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8698 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8700 // The result is fine to be handled by the generic logic.
8701 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8702 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8703 int AOffset, int BOffset) {
8704 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8705 "Must call this with A having 3 or 1 inputs from the A half.");
8706 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8707 "Must call this with B having 1 or 3 inputs from the B half.");
8708 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8709 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8711 // Compute the index of dword with only one word among the three inputs in
8712 // a half by taking the sum of the half with three inputs and subtracting
8713 // the sum of the actual three inputs. The difference is the remaining
8716 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8717 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8718 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8719 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8720 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8721 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8722 int TripleNonInputIdx =
8723 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8724 TripleDWord = TripleNonInputIdx / 2;
8726 // We use xor with one to compute the adjacent DWord to whichever one the
8728 OneInputDWord = (OneInput / 2) ^ 1;
8730 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8731 // and BToA inputs. If there is also such a problem with the BToB and AToB
8732 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8733 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8734 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8735 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8736 // Compute how many inputs will be flipped by swapping these DWords. We
8738 // to balance this to ensure we don't form a 3-1 shuffle in the other
8740 int NumFlippedAToBInputs =
8741 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8742 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8743 int NumFlippedBToBInputs =
8744 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8745 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8746 if ((NumFlippedAToBInputs == 1 &&
8747 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8748 (NumFlippedBToBInputs == 1 &&
8749 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8750 // We choose whether to fix the A half or B half based on whether that
8751 // half has zero flipped inputs. At zero, we may not be able to fix it
8752 // with that half. We also bias towards fixing the B half because that
8753 // will more commonly be the high half, and we have to bias one way.
8754 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8755 ArrayRef<int> Inputs) {
8756 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8757 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8758 PinnedIdx ^ 1) != Inputs.end();
8759 // Determine whether the free index is in the flipped dword or the
8760 // unflipped dword based on where the pinned index is. We use this bit
8761 // in an xor to conditionally select the adjacent dword.
8762 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8763 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8764 FixFreeIdx) != Inputs.end();
8765 if (IsFixIdxInput == IsFixFreeIdxInput)
8767 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8768 FixFreeIdx) != Inputs.end();
8769 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8770 "We need to be changing the number of flipped inputs!");
8771 int PSHUFHalfMask[] = {0, 1, 2, 3};
8772 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8773 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8775 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8778 if (M != -1 && M == FixIdx)
8780 else if (M != -1 && M == FixFreeIdx)
8783 if (NumFlippedBToBInputs != 0) {
8785 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8786 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8788 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8790 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8791 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8796 int PSHUFDMask[] = {0, 1, 2, 3};
8797 PSHUFDMask[ADWord] = BDWord;
8798 PSHUFDMask[BDWord] = ADWord;
8799 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8800 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8801 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8802 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8804 // Adjust the mask to match the new locations of A and B.
8806 if (M != -1 && M/2 == ADWord)
8807 M = 2 * BDWord + M % 2;
8808 else if (M != -1 && M/2 == BDWord)
8809 M = 2 * ADWord + M % 2;
8811 // Recurse back into this routine to re-compute state now that this isn't
8812 // a 3 and 1 problem.
8813 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8816 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8817 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8818 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8819 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8821 // At this point there are at most two inputs to the low and high halves from
8822 // each half. That means the inputs can always be grouped into dwords and
8823 // those dwords can then be moved to the correct half with a dword shuffle.
8824 // We use at most one low and one high word shuffle to collect these paired
8825 // inputs into dwords, and finally a dword shuffle to place them.
8826 int PSHUFLMask[4] = {-1, -1, -1, -1};
8827 int PSHUFHMask[4] = {-1, -1, -1, -1};
8828 int PSHUFDMask[4] = {-1, -1, -1, -1};
8830 // First fix the masks for all the inputs that are staying in their
8831 // original halves. This will then dictate the targets of the cross-half
8833 auto fixInPlaceInputs =
8834 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8835 MutableArrayRef<int> SourceHalfMask,
8836 MutableArrayRef<int> HalfMask, int HalfOffset) {
8837 if (InPlaceInputs.empty())
8839 if (InPlaceInputs.size() == 1) {
8840 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8841 InPlaceInputs[0] - HalfOffset;
8842 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8845 if (IncomingInputs.empty()) {
8846 // Just fix all of the in place inputs.
8847 for (int Input : InPlaceInputs) {
8848 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8849 PSHUFDMask[Input / 2] = Input / 2;
8854 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8855 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8856 InPlaceInputs[0] - HalfOffset;
8857 // Put the second input next to the first so that they are packed into
8858 // a dword. We find the adjacent index by toggling the low bit.
8859 int AdjIndex = InPlaceInputs[0] ^ 1;
8860 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8861 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8862 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8864 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8865 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8867 // Now gather the cross-half inputs and place them into a free dword of
8868 // their target half.
8869 // FIXME: This operation could almost certainly be simplified dramatically to
8870 // look more like the 3-1 fixing operation.
8871 auto moveInputsToRightHalf = [&PSHUFDMask](
8872 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8873 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8874 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8876 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8877 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8879 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8881 int LowWord = Word & ~1;
8882 int HighWord = Word | 1;
8883 return isWordClobbered(SourceHalfMask, LowWord) ||
8884 isWordClobbered(SourceHalfMask, HighWord);
8887 if (IncomingInputs.empty())
8890 if (ExistingInputs.empty()) {
8891 // Map any dwords with inputs from them into the right half.
8892 for (int Input : IncomingInputs) {
8893 // If the source half mask maps over the inputs, turn those into
8894 // swaps and use the swapped lane.
8895 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8896 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8897 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8898 Input - SourceOffset;
8899 // We have to swap the uses in our half mask in one sweep.
8900 for (int &M : HalfMask)
8901 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8903 else if (M == Input)
8904 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8906 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8907 Input - SourceOffset &&
8908 "Previous placement doesn't match!");
8910 // Note that this correctly re-maps both when we do a swap and when
8911 // we observe the other side of the swap above. We rely on that to
8912 // avoid swapping the members of the input list directly.
8913 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8916 // Map the input's dword into the correct half.
8917 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8918 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8920 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8922 "Previous placement doesn't match!");
8925 // And just directly shift any other-half mask elements to be same-half
8926 // as we will have mirrored the dword containing the element into the
8927 // same position within that half.
8928 for (int &M : HalfMask)
8929 if (M >= SourceOffset && M < SourceOffset + 4) {
8930 M = M - SourceOffset + DestOffset;
8931 assert(M >= 0 && "This should never wrap below zero!");
8936 // Ensure we have the input in a viable dword of its current half. This
8937 // is particularly tricky because the original position may be clobbered
8938 // by inputs being moved and *staying* in that half.
8939 if (IncomingInputs.size() == 1) {
8940 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8941 int InputFixed = std::find(std::begin(SourceHalfMask),
8942 std::end(SourceHalfMask), -1) -
8943 std::begin(SourceHalfMask) + SourceOffset;
8944 SourceHalfMask[InputFixed - SourceOffset] =
8945 IncomingInputs[0] - SourceOffset;
8946 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8948 IncomingInputs[0] = InputFixed;
8950 } else if (IncomingInputs.size() == 2) {
8951 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8952 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8953 // We have two non-adjacent or clobbered inputs we need to extract from
8954 // the source half. To do this, we need to map them into some adjacent
8955 // dword slot in the source mask.
8956 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8957 IncomingInputs[1] - SourceOffset};
8959 // If there is a free slot in the source half mask adjacent to one of
8960 // the inputs, place the other input in it. We use (Index XOR 1) to
8961 // compute an adjacent index.
8962 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8963 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8964 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8965 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8966 InputsFixed[1] = InputsFixed[0] ^ 1;
8967 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8968 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8969 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8970 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8971 InputsFixed[0] = InputsFixed[1] ^ 1;
8972 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8973 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8974 // The two inputs are in the same DWord but it is clobbered and the
8975 // adjacent DWord isn't used at all. Move both inputs to the free
8977 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8978 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8979 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8980 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8982 // The only way we hit this point is if there is no clobbering
8983 // (because there are no off-half inputs to this half) and there is no
8984 // free slot adjacent to one of the inputs. In this case, we have to
8985 // swap an input with a non-input.
8986 for (int i = 0; i < 4; ++i)
8987 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8988 "We can't handle any clobbers here!");
8989 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8990 "Cannot have adjacent inputs here!");
8992 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8993 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8995 // We also have to update the final source mask in this case because
8996 // it may need to undo the above swap.
8997 for (int &M : FinalSourceHalfMask)
8998 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8999 M = InputsFixed[1] + SourceOffset;
9000 else if (M == InputsFixed[1] + SourceOffset)
9001 M = (InputsFixed[0] ^ 1) + SourceOffset;
9003 InputsFixed[1] = InputsFixed[0] ^ 1;
9006 // Point everything at the fixed inputs.
9007 for (int &M : HalfMask)
9008 if (M == IncomingInputs[0])
9009 M = InputsFixed[0] + SourceOffset;
9010 else if (M == IncomingInputs[1])
9011 M = InputsFixed[1] + SourceOffset;
9013 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9014 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9017 llvm_unreachable("Unhandled input size!");
9020 // Now hoist the DWord down to the right half.
9021 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9022 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9023 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9024 for (int &M : HalfMask)
9025 for (int Input : IncomingInputs)
9027 M = FreeDWord * 2 + Input % 2;
9029 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9030 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9031 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9032 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9034 // Now enact all the shuffles we've computed to move the inputs into their
9036 if (!isNoopShuffleMask(PSHUFLMask))
9037 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9038 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9039 if (!isNoopShuffleMask(PSHUFHMask))
9040 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9041 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9042 if (!isNoopShuffleMask(PSHUFDMask))
9043 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9044 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9045 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9046 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9048 // At this point, each half should contain all its inputs, and we can then
9049 // just shuffle them into their final position.
9050 assert(std::count_if(LoMask.begin(), LoMask.end(),
9051 [](int M) { return M >= 4; }) == 0 &&
9052 "Failed to lift all the high half inputs to the low mask!");
9053 assert(std::count_if(HiMask.begin(), HiMask.end(),
9054 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9055 "Failed to lift all the low half inputs to the high mask!");
9057 // Do a half shuffle for the low mask.
9058 if (!isNoopShuffleMask(LoMask))
9059 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9060 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9062 // Do a half shuffle with the high mask after shifting its values down.
9063 for (int &M : HiMask)
9066 if (!isNoopShuffleMask(HiMask))
9067 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9068 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9073 /// \brief Detect whether the mask pattern should be lowered through
9076 /// This essentially tests whether viewing the mask as an interleaving of two
9077 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9078 /// lowering it through interleaving is a significantly better strategy.
9079 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9080 int NumEvenInputs[2] = {0, 0};
9081 int NumOddInputs[2] = {0, 0};
9082 int NumLoInputs[2] = {0, 0};
9083 int NumHiInputs[2] = {0, 0};
9084 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9088 int InputIdx = Mask[i] >= Size;
9091 ++NumLoInputs[InputIdx];
9093 ++NumHiInputs[InputIdx];
9096 ++NumEvenInputs[InputIdx];
9098 ++NumOddInputs[InputIdx];
9101 // The minimum number of cross-input results for both the interleaved and
9102 // split cases. If interleaving results in fewer cross-input results, return
9104 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9105 NumEvenInputs[0] + NumOddInputs[1]);
9106 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9107 NumLoInputs[0] + NumHiInputs[1]);
9108 return InterleavedCrosses < SplitCrosses;
9111 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9113 /// This strategy only works when the inputs from each vector fit into a single
9114 /// half of that vector, and generally there are not so many inputs as to leave
9115 /// the in-place shuffles required highly constrained (and thus expensive). It
9116 /// shifts all the inputs into a single side of both input vectors and then
9117 /// uses an unpack to interleave these inputs in a single vector. At that
9118 /// point, we will fall back on the generic single input shuffle lowering.
9119 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9121 MutableArrayRef<int> Mask,
9122 const X86Subtarget *Subtarget,
9123 SelectionDAG &DAG) {
9124 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9125 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9126 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9127 for (int i = 0; i < 8; ++i)
9128 if (Mask[i] >= 0 && Mask[i] < 4)
9129 LoV1Inputs.push_back(i);
9130 else if (Mask[i] >= 4 && Mask[i] < 8)
9131 HiV1Inputs.push_back(i);
9132 else if (Mask[i] >= 8 && Mask[i] < 12)
9133 LoV2Inputs.push_back(i);
9134 else if (Mask[i] >= 12)
9135 HiV2Inputs.push_back(i);
9137 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9138 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9141 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9142 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9143 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9145 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9146 HiV1Inputs.size() + HiV2Inputs.size();
9148 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9149 ArrayRef<int> HiInputs, bool MoveToLo,
9151 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9152 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9153 if (BadInputs.empty())
9156 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9157 int MoveOffset = MoveToLo ? 0 : 4;
9159 if (GoodInputs.empty()) {
9160 for (int BadInput : BadInputs) {
9161 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9162 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9165 if (GoodInputs.size() == 2) {
9166 // If the low inputs are spread across two dwords, pack them into
9168 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9169 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9170 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9171 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9173 // Otherwise pin the good inputs.
9174 for (int GoodInput : GoodInputs)
9175 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9178 if (BadInputs.size() == 2) {
9179 // If we have two bad inputs then there may be either one or two good
9180 // inputs fixed in place. Find a fixed input, and then find the *other*
9181 // two adjacent indices by using modular arithmetic.
9183 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9184 [](int M) { return M >= 0; }) -
9185 std::begin(MoveMask);
9187 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9188 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9189 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9190 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9191 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9192 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9193 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9195 assert(BadInputs.size() == 1 && "All sizes handled");
9196 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9197 std::end(MoveMask), -1) -
9198 std::begin(MoveMask);
9199 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9200 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9204 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9207 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9209 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9212 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9213 // cross-half traffic in the final shuffle.
9215 // Munge the mask to be a single-input mask after the unpack merges the
9219 M = 2 * (M % 4) + (M / 8);
9221 return DAG.getVectorShuffle(
9222 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9223 DL, MVT::v8i16, V1, V2),
9224 DAG.getUNDEF(MVT::v8i16), Mask);
9227 /// \brief Generic lowering of 8-lane i16 shuffles.
9229 /// This handles both single-input shuffles and combined shuffle/blends with
9230 /// two inputs. The single input shuffles are immediately delegated to
9231 /// a dedicated lowering routine.
9233 /// The blends are lowered in one of three fundamental ways. If there are few
9234 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9235 /// of the input is significantly cheaper when lowered as an interleaving of
9236 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9237 /// halves of the inputs separately (making them have relatively few inputs)
9238 /// and then concatenate them.
9239 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9240 const X86Subtarget *Subtarget,
9241 SelectionDAG &DAG) {
9243 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9244 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9245 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9247 ArrayRef<int> OrigMask = SVOp->getMask();
9248 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9249 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9250 MutableArrayRef<int> Mask(MaskStorage);
9252 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9254 // Whenever we can lower this as a zext, that instruction is strictly faster
9255 // than any alternative.
9256 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9257 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9260 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9261 auto isV2 = [](int M) { return M >= 8; };
9263 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9264 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9266 if (NumV2Inputs == 0)
9267 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9269 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9270 "to be V1-input shuffles.");
9272 // Try to use byte shift instructions.
9273 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9274 DL, MVT::v8i16, V1, V2, Mask, DAG))
9277 // There are special ways we can lower some single-element blends.
9278 if (NumV2Inputs == 1)
9279 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9280 Mask, Subtarget, DAG))
9283 // Use dedicated unpack instructions for masks that match their pattern.
9284 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9285 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9286 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9287 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9289 if (Subtarget->hasSSE41())
9290 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9294 // Try to use byte rotation instructions.
9295 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9296 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9299 if (NumV1Inputs + NumV2Inputs <= 4)
9300 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9302 // Check whether an interleaving lowering is likely to be more efficient.
9303 // This isn't perfect but it is a strong heuristic that tends to work well on
9304 // the kinds of shuffles that show up in practice.
9306 // FIXME: Handle 1x, 2x, and 4x interleaving.
9307 if (shouldLowerAsInterleaving(Mask)) {
9308 // FIXME: Figure out whether we should pack these into the low or high
9311 int EMask[8], OMask[8];
9312 for (int i = 0; i < 4; ++i) {
9313 EMask[i] = Mask[2*i];
9314 OMask[i] = Mask[2*i + 1];
9319 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9320 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9322 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9325 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9326 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9328 for (int i = 0; i < 4; ++i) {
9329 LoBlendMask[i] = Mask[i];
9330 HiBlendMask[i] = Mask[i + 4];
9333 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9334 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9335 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9336 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9338 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9339 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9342 /// \brief Check whether a compaction lowering can be done by dropping even
9343 /// elements and compute how many times even elements must be dropped.
9345 /// This handles shuffles which take every Nth element where N is a power of
9346 /// two. Example shuffle masks:
9348 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9349 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9350 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9351 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9352 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9353 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9355 /// Any of these lanes can of course be undef.
9357 /// This routine only supports N <= 3.
9358 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9361 /// \returns N above, or the number of times even elements must be dropped if
9362 /// there is such a number. Otherwise returns zero.
9363 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9364 // Figure out whether we're looping over two inputs or just one.
9365 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9367 // The modulus for the shuffle vector entries is based on whether this is
9368 // a single input or not.
9369 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9370 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9371 "We should only be called with masks with a power-of-2 size!");
9373 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9375 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9376 // and 2^3 simultaneously. This is because we may have ambiguity with
9377 // partially undef inputs.
9378 bool ViableForN[3] = {true, true, true};
9380 for (int i = 0, e = Mask.size(); i < e; ++i) {
9381 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9386 bool IsAnyViable = false;
9387 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9388 if (ViableForN[j]) {
9391 // The shuffle mask must be equal to (i * 2^N) % M.
9392 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9395 ViableForN[j] = false;
9397 // Early exit if we exhaust the possible powers of two.
9402 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9406 // Return 0 as there is no viable power of two.
9410 /// \brief Generic lowering of v16i8 shuffles.
9412 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9413 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9414 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9415 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9417 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9418 const X86Subtarget *Subtarget,
9419 SelectionDAG &DAG) {
9421 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9422 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9423 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9424 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9425 ArrayRef<int> OrigMask = SVOp->getMask();
9426 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9428 // Try to use byte shift instructions.
9429 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9430 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9433 // Try to use byte rotation instructions.
9434 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9435 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9438 // Try to use a zext lowering.
9439 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9440 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9443 int MaskStorage[16] = {
9444 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9445 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9446 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9447 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9448 MutableArrayRef<int> Mask(MaskStorage);
9449 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9450 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9453 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9455 // For single-input shuffles, there are some nicer lowering tricks we can use.
9456 if (NumV2Elements == 0) {
9457 // Check for being able to broadcast a single element.
9458 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9459 Mask, Subtarget, DAG))
9462 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9463 // Notably, this handles splat and partial-splat shuffles more efficiently.
9464 // However, it only makes sense if the pre-duplication shuffle simplifies
9465 // things significantly. Currently, this means we need to be able to
9466 // express the pre-duplication shuffle as an i16 shuffle.
9468 // FIXME: We should check for other patterns which can be widened into an
9469 // i16 shuffle as well.
9470 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9471 for (int i = 0; i < 16; i += 2)
9472 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9477 auto tryToWidenViaDuplication = [&]() -> SDValue {
9478 if (!canWidenViaDuplication(Mask))
9480 SmallVector<int, 4> LoInputs;
9481 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9482 [](int M) { return M >= 0 && M < 8; });
9483 std::sort(LoInputs.begin(), LoInputs.end());
9484 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9486 SmallVector<int, 4> HiInputs;
9487 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9488 [](int M) { return M >= 8; });
9489 std::sort(HiInputs.begin(), HiInputs.end());
9490 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9493 bool TargetLo = LoInputs.size() >= HiInputs.size();
9494 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9495 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9497 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9498 SmallDenseMap<int, int, 8> LaneMap;
9499 for (int I : InPlaceInputs) {
9500 PreDupI16Shuffle[I/2] = I/2;
9503 int j = TargetLo ? 0 : 4, je = j + 4;
9504 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9505 // Check if j is already a shuffle of this input. This happens when
9506 // there are two adjacent bytes after we move the low one.
9507 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9508 // If we haven't yet mapped the input, search for a slot into which
9510 while (j < je && PreDupI16Shuffle[j] != -1)
9514 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9517 // Map this input with the i16 shuffle.
9518 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9521 // Update the lane map based on the mapping we ended up with.
9522 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9525 ISD::BITCAST, DL, MVT::v16i8,
9526 DAG.getVectorShuffle(MVT::v8i16, DL,
9527 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9528 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9530 // Unpack the bytes to form the i16s that will be shuffled into place.
9531 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9532 MVT::v16i8, V1, V1);
9534 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9535 for (int i = 0; i < 16; ++i)
9536 if (Mask[i] != -1) {
9537 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9538 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9539 if (PostDupI16Shuffle[i / 2] == -1)
9540 PostDupI16Shuffle[i / 2] = MappedMask;
9542 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9543 "Conflicting entrties in the original shuffle!");
9546 ISD::BITCAST, DL, MVT::v16i8,
9547 DAG.getVectorShuffle(MVT::v8i16, DL,
9548 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9549 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9551 if (SDValue V = tryToWidenViaDuplication())
9555 // Check whether an interleaving lowering is likely to be more efficient.
9556 // This isn't perfect but it is a strong heuristic that tends to work well on
9557 // the kinds of shuffles that show up in practice.
9559 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9560 if (shouldLowerAsInterleaving(Mask)) {
9561 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9562 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9564 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9565 return (M >= 8 && M < 16) || M >= 24;
9567 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9568 -1, -1, -1, -1, -1, -1, -1, -1};
9569 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9570 -1, -1, -1, -1, -1, -1, -1, -1};
9571 bool UnpackLo = NumLoHalf >= NumHiHalf;
9572 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9573 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9574 for (int i = 0; i < 8; ++i) {
9575 TargetEMask[i] = Mask[2 * i];
9576 TargetOMask[i] = Mask[2 * i + 1];
9579 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9580 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9582 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9583 MVT::v16i8, Evens, Odds);
9586 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9587 // with PSHUFB. It is important to do this before we attempt to generate any
9588 // blends but after all of the single-input lowerings. If the single input
9589 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9590 // want to preserve that and we can DAG combine any longer sequences into
9591 // a PSHUFB in the end. But once we start blending from multiple inputs,
9592 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9593 // and there are *very* few patterns that would actually be faster than the
9594 // PSHUFB approach because of its ability to zero lanes.
9596 // FIXME: The only exceptions to the above are blends which are exact
9597 // interleavings with direct instructions supporting them. We currently don't
9598 // handle those well here.
9599 if (Subtarget->hasSSSE3()) {
9602 for (int i = 0; i < 16; ++i)
9603 if (Mask[i] == -1) {
9604 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9606 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9608 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9610 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9611 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9612 if (isSingleInputShuffleMask(Mask))
9613 return V1; // Single inputs are easy.
9615 // Otherwise, blend the two.
9616 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9617 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9618 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9621 // There are special ways we can lower some single-element blends.
9622 if (NumV2Elements == 1)
9623 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9624 Mask, Subtarget, DAG))
9627 // Check whether a compaction lowering can be done. This handles shuffles
9628 // which take every Nth element for some even N. See the helper function for
9631 // We special case these as they can be particularly efficiently handled with
9632 // the PACKUSB instruction on x86 and they show up in common patterns of
9633 // rearranging bytes to truncate wide elements.
9634 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9635 // NumEvenDrops is the power of two stride of the elements. Another way of
9636 // thinking about it is that we need to drop the even elements this many
9637 // times to get the original input.
9638 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9640 // First we need to zero all the dropped bytes.
9641 assert(NumEvenDrops <= 3 &&
9642 "No support for dropping even elements more than 3 times.");
9643 // We use the mask type to pick which bytes are preserved based on how many
9644 // elements are dropped.
9645 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9646 SDValue ByteClearMask =
9647 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9648 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9649 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9651 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9653 // Now pack things back together.
9654 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9655 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9656 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9657 for (int i = 1; i < NumEvenDrops; ++i) {
9658 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9659 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9665 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9666 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9667 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9668 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9670 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9671 MutableArrayRef<int> V1HalfBlendMask,
9672 MutableArrayRef<int> V2HalfBlendMask) {
9673 for (int i = 0; i < 8; ++i)
9674 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9675 V1HalfBlendMask[i] = HalfMask[i];
9677 } else if (HalfMask[i] >= 16) {
9678 V2HalfBlendMask[i] = HalfMask[i] - 16;
9679 HalfMask[i] = i + 8;
9682 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9683 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9685 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9687 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9688 MutableArrayRef<int> HiBlendMask) {
9690 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9691 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9693 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9694 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9695 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9696 [](int M) { return M >= 0 && M % 2 == 1; })) {
9697 // Use a mask to drop the high bytes.
9698 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9699 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9700 DAG.getConstant(0x00FF, MVT::v8i16));
9702 // This will be a single vector shuffle instead of a blend so nuke V2.
9703 V2 = DAG.getUNDEF(MVT::v8i16);
9705 // Squash the masks to point directly into V1.
9706 for (int &M : LoBlendMask)
9709 for (int &M : HiBlendMask)
9713 // Otherwise just unpack the low half of V into V1 and the high half into
9714 // V2 so that we can blend them as i16s.
9715 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9716 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9717 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9718 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9721 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9722 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9723 return std::make_pair(BlendedLo, BlendedHi);
9725 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9726 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9727 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9729 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9730 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9732 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9735 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9737 /// This routine breaks down the specific type of 128-bit shuffle and
9738 /// dispatches to the lowering routines accordingly.
9739 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9740 MVT VT, const X86Subtarget *Subtarget,
9741 SelectionDAG &DAG) {
9742 switch (VT.SimpleTy) {
9744 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9746 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9748 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9750 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9752 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9754 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9757 llvm_unreachable("Unimplemented!");
9761 /// \brief Helper function to test whether a shuffle mask could be
9762 /// simplified by widening the elements being shuffled.
9764 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9765 /// leaves it in an unspecified state.
9767 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9768 /// shuffle masks. The latter have the special property of a '-2' representing
9769 /// a zero-ed lane of a vector.
9770 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9771 SmallVectorImpl<int> &WidenedMask) {
9772 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9773 // If both elements are undef, its trivial.
9774 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9775 WidenedMask.push_back(SM_SentinelUndef);
9779 // Check for an undef mask and a mask value properly aligned to fit with
9780 // a pair of values. If we find such a case, use the non-undef mask's value.
9781 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9782 WidenedMask.push_back(Mask[i + 1] / 2);
9785 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9786 WidenedMask.push_back(Mask[i] / 2);
9790 // When zeroing, we need to spread the zeroing across both lanes to widen.
9791 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9792 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9793 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9794 WidenedMask.push_back(SM_SentinelZero);
9800 // Finally check if the two mask values are adjacent and aligned with
9802 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9803 WidenedMask.push_back(Mask[i] / 2);
9807 // Otherwise we can't safely widen the elements used in this shuffle.
9810 assert(WidenedMask.size() == Mask.size() / 2 &&
9811 "Incorrect size of mask after widening the elements!");
9816 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9818 /// This routine just extracts two subvectors, shuffles them independently, and
9819 /// then concatenates them back together. This should work effectively with all
9820 /// AVX vector shuffle types.
9821 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9822 SDValue V2, ArrayRef<int> Mask,
9823 SelectionDAG &DAG) {
9824 assert(VT.getSizeInBits() >= 256 &&
9825 "Only for 256-bit or wider vector shuffles!");
9826 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9827 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9829 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9830 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9832 int NumElements = VT.getVectorNumElements();
9833 int SplitNumElements = NumElements / 2;
9834 MVT ScalarVT = VT.getScalarType();
9835 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9837 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9838 DAG.getIntPtrConstant(0));
9839 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9840 DAG.getIntPtrConstant(SplitNumElements));
9841 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9842 DAG.getIntPtrConstant(0));
9843 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9844 DAG.getIntPtrConstant(SplitNumElements));
9846 // Now create two 4-way blends of these half-width vectors.
9847 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9848 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9849 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9850 for (int i = 0; i < SplitNumElements; ++i) {
9851 int M = HalfMask[i];
9852 if (M >= NumElements) {
9853 if (M >= NumElements + SplitNumElements)
9857 V2BlendMask.push_back(M - NumElements);
9858 V1BlendMask.push_back(-1);
9859 BlendMask.push_back(SplitNumElements + i);
9860 } else if (M >= 0) {
9861 if (M >= SplitNumElements)
9865 V2BlendMask.push_back(-1);
9866 V1BlendMask.push_back(M);
9867 BlendMask.push_back(i);
9869 V2BlendMask.push_back(-1);
9870 V1BlendMask.push_back(-1);
9871 BlendMask.push_back(-1);
9875 // Because the lowering happens after all combining takes place, we need to
9876 // manually combine these blend masks as much as possible so that we create
9877 // a minimal number of high-level vector shuffle nodes.
9879 // First try just blending the halves of V1 or V2.
9880 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9881 return DAG.getUNDEF(SplitVT);
9882 if (!UseLoV2 && !UseHiV2)
9883 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9884 if (!UseLoV1 && !UseHiV1)
9885 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9887 SDValue V1Blend, V2Blend;
9888 if (UseLoV1 && UseHiV1) {
9890 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9892 // We only use half of V1 so map the usage down into the final blend mask.
9893 V1Blend = UseLoV1 ? LoV1 : HiV1;
9894 for (int i = 0; i < SplitNumElements; ++i)
9895 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9896 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9898 if (UseLoV2 && UseHiV2) {
9900 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9902 // We only use half of V2 so map the usage down into the final blend mask.
9903 V2Blend = UseLoV2 ? LoV2 : HiV2;
9904 for (int i = 0; i < SplitNumElements; ++i)
9905 if (BlendMask[i] >= SplitNumElements)
9906 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9908 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9910 SDValue Lo = HalfBlend(LoMask);
9911 SDValue Hi = HalfBlend(HiMask);
9912 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9915 /// \brief Either split a vector in halves or decompose the shuffles and the
9918 /// This is provided as a good fallback for many lowerings of non-single-input
9919 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9920 /// between splitting the shuffle into 128-bit components and stitching those
9921 /// back together vs. extracting the single-input shuffles and blending those
9923 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9924 SDValue V2, ArrayRef<int> Mask,
9925 SelectionDAG &DAG) {
9926 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9927 "lower single-input shuffles as it "
9928 "could then recurse on itself.");
9929 int Size = Mask.size();
9931 // If this can be modeled as a broadcast of two elements followed by a blend,
9932 // prefer that lowering. This is especially important because broadcasts can
9933 // often fold with memory operands.
9934 auto DoBothBroadcast = [&] {
9935 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9938 if (V2BroadcastIdx == -1)
9939 V2BroadcastIdx = M - Size;
9940 else if (M - Size != V2BroadcastIdx)
9942 } else if (M >= 0) {
9943 if (V1BroadcastIdx == -1)
9945 else if (M != V1BroadcastIdx)
9950 if (DoBothBroadcast())
9951 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9954 // If the inputs all stem from a single 128-bit lane of each input, then we
9955 // split them rather than blending because the split will decompose to
9956 // unusually few instructions.
9957 int LaneCount = VT.getSizeInBits() / 128;
9958 int LaneSize = Size / LaneCount;
9959 SmallBitVector LaneInputs[2];
9960 LaneInputs[0].resize(LaneCount, false);
9961 LaneInputs[1].resize(LaneCount, false);
9962 for (int i = 0; i < Size; ++i)
9964 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9965 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9966 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9968 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9969 // that the decomposed single-input shuffles don't end up here.
9970 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9973 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9974 /// a permutation and blend of those lanes.
9976 /// This essentially blends the out-of-lane inputs to each lane into the lane
9977 /// from a permuted copy of the vector. This lowering strategy results in four
9978 /// instructions in the worst case for a single-input cross lane shuffle which
9979 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9980 /// of. Special cases for each particular shuffle pattern should be handled
9981 /// prior to trying this lowering.
9982 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9983 SDValue V1, SDValue V2,
9985 SelectionDAG &DAG) {
9986 // FIXME: This should probably be generalized for 512-bit vectors as well.
9987 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9988 int LaneSize = Mask.size() / 2;
9990 // If there are only inputs from one 128-bit lane, splitting will in fact be
9991 // less expensive. The flags track wether the given lane contains an element
9992 // that crosses to another lane.
9993 bool LaneCrossing[2] = {false, false};
9994 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9995 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9996 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9997 if (!LaneCrossing[0] || !LaneCrossing[1])
9998 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10000 if (isSingleInputShuffleMask(Mask)) {
10001 SmallVector<int, 32> FlippedBlendMask;
10002 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10003 FlippedBlendMask.push_back(
10004 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10006 : Mask[i] % LaneSize +
10007 (i / LaneSize) * LaneSize + Size));
10009 // Flip the vector, and blend the results which should now be in-lane. The
10010 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10011 // 5 for the high source. The value 3 selects the high half of source 2 and
10012 // the value 2 selects the low half of source 2. We only use source 2 to
10013 // allow folding it into a memory operand.
10014 unsigned PERMMask = 3 | 2 << 4;
10015 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10016 V1, DAG.getConstant(PERMMask, MVT::i8));
10017 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10020 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10021 // will be handled by the above logic and a blend of the results, much like
10022 // other patterns in AVX.
10023 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10026 /// \brief Handle lowering 2-lane 128-bit shuffles.
10027 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10028 SDValue V2, ArrayRef<int> Mask,
10029 const X86Subtarget *Subtarget,
10030 SelectionDAG &DAG) {
10031 // Blends are faster and handle all the non-lane-crossing cases.
10032 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10036 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10037 VT.getVectorNumElements() / 2);
10038 // Check for patterns which can be matched with a single insert of a 128-bit
10040 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10041 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10042 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10043 DAG.getIntPtrConstant(0));
10044 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10045 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10046 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10048 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10049 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10050 DAG.getIntPtrConstant(0));
10051 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10052 DAG.getIntPtrConstant(2));
10053 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10056 // Otherwise form a 128-bit permutation.
10057 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10058 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10059 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10060 DAG.getConstant(PermMask, MVT::i8));
10063 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10064 /// shuffling each lane.
10066 /// This will only succeed when the result of fixing the 128-bit lanes results
10067 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10068 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10069 /// the lane crosses early and then use simpler shuffles within each lane.
10071 /// FIXME: It might be worthwhile at some point to support this without
10072 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10073 /// in x86 only floating point has interesting non-repeating shuffles, and even
10074 /// those are still *marginally* more expensive.
10075 static SDValue lowerVectorShuffleByMerging128BitLanes(
10076 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10077 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10078 assert(!isSingleInputShuffleMask(Mask) &&
10079 "This is only useful with multiple inputs.");
10081 int Size = Mask.size();
10082 int LaneSize = 128 / VT.getScalarSizeInBits();
10083 int NumLanes = Size / LaneSize;
10084 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10086 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10087 // check whether the in-128-bit lane shuffles share a repeating pattern.
10088 SmallVector<int, 4> Lanes;
10089 Lanes.resize(NumLanes, -1);
10090 SmallVector<int, 4> InLaneMask;
10091 InLaneMask.resize(LaneSize, -1);
10092 for (int i = 0; i < Size; ++i) {
10096 int j = i / LaneSize;
10098 if (Lanes[j] < 0) {
10099 // First entry we've seen for this lane.
10100 Lanes[j] = Mask[i] / LaneSize;
10101 } else if (Lanes[j] != Mask[i] / LaneSize) {
10102 // This doesn't match the lane selected previously!
10106 // Check that within each lane we have a consistent shuffle mask.
10107 int k = i % LaneSize;
10108 if (InLaneMask[k] < 0) {
10109 InLaneMask[k] = Mask[i] % LaneSize;
10110 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10111 // This doesn't fit a repeating in-lane mask.
10116 // First shuffle the lanes into place.
10117 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10118 VT.getSizeInBits() / 64);
10119 SmallVector<int, 8> LaneMask;
10120 LaneMask.resize(NumLanes * 2, -1);
10121 for (int i = 0; i < NumLanes; ++i)
10122 if (Lanes[i] >= 0) {
10123 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10124 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10127 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10128 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10129 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10131 // Cast it back to the type we actually want.
10132 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10134 // Now do a simple shuffle that isn't lane crossing.
10135 SmallVector<int, 8> NewMask;
10136 NewMask.resize(Size, -1);
10137 for (int i = 0; i < Size; ++i)
10139 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10140 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10141 "Must not introduce lane crosses at this point!");
10143 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10146 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10149 /// This returns true if the elements from a particular input are already in the
10150 /// slot required by the given mask and require no permutation.
10151 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10152 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10153 int Size = Mask.size();
10154 for (int i = 0; i < Size; ++i)
10155 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10161 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10163 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10164 /// isn't available.
10165 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10166 const X86Subtarget *Subtarget,
10167 SelectionDAG &DAG) {
10169 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10170 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10172 ArrayRef<int> Mask = SVOp->getMask();
10173 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10175 SmallVector<int, 4> WidenedMask;
10176 if (canWidenShuffleElements(Mask, WidenedMask))
10177 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10180 if (isSingleInputShuffleMask(Mask)) {
10181 // Check for being able to broadcast a single element.
10182 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10183 Mask, Subtarget, DAG))
10186 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10187 // Non-half-crossing single input shuffles can be lowerid with an
10188 // interleaved permutation.
10189 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10190 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10191 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10192 DAG.getConstant(VPERMILPMask, MVT::i8));
10195 // With AVX2 we have direct support for this permutation.
10196 if (Subtarget->hasAVX2())
10197 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10198 getV4X86ShuffleImm8ForMask(Mask, DAG));
10200 // Otherwise, fall back.
10201 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10205 // X86 has dedicated unpack instructions that can handle specific blend
10206 // operations: UNPCKH and UNPCKL.
10207 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10208 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10209 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10210 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10212 // If we have a single input to the zero element, insert that into V1 if we
10213 // can do so cheaply.
10214 int NumV2Elements =
10215 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10216 if (NumV2Elements == 1 && Mask[0] >= 4)
10217 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10218 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10221 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10225 // Check if the blend happens to exactly fit that of SHUFPD.
10226 if ((Mask[0] == -1 || Mask[0] < 2) &&
10227 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10228 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10229 (Mask[3] == -1 || Mask[3] >= 6)) {
10230 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10231 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10232 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10233 DAG.getConstant(SHUFPDMask, MVT::i8));
10235 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10236 (Mask[1] == -1 || Mask[1] < 2) &&
10237 (Mask[2] == -1 || Mask[2] >= 6) &&
10238 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10239 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10240 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10241 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10242 DAG.getConstant(SHUFPDMask, MVT::i8));
10245 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10246 // shuffle. However, if we have AVX2 and either inputs are already in place,
10247 // we will be able to shuffle even across lanes the other input in a single
10248 // instruction so skip this pattern.
10249 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10250 isShuffleMaskInputInPlace(1, Mask))))
10251 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10252 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10255 // If we have AVX2 then we always want to lower with a blend because an v4 we
10256 // can fully permute the elements.
10257 if (Subtarget->hasAVX2())
10258 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10261 // Otherwise fall back on generic lowering.
10262 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10265 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10267 /// This routine is only called when we have AVX2 and thus a reasonable
10268 /// instruction set for v4i64 shuffling..
10269 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10270 const X86Subtarget *Subtarget,
10271 SelectionDAG &DAG) {
10273 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10274 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10276 ArrayRef<int> Mask = SVOp->getMask();
10277 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10278 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10280 SmallVector<int, 4> WidenedMask;
10281 if (canWidenShuffleElements(Mask, WidenedMask))
10282 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10285 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10289 // Check for being able to broadcast a single element.
10290 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10291 Mask, Subtarget, DAG))
10294 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10295 // use lower latency instructions that will operate on both 128-bit lanes.
10296 SmallVector<int, 2> RepeatedMask;
10297 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10298 if (isSingleInputShuffleMask(Mask)) {
10299 int PSHUFDMask[] = {-1, -1, -1, -1};
10300 for (int i = 0; i < 2; ++i)
10301 if (RepeatedMask[i] >= 0) {
10302 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10303 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10305 return DAG.getNode(
10306 ISD::BITCAST, DL, MVT::v4i64,
10307 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10308 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10309 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10312 // Use dedicated unpack instructions for masks that match their pattern.
10313 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10314 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10315 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10316 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10319 // AVX2 provides a direct instruction for permuting a single input across
10321 if (isSingleInputShuffleMask(Mask))
10322 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10323 getV4X86ShuffleImm8ForMask(Mask, DAG));
10325 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10326 // shuffle. However, if we have AVX2 and either inputs are already in place,
10327 // we will be able to shuffle even across lanes the other input in a single
10328 // instruction so skip this pattern.
10329 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10330 isShuffleMaskInputInPlace(1, Mask))))
10331 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10332 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10335 // Otherwise fall back on generic blend lowering.
10336 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10340 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10342 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10343 /// isn't available.
10344 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10345 const X86Subtarget *Subtarget,
10346 SelectionDAG &DAG) {
10348 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10349 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10351 ArrayRef<int> Mask = SVOp->getMask();
10352 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10354 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10358 // Check for being able to broadcast a single element.
10359 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10360 Mask, Subtarget, DAG))
10363 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10364 // options to efficiently lower the shuffle.
10365 SmallVector<int, 4> RepeatedMask;
10366 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10367 assert(RepeatedMask.size() == 4 &&
10368 "Repeated masks must be half the mask width!");
10369 if (isSingleInputShuffleMask(Mask))
10370 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10371 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10373 // Use dedicated unpack instructions for masks that match their pattern.
10374 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10375 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10376 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10377 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10379 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10380 // have already handled any direct blends. We also need to squash the
10381 // repeated mask into a simulated v4f32 mask.
10382 for (int i = 0; i < 4; ++i)
10383 if (RepeatedMask[i] >= 8)
10384 RepeatedMask[i] -= 4;
10385 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10388 // If we have a single input shuffle with different shuffle patterns in the
10389 // two 128-bit lanes use the variable mask to VPERMILPS.
10390 if (isSingleInputShuffleMask(Mask)) {
10391 SDValue VPermMask[8];
10392 for (int i = 0; i < 8; ++i)
10393 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10394 : DAG.getConstant(Mask[i], MVT::i32);
10395 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10396 return DAG.getNode(
10397 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10398 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10400 if (Subtarget->hasAVX2())
10401 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10402 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10403 DAG.getNode(ISD::BUILD_VECTOR, DL,
10404 MVT::v8i32, VPermMask)),
10407 // Otherwise, fall back.
10408 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10412 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10414 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10415 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10418 // If we have AVX2 then we always want to lower with a blend because at v8 we
10419 // can fully permute the elements.
10420 if (Subtarget->hasAVX2())
10421 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10424 // Otherwise fall back on generic lowering.
10425 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10428 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10430 /// This routine is only called when we have AVX2 and thus a reasonable
10431 /// instruction set for v8i32 shuffling..
10432 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10433 const X86Subtarget *Subtarget,
10434 SelectionDAG &DAG) {
10436 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10437 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10439 ArrayRef<int> Mask = SVOp->getMask();
10440 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10441 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10443 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10447 // Check for being able to broadcast a single element.
10448 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10449 Mask, Subtarget, DAG))
10452 // If the shuffle mask is repeated in each 128-bit lane we can use more
10453 // efficient instructions that mirror the shuffles across the two 128-bit
10455 SmallVector<int, 4> RepeatedMask;
10456 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10457 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10458 if (isSingleInputShuffleMask(Mask))
10459 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10460 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10462 // Use dedicated unpack instructions for masks that match their pattern.
10463 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10464 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10465 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10466 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10469 // If the shuffle patterns aren't repeated but it is a single input, directly
10470 // generate a cross-lane VPERMD instruction.
10471 if (isSingleInputShuffleMask(Mask)) {
10472 SDValue VPermMask[8];
10473 for (int i = 0; i < 8; ++i)
10474 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10475 : DAG.getConstant(Mask[i], MVT::i32);
10476 return DAG.getNode(
10477 X86ISD::VPERMV, DL, MVT::v8i32,
10478 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10481 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10483 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10484 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10487 // Otherwise fall back on generic blend lowering.
10488 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10492 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10494 /// This routine is only called when we have AVX2 and thus a reasonable
10495 /// instruction set for v16i16 shuffling..
10496 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10497 const X86Subtarget *Subtarget,
10498 SelectionDAG &DAG) {
10500 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10501 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10503 ArrayRef<int> Mask = SVOp->getMask();
10504 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10505 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10507 // Check for being able to broadcast a single element.
10508 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10509 Mask, Subtarget, DAG))
10512 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10516 // Use dedicated unpack instructions for masks that match their pattern.
10517 if (isShuffleEquivalent(Mask,
10518 // First 128-bit lane:
10519 0, 16, 1, 17, 2, 18, 3, 19,
10520 // Second 128-bit lane:
10521 8, 24, 9, 25, 10, 26, 11, 27))
10522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10523 if (isShuffleEquivalent(Mask,
10524 // First 128-bit lane:
10525 4, 20, 5, 21, 6, 22, 7, 23,
10526 // Second 128-bit lane:
10527 12, 28, 13, 29, 14, 30, 15, 31))
10528 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10530 if (isSingleInputShuffleMask(Mask)) {
10531 // There are no generalized cross-lane shuffle operations available on i16
10533 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10534 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10537 SDValue PSHUFBMask[32];
10538 for (int i = 0; i < 16; ++i) {
10539 if (Mask[i] == -1) {
10540 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10544 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10545 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10546 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10547 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10549 return DAG.getNode(
10550 ISD::BITCAST, DL, MVT::v16i16,
10552 X86ISD::PSHUFB, DL, MVT::v32i8,
10553 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10554 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10557 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10559 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10560 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10563 // Otherwise fall back on generic lowering.
10564 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10567 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10569 /// This routine is only called when we have AVX2 and thus a reasonable
10570 /// instruction set for v32i8 shuffling..
10571 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10572 const X86Subtarget *Subtarget,
10573 SelectionDAG &DAG) {
10575 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10576 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10577 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10578 ArrayRef<int> Mask = SVOp->getMask();
10579 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10580 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10582 // Check for being able to broadcast a single element.
10583 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10584 Mask, Subtarget, DAG))
10587 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10591 // Use dedicated unpack instructions for masks that match their pattern.
10592 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10594 if (isShuffleEquivalent(
10596 // First 128-bit lane:
10597 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10598 // Second 128-bit lane:
10599 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10600 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10601 if (isShuffleEquivalent(
10603 // First 128-bit lane:
10604 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10605 // Second 128-bit lane:
10606 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10607 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10609 if (isSingleInputShuffleMask(Mask)) {
10610 // There are no generalized cross-lane shuffle operations available on i8
10612 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10613 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10616 SDValue PSHUFBMask[32];
10617 for (int i = 0; i < 32; ++i)
10620 ? DAG.getUNDEF(MVT::i8)
10621 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10623 return DAG.getNode(
10624 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10625 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10628 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10630 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10631 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10634 // Otherwise fall back on generic lowering.
10635 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10638 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10640 /// This routine either breaks down the specific type of a 256-bit x86 vector
10641 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10642 /// together based on the available instructions.
10643 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10644 MVT VT, const X86Subtarget *Subtarget,
10645 SelectionDAG &DAG) {
10647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10648 ArrayRef<int> Mask = SVOp->getMask();
10650 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10651 // check for those subtargets here and avoid much of the subtarget querying in
10652 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10653 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10654 // floating point types there eventually, just immediately cast everything to
10655 // a float and operate entirely in that domain.
10656 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10657 int ElementBits = VT.getScalarSizeInBits();
10658 if (ElementBits < 32)
10659 // No floating point type available, decompose into 128-bit vectors.
10660 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10662 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10663 VT.getVectorNumElements());
10664 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10665 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10666 return DAG.getNode(ISD::BITCAST, DL, VT,
10667 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10670 switch (VT.SimpleTy) {
10672 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10674 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10676 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10678 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10680 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10682 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10685 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10689 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10690 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10691 const X86Subtarget *Subtarget,
10692 SelectionDAG &DAG) {
10694 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10695 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10697 ArrayRef<int> Mask = SVOp->getMask();
10698 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10700 // FIXME: Implement direct support for this type!
10701 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10704 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10705 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10706 const X86Subtarget *Subtarget,
10707 SelectionDAG &DAG) {
10709 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10710 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10712 ArrayRef<int> Mask = SVOp->getMask();
10713 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10715 // FIXME: Implement direct support for this type!
10716 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10719 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10720 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10721 const X86Subtarget *Subtarget,
10722 SelectionDAG &DAG) {
10724 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10725 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10727 ArrayRef<int> Mask = SVOp->getMask();
10728 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10730 // FIXME: Implement direct support for this type!
10731 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10734 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10735 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10736 const X86Subtarget *Subtarget,
10737 SelectionDAG &DAG) {
10739 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10740 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10741 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10742 ArrayRef<int> Mask = SVOp->getMask();
10743 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10745 // FIXME: Implement direct support for this type!
10746 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10749 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10750 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10751 const X86Subtarget *Subtarget,
10752 SelectionDAG &DAG) {
10754 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10755 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10756 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10757 ArrayRef<int> Mask = SVOp->getMask();
10758 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10759 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10761 // FIXME: Implement direct support for this type!
10762 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10765 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10766 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10767 const X86Subtarget *Subtarget,
10768 SelectionDAG &DAG) {
10770 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10771 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10772 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10773 ArrayRef<int> Mask = SVOp->getMask();
10774 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10775 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10777 // FIXME: Implement direct support for this type!
10778 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10781 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10783 /// This routine either breaks down the specific type of a 512-bit x86 vector
10784 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10785 /// together based on the available instructions.
10786 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10787 MVT VT, const X86Subtarget *Subtarget,
10788 SelectionDAG &DAG) {
10790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10791 ArrayRef<int> Mask = SVOp->getMask();
10792 assert(Subtarget->hasAVX512() &&
10793 "Cannot lower 512-bit vectors w/ basic ISA!");
10795 // Check for being able to broadcast a single element.
10796 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10797 Mask, Subtarget, DAG))
10800 // Dispatch to each element type for lowering. If we don't have supprot for
10801 // specific element type shuffles at 512 bits, immediately split them and
10802 // lower them. Each lowering routine of a given type is allowed to assume that
10803 // the requisite ISA extensions for that element type are available.
10804 switch (VT.SimpleTy) {
10806 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10808 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10810 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10812 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10814 if (Subtarget->hasBWI())
10815 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10818 if (Subtarget->hasBWI())
10819 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10823 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10826 // Otherwise fall back on splitting.
10827 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10830 /// \brief Top-level lowering for x86 vector shuffles.
10832 /// This handles decomposition, canonicalization, and lowering of all x86
10833 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10834 /// above in helper routines. The canonicalization attempts to widen shuffles
10835 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10836 /// s.t. only one of the two inputs needs to be tested, etc.
10837 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10838 SelectionDAG &DAG) {
10839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10840 ArrayRef<int> Mask = SVOp->getMask();
10841 SDValue V1 = Op.getOperand(0);
10842 SDValue V2 = Op.getOperand(1);
10843 MVT VT = Op.getSimpleValueType();
10844 int NumElements = VT.getVectorNumElements();
10847 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10849 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10850 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10851 if (V1IsUndef && V2IsUndef)
10852 return DAG.getUNDEF(VT);
10854 // When we create a shuffle node we put the UNDEF node to second operand,
10855 // but in some cases the first operand may be transformed to UNDEF.
10856 // In this case we should just commute the node.
10858 return DAG.getCommutedVectorShuffle(*SVOp);
10860 // Check for non-undef masks pointing at an undef vector and make the masks
10861 // undef as well. This makes it easier to match the shuffle based solely on
10865 if (M >= NumElements) {
10866 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10867 for (int &M : NewMask)
10868 if (M >= NumElements)
10870 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10873 // Try to collapse shuffles into using a vector type with fewer elements but
10874 // wider element types. We cap this to not form integers or floating point
10875 // elements wider than 64 bits, but it might be interesting to form i128
10876 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10877 SmallVector<int, 16> WidenedMask;
10878 if (VT.getScalarSizeInBits() < 64 &&
10879 canWidenShuffleElements(Mask, WidenedMask)) {
10880 MVT NewEltVT = VT.isFloatingPoint()
10881 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10882 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10883 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10884 // Make sure that the new vector type is legal. For example, v2f64 isn't
10886 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10887 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10888 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10889 return DAG.getNode(ISD::BITCAST, dl, VT,
10890 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10894 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10895 for (int M : SVOp->getMask())
10897 ++NumUndefElements;
10898 else if (M < NumElements)
10903 // Commute the shuffle as needed such that more elements come from V1 than
10904 // V2. This allows us to match the shuffle pattern strictly on how many
10905 // elements come from V1 without handling the symmetric cases.
10906 if (NumV2Elements > NumV1Elements)
10907 return DAG.getCommutedVectorShuffle(*SVOp);
10909 // When the number of V1 and V2 elements are the same, try to minimize the
10910 // number of uses of V2 in the low half of the vector. When that is tied,
10911 // ensure that the sum of indices for V1 is equal to or lower than the sum
10912 // indices for V2. When those are equal, try to ensure that the number of odd
10913 // indices for V1 is lower than the number of odd indices for V2.
10914 if (NumV1Elements == NumV2Elements) {
10915 int LowV1Elements = 0, LowV2Elements = 0;
10916 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10917 if (M >= NumElements)
10921 if (LowV2Elements > LowV1Elements) {
10922 return DAG.getCommutedVectorShuffle(*SVOp);
10923 } else if (LowV2Elements == LowV1Elements) {
10924 int SumV1Indices = 0, SumV2Indices = 0;
10925 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10926 if (SVOp->getMask()[i] >= NumElements)
10928 else if (SVOp->getMask()[i] >= 0)
10930 if (SumV2Indices < SumV1Indices) {
10931 return DAG.getCommutedVectorShuffle(*SVOp);
10932 } else if (SumV2Indices == SumV1Indices) {
10933 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10934 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10935 if (SVOp->getMask()[i] >= NumElements)
10936 NumV2OddIndices += i % 2;
10937 else if (SVOp->getMask()[i] >= 0)
10938 NumV1OddIndices += i % 2;
10939 if (NumV2OddIndices < NumV1OddIndices)
10940 return DAG.getCommutedVectorShuffle(*SVOp);
10945 // For each vector width, delegate to a specialized lowering routine.
10946 if (VT.getSizeInBits() == 128)
10947 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10949 if (VT.getSizeInBits() == 256)
10950 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10952 // Force AVX-512 vectors to be scalarized for now.
10953 // FIXME: Implement AVX-512 support!
10954 if (VT.getSizeInBits() == 512)
10955 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10957 llvm_unreachable("Unimplemented!");
10961 //===----------------------------------------------------------------------===//
10962 // Legacy vector shuffle lowering
10964 // This code is the legacy code handling vector shuffles until the above
10965 // replaces its functionality and performance.
10966 //===----------------------------------------------------------------------===//
10968 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10969 bool hasInt256, unsigned *MaskOut = nullptr) {
10970 MVT EltVT = VT.getVectorElementType();
10972 // There is no blend with immediate in AVX-512.
10973 if (VT.is512BitVector())
10976 if (!hasSSE41 || EltVT == MVT::i8)
10978 if (!hasInt256 && VT == MVT::v16i16)
10981 unsigned MaskValue = 0;
10982 unsigned NumElems = VT.getVectorNumElements();
10983 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10984 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10985 unsigned NumElemsInLane = NumElems / NumLanes;
10987 // Blend for v16i16 should be symetric for the both lanes.
10988 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10990 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10991 int EltIdx = MaskVals[i];
10993 if ((EltIdx < 0 || EltIdx == (int)i) &&
10994 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10997 if (((unsigned)EltIdx == (i + NumElems)) &&
10998 (SndLaneEltIdx < 0 ||
10999 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
11000 MaskValue |= (1 << i);
11006 *MaskOut = MaskValue;
11010 // Try to lower a shuffle node into a simple blend instruction.
11011 // This function assumes isBlendMask returns true for this
11012 // SuffleVectorSDNode
11013 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11014 unsigned MaskValue,
11015 const X86Subtarget *Subtarget,
11016 SelectionDAG &DAG) {
11017 MVT VT = SVOp->getSimpleValueType(0);
11018 MVT EltVT = VT.getVectorElementType();
11019 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11020 Subtarget->hasInt256() && "Trying to lower a "
11021 "VECTOR_SHUFFLE to a Blend but "
11022 "with the wrong mask"));
11023 SDValue V1 = SVOp->getOperand(0);
11024 SDValue V2 = SVOp->getOperand(1);
11026 unsigned NumElems = VT.getVectorNumElements();
11028 // Convert i32 vectors to floating point if it is not AVX2.
11029 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11031 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11032 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11034 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11035 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11038 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11039 DAG.getConstant(MaskValue, MVT::i32));
11040 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11043 /// In vector type \p VT, return true if the element at index \p InputIdx
11044 /// falls on a different 128-bit lane than \p OutputIdx.
11045 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11046 unsigned OutputIdx) {
11047 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11048 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11051 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11052 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11053 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11054 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11056 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11057 SelectionDAG &DAG) {
11058 MVT VT = V1.getSimpleValueType();
11059 assert(VT.is128BitVector() || VT.is256BitVector());
11061 MVT EltVT = VT.getVectorElementType();
11062 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11063 unsigned NumElts = VT.getVectorNumElements();
11065 SmallVector<SDValue, 32> PshufbMask;
11066 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11067 int InputIdx = MaskVals[OutputIdx];
11068 unsigned InputByteIdx;
11070 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11071 InputByteIdx = 0x80;
11073 // Cross lane is not allowed.
11074 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11076 InputByteIdx = InputIdx * EltSizeInBytes;
11077 // Index is an byte offset within the 128-bit lane.
11078 InputByteIdx &= 0xf;
11081 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11082 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11083 if (InputByteIdx != 0x80)
11088 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11090 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11091 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11092 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11095 // v8i16 shuffles - Prefer shuffles in the following order:
11096 // 1. [all] pshuflw, pshufhw, optional move
11097 // 2. [ssse3] 1 x pshufb
11098 // 3. [ssse3] 2 x pshufb + 1 x por
11099 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11101 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11102 SelectionDAG &DAG) {
11103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11104 SDValue V1 = SVOp->getOperand(0);
11105 SDValue V2 = SVOp->getOperand(1);
11107 SmallVector<int, 8> MaskVals;
11109 // Determine if more than 1 of the words in each of the low and high quadwords
11110 // of the result come from the same quadword of one of the two inputs. Undef
11111 // mask values count as coming from any quadword, for better codegen.
11113 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11114 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11115 unsigned LoQuad[] = { 0, 0, 0, 0 };
11116 unsigned HiQuad[] = { 0, 0, 0, 0 };
11117 // Indices of quads used.
11118 std::bitset<4> InputQuads;
11119 for (unsigned i = 0; i < 8; ++i) {
11120 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11121 int EltIdx = SVOp->getMaskElt(i);
11122 MaskVals.push_back(EltIdx);
11130 ++Quad[EltIdx / 4];
11131 InputQuads.set(EltIdx / 4);
11134 int BestLoQuad = -1;
11135 unsigned MaxQuad = 1;
11136 for (unsigned i = 0; i < 4; ++i) {
11137 if (LoQuad[i] > MaxQuad) {
11139 MaxQuad = LoQuad[i];
11143 int BestHiQuad = -1;
11145 for (unsigned i = 0; i < 4; ++i) {
11146 if (HiQuad[i] > MaxQuad) {
11148 MaxQuad = HiQuad[i];
11152 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11153 // of the two input vectors, shuffle them into one input vector so only a
11154 // single pshufb instruction is necessary. If there are more than 2 input
11155 // quads, disable the next transformation since it does not help SSSE3.
11156 bool V1Used = InputQuads[0] || InputQuads[1];
11157 bool V2Used = InputQuads[2] || InputQuads[3];
11158 if (Subtarget->hasSSSE3()) {
11159 if (InputQuads.count() == 2 && V1Used && V2Used) {
11160 BestLoQuad = InputQuads[0] ? 0 : 1;
11161 BestHiQuad = InputQuads[2] ? 2 : 3;
11163 if (InputQuads.count() > 2) {
11169 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11170 // the shuffle mask. If a quad is scored as -1, that means that it contains
11171 // words from all 4 input quadwords.
11173 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11175 BestLoQuad < 0 ? 0 : BestLoQuad,
11176 BestHiQuad < 0 ? 1 : BestHiQuad
11178 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11179 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11180 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11181 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11183 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11184 // source words for the shuffle, to aid later transformations.
11185 bool AllWordsInNewV = true;
11186 bool InOrder[2] = { true, true };
11187 for (unsigned i = 0; i != 8; ++i) {
11188 int idx = MaskVals[i];
11190 InOrder[i/4] = false;
11191 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11193 AllWordsInNewV = false;
11197 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11198 if (AllWordsInNewV) {
11199 for (int i = 0; i != 8; ++i) {
11200 int idx = MaskVals[i];
11203 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11204 if ((idx != i) && idx < 4)
11206 if ((idx != i) && idx > 3)
11215 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11216 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11217 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11218 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11219 unsigned TargetMask = 0;
11220 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11221 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11223 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11224 getShufflePSHUFLWImmediate(SVOp);
11225 V1 = NewV.getOperand(0);
11226 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11230 // Promote splats to a larger type which usually leads to more efficient code.
11231 // FIXME: Is this true if pshufb is available?
11232 if (SVOp->isSplat())
11233 return PromoteSplat(SVOp, DAG);
11235 // If we have SSSE3, and all words of the result are from 1 input vector,
11236 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11237 // is present, fall back to case 4.
11238 if (Subtarget->hasSSSE3()) {
11239 SmallVector<SDValue,16> pshufbMask;
11241 // If we have elements from both input vectors, set the high bit of the
11242 // shuffle mask element to zero out elements that come from V2 in the V1
11243 // mask, and elements that come from V1 in the V2 mask, so that the two
11244 // results can be OR'd together.
11245 bool TwoInputs = V1Used && V2Used;
11246 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11248 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11250 // Calculate the shuffle mask for the second input, shuffle it, and
11251 // OR it with the first shuffled input.
11252 CommuteVectorShuffleMask(MaskVals, 8);
11253 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11254 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11255 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11258 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11259 // and update MaskVals with new element order.
11260 std::bitset<8> InOrder;
11261 if (BestLoQuad >= 0) {
11262 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11263 for (int i = 0; i != 4; ++i) {
11264 int idx = MaskVals[i];
11267 } else if ((idx / 4) == BestLoQuad) {
11268 MaskV[i] = idx & 3;
11272 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11275 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11277 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11278 NewV.getOperand(0),
11279 getShufflePSHUFLWImmediate(SVOp), DAG);
11283 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11284 // and update MaskVals with the new element order.
11285 if (BestHiQuad >= 0) {
11286 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11287 for (unsigned i = 4; i != 8; ++i) {
11288 int idx = MaskVals[i];
11291 } else if ((idx / 4) == BestHiQuad) {
11292 MaskV[i] = (idx & 3) + 4;
11296 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11299 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11300 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11301 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11302 NewV.getOperand(0),
11303 getShufflePSHUFHWImmediate(SVOp), DAG);
11307 // In case BestHi & BestLo were both -1, which means each quadword has a word
11308 // from each of the four input quadwords, calculate the InOrder bitvector now
11309 // before falling through to the insert/extract cleanup.
11310 if (BestLoQuad == -1 && BestHiQuad == -1) {
11312 for (int i = 0; i != 8; ++i)
11313 if (MaskVals[i] < 0 || MaskVals[i] == i)
11317 // The other elements are put in the right place using pextrw and pinsrw.
11318 for (unsigned i = 0; i != 8; ++i) {
11321 int EltIdx = MaskVals[i];
11324 SDValue ExtOp = (EltIdx < 8) ?
11325 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11326 DAG.getIntPtrConstant(EltIdx)) :
11327 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11328 DAG.getIntPtrConstant(EltIdx - 8));
11329 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11330 DAG.getIntPtrConstant(i));
11335 /// \brief v16i16 shuffles
11337 /// FIXME: We only support generation of a single pshufb currently. We can
11338 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11339 /// well (e.g 2 x pshufb + 1 x por).
11341 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11343 SDValue V1 = SVOp->getOperand(0);
11344 SDValue V2 = SVOp->getOperand(1);
11347 if (V2.getOpcode() != ISD::UNDEF)
11350 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11351 return getPSHUFB(MaskVals, V1, dl, DAG);
11354 // v16i8 shuffles - Prefer shuffles in the following order:
11355 // 1. [ssse3] 1 x pshufb
11356 // 2. [ssse3] 2 x pshufb + 1 x por
11357 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11358 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11359 const X86Subtarget* Subtarget,
11360 SelectionDAG &DAG) {
11361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11362 SDValue V1 = SVOp->getOperand(0);
11363 SDValue V2 = SVOp->getOperand(1);
11365 ArrayRef<int> MaskVals = SVOp->getMask();
11367 // Promote splats to a larger type which usually leads to more efficient code.
11368 // FIXME: Is this true if pshufb is available?
11369 if (SVOp->isSplat())
11370 return PromoteSplat(SVOp, DAG);
11372 // If we have SSSE3, case 1 is generated when all result bytes come from
11373 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11374 // present, fall back to case 3.
11376 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11377 if (Subtarget->hasSSSE3()) {
11378 SmallVector<SDValue,16> pshufbMask;
11380 // If all result elements are from one input vector, then only translate
11381 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11383 // Otherwise, we have elements from both input vectors, and must zero out
11384 // elements that come from V2 in the first mask, and V1 in the second mask
11385 // so that we can OR them together.
11386 for (unsigned i = 0; i != 16; ++i) {
11387 int EltIdx = MaskVals[i];
11388 if (EltIdx < 0 || EltIdx >= 16)
11390 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11392 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11393 DAG.getNode(ISD::BUILD_VECTOR, dl,
11394 MVT::v16i8, pshufbMask));
11396 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11397 // the 2nd operand if it's undefined or zero.
11398 if (V2.getOpcode() == ISD::UNDEF ||
11399 ISD::isBuildVectorAllZeros(V2.getNode()))
11402 // Calculate the shuffle mask for the second input, shuffle it, and
11403 // OR it with the first shuffled input.
11404 pshufbMask.clear();
11405 for (unsigned i = 0; i != 16; ++i) {
11406 int EltIdx = MaskVals[i];
11407 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11408 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11410 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11411 DAG.getNode(ISD::BUILD_VECTOR, dl,
11412 MVT::v16i8, pshufbMask));
11413 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11416 // No SSSE3 - Calculate in place words and then fix all out of place words
11417 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11418 // the 16 different words that comprise the two doublequadword input vectors.
11419 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11420 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11422 for (int i = 0; i != 8; ++i) {
11423 int Elt0 = MaskVals[i*2];
11424 int Elt1 = MaskVals[i*2+1];
11426 // This word of the result is all undef, skip it.
11427 if (Elt0 < 0 && Elt1 < 0)
11430 // This word of the result is already in the correct place, skip it.
11431 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11434 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11435 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11438 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11439 // using a single extract together, load it and store it.
11440 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11441 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11442 DAG.getIntPtrConstant(Elt1 / 2));
11443 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11444 DAG.getIntPtrConstant(i));
11448 // If Elt1 is defined, extract it from the appropriate source. If the
11449 // source byte is not also odd, shift the extracted word left 8 bits
11450 // otherwise clear the bottom 8 bits if we need to do an or.
11452 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11453 DAG.getIntPtrConstant(Elt1 / 2));
11454 if ((Elt1 & 1) == 0)
11455 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11457 TLI.getShiftAmountTy(InsElt.getValueType())));
11458 else if (Elt0 >= 0)
11459 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11460 DAG.getConstant(0xFF00, MVT::i16));
11462 // If Elt0 is defined, extract it from the appropriate source. If the
11463 // source byte is not also even, shift the extracted word right 8 bits. If
11464 // Elt1 was also defined, OR the extracted values together before
11465 // inserting them in the result.
11467 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11468 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11469 if ((Elt0 & 1) != 0)
11470 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11472 TLI.getShiftAmountTy(InsElt0.getValueType())));
11473 else if (Elt1 >= 0)
11474 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11475 DAG.getConstant(0x00FF, MVT::i16));
11476 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11479 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11480 DAG.getIntPtrConstant(i));
11482 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11485 // v32i8 shuffles - Translate to VPSHUFB if possible.
11487 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11488 const X86Subtarget *Subtarget,
11489 SelectionDAG &DAG) {
11490 MVT VT = SVOp->getSimpleValueType(0);
11491 SDValue V1 = SVOp->getOperand(0);
11492 SDValue V2 = SVOp->getOperand(1);
11494 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11496 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11497 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11498 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11500 // VPSHUFB may be generated if
11501 // (1) one of input vector is undefined or zeroinitializer.
11502 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11503 // And (2) the mask indexes don't cross the 128-bit lane.
11504 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11505 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11508 if (V1IsAllZero && !V2IsAllZero) {
11509 CommuteVectorShuffleMask(MaskVals, 32);
11512 return getPSHUFB(MaskVals, V1, dl, DAG);
11515 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11516 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11517 /// done when every pair / quad of shuffle mask elements point to elements in
11518 /// the right sequence. e.g.
11519 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11521 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11522 SelectionDAG &DAG) {
11523 MVT VT = SVOp->getSimpleValueType(0);
11525 unsigned NumElems = VT.getVectorNumElements();
11528 switch (VT.SimpleTy) {
11529 default: llvm_unreachable("Unexpected!");
11532 return SDValue(SVOp, 0);
11533 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11534 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11535 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11536 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11537 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11538 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11541 SmallVector<int, 8> MaskVec;
11542 for (unsigned i = 0; i != NumElems; i += Scale) {
11544 for (unsigned j = 0; j != Scale; ++j) {
11545 int EltIdx = SVOp->getMaskElt(i+j);
11549 StartIdx = (EltIdx / Scale);
11550 if (EltIdx != (int)(StartIdx*Scale + j))
11553 MaskVec.push_back(StartIdx);
11556 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11557 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11558 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11561 /// getVZextMovL - Return a zero-extending vector move low node.
11563 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11564 SDValue SrcOp, SelectionDAG &DAG,
11565 const X86Subtarget *Subtarget, SDLoc dl) {
11566 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11567 LoadSDNode *LD = nullptr;
11568 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11569 LD = dyn_cast<LoadSDNode>(SrcOp);
11571 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11573 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11574 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11575 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11576 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11577 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11579 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11580 return DAG.getNode(ISD::BITCAST, dl, VT,
11581 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11582 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11584 SrcOp.getOperand(0)
11590 return DAG.getNode(ISD::BITCAST, dl, VT,
11591 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11592 DAG.getNode(ISD::BITCAST, dl,
11596 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11597 /// which could not be matched by any known target speficic shuffle
11599 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11601 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11602 if (NewOp.getNode())
11605 MVT VT = SVOp->getSimpleValueType(0);
11607 unsigned NumElems = VT.getVectorNumElements();
11608 unsigned NumLaneElems = NumElems / 2;
11611 MVT EltVT = VT.getVectorElementType();
11612 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11615 SmallVector<int, 16> Mask;
11616 for (unsigned l = 0; l < 2; ++l) {
11617 // Build a shuffle mask for the output, discovering on the fly which
11618 // input vectors to use as shuffle operands (recorded in InputUsed).
11619 // If building a suitable shuffle vector proves too hard, then bail
11620 // out with UseBuildVector set.
11621 bool UseBuildVector = false;
11622 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11623 unsigned LaneStart = l * NumLaneElems;
11624 for (unsigned i = 0; i != NumLaneElems; ++i) {
11625 // The mask element. This indexes into the input.
11626 int Idx = SVOp->getMaskElt(i+LaneStart);
11628 // the mask element does not index into any input vector.
11629 Mask.push_back(-1);
11633 // The input vector this mask element indexes into.
11634 int Input = Idx / NumLaneElems;
11636 // Turn the index into an offset from the start of the input vector.
11637 Idx -= Input * NumLaneElems;
11639 // Find or create a shuffle vector operand to hold this input.
11641 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11642 if (InputUsed[OpNo] == Input)
11643 // This input vector is already an operand.
11645 if (InputUsed[OpNo] < 0) {
11646 // Create a new operand for this input vector.
11647 InputUsed[OpNo] = Input;
11652 if (OpNo >= array_lengthof(InputUsed)) {
11653 // More than two input vectors used! Give up on trying to create a
11654 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11655 UseBuildVector = true;
11659 // Add the mask index for the new shuffle vector.
11660 Mask.push_back(Idx + OpNo * NumLaneElems);
11663 if (UseBuildVector) {
11664 SmallVector<SDValue, 16> SVOps;
11665 for (unsigned i = 0; i != NumLaneElems; ++i) {
11666 // The mask element. This indexes into the input.
11667 int Idx = SVOp->getMaskElt(i+LaneStart);
11669 SVOps.push_back(DAG.getUNDEF(EltVT));
11673 // The input vector this mask element indexes into.
11674 int Input = Idx / NumElems;
11676 // Turn the index into an offset from the start of the input vector.
11677 Idx -= Input * NumElems;
11679 // Extract the vector element by hand.
11680 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11681 SVOp->getOperand(Input),
11682 DAG.getIntPtrConstant(Idx)));
11685 // Construct the output using a BUILD_VECTOR.
11686 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11687 } else if (InputUsed[0] < 0) {
11688 // No input vectors were used! The result is undefined.
11689 Output[l] = DAG.getUNDEF(NVT);
11691 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11692 (InputUsed[0] % 2) * NumLaneElems,
11694 // If only one input was used, use an undefined vector for the other.
11695 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11696 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11697 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11698 // At least one input vector was used. Create a new shuffle vector.
11699 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11705 // Concatenate the result back
11706 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11709 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11710 /// 4 elements, and match them with several different shuffle types.
11712 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11713 SDValue V1 = SVOp->getOperand(0);
11714 SDValue V2 = SVOp->getOperand(1);
11716 MVT VT = SVOp->getSimpleValueType(0);
11718 assert(VT.is128BitVector() && "Unsupported vector size");
11720 std::pair<int, int> Locs[4];
11721 int Mask1[] = { -1, -1, -1, -1 };
11722 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11724 unsigned NumHi = 0;
11725 unsigned NumLo = 0;
11726 for (unsigned i = 0; i != 4; ++i) {
11727 int Idx = PermMask[i];
11729 Locs[i] = std::make_pair(-1, -1);
11731 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11733 Locs[i] = std::make_pair(0, NumLo);
11734 Mask1[NumLo] = Idx;
11737 Locs[i] = std::make_pair(1, NumHi);
11739 Mask1[2+NumHi] = Idx;
11745 if (NumLo <= 2 && NumHi <= 2) {
11746 // If no more than two elements come from either vector. This can be
11747 // implemented with two shuffles. First shuffle gather the elements.
11748 // The second shuffle, which takes the first shuffle as both of its
11749 // vector operands, put the elements into the right order.
11750 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11752 int Mask2[] = { -1, -1, -1, -1 };
11754 for (unsigned i = 0; i != 4; ++i)
11755 if (Locs[i].first != -1) {
11756 unsigned Idx = (i < 2) ? 0 : 4;
11757 Idx += Locs[i].first * 2 + Locs[i].second;
11761 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11764 if (NumLo == 3 || NumHi == 3) {
11765 // Otherwise, we must have three elements from one vector, call it X, and
11766 // one element from the other, call it Y. First, use a shufps to build an
11767 // intermediate vector with the one element from Y and the element from X
11768 // that will be in the same half in the final destination (the indexes don't
11769 // matter). Then, use a shufps to build the final vector, taking the half
11770 // containing the element from Y from the intermediate, and the other half
11773 // Normalize it so the 3 elements come from V1.
11774 CommuteVectorShuffleMask(PermMask, 4);
11778 // Find the element from V2.
11780 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11781 int Val = PermMask[HiIndex];
11788 Mask1[0] = PermMask[HiIndex];
11790 Mask1[2] = PermMask[HiIndex^1];
11792 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11794 if (HiIndex >= 2) {
11795 Mask1[0] = PermMask[0];
11796 Mask1[1] = PermMask[1];
11797 Mask1[2] = HiIndex & 1 ? 6 : 4;
11798 Mask1[3] = HiIndex & 1 ? 4 : 6;
11799 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11802 Mask1[0] = HiIndex & 1 ? 2 : 0;
11803 Mask1[1] = HiIndex & 1 ? 0 : 2;
11804 Mask1[2] = PermMask[2];
11805 Mask1[3] = PermMask[3];
11810 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11813 // Break it into (shuffle shuffle_hi, shuffle_lo).
11814 int LoMask[] = { -1, -1, -1, -1 };
11815 int HiMask[] = { -1, -1, -1, -1 };
11817 int *MaskPtr = LoMask;
11818 unsigned MaskIdx = 0;
11819 unsigned LoIdx = 0;
11820 unsigned HiIdx = 2;
11821 for (unsigned i = 0; i != 4; ++i) {
11828 int Idx = PermMask[i];
11830 Locs[i] = std::make_pair(-1, -1);
11831 } else if (Idx < 4) {
11832 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11833 MaskPtr[LoIdx] = Idx;
11836 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11837 MaskPtr[HiIdx] = Idx;
11842 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11843 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11844 int MaskOps[] = { -1, -1, -1, -1 };
11845 for (unsigned i = 0; i != 4; ++i)
11846 if (Locs[i].first != -1)
11847 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11848 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11851 static bool MayFoldVectorLoad(SDValue V) {
11852 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11853 V = V.getOperand(0);
11855 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11856 V = V.getOperand(0);
11857 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11858 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11859 // BUILD_VECTOR (load), undef
11860 V = V.getOperand(0);
11862 return MayFoldLoad(V);
11866 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11867 MVT VT = Op.getSimpleValueType();
11869 // Canonizalize to v2f64.
11870 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11871 return DAG.getNode(ISD::BITCAST, dl, VT,
11872 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11877 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11879 SDValue V1 = Op.getOperand(0);
11880 SDValue V2 = Op.getOperand(1);
11881 MVT VT = Op.getSimpleValueType();
11883 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11885 if (HasSSE2 && VT == MVT::v2f64)
11886 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11888 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11889 return DAG.getNode(ISD::BITCAST, dl, VT,
11890 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11891 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11892 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11896 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11897 SDValue V1 = Op.getOperand(0);
11898 SDValue V2 = Op.getOperand(1);
11899 MVT VT = Op.getSimpleValueType();
11901 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11902 "unsupported shuffle type");
11904 if (V2.getOpcode() == ISD::UNDEF)
11908 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11912 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11913 SDValue V1 = Op.getOperand(0);
11914 SDValue V2 = Op.getOperand(1);
11915 MVT VT = Op.getSimpleValueType();
11916 unsigned NumElems = VT.getVectorNumElements();
11918 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11919 // operand of these instructions is only memory, so check if there's a
11920 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11922 bool CanFoldLoad = false;
11924 // Trivial case, when V2 comes from a load.
11925 if (MayFoldVectorLoad(V2))
11926 CanFoldLoad = true;
11928 // When V1 is a load, it can be folded later into a store in isel, example:
11929 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11931 // (MOVLPSmr addr:$src1, VR128:$src2)
11932 // So, recognize this potential and also use MOVLPS or MOVLPD
11933 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11934 CanFoldLoad = true;
11936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11938 if (HasSSE2 && NumElems == 2)
11939 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11942 // If we don't care about the second element, proceed to use movss.
11943 if (SVOp->getMaskElt(1) != -1)
11944 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11947 // movl and movlp will both match v2i64, but v2i64 is never matched by
11948 // movl earlier because we make it strict to avoid messing with the movlp load
11949 // folding logic (see the code above getMOVLP call). Match it here then,
11950 // this is horrible, but will stay like this until we move all shuffle
11951 // matching to x86 specific nodes. Note that for the 1st condition all
11952 // types are matched with movsd.
11954 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11955 // as to remove this logic from here, as much as possible
11956 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11957 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11958 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11961 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11963 // Invert the operand order and use SHUFPS to match it.
11964 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11965 getShuffleSHUFImmediate(SVOp), DAG);
11968 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11969 SelectionDAG &DAG) {
11971 MVT VT = Load->getSimpleValueType(0);
11972 MVT EVT = VT.getVectorElementType();
11973 SDValue Addr = Load->getOperand(1);
11974 SDValue NewAddr = DAG.getNode(
11975 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11976 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11979 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11980 DAG.getMachineFunction().getMachineMemOperand(
11981 Load->getMemOperand(), 0, EVT.getStoreSize()));
11985 // It is only safe to call this function if isINSERTPSMask is true for
11986 // this shufflevector mask.
11987 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11988 SelectionDAG &DAG) {
11989 // Generate an insertps instruction when inserting an f32 from memory onto a
11990 // v4f32 or when copying a member from one v4f32 to another.
11991 // We also use it for transferring i32 from one register to another,
11992 // since it simply copies the same bits.
11993 // If we're transferring an i32 from memory to a specific element in a
11994 // register, we output a generic DAG that will match the PINSRD
11996 MVT VT = SVOp->getSimpleValueType(0);
11997 MVT EVT = VT.getVectorElementType();
11998 SDValue V1 = SVOp->getOperand(0);
11999 SDValue V2 = SVOp->getOperand(1);
12000 auto Mask = SVOp->getMask();
12001 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
12002 "unsupported vector type for insertps/pinsrd");
12004 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
12005 auto FromV2Predicate = [](const int &i) { return i >= 4; };
12006 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12010 unsigned DestIndex;
12014 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12017 // If we have 1 element from each vector, we have to check if we're
12018 // changing V1's element's place. If so, we're done. Otherwise, we
12019 // should assume we're changing V2's element's place and behave
12021 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12022 assert(DestIndex <= INT32_MAX && "truncated destination index");
12023 if (FromV1 == FromV2 &&
12024 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12028 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12031 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12032 "More than one element from V1 and from V2, or no elements from one "
12033 "of the vectors. This case should not have returned true from "
12038 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12041 // Get an index into the source vector in the range [0,4) (the mask is
12042 // in the range [0,8) because it can address V1 and V2)
12043 unsigned SrcIndex = Mask[DestIndex] % 4;
12044 if (MayFoldLoad(From)) {
12045 // Trivial case, when From comes from a load and is only used by the
12046 // shuffle. Make it use insertps from the vector that we need from that
12049 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12050 if (!NewLoad.getNode())
12053 if (EVT == MVT::f32) {
12054 // Create this as a scalar to vector to match the instruction pattern.
12055 SDValue LoadScalarToVector =
12056 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12057 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12058 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12060 } else { // EVT == MVT::i32
12061 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12062 // instruction, to match the PINSRD instruction, which loads an i32 to a
12063 // certain vector element.
12064 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12065 DAG.getConstant(DestIndex, MVT::i32));
12069 // Vector-element-to-vector
12070 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12071 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12074 // Reduce a vector shuffle to zext.
12075 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12076 SelectionDAG &DAG) {
12077 // PMOVZX is only available from SSE41.
12078 if (!Subtarget->hasSSE41())
12081 MVT VT = Op.getSimpleValueType();
12083 // Only AVX2 support 256-bit vector integer extending.
12084 if (!Subtarget->hasInt256() && VT.is256BitVector())
12087 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12089 SDValue V1 = Op.getOperand(0);
12090 SDValue V2 = Op.getOperand(1);
12091 unsigned NumElems = VT.getVectorNumElements();
12093 // Extending is an unary operation and the element type of the source vector
12094 // won't be equal to or larger than i64.
12095 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12096 VT.getVectorElementType() == MVT::i64)
12099 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12100 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12101 while ((1U << Shift) < NumElems) {
12102 if (SVOp->getMaskElt(1U << Shift) == 1)
12105 // The maximal ratio is 8, i.e. from i8 to i64.
12110 // Check the shuffle mask.
12111 unsigned Mask = (1U << Shift) - 1;
12112 for (unsigned i = 0; i != NumElems; ++i) {
12113 int EltIdx = SVOp->getMaskElt(i);
12114 if ((i & Mask) != 0 && EltIdx != -1)
12116 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12120 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12121 MVT NeVT = MVT::getIntegerVT(NBits);
12122 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12124 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12127 return DAG.getNode(ISD::BITCAST, DL, VT,
12128 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12131 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12132 SelectionDAG &DAG) {
12133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12134 MVT VT = Op.getSimpleValueType();
12136 SDValue V1 = Op.getOperand(0);
12137 SDValue V2 = Op.getOperand(1);
12139 if (isZeroShuffle(SVOp))
12140 return getZeroVector(VT, Subtarget, DAG, dl);
12142 // Handle splat operations
12143 if (SVOp->isSplat()) {
12144 // Use vbroadcast whenever the splat comes from a foldable load
12145 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12146 if (Broadcast.getNode())
12150 // Check integer expanding shuffles.
12151 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12152 if (NewOp.getNode())
12155 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12157 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12158 VT == MVT::v32i8) {
12159 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12160 if (NewOp.getNode())
12161 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12162 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12163 // FIXME: Figure out a cleaner way to do this.
12164 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12165 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12166 if (NewOp.getNode()) {
12167 MVT NewVT = NewOp.getSimpleValueType();
12168 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12169 NewVT, true, false))
12170 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12173 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12174 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12175 if (NewOp.getNode()) {
12176 MVT NewVT = NewOp.getSimpleValueType();
12177 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12178 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12187 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12188 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12189 SDValue V1 = Op.getOperand(0);
12190 SDValue V2 = Op.getOperand(1);
12191 MVT VT = Op.getSimpleValueType();
12193 unsigned NumElems = VT.getVectorNumElements();
12194 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12195 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12196 bool V1IsSplat = false;
12197 bool V2IsSplat = false;
12198 bool HasSSE2 = Subtarget->hasSSE2();
12199 bool HasFp256 = Subtarget->hasFp256();
12200 bool HasInt256 = Subtarget->hasInt256();
12201 MachineFunction &MF = DAG.getMachineFunction();
12202 bool OptForSize = MF.getFunction()->getAttributes().
12203 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12205 // Check if we should use the experimental vector shuffle lowering. If so,
12206 // delegate completely to that code path.
12207 if (ExperimentalVectorShuffleLowering)
12208 return lowerVectorShuffle(Op, Subtarget, DAG);
12210 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12212 if (V1IsUndef && V2IsUndef)
12213 return DAG.getUNDEF(VT);
12215 // When we create a shuffle node we put the UNDEF node to second operand,
12216 // but in some cases the first operand may be transformed to UNDEF.
12217 // In this case we should just commute the node.
12219 return DAG.getCommutedVectorShuffle(*SVOp);
12221 // Vector shuffle lowering takes 3 steps:
12223 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12224 // narrowing and commutation of operands should be handled.
12225 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12227 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12228 // so the shuffle can be broken into other shuffles and the legalizer can
12229 // try the lowering again.
12231 // The general idea is that no vector_shuffle operation should be left to
12232 // be matched during isel, all of them must be converted to a target specific
12235 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12236 // narrowing and commutation of operands should be handled. The actual code
12237 // doesn't include all of those, work in progress...
12238 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12239 if (NewOp.getNode())
12242 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12244 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12245 // unpckh_undef). Only use pshufd if speed is more important than size.
12246 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12247 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12248 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12249 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12251 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12252 V2IsUndef && MayFoldVectorLoad(V1))
12253 return getMOVDDup(Op, dl, V1, DAG);
12255 if (isMOVHLPS_v_undef_Mask(M, VT))
12256 return getMOVHighToLow(Op, dl, DAG);
12258 // Use to match splats
12259 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12260 (VT == MVT::v2f64 || VT == MVT::v2i64))
12261 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12263 if (isPSHUFDMask(M, VT)) {
12264 // The actual implementation will match the mask in the if above and then
12265 // during isel it can match several different instructions, not only pshufd
12266 // as its name says, sad but true, emulate the behavior for now...
12267 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12268 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12270 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12272 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12273 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12275 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12276 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12279 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12283 if (isPALIGNRMask(M, VT, Subtarget))
12284 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12285 getShufflePALIGNRImmediate(SVOp),
12288 if (isVALIGNMask(M, VT, Subtarget))
12289 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12290 getShuffleVALIGNImmediate(SVOp),
12293 // Check if this can be converted into a logical shift.
12294 bool isLeft = false;
12295 unsigned ShAmt = 0;
12297 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12298 if (isShift && ShVal.hasOneUse()) {
12299 // If the shifted value has multiple uses, it may be cheaper to use
12300 // v_set0 + movlhps or movhlps, etc.
12301 MVT EltVT = VT.getVectorElementType();
12302 ShAmt *= EltVT.getSizeInBits();
12303 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12306 if (isMOVLMask(M, VT)) {
12307 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12308 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12309 if (!isMOVLPMask(M, VT)) {
12310 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12311 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12313 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12314 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12318 // FIXME: fold these into legal mask.
12319 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12320 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12322 if (isMOVHLPSMask(M, VT))
12323 return getMOVHighToLow(Op, dl, DAG);
12325 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12326 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12328 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12329 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12331 if (isMOVLPMask(M, VT))
12332 return getMOVLP(Op, dl, DAG, HasSSE2);
12334 if (ShouldXformToMOVHLPS(M, VT) ||
12335 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12336 return DAG.getCommutedVectorShuffle(*SVOp);
12339 // No better options. Use a vshldq / vsrldq.
12340 MVT EltVT = VT.getVectorElementType();
12341 ShAmt *= EltVT.getSizeInBits();
12342 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12345 bool Commuted = false;
12346 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12347 // 1,1,1,1 -> v8i16 though.
12348 BitVector UndefElements;
12349 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12350 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12352 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12353 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12356 // Canonicalize the splat or undef, if present, to be on the RHS.
12357 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12358 CommuteVectorShuffleMask(M, NumElems);
12360 std::swap(V1IsSplat, V2IsSplat);
12364 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12365 // Shuffling low element of v1 into undef, just return v1.
12368 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12369 // the instruction selector will not match, so get a canonical MOVL with
12370 // swapped operands to undo the commute.
12371 return getMOVL(DAG, dl, VT, V2, V1);
12374 if (isUNPCKLMask(M, VT, HasInt256))
12375 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12377 if (isUNPCKHMask(M, VT, HasInt256))
12378 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12381 // Normalize mask so all entries that point to V2 points to its first
12382 // element then try to match unpck{h|l} again. If match, return a
12383 // new vector_shuffle with the corrected mask.p
12384 SmallVector<int, 8> NewMask(M.begin(), M.end());
12385 NormalizeMask(NewMask, NumElems);
12386 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12387 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12388 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12389 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12393 // Commute is back and try unpck* again.
12394 // FIXME: this seems wrong.
12395 CommuteVectorShuffleMask(M, NumElems);
12397 std::swap(V1IsSplat, V2IsSplat);
12399 if (isUNPCKLMask(M, VT, HasInt256))
12400 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12402 if (isUNPCKHMask(M, VT, HasInt256))
12403 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12406 // Normalize the node to match x86 shuffle ops if needed
12407 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12408 return DAG.getCommutedVectorShuffle(*SVOp);
12410 // The checks below are all present in isShuffleMaskLegal, but they are
12411 // inlined here right now to enable us to directly emit target specific
12412 // nodes, and remove one by one until they don't return Op anymore.
12414 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12415 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12416 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12417 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12420 if (isPSHUFHWMask(M, VT, HasInt256))
12421 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12422 getShufflePSHUFHWImmediate(SVOp),
12425 if (isPSHUFLWMask(M, VT, HasInt256))
12426 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12427 getShufflePSHUFLWImmediate(SVOp),
12430 unsigned MaskValue;
12431 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12433 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12435 if (isSHUFPMask(M, VT))
12436 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12437 getShuffleSHUFImmediate(SVOp), DAG);
12439 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12440 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12441 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12442 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12444 //===--------------------------------------------------------------------===//
12445 // Generate target specific nodes for 128 or 256-bit shuffles only
12446 // supported in the AVX instruction set.
12449 // Handle VMOVDDUPY permutations
12450 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12451 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12453 // Handle VPERMILPS/D* permutations
12454 if (isVPERMILPMask(M, VT)) {
12455 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12456 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12457 getShuffleSHUFImmediate(SVOp), DAG);
12458 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12459 getShuffleSHUFImmediate(SVOp), DAG);
12463 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12464 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12465 Idx*(NumElems/2), DAG, dl);
12467 // Handle VPERM2F128/VPERM2I128 permutations
12468 if (isVPERM2X128Mask(M, VT, HasFp256))
12469 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12470 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12472 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12473 return getINSERTPS(SVOp, dl, DAG);
12476 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12477 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12479 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12480 VT.is512BitVector()) {
12481 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12482 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12483 SmallVector<SDValue, 16> permclMask;
12484 for (unsigned i = 0; i != NumElems; ++i) {
12485 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12488 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12490 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12491 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12492 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12493 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12494 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12497 //===--------------------------------------------------------------------===//
12498 // Since no target specific shuffle was selected for this generic one,
12499 // lower it into other known shuffles. FIXME: this isn't true yet, but
12500 // this is the plan.
12503 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12504 if (VT == MVT::v8i16) {
12505 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12506 if (NewOp.getNode())
12510 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12511 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12512 if (NewOp.getNode())
12516 if (VT == MVT::v16i8) {
12517 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12518 if (NewOp.getNode())
12522 if (VT == MVT::v32i8) {
12523 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12524 if (NewOp.getNode())
12528 // Handle all 128-bit wide vectors with 4 elements, and match them with
12529 // several different shuffle types.
12530 if (NumElems == 4 && VT.is128BitVector())
12531 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12533 // Handle general 256-bit shuffles
12534 if (VT.is256BitVector())
12535 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12540 // This function assumes its argument is a BUILD_VECTOR of constants or
12541 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12543 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12544 unsigned &MaskValue) {
12546 unsigned NumElems = BuildVector->getNumOperands();
12547 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12548 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12549 unsigned NumElemsInLane = NumElems / NumLanes;
12551 // Blend for v16i16 should be symetric for the both lanes.
12552 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12553 SDValue EltCond = BuildVector->getOperand(i);
12554 SDValue SndLaneEltCond =
12555 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12557 int Lane1Cond = -1, Lane2Cond = -1;
12558 if (isa<ConstantSDNode>(EltCond))
12559 Lane1Cond = !isZero(EltCond);
12560 if (isa<ConstantSDNode>(SndLaneEltCond))
12561 Lane2Cond = !isZero(SndLaneEltCond);
12563 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12564 // Lane1Cond != 0, means we want the first argument.
12565 // Lane1Cond == 0, means we want the second argument.
12566 // The encoding of this argument is 0 for the first argument, 1
12567 // for the second. Therefore, invert the condition.
12568 MaskValue |= !Lane1Cond << i;
12569 else if (Lane1Cond < 0)
12570 MaskValue |= !Lane2Cond << i;
12577 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12579 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12580 SelectionDAG &DAG) {
12581 SDValue Cond = Op.getOperand(0);
12582 SDValue LHS = Op.getOperand(1);
12583 SDValue RHS = Op.getOperand(2);
12585 MVT VT = Op.getSimpleValueType();
12586 MVT EltVT = VT.getVectorElementType();
12587 unsigned NumElems = VT.getVectorNumElements();
12589 // There is no blend with immediate in AVX-512.
12590 if (VT.is512BitVector())
12593 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12595 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12598 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12601 // Check the mask for BLEND and build the value.
12602 unsigned MaskValue = 0;
12603 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12606 // Convert i32 vectors to floating point if it is not AVX2.
12607 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12609 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12610 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12612 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12613 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12616 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12617 DAG.getConstant(MaskValue, MVT::i32));
12618 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12621 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12622 // A vselect where all conditions and data are constants can be optimized into
12623 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12624 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12625 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12626 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12629 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12630 if (BlendOp.getNode())
12633 // Some types for vselect were previously set to Expand, not Legal or
12634 // Custom. Return an empty SDValue so we fall-through to Expand, after
12635 // the Custom lowering phase.
12636 MVT VT = Op.getSimpleValueType();
12637 switch (VT.SimpleTy) {
12642 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12647 // We couldn't create a "Blend with immediate" node.
12648 // This node should still be legal, but we'll have to emit a blendv*
12653 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12654 MVT VT = Op.getSimpleValueType();
12657 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12660 if (VT.getSizeInBits() == 8) {
12661 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12662 Op.getOperand(0), Op.getOperand(1));
12663 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12664 DAG.getValueType(VT));
12665 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12668 if (VT.getSizeInBits() == 16) {
12669 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12670 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12672 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12673 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12674 DAG.getNode(ISD::BITCAST, dl,
12677 Op.getOperand(1)));
12678 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12679 Op.getOperand(0), Op.getOperand(1));
12680 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12681 DAG.getValueType(VT));
12682 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12685 if (VT == MVT::f32) {
12686 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12687 // the result back to FR32 register. It's only worth matching if the
12688 // result has a single use which is a store or a bitcast to i32. And in
12689 // the case of a store, it's not worth it if the index is a constant 0,
12690 // because a MOVSSmr can be used instead, which is smaller and faster.
12691 if (!Op.hasOneUse())
12693 SDNode *User = *Op.getNode()->use_begin();
12694 if ((User->getOpcode() != ISD::STORE ||
12695 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12696 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12697 (User->getOpcode() != ISD::BITCAST ||
12698 User->getValueType(0) != MVT::i32))
12700 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12701 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12704 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12707 if (VT == MVT::i32 || VT == MVT::i64) {
12708 // ExtractPS/pextrq works with constant index.
12709 if (isa<ConstantSDNode>(Op.getOperand(1)))
12715 /// Extract one bit from mask vector, like v16i1 or v8i1.
12716 /// AVX-512 feature.
12718 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12719 SDValue Vec = Op.getOperand(0);
12721 MVT VecVT = Vec.getSimpleValueType();
12722 SDValue Idx = Op.getOperand(1);
12723 MVT EltVT = Op.getSimpleValueType();
12725 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12727 // variable index can't be handled in mask registers,
12728 // extend vector to VR512
12729 if (!isa<ConstantSDNode>(Idx)) {
12730 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12731 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12732 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12733 ExtVT.getVectorElementType(), Ext, Idx);
12734 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12737 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12738 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12739 unsigned MaxSift = rc->getSize()*8 - 1;
12740 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12741 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12742 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12743 DAG.getConstant(MaxSift, MVT::i8));
12744 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12745 DAG.getIntPtrConstant(0));
12749 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12750 SelectionDAG &DAG) const {
12752 SDValue Vec = Op.getOperand(0);
12753 MVT VecVT = Vec.getSimpleValueType();
12754 SDValue Idx = Op.getOperand(1);
12756 if (Op.getSimpleValueType() == MVT::i1)
12757 return ExtractBitFromMaskVector(Op, DAG);
12759 if (!isa<ConstantSDNode>(Idx)) {
12760 if (VecVT.is512BitVector() ||
12761 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12762 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12765 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12766 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12767 MaskEltVT.getSizeInBits());
12769 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12770 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12771 getZeroVector(MaskVT, Subtarget, DAG, dl),
12772 Idx, DAG.getConstant(0, getPointerTy()));
12773 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12774 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12775 Perm, DAG.getConstant(0, getPointerTy()));
12780 // If this is a 256-bit vector result, first extract the 128-bit vector and
12781 // then extract the element from the 128-bit vector.
12782 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12784 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12785 // Get the 128-bit vector.
12786 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12787 MVT EltVT = VecVT.getVectorElementType();
12789 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12791 //if (IdxVal >= NumElems/2)
12792 // IdxVal -= NumElems/2;
12793 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12794 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12795 DAG.getConstant(IdxVal, MVT::i32));
12798 assert(VecVT.is128BitVector() && "Unexpected vector length");
12800 if (Subtarget->hasSSE41()) {
12801 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12806 MVT VT = Op.getSimpleValueType();
12807 // TODO: handle v16i8.
12808 if (VT.getSizeInBits() == 16) {
12809 SDValue Vec = Op.getOperand(0);
12810 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12812 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12813 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12814 DAG.getNode(ISD::BITCAST, dl,
12816 Op.getOperand(1)));
12817 // Transform it so it match pextrw which produces a 32-bit result.
12818 MVT EltVT = MVT::i32;
12819 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12820 Op.getOperand(0), Op.getOperand(1));
12821 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12822 DAG.getValueType(VT));
12823 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12826 if (VT.getSizeInBits() == 32) {
12827 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12831 // SHUFPS the element to the lowest double word, then movss.
12832 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12833 MVT VVT = Op.getOperand(0).getSimpleValueType();
12834 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12835 DAG.getUNDEF(VVT), Mask);
12836 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12837 DAG.getIntPtrConstant(0));
12840 if (VT.getSizeInBits() == 64) {
12841 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12842 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12843 // to match extract_elt for f64.
12844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12848 // UNPCKHPD the element to the lowest double word, then movsd.
12849 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12850 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12851 int Mask[2] = { 1, -1 };
12852 MVT VVT = Op.getOperand(0).getSimpleValueType();
12853 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12854 DAG.getUNDEF(VVT), Mask);
12855 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12856 DAG.getIntPtrConstant(0));
12862 /// Insert one bit to mask vector, like v16i1 or v8i1.
12863 /// AVX-512 feature.
12865 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12867 SDValue Vec = Op.getOperand(0);
12868 SDValue Elt = Op.getOperand(1);
12869 SDValue Idx = Op.getOperand(2);
12870 MVT VecVT = Vec.getSimpleValueType();
12872 if (!isa<ConstantSDNode>(Idx)) {
12873 // Non constant index. Extend source and destination,
12874 // insert element and then truncate the result.
12875 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12876 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12877 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12878 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12879 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12880 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12883 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12884 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12885 if (Vec.getOpcode() == ISD::UNDEF)
12886 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12887 DAG.getConstant(IdxVal, MVT::i8));
12888 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12889 unsigned MaxSift = rc->getSize()*8 - 1;
12890 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12891 DAG.getConstant(MaxSift, MVT::i8));
12892 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12893 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12894 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12897 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12898 SelectionDAG &DAG) const {
12899 MVT VT = Op.getSimpleValueType();
12900 MVT EltVT = VT.getVectorElementType();
12902 if (EltVT == MVT::i1)
12903 return InsertBitToMaskVector(Op, DAG);
12906 SDValue N0 = Op.getOperand(0);
12907 SDValue N1 = Op.getOperand(1);
12908 SDValue N2 = Op.getOperand(2);
12909 if (!isa<ConstantSDNode>(N2))
12911 auto *N2C = cast<ConstantSDNode>(N2);
12912 unsigned IdxVal = N2C->getZExtValue();
12914 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12915 // into that, and then insert the subvector back into the result.
12916 if (VT.is256BitVector() || VT.is512BitVector()) {
12917 // Get the desired 128-bit vector half.
12918 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12920 // Insert the element into the desired half.
12921 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12922 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12924 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12925 DAG.getConstant(IdxIn128, MVT::i32));
12927 // Insert the changed part back to the 256-bit vector
12928 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12930 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12932 if (Subtarget->hasSSE41()) {
12933 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12935 if (VT == MVT::v8i16) {
12936 Opc = X86ISD::PINSRW;
12938 assert(VT == MVT::v16i8);
12939 Opc = X86ISD::PINSRB;
12942 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12944 if (N1.getValueType() != MVT::i32)
12945 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12946 if (N2.getValueType() != MVT::i32)
12947 N2 = DAG.getIntPtrConstant(IdxVal);
12948 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12951 if (EltVT == MVT::f32) {
12952 // Bits [7:6] of the constant are the source select. This will always be
12953 // zero here. The DAG Combiner may combine an extract_elt index into
12955 // bits. For example (insert (extract, 3), 2) could be matched by
12957 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12958 // Bits [5:4] of the constant are the destination select. This is the
12959 // value of the incoming immediate.
12960 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12961 // combine either bitwise AND or insert of float 0.0 to set these bits.
12962 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12963 // Create this as a scalar to vector..
12964 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12965 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12968 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12969 // PINSR* works with constant index.
12974 if (EltVT == MVT::i8)
12977 if (EltVT.getSizeInBits() == 16) {
12978 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12979 // as its second argument.
12980 if (N1.getValueType() != MVT::i32)
12981 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12982 if (N2.getValueType() != MVT::i32)
12983 N2 = DAG.getIntPtrConstant(IdxVal);
12984 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12989 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12991 MVT OpVT = Op.getSimpleValueType();
12993 // If this is a 256-bit vector result, first insert into a 128-bit
12994 // vector and then insert into the 256-bit vector.
12995 if (!OpVT.is128BitVector()) {
12996 // Insert into a 128-bit vector.
12997 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12998 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12999 OpVT.getVectorNumElements() / SizeFactor);
13001 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
13003 // Insert the 128-bit vector.
13004 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
13007 if (OpVT == MVT::v1i64 &&
13008 Op.getOperand(0).getValueType() == MVT::i64)
13009 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13011 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13012 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13013 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13014 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13017 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13018 // a simple subregister reference or explicit instructions to grab
13019 // upper bits of a vector.
13020 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13021 SelectionDAG &DAG) {
13023 SDValue In = Op.getOperand(0);
13024 SDValue Idx = Op.getOperand(1);
13025 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13026 MVT ResVT = Op.getSimpleValueType();
13027 MVT InVT = In.getSimpleValueType();
13029 if (Subtarget->hasFp256()) {
13030 if (ResVT.is128BitVector() &&
13031 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13032 isa<ConstantSDNode>(Idx)) {
13033 return Extract128BitVector(In, IdxVal, DAG, dl);
13035 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13036 isa<ConstantSDNode>(Idx)) {
13037 return Extract256BitVector(In, IdxVal, DAG, dl);
13043 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13044 // simple superregister reference or explicit instructions to insert
13045 // the upper bits of a vector.
13046 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13047 SelectionDAG &DAG) {
13048 if (Subtarget->hasFp256()) {
13049 SDLoc dl(Op.getNode());
13050 SDValue Vec = Op.getNode()->getOperand(0);
13051 SDValue SubVec = Op.getNode()->getOperand(1);
13052 SDValue Idx = Op.getNode()->getOperand(2);
13054 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13055 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13056 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13057 isa<ConstantSDNode>(Idx)) {
13058 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13059 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13062 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13063 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13064 isa<ConstantSDNode>(Idx)) {
13065 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13066 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13072 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13073 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13074 // one of the above mentioned nodes. It has to be wrapped because otherwise
13075 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13076 // be used to form addressing mode. These wrapped nodes will be selected
13079 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13080 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13082 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13083 // global base reg.
13084 unsigned char OpFlag = 0;
13085 unsigned WrapperKind = X86ISD::Wrapper;
13086 CodeModel::Model M = DAG.getTarget().getCodeModel();
13088 if (Subtarget->isPICStyleRIPRel() &&
13089 (M == CodeModel::Small || M == CodeModel::Kernel))
13090 WrapperKind = X86ISD::WrapperRIP;
13091 else if (Subtarget->isPICStyleGOT())
13092 OpFlag = X86II::MO_GOTOFF;
13093 else if (Subtarget->isPICStyleStubPIC())
13094 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13096 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13097 CP->getAlignment(),
13098 CP->getOffset(), OpFlag);
13100 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13101 // With PIC, the address is actually $g + Offset.
13103 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13104 DAG.getNode(X86ISD::GlobalBaseReg,
13105 SDLoc(), getPointerTy()),
13112 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13113 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13115 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13116 // global base reg.
13117 unsigned char OpFlag = 0;
13118 unsigned WrapperKind = X86ISD::Wrapper;
13119 CodeModel::Model M = DAG.getTarget().getCodeModel();
13121 if (Subtarget->isPICStyleRIPRel() &&
13122 (M == CodeModel::Small || M == CodeModel::Kernel))
13123 WrapperKind = X86ISD::WrapperRIP;
13124 else if (Subtarget->isPICStyleGOT())
13125 OpFlag = X86II::MO_GOTOFF;
13126 else if (Subtarget->isPICStyleStubPIC())
13127 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13129 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13132 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13134 // With PIC, the address is actually $g + Offset.
13136 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13137 DAG.getNode(X86ISD::GlobalBaseReg,
13138 SDLoc(), getPointerTy()),
13145 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13146 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13148 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13149 // global base reg.
13150 unsigned char OpFlag = 0;
13151 unsigned WrapperKind = X86ISD::Wrapper;
13152 CodeModel::Model M = DAG.getTarget().getCodeModel();
13154 if (Subtarget->isPICStyleRIPRel() &&
13155 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13156 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13157 OpFlag = X86II::MO_GOTPCREL;
13158 WrapperKind = X86ISD::WrapperRIP;
13159 } else if (Subtarget->isPICStyleGOT()) {
13160 OpFlag = X86II::MO_GOT;
13161 } else if (Subtarget->isPICStyleStubPIC()) {
13162 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13163 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13164 OpFlag = X86II::MO_DARWIN_NONLAZY;
13167 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13170 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13172 // With PIC, the address is actually $g + Offset.
13173 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13174 !Subtarget->is64Bit()) {
13175 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13176 DAG.getNode(X86ISD::GlobalBaseReg,
13177 SDLoc(), getPointerTy()),
13181 // For symbols that require a load from a stub to get the address, emit the
13183 if (isGlobalStubReference(OpFlag))
13184 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13185 MachinePointerInfo::getGOT(), false, false, false, 0);
13191 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13192 // Create the TargetBlockAddressAddress node.
13193 unsigned char OpFlags =
13194 Subtarget->ClassifyBlockAddressReference();
13195 CodeModel::Model M = DAG.getTarget().getCodeModel();
13196 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13197 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13199 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13202 if (Subtarget->isPICStyleRIPRel() &&
13203 (M == CodeModel::Small || M == CodeModel::Kernel))
13204 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13206 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13208 // With PIC, the address is actually $g + Offset.
13209 if (isGlobalRelativeToPICBase(OpFlags)) {
13210 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13211 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13219 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13220 int64_t Offset, SelectionDAG &DAG) const {
13221 // Create the TargetGlobalAddress node, folding in the constant
13222 // offset if it is legal.
13223 unsigned char OpFlags =
13224 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13225 CodeModel::Model M = DAG.getTarget().getCodeModel();
13227 if (OpFlags == X86II::MO_NO_FLAG &&
13228 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13229 // A direct static reference to a global.
13230 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13233 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13236 if (Subtarget->isPICStyleRIPRel() &&
13237 (M == CodeModel::Small || M == CodeModel::Kernel))
13238 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13240 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13242 // With PIC, the address is actually $g + Offset.
13243 if (isGlobalRelativeToPICBase(OpFlags)) {
13244 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13245 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13249 // For globals that require a load from a stub to get the address, emit the
13251 if (isGlobalStubReference(OpFlags))
13252 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13253 MachinePointerInfo::getGOT(), false, false, false, 0);
13255 // If there was a non-zero offset that we didn't fold, create an explicit
13256 // addition for it.
13258 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13259 DAG.getConstant(Offset, getPointerTy()));
13265 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13266 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13267 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13268 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13272 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13273 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13274 unsigned char OperandFlags, bool LocalDynamic = false) {
13275 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13276 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13278 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13279 GA->getValueType(0),
13283 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13287 SDValue Ops[] = { Chain, TGA, *InFlag };
13288 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13290 SDValue Ops[] = { Chain, TGA };
13291 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13294 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13295 MFI->setAdjustsStack(true);
13296 MFI->setHasCalls(true);
13298 SDValue Flag = Chain.getValue(1);
13299 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13302 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13304 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13307 SDLoc dl(GA); // ? function entry point might be better
13308 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13309 DAG.getNode(X86ISD::GlobalBaseReg,
13310 SDLoc(), PtrVT), InFlag);
13311 InFlag = Chain.getValue(1);
13313 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13316 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13318 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13320 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13321 X86::RAX, X86II::MO_TLSGD);
13324 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13330 // Get the start address of the TLS block for this module.
13331 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13332 .getInfo<X86MachineFunctionInfo>();
13333 MFI->incNumLocalDynamicTLSAccesses();
13337 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13338 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13341 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13342 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13343 InFlag = Chain.getValue(1);
13344 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13345 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13348 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13352 unsigned char OperandFlags = X86II::MO_DTPOFF;
13353 unsigned WrapperKind = X86ISD::Wrapper;
13354 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13355 GA->getValueType(0),
13356 GA->getOffset(), OperandFlags);
13357 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13359 // Add x@dtpoff with the base.
13360 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13363 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13364 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13365 const EVT PtrVT, TLSModel::Model model,
13366 bool is64Bit, bool isPIC) {
13369 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13370 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13371 is64Bit ? 257 : 256));
13373 SDValue ThreadPointer =
13374 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13375 MachinePointerInfo(Ptr), false, false, false, 0);
13377 unsigned char OperandFlags = 0;
13378 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13380 unsigned WrapperKind = X86ISD::Wrapper;
13381 if (model == TLSModel::LocalExec) {
13382 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13383 } else if (model == TLSModel::InitialExec) {
13385 OperandFlags = X86II::MO_GOTTPOFF;
13386 WrapperKind = X86ISD::WrapperRIP;
13388 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13391 llvm_unreachable("Unexpected model");
13394 // emit "addl x@ntpoff,%eax" (local exec)
13395 // or "addl x@indntpoff,%eax" (initial exec)
13396 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13398 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13399 GA->getOffset(), OperandFlags);
13400 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13402 if (model == TLSModel::InitialExec) {
13403 if (isPIC && !is64Bit) {
13404 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13405 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13409 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13410 MachinePointerInfo::getGOT(), false, false, false, 0);
13413 // The address of the thread local variable is the add of the thread
13414 // pointer with the offset of the variable.
13415 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13419 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13421 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13422 const GlobalValue *GV = GA->getGlobal();
13424 if (Subtarget->isTargetELF()) {
13425 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13428 case TLSModel::GeneralDynamic:
13429 if (Subtarget->is64Bit())
13430 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13431 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13432 case TLSModel::LocalDynamic:
13433 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13434 Subtarget->is64Bit());
13435 case TLSModel::InitialExec:
13436 case TLSModel::LocalExec:
13437 return LowerToTLSExecModel(
13438 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13439 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13441 llvm_unreachable("Unknown TLS model.");
13444 if (Subtarget->isTargetDarwin()) {
13445 // Darwin only has one model of TLS. Lower to that.
13446 unsigned char OpFlag = 0;
13447 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13448 X86ISD::WrapperRIP : X86ISD::Wrapper;
13450 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13451 // global base reg.
13452 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13453 !Subtarget->is64Bit();
13455 OpFlag = X86II::MO_TLVP_PIC_BASE;
13457 OpFlag = X86II::MO_TLVP;
13459 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13460 GA->getValueType(0),
13461 GA->getOffset(), OpFlag);
13462 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13464 // With PIC32, the address is actually $g + Offset.
13466 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13467 DAG.getNode(X86ISD::GlobalBaseReg,
13468 SDLoc(), getPointerTy()),
13471 // Lowering the machine isd will make sure everything is in the right
13473 SDValue Chain = DAG.getEntryNode();
13474 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13475 SDValue Args[] = { Chain, Offset };
13476 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13478 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13479 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13480 MFI->setAdjustsStack(true);
13482 // And our return value (tls address) is in the standard call return value
13484 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13485 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13486 Chain.getValue(1));
13489 if (Subtarget->isTargetKnownWindowsMSVC() ||
13490 Subtarget->isTargetWindowsGNU()) {
13491 // Just use the implicit TLS architecture
13492 // Need to generate someting similar to:
13493 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13495 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13496 // mov rcx, qword [rdx+rcx*8]
13497 // mov eax, .tls$:tlsvar
13498 // [rax+rcx] contains the address
13499 // Windows 64bit: gs:0x58
13500 // Windows 32bit: fs:__tls_array
13503 SDValue Chain = DAG.getEntryNode();
13505 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13506 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13507 // use its literal value of 0x2C.
13508 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13509 ? Type::getInt8PtrTy(*DAG.getContext(),
13511 : Type::getInt32PtrTy(*DAG.getContext(),
13515 Subtarget->is64Bit()
13516 ? DAG.getIntPtrConstant(0x58)
13517 : (Subtarget->isTargetWindowsGNU()
13518 ? DAG.getIntPtrConstant(0x2C)
13519 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13521 SDValue ThreadPointer =
13522 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13523 MachinePointerInfo(Ptr), false, false, false, 0);
13525 // Load the _tls_index variable
13526 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13527 if (Subtarget->is64Bit())
13528 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13529 IDX, MachinePointerInfo(), MVT::i32,
13530 false, false, false, 0);
13532 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13533 false, false, false, 0);
13535 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13537 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13539 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13540 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13541 false, false, false, 0);
13543 // Get the offset of start of .tls section
13544 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13545 GA->getValueType(0),
13546 GA->getOffset(), X86II::MO_SECREL);
13547 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13549 // The address of the thread local variable is the add of the thread
13550 // pointer with the offset of the variable.
13551 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13554 llvm_unreachable("TLS not implemented for this target.");
13557 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13558 /// and take a 2 x i32 value to shift plus a shift amount.
13559 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13560 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13561 MVT VT = Op.getSimpleValueType();
13562 unsigned VTBits = VT.getSizeInBits();
13564 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13565 SDValue ShOpLo = Op.getOperand(0);
13566 SDValue ShOpHi = Op.getOperand(1);
13567 SDValue ShAmt = Op.getOperand(2);
13568 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13569 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13571 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13572 DAG.getConstant(VTBits - 1, MVT::i8));
13573 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13574 DAG.getConstant(VTBits - 1, MVT::i8))
13575 : DAG.getConstant(0, VT);
13577 SDValue Tmp2, Tmp3;
13578 if (Op.getOpcode() == ISD::SHL_PARTS) {
13579 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13580 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13582 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13583 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13586 // If the shift amount is larger or equal than the width of a part we can't
13587 // rely on the results of shld/shrd. Insert a test and select the appropriate
13588 // values for large shift amounts.
13589 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13590 DAG.getConstant(VTBits, MVT::i8));
13591 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13592 AndNode, DAG.getConstant(0, MVT::i8));
13595 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13596 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13597 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13599 if (Op.getOpcode() == ISD::SHL_PARTS) {
13600 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13601 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13603 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13604 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13607 SDValue Ops[2] = { Lo, Hi };
13608 return DAG.getMergeValues(Ops, dl);
13611 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13612 SelectionDAG &DAG) const {
13613 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13616 if (SrcVT.isVector()) {
13617 if (SrcVT.getVectorElementType() == MVT::i1) {
13618 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13619 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13620 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13621 Op.getOperand(0)));
13626 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13627 "Unknown SINT_TO_FP to lower!");
13629 // These are really Legal; return the operand so the caller accepts it as
13631 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13633 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13634 Subtarget->is64Bit()) {
13638 unsigned Size = SrcVT.getSizeInBits()/8;
13639 MachineFunction &MF = DAG.getMachineFunction();
13640 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13641 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13642 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13644 MachinePointerInfo::getFixedStack(SSFI),
13646 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13649 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13651 SelectionDAG &DAG) const {
13655 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13657 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13659 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13661 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13663 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13664 MachineMemOperand *MMO;
13666 int SSFI = FI->getIndex();
13668 DAG.getMachineFunction()
13669 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13670 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13672 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13673 StackSlot = StackSlot.getOperand(1);
13675 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13676 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13678 Tys, Ops, SrcVT, MMO);
13681 Chain = Result.getValue(1);
13682 SDValue InFlag = Result.getValue(2);
13684 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13685 // shouldn't be necessary except that RFP cannot be live across
13686 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13687 MachineFunction &MF = DAG.getMachineFunction();
13688 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13689 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13690 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13691 Tys = DAG.getVTList(MVT::Other);
13693 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13695 MachineMemOperand *MMO =
13696 DAG.getMachineFunction()
13697 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13698 MachineMemOperand::MOStore, SSFISize, SSFISize);
13700 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13701 Ops, Op.getValueType(), MMO);
13702 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13703 MachinePointerInfo::getFixedStack(SSFI),
13704 false, false, false, 0);
13710 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13711 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13712 SelectionDAG &DAG) const {
13713 // This algorithm is not obvious. Here it is what we're trying to output:
13716 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13717 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13719 haddpd %xmm0, %xmm0
13721 pshufd $0x4e, %xmm0, %xmm1
13727 LLVMContext *Context = DAG.getContext();
13729 // Build some magic constants.
13730 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13731 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13732 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13734 SmallVector<Constant*,2> CV1;
13736 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13737 APInt(64, 0x4330000000000000ULL))));
13739 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13740 APInt(64, 0x4530000000000000ULL))));
13741 Constant *C1 = ConstantVector::get(CV1);
13742 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13744 // Load the 64-bit value into an XMM register.
13745 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13747 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13748 MachinePointerInfo::getConstantPool(),
13749 false, false, false, 16);
13750 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13751 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13754 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13755 MachinePointerInfo::getConstantPool(),
13756 false, false, false, 16);
13757 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13758 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13761 if (Subtarget->hasSSE3()) {
13762 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13763 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13765 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13766 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13768 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13769 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13774 DAG.getIntPtrConstant(0));
13777 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13778 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13779 SelectionDAG &DAG) const {
13781 // FP constant to bias correct the final result.
13782 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13785 // Load the 32-bit value into an XMM register.
13786 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13789 // Zero out the upper parts of the register.
13790 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13792 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13793 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13794 DAG.getIntPtrConstant(0));
13796 // Or the load with the bias.
13797 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13798 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13799 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13800 MVT::v2f64, Load)),
13801 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13802 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13803 MVT::v2f64, Bias)));
13804 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13805 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13806 DAG.getIntPtrConstant(0));
13808 // Subtract the bias.
13809 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13811 // Handle final rounding.
13812 EVT DestVT = Op.getValueType();
13814 if (DestVT.bitsLT(MVT::f64))
13815 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13816 DAG.getIntPtrConstant(0));
13817 if (DestVT.bitsGT(MVT::f64))
13818 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13820 // Handle final rounding.
13824 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13825 const X86Subtarget &Subtarget) {
13826 // The algorithm is the following:
13827 // #ifdef __SSE4_1__
13828 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13829 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13830 // (uint4) 0x53000000, 0xaa);
13832 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13833 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13835 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13836 // return (float4) lo + fhi;
13839 SDValue V = Op->getOperand(0);
13840 EVT VecIntVT = V.getValueType();
13841 bool Is128 = VecIntVT == MVT::v4i32;
13842 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13843 // If we convert to something else than the supported type, e.g., to v4f64,
13845 if (VecFloatVT != Op->getValueType(0))
13848 unsigned NumElts = VecIntVT.getVectorNumElements();
13849 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13850 "Unsupported custom type");
13851 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13853 // In the #idef/#else code, we have in common:
13854 // - The vector of constants:
13860 // Create the splat vector for 0x4b000000.
13861 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13862 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13863 CstLow, CstLow, CstLow, CstLow};
13864 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13865 makeArrayRef(&CstLowArray[0], NumElts));
13866 // Create the splat vector for 0x53000000.
13867 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13868 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13869 CstHigh, CstHigh, CstHigh, CstHigh};
13870 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13871 makeArrayRef(&CstHighArray[0], NumElts));
13873 // Create the right shift.
13874 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13875 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13876 CstShift, CstShift, CstShift, CstShift};
13877 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13878 makeArrayRef(&CstShiftArray[0], NumElts));
13879 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13882 if (Subtarget.hasSSE41()) {
13883 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13884 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13885 SDValue VecCstLowBitcast =
13886 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13887 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13888 // Low will be bitcasted right away, so do not bother bitcasting back to its
13890 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13891 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13892 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13893 // (uint4) 0x53000000, 0xaa);
13894 SDValue VecCstHighBitcast =
13895 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13896 SDValue VecShiftBitcast =
13897 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13898 // High will be bitcasted right away, so do not bother bitcasting back to
13899 // its original type.
13900 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13901 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13903 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13904 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13905 CstMask, CstMask, CstMask);
13906 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13907 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13908 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13910 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13911 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13914 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13915 SDValue CstFAdd = DAG.getConstantFP(
13916 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13917 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13918 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13919 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13920 makeArrayRef(&CstFAddArray[0], NumElts));
13922 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13923 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13925 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13926 // return (float4) lo + fhi;
13927 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13928 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13931 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13932 SelectionDAG &DAG) const {
13933 SDValue N0 = Op.getOperand(0);
13934 MVT SVT = N0.getSimpleValueType();
13937 switch (SVT.SimpleTy) {
13939 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13944 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13945 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13946 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13950 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13952 llvm_unreachable(nullptr);
13955 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13956 SelectionDAG &DAG) const {
13957 SDValue N0 = Op.getOperand(0);
13960 if (Op.getValueType().isVector())
13961 return lowerUINT_TO_FP_vec(Op, DAG);
13963 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13964 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13965 // the optimization here.
13966 if (DAG.SignBitIsZero(N0))
13967 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13969 MVT SrcVT = N0.getSimpleValueType();
13970 MVT DstVT = Op.getSimpleValueType();
13971 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13972 return LowerUINT_TO_FP_i64(Op, DAG);
13973 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13974 return LowerUINT_TO_FP_i32(Op, DAG);
13975 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13978 // Make a 64-bit buffer, and use it to build an FILD.
13979 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13980 if (SrcVT == MVT::i32) {
13981 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13982 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13983 getPointerTy(), StackSlot, WordOff);
13984 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13985 StackSlot, MachinePointerInfo(),
13987 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13988 OffsetSlot, MachinePointerInfo(),
13990 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13994 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13995 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13996 StackSlot, MachinePointerInfo(),
13998 // For i64 source, we need to add the appropriate power of 2 if the input
13999 // was negative. This is the same as the optimization in
14000 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
14001 // we must be careful to do the computation in x87 extended precision, not
14002 // in SSE. (The generic code can't know it's OK to do this, or how to.)
14003 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
14004 MachineMemOperand *MMO =
14005 DAG.getMachineFunction()
14006 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14007 MachineMemOperand::MOLoad, 8, 8);
14009 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14010 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14011 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14014 APInt FF(32, 0x5F800000ULL);
14016 // Check whether the sign bit is set.
14017 SDValue SignSet = DAG.getSetCC(dl,
14018 getSetCCResultType(*DAG.getContext(), MVT::i64),
14019 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14022 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14023 SDValue FudgePtr = DAG.getConstantPool(
14024 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14027 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14028 SDValue Zero = DAG.getIntPtrConstant(0);
14029 SDValue Four = DAG.getIntPtrConstant(4);
14030 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14032 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14034 // Load the value out, extending it from f32 to f80.
14035 // FIXME: Avoid the extend by constructing the right constant pool?
14036 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14037 FudgePtr, MachinePointerInfo::getConstantPool(),
14038 MVT::f32, false, false, false, 4);
14039 // Extend everything to 80 bits to force it to be done on x87.
14040 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14041 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14044 std::pair<SDValue,SDValue>
14045 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14046 bool IsSigned, bool IsReplace) const {
14049 EVT DstTy = Op.getValueType();
14051 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14052 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14056 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14057 DstTy.getSimpleVT() >= MVT::i16 &&
14058 "Unknown FP_TO_INT to lower!");
14060 // These are really Legal.
14061 if (DstTy == MVT::i32 &&
14062 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14063 return std::make_pair(SDValue(), SDValue());
14064 if (Subtarget->is64Bit() &&
14065 DstTy == MVT::i64 &&
14066 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14067 return std::make_pair(SDValue(), SDValue());
14069 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14070 // stack slot, or into the FTOL runtime function.
14071 MachineFunction &MF = DAG.getMachineFunction();
14072 unsigned MemSize = DstTy.getSizeInBits()/8;
14073 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14074 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14077 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14078 Opc = X86ISD::WIN_FTOL;
14080 switch (DstTy.getSimpleVT().SimpleTy) {
14081 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14082 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14083 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14084 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14087 SDValue Chain = DAG.getEntryNode();
14088 SDValue Value = Op.getOperand(0);
14089 EVT TheVT = Op.getOperand(0).getValueType();
14090 // FIXME This causes a redundant load/store if the SSE-class value is already
14091 // in memory, such as if it is on the callstack.
14092 if (isScalarFPTypeInSSEReg(TheVT)) {
14093 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14094 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14095 MachinePointerInfo::getFixedStack(SSFI),
14097 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14099 Chain, StackSlot, DAG.getValueType(TheVT)
14102 MachineMemOperand *MMO =
14103 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14104 MachineMemOperand::MOLoad, MemSize, MemSize);
14105 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14106 Chain = Value.getValue(1);
14107 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14108 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14111 MachineMemOperand *MMO =
14112 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14113 MachineMemOperand::MOStore, MemSize, MemSize);
14115 if (Opc != X86ISD::WIN_FTOL) {
14116 // Build the FP_TO_INT*_IN_MEM
14117 SDValue Ops[] = { Chain, Value, StackSlot };
14118 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14120 return std::make_pair(FIST, StackSlot);
14122 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14123 DAG.getVTList(MVT::Other, MVT::Glue),
14125 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14126 MVT::i32, ftol.getValue(1));
14127 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14128 MVT::i32, eax.getValue(2));
14129 SDValue Ops[] = { eax, edx };
14130 SDValue pair = IsReplace
14131 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14132 : DAG.getMergeValues(Ops, DL);
14133 return std::make_pair(pair, SDValue());
14137 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14138 const X86Subtarget *Subtarget) {
14139 MVT VT = Op->getSimpleValueType(0);
14140 SDValue In = Op->getOperand(0);
14141 MVT InVT = In.getSimpleValueType();
14144 // Optimize vectors in AVX mode:
14147 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14148 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14149 // Concat upper and lower parts.
14152 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14153 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14154 // Concat upper and lower parts.
14157 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14158 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14159 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14162 if (Subtarget->hasInt256())
14163 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14165 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14166 SDValue Undef = DAG.getUNDEF(InVT);
14167 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14168 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14169 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14171 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14172 VT.getVectorNumElements()/2);
14174 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14175 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14177 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14180 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14181 SelectionDAG &DAG) {
14182 MVT VT = Op->getSimpleValueType(0);
14183 SDValue In = Op->getOperand(0);
14184 MVT InVT = In.getSimpleValueType();
14186 unsigned int NumElts = VT.getVectorNumElements();
14187 if (NumElts != 8 && NumElts != 16)
14190 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14191 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14193 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14194 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14195 // Now we have only mask extension
14196 assert(InVT.getVectorElementType() == MVT::i1);
14197 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14198 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14199 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14200 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14201 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14202 MachinePointerInfo::getConstantPool(),
14203 false, false, false, Alignment);
14205 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14206 if (VT.is512BitVector())
14208 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14211 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14212 SelectionDAG &DAG) {
14213 if (Subtarget->hasFp256()) {
14214 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14222 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14223 SelectionDAG &DAG) {
14225 MVT VT = Op.getSimpleValueType();
14226 SDValue In = Op.getOperand(0);
14227 MVT SVT = In.getSimpleValueType();
14229 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14230 return LowerZERO_EXTEND_AVX512(Op, DAG);
14232 if (Subtarget->hasFp256()) {
14233 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14238 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14239 VT.getVectorNumElements() != SVT.getVectorNumElements());
14243 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14245 MVT VT = Op.getSimpleValueType();
14246 SDValue In = Op.getOperand(0);
14247 MVT InVT = In.getSimpleValueType();
14249 if (VT == MVT::i1) {
14250 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14251 "Invalid scalar TRUNCATE operation");
14252 if (InVT.getSizeInBits() >= 32)
14254 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14255 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14257 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14258 "Invalid TRUNCATE operation");
14260 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14261 if (VT.getVectorElementType().getSizeInBits() >=8)
14262 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14264 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14265 unsigned NumElts = InVT.getVectorNumElements();
14266 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14267 if (InVT.getSizeInBits() < 512) {
14268 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14269 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14273 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14274 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14275 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14276 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14277 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14278 MachinePointerInfo::getConstantPool(),
14279 false, false, false, Alignment);
14280 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14281 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14282 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14285 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14286 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14287 if (Subtarget->hasInt256()) {
14288 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14289 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14290 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14292 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14293 DAG.getIntPtrConstant(0));
14296 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14297 DAG.getIntPtrConstant(0));
14298 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14299 DAG.getIntPtrConstant(2));
14300 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14301 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14302 static const int ShufMask[] = {0, 2, 4, 6};
14303 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14306 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14307 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14308 if (Subtarget->hasInt256()) {
14309 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14311 SmallVector<SDValue,32> pshufbMask;
14312 for (unsigned i = 0; i < 2; ++i) {
14313 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14314 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14315 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14316 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14317 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14318 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14319 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14320 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14321 for (unsigned j = 0; j < 8; ++j)
14322 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14324 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14325 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14326 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14328 static const int ShufMask[] = {0, 2, -1, -1};
14329 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14331 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14332 DAG.getIntPtrConstant(0));
14333 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14336 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14337 DAG.getIntPtrConstant(0));
14339 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14340 DAG.getIntPtrConstant(4));
14342 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14343 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14345 // The PSHUFB mask:
14346 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14347 -1, -1, -1, -1, -1, -1, -1, -1};
14349 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14350 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14351 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14353 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14354 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14356 // The MOVLHPS Mask:
14357 static const int ShufMask2[] = {0, 1, 4, 5};
14358 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14359 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14362 // Handle truncation of V256 to V128 using shuffles.
14363 if (!VT.is128BitVector() || !InVT.is256BitVector())
14366 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14368 unsigned NumElems = VT.getVectorNumElements();
14369 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14371 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14372 // Prepare truncation shuffle mask
14373 for (unsigned i = 0; i != NumElems; ++i)
14374 MaskVec[i] = i * 2;
14375 SDValue V = DAG.getVectorShuffle(NVT, DL,
14376 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14377 DAG.getUNDEF(NVT), &MaskVec[0]);
14378 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14379 DAG.getIntPtrConstant(0));
14382 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14383 SelectionDAG &DAG) const {
14384 assert(!Op.getSimpleValueType().isVector());
14386 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14387 /*IsSigned=*/ true, /*IsReplace=*/ false);
14388 SDValue FIST = Vals.first, StackSlot = Vals.second;
14389 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14390 if (!FIST.getNode()) return Op;
14392 if (StackSlot.getNode())
14393 // Load the result.
14394 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14395 FIST, StackSlot, MachinePointerInfo(),
14396 false, false, false, 0);
14398 // The node is the result.
14402 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14403 SelectionDAG &DAG) const {
14404 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14405 /*IsSigned=*/ false, /*IsReplace=*/ false);
14406 SDValue FIST = Vals.first, StackSlot = Vals.second;
14407 assert(FIST.getNode() && "Unexpected failure");
14409 if (StackSlot.getNode())
14410 // Load the result.
14411 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14412 FIST, StackSlot, MachinePointerInfo(),
14413 false, false, false, 0);
14415 // The node is the result.
14419 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14421 MVT VT = Op.getSimpleValueType();
14422 SDValue In = Op.getOperand(0);
14423 MVT SVT = In.getSimpleValueType();
14425 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14427 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14428 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14429 In, DAG.getUNDEF(SVT)));
14432 /// The only differences between FABS and FNEG are the mask and the logic op.
14433 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14434 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14435 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14436 "Wrong opcode for lowering FABS or FNEG.");
14438 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14440 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14441 // into an FNABS. We'll lower the FABS after that if it is still in use.
14443 for (SDNode *User : Op->uses())
14444 if (User->getOpcode() == ISD::FNEG)
14447 SDValue Op0 = Op.getOperand(0);
14448 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14451 MVT VT = Op.getSimpleValueType();
14452 // Assume scalar op for initialization; update for vector if needed.
14453 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14454 // generate a 16-byte vector constant and logic op even for the scalar case.
14455 // Using a 16-byte mask allows folding the load of the mask with
14456 // the logic op, so it can save (~4 bytes) on code size.
14458 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14459 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14460 // decide if we should generate a 16-byte constant mask when we only need 4 or
14461 // 8 bytes for the scalar case.
14462 if (VT.isVector()) {
14463 EltVT = VT.getVectorElementType();
14464 NumElts = VT.getVectorNumElements();
14467 unsigned EltBits = EltVT.getSizeInBits();
14468 LLVMContext *Context = DAG.getContext();
14469 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14471 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14472 Constant *C = ConstantInt::get(*Context, MaskElt);
14473 C = ConstantVector::getSplat(NumElts, C);
14474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14475 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14476 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14477 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14478 MachinePointerInfo::getConstantPool(),
14479 false, false, false, Alignment);
14481 if (VT.isVector()) {
14482 // For a vector, cast operands to a vector type, perform the logic op,
14483 // and cast the result back to the original value type.
14484 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14485 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14486 SDValue Operand = IsFNABS ?
14487 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14488 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14489 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14490 return DAG.getNode(ISD::BITCAST, dl, VT,
14491 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14494 // If not vector, then scalar.
14495 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14496 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14497 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14500 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14501 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14502 LLVMContext *Context = DAG.getContext();
14503 SDValue Op0 = Op.getOperand(0);
14504 SDValue Op1 = Op.getOperand(1);
14506 MVT VT = Op.getSimpleValueType();
14507 MVT SrcVT = Op1.getSimpleValueType();
14509 // If second operand is smaller, extend it first.
14510 if (SrcVT.bitsLT(VT)) {
14511 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14514 // And if it is bigger, shrink it first.
14515 if (SrcVT.bitsGT(VT)) {
14516 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14520 // At this point the operands and the result should have the same
14521 // type, and that won't be f80 since that is not custom lowered.
14523 const fltSemantics &Sem =
14524 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14525 const unsigned SizeInBits = VT.getSizeInBits();
14527 SmallVector<Constant *, 4> CV(
14528 VT == MVT::f64 ? 2 : 4,
14529 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14531 // First, clear all bits but the sign bit from the second operand (sign).
14532 CV[0] = ConstantFP::get(*Context,
14533 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14534 Constant *C = ConstantVector::get(CV);
14535 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14536 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14537 MachinePointerInfo::getConstantPool(),
14538 false, false, false, 16);
14539 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14541 // Next, clear the sign bit from the first operand (magnitude).
14542 // If it's a constant, we can clear it here.
14543 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14544 APFloat APF = Op0CN->getValueAPF();
14545 // If the magnitude is a positive zero, the sign bit alone is enough.
14546 if (APF.isPosZero())
14549 CV[0] = ConstantFP::get(*Context, APF);
14551 CV[0] = ConstantFP::get(
14553 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14555 C = ConstantVector::get(CV);
14556 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14557 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14558 MachinePointerInfo::getConstantPool(),
14559 false, false, false, 16);
14560 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14561 if (!isa<ConstantFPSDNode>(Op0))
14562 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14564 // OR the magnitude value with the sign bit.
14565 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14568 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14569 SDValue N0 = Op.getOperand(0);
14571 MVT VT = Op.getSimpleValueType();
14573 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14574 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14575 DAG.getConstant(1, VT));
14576 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14579 // Check whether an OR'd tree is PTEST-able.
14580 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14581 SelectionDAG &DAG) {
14582 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14584 if (!Subtarget->hasSSE41())
14587 if (!Op->hasOneUse())
14590 SDNode *N = Op.getNode();
14593 SmallVector<SDValue, 8> Opnds;
14594 DenseMap<SDValue, unsigned> VecInMap;
14595 SmallVector<SDValue, 8> VecIns;
14596 EVT VT = MVT::Other;
14598 // Recognize a special case where a vector is casted into wide integer to
14600 Opnds.push_back(N->getOperand(0));
14601 Opnds.push_back(N->getOperand(1));
14603 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14604 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14605 // BFS traverse all OR'd operands.
14606 if (I->getOpcode() == ISD::OR) {
14607 Opnds.push_back(I->getOperand(0));
14608 Opnds.push_back(I->getOperand(1));
14609 // Re-evaluate the number of nodes to be traversed.
14610 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14614 // Quit if a non-EXTRACT_VECTOR_ELT
14615 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14618 // Quit if without a constant index.
14619 SDValue Idx = I->getOperand(1);
14620 if (!isa<ConstantSDNode>(Idx))
14623 SDValue ExtractedFromVec = I->getOperand(0);
14624 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14625 if (M == VecInMap.end()) {
14626 VT = ExtractedFromVec.getValueType();
14627 // Quit if not 128/256-bit vector.
14628 if (!VT.is128BitVector() && !VT.is256BitVector())
14630 // Quit if not the same type.
14631 if (VecInMap.begin() != VecInMap.end() &&
14632 VT != VecInMap.begin()->first.getValueType())
14634 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14635 VecIns.push_back(ExtractedFromVec);
14637 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14640 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14641 "Not extracted from 128-/256-bit vector.");
14643 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14645 for (DenseMap<SDValue, unsigned>::const_iterator
14646 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14647 // Quit if not all elements are used.
14648 if (I->second != FullMask)
14652 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14654 // Cast all vectors into TestVT for PTEST.
14655 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14656 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14658 // If more than one full vectors are evaluated, OR them first before PTEST.
14659 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14660 // Each iteration will OR 2 nodes and append the result until there is only
14661 // 1 node left, i.e. the final OR'd value of all vectors.
14662 SDValue LHS = VecIns[Slot];
14663 SDValue RHS = VecIns[Slot + 1];
14664 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14667 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14668 VecIns.back(), VecIns.back());
14671 /// \brief return true if \c Op has a use that doesn't just read flags.
14672 static bool hasNonFlagsUse(SDValue Op) {
14673 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14675 SDNode *User = *UI;
14676 unsigned UOpNo = UI.getOperandNo();
14677 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14678 // Look pass truncate.
14679 UOpNo = User->use_begin().getOperandNo();
14680 User = *User->use_begin();
14683 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14684 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14690 /// Emit nodes that will be selected as "test Op0,Op0", or something
14692 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14693 SelectionDAG &DAG) const {
14694 if (Op.getValueType() == MVT::i1)
14695 // KORTEST instruction should be selected
14696 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14697 DAG.getConstant(0, Op.getValueType()));
14699 // CF and OF aren't always set the way we want. Determine which
14700 // of these we need.
14701 bool NeedCF = false;
14702 bool NeedOF = false;
14705 case X86::COND_A: case X86::COND_AE:
14706 case X86::COND_B: case X86::COND_BE:
14709 case X86::COND_G: case X86::COND_GE:
14710 case X86::COND_L: case X86::COND_LE:
14711 case X86::COND_O: case X86::COND_NO: {
14712 // Check if we really need to set the
14713 // Overflow flag. If NoSignedWrap is present
14714 // that is not actually needed.
14715 switch (Op->getOpcode()) {
14720 const BinaryWithFlagsSDNode *BinNode =
14721 cast<BinaryWithFlagsSDNode>(Op.getNode());
14722 if (BinNode->hasNoSignedWrap())
14732 // See if we can use the EFLAGS value from the operand instead of
14733 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14734 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14735 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14736 // Emit a CMP with 0, which is the TEST pattern.
14737 //if (Op.getValueType() == MVT::i1)
14738 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14739 // DAG.getConstant(0, MVT::i1));
14740 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14741 DAG.getConstant(0, Op.getValueType()));
14743 unsigned Opcode = 0;
14744 unsigned NumOperands = 0;
14746 // Truncate operations may prevent the merge of the SETCC instruction
14747 // and the arithmetic instruction before it. Attempt to truncate the operands
14748 // of the arithmetic instruction and use a reduced bit-width instruction.
14749 bool NeedTruncation = false;
14750 SDValue ArithOp = Op;
14751 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14752 SDValue Arith = Op->getOperand(0);
14753 // Both the trunc and the arithmetic op need to have one user each.
14754 if (Arith->hasOneUse())
14755 switch (Arith.getOpcode()) {
14762 NeedTruncation = true;
14768 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14769 // which may be the result of a CAST. We use the variable 'Op', which is the
14770 // non-casted variable when we check for possible users.
14771 switch (ArithOp.getOpcode()) {
14773 // Due to an isel shortcoming, be conservative if this add is likely to be
14774 // selected as part of a load-modify-store instruction. When the root node
14775 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14776 // uses of other nodes in the match, such as the ADD in this case. This
14777 // leads to the ADD being left around and reselected, with the result being
14778 // two adds in the output. Alas, even if none our users are stores, that
14779 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14780 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14781 // climbing the DAG back to the root, and it doesn't seem to be worth the
14783 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14784 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14785 if (UI->getOpcode() != ISD::CopyToReg &&
14786 UI->getOpcode() != ISD::SETCC &&
14787 UI->getOpcode() != ISD::STORE)
14790 if (ConstantSDNode *C =
14791 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14792 // An add of one will be selected as an INC.
14793 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14794 Opcode = X86ISD::INC;
14799 // An add of negative one (subtract of one) will be selected as a DEC.
14800 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14801 Opcode = X86ISD::DEC;
14807 // Otherwise use a regular EFLAGS-setting add.
14808 Opcode = X86ISD::ADD;
14813 // If we have a constant logical shift that's only used in a comparison
14814 // against zero turn it into an equivalent AND. This allows turning it into
14815 // a TEST instruction later.
14816 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14817 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14818 EVT VT = Op.getValueType();
14819 unsigned BitWidth = VT.getSizeInBits();
14820 unsigned ShAmt = Op->getConstantOperandVal(1);
14821 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14823 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14824 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14825 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14826 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14828 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14829 DAG.getConstant(Mask, VT));
14830 DAG.ReplaceAllUsesWith(Op, New);
14836 // If the primary and result isn't used, don't bother using X86ISD::AND,
14837 // because a TEST instruction will be better.
14838 if (!hasNonFlagsUse(Op))
14844 // Due to the ISEL shortcoming noted above, be conservative if this op is
14845 // likely to be selected as part of a load-modify-store instruction.
14846 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14847 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14848 if (UI->getOpcode() == ISD::STORE)
14851 // Otherwise use a regular EFLAGS-setting instruction.
14852 switch (ArithOp.getOpcode()) {
14853 default: llvm_unreachable("unexpected operator!");
14854 case ISD::SUB: Opcode = X86ISD::SUB; break;
14855 case ISD::XOR: Opcode = X86ISD::XOR; break;
14856 case ISD::AND: Opcode = X86ISD::AND; break;
14858 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14859 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14860 if (EFLAGS.getNode())
14863 Opcode = X86ISD::OR;
14877 return SDValue(Op.getNode(), 1);
14883 // If we found that truncation is beneficial, perform the truncation and
14885 if (NeedTruncation) {
14886 EVT VT = Op.getValueType();
14887 SDValue WideVal = Op->getOperand(0);
14888 EVT WideVT = WideVal.getValueType();
14889 unsigned ConvertedOp = 0;
14890 // Use a target machine opcode to prevent further DAGCombine
14891 // optimizations that may separate the arithmetic operations
14892 // from the setcc node.
14893 switch (WideVal.getOpcode()) {
14895 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14896 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14897 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14898 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14899 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14904 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14905 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14906 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14907 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14913 // Emit a CMP with 0, which is the TEST pattern.
14914 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14915 DAG.getConstant(0, Op.getValueType()));
14917 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14918 SmallVector<SDValue, 4> Ops;
14919 for (unsigned i = 0; i != NumOperands; ++i)
14920 Ops.push_back(Op.getOperand(i));
14922 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14923 DAG.ReplaceAllUsesWith(Op, New);
14924 return SDValue(New.getNode(), 1);
14927 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14929 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14930 SDLoc dl, SelectionDAG &DAG) const {
14931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14932 if (C->getAPIntValue() == 0)
14933 return EmitTest(Op0, X86CC, dl, DAG);
14935 if (Op0.getValueType() == MVT::i1)
14936 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14939 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14940 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14941 // Do the comparison at i32 if it's smaller, besides the Atom case.
14942 // This avoids subregister aliasing issues. Keep the smaller reference
14943 // if we're optimizing for size, however, as that'll allow better folding
14944 // of memory operations.
14945 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14946 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14947 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14948 !Subtarget->isAtom()) {
14949 unsigned ExtendOp =
14950 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14951 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14952 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14954 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14955 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14956 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14958 return SDValue(Sub.getNode(), 1);
14960 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14963 /// Convert a comparison if required by the subtarget.
14964 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14965 SelectionDAG &DAG) const {
14966 // If the subtarget does not support the FUCOMI instruction, floating-point
14967 // comparisons have to be converted.
14968 if (Subtarget->hasCMov() ||
14969 Cmp.getOpcode() != X86ISD::CMP ||
14970 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14971 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14974 // The instruction selector will select an FUCOM instruction instead of
14975 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14976 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14977 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14979 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14980 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14981 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14982 DAG.getConstant(8, MVT::i8));
14983 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14984 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14987 /// The minimum architected relative accuracy is 2^-12. We need one
14988 /// Newton-Raphson step to have a good float result (24 bits of precision).
14989 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14990 DAGCombinerInfo &DCI,
14991 unsigned &RefinementSteps,
14992 bool &UseOneConstNR) const {
14993 // FIXME: We should use instruction latency models to calculate the cost of
14994 // each potential sequence, but this is very hard to do reliably because
14995 // at least Intel's Core* chips have variable timing based on the number of
14996 // significant digits in the divisor and/or sqrt operand.
14997 if (!Subtarget->useSqrtEst())
15000 EVT VT = Op.getValueType();
15002 // SSE1 has rsqrtss and rsqrtps.
15003 // TODO: Add support for AVX512 (v16f32).
15004 // It is likely not profitable to do this for f64 because a double-precision
15005 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
15006 // instructions: convert to single, rsqrtss, convert back to double, refine
15007 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
15008 // along with FMA, this could be a throughput win.
15009 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15010 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15011 RefinementSteps = 1;
15012 UseOneConstNR = false;
15013 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15018 /// The minimum architected relative accuracy is 2^-12. We need one
15019 /// Newton-Raphson step to have a good float result (24 bits of precision).
15020 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15021 DAGCombinerInfo &DCI,
15022 unsigned &RefinementSteps) const {
15023 // FIXME: We should use instruction latency models to calculate the cost of
15024 // each potential sequence, but this is very hard to do reliably because
15025 // at least Intel's Core* chips have variable timing based on the number of
15026 // significant digits in the divisor.
15027 if (!Subtarget->useReciprocalEst())
15030 EVT VT = Op.getValueType();
15032 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15033 // TODO: Add support for AVX512 (v16f32).
15034 // It is likely not profitable to do this for f64 because a double-precision
15035 // reciprocal estimate with refinement on x86 prior to FMA requires
15036 // 15 instructions: convert to single, rcpss, convert back to double, refine
15037 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15038 // along with FMA, this could be a throughput win.
15039 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15040 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15041 RefinementSteps = ReciprocalEstimateRefinementSteps;
15042 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15047 static bool isAllOnes(SDValue V) {
15048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15049 return C && C->isAllOnesValue();
15052 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15053 /// if it's possible.
15054 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15055 SDLoc dl, SelectionDAG &DAG) const {
15056 SDValue Op0 = And.getOperand(0);
15057 SDValue Op1 = And.getOperand(1);
15058 if (Op0.getOpcode() == ISD::TRUNCATE)
15059 Op0 = Op0.getOperand(0);
15060 if (Op1.getOpcode() == ISD::TRUNCATE)
15061 Op1 = Op1.getOperand(0);
15064 if (Op1.getOpcode() == ISD::SHL)
15065 std::swap(Op0, Op1);
15066 if (Op0.getOpcode() == ISD::SHL) {
15067 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15068 if (And00C->getZExtValue() == 1) {
15069 // If we looked past a truncate, check that it's only truncating away
15071 unsigned BitWidth = Op0.getValueSizeInBits();
15072 unsigned AndBitWidth = And.getValueSizeInBits();
15073 if (BitWidth > AndBitWidth) {
15075 DAG.computeKnownBits(Op0, Zeros, Ones);
15076 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15080 RHS = Op0.getOperand(1);
15082 } else if (Op1.getOpcode() == ISD::Constant) {
15083 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15084 uint64_t AndRHSVal = AndRHS->getZExtValue();
15085 SDValue AndLHS = Op0;
15087 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15088 LHS = AndLHS.getOperand(0);
15089 RHS = AndLHS.getOperand(1);
15092 // Use BT if the immediate can't be encoded in a TEST instruction.
15093 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15095 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15099 if (LHS.getNode()) {
15100 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15101 // instruction. Since the shift amount is in-range-or-undefined, we know
15102 // that doing a bittest on the i32 value is ok. We extend to i32 because
15103 // the encoding for the i16 version is larger than the i32 version.
15104 // Also promote i16 to i32 for performance / code size reason.
15105 if (LHS.getValueType() == MVT::i8 ||
15106 LHS.getValueType() == MVT::i16)
15107 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15109 // If the operand types disagree, extend the shift amount to match. Since
15110 // BT ignores high bits (like shifts) we can use anyextend.
15111 if (LHS.getValueType() != RHS.getValueType())
15112 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15114 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15115 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15116 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15117 DAG.getConstant(Cond, MVT::i8), BT);
15123 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15125 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15130 // SSE Condition code mapping:
15139 switch (SetCCOpcode) {
15140 default: llvm_unreachable("Unexpected SETCC condition");
15142 case ISD::SETEQ: SSECC = 0; break;
15144 case ISD::SETGT: Swap = true; // Fallthrough
15146 case ISD::SETOLT: SSECC = 1; break;
15148 case ISD::SETGE: Swap = true; // Fallthrough
15150 case ISD::SETOLE: SSECC = 2; break;
15151 case ISD::SETUO: SSECC = 3; break;
15153 case ISD::SETNE: SSECC = 4; break;
15154 case ISD::SETULE: Swap = true; // Fallthrough
15155 case ISD::SETUGE: SSECC = 5; break;
15156 case ISD::SETULT: Swap = true; // Fallthrough
15157 case ISD::SETUGT: SSECC = 6; break;
15158 case ISD::SETO: SSECC = 7; break;
15160 case ISD::SETONE: SSECC = 8; break;
15163 std::swap(Op0, Op1);
15168 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15169 // ones, and then concatenate the result back.
15170 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15171 MVT VT = Op.getSimpleValueType();
15173 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15174 "Unsupported value type for operation");
15176 unsigned NumElems = VT.getVectorNumElements();
15178 SDValue CC = Op.getOperand(2);
15180 // Extract the LHS vectors
15181 SDValue LHS = Op.getOperand(0);
15182 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15183 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15185 // Extract the RHS vectors
15186 SDValue RHS = Op.getOperand(1);
15187 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15188 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15190 // Issue the operation on the smaller types and concatenate the result back
15191 MVT EltVT = VT.getVectorElementType();
15192 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15193 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15194 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15195 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15198 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15199 const X86Subtarget *Subtarget) {
15200 SDValue Op0 = Op.getOperand(0);
15201 SDValue Op1 = Op.getOperand(1);
15202 SDValue CC = Op.getOperand(2);
15203 MVT VT = Op.getSimpleValueType();
15206 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15207 Op.getValueType().getScalarType() == MVT::i1 &&
15208 "Cannot set masked compare for this operation");
15210 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15212 bool Unsigned = false;
15215 switch (SetCCOpcode) {
15216 default: llvm_unreachable("Unexpected SETCC condition");
15217 case ISD::SETNE: SSECC = 4; break;
15218 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15219 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15220 case ISD::SETLT: Swap = true; //fall-through
15221 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15222 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15223 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15224 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15225 case ISD::SETULE: Unsigned = true; //fall-through
15226 case ISD::SETLE: SSECC = 2; break;
15230 std::swap(Op0, Op1);
15232 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15233 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15234 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15235 DAG.getConstant(SSECC, MVT::i8));
15238 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15239 /// operand \p Op1. If non-trivial (for example because it's not constant)
15240 /// return an empty value.
15241 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15243 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15247 MVT VT = Op1.getSimpleValueType();
15248 MVT EVT = VT.getVectorElementType();
15249 unsigned n = VT.getVectorNumElements();
15250 SmallVector<SDValue, 8> ULTOp1;
15252 for (unsigned i = 0; i < n; ++i) {
15253 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15254 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15257 // Avoid underflow.
15258 APInt Val = Elt->getAPIntValue();
15262 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15265 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15268 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15269 SelectionDAG &DAG) {
15270 SDValue Op0 = Op.getOperand(0);
15271 SDValue Op1 = Op.getOperand(1);
15272 SDValue CC = Op.getOperand(2);
15273 MVT VT = Op.getSimpleValueType();
15274 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15275 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15280 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15281 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15284 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15285 unsigned Opc = X86ISD::CMPP;
15286 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15287 assert(VT.getVectorNumElements() <= 16);
15288 Opc = X86ISD::CMPM;
15290 // In the two special cases we can't handle, emit two comparisons.
15293 unsigned CombineOpc;
15294 if (SetCCOpcode == ISD::SETUEQ) {
15295 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15297 assert(SetCCOpcode == ISD::SETONE);
15298 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15301 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15302 DAG.getConstant(CC0, MVT::i8));
15303 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15304 DAG.getConstant(CC1, MVT::i8));
15305 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15307 // Handle all other FP comparisons here.
15308 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15309 DAG.getConstant(SSECC, MVT::i8));
15312 // Break 256-bit integer vector compare into smaller ones.
15313 if (VT.is256BitVector() && !Subtarget->hasInt256())
15314 return Lower256IntVSETCC(Op, DAG);
15316 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15317 EVT OpVT = Op1.getValueType();
15318 if (Subtarget->hasAVX512()) {
15319 if (Op1.getValueType().is512BitVector() ||
15320 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15321 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15322 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15324 // In AVX-512 architecture setcc returns mask with i1 elements,
15325 // But there is no compare instruction for i8 and i16 elements in KNL.
15326 // We are not talking about 512-bit operands in this case, these
15327 // types are illegal.
15329 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15330 OpVT.getVectorElementType().getSizeInBits() >= 8))
15331 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15332 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15335 // We are handling one of the integer comparisons here. Since SSE only has
15336 // GT and EQ comparisons for integer, swapping operands and multiple
15337 // operations may be required for some comparisons.
15339 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15340 bool Subus = false;
15342 switch (SetCCOpcode) {
15343 default: llvm_unreachable("Unexpected SETCC condition");
15344 case ISD::SETNE: Invert = true;
15345 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15346 case ISD::SETLT: Swap = true;
15347 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15348 case ISD::SETGE: Swap = true;
15349 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15350 Invert = true; break;
15351 case ISD::SETULT: Swap = true;
15352 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15353 FlipSigns = true; break;
15354 case ISD::SETUGE: Swap = true;
15355 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15356 FlipSigns = true; Invert = true; break;
15359 // Special case: Use min/max operations for SETULE/SETUGE
15360 MVT VET = VT.getVectorElementType();
15362 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15363 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15366 switch (SetCCOpcode) {
15368 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15369 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15372 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15375 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15376 if (!MinMax && hasSubus) {
15377 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15379 // t = psubus Op0, Op1
15380 // pcmpeq t, <0..0>
15381 switch (SetCCOpcode) {
15383 case ISD::SETULT: {
15384 // If the comparison is against a constant we can turn this into a
15385 // setule. With psubus, setule does not require a swap. This is
15386 // beneficial because the constant in the register is no longer
15387 // destructed as the destination so it can be hoisted out of a loop.
15388 // Only do this pre-AVX since vpcmp* is no longer destructive.
15389 if (Subtarget->hasAVX())
15391 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15392 if (ULEOp1.getNode()) {
15394 Subus = true; Invert = false; Swap = false;
15398 // Psubus is better than flip-sign because it requires no inversion.
15399 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15400 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15404 Opc = X86ISD::SUBUS;
15410 std::swap(Op0, Op1);
15412 // Check that the operation in question is available (most are plain SSE2,
15413 // but PCMPGTQ and PCMPEQQ have different requirements).
15414 if (VT == MVT::v2i64) {
15415 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15416 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15418 // First cast everything to the right type.
15419 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15420 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15422 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15423 // bits of the inputs before performing those operations. The lower
15424 // compare is always unsigned.
15427 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15429 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15430 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15431 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15432 Sign, Zero, Sign, Zero);
15434 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15435 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15437 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15438 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15439 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15441 // Create masks for only the low parts/high parts of the 64 bit integers.
15442 static const int MaskHi[] = { 1, 1, 3, 3 };
15443 static const int MaskLo[] = { 0, 0, 2, 2 };
15444 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15445 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15446 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15448 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15449 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15452 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15454 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15457 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15458 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15459 // pcmpeqd + pshufd + pand.
15460 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15462 // First cast everything to the right type.
15463 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15464 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15467 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15469 // Make sure the lower and upper halves are both all-ones.
15470 static const int Mask[] = { 1, 0, 3, 2 };
15471 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15472 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15475 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15477 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15481 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15482 // bits of the inputs before performing those operations.
15484 EVT EltVT = VT.getVectorElementType();
15485 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15486 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15487 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15490 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15492 // If the logical-not of the result is required, perform that now.
15494 Result = DAG.getNOT(dl, Result, VT);
15497 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15500 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15501 getZeroVector(VT, Subtarget, DAG, dl));
15506 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15508 MVT VT = Op.getSimpleValueType();
15510 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15512 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15513 && "SetCC type must be 8-bit or 1-bit integer");
15514 SDValue Op0 = Op.getOperand(0);
15515 SDValue Op1 = Op.getOperand(1);
15517 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15519 // Optimize to BT if possible.
15520 // Lower (X & (1 << N)) == 0 to BT(X, N).
15521 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15522 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15523 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15524 Op1.getOpcode() == ISD::Constant &&
15525 cast<ConstantSDNode>(Op1)->isNullValue() &&
15526 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15527 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15528 if (NewSetCC.getNode()) {
15530 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15535 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15537 if (Op1.getOpcode() == ISD::Constant &&
15538 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15539 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15540 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15542 // If the input is a setcc, then reuse the input setcc or use a new one with
15543 // the inverted condition.
15544 if (Op0.getOpcode() == X86ISD::SETCC) {
15545 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15546 bool Invert = (CC == ISD::SETNE) ^
15547 cast<ConstantSDNode>(Op1)->isNullValue();
15551 CCode = X86::GetOppositeBranchCondition(CCode);
15552 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15553 DAG.getConstant(CCode, MVT::i8),
15554 Op0.getOperand(1));
15556 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15560 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15561 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15562 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15564 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15565 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15568 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15569 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15570 if (X86CC == X86::COND_INVALID)
15573 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15574 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15575 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15576 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15578 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15582 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15583 static bool isX86LogicalCmp(SDValue Op) {
15584 unsigned Opc = Op.getNode()->getOpcode();
15585 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15586 Opc == X86ISD::SAHF)
15588 if (Op.getResNo() == 1 &&
15589 (Opc == X86ISD::ADD ||
15590 Opc == X86ISD::SUB ||
15591 Opc == X86ISD::ADC ||
15592 Opc == X86ISD::SBB ||
15593 Opc == X86ISD::SMUL ||
15594 Opc == X86ISD::UMUL ||
15595 Opc == X86ISD::INC ||
15596 Opc == X86ISD::DEC ||
15597 Opc == X86ISD::OR ||
15598 Opc == X86ISD::XOR ||
15599 Opc == X86ISD::AND))
15602 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15608 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15609 if (V.getOpcode() != ISD::TRUNCATE)
15612 SDValue VOp0 = V.getOperand(0);
15613 unsigned InBits = VOp0.getValueSizeInBits();
15614 unsigned Bits = V.getValueSizeInBits();
15615 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15618 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15619 bool addTest = true;
15620 SDValue Cond = Op.getOperand(0);
15621 SDValue Op1 = Op.getOperand(1);
15622 SDValue Op2 = Op.getOperand(2);
15624 EVT VT = Op1.getValueType();
15627 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15628 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15629 // sequence later on.
15630 if (Cond.getOpcode() == ISD::SETCC &&
15631 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15632 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15633 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15634 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15635 int SSECC = translateX86FSETCC(
15636 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15639 if (Subtarget->hasAVX512()) {
15640 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15641 DAG.getConstant(SSECC, MVT::i8));
15642 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15644 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15645 DAG.getConstant(SSECC, MVT::i8));
15646 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15647 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15648 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15652 if (Cond.getOpcode() == ISD::SETCC) {
15653 SDValue NewCond = LowerSETCC(Cond, DAG);
15654 if (NewCond.getNode())
15658 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15659 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15660 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15661 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15662 if (Cond.getOpcode() == X86ISD::SETCC &&
15663 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15664 isZero(Cond.getOperand(1).getOperand(1))) {
15665 SDValue Cmp = Cond.getOperand(1);
15667 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15669 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15670 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15671 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15673 SDValue CmpOp0 = Cmp.getOperand(0);
15674 // Apply further optimizations for special cases
15675 // (select (x != 0), -1, 0) -> neg & sbb
15676 // (select (x == 0), 0, -1) -> neg & sbb
15677 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15678 if (YC->isNullValue() &&
15679 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15680 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15681 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15682 DAG.getConstant(0, CmpOp0.getValueType()),
15684 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15685 DAG.getConstant(X86::COND_B, MVT::i8),
15686 SDValue(Neg.getNode(), 1));
15690 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15691 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15692 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15694 SDValue Res = // Res = 0 or -1.
15695 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15696 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15698 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15699 Res = DAG.getNOT(DL, Res, Res.getValueType());
15701 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15702 if (!N2C || !N2C->isNullValue())
15703 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15708 // Look past (and (setcc_carry (cmp ...)), 1).
15709 if (Cond.getOpcode() == ISD::AND &&
15710 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15711 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15712 if (C && C->getAPIntValue() == 1)
15713 Cond = Cond.getOperand(0);
15716 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15717 // setting operand in place of the X86ISD::SETCC.
15718 unsigned CondOpcode = Cond.getOpcode();
15719 if (CondOpcode == X86ISD::SETCC ||
15720 CondOpcode == X86ISD::SETCC_CARRY) {
15721 CC = Cond.getOperand(0);
15723 SDValue Cmp = Cond.getOperand(1);
15724 unsigned Opc = Cmp.getOpcode();
15725 MVT VT = Op.getSimpleValueType();
15727 bool IllegalFPCMov = false;
15728 if (VT.isFloatingPoint() && !VT.isVector() &&
15729 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15730 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15732 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15733 Opc == X86ISD::BT) { // FIXME
15737 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15738 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15739 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15740 Cond.getOperand(0).getValueType() != MVT::i8)) {
15741 SDValue LHS = Cond.getOperand(0);
15742 SDValue RHS = Cond.getOperand(1);
15743 unsigned X86Opcode;
15746 switch (CondOpcode) {
15747 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15748 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15749 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15750 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15751 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15752 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15753 default: llvm_unreachable("unexpected overflowing operator");
15755 if (CondOpcode == ISD::UMULO)
15756 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15759 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15761 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15763 if (CondOpcode == ISD::UMULO)
15764 Cond = X86Op.getValue(2);
15766 Cond = X86Op.getValue(1);
15768 CC = DAG.getConstant(X86Cond, MVT::i8);
15773 // Look pass the truncate if the high bits are known zero.
15774 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15775 Cond = Cond.getOperand(0);
15777 // We know the result of AND is compared against zero. Try to match
15779 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15780 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15781 if (NewSetCC.getNode()) {
15782 CC = NewSetCC.getOperand(0);
15783 Cond = NewSetCC.getOperand(1);
15790 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15791 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15794 // a < b ? -1 : 0 -> RES = ~setcc_carry
15795 // a < b ? 0 : -1 -> RES = setcc_carry
15796 // a >= b ? -1 : 0 -> RES = setcc_carry
15797 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15798 if (Cond.getOpcode() == X86ISD::SUB) {
15799 Cond = ConvertCmpIfNecessary(Cond, DAG);
15800 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15802 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15803 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15804 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15805 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15806 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15807 return DAG.getNOT(DL, Res, Res.getValueType());
15812 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15813 // widen the cmov and push the truncate through. This avoids introducing a new
15814 // branch during isel and doesn't add any extensions.
15815 if (Op.getValueType() == MVT::i8 &&
15816 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15817 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15818 if (T1.getValueType() == T2.getValueType() &&
15819 // Blacklist CopyFromReg to avoid partial register stalls.
15820 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15821 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15822 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15823 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15827 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15828 // condition is true.
15829 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15830 SDValue Ops[] = { Op2, Op1, CC, Cond };
15831 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15834 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15835 SelectionDAG &DAG) {
15836 MVT VT = Op->getSimpleValueType(0);
15837 SDValue In = Op->getOperand(0);
15838 MVT InVT = In.getSimpleValueType();
15839 MVT VTElt = VT.getVectorElementType();
15840 MVT InVTElt = InVT.getVectorElementType();
15844 if ((InVTElt == MVT::i1) &&
15845 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15846 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15848 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15849 VTElt.getSizeInBits() <= 16)) ||
15851 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15852 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15854 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15855 VTElt.getSizeInBits() >= 32))))
15856 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15858 unsigned int NumElts = VT.getVectorNumElements();
15860 if (NumElts != 8 && NumElts != 16)
15863 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15864 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15865 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15866 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15870 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15872 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15873 Constant *C = ConstantInt::get(*DAG.getContext(),
15874 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15876 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15877 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15878 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15879 MachinePointerInfo::getConstantPool(),
15880 false, false, false, Alignment);
15881 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15882 if (VT.is512BitVector())
15884 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15887 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15888 SelectionDAG &DAG) {
15889 MVT VT = Op->getSimpleValueType(0);
15890 SDValue In = Op->getOperand(0);
15891 MVT InVT = In.getSimpleValueType();
15894 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15895 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15897 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15898 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15899 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15902 if (Subtarget->hasInt256())
15903 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15905 // Optimize vectors in AVX mode
15906 // Sign extend v8i16 to v8i32 and
15909 // Divide input vector into two parts
15910 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15911 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15912 // concat the vectors to original VT
15914 unsigned NumElems = InVT.getVectorNumElements();
15915 SDValue Undef = DAG.getUNDEF(InVT);
15917 SmallVector<int,8> ShufMask1(NumElems, -1);
15918 for (unsigned i = 0; i != NumElems/2; ++i)
15921 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15923 SmallVector<int,8> ShufMask2(NumElems, -1);
15924 for (unsigned i = 0; i != NumElems/2; ++i)
15925 ShufMask2[i] = i + NumElems/2;
15927 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15929 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15930 VT.getVectorNumElements()/2);
15932 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15933 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15938 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15939 // may emit an illegal shuffle but the expansion is still better than scalar
15940 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15941 // we'll emit a shuffle and a arithmetic shift.
15942 // TODO: It is possible to support ZExt by zeroing the undef values during
15943 // the shuffle phase or after the shuffle.
15944 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15945 SelectionDAG &DAG) {
15946 MVT RegVT = Op.getSimpleValueType();
15947 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15948 assert(RegVT.isInteger() &&
15949 "We only custom lower integer vector sext loads.");
15951 // Nothing useful we can do without SSE2 shuffles.
15952 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15954 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15956 EVT MemVT = Ld->getMemoryVT();
15957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15958 unsigned RegSz = RegVT.getSizeInBits();
15960 ISD::LoadExtType Ext = Ld->getExtensionType();
15962 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15963 && "Only anyext and sext are currently implemented.");
15964 assert(MemVT != RegVT && "Cannot extend to the same type");
15965 assert(MemVT.isVector() && "Must load a vector from memory");
15967 unsigned NumElems = RegVT.getVectorNumElements();
15968 unsigned MemSz = MemVT.getSizeInBits();
15969 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15971 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15972 // The only way in which we have a legal 256-bit vector result but not the
15973 // integer 256-bit operations needed to directly lower a sextload is if we
15974 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15975 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15976 // correctly legalized. We do this late to allow the canonical form of
15977 // sextload to persist throughout the rest of the DAG combiner -- it wants
15978 // to fold together any extensions it can, and so will fuse a sign_extend
15979 // of an sextload into a sextload targeting a wider value.
15981 if (MemSz == 128) {
15982 // Just switch this to a normal load.
15983 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15984 "it must be a legal 128-bit vector "
15986 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15987 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15988 Ld->isInvariant(), Ld->getAlignment());
15990 assert(MemSz < 128 &&
15991 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15992 // Do an sext load to a 128-bit vector type. We want to use the same
15993 // number of elements, but elements half as wide. This will end up being
15994 // recursively lowered by this routine, but will succeed as we definitely
15995 // have all the necessary features if we're using AVX1.
15997 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15998 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
16000 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
16001 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
16002 Ld->isNonTemporal(), Ld->isInvariant(),
16003 Ld->getAlignment());
16006 // Replace chain users with the new chain.
16007 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
16008 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16010 // Finally, do a normal sign-extend to the desired register.
16011 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16014 // All sizes must be a power of two.
16015 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16016 "Non-power-of-two elements are not custom lowered!");
16018 // Attempt to load the original value using scalar loads.
16019 // Find the largest scalar type that divides the total loaded size.
16020 MVT SclrLoadTy = MVT::i8;
16021 for (MVT Tp : MVT::integer_valuetypes()) {
16022 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16027 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16028 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16030 SclrLoadTy = MVT::f64;
16032 // Calculate the number of scalar loads that we need to perform
16033 // in order to load our vector from memory.
16034 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16036 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16037 "Can only lower sext loads with a single scalar load!");
16039 unsigned loadRegZize = RegSz;
16040 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16043 // Represent our vector as a sequence of elements which are the
16044 // largest scalar that we can load.
16045 EVT LoadUnitVecVT = EVT::getVectorVT(
16046 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16048 // Represent the data using the same element type that is stored in
16049 // memory. In practice, we ''widen'' MemVT.
16051 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16052 loadRegZize / MemVT.getScalarType().getSizeInBits());
16054 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16055 "Invalid vector type");
16057 // We can't shuffle using an illegal type.
16058 assert(TLI.isTypeLegal(WideVecVT) &&
16059 "We only lower types that form legal widened vector types");
16061 SmallVector<SDValue, 8> Chains;
16062 SDValue Ptr = Ld->getBasePtr();
16063 SDValue Increment =
16064 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16065 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16067 for (unsigned i = 0; i < NumLoads; ++i) {
16068 // Perform a single load.
16069 SDValue ScalarLoad =
16070 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16071 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16072 Ld->getAlignment());
16073 Chains.push_back(ScalarLoad.getValue(1));
16074 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16075 // another round of DAGCombining.
16077 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16079 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16080 ScalarLoad, DAG.getIntPtrConstant(i));
16082 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16085 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16087 // Bitcast the loaded value to a vector of the original element type, in
16088 // the size of the target vector type.
16089 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16090 unsigned SizeRatio = RegSz / MemSz;
16092 if (Ext == ISD::SEXTLOAD) {
16093 // If we have SSE4.1, we can directly emit a VSEXT node.
16094 if (Subtarget->hasSSE41()) {
16095 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16096 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16100 // Otherwise we'll shuffle the small elements in the high bits of the
16101 // larger type and perform an arithmetic shift. If the shift is not legal
16102 // it's better to scalarize.
16103 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16104 "We can't implement a sext load without an arithmetic right shift!");
16106 // Redistribute the loaded elements into the different locations.
16107 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16108 for (unsigned i = 0; i != NumElems; ++i)
16109 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16111 SDValue Shuff = DAG.getVectorShuffle(
16112 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16114 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16116 // Build the arithmetic shift.
16117 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16118 MemVT.getVectorElementType().getSizeInBits();
16120 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16122 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16126 // Redistribute the loaded elements into the different locations.
16127 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16128 for (unsigned i = 0; i != NumElems; ++i)
16129 ShuffleVec[i * SizeRatio] = i;
16131 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16132 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16134 // Bitcast to the requested type.
16135 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16136 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16140 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16141 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16142 // from the AND / OR.
16143 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16144 Opc = Op.getOpcode();
16145 if (Opc != ISD::OR && Opc != ISD::AND)
16147 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16148 Op.getOperand(0).hasOneUse() &&
16149 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16150 Op.getOperand(1).hasOneUse());
16153 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16154 // 1 and that the SETCC node has a single use.
16155 static bool isXor1OfSetCC(SDValue Op) {
16156 if (Op.getOpcode() != ISD::XOR)
16158 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16159 if (N1C && N1C->getAPIntValue() == 1) {
16160 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16161 Op.getOperand(0).hasOneUse();
16166 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16167 bool addTest = true;
16168 SDValue Chain = Op.getOperand(0);
16169 SDValue Cond = Op.getOperand(1);
16170 SDValue Dest = Op.getOperand(2);
16173 bool Inverted = false;
16175 if (Cond.getOpcode() == ISD::SETCC) {
16176 // Check for setcc([su]{add,sub,mul}o == 0).
16177 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16178 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16179 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16180 Cond.getOperand(0).getResNo() == 1 &&
16181 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16182 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16183 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16184 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16185 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16186 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16188 Cond = Cond.getOperand(0);
16190 SDValue NewCond = LowerSETCC(Cond, DAG);
16191 if (NewCond.getNode())
16196 // FIXME: LowerXALUO doesn't handle these!!
16197 else if (Cond.getOpcode() == X86ISD::ADD ||
16198 Cond.getOpcode() == X86ISD::SUB ||
16199 Cond.getOpcode() == X86ISD::SMUL ||
16200 Cond.getOpcode() == X86ISD::UMUL)
16201 Cond = LowerXALUO(Cond, DAG);
16204 // Look pass (and (setcc_carry (cmp ...)), 1).
16205 if (Cond.getOpcode() == ISD::AND &&
16206 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16208 if (C && C->getAPIntValue() == 1)
16209 Cond = Cond.getOperand(0);
16212 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16213 // setting operand in place of the X86ISD::SETCC.
16214 unsigned CondOpcode = Cond.getOpcode();
16215 if (CondOpcode == X86ISD::SETCC ||
16216 CondOpcode == X86ISD::SETCC_CARRY) {
16217 CC = Cond.getOperand(0);
16219 SDValue Cmp = Cond.getOperand(1);
16220 unsigned Opc = Cmp.getOpcode();
16221 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16222 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16226 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16230 // These can only come from an arithmetic instruction with overflow,
16231 // e.g. SADDO, UADDO.
16232 Cond = Cond.getNode()->getOperand(1);
16238 CondOpcode = Cond.getOpcode();
16239 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16240 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16241 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16242 Cond.getOperand(0).getValueType() != MVT::i8)) {
16243 SDValue LHS = Cond.getOperand(0);
16244 SDValue RHS = Cond.getOperand(1);
16245 unsigned X86Opcode;
16248 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16249 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16251 switch (CondOpcode) {
16252 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16256 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16259 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16260 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16264 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16267 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16268 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16269 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16270 default: llvm_unreachable("unexpected overflowing operator");
16273 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16274 if (CondOpcode == ISD::UMULO)
16275 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16278 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16280 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16282 if (CondOpcode == ISD::UMULO)
16283 Cond = X86Op.getValue(2);
16285 Cond = X86Op.getValue(1);
16287 CC = DAG.getConstant(X86Cond, MVT::i8);
16291 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16292 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16293 if (CondOpc == ISD::OR) {
16294 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16295 // two branches instead of an explicit OR instruction with a
16297 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16298 isX86LogicalCmp(Cmp)) {
16299 CC = Cond.getOperand(0).getOperand(0);
16300 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16301 Chain, Dest, CC, Cmp);
16302 CC = Cond.getOperand(1).getOperand(0);
16306 } else { // ISD::AND
16307 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16308 // two branches instead of an explicit AND instruction with a
16309 // separate test. However, we only do this if this block doesn't
16310 // have a fall-through edge, because this requires an explicit
16311 // jmp when the condition is false.
16312 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16313 isX86LogicalCmp(Cmp) &&
16314 Op.getNode()->hasOneUse()) {
16315 X86::CondCode CCode =
16316 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16317 CCode = X86::GetOppositeBranchCondition(CCode);
16318 CC = DAG.getConstant(CCode, MVT::i8);
16319 SDNode *User = *Op.getNode()->use_begin();
16320 // Look for an unconditional branch following this conditional branch.
16321 // We need this because we need to reverse the successors in order
16322 // to implement FCMP_OEQ.
16323 if (User->getOpcode() == ISD::BR) {
16324 SDValue FalseBB = User->getOperand(1);
16326 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16327 assert(NewBR == User);
16331 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16332 Chain, Dest, CC, Cmp);
16333 X86::CondCode CCode =
16334 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16335 CCode = X86::GetOppositeBranchCondition(CCode);
16336 CC = DAG.getConstant(CCode, MVT::i8);
16342 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16343 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16344 // It should be transformed during dag combiner except when the condition
16345 // is set by a arithmetics with overflow node.
16346 X86::CondCode CCode =
16347 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16348 CCode = X86::GetOppositeBranchCondition(CCode);
16349 CC = DAG.getConstant(CCode, MVT::i8);
16350 Cond = Cond.getOperand(0).getOperand(1);
16352 } else if (Cond.getOpcode() == ISD::SETCC &&
16353 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16354 // For FCMP_OEQ, we can emit
16355 // two branches instead of an explicit AND instruction with a
16356 // separate test. However, we only do this if this block doesn't
16357 // have a fall-through edge, because this requires an explicit
16358 // jmp when the condition is false.
16359 if (Op.getNode()->hasOneUse()) {
16360 SDNode *User = *Op.getNode()->use_begin();
16361 // Look for an unconditional branch following this conditional branch.
16362 // We need this because we need to reverse the successors in order
16363 // to implement FCMP_OEQ.
16364 if (User->getOpcode() == ISD::BR) {
16365 SDValue FalseBB = User->getOperand(1);
16367 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16368 assert(NewBR == User);
16372 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16373 Cond.getOperand(0), Cond.getOperand(1));
16374 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16375 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16376 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16377 Chain, Dest, CC, Cmp);
16378 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16383 } else if (Cond.getOpcode() == ISD::SETCC &&
16384 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16385 // For FCMP_UNE, we can emit
16386 // two branches instead of an explicit AND instruction with a
16387 // separate test. However, we only do this if this block doesn't
16388 // have a fall-through edge, because this requires an explicit
16389 // jmp when the condition is false.
16390 if (Op.getNode()->hasOneUse()) {
16391 SDNode *User = *Op.getNode()->use_begin();
16392 // Look for an unconditional branch following this conditional branch.
16393 // We need this because we need to reverse the successors in order
16394 // to implement FCMP_UNE.
16395 if (User->getOpcode() == ISD::BR) {
16396 SDValue FalseBB = User->getOperand(1);
16398 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16399 assert(NewBR == User);
16402 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16403 Cond.getOperand(0), Cond.getOperand(1));
16404 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16405 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16406 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16407 Chain, Dest, CC, Cmp);
16408 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16418 // Look pass the truncate if the high bits are known zero.
16419 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16420 Cond = Cond.getOperand(0);
16422 // We know the result of AND is compared against zero. Try to match
16424 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16425 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16426 if (NewSetCC.getNode()) {
16427 CC = NewSetCC.getOperand(0);
16428 Cond = NewSetCC.getOperand(1);
16435 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16436 CC = DAG.getConstant(X86Cond, MVT::i8);
16437 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16439 Cond = ConvertCmpIfNecessary(Cond, DAG);
16440 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16441 Chain, Dest, CC, Cond);
16444 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16445 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16446 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16447 // that the guard pages used by the OS virtual memory manager are allocated in
16448 // correct sequence.
16450 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16451 SelectionDAG &DAG) const {
16452 MachineFunction &MF = DAG.getMachineFunction();
16453 bool SplitStack = MF.shouldSplitStack();
16454 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16460 SDNode* Node = Op.getNode();
16462 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16463 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16464 " not tell us which reg is the stack pointer!");
16465 EVT VT = Node->getValueType(0);
16466 SDValue Tmp1 = SDValue(Node, 0);
16467 SDValue Tmp2 = SDValue(Node, 1);
16468 SDValue Tmp3 = Node->getOperand(2);
16469 SDValue Chain = Tmp1.getOperand(0);
16471 // Chain the dynamic stack allocation so that it doesn't modify the stack
16472 // pointer when other instructions are using the stack.
16473 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16476 SDValue Size = Tmp2.getOperand(1);
16477 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16478 Chain = SP.getValue(1);
16479 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16480 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16481 unsigned StackAlign = TFI.getStackAlignment();
16482 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16483 if (Align > StackAlign)
16484 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16485 DAG.getConstant(-(uint64_t)Align, VT));
16486 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16488 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16489 DAG.getIntPtrConstant(0, true), SDValue(),
16492 SDValue Ops[2] = { Tmp1, Tmp2 };
16493 return DAG.getMergeValues(Ops, dl);
16497 SDValue Chain = Op.getOperand(0);
16498 SDValue Size = Op.getOperand(1);
16499 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16500 EVT VT = Op.getNode()->getValueType(0);
16502 bool Is64Bit = Subtarget->is64Bit();
16503 EVT SPTy = getPointerTy();
16506 MachineRegisterInfo &MRI = MF.getRegInfo();
16509 // The 64 bit implementation of segmented stacks needs to clobber both r10
16510 // r11. This makes it impossible to use it along with nested parameters.
16511 const Function *F = MF.getFunction();
16513 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16515 if (I->hasNestAttr())
16516 report_fatal_error("Cannot use segmented stacks with functions that "
16517 "have nested arguments.");
16520 const TargetRegisterClass *AddrRegClass =
16521 getRegClassFor(getPointerTy());
16522 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16523 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16524 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16525 DAG.getRegister(Vreg, SPTy));
16526 SDValue Ops1[2] = { Value, Chain };
16527 return DAG.getMergeValues(Ops1, dl);
16530 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16532 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16533 Flag = Chain.getValue(1);
16534 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16536 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16538 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16539 DAG.getSubtarget().getRegisterInfo());
16540 unsigned SPReg = RegInfo->getStackRegister();
16541 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16542 Chain = SP.getValue(1);
16545 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16546 DAG.getConstant(-(uint64_t)Align, VT));
16547 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16550 SDValue Ops1[2] = { SP, Chain };
16551 return DAG.getMergeValues(Ops1, dl);
16555 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16556 MachineFunction &MF = DAG.getMachineFunction();
16557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16559 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16562 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16563 // vastart just stores the address of the VarArgsFrameIndex slot into the
16564 // memory location argument.
16565 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16567 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16568 MachinePointerInfo(SV), false, false, 0);
16572 // gp_offset (0 - 6 * 8)
16573 // fp_offset (48 - 48 + 8 * 16)
16574 // overflow_arg_area (point to parameters coming in memory).
16576 SmallVector<SDValue, 8> MemOps;
16577 SDValue FIN = Op.getOperand(1);
16579 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16580 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16582 FIN, MachinePointerInfo(SV), false, false, 0);
16583 MemOps.push_back(Store);
16586 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16587 FIN, DAG.getIntPtrConstant(4));
16588 Store = DAG.getStore(Op.getOperand(0), DL,
16589 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16591 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16592 MemOps.push_back(Store);
16594 // Store ptr to overflow_arg_area
16595 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16596 FIN, DAG.getIntPtrConstant(4));
16597 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16599 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16600 MachinePointerInfo(SV, 8),
16602 MemOps.push_back(Store);
16604 // Store ptr to reg_save_area.
16605 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16606 FIN, DAG.getIntPtrConstant(8));
16607 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16609 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16610 MachinePointerInfo(SV, 16), false, false, 0);
16611 MemOps.push_back(Store);
16612 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16615 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16616 assert(Subtarget->is64Bit() &&
16617 "LowerVAARG only handles 64-bit va_arg!");
16618 assert((Subtarget->isTargetLinux() ||
16619 Subtarget->isTargetDarwin()) &&
16620 "Unhandled target in LowerVAARG");
16621 assert(Op.getNode()->getNumOperands() == 4);
16622 SDValue Chain = Op.getOperand(0);
16623 SDValue SrcPtr = Op.getOperand(1);
16624 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16625 unsigned Align = Op.getConstantOperandVal(3);
16628 EVT ArgVT = Op.getNode()->getValueType(0);
16629 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16630 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16633 // Decide which area this value should be read from.
16634 // TODO: Implement the AMD64 ABI in its entirety. This simple
16635 // selection mechanism works only for the basic types.
16636 if (ArgVT == MVT::f80) {
16637 llvm_unreachable("va_arg for f80 not yet implemented");
16638 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16639 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16640 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16641 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16643 llvm_unreachable("Unhandled argument type in LowerVAARG");
16646 if (ArgMode == 2) {
16647 // Sanity Check: Make sure using fp_offset makes sense.
16648 assert(!DAG.getTarget().Options.UseSoftFloat &&
16649 !(DAG.getMachineFunction()
16650 .getFunction()->getAttributes()
16651 .hasAttribute(AttributeSet::FunctionIndex,
16652 Attribute::NoImplicitFloat)) &&
16653 Subtarget->hasSSE1());
16656 // Insert VAARG_64 node into the DAG
16657 // VAARG_64 returns two values: Variable Argument Address, Chain
16658 SmallVector<SDValue, 11> InstOps;
16659 InstOps.push_back(Chain);
16660 InstOps.push_back(SrcPtr);
16661 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16662 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16663 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16664 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16665 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16666 VTs, InstOps, MVT::i64,
16667 MachinePointerInfo(SV),
16669 /*Volatile=*/false,
16671 /*WriteMem=*/true);
16672 Chain = VAARG.getValue(1);
16674 // Load the next argument and return it
16675 return DAG.getLoad(ArgVT, dl,
16678 MachinePointerInfo(),
16679 false, false, false, 0);
16682 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16683 SelectionDAG &DAG) {
16684 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16685 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16686 SDValue Chain = Op.getOperand(0);
16687 SDValue DstPtr = Op.getOperand(1);
16688 SDValue SrcPtr = Op.getOperand(2);
16689 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16690 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16693 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16694 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16696 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16699 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16700 // amount is a constant. Takes immediate version of shift as input.
16701 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16702 SDValue SrcOp, uint64_t ShiftAmt,
16703 SelectionDAG &DAG) {
16704 MVT ElementType = VT.getVectorElementType();
16706 // Fold this packed shift into its first operand if ShiftAmt is 0.
16710 // Check for ShiftAmt >= element width
16711 if (ShiftAmt >= ElementType.getSizeInBits()) {
16712 if (Opc == X86ISD::VSRAI)
16713 ShiftAmt = ElementType.getSizeInBits() - 1;
16715 return DAG.getConstant(0, VT);
16718 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16719 && "Unknown target vector shift-by-constant node");
16721 // Fold this packed vector shift into a build vector if SrcOp is a
16722 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16723 if (VT == SrcOp.getSimpleValueType() &&
16724 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16725 SmallVector<SDValue, 8> Elts;
16726 unsigned NumElts = SrcOp->getNumOperands();
16727 ConstantSDNode *ND;
16730 default: llvm_unreachable(nullptr);
16731 case X86ISD::VSHLI:
16732 for (unsigned i=0; i!=NumElts; ++i) {
16733 SDValue CurrentOp = SrcOp->getOperand(i);
16734 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16735 Elts.push_back(CurrentOp);
16738 ND = cast<ConstantSDNode>(CurrentOp);
16739 const APInt &C = ND->getAPIntValue();
16740 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16743 case X86ISD::VSRLI:
16744 for (unsigned i=0; i!=NumElts; ++i) {
16745 SDValue CurrentOp = SrcOp->getOperand(i);
16746 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16747 Elts.push_back(CurrentOp);
16750 ND = cast<ConstantSDNode>(CurrentOp);
16751 const APInt &C = ND->getAPIntValue();
16752 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16755 case X86ISD::VSRAI:
16756 for (unsigned i=0; i!=NumElts; ++i) {
16757 SDValue CurrentOp = SrcOp->getOperand(i);
16758 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16759 Elts.push_back(CurrentOp);
16762 ND = cast<ConstantSDNode>(CurrentOp);
16763 const APInt &C = ND->getAPIntValue();
16764 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16769 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16772 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16775 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16776 // may or may not be a constant. Takes immediate version of shift as input.
16777 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16778 SDValue SrcOp, SDValue ShAmt,
16779 SelectionDAG &DAG) {
16780 MVT SVT = ShAmt.getSimpleValueType();
16781 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16783 // Catch shift-by-constant.
16784 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16785 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16786 CShAmt->getZExtValue(), DAG);
16788 // Change opcode to non-immediate version
16790 default: llvm_unreachable("Unknown target vector shift node");
16791 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16792 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16793 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16796 const X86Subtarget &Subtarget =
16797 DAG.getTarget().getSubtarget<X86Subtarget>();
16798 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16799 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16800 // Let the shuffle legalizer expand this shift amount node.
16801 SDValue Op0 = ShAmt.getOperand(0);
16802 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16803 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16805 // Need to build a vector containing shift amount.
16806 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16807 SmallVector<SDValue, 4> ShOps;
16808 ShOps.push_back(ShAmt);
16809 if (SVT == MVT::i32) {
16810 ShOps.push_back(DAG.getConstant(0, SVT));
16811 ShOps.push_back(DAG.getUNDEF(SVT));
16813 ShOps.push_back(DAG.getUNDEF(SVT));
16815 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16816 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16819 // The return type has to be a 128-bit type with the same element
16820 // type as the input type.
16821 MVT EltVT = VT.getVectorElementType();
16822 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16824 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16825 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16828 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16829 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16830 /// necessary casting for \p Mask when lowering masking intrinsics.
16831 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16832 SDValue PreservedSrc,
16833 const X86Subtarget *Subtarget,
16834 SelectionDAG &DAG) {
16835 EVT VT = Op.getValueType();
16836 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16837 MVT::i1, VT.getVectorNumElements());
16838 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16839 Mask.getValueType().getSizeInBits());
16842 assert(MaskVT.isSimple() && "invalid mask type");
16844 if (isAllOnes(Mask))
16847 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16848 // are extracted by EXTRACT_SUBVECTOR.
16849 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16850 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16851 DAG.getIntPtrConstant(0));
16853 switch (Op.getOpcode()) {
16855 case X86ISD::PCMPEQM:
16856 case X86ISD::PCMPGTM:
16858 case X86ISD::CMPMU:
16859 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16861 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16862 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16863 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16866 /// \brief Creates an SDNode for a predicated scalar operation.
16867 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16868 /// The mask is comming as MVT::i8 and it should be truncated
16869 /// to MVT::i1 while lowering masking intrinsics.
16870 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16871 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16872 /// a scalar instruction.
16873 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16874 SDValue PreservedSrc,
16875 const X86Subtarget *Subtarget,
16876 SelectionDAG &DAG) {
16877 if (isAllOnes(Mask))
16880 EVT VT = Op.getValueType();
16882 // The mask should be of type MVT::i1
16883 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16885 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16886 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16887 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16890 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16892 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16893 case Intrinsic::x86_fma_vfmadd_ps:
16894 case Intrinsic::x86_fma_vfmadd_pd:
16895 case Intrinsic::x86_fma_vfmadd_ps_256:
16896 case Intrinsic::x86_fma_vfmadd_pd_256:
16897 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16898 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16899 return X86ISD::FMADD;
16900 case Intrinsic::x86_fma_vfmsub_ps:
16901 case Intrinsic::x86_fma_vfmsub_pd:
16902 case Intrinsic::x86_fma_vfmsub_ps_256:
16903 case Intrinsic::x86_fma_vfmsub_pd_256:
16904 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16905 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16906 return X86ISD::FMSUB;
16907 case Intrinsic::x86_fma_vfnmadd_ps:
16908 case Intrinsic::x86_fma_vfnmadd_pd:
16909 case Intrinsic::x86_fma_vfnmadd_ps_256:
16910 case Intrinsic::x86_fma_vfnmadd_pd_256:
16911 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16912 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16913 return X86ISD::FNMADD;
16914 case Intrinsic::x86_fma_vfnmsub_ps:
16915 case Intrinsic::x86_fma_vfnmsub_pd:
16916 case Intrinsic::x86_fma_vfnmsub_ps_256:
16917 case Intrinsic::x86_fma_vfnmsub_pd_256:
16918 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16919 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16920 return X86ISD::FNMSUB;
16921 case Intrinsic::x86_fma_vfmaddsub_ps:
16922 case Intrinsic::x86_fma_vfmaddsub_pd:
16923 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16924 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16925 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16926 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16927 return X86ISD::FMADDSUB;
16928 case Intrinsic::x86_fma_vfmsubadd_ps:
16929 case Intrinsic::x86_fma_vfmsubadd_pd:
16930 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16931 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16932 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16933 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16934 return X86ISD::FMSUBADD;
16938 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16939 SelectionDAG &DAG) {
16941 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16942 EVT VT = Op.getValueType();
16943 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16945 switch(IntrData->Type) {
16946 case INTR_TYPE_1OP:
16947 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16948 case INTR_TYPE_2OP:
16949 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16951 case INTR_TYPE_3OP:
16952 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16953 Op.getOperand(2), Op.getOperand(3));
16954 case INTR_TYPE_1OP_MASK_RM: {
16955 SDValue Src = Op.getOperand(1);
16956 SDValue Src0 = Op.getOperand(2);
16957 SDValue Mask = Op.getOperand(3);
16958 SDValue RoundingMode = Op.getOperand(4);
16959 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16961 Mask, Src0, Subtarget, DAG);
16963 case INTR_TYPE_SCALAR_MASK_RM: {
16964 SDValue Src1 = Op.getOperand(1);
16965 SDValue Src2 = Op.getOperand(2);
16966 SDValue Src0 = Op.getOperand(3);
16967 SDValue Mask = Op.getOperand(4);
16968 SDValue RoundingMode = Op.getOperand(5);
16969 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16971 Mask, Src0, Subtarget, DAG);
16973 case INTR_TYPE_2OP_MASK: {
16974 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16976 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16979 case CMP_MASK_CC: {
16980 // Comparison intrinsics with masks.
16981 // Example of transformation:
16982 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16983 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16985 // (v8i1 (insert_subvector undef,
16986 // (v2i1 (and (PCMPEQM %a, %b),
16987 // (extract_subvector
16988 // (v8i1 (bitcast %mask)), 0))), 0))))
16989 EVT VT = Op.getOperand(1).getValueType();
16990 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16991 VT.getVectorNumElements());
16992 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16993 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16994 Mask.getValueType().getSizeInBits());
16996 if (IntrData->Type == CMP_MASK_CC) {
16997 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16998 Op.getOperand(2), Op.getOperand(3));
17000 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
17001 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17004 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
17005 DAG.getTargetConstant(0, MaskVT),
17007 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
17008 DAG.getUNDEF(BitcastVT), CmpMask,
17009 DAG.getIntPtrConstant(0));
17010 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17012 case COMI: { // Comparison intrinsics
17013 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17014 SDValue LHS = Op.getOperand(1);
17015 SDValue RHS = Op.getOperand(2);
17016 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17017 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17018 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17019 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17020 DAG.getConstant(X86CC, MVT::i8), Cond);
17021 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17024 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17025 Op.getOperand(1), Op.getOperand(2), DAG);
17027 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17028 Op.getSimpleValueType(),
17030 Op.getOperand(2), DAG),
17031 Op.getOperand(4), Op.getOperand(3), Subtarget,
17033 case COMPRESS_EXPAND_IN_REG: {
17034 SDValue Mask = Op.getOperand(3);
17035 SDValue DataToCompress = Op.getOperand(1);
17036 SDValue PassThru = Op.getOperand(2);
17037 if (isAllOnes(Mask)) // return data as is
17038 return Op.getOperand(1);
17039 EVT VT = Op.getValueType();
17040 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17041 VT.getVectorNumElements());
17042 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17043 Mask.getValueType().getSizeInBits());
17045 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17046 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17047 DAG.getIntPtrConstant(0));
17049 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17053 SDValue Mask = Op.getOperand(3);
17054 EVT VT = Op.getValueType();
17055 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17056 VT.getVectorNumElements());
17057 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17058 Mask.getValueType().getSizeInBits());
17060 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17061 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17062 DAG.getIntPtrConstant(0));
17063 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17068 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17069 dl, Op.getValueType(),
17073 Op.getOperand(4), Op.getOperand(1),
17082 default: return SDValue(); // Don't custom lower most intrinsics.
17084 case Intrinsic::x86_avx512_mask_valign_q_512:
17085 case Intrinsic::x86_avx512_mask_valign_d_512:
17086 // Vector source operands are swapped.
17087 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17088 Op.getValueType(), Op.getOperand(2),
17091 Op.getOperand(5), Op.getOperand(4),
17094 // ptest and testp intrinsics. The intrinsic these come from are designed to
17095 // return an integer value, not just an instruction so lower it to the ptest
17096 // or testp pattern and a setcc for the result.
17097 case Intrinsic::x86_sse41_ptestz:
17098 case Intrinsic::x86_sse41_ptestc:
17099 case Intrinsic::x86_sse41_ptestnzc:
17100 case Intrinsic::x86_avx_ptestz_256:
17101 case Intrinsic::x86_avx_ptestc_256:
17102 case Intrinsic::x86_avx_ptestnzc_256:
17103 case Intrinsic::x86_avx_vtestz_ps:
17104 case Intrinsic::x86_avx_vtestc_ps:
17105 case Intrinsic::x86_avx_vtestnzc_ps:
17106 case Intrinsic::x86_avx_vtestz_pd:
17107 case Intrinsic::x86_avx_vtestc_pd:
17108 case Intrinsic::x86_avx_vtestnzc_pd:
17109 case Intrinsic::x86_avx_vtestz_ps_256:
17110 case Intrinsic::x86_avx_vtestc_ps_256:
17111 case Intrinsic::x86_avx_vtestnzc_ps_256:
17112 case Intrinsic::x86_avx_vtestz_pd_256:
17113 case Intrinsic::x86_avx_vtestc_pd_256:
17114 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17115 bool IsTestPacked = false;
17118 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17119 case Intrinsic::x86_avx_vtestz_ps:
17120 case Intrinsic::x86_avx_vtestz_pd:
17121 case Intrinsic::x86_avx_vtestz_ps_256:
17122 case Intrinsic::x86_avx_vtestz_pd_256:
17123 IsTestPacked = true; // Fallthrough
17124 case Intrinsic::x86_sse41_ptestz:
17125 case Intrinsic::x86_avx_ptestz_256:
17127 X86CC = X86::COND_E;
17129 case Intrinsic::x86_avx_vtestc_ps:
17130 case Intrinsic::x86_avx_vtestc_pd:
17131 case Intrinsic::x86_avx_vtestc_ps_256:
17132 case Intrinsic::x86_avx_vtestc_pd_256:
17133 IsTestPacked = true; // Fallthrough
17134 case Intrinsic::x86_sse41_ptestc:
17135 case Intrinsic::x86_avx_ptestc_256:
17137 X86CC = X86::COND_B;
17139 case Intrinsic::x86_avx_vtestnzc_ps:
17140 case Intrinsic::x86_avx_vtestnzc_pd:
17141 case Intrinsic::x86_avx_vtestnzc_ps_256:
17142 case Intrinsic::x86_avx_vtestnzc_pd_256:
17143 IsTestPacked = true; // Fallthrough
17144 case Intrinsic::x86_sse41_ptestnzc:
17145 case Intrinsic::x86_avx_ptestnzc_256:
17147 X86CC = X86::COND_A;
17151 SDValue LHS = Op.getOperand(1);
17152 SDValue RHS = Op.getOperand(2);
17153 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17154 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17155 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17156 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17157 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17159 case Intrinsic::x86_avx512_kortestz_w:
17160 case Intrinsic::x86_avx512_kortestc_w: {
17161 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17162 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17163 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17164 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17165 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17166 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17167 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17170 case Intrinsic::x86_sse42_pcmpistria128:
17171 case Intrinsic::x86_sse42_pcmpestria128:
17172 case Intrinsic::x86_sse42_pcmpistric128:
17173 case Intrinsic::x86_sse42_pcmpestric128:
17174 case Intrinsic::x86_sse42_pcmpistrio128:
17175 case Intrinsic::x86_sse42_pcmpestrio128:
17176 case Intrinsic::x86_sse42_pcmpistris128:
17177 case Intrinsic::x86_sse42_pcmpestris128:
17178 case Intrinsic::x86_sse42_pcmpistriz128:
17179 case Intrinsic::x86_sse42_pcmpestriz128: {
17183 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17184 case Intrinsic::x86_sse42_pcmpistria128:
17185 Opcode = X86ISD::PCMPISTRI;
17186 X86CC = X86::COND_A;
17188 case Intrinsic::x86_sse42_pcmpestria128:
17189 Opcode = X86ISD::PCMPESTRI;
17190 X86CC = X86::COND_A;
17192 case Intrinsic::x86_sse42_pcmpistric128:
17193 Opcode = X86ISD::PCMPISTRI;
17194 X86CC = X86::COND_B;
17196 case Intrinsic::x86_sse42_pcmpestric128:
17197 Opcode = X86ISD::PCMPESTRI;
17198 X86CC = X86::COND_B;
17200 case Intrinsic::x86_sse42_pcmpistrio128:
17201 Opcode = X86ISD::PCMPISTRI;
17202 X86CC = X86::COND_O;
17204 case Intrinsic::x86_sse42_pcmpestrio128:
17205 Opcode = X86ISD::PCMPESTRI;
17206 X86CC = X86::COND_O;
17208 case Intrinsic::x86_sse42_pcmpistris128:
17209 Opcode = X86ISD::PCMPISTRI;
17210 X86CC = X86::COND_S;
17212 case Intrinsic::x86_sse42_pcmpestris128:
17213 Opcode = X86ISD::PCMPESTRI;
17214 X86CC = X86::COND_S;
17216 case Intrinsic::x86_sse42_pcmpistriz128:
17217 Opcode = X86ISD::PCMPISTRI;
17218 X86CC = X86::COND_E;
17220 case Intrinsic::x86_sse42_pcmpestriz128:
17221 Opcode = X86ISD::PCMPESTRI;
17222 X86CC = X86::COND_E;
17225 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17226 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17227 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17228 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17229 DAG.getConstant(X86CC, MVT::i8),
17230 SDValue(PCMP.getNode(), 1));
17231 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17234 case Intrinsic::x86_sse42_pcmpistri128:
17235 case Intrinsic::x86_sse42_pcmpestri128: {
17237 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17238 Opcode = X86ISD::PCMPISTRI;
17240 Opcode = X86ISD::PCMPESTRI;
17242 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17243 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17244 return DAG.getNode(Opcode, dl, VTs, NewOps);
17247 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17248 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17249 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17250 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17251 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17252 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17253 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17254 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17255 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17256 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17257 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17258 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17259 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17260 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17261 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17262 dl, Op.getValueType(),
17266 Op.getOperand(4), Op.getOperand(1),
17272 case Intrinsic::x86_fma_vfmadd_ps:
17273 case Intrinsic::x86_fma_vfmadd_pd:
17274 case Intrinsic::x86_fma_vfmsub_ps:
17275 case Intrinsic::x86_fma_vfmsub_pd:
17276 case Intrinsic::x86_fma_vfnmadd_ps:
17277 case Intrinsic::x86_fma_vfnmadd_pd:
17278 case Intrinsic::x86_fma_vfnmsub_ps:
17279 case Intrinsic::x86_fma_vfnmsub_pd:
17280 case Intrinsic::x86_fma_vfmaddsub_ps:
17281 case Intrinsic::x86_fma_vfmaddsub_pd:
17282 case Intrinsic::x86_fma_vfmsubadd_ps:
17283 case Intrinsic::x86_fma_vfmsubadd_pd:
17284 case Intrinsic::x86_fma_vfmadd_ps_256:
17285 case Intrinsic::x86_fma_vfmadd_pd_256:
17286 case Intrinsic::x86_fma_vfmsub_ps_256:
17287 case Intrinsic::x86_fma_vfmsub_pd_256:
17288 case Intrinsic::x86_fma_vfnmadd_ps_256:
17289 case Intrinsic::x86_fma_vfnmadd_pd_256:
17290 case Intrinsic::x86_fma_vfnmsub_ps_256:
17291 case Intrinsic::x86_fma_vfnmsub_pd_256:
17292 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17293 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17294 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17295 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17296 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17297 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17301 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17302 SDValue Src, SDValue Mask, SDValue Base,
17303 SDValue Index, SDValue ScaleOp, SDValue Chain,
17304 const X86Subtarget * Subtarget) {
17306 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17307 assert(C && "Invalid scale type");
17308 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17309 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17310 Index.getSimpleValueType().getVectorNumElements());
17312 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17314 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17316 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17317 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17318 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17319 SDValue Segment = DAG.getRegister(0, MVT::i32);
17320 if (Src.getOpcode() == ISD::UNDEF)
17321 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17322 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17323 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17324 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17325 return DAG.getMergeValues(RetOps, dl);
17328 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17329 SDValue Src, SDValue Mask, SDValue Base,
17330 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17332 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17333 assert(C && "Invalid scale type");
17334 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17335 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17336 SDValue Segment = DAG.getRegister(0, MVT::i32);
17337 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17338 Index.getSimpleValueType().getVectorNumElements());
17340 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17342 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17344 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17345 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17346 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17347 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17348 return SDValue(Res, 1);
17351 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17352 SDValue Mask, SDValue Base, SDValue Index,
17353 SDValue ScaleOp, SDValue Chain) {
17355 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17356 assert(C && "Invalid scale type");
17357 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17358 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17359 SDValue Segment = DAG.getRegister(0, MVT::i32);
17361 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17363 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17365 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17367 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17368 //SDVTList VTs = DAG.getVTList(MVT::Other);
17369 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17370 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17371 return SDValue(Res, 0);
17374 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17375 // read performance monitor counters (x86_rdpmc).
17376 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17377 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17378 SmallVectorImpl<SDValue> &Results) {
17379 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17380 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17383 // The ECX register is used to select the index of the performance counter
17385 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17387 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17389 // Reads the content of a 64-bit performance counter and returns it in the
17390 // registers EDX:EAX.
17391 if (Subtarget->is64Bit()) {
17392 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17393 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17396 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17397 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17400 Chain = HI.getValue(1);
17402 if (Subtarget->is64Bit()) {
17403 // The EAX register is loaded with the low-order 32 bits. The EDX register
17404 // is loaded with the supported high-order bits of the counter.
17405 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17406 DAG.getConstant(32, MVT::i8));
17407 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17408 Results.push_back(Chain);
17412 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17413 SDValue Ops[] = { LO, HI };
17414 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17415 Results.push_back(Pair);
17416 Results.push_back(Chain);
17419 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17420 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17421 // also used to custom lower READCYCLECOUNTER nodes.
17422 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17423 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17424 SmallVectorImpl<SDValue> &Results) {
17425 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17426 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17429 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17430 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17431 // and the EAX register is loaded with the low-order 32 bits.
17432 if (Subtarget->is64Bit()) {
17433 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17434 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17437 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17438 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17441 SDValue Chain = HI.getValue(1);
17443 if (Opcode == X86ISD::RDTSCP_DAG) {
17444 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17446 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17447 // the ECX register. Add 'ecx' explicitly to the chain.
17448 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17450 // Explicitly store the content of ECX at the location passed in input
17451 // to the 'rdtscp' intrinsic.
17452 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17453 MachinePointerInfo(), false, false, 0);
17456 if (Subtarget->is64Bit()) {
17457 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17458 // the EAX register is loaded with the low-order 32 bits.
17459 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17460 DAG.getConstant(32, MVT::i8));
17461 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17462 Results.push_back(Chain);
17466 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17467 SDValue Ops[] = { LO, HI };
17468 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17469 Results.push_back(Pair);
17470 Results.push_back(Chain);
17473 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17474 SelectionDAG &DAG) {
17475 SmallVector<SDValue, 2> Results;
17477 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17479 return DAG.getMergeValues(Results, DL);
17483 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17484 SelectionDAG &DAG) {
17485 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17487 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17492 switch(IntrData->Type) {
17494 llvm_unreachable("Unknown Intrinsic Type");
17498 // Emit the node with the right value type.
17499 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17500 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17502 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17503 // Otherwise return the value from Rand, which is always 0, casted to i32.
17504 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17505 DAG.getConstant(1, Op->getValueType(1)),
17506 DAG.getConstant(X86::COND_B, MVT::i32),
17507 SDValue(Result.getNode(), 1) };
17508 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17509 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17512 // Return { result, isValid, chain }.
17513 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17514 SDValue(Result.getNode(), 2));
17517 //gather(v1, mask, index, base, scale);
17518 SDValue Chain = Op.getOperand(0);
17519 SDValue Src = Op.getOperand(2);
17520 SDValue Base = Op.getOperand(3);
17521 SDValue Index = Op.getOperand(4);
17522 SDValue Mask = Op.getOperand(5);
17523 SDValue Scale = Op.getOperand(6);
17524 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17528 //scatter(base, mask, index, v1, scale);
17529 SDValue Chain = Op.getOperand(0);
17530 SDValue Base = Op.getOperand(2);
17531 SDValue Mask = Op.getOperand(3);
17532 SDValue Index = Op.getOperand(4);
17533 SDValue Src = Op.getOperand(5);
17534 SDValue Scale = Op.getOperand(6);
17535 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17538 SDValue Hint = Op.getOperand(6);
17540 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17541 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17542 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17543 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17544 SDValue Chain = Op.getOperand(0);
17545 SDValue Mask = Op.getOperand(2);
17546 SDValue Index = Op.getOperand(3);
17547 SDValue Base = Op.getOperand(4);
17548 SDValue Scale = Op.getOperand(5);
17549 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17551 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17553 SmallVector<SDValue, 2> Results;
17554 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17555 return DAG.getMergeValues(Results, dl);
17557 // Read Performance Monitoring Counters.
17559 SmallVector<SDValue, 2> Results;
17560 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17561 return DAG.getMergeValues(Results, dl);
17563 // XTEST intrinsics.
17565 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17566 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17567 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17568 DAG.getConstant(X86::COND_NE, MVT::i8),
17570 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17571 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17572 Ret, SDValue(InTrans.getNode(), 1));
17576 SmallVector<SDValue, 2> Results;
17577 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17578 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17579 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17580 DAG.getConstant(-1, MVT::i8));
17581 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17582 Op.getOperand(4), GenCF.getValue(1));
17583 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17584 Op.getOperand(5), MachinePointerInfo(),
17586 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17587 DAG.getConstant(X86::COND_B, MVT::i8),
17589 Results.push_back(SetCC);
17590 Results.push_back(Store);
17591 return DAG.getMergeValues(Results, dl);
17593 case COMPRESS_TO_MEM: {
17595 SDValue Mask = Op.getOperand(4);
17596 SDValue DataToCompress = Op.getOperand(3);
17597 SDValue Addr = Op.getOperand(2);
17598 SDValue Chain = Op.getOperand(0);
17600 if (isAllOnes(Mask)) // return just a store
17601 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17602 MachinePointerInfo(), false, false, 0);
17604 EVT VT = DataToCompress.getValueType();
17605 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17606 VT.getVectorNumElements());
17607 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17608 Mask.getValueType().getSizeInBits());
17609 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17610 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17611 DAG.getIntPtrConstant(0));
17613 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17614 DataToCompress, DAG.getUNDEF(VT));
17615 return DAG.getStore(Chain, dl, Compressed, Addr,
17616 MachinePointerInfo(), false, false, 0);
17618 case EXPAND_FROM_MEM: {
17620 SDValue Mask = Op.getOperand(4);
17621 SDValue PathThru = Op.getOperand(3);
17622 SDValue Addr = Op.getOperand(2);
17623 SDValue Chain = Op.getOperand(0);
17624 EVT VT = Op.getValueType();
17626 if (isAllOnes(Mask)) // return just a load
17627 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17629 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17630 VT.getVectorNumElements());
17631 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17632 Mask.getValueType().getSizeInBits());
17633 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17634 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17635 DAG.getIntPtrConstant(0));
17637 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17638 false, false, false, 0);
17640 SmallVector<SDValue, 2> Results;
17641 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17643 Results.push_back(Chain);
17644 return DAG.getMergeValues(Results, dl);
17649 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17650 SelectionDAG &DAG) const {
17651 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17652 MFI->setReturnAddressIsTaken(true);
17654 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17657 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17659 EVT PtrVT = getPointerTy();
17662 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17663 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17664 DAG.getSubtarget().getRegisterInfo());
17665 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17666 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17667 DAG.getNode(ISD::ADD, dl, PtrVT,
17668 FrameAddr, Offset),
17669 MachinePointerInfo(), false, false, false, 0);
17672 // Just load the return address.
17673 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17674 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17675 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17678 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17679 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17680 MFI->setFrameAddressIsTaken(true);
17682 EVT VT = Op.getValueType();
17683 SDLoc dl(Op); // FIXME probably not meaningful
17684 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17685 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17686 DAG.getSubtarget().getRegisterInfo());
17687 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17688 DAG.getMachineFunction());
17689 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17690 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17691 "Invalid Frame Register!");
17692 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17694 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17695 MachinePointerInfo(),
17696 false, false, false, 0);
17700 // FIXME? Maybe this could be a TableGen attribute on some registers and
17701 // this table could be generated automatically from RegInfo.
17702 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17704 unsigned Reg = StringSwitch<unsigned>(RegName)
17705 .Case("esp", X86::ESP)
17706 .Case("rsp", X86::RSP)
17710 report_fatal_error("Invalid register name global variable");
17713 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17714 SelectionDAG &DAG) const {
17715 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17716 DAG.getSubtarget().getRegisterInfo());
17717 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17720 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17721 SDValue Chain = Op.getOperand(0);
17722 SDValue Offset = Op.getOperand(1);
17723 SDValue Handler = Op.getOperand(2);
17726 EVT PtrVT = getPointerTy();
17727 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17728 DAG.getSubtarget().getRegisterInfo());
17729 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17730 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17731 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17732 "Invalid Frame Register!");
17733 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17734 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17736 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17737 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17738 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17739 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17741 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17743 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17744 DAG.getRegister(StoreAddrReg, PtrVT));
17747 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17748 SelectionDAG &DAG) const {
17750 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17751 DAG.getVTList(MVT::i32, MVT::Other),
17752 Op.getOperand(0), Op.getOperand(1));
17755 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17756 SelectionDAG &DAG) const {
17758 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17759 Op.getOperand(0), Op.getOperand(1));
17762 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17763 return Op.getOperand(0);
17766 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17767 SelectionDAG &DAG) const {
17768 SDValue Root = Op.getOperand(0);
17769 SDValue Trmp = Op.getOperand(1); // trampoline
17770 SDValue FPtr = Op.getOperand(2); // nested function
17771 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17774 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17775 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17777 if (Subtarget->is64Bit()) {
17778 SDValue OutChains[6];
17780 // Large code-model.
17781 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17782 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17784 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17785 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17787 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17789 // Load the pointer to the nested function into R11.
17790 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17791 SDValue Addr = Trmp;
17792 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17793 Addr, MachinePointerInfo(TrmpAddr),
17796 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17797 DAG.getConstant(2, MVT::i64));
17798 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17799 MachinePointerInfo(TrmpAddr, 2),
17802 // Load the 'nest' parameter value into R10.
17803 // R10 is specified in X86CallingConv.td
17804 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17806 DAG.getConstant(10, MVT::i64));
17807 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17808 Addr, MachinePointerInfo(TrmpAddr, 10),
17811 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17812 DAG.getConstant(12, MVT::i64));
17813 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17814 MachinePointerInfo(TrmpAddr, 12),
17817 // Jump to the nested function.
17818 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17820 DAG.getConstant(20, MVT::i64));
17821 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17822 Addr, MachinePointerInfo(TrmpAddr, 20),
17825 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17826 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17827 DAG.getConstant(22, MVT::i64));
17828 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17829 MachinePointerInfo(TrmpAddr, 22),
17832 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17834 const Function *Func =
17835 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17836 CallingConv::ID CC = Func->getCallingConv();
17841 llvm_unreachable("Unsupported calling convention");
17842 case CallingConv::C:
17843 case CallingConv::X86_StdCall: {
17844 // Pass 'nest' parameter in ECX.
17845 // Must be kept in sync with X86CallingConv.td
17846 NestReg = X86::ECX;
17848 // Check that ECX wasn't needed by an 'inreg' parameter.
17849 FunctionType *FTy = Func->getFunctionType();
17850 const AttributeSet &Attrs = Func->getAttributes();
17852 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17853 unsigned InRegCount = 0;
17856 for (FunctionType::param_iterator I = FTy->param_begin(),
17857 E = FTy->param_end(); I != E; ++I, ++Idx)
17858 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17859 // FIXME: should only count parameters that are lowered to integers.
17860 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17862 if (InRegCount > 2) {
17863 report_fatal_error("Nest register in use - reduce number of inreg"
17869 case CallingConv::X86_FastCall:
17870 case CallingConv::X86_ThisCall:
17871 case CallingConv::Fast:
17872 // Pass 'nest' parameter in EAX.
17873 // Must be kept in sync with X86CallingConv.td
17874 NestReg = X86::EAX;
17878 SDValue OutChains[4];
17879 SDValue Addr, Disp;
17881 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17882 DAG.getConstant(10, MVT::i32));
17883 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17885 // This is storing the opcode for MOV32ri.
17886 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17887 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17888 OutChains[0] = DAG.getStore(Root, dl,
17889 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17890 Trmp, MachinePointerInfo(TrmpAddr),
17893 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17894 DAG.getConstant(1, MVT::i32));
17895 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17896 MachinePointerInfo(TrmpAddr, 1),
17899 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17901 DAG.getConstant(5, MVT::i32));
17902 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17903 MachinePointerInfo(TrmpAddr, 5),
17906 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17907 DAG.getConstant(6, MVT::i32));
17908 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17909 MachinePointerInfo(TrmpAddr, 6),
17912 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17916 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17917 SelectionDAG &DAG) const {
17919 The rounding mode is in bits 11:10 of FPSR, and has the following
17921 00 Round to nearest
17926 FLT_ROUNDS, on the other hand, expects the following:
17933 To perform the conversion, we do:
17934 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17937 MachineFunction &MF = DAG.getMachineFunction();
17938 const TargetMachine &TM = MF.getTarget();
17939 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17940 unsigned StackAlignment = TFI.getStackAlignment();
17941 MVT VT = Op.getSimpleValueType();
17944 // Save FP Control Word to stack slot
17945 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17946 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17948 MachineMemOperand *MMO =
17949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17950 MachineMemOperand::MOStore, 2, 2);
17952 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17953 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17954 DAG.getVTList(MVT::Other),
17955 Ops, MVT::i16, MMO);
17957 // Load FP Control Word from stack slot
17958 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17959 MachinePointerInfo(), false, false, false, 0);
17961 // Transform as necessary
17963 DAG.getNode(ISD::SRL, DL, MVT::i16,
17964 DAG.getNode(ISD::AND, DL, MVT::i16,
17965 CWD, DAG.getConstant(0x800, MVT::i16)),
17966 DAG.getConstant(11, MVT::i8));
17968 DAG.getNode(ISD::SRL, DL, MVT::i16,
17969 DAG.getNode(ISD::AND, DL, MVT::i16,
17970 CWD, DAG.getConstant(0x400, MVT::i16)),
17971 DAG.getConstant(9, MVT::i8));
17974 DAG.getNode(ISD::AND, DL, MVT::i16,
17975 DAG.getNode(ISD::ADD, DL, MVT::i16,
17976 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17977 DAG.getConstant(1, MVT::i16)),
17978 DAG.getConstant(3, MVT::i16));
17980 return DAG.getNode((VT.getSizeInBits() < 16 ?
17981 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17984 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17985 MVT VT = Op.getSimpleValueType();
17987 unsigned NumBits = VT.getSizeInBits();
17990 Op = Op.getOperand(0);
17991 if (VT == MVT::i8) {
17992 // Zero extend to i32 since there is not an i8 bsr.
17994 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17997 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17998 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17999 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18001 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18004 DAG.getConstant(NumBits+NumBits-1, OpVT),
18005 DAG.getConstant(X86::COND_E, MVT::i8),
18008 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18010 // Finally xor with NumBits-1.
18011 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18014 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18018 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18019 MVT VT = Op.getSimpleValueType();
18021 unsigned NumBits = VT.getSizeInBits();
18024 Op = Op.getOperand(0);
18025 if (VT == MVT::i8) {
18026 // Zero extend to i32 since there is not an i8 bsr.
18028 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18031 // Issue a bsr (scan bits in reverse).
18032 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18033 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18035 // And xor with NumBits-1.
18036 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18039 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18043 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18044 MVT VT = Op.getSimpleValueType();
18045 unsigned NumBits = VT.getSizeInBits();
18047 Op = Op.getOperand(0);
18049 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18050 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18051 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18053 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18056 DAG.getConstant(NumBits, VT),
18057 DAG.getConstant(X86::COND_E, MVT::i8),
18060 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18063 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18064 // ones, and then concatenate the result back.
18065 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18066 MVT VT = Op.getSimpleValueType();
18068 assert(VT.is256BitVector() && VT.isInteger() &&
18069 "Unsupported value type for operation");
18071 unsigned NumElems = VT.getVectorNumElements();
18074 // Extract the LHS vectors
18075 SDValue LHS = Op.getOperand(0);
18076 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18077 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18079 // Extract the RHS vectors
18080 SDValue RHS = Op.getOperand(1);
18081 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18082 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18084 MVT EltVT = VT.getVectorElementType();
18085 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18087 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18088 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18089 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18092 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18093 assert(Op.getSimpleValueType().is256BitVector() &&
18094 Op.getSimpleValueType().isInteger() &&
18095 "Only handle AVX 256-bit vector integer operation");
18096 return Lower256IntArith(Op, DAG);
18099 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18100 assert(Op.getSimpleValueType().is256BitVector() &&
18101 Op.getSimpleValueType().isInteger() &&
18102 "Only handle AVX 256-bit vector integer operation");
18103 return Lower256IntArith(Op, DAG);
18106 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18107 SelectionDAG &DAG) {
18109 MVT VT = Op.getSimpleValueType();
18111 // Decompose 256-bit ops into smaller 128-bit ops.
18112 if (VT.is256BitVector() && !Subtarget->hasInt256())
18113 return Lower256IntArith(Op, DAG);
18115 SDValue A = Op.getOperand(0);
18116 SDValue B = Op.getOperand(1);
18118 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18119 if (VT == MVT::v4i32) {
18120 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18121 "Should not custom lower when pmuldq is available!");
18123 // Extract the odd parts.
18124 static const int UnpackMask[] = { 1, -1, 3, -1 };
18125 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18126 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18128 // Multiply the even parts.
18129 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18130 // Now multiply odd parts.
18131 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18133 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18134 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18136 // Merge the two vectors back together with a shuffle. This expands into 2
18138 static const int ShufMask[] = { 0, 4, 2, 6 };
18139 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18142 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18143 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18145 // Ahi = psrlqi(a, 32);
18146 // Bhi = psrlqi(b, 32);
18148 // AloBlo = pmuludq(a, b);
18149 // AloBhi = pmuludq(a, Bhi);
18150 // AhiBlo = pmuludq(Ahi, b);
18152 // AloBhi = psllqi(AloBhi, 32);
18153 // AhiBlo = psllqi(AhiBlo, 32);
18154 // return AloBlo + AloBhi + AhiBlo;
18156 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18157 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18159 // Bit cast to 32-bit vectors for MULUDQ
18160 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18161 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18162 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18163 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18164 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18165 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18167 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18168 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18169 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18171 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18172 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18174 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18175 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18178 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18179 assert(Subtarget->isTargetWin64() && "Unexpected target");
18180 EVT VT = Op.getValueType();
18181 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18182 "Unexpected return type for lowering");
18186 switch (Op->getOpcode()) {
18187 default: llvm_unreachable("Unexpected request for libcall!");
18188 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18189 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18190 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18191 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18192 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18193 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18197 SDValue InChain = DAG.getEntryNode();
18199 TargetLowering::ArgListTy Args;
18200 TargetLowering::ArgListEntry Entry;
18201 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18202 EVT ArgVT = Op->getOperand(i).getValueType();
18203 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18204 "Unexpected argument type for lowering");
18205 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18206 Entry.Node = StackPtr;
18207 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18209 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18210 Entry.Ty = PointerType::get(ArgTy,0);
18211 Entry.isSExt = false;
18212 Entry.isZExt = false;
18213 Args.push_back(Entry);
18216 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18219 TargetLowering::CallLoweringInfo CLI(DAG);
18220 CLI.setDebugLoc(dl).setChain(InChain)
18221 .setCallee(getLibcallCallingConv(LC),
18222 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18223 Callee, std::move(Args), 0)
18224 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18226 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18227 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18230 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18231 SelectionDAG &DAG) {
18232 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18233 EVT VT = Op0.getValueType();
18236 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18237 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18239 // PMULxD operations multiply each even value (starting at 0) of LHS with
18240 // the related value of RHS and produce a widen result.
18241 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18242 // => <2 x i64> <ae|cg>
18244 // In other word, to have all the results, we need to perform two PMULxD:
18245 // 1. one with the even values.
18246 // 2. one with the odd values.
18247 // To achieve #2, with need to place the odd values at an even position.
18249 // Place the odd value at an even position (basically, shift all values 1
18250 // step to the left):
18251 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18252 // <a|b|c|d> => <b|undef|d|undef>
18253 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18254 // <e|f|g|h> => <f|undef|h|undef>
18255 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18257 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18259 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18260 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18262 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18263 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18264 // => <2 x i64> <ae|cg>
18265 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18266 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18267 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18268 // => <2 x i64> <bf|dh>
18269 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18270 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18272 // Shuffle it back into the right order.
18273 SDValue Highs, Lows;
18274 if (VT == MVT::v8i32) {
18275 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18276 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18277 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18278 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18280 const int HighMask[] = {1, 5, 3, 7};
18281 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18282 const int LowMask[] = {0, 4, 2, 6};
18283 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18286 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18287 // unsigned multiply.
18288 if (IsSigned && !Subtarget->hasSSE41()) {
18290 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18291 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18292 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18293 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18294 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18296 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18297 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18300 // The first result of MUL_LOHI is actually the low value, followed by the
18302 SDValue Ops[] = {Lows, Highs};
18303 return DAG.getMergeValues(Ops, dl);
18306 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18307 const X86Subtarget *Subtarget) {
18308 MVT VT = Op.getSimpleValueType();
18310 SDValue R = Op.getOperand(0);
18311 SDValue Amt = Op.getOperand(1);
18313 // Optimize shl/srl/sra with constant shift amount.
18314 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18315 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18316 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18318 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18319 (Subtarget->hasInt256() &&
18320 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18321 (Subtarget->hasAVX512() &&
18322 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18323 if (Op.getOpcode() == ISD::SHL)
18324 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18326 if (Op.getOpcode() == ISD::SRL)
18327 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18329 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18330 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18334 if (VT == MVT::v16i8) {
18335 if (Op.getOpcode() == ISD::SHL) {
18336 // Make a large shift.
18337 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18338 MVT::v8i16, R, ShiftAmt,
18340 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18341 // Zero out the rightmost bits.
18342 SmallVector<SDValue, 16> V(16,
18343 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18345 return DAG.getNode(ISD::AND, dl, VT, SHL,
18346 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18348 if (Op.getOpcode() == ISD::SRL) {
18349 // Make a large shift.
18350 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18351 MVT::v8i16, R, ShiftAmt,
18353 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18354 // Zero out the leftmost bits.
18355 SmallVector<SDValue, 16> V(16,
18356 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18358 return DAG.getNode(ISD::AND, dl, VT, SRL,
18359 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18361 if (Op.getOpcode() == ISD::SRA) {
18362 if (ShiftAmt == 7) {
18363 // R s>> 7 === R s< 0
18364 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18365 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18368 // R s>> a === ((R u>> a) ^ m) - m
18369 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18370 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18372 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18373 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18374 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18377 llvm_unreachable("Unknown shift opcode.");
18380 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18381 if (Op.getOpcode() == ISD::SHL) {
18382 // Make a large shift.
18383 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18384 MVT::v16i16, R, ShiftAmt,
18386 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18387 // Zero out the rightmost bits.
18388 SmallVector<SDValue, 32> V(32,
18389 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18391 return DAG.getNode(ISD::AND, dl, VT, SHL,
18392 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18394 if (Op.getOpcode() == ISD::SRL) {
18395 // Make a large shift.
18396 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18397 MVT::v16i16, R, ShiftAmt,
18399 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18400 // Zero out the leftmost bits.
18401 SmallVector<SDValue, 32> V(32,
18402 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18404 return DAG.getNode(ISD::AND, dl, VT, SRL,
18405 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18407 if (Op.getOpcode() == ISD::SRA) {
18408 if (ShiftAmt == 7) {
18409 // R s>> 7 === R s< 0
18410 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18411 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18414 // R s>> a === ((R u>> a) ^ m) - m
18415 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18416 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18418 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18419 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18420 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18423 llvm_unreachable("Unknown shift opcode.");
18428 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18429 if (!Subtarget->is64Bit() &&
18430 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18431 Amt.getOpcode() == ISD::BITCAST &&
18432 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18433 Amt = Amt.getOperand(0);
18434 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18435 VT.getVectorNumElements();
18436 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18437 uint64_t ShiftAmt = 0;
18438 for (unsigned i = 0; i != Ratio; ++i) {
18439 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18443 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18445 // Check remaining shift amounts.
18446 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18447 uint64_t ShAmt = 0;
18448 for (unsigned j = 0; j != Ratio; ++j) {
18449 ConstantSDNode *C =
18450 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18454 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18456 if (ShAmt != ShiftAmt)
18459 switch (Op.getOpcode()) {
18461 llvm_unreachable("Unknown shift opcode!");
18463 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18466 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18469 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18477 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18478 const X86Subtarget* Subtarget) {
18479 MVT VT = Op.getSimpleValueType();
18481 SDValue R = Op.getOperand(0);
18482 SDValue Amt = Op.getOperand(1);
18484 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18485 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18486 (Subtarget->hasInt256() &&
18487 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18488 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18489 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18491 EVT EltVT = VT.getVectorElementType();
18493 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18494 // Check if this build_vector node is doing a splat.
18495 // If so, then set BaseShAmt equal to the splat value.
18496 BaseShAmt = BV->getSplatValue();
18497 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18498 BaseShAmt = SDValue();
18500 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18501 Amt = Amt.getOperand(0);
18503 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18504 if (SVN && SVN->isSplat()) {
18505 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18506 SDValue InVec = Amt.getOperand(0);
18507 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18508 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18509 "Unexpected shuffle index found!");
18510 BaseShAmt = InVec.getOperand(SplatIdx);
18511 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18512 if (ConstantSDNode *C =
18513 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18514 if (C->getZExtValue() == SplatIdx)
18515 BaseShAmt = InVec.getOperand(1);
18520 // Avoid introducing an extract element from a shuffle.
18521 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18522 DAG.getIntPtrConstant(SplatIdx));
18526 if (BaseShAmt.getNode()) {
18527 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18528 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18529 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18530 else if (EltVT.bitsLT(MVT::i32))
18531 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18533 switch (Op.getOpcode()) {
18535 llvm_unreachable("Unknown shift opcode!");
18537 switch (VT.SimpleTy) {
18538 default: return SDValue();
18547 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18550 switch (VT.SimpleTy) {
18551 default: return SDValue();
18558 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18561 switch (VT.SimpleTy) {
18562 default: return SDValue();
18571 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18577 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18578 if (!Subtarget->is64Bit() &&
18579 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18580 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18581 Amt.getOpcode() == ISD::BITCAST &&
18582 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18583 Amt = Amt.getOperand(0);
18584 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18585 VT.getVectorNumElements();
18586 std::vector<SDValue> Vals(Ratio);
18587 for (unsigned i = 0; i != Ratio; ++i)
18588 Vals[i] = Amt.getOperand(i);
18589 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18590 for (unsigned j = 0; j != Ratio; ++j)
18591 if (Vals[j] != Amt.getOperand(i + j))
18594 switch (Op.getOpcode()) {
18596 llvm_unreachable("Unknown shift opcode!");
18598 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18600 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18602 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18609 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18610 SelectionDAG &DAG) {
18611 MVT VT = Op.getSimpleValueType();
18613 SDValue R = Op.getOperand(0);
18614 SDValue Amt = Op.getOperand(1);
18617 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18618 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18620 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18624 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18628 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18630 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18631 if (Subtarget->hasInt256()) {
18632 if (Op.getOpcode() == ISD::SRL &&
18633 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18634 VT == MVT::v4i64 || VT == MVT::v8i32))
18636 if (Op.getOpcode() == ISD::SHL &&
18637 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18638 VT == MVT::v4i64 || VT == MVT::v8i32))
18640 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18644 // If possible, lower this packed shift into a vector multiply instead of
18645 // expanding it into a sequence of scalar shifts.
18646 // Do this only if the vector shift count is a constant build_vector.
18647 if (Op.getOpcode() == ISD::SHL &&
18648 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18649 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18650 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18651 SmallVector<SDValue, 8> Elts;
18652 EVT SVT = VT.getScalarType();
18653 unsigned SVTBits = SVT.getSizeInBits();
18654 const APInt &One = APInt(SVTBits, 1);
18655 unsigned NumElems = VT.getVectorNumElements();
18657 for (unsigned i=0; i !=NumElems; ++i) {
18658 SDValue Op = Amt->getOperand(i);
18659 if (Op->getOpcode() == ISD::UNDEF) {
18660 Elts.push_back(Op);
18664 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18665 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18666 uint64_t ShAmt = C.getZExtValue();
18667 if (ShAmt >= SVTBits) {
18668 Elts.push_back(DAG.getUNDEF(SVT));
18671 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18673 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18674 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18677 // Lower SHL with variable shift amount.
18678 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18679 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18681 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18682 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18683 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18684 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18687 // If possible, lower this shift as a sequence of two shifts by
18688 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18690 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18692 // Could be rewritten as:
18693 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18695 // The advantage is that the two shifts from the example would be
18696 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18697 // the vector shift into four scalar shifts plus four pairs of vector
18699 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18700 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18701 unsigned TargetOpcode = X86ISD::MOVSS;
18702 bool CanBeSimplified;
18703 // The splat value for the first packed shift (the 'X' from the example).
18704 SDValue Amt1 = Amt->getOperand(0);
18705 // The splat value for the second packed shift (the 'Y' from the example).
18706 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18707 Amt->getOperand(2);
18709 // See if it is possible to replace this node with a sequence of
18710 // two shifts followed by a MOVSS/MOVSD
18711 if (VT == MVT::v4i32) {
18712 // Check if it is legal to use a MOVSS.
18713 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18714 Amt2 == Amt->getOperand(3);
18715 if (!CanBeSimplified) {
18716 // Otherwise, check if we can still simplify this node using a MOVSD.
18717 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18718 Amt->getOperand(2) == Amt->getOperand(3);
18719 TargetOpcode = X86ISD::MOVSD;
18720 Amt2 = Amt->getOperand(2);
18723 // Do similar checks for the case where the machine value type
18725 CanBeSimplified = Amt1 == Amt->getOperand(1);
18726 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18727 CanBeSimplified = Amt2 == Amt->getOperand(i);
18729 if (!CanBeSimplified) {
18730 TargetOpcode = X86ISD::MOVSD;
18731 CanBeSimplified = true;
18732 Amt2 = Amt->getOperand(4);
18733 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18734 CanBeSimplified = Amt1 == Amt->getOperand(i);
18735 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18736 CanBeSimplified = Amt2 == Amt->getOperand(j);
18740 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18741 isa<ConstantSDNode>(Amt2)) {
18742 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18743 EVT CastVT = MVT::v4i32;
18745 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18746 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18748 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18749 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18750 if (TargetOpcode == X86ISD::MOVSD)
18751 CastVT = MVT::v2i64;
18752 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18753 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18754 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18756 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18760 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18761 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18764 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18765 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18767 // Turn 'a' into a mask suitable for VSELECT
18768 SDValue VSelM = DAG.getConstant(0x80, VT);
18769 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18770 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18772 SDValue CM1 = DAG.getConstant(0x0f, VT);
18773 SDValue CM2 = DAG.getConstant(0x3f, VT);
18775 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18776 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18777 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18778 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18779 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18782 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18783 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18784 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18786 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18787 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18788 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18789 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18790 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18793 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18794 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18795 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18797 // return VSELECT(r, r+r, a);
18798 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18799 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18803 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18804 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18805 // solution better.
18806 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18807 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18809 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18810 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18811 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18812 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18813 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18816 // Decompose 256-bit shifts into smaller 128-bit shifts.
18817 if (VT.is256BitVector()) {
18818 unsigned NumElems = VT.getVectorNumElements();
18819 MVT EltVT = VT.getVectorElementType();
18820 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18822 // Extract the two vectors
18823 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18824 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18826 // Recreate the shift amount vectors
18827 SDValue Amt1, Amt2;
18828 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18829 // Constant shift amount
18830 SmallVector<SDValue, 4> Amt1Csts;
18831 SmallVector<SDValue, 4> Amt2Csts;
18832 for (unsigned i = 0; i != NumElems/2; ++i)
18833 Amt1Csts.push_back(Amt->getOperand(i));
18834 for (unsigned i = NumElems/2; i != NumElems; ++i)
18835 Amt2Csts.push_back(Amt->getOperand(i));
18837 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18838 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18840 // Variable shift amount
18841 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18842 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18845 // Issue new vector shifts for the smaller types
18846 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18847 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18849 // Concatenate the result back
18850 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18856 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18857 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18858 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18859 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18860 // has only one use.
18861 SDNode *N = Op.getNode();
18862 SDValue LHS = N->getOperand(0);
18863 SDValue RHS = N->getOperand(1);
18864 unsigned BaseOp = 0;
18867 switch (Op.getOpcode()) {
18868 default: llvm_unreachable("Unknown ovf instruction!");
18870 // A subtract of one will be selected as a INC. Note that INC doesn't
18871 // set CF, so we can't do this for UADDO.
18872 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18874 BaseOp = X86ISD::INC;
18875 Cond = X86::COND_O;
18878 BaseOp = X86ISD::ADD;
18879 Cond = X86::COND_O;
18882 BaseOp = X86ISD::ADD;
18883 Cond = X86::COND_B;
18886 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18887 // set CF, so we can't do this for USUBO.
18888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18890 BaseOp = X86ISD::DEC;
18891 Cond = X86::COND_O;
18894 BaseOp = X86ISD::SUB;
18895 Cond = X86::COND_O;
18898 BaseOp = X86ISD::SUB;
18899 Cond = X86::COND_B;
18902 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18903 Cond = X86::COND_O;
18905 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18906 if (N->getValueType(0) == MVT::i8) {
18907 BaseOp = X86ISD::UMUL8;
18908 Cond = X86::COND_O;
18911 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18913 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18916 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18917 DAG.getConstant(X86::COND_O, MVT::i32),
18918 SDValue(Sum.getNode(), 2));
18920 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18924 // Also sets EFLAGS.
18925 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18926 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18929 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18930 DAG.getConstant(Cond, MVT::i32),
18931 SDValue(Sum.getNode(), 1));
18933 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18936 // Sign extension of the low part of vector elements. This may be used either
18937 // when sign extend instructions are not available or if the vector element
18938 // sizes already match the sign-extended size. If the vector elements are in
18939 // their pre-extended size and sign extend instructions are available, that will
18940 // be handled by LowerSIGN_EXTEND.
18941 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18942 SelectionDAG &DAG) const {
18944 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18945 MVT VT = Op.getSimpleValueType();
18947 if (!Subtarget->hasSSE2() || !VT.isVector())
18950 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18951 ExtraVT.getScalarType().getSizeInBits();
18953 switch (VT.SimpleTy) {
18954 default: return SDValue();
18957 if (!Subtarget->hasFp256())
18959 if (!Subtarget->hasInt256()) {
18960 // needs to be split
18961 unsigned NumElems = VT.getVectorNumElements();
18963 // Extract the LHS vectors
18964 SDValue LHS = Op.getOperand(0);
18965 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18966 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18968 MVT EltVT = VT.getVectorElementType();
18969 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18971 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18972 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18973 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18975 SDValue Extra = DAG.getValueType(ExtraVT);
18977 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18978 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18985 SDValue Op0 = Op.getOperand(0);
18987 // This is a sign extension of some low part of vector elements without
18988 // changing the size of the vector elements themselves:
18989 // Shift-Left + Shift-Right-Algebraic.
18990 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18992 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18998 /// Returns true if the operand type is exactly twice the native width, and
18999 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19000 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19001 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19002 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
19003 const X86Subtarget &Subtarget =
19004 getTargetMachine().getSubtarget<X86Subtarget>();
19005 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19008 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19009 else if (OpWidth == 128)
19010 return Subtarget.hasCmpxchg16b();
19015 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19016 return needsCmpXchgNb(SI->getValueOperand()->getType());
19019 // Note: this turns large loads into lock cmpxchg8b/16b.
19020 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19021 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19022 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19023 return needsCmpXchgNb(PTy->getElementType());
19026 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19027 const X86Subtarget &Subtarget =
19028 getTargetMachine().getSubtarget<X86Subtarget>();
19029 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19030 const Type *MemType = AI->getType();
19032 // If the operand is too big, we must see if cmpxchg8/16b is available
19033 // and default to library calls otherwise.
19034 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19035 return needsCmpXchgNb(MemType);
19037 AtomicRMWInst::BinOp Op = AI->getOperation();
19040 llvm_unreachable("Unknown atomic operation");
19041 case AtomicRMWInst::Xchg:
19042 case AtomicRMWInst::Add:
19043 case AtomicRMWInst::Sub:
19044 // It's better to use xadd, xsub or xchg for these in all cases.
19046 case AtomicRMWInst::Or:
19047 case AtomicRMWInst::And:
19048 case AtomicRMWInst::Xor:
19049 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19050 // prefix to a normal instruction for these operations.
19051 return !AI->use_empty();
19052 case AtomicRMWInst::Nand:
19053 case AtomicRMWInst::Max:
19054 case AtomicRMWInst::Min:
19055 case AtomicRMWInst::UMax:
19056 case AtomicRMWInst::UMin:
19057 // These always require a non-trivial set of data operations on x86. We must
19058 // use a cmpxchg loop.
19063 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19064 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19065 // no-sse2). There isn't any reason to disable it if the target processor
19067 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19071 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19072 const X86Subtarget &Subtarget =
19073 getTargetMachine().getSubtarget<X86Subtarget>();
19074 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19075 const Type *MemType = AI->getType();
19076 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19077 // there is no benefit in turning such RMWs into loads, and it is actually
19078 // harmful as it introduces a mfence.
19079 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19082 auto Builder = IRBuilder<>(AI);
19083 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19084 auto SynchScope = AI->getSynchScope();
19085 // We must restrict the ordering to avoid generating loads with Release or
19086 // ReleaseAcquire orderings.
19087 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19088 auto Ptr = AI->getPointerOperand();
19090 // Before the load we need a fence. Here is an example lifted from
19091 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19094 // x.store(1, relaxed);
19095 // r1 = y.fetch_add(0, release);
19097 // y.fetch_add(42, acquire);
19098 // r2 = x.load(relaxed);
19099 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19100 // lowered to just a load without a fence. A mfence flushes the store buffer,
19101 // making the optimization clearly correct.
19102 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19103 // otherwise, we might be able to be more agressive on relaxed idempotent
19104 // rmw. In practice, they do not look useful, so we don't try to be
19105 // especially clever.
19106 if (SynchScope == SingleThread) {
19107 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19108 // the IR level, so we must wrap it in an intrinsic.
19110 } else if (hasMFENCE(Subtarget)) {
19111 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19112 Intrinsic::x86_sse2_mfence);
19113 Builder.CreateCall(MFence);
19115 // FIXME: it might make sense to use a locked operation here but on a
19116 // different cache-line to prevent cache-line bouncing. In practice it
19117 // is probably a small win, and x86 processors without mfence are rare
19118 // enough that we do not bother.
19122 // Finally we can emit the atomic load.
19123 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19124 AI->getType()->getPrimitiveSizeInBits());
19125 Loaded->setAtomic(Order, SynchScope);
19126 AI->replaceAllUsesWith(Loaded);
19127 AI->eraseFromParent();
19131 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19132 SelectionDAG &DAG) {
19134 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19135 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19136 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19137 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19139 // The only fence that needs an instruction is a sequentially-consistent
19140 // cross-thread fence.
19141 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19142 if (hasMFENCE(*Subtarget))
19143 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19145 SDValue Chain = Op.getOperand(0);
19146 SDValue Zero = DAG.getConstant(0, MVT::i32);
19148 DAG.getRegister(X86::ESP, MVT::i32), // Base
19149 DAG.getTargetConstant(1, MVT::i8), // Scale
19150 DAG.getRegister(0, MVT::i32), // Index
19151 DAG.getTargetConstant(0, MVT::i32), // Disp
19152 DAG.getRegister(0, MVT::i32), // Segment.
19156 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19157 return SDValue(Res, 0);
19160 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19161 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19164 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19165 SelectionDAG &DAG) {
19166 MVT T = Op.getSimpleValueType();
19170 switch(T.SimpleTy) {
19171 default: llvm_unreachable("Invalid value type!");
19172 case MVT::i8: Reg = X86::AL; size = 1; break;
19173 case MVT::i16: Reg = X86::AX; size = 2; break;
19174 case MVT::i32: Reg = X86::EAX; size = 4; break;
19176 assert(Subtarget->is64Bit() && "Node not type legal!");
19177 Reg = X86::RAX; size = 8;
19180 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19181 Op.getOperand(2), SDValue());
19182 SDValue Ops[] = { cpIn.getValue(0),
19185 DAG.getTargetConstant(size, MVT::i8),
19186 cpIn.getValue(1) };
19187 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19188 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19189 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19193 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19194 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19195 MVT::i32, cpOut.getValue(2));
19196 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19197 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19199 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19200 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19201 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19205 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19206 SelectionDAG &DAG) {
19207 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19208 MVT DstVT = Op.getSimpleValueType();
19210 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19211 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19212 if (DstVT != MVT::f64)
19213 // This conversion needs to be expanded.
19216 SDValue InVec = Op->getOperand(0);
19218 unsigned NumElts = SrcVT.getVectorNumElements();
19219 EVT SVT = SrcVT.getVectorElementType();
19221 // Widen the vector in input in the case of MVT::v2i32.
19222 // Example: from MVT::v2i32 to MVT::v4i32.
19223 SmallVector<SDValue, 16> Elts;
19224 for (unsigned i = 0, e = NumElts; i != e; ++i)
19225 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19226 DAG.getIntPtrConstant(i)));
19228 // Explicitly mark the extra elements as Undef.
19229 SDValue Undef = DAG.getUNDEF(SVT);
19230 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19231 Elts.push_back(Undef);
19233 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19234 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19235 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19237 DAG.getIntPtrConstant(0));
19240 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19241 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19242 assert((DstVT == MVT::i64 ||
19243 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19244 "Unexpected custom BITCAST");
19245 // i64 <=> MMX conversions are Legal.
19246 if (SrcVT==MVT::i64 && DstVT.isVector())
19248 if (DstVT==MVT::i64 && SrcVT.isVector())
19250 // MMX <=> MMX conversions are Legal.
19251 if (SrcVT.isVector() && DstVT.isVector())
19253 // All other conversions need to be expanded.
19257 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19258 SelectionDAG &DAG) {
19259 SDNode *Node = Op.getNode();
19262 Op = Op.getOperand(0);
19263 EVT VT = Op.getValueType();
19264 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19265 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19267 unsigned NumElts = VT.getVectorNumElements();
19268 EVT EltVT = VT.getVectorElementType();
19269 unsigned Len = EltVT.getSizeInBits();
19271 // This is the vectorized version of the "best" algorithm from
19272 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19273 // with a minor tweak to use a series of adds + shifts instead of vector
19274 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19276 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19277 // v8i32 => Always profitable
19279 // FIXME: There a couple of possible improvements:
19281 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19282 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19284 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19285 "CTPOP not implemented for this vector element type.");
19287 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19288 // extra legalization.
19289 bool NeedsBitcast = EltVT == MVT::i32;
19290 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19292 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19293 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19294 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19296 // v = v - ((v >> 1) & 0x55555555...)
19297 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19298 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19299 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19301 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19303 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19304 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19306 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19308 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19309 if (VT != And.getValueType())
19310 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19311 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19313 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19314 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19315 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19316 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19317 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19319 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19320 if (NeedsBitcast) {
19321 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19322 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19323 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19326 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19327 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19328 if (VT != AndRHS.getValueType()) {
19329 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19330 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19332 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19334 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19335 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19336 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19337 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19338 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19340 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19341 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19342 if (NeedsBitcast) {
19343 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19344 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19346 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19347 if (VT != And.getValueType())
19348 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19350 // The algorithm mentioned above uses:
19351 // v = (v * 0x01010101...) >> (Len - 8)
19353 // Change it to use vector adds + vector shifts which yield faster results on
19354 // Haswell than using vector integer multiplication.
19356 // For i32 elements:
19357 // v = v + (v >> 8)
19358 // v = v + (v >> 16)
19360 // For i64 elements:
19361 // v = v + (v >> 8)
19362 // v = v + (v >> 16)
19363 // v = v + (v >> 32)
19366 SmallVector<SDValue, 8> Csts;
19367 for (unsigned i = 8; i <= Len/2; i *= 2) {
19368 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19369 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19370 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19371 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19375 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19376 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19377 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19378 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19379 if (NeedsBitcast) {
19380 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19381 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19383 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19384 if (VT != And.getValueType())
19385 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19390 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19391 SDNode *Node = Op.getNode();
19393 EVT T = Node->getValueType(0);
19394 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19395 DAG.getConstant(0, T), Node->getOperand(2));
19396 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19397 cast<AtomicSDNode>(Node)->getMemoryVT(),
19398 Node->getOperand(0),
19399 Node->getOperand(1), negOp,
19400 cast<AtomicSDNode>(Node)->getMemOperand(),
19401 cast<AtomicSDNode>(Node)->getOrdering(),
19402 cast<AtomicSDNode>(Node)->getSynchScope());
19405 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19406 SDNode *Node = Op.getNode();
19408 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19410 // Convert seq_cst store -> xchg
19411 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19412 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19413 // (The only way to get a 16-byte store is cmpxchg16b)
19414 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19415 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19416 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19417 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19418 cast<AtomicSDNode>(Node)->getMemoryVT(),
19419 Node->getOperand(0),
19420 Node->getOperand(1), Node->getOperand(2),
19421 cast<AtomicSDNode>(Node)->getMemOperand(),
19422 cast<AtomicSDNode>(Node)->getOrdering(),
19423 cast<AtomicSDNode>(Node)->getSynchScope());
19424 return Swap.getValue(1);
19426 // Other atomic stores have a simple pattern.
19430 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19431 EVT VT = Op.getNode()->getSimpleValueType(0);
19433 // Let legalize expand this if it isn't a legal type yet.
19434 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19437 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19440 bool ExtraOp = false;
19441 switch (Op.getOpcode()) {
19442 default: llvm_unreachable("Invalid code");
19443 case ISD::ADDC: Opc = X86ISD::ADD; break;
19444 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19445 case ISD::SUBC: Opc = X86ISD::SUB; break;
19446 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19450 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19452 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19453 Op.getOperand(1), Op.getOperand(2));
19456 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19457 SelectionDAG &DAG) {
19458 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19460 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19461 // which returns the values as { float, float } (in XMM0) or
19462 // { double, double } (which is returned in XMM0, XMM1).
19464 SDValue Arg = Op.getOperand(0);
19465 EVT ArgVT = Arg.getValueType();
19466 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19468 TargetLowering::ArgListTy Args;
19469 TargetLowering::ArgListEntry Entry;
19473 Entry.isSExt = false;
19474 Entry.isZExt = false;
19475 Args.push_back(Entry);
19477 bool isF64 = ArgVT == MVT::f64;
19478 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19479 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19480 // the results are returned via SRet in memory.
19481 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19483 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19485 Type *RetTy = isF64
19486 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19487 : (Type*)VectorType::get(ArgTy, 4);
19489 TargetLowering::CallLoweringInfo CLI(DAG);
19490 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19491 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19493 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19496 // Returned in xmm0 and xmm1.
19497 return CallResult.first;
19499 // Returned in bits 0:31 and 32:64 xmm0.
19500 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19501 CallResult.first, DAG.getIntPtrConstant(0));
19502 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19503 CallResult.first, DAG.getIntPtrConstant(1));
19504 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19505 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19508 /// LowerOperation - Provide custom lowering hooks for some operations.
19510 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19511 switch (Op.getOpcode()) {
19512 default: llvm_unreachable("Should not custom lower this!");
19513 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19514 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19515 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19516 return LowerCMP_SWAP(Op, Subtarget, DAG);
19517 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19518 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19519 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19520 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19521 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19522 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19523 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19524 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19525 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19526 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19527 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19528 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19529 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19530 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19531 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19532 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19533 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19534 case ISD::SHL_PARTS:
19535 case ISD::SRA_PARTS:
19536 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19537 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19538 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19539 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19540 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19541 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19542 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19543 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19544 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19545 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19546 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19548 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19549 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19550 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19551 case ISD::SETCC: return LowerSETCC(Op, DAG);
19552 case ISD::SELECT: return LowerSELECT(Op, DAG);
19553 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19554 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19555 case ISD::VASTART: return LowerVASTART(Op, DAG);
19556 case ISD::VAARG: return LowerVAARG(Op, DAG);
19557 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19558 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19559 case ISD::INTRINSIC_VOID:
19560 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19561 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19562 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19563 case ISD::FRAME_TO_ARGS_OFFSET:
19564 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19565 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19566 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19567 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19568 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19569 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19570 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19571 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19572 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19573 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19574 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19575 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19576 case ISD::UMUL_LOHI:
19577 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19580 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19586 case ISD::UMULO: return LowerXALUO(Op, DAG);
19587 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19588 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19592 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19593 case ISD::ADD: return LowerADD(Op, DAG);
19594 case ISD::SUB: return LowerSUB(Op, DAG);
19595 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19599 /// ReplaceNodeResults - Replace a node with an illegal result type
19600 /// with a new node built out of custom code.
19601 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19602 SmallVectorImpl<SDValue>&Results,
19603 SelectionDAG &DAG) const {
19605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19606 switch (N->getOpcode()) {
19608 llvm_unreachable("Do not know how to custom type legalize this operation!");
19609 case ISD::SIGN_EXTEND_INREG:
19614 // We don't want to expand or promote these.
19621 case ISD::UDIVREM: {
19622 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19623 Results.push_back(V);
19626 case ISD::FP_TO_SINT:
19627 case ISD::FP_TO_UINT: {
19628 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19630 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19633 std::pair<SDValue,SDValue> Vals =
19634 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19635 SDValue FIST = Vals.first, StackSlot = Vals.second;
19636 if (FIST.getNode()) {
19637 EVT VT = N->getValueType(0);
19638 // Return a load from the stack slot.
19639 if (StackSlot.getNode())
19640 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19641 MachinePointerInfo(),
19642 false, false, false, 0));
19644 Results.push_back(FIST);
19648 case ISD::UINT_TO_FP: {
19649 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19650 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19651 N->getValueType(0) != MVT::v2f32)
19653 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19655 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19657 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19658 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19659 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19660 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19661 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19662 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19665 case ISD::FP_ROUND: {
19666 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19668 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19669 Results.push_back(V);
19672 case ISD::INTRINSIC_W_CHAIN: {
19673 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19675 default : llvm_unreachable("Do not know how to custom type "
19676 "legalize this intrinsic operation!");
19677 case Intrinsic::x86_rdtsc:
19678 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19680 case Intrinsic::x86_rdtscp:
19681 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19683 case Intrinsic::x86_rdpmc:
19684 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19687 case ISD::READCYCLECOUNTER: {
19688 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19691 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19692 EVT T = N->getValueType(0);
19693 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19694 bool Regs64bit = T == MVT::i128;
19695 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19696 SDValue cpInL, cpInH;
19697 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19698 DAG.getConstant(0, HalfT));
19699 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19700 DAG.getConstant(1, HalfT));
19701 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19702 Regs64bit ? X86::RAX : X86::EAX,
19704 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19705 Regs64bit ? X86::RDX : X86::EDX,
19706 cpInH, cpInL.getValue(1));
19707 SDValue swapInL, swapInH;
19708 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19709 DAG.getConstant(0, HalfT));
19710 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19711 DAG.getConstant(1, HalfT));
19712 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19713 Regs64bit ? X86::RBX : X86::EBX,
19714 swapInL, cpInH.getValue(1));
19715 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19716 Regs64bit ? X86::RCX : X86::ECX,
19717 swapInH, swapInL.getValue(1));
19718 SDValue Ops[] = { swapInH.getValue(0),
19720 swapInH.getValue(1) };
19721 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19722 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19723 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19724 X86ISD::LCMPXCHG8_DAG;
19725 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19726 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19727 Regs64bit ? X86::RAX : X86::EAX,
19728 HalfT, Result.getValue(1));
19729 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19730 Regs64bit ? X86::RDX : X86::EDX,
19731 HalfT, cpOutL.getValue(2));
19732 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19734 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19735 MVT::i32, cpOutH.getValue(2));
19737 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19738 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19739 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19741 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19742 Results.push_back(Success);
19743 Results.push_back(EFLAGS.getValue(1));
19746 case ISD::ATOMIC_SWAP:
19747 case ISD::ATOMIC_LOAD_ADD:
19748 case ISD::ATOMIC_LOAD_SUB:
19749 case ISD::ATOMIC_LOAD_AND:
19750 case ISD::ATOMIC_LOAD_OR:
19751 case ISD::ATOMIC_LOAD_XOR:
19752 case ISD::ATOMIC_LOAD_NAND:
19753 case ISD::ATOMIC_LOAD_MIN:
19754 case ISD::ATOMIC_LOAD_MAX:
19755 case ISD::ATOMIC_LOAD_UMIN:
19756 case ISD::ATOMIC_LOAD_UMAX:
19757 case ISD::ATOMIC_LOAD: {
19758 // Delegate to generic TypeLegalization. Situations we can really handle
19759 // should have already been dealt with by AtomicExpandPass.cpp.
19762 case ISD::BITCAST: {
19763 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19764 EVT DstVT = N->getValueType(0);
19765 EVT SrcVT = N->getOperand(0)->getValueType(0);
19767 if (SrcVT != MVT::f64 ||
19768 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19771 unsigned NumElts = DstVT.getVectorNumElements();
19772 EVT SVT = DstVT.getVectorElementType();
19773 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19774 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19775 MVT::v2f64, N->getOperand(0));
19776 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19778 if (ExperimentalVectorWideningLegalization) {
19779 // If we are legalizing vectors by widening, we already have the desired
19780 // legal vector type, just return it.
19781 Results.push_back(ToVecInt);
19785 SmallVector<SDValue, 8> Elts;
19786 for (unsigned i = 0, e = NumElts; i != e; ++i)
19787 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19788 ToVecInt, DAG.getIntPtrConstant(i)));
19790 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19795 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19797 default: return nullptr;
19798 case X86ISD::BSF: return "X86ISD::BSF";
19799 case X86ISD::BSR: return "X86ISD::BSR";
19800 case X86ISD::SHLD: return "X86ISD::SHLD";
19801 case X86ISD::SHRD: return "X86ISD::SHRD";
19802 case X86ISD::FAND: return "X86ISD::FAND";
19803 case X86ISD::FANDN: return "X86ISD::FANDN";
19804 case X86ISD::FOR: return "X86ISD::FOR";
19805 case X86ISD::FXOR: return "X86ISD::FXOR";
19806 case X86ISD::FSRL: return "X86ISD::FSRL";
19807 case X86ISD::FILD: return "X86ISD::FILD";
19808 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19809 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19810 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19811 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19812 case X86ISD::FLD: return "X86ISD::FLD";
19813 case X86ISD::FST: return "X86ISD::FST";
19814 case X86ISD::CALL: return "X86ISD::CALL";
19815 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19816 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19817 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19818 case X86ISD::BT: return "X86ISD::BT";
19819 case X86ISD::CMP: return "X86ISD::CMP";
19820 case X86ISD::COMI: return "X86ISD::COMI";
19821 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19822 case X86ISD::CMPM: return "X86ISD::CMPM";
19823 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19824 case X86ISD::SETCC: return "X86ISD::SETCC";
19825 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19826 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19827 case X86ISD::CMOV: return "X86ISD::CMOV";
19828 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19829 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19830 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19831 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19832 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19833 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19834 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19835 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19836 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19837 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19838 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19839 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19840 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19841 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19842 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19843 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19844 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19845 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19846 case X86ISD::HADD: return "X86ISD::HADD";
19847 case X86ISD::HSUB: return "X86ISD::HSUB";
19848 case X86ISD::FHADD: return "X86ISD::FHADD";
19849 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19850 case X86ISD::UMAX: return "X86ISD::UMAX";
19851 case X86ISD::UMIN: return "X86ISD::UMIN";
19852 case X86ISD::SMAX: return "X86ISD::SMAX";
19853 case X86ISD::SMIN: return "X86ISD::SMIN";
19854 case X86ISD::FMAX: return "X86ISD::FMAX";
19855 case X86ISD::FMIN: return "X86ISD::FMIN";
19856 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19857 case X86ISD::FMINC: return "X86ISD::FMINC";
19858 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19859 case X86ISD::FRCP: return "X86ISD::FRCP";
19860 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19861 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19862 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19863 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19864 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19865 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19866 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19867 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19868 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19869 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19870 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19871 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19872 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19873 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19874 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19875 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19876 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19877 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19878 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19879 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19880 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19881 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19882 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19883 case X86ISD::VSHL: return "X86ISD::VSHL";
19884 case X86ISD::VSRL: return "X86ISD::VSRL";
19885 case X86ISD::VSRA: return "X86ISD::VSRA";
19886 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19887 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19888 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19889 case X86ISD::CMPP: return "X86ISD::CMPP";
19890 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19891 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19892 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19893 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19894 case X86ISD::ADD: return "X86ISD::ADD";
19895 case X86ISD::SUB: return "X86ISD::SUB";
19896 case X86ISD::ADC: return "X86ISD::ADC";
19897 case X86ISD::SBB: return "X86ISD::SBB";
19898 case X86ISD::SMUL: return "X86ISD::SMUL";
19899 case X86ISD::UMUL: return "X86ISD::UMUL";
19900 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19901 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19902 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19903 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19904 case X86ISD::INC: return "X86ISD::INC";
19905 case X86ISD::DEC: return "X86ISD::DEC";
19906 case X86ISD::OR: return "X86ISD::OR";
19907 case X86ISD::XOR: return "X86ISD::XOR";
19908 case X86ISD::AND: return "X86ISD::AND";
19909 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19910 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19911 case X86ISD::PTEST: return "X86ISD::PTEST";
19912 case X86ISD::TESTP: return "X86ISD::TESTP";
19913 case X86ISD::TESTM: return "X86ISD::TESTM";
19914 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19915 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19916 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19917 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19918 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19919 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19920 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19921 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19922 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19923 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19924 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19925 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19926 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19927 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19928 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19929 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19930 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19931 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19932 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19933 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19934 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19935 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19936 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19937 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19938 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19939 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19940 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19941 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19942 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19943 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19944 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19945 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19946 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19947 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19948 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19949 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19950 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19951 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19952 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19953 case X86ISD::SAHF: return "X86ISD::SAHF";
19954 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19955 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19956 case X86ISD::FMADD: return "X86ISD::FMADD";
19957 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19958 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19959 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19960 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19961 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19962 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19963 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19964 case X86ISD::XTEST: return "X86ISD::XTEST";
19965 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19966 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19967 case X86ISD::SELECT: return "X86ISD::SELECT";
19971 // isLegalAddressingMode - Return true if the addressing mode represented
19972 // by AM is legal for this target, for a load/store of the specified type.
19973 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19975 // X86 supports extremely general addressing modes.
19976 CodeModel::Model M = getTargetMachine().getCodeModel();
19977 Reloc::Model R = getTargetMachine().getRelocationModel();
19979 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19980 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19985 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19987 // If a reference to this global requires an extra load, we can't fold it.
19988 if (isGlobalStubReference(GVFlags))
19991 // If BaseGV requires a register for the PIC base, we cannot also have a
19992 // BaseReg specified.
19993 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19996 // If lower 4G is not available, then we must use rip-relative addressing.
19997 if ((M != CodeModel::Small || R != Reloc::Static) &&
19998 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20002 switch (AM.Scale) {
20008 // These scales always work.
20013 // These scales are formed with basereg+scalereg. Only accept if there is
20018 default: // Other stuff never works.
20025 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20026 unsigned Bits = Ty->getScalarSizeInBits();
20028 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20029 // particularly cheaper than those without.
20033 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20034 // variable shifts just as cheap as scalar ones.
20035 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20038 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20039 // fully general vector.
20043 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20044 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20046 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20047 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20048 return NumBits1 > NumBits2;
20051 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20052 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20055 if (!isTypeLegal(EVT::getEVT(Ty1)))
20058 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20060 // Assuming the caller doesn't have a zeroext or signext return parameter,
20061 // truncation all the way down to i1 is valid.
20065 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20066 return isInt<32>(Imm);
20069 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20070 // Can also use sub to handle negated immediates.
20071 return isInt<32>(Imm);
20074 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20075 if (!VT1.isInteger() || !VT2.isInteger())
20077 unsigned NumBits1 = VT1.getSizeInBits();
20078 unsigned NumBits2 = VT2.getSizeInBits();
20079 return NumBits1 > NumBits2;
20082 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20083 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20084 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20087 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20088 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20089 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20092 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20093 EVT VT1 = Val.getValueType();
20094 if (isZExtFree(VT1, VT2))
20097 if (Val.getOpcode() != ISD::LOAD)
20100 if (!VT1.isSimple() || !VT1.isInteger() ||
20101 !VT2.isSimple() || !VT2.isInteger())
20104 switch (VT1.getSimpleVT().SimpleTy) {
20109 // X86 has 8, 16, and 32-bit zero-extending loads.
20117 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20118 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20121 VT = VT.getScalarType();
20123 if (!VT.isSimple())
20126 switch (VT.getSimpleVT().SimpleTy) {
20137 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20138 // i16 instructions are longer (0x66 prefix) and potentially slower.
20139 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20142 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20143 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20144 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20145 /// are assumed to be legal.
20147 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20149 if (!VT.isSimple())
20152 MVT SVT = VT.getSimpleVT();
20154 // Very little shuffling can be done for 64-bit vectors right now.
20155 if (VT.getSizeInBits() == 64)
20158 // This is an experimental legality test that is tailored to match the
20159 // legality test of the experimental lowering more closely. They are gated
20160 // separately to ease testing of performance differences.
20161 if (ExperimentalVectorShuffleLegality)
20162 // We only care that the types being shuffled are legal. The lowering can
20163 // handle any possible shuffle mask that results.
20164 return isTypeLegal(SVT);
20166 // If this is a single-input shuffle with no 128 bit lane crossings we can
20167 // lower it into pshufb.
20168 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20169 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20170 bool isLegal = true;
20171 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20172 if (M[I] >= (int)SVT.getVectorNumElements() ||
20173 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20182 // FIXME: blends, shifts.
20183 return (SVT.getVectorNumElements() == 2 ||
20184 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20185 isMOVLMask(M, SVT) ||
20186 isCommutedMOVLMask(M, SVT) ||
20187 isMOVHLPSMask(M, SVT) ||
20188 isSHUFPMask(M, SVT) ||
20189 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20190 isPSHUFDMask(M, SVT) ||
20191 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20192 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20193 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20194 isPALIGNRMask(M, SVT, Subtarget) ||
20195 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20196 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20197 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20198 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20199 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20200 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20204 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20206 if (!VT.isSimple())
20209 MVT SVT = VT.getSimpleVT();
20211 // This is an experimental legality test that is tailored to match the
20212 // legality test of the experimental lowering more closely. They are gated
20213 // separately to ease testing of performance differences.
20214 if (ExperimentalVectorShuffleLegality)
20215 // The new vector shuffle lowering is very good at managing zero-inputs.
20216 return isShuffleMaskLegal(Mask, VT);
20218 unsigned NumElts = SVT.getVectorNumElements();
20219 // FIXME: This collection of masks seems suspect.
20222 if (NumElts == 4 && SVT.is128BitVector()) {
20223 return (isMOVLMask(Mask, SVT) ||
20224 isCommutedMOVLMask(Mask, SVT, true) ||
20225 isSHUFPMask(Mask, SVT) ||
20226 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20227 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20228 Subtarget->hasInt256()));
20233 //===----------------------------------------------------------------------===//
20234 // X86 Scheduler Hooks
20235 //===----------------------------------------------------------------------===//
20237 /// Utility function to emit xbegin specifying the start of an RTM region.
20238 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20239 const TargetInstrInfo *TII) {
20240 DebugLoc DL = MI->getDebugLoc();
20242 const BasicBlock *BB = MBB->getBasicBlock();
20243 MachineFunction::iterator I = MBB;
20246 // For the v = xbegin(), we generate
20257 MachineBasicBlock *thisMBB = MBB;
20258 MachineFunction *MF = MBB->getParent();
20259 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20260 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20261 MF->insert(I, mainMBB);
20262 MF->insert(I, sinkMBB);
20264 // Transfer the remainder of BB and its successor edges to sinkMBB.
20265 sinkMBB->splice(sinkMBB->begin(), MBB,
20266 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20267 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20271 // # fallthrough to mainMBB
20272 // # abortion to sinkMBB
20273 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20274 thisMBB->addSuccessor(mainMBB);
20275 thisMBB->addSuccessor(sinkMBB);
20279 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20280 mainMBB->addSuccessor(sinkMBB);
20283 // EAX is live into the sinkMBB
20284 sinkMBB->addLiveIn(X86::EAX);
20285 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20286 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20289 MI->eraseFromParent();
20293 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20294 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20295 // in the .td file.
20296 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20297 const TargetInstrInfo *TII) {
20299 switch (MI->getOpcode()) {
20300 default: llvm_unreachable("illegal opcode!");
20301 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20302 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20303 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20304 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20305 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20306 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20307 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20308 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20311 DebugLoc dl = MI->getDebugLoc();
20312 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20314 unsigned NumArgs = MI->getNumOperands();
20315 for (unsigned i = 1; i < NumArgs; ++i) {
20316 MachineOperand &Op = MI->getOperand(i);
20317 if (!(Op.isReg() && Op.isImplicit()))
20318 MIB.addOperand(Op);
20320 if (MI->hasOneMemOperand())
20321 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20323 BuildMI(*BB, MI, dl,
20324 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20325 .addReg(X86::XMM0);
20327 MI->eraseFromParent();
20331 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20332 // defs in an instruction pattern
20333 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20334 const TargetInstrInfo *TII) {
20336 switch (MI->getOpcode()) {
20337 default: llvm_unreachable("illegal opcode!");
20338 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20339 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20340 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20341 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20342 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20343 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20344 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20345 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20348 DebugLoc dl = MI->getDebugLoc();
20349 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20351 unsigned NumArgs = MI->getNumOperands(); // remove the results
20352 for (unsigned i = 1; i < NumArgs; ++i) {
20353 MachineOperand &Op = MI->getOperand(i);
20354 if (!(Op.isReg() && Op.isImplicit()))
20355 MIB.addOperand(Op);
20357 if (MI->hasOneMemOperand())
20358 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20360 BuildMI(*BB, MI, dl,
20361 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20364 MI->eraseFromParent();
20368 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20369 const TargetInstrInfo *TII,
20370 const X86Subtarget* Subtarget) {
20371 DebugLoc dl = MI->getDebugLoc();
20373 // Address into RAX/EAX, other two args into ECX, EDX.
20374 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20375 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20376 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20377 for (int i = 0; i < X86::AddrNumOperands; ++i)
20378 MIB.addOperand(MI->getOperand(i));
20380 unsigned ValOps = X86::AddrNumOperands;
20381 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20382 .addReg(MI->getOperand(ValOps).getReg());
20383 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20384 .addReg(MI->getOperand(ValOps+1).getReg());
20386 // The instruction doesn't actually take any operands though.
20387 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20389 MI->eraseFromParent(); // The pseudo is gone now.
20393 MachineBasicBlock *
20394 X86TargetLowering::EmitVAARG64WithCustomInserter(
20396 MachineBasicBlock *MBB) const {
20397 // Emit va_arg instruction on X86-64.
20399 // Operands to this pseudo-instruction:
20400 // 0 ) Output : destination address (reg)
20401 // 1-5) Input : va_list address (addr, i64mem)
20402 // 6 ) ArgSize : Size (in bytes) of vararg type
20403 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20404 // 8 ) Align : Alignment of type
20405 // 9 ) EFLAGS (implicit-def)
20407 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20408 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20410 unsigned DestReg = MI->getOperand(0).getReg();
20411 MachineOperand &Base = MI->getOperand(1);
20412 MachineOperand &Scale = MI->getOperand(2);
20413 MachineOperand &Index = MI->getOperand(3);
20414 MachineOperand &Disp = MI->getOperand(4);
20415 MachineOperand &Segment = MI->getOperand(5);
20416 unsigned ArgSize = MI->getOperand(6).getImm();
20417 unsigned ArgMode = MI->getOperand(7).getImm();
20418 unsigned Align = MI->getOperand(8).getImm();
20420 // Memory Reference
20421 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20422 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20423 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20425 // Machine Information
20426 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20427 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20428 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20429 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20430 DebugLoc DL = MI->getDebugLoc();
20432 // struct va_list {
20435 // i64 overflow_area (address)
20436 // i64 reg_save_area (address)
20438 // sizeof(va_list) = 24
20439 // alignment(va_list) = 8
20441 unsigned TotalNumIntRegs = 6;
20442 unsigned TotalNumXMMRegs = 8;
20443 bool UseGPOffset = (ArgMode == 1);
20444 bool UseFPOffset = (ArgMode == 2);
20445 unsigned MaxOffset = TotalNumIntRegs * 8 +
20446 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20448 /* Align ArgSize to a multiple of 8 */
20449 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20450 bool NeedsAlign = (Align > 8);
20452 MachineBasicBlock *thisMBB = MBB;
20453 MachineBasicBlock *overflowMBB;
20454 MachineBasicBlock *offsetMBB;
20455 MachineBasicBlock *endMBB;
20457 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20458 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20459 unsigned OffsetReg = 0;
20461 if (!UseGPOffset && !UseFPOffset) {
20462 // If we only pull from the overflow region, we don't create a branch.
20463 // We don't need to alter control flow.
20464 OffsetDestReg = 0; // unused
20465 OverflowDestReg = DestReg;
20467 offsetMBB = nullptr;
20468 overflowMBB = thisMBB;
20471 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20472 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20473 // If not, pull from overflow_area. (branch to overflowMBB)
20478 // offsetMBB overflowMBB
20483 // Registers for the PHI in endMBB
20484 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20485 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20487 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20488 MachineFunction *MF = MBB->getParent();
20489 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20490 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20491 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20493 MachineFunction::iterator MBBIter = MBB;
20496 // Insert the new basic blocks
20497 MF->insert(MBBIter, offsetMBB);
20498 MF->insert(MBBIter, overflowMBB);
20499 MF->insert(MBBIter, endMBB);
20501 // Transfer the remainder of MBB and its successor edges to endMBB.
20502 endMBB->splice(endMBB->begin(), thisMBB,
20503 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20504 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20506 // Make offsetMBB and overflowMBB successors of thisMBB
20507 thisMBB->addSuccessor(offsetMBB);
20508 thisMBB->addSuccessor(overflowMBB);
20510 // endMBB is a successor of both offsetMBB and overflowMBB
20511 offsetMBB->addSuccessor(endMBB);
20512 overflowMBB->addSuccessor(endMBB);
20514 // Load the offset value into a register
20515 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20516 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20520 .addDisp(Disp, UseFPOffset ? 4 : 0)
20521 .addOperand(Segment)
20522 .setMemRefs(MMOBegin, MMOEnd);
20524 // Check if there is enough room left to pull this argument.
20525 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20527 .addImm(MaxOffset + 8 - ArgSizeA8);
20529 // Branch to "overflowMBB" if offset >= max
20530 // Fall through to "offsetMBB" otherwise
20531 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20532 .addMBB(overflowMBB);
20535 // In offsetMBB, emit code to use the reg_save_area.
20537 assert(OffsetReg != 0);
20539 // Read the reg_save_area address.
20540 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20541 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20546 .addOperand(Segment)
20547 .setMemRefs(MMOBegin, MMOEnd);
20549 // Zero-extend the offset
20550 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20551 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20554 .addImm(X86::sub_32bit);
20556 // Add the offset to the reg_save_area to get the final address.
20557 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20558 .addReg(OffsetReg64)
20559 .addReg(RegSaveReg);
20561 // Compute the offset for the next argument
20562 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20563 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20565 .addImm(UseFPOffset ? 16 : 8);
20567 // Store it back into the va_list.
20568 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20572 .addDisp(Disp, UseFPOffset ? 4 : 0)
20573 .addOperand(Segment)
20574 .addReg(NextOffsetReg)
20575 .setMemRefs(MMOBegin, MMOEnd);
20578 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20583 // Emit code to use overflow area
20586 // Load the overflow_area address into a register.
20587 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20588 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20593 .addOperand(Segment)
20594 .setMemRefs(MMOBegin, MMOEnd);
20596 // If we need to align it, do so. Otherwise, just copy the address
20597 // to OverflowDestReg.
20599 // Align the overflow address
20600 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20601 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20603 // aligned_addr = (addr + (align-1)) & ~(align-1)
20604 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20605 .addReg(OverflowAddrReg)
20608 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20610 .addImm(~(uint64_t)(Align-1));
20612 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20613 .addReg(OverflowAddrReg);
20616 // Compute the next overflow address after this argument.
20617 // (the overflow address should be kept 8-byte aligned)
20618 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20619 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20620 .addReg(OverflowDestReg)
20621 .addImm(ArgSizeA8);
20623 // Store the new overflow address.
20624 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20629 .addOperand(Segment)
20630 .addReg(NextAddrReg)
20631 .setMemRefs(MMOBegin, MMOEnd);
20633 // If we branched, emit the PHI to the front of endMBB.
20635 BuildMI(*endMBB, endMBB->begin(), DL,
20636 TII->get(X86::PHI), DestReg)
20637 .addReg(OffsetDestReg).addMBB(offsetMBB)
20638 .addReg(OverflowDestReg).addMBB(overflowMBB);
20641 // Erase the pseudo instruction
20642 MI->eraseFromParent();
20647 MachineBasicBlock *
20648 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20650 MachineBasicBlock *MBB) const {
20651 // Emit code to save XMM registers to the stack. The ABI says that the
20652 // number of registers to save is given in %al, so it's theoretically
20653 // possible to do an indirect jump trick to avoid saving all of them,
20654 // however this code takes a simpler approach and just executes all
20655 // of the stores if %al is non-zero. It's less code, and it's probably
20656 // easier on the hardware branch predictor, and stores aren't all that
20657 // expensive anyway.
20659 // Create the new basic blocks. One block contains all the XMM stores,
20660 // and one block is the final destination regardless of whether any
20661 // stores were performed.
20662 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20663 MachineFunction *F = MBB->getParent();
20664 MachineFunction::iterator MBBIter = MBB;
20666 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20667 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20668 F->insert(MBBIter, XMMSaveMBB);
20669 F->insert(MBBIter, EndMBB);
20671 // Transfer the remainder of MBB and its successor edges to EndMBB.
20672 EndMBB->splice(EndMBB->begin(), MBB,
20673 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20674 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20676 // The original block will now fall through to the XMM save block.
20677 MBB->addSuccessor(XMMSaveMBB);
20678 // The XMMSaveMBB will fall through to the end block.
20679 XMMSaveMBB->addSuccessor(EndMBB);
20681 // Now add the instructions.
20682 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20683 DebugLoc DL = MI->getDebugLoc();
20685 unsigned CountReg = MI->getOperand(0).getReg();
20686 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20687 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20689 if (!Subtarget->isTargetWin64()) {
20690 // If %al is 0, branch around the XMM save block.
20691 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20692 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20693 MBB->addSuccessor(EndMBB);
20696 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20697 // that was just emitted, but clearly shouldn't be "saved".
20698 assert((MI->getNumOperands() <= 3 ||
20699 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20700 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20701 && "Expected last argument to be EFLAGS");
20702 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20703 // In the XMM save block, save all the XMM argument registers.
20704 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20705 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20706 MachineMemOperand *MMO =
20707 F->getMachineMemOperand(
20708 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20709 MachineMemOperand::MOStore,
20710 /*Size=*/16, /*Align=*/16);
20711 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20712 .addFrameIndex(RegSaveFrameIndex)
20713 .addImm(/*Scale=*/1)
20714 .addReg(/*IndexReg=*/0)
20715 .addImm(/*Disp=*/Offset)
20716 .addReg(/*Segment=*/0)
20717 .addReg(MI->getOperand(i).getReg())
20718 .addMemOperand(MMO);
20721 MI->eraseFromParent(); // The pseudo instruction is gone now.
20726 // The EFLAGS operand of SelectItr might be missing a kill marker
20727 // because there were multiple uses of EFLAGS, and ISel didn't know
20728 // which to mark. Figure out whether SelectItr should have had a
20729 // kill marker, and set it if it should. Returns the correct kill
20731 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20732 MachineBasicBlock* BB,
20733 const TargetRegisterInfo* TRI) {
20734 // Scan forward through BB for a use/def of EFLAGS.
20735 MachineBasicBlock::iterator miI(std::next(SelectItr));
20736 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20737 const MachineInstr& mi = *miI;
20738 if (mi.readsRegister(X86::EFLAGS))
20740 if (mi.definesRegister(X86::EFLAGS))
20741 break; // Should have kill-flag - update below.
20744 // If we hit the end of the block, check whether EFLAGS is live into a
20746 if (miI == BB->end()) {
20747 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20748 sEnd = BB->succ_end();
20749 sItr != sEnd; ++sItr) {
20750 MachineBasicBlock* succ = *sItr;
20751 if (succ->isLiveIn(X86::EFLAGS))
20756 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20757 // out. SelectMI should have a kill flag on EFLAGS.
20758 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20762 MachineBasicBlock *
20763 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20764 MachineBasicBlock *BB) const {
20765 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20766 DebugLoc DL = MI->getDebugLoc();
20768 // To "insert" a SELECT_CC instruction, we actually have to insert the
20769 // diamond control-flow pattern. The incoming instruction knows the
20770 // destination vreg to set, the condition code register to branch on, the
20771 // true/false values to select between, and a branch opcode to use.
20772 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20773 MachineFunction::iterator It = BB;
20779 // cmpTY ccX, r1, r2
20781 // fallthrough --> copy0MBB
20782 MachineBasicBlock *thisMBB = BB;
20783 MachineFunction *F = BB->getParent();
20784 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20785 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20786 F->insert(It, copy0MBB);
20787 F->insert(It, sinkMBB);
20789 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20790 // live into the sink and copy blocks.
20791 const TargetRegisterInfo *TRI =
20792 BB->getParent()->getSubtarget().getRegisterInfo();
20793 if (!MI->killsRegister(X86::EFLAGS) &&
20794 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20795 copy0MBB->addLiveIn(X86::EFLAGS);
20796 sinkMBB->addLiveIn(X86::EFLAGS);
20799 // Transfer the remainder of BB and its successor edges to sinkMBB.
20800 sinkMBB->splice(sinkMBB->begin(), BB,
20801 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20802 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20804 // Add the true and fallthrough blocks as its successors.
20805 BB->addSuccessor(copy0MBB);
20806 BB->addSuccessor(sinkMBB);
20808 // Create the conditional branch instruction.
20810 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20811 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20814 // %FalseValue = ...
20815 // # fallthrough to sinkMBB
20816 copy0MBB->addSuccessor(sinkMBB);
20819 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20821 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20822 TII->get(X86::PHI), MI->getOperand(0).getReg())
20823 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20824 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20826 MI->eraseFromParent(); // The pseudo instruction is gone now.
20830 MachineBasicBlock *
20831 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20832 MachineBasicBlock *BB) const {
20833 MachineFunction *MF = BB->getParent();
20834 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20835 DebugLoc DL = MI->getDebugLoc();
20836 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20838 assert(MF->shouldSplitStack());
20840 const bool Is64Bit = Subtarget->is64Bit();
20841 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20843 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20844 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20847 // ... [Till the alloca]
20848 // If stacklet is not large enough, jump to mallocMBB
20851 // Allocate by subtracting from RSP
20852 // Jump to continueMBB
20855 // Allocate by call to runtime
20859 // [rest of original BB]
20862 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20863 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20864 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20866 MachineRegisterInfo &MRI = MF->getRegInfo();
20867 const TargetRegisterClass *AddrRegClass =
20868 getRegClassFor(getPointerTy());
20870 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20871 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20872 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20873 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20874 sizeVReg = MI->getOperand(1).getReg(),
20875 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20877 MachineFunction::iterator MBBIter = BB;
20880 MF->insert(MBBIter, bumpMBB);
20881 MF->insert(MBBIter, mallocMBB);
20882 MF->insert(MBBIter, continueMBB);
20884 continueMBB->splice(continueMBB->begin(), BB,
20885 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20886 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20888 // Add code to the main basic block to check if the stack limit has been hit,
20889 // and if so, jump to mallocMBB otherwise to bumpMBB.
20890 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20891 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20892 .addReg(tmpSPVReg).addReg(sizeVReg);
20893 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20894 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20895 .addReg(SPLimitVReg);
20896 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20898 // bumpMBB simply decreases the stack pointer, since we know the current
20899 // stacklet has enough space.
20900 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20901 .addReg(SPLimitVReg);
20902 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20903 .addReg(SPLimitVReg);
20904 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20906 // Calls into a routine in libgcc to allocate more space from the heap.
20907 const uint32_t *RegMask = MF->getTarget()
20908 .getSubtargetImpl()
20909 ->getRegisterInfo()
20910 ->getCallPreservedMask(CallingConv::C);
20912 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20914 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20915 .addExternalSymbol("__morestack_allocate_stack_space")
20916 .addRegMask(RegMask)
20917 .addReg(X86::RDI, RegState::Implicit)
20918 .addReg(X86::RAX, RegState::ImplicitDefine);
20919 } else if (Is64Bit) {
20920 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20922 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20923 .addExternalSymbol("__morestack_allocate_stack_space")
20924 .addRegMask(RegMask)
20925 .addReg(X86::EDI, RegState::Implicit)
20926 .addReg(X86::EAX, RegState::ImplicitDefine);
20928 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20930 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20931 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20932 .addExternalSymbol("__morestack_allocate_stack_space")
20933 .addRegMask(RegMask)
20934 .addReg(X86::EAX, RegState::ImplicitDefine);
20938 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20941 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20942 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20943 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20945 // Set up the CFG correctly.
20946 BB->addSuccessor(bumpMBB);
20947 BB->addSuccessor(mallocMBB);
20948 mallocMBB->addSuccessor(continueMBB);
20949 bumpMBB->addSuccessor(continueMBB);
20951 // Take care of the PHI nodes.
20952 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20953 MI->getOperand(0).getReg())
20954 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20955 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20957 // Delete the original pseudo instruction.
20958 MI->eraseFromParent();
20961 return continueMBB;
20964 MachineBasicBlock *
20965 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20966 MachineBasicBlock *BB) const {
20967 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20968 DebugLoc DL = MI->getDebugLoc();
20970 assert(!Subtarget->isTargetMachO());
20972 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20973 // non-trivial part is impdef of ESP.
20975 if (Subtarget->isTargetWin64()) {
20976 if (Subtarget->isTargetCygMing()) {
20977 // ___chkstk(Mingw64):
20978 // Clobbers R10, R11, RAX and EFLAGS.
20980 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20981 .addExternalSymbol("___chkstk")
20982 .addReg(X86::RAX, RegState::Implicit)
20983 .addReg(X86::RSP, RegState::Implicit)
20984 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20985 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20986 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20988 // __chkstk(MSVCRT): does not update stack pointer.
20989 // Clobbers R10, R11 and EFLAGS.
20990 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20991 .addExternalSymbol("__chkstk")
20992 .addReg(X86::RAX, RegState::Implicit)
20993 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20994 // RAX has the offset to be subtracted from RSP.
20995 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
21000 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
21001 Subtarget->isTargetWindowsItanium())
21005 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
21006 .addExternalSymbol(StackProbeSymbol)
21007 .addReg(X86::EAX, RegState::Implicit)
21008 .addReg(X86::ESP, RegState::Implicit)
21009 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
21010 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
21011 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21014 MI->eraseFromParent(); // The pseudo instruction is gone now.
21018 MachineBasicBlock *
21019 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21020 MachineBasicBlock *BB) const {
21021 // This is pretty easy. We're taking the value that we received from
21022 // our load from the relocation, sticking it in either RDI (x86-64)
21023 // or EAX and doing an indirect call. The return value will then
21024 // be in the normal return register.
21025 MachineFunction *F = BB->getParent();
21026 const X86InstrInfo *TII =
21027 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21028 DebugLoc DL = MI->getDebugLoc();
21030 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21031 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21033 // Get a register mask for the lowered call.
21034 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21035 // proper register mask.
21036 const uint32_t *RegMask = F->getTarget()
21037 .getSubtargetImpl()
21038 ->getRegisterInfo()
21039 ->getCallPreservedMask(CallingConv::C);
21040 if (Subtarget->is64Bit()) {
21041 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21042 TII->get(X86::MOV64rm), X86::RDI)
21044 .addImm(0).addReg(0)
21045 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21046 MI->getOperand(3).getTargetFlags())
21048 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21049 addDirectMem(MIB, X86::RDI);
21050 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21051 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21052 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21053 TII->get(X86::MOV32rm), X86::EAX)
21055 .addImm(0).addReg(0)
21056 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21057 MI->getOperand(3).getTargetFlags())
21059 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21060 addDirectMem(MIB, X86::EAX);
21061 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21063 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21064 TII->get(X86::MOV32rm), X86::EAX)
21065 .addReg(TII->getGlobalBaseReg(F))
21066 .addImm(0).addReg(0)
21067 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21068 MI->getOperand(3).getTargetFlags())
21070 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21071 addDirectMem(MIB, X86::EAX);
21072 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21075 MI->eraseFromParent(); // The pseudo instruction is gone now.
21079 MachineBasicBlock *
21080 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21081 MachineBasicBlock *MBB) const {
21082 DebugLoc DL = MI->getDebugLoc();
21083 MachineFunction *MF = MBB->getParent();
21084 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21085 MachineRegisterInfo &MRI = MF->getRegInfo();
21087 const BasicBlock *BB = MBB->getBasicBlock();
21088 MachineFunction::iterator I = MBB;
21091 // Memory Reference
21092 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21093 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21096 unsigned MemOpndSlot = 0;
21098 unsigned CurOp = 0;
21100 DstReg = MI->getOperand(CurOp++).getReg();
21101 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21102 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21103 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21104 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21106 MemOpndSlot = CurOp;
21108 MVT PVT = getPointerTy();
21109 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21110 "Invalid Pointer Size!");
21112 // For v = setjmp(buf), we generate
21115 // buf[LabelOffset] = restoreMBB
21116 // SjLjSetup restoreMBB
21122 // v = phi(main, restore)
21125 // if base pointer being used, load it from frame
21128 MachineBasicBlock *thisMBB = MBB;
21129 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21130 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21131 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21132 MF->insert(I, mainMBB);
21133 MF->insert(I, sinkMBB);
21134 MF->push_back(restoreMBB);
21136 MachineInstrBuilder MIB;
21138 // Transfer the remainder of BB and its successor edges to sinkMBB.
21139 sinkMBB->splice(sinkMBB->begin(), MBB,
21140 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21141 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21144 unsigned PtrStoreOpc = 0;
21145 unsigned LabelReg = 0;
21146 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21147 Reloc::Model RM = MF->getTarget().getRelocationModel();
21148 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21149 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21151 // Prepare IP either in reg or imm.
21152 if (!UseImmLabel) {
21153 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21154 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21155 LabelReg = MRI.createVirtualRegister(PtrRC);
21156 if (Subtarget->is64Bit()) {
21157 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21161 .addMBB(restoreMBB)
21164 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21165 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21166 .addReg(XII->getGlobalBaseReg(MF))
21169 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21173 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21175 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21176 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21177 if (i == X86::AddrDisp)
21178 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21180 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21183 MIB.addReg(LabelReg);
21185 MIB.addMBB(restoreMBB);
21186 MIB.setMemRefs(MMOBegin, MMOEnd);
21188 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21189 .addMBB(restoreMBB);
21191 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21192 MF->getSubtarget().getRegisterInfo());
21193 MIB.addRegMask(RegInfo->getNoPreservedMask());
21194 thisMBB->addSuccessor(mainMBB);
21195 thisMBB->addSuccessor(restoreMBB);
21199 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21200 mainMBB->addSuccessor(sinkMBB);
21203 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21204 TII->get(X86::PHI), DstReg)
21205 .addReg(mainDstReg).addMBB(mainMBB)
21206 .addReg(restoreDstReg).addMBB(restoreMBB);
21209 if (RegInfo->hasBasePointer(*MF)) {
21210 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21211 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21212 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21213 X86FI->setRestoreBasePointer(MF);
21214 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21215 unsigned BasePtr = RegInfo->getBaseRegister();
21216 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21217 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21218 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21219 .setMIFlag(MachineInstr::FrameSetup);
21221 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21222 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21223 restoreMBB->addSuccessor(sinkMBB);
21225 MI->eraseFromParent();
21229 MachineBasicBlock *
21230 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21231 MachineBasicBlock *MBB) const {
21232 DebugLoc DL = MI->getDebugLoc();
21233 MachineFunction *MF = MBB->getParent();
21234 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21235 MachineRegisterInfo &MRI = MF->getRegInfo();
21237 // Memory Reference
21238 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21239 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21241 MVT PVT = getPointerTy();
21242 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21243 "Invalid Pointer Size!");
21245 const TargetRegisterClass *RC =
21246 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21247 unsigned Tmp = MRI.createVirtualRegister(RC);
21248 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21249 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21250 MF->getSubtarget().getRegisterInfo());
21251 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21252 unsigned SP = RegInfo->getStackRegister();
21254 MachineInstrBuilder MIB;
21256 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21257 const int64_t SPOffset = 2 * PVT.getStoreSize();
21259 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21260 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21263 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21264 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21265 MIB.addOperand(MI->getOperand(i));
21266 MIB.setMemRefs(MMOBegin, MMOEnd);
21268 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21269 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21270 if (i == X86::AddrDisp)
21271 MIB.addDisp(MI->getOperand(i), LabelOffset);
21273 MIB.addOperand(MI->getOperand(i));
21275 MIB.setMemRefs(MMOBegin, MMOEnd);
21277 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21278 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21279 if (i == X86::AddrDisp)
21280 MIB.addDisp(MI->getOperand(i), SPOffset);
21282 MIB.addOperand(MI->getOperand(i));
21284 MIB.setMemRefs(MMOBegin, MMOEnd);
21286 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21288 MI->eraseFromParent();
21292 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21293 // accumulator loops. Writing back to the accumulator allows the coalescer
21294 // to remove extra copies in the loop.
21295 MachineBasicBlock *
21296 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21297 MachineBasicBlock *MBB) const {
21298 MachineOperand &AddendOp = MI->getOperand(3);
21300 // Bail out early if the addend isn't a register - we can't switch these.
21301 if (!AddendOp.isReg())
21304 MachineFunction &MF = *MBB->getParent();
21305 MachineRegisterInfo &MRI = MF.getRegInfo();
21307 // Check whether the addend is defined by a PHI:
21308 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21309 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21310 if (!AddendDef.isPHI())
21313 // Look for the following pattern:
21315 // %addend = phi [%entry, 0], [%loop, %result]
21317 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21321 // %addend = phi [%entry, 0], [%loop, %result]
21323 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21325 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21326 assert(AddendDef.getOperand(i).isReg());
21327 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21328 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21329 if (&PHISrcInst == MI) {
21330 // Found a matching instruction.
21331 unsigned NewFMAOpc = 0;
21332 switch (MI->getOpcode()) {
21333 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21334 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21335 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21336 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21337 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21338 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21339 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21340 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21341 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21342 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21343 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21344 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21345 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21346 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21347 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21348 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21349 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21350 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21351 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21352 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21354 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21355 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21356 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21357 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21358 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21359 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21360 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21361 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21362 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21363 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21364 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21365 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21366 default: llvm_unreachable("Unrecognized FMA variant.");
21369 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21370 MachineInstrBuilder MIB =
21371 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21372 .addOperand(MI->getOperand(0))
21373 .addOperand(MI->getOperand(3))
21374 .addOperand(MI->getOperand(2))
21375 .addOperand(MI->getOperand(1));
21376 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21377 MI->eraseFromParent();
21384 MachineBasicBlock *
21385 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21386 MachineBasicBlock *BB) const {
21387 switch (MI->getOpcode()) {
21388 default: llvm_unreachable("Unexpected instr type to insert");
21389 case X86::TAILJMPd64:
21390 case X86::TAILJMPr64:
21391 case X86::TAILJMPm64:
21392 llvm_unreachable("TAILJMP64 would not be touched here.");
21393 case X86::TCRETURNdi64:
21394 case X86::TCRETURNri64:
21395 case X86::TCRETURNmi64:
21397 case X86::WIN_ALLOCA:
21398 return EmitLoweredWinAlloca(MI, BB);
21399 case X86::SEG_ALLOCA_32:
21400 case X86::SEG_ALLOCA_64:
21401 return EmitLoweredSegAlloca(MI, BB);
21402 case X86::TLSCall_32:
21403 case X86::TLSCall_64:
21404 return EmitLoweredTLSCall(MI, BB);
21405 case X86::CMOV_GR8:
21406 case X86::CMOV_FR32:
21407 case X86::CMOV_FR64:
21408 case X86::CMOV_V4F32:
21409 case X86::CMOV_V2F64:
21410 case X86::CMOV_V2I64:
21411 case X86::CMOV_V8F32:
21412 case X86::CMOV_V4F64:
21413 case X86::CMOV_V4I64:
21414 case X86::CMOV_V16F32:
21415 case X86::CMOV_V8F64:
21416 case X86::CMOV_V8I64:
21417 case X86::CMOV_GR16:
21418 case X86::CMOV_GR32:
21419 case X86::CMOV_RFP32:
21420 case X86::CMOV_RFP64:
21421 case X86::CMOV_RFP80:
21422 return EmitLoweredSelect(MI, BB);
21424 case X86::FP32_TO_INT16_IN_MEM:
21425 case X86::FP32_TO_INT32_IN_MEM:
21426 case X86::FP32_TO_INT64_IN_MEM:
21427 case X86::FP64_TO_INT16_IN_MEM:
21428 case X86::FP64_TO_INT32_IN_MEM:
21429 case X86::FP64_TO_INT64_IN_MEM:
21430 case X86::FP80_TO_INT16_IN_MEM:
21431 case X86::FP80_TO_INT32_IN_MEM:
21432 case X86::FP80_TO_INT64_IN_MEM: {
21433 MachineFunction *F = BB->getParent();
21434 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21435 DebugLoc DL = MI->getDebugLoc();
21437 // Change the floating point control register to use "round towards zero"
21438 // mode when truncating to an integer value.
21439 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21440 addFrameReference(BuildMI(*BB, MI, DL,
21441 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21443 // Load the old value of the high byte of the control word...
21445 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21446 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21449 // Set the high part to be round to zero...
21450 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21453 // Reload the modified control word now...
21454 addFrameReference(BuildMI(*BB, MI, DL,
21455 TII->get(X86::FLDCW16m)), CWFrameIdx);
21457 // Restore the memory image of control word to original value
21458 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21461 // Get the X86 opcode to use.
21463 switch (MI->getOpcode()) {
21464 default: llvm_unreachable("illegal opcode!");
21465 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21466 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21467 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21468 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21469 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21470 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21471 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21472 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21473 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21477 MachineOperand &Op = MI->getOperand(0);
21479 AM.BaseType = X86AddressMode::RegBase;
21480 AM.Base.Reg = Op.getReg();
21482 AM.BaseType = X86AddressMode::FrameIndexBase;
21483 AM.Base.FrameIndex = Op.getIndex();
21485 Op = MI->getOperand(1);
21487 AM.Scale = Op.getImm();
21488 Op = MI->getOperand(2);
21490 AM.IndexReg = Op.getImm();
21491 Op = MI->getOperand(3);
21492 if (Op.isGlobal()) {
21493 AM.GV = Op.getGlobal();
21495 AM.Disp = Op.getImm();
21497 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21498 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21500 // Reload the original control word now.
21501 addFrameReference(BuildMI(*BB, MI, DL,
21502 TII->get(X86::FLDCW16m)), CWFrameIdx);
21504 MI->eraseFromParent(); // The pseudo instruction is gone now.
21507 // String/text processing lowering.
21508 case X86::PCMPISTRM128REG:
21509 case X86::VPCMPISTRM128REG:
21510 case X86::PCMPISTRM128MEM:
21511 case X86::VPCMPISTRM128MEM:
21512 case X86::PCMPESTRM128REG:
21513 case X86::VPCMPESTRM128REG:
21514 case X86::PCMPESTRM128MEM:
21515 case X86::VPCMPESTRM128MEM:
21516 assert(Subtarget->hasSSE42() &&
21517 "Target must have SSE4.2 or AVX features enabled");
21518 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21520 // String/text processing lowering.
21521 case X86::PCMPISTRIREG:
21522 case X86::VPCMPISTRIREG:
21523 case X86::PCMPISTRIMEM:
21524 case X86::VPCMPISTRIMEM:
21525 case X86::PCMPESTRIREG:
21526 case X86::VPCMPESTRIREG:
21527 case X86::PCMPESTRIMEM:
21528 case X86::VPCMPESTRIMEM:
21529 assert(Subtarget->hasSSE42() &&
21530 "Target must have SSE4.2 or AVX features enabled");
21531 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21533 // Thread synchronization.
21535 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21540 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21542 case X86::VASTART_SAVE_XMM_REGS:
21543 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21545 case X86::VAARG_64:
21546 return EmitVAARG64WithCustomInserter(MI, BB);
21548 case X86::EH_SjLj_SetJmp32:
21549 case X86::EH_SjLj_SetJmp64:
21550 return emitEHSjLjSetJmp(MI, BB);
21552 case X86::EH_SjLj_LongJmp32:
21553 case X86::EH_SjLj_LongJmp64:
21554 return emitEHSjLjLongJmp(MI, BB);
21556 case TargetOpcode::STATEPOINT:
21557 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21558 // this point in the process. We diverge later.
21559 return emitPatchPoint(MI, BB);
21561 case TargetOpcode::STACKMAP:
21562 case TargetOpcode::PATCHPOINT:
21563 return emitPatchPoint(MI, BB);
21565 case X86::VFMADDPDr213r:
21566 case X86::VFMADDPSr213r:
21567 case X86::VFMADDSDr213r:
21568 case X86::VFMADDSSr213r:
21569 case X86::VFMSUBPDr213r:
21570 case X86::VFMSUBPSr213r:
21571 case X86::VFMSUBSDr213r:
21572 case X86::VFMSUBSSr213r:
21573 case X86::VFNMADDPDr213r:
21574 case X86::VFNMADDPSr213r:
21575 case X86::VFNMADDSDr213r:
21576 case X86::VFNMADDSSr213r:
21577 case X86::VFNMSUBPDr213r:
21578 case X86::VFNMSUBPSr213r:
21579 case X86::VFNMSUBSDr213r:
21580 case X86::VFNMSUBSSr213r:
21581 case X86::VFMADDSUBPDr213r:
21582 case X86::VFMADDSUBPSr213r:
21583 case X86::VFMSUBADDPDr213r:
21584 case X86::VFMSUBADDPSr213r:
21585 case X86::VFMADDPDr213rY:
21586 case X86::VFMADDPSr213rY:
21587 case X86::VFMSUBPDr213rY:
21588 case X86::VFMSUBPSr213rY:
21589 case X86::VFNMADDPDr213rY:
21590 case X86::VFNMADDPSr213rY:
21591 case X86::VFNMSUBPDr213rY:
21592 case X86::VFNMSUBPSr213rY:
21593 case X86::VFMADDSUBPDr213rY:
21594 case X86::VFMADDSUBPSr213rY:
21595 case X86::VFMSUBADDPDr213rY:
21596 case X86::VFMSUBADDPSr213rY:
21597 return emitFMA3Instr(MI, BB);
21601 //===----------------------------------------------------------------------===//
21602 // X86 Optimization Hooks
21603 //===----------------------------------------------------------------------===//
21605 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21608 const SelectionDAG &DAG,
21609 unsigned Depth) const {
21610 unsigned BitWidth = KnownZero.getBitWidth();
21611 unsigned Opc = Op.getOpcode();
21612 assert((Opc >= ISD::BUILTIN_OP_END ||
21613 Opc == ISD::INTRINSIC_WO_CHAIN ||
21614 Opc == ISD::INTRINSIC_W_CHAIN ||
21615 Opc == ISD::INTRINSIC_VOID) &&
21616 "Should use MaskedValueIsZero if you don't know whether Op"
21617 " is a target node!");
21619 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21633 // These nodes' second result is a boolean.
21634 if (Op.getResNo() == 0)
21637 case X86ISD::SETCC:
21638 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21640 case ISD::INTRINSIC_WO_CHAIN: {
21641 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21642 unsigned NumLoBits = 0;
21645 case Intrinsic::x86_sse_movmsk_ps:
21646 case Intrinsic::x86_avx_movmsk_ps_256:
21647 case Intrinsic::x86_sse2_movmsk_pd:
21648 case Intrinsic::x86_avx_movmsk_pd_256:
21649 case Intrinsic::x86_mmx_pmovmskb:
21650 case Intrinsic::x86_sse2_pmovmskb_128:
21651 case Intrinsic::x86_avx2_pmovmskb: {
21652 // High bits of movmskp{s|d}, pmovmskb are known zero.
21654 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21655 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21656 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21657 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21658 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21659 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21660 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21661 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21663 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21672 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21674 const SelectionDAG &,
21675 unsigned Depth) const {
21676 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21677 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21678 return Op.getValueType().getScalarType().getSizeInBits();
21684 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21685 /// node is a GlobalAddress + offset.
21686 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21687 const GlobalValue* &GA,
21688 int64_t &Offset) const {
21689 if (N->getOpcode() == X86ISD::Wrapper) {
21690 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21691 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21692 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21696 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21699 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21700 /// same as extracting the high 128-bit part of 256-bit vector and then
21701 /// inserting the result into the low part of a new 256-bit vector
21702 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21703 EVT VT = SVOp->getValueType(0);
21704 unsigned NumElems = VT.getVectorNumElements();
21706 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21707 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21708 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21709 SVOp->getMaskElt(j) >= 0)
21715 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21716 /// same as extracting the low 128-bit part of 256-bit vector and then
21717 /// inserting the result into the high part of a new 256-bit vector
21718 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21719 EVT VT = SVOp->getValueType(0);
21720 unsigned NumElems = VT.getVectorNumElements();
21722 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21723 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21724 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21725 SVOp->getMaskElt(j) >= 0)
21731 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21732 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21733 TargetLowering::DAGCombinerInfo &DCI,
21734 const X86Subtarget* Subtarget) {
21736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21737 SDValue V1 = SVOp->getOperand(0);
21738 SDValue V2 = SVOp->getOperand(1);
21739 EVT VT = SVOp->getValueType(0);
21740 unsigned NumElems = VT.getVectorNumElements();
21742 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21743 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21747 // V UNDEF BUILD_VECTOR UNDEF
21749 // CONCAT_VECTOR CONCAT_VECTOR
21752 // RESULT: V + zero extended
21754 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21755 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21756 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21759 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21762 // To match the shuffle mask, the first half of the mask should
21763 // be exactly the first vector, and all the rest a splat with the
21764 // first element of the second one.
21765 for (unsigned i = 0; i != NumElems/2; ++i)
21766 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21767 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21770 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21771 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21772 if (Ld->hasNUsesOfValue(1, 0)) {
21773 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21774 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21776 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21778 Ld->getPointerInfo(),
21779 Ld->getAlignment(),
21780 false/*isVolatile*/, true/*ReadMem*/,
21781 false/*WriteMem*/);
21783 // Make sure the newly-created LOAD is in the same position as Ld in
21784 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21785 // and update uses of Ld's output chain to use the TokenFactor.
21786 if (Ld->hasAnyUseOfValue(1)) {
21787 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21788 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21789 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21790 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21791 SDValue(ResNode.getNode(), 1));
21794 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21798 // Emit a zeroed vector and insert the desired subvector on its
21800 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21801 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21802 return DCI.CombineTo(N, InsV);
21805 //===--------------------------------------------------------------------===//
21806 // Combine some shuffles into subvector extracts and inserts:
21809 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21810 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21811 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21812 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21813 return DCI.CombineTo(N, InsV);
21816 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21817 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21818 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21819 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21820 return DCI.CombineTo(N, InsV);
21826 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21829 /// This is the leaf of the recursive combinine below. When we have found some
21830 /// chain of single-use x86 shuffle instructions and accumulated the combined
21831 /// shuffle mask represented by them, this will try to pattern match that mask
21832 /// into either a single instruction if there is a special purpose instruction
21833 /// for this operation, or into a PSHUFB instruction which is a fully general
21834 /// instruction but should only be used to replace chains over a certain depth.
21835 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21836 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21837 TargetLowering::DAGCombinerInfo &DCI,
21838 const X86Subtarget *Subtarget) {
21839 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21841 // Find the operand that enters the chain. Note that multiple uses are OK
21842 // here, we're not going to remove the operand we find.
21843 SDValue Input = Op.getOperand(0);
21844 while (Input.getOpcode() == ISD::BITCAST)
21845 Input = Input.getOperand(0);
21847 MVT VT = Input.getSimpleValueType();
21848 MVT RootVT = Root.getSimpleValueType();
21851 // Just remove no-op shuffle masks.
21852 if (Mask.size() == 1) {
21853 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21858 // Use the float domain if the operand type is a floating point type.
21859 bool FloatDomain = VT.isFloatingPoint();
21861 // For floating point shuffles, we don't have free copies in the shuffle
21862 // instructions or the ability to load as part of the instruction, so
21863 // canonicalize their shuffles to UNPCK or MOV variants.
21865 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21866 // vectors because it can have a load folded into it that UNPCK cannot. This
21867 // doesn't preclude something switching to the shorter encoding post-RA.
21869 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21870 bool Lo = Mask.equals(0, 0);
21873 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21874 // is no slower than UNPCKLPD but has the option to fold the input operand
21875 // into even an unaligned memory load.
21876 if (Lo && Subtarget->hasSSE3()) {
21877 Shuffle = X86ISD::MOVDDUP;
21878 ShuffleVT = MVT::v2f64;
21880 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21881 // than the UNPCK variants.
21882 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21883 ShuffleVT = MVT::v4f32;
21885 if (Depth == 1 && Root->getOpcode() == Shuffle)
21886 return false; // Nothing to do!
21887 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21888 DCI.AddToWorklist(Op.getNode());
21889 if (Shuffle == X86ISD::MOVDDUP)
21890 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21892 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21893 DCI.AddToWorklist(Op.getNode());
21894 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21898 if (Subtarget->hasSSE3() &&
21899 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21900 bool Lo = Mask.equals(0, 0, 2, 2);
21901 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21902 MVT ShuffleVT = MVT::v4f32;
21903 if (Depth == 1 && Root->getOpcode() == Shuffle)
21904 return false; // Nothing to do!
21905 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21906 DCI.AddToWorklist(Op.getNode());
21907 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21908 DCI.AddToWorklist(Op.getNode());
21909 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21913 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21914 bool Lo = Mask.equals(0, 0, 1, 1);
21915 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21916 MVT ShuffleVT = MVT::v4f32;
21917 if (Depth == 1 && Root->getOpcode() == Shuffle)
21918 return false; // Nothing to do!
21919 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21920 DCI.AddToWorklist(Op.getNode());
21921 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21922 DCI.AddToWorklist(Op.getNode());
21923 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21929 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21930 // variants as none of these have single-instruction variants that are
21931 // superior to the UNPCK formulation.
21932 if (!FloatDomain &&
21933 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21934 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21935 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21936 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21938 bool Lo = Mask[0] == 0;
21939 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21940 if (Depth == 1 && Root->getOpcode() == Shuffle)
21941 return false; // Nothing to do!
21943 switch (Mask.size()) {
21945 ShuffleVT = MVT::v8i16;
21948 ShuffleVT = MVT::v16i8;
21951 llvm_unreachable("Impossible mask size!");
21953 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21954 DCI.AddToWorklist(Op.getNode());
21955 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21956 DCI.AddToWorklist(Op.getNode());
21957 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21962 // Don't try to re-form single instruction chains under any circumstances now
21963 // that we've done encoding canonicalization for them.
21967 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21968 // can replace them with a single PSHUFB instruction profitably. Intel's
21969 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21970 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21971 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21972 SmallVector<SDValue, 16> PSHUFBMask;
21973 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21974 int Ratio = 16 / Mask.size();
21975 for (unsigned i = 0; i < 16; ++i) {
21976 if (Mask[i / Ratio] == SM_SentinelUndef) {
21977 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21980 int M = Mask[i / Ratio] != SM_SentinelZero
21981 ? Ratio * Mask[i / Ratio] + i % Ratio
21983 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21985 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21986 DCI.AddToWorklist(Op.getNode());
21987 SDValue PSHUFBMaskOp =
21988 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21989 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21990 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21991 DCI.AddToWorklist(Op.getNode());
21992 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21997 // Failed to find any combines.
22001 /// \brief Fully generic combining of x86 shuffle instructions.
22003 /// This should be the last combine run over the x86 shuffle instructions. Once
22004 /// they have been fully optimized, this will recursively consider all chains
22005 /// of single-use shuffle instructions, build a generic model of the cumulative
22006 /// shuffle operation, and check for simpler instructions which implement this
22007 /// operation. We use this primarily for two purposes:
22009 /// 1) Collapse generic shuffles to specialized single instructions when
22010 /// equivalent. In most cases, this is just an encoding size win, but
22011 /// sometimes we will collapse multiple generic shuffles into a single
22012 /// special-purpose shuffle.
22013 /// 2) Look for sequences of shuffle instructions with 3 or more total
22014 /// instructions, and replace them with the slightly more expensive SSSE3
22015 /// PSHUFB instruction if available. We do this as the last combining step
22016 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22017 /// a suitable short sequence of other instructions. The PHUFB will either
22018 /// use a register or have to read from memory and so is slightly (but only
22019 /// slightly) more expensive than the other shuffle instructions.
22021 /// Because this is inherently a quadratic operation (for each shuffle in
22022 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22023 /// This should never be an issue in practice as the shuffle lowering doesn't
22024 /// produce sequences of more than 8 instructions.
22026 /// FIXME: We will currently miss some cases where the redundant shuffling
22027 /// would simplify under the threshold for PSHUFB formation because of
22028 /// combine-ordering. To fix this, we should do the redundant instruction
22029 /// combining in this recursive walk.
22030 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22031 ArrayRef<int> RootMask,
22032 int Depth, bool HasPSHUFB,
22034 TargetLowering::DAGCombinerInfo &DCI,
22035 const X86Subtarget *Subtarget) {
22036 // Bound the depth of our recursive combine because this is ultimately
22037 // quadratic in nature.
22041 // Directly rip through bitcasts to find the underlying operand.
22042 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22043 Op = Op.getOperand(0);
22045 MVT VT = Op.getSimpleValueType();
22046 if (!VT.isVector())
22047 return false; // Bail if we hit a non-vector.
22048 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22049 // version should be added.
22050 if (VT.getSizeInBits() != 128)
22053 assert(Root.getSimpleValueType().isVector() &&
22054 "Shuffles operate on vector types!");
22055 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22056 "Can only combine shuffles of the same vector register size.");
22058 if (!isTargetShuffle(Op.getOpcode()))
22060 SmallVector<int, 16> OpMask;
22062 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22063 // We only can combine unary shuffles which we can decode the mask for.
22064 if (!HaveMask || !IsUnary)
22067 assert(VT.getVectorNumElements() == OpMask.size() &&
22068 "Different mask size from vector size!");
22069 assert(((RootMask.size() > OpMask.size() &&
22070 RootMask.size() % OpMask.size() == 0) ||
22071 (OpMask.size() > RootMask.size() &&
22072 OpMask.size() % RootMask.size() == 0) ||
22073 OpMask.size() == RootMask.size()) &&
22074 "The smaller number of elements must divide the larger.");
22075 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22076 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22077 assert(((RootRatio == 1 && OpRatio == 1) ||
22078 (RootRatio == 1) != (OpRatio == 1)) &&
22079 "Must not have a ratio for both incoming and op masks!");
22081 SmallVector<int, 16> Mask;
22082 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22084 // Merge this shuffle operation's mask into our accumulated mask. Note that
22085 // this shuffle's mask will be the first applied to the input, followed by the
22086 // root mask to get us all the way to the root value arrangement. The reason
22087 // for this order is that we are recursing up the operation chain.
22088 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22089 int RootIdx = i / RootRatio;
22090 if (RootMask[RootIdx] < 0) {
22091 // This is a zero or undef lane, we're done.
22092 Mask.push_back(RootMask[RootIdx]);
22096 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22097 int OpIdx = RootMaskedIdx / OpRatio;
22098 if (OpMask[OpIdx] < 0) {
22099 // The incoming lanes are zero or undef, it doesn't matter which ones we
22101 Mask.push_back(OpMask[OpIdx]);
22105 // Ok, we have non-zero lanes, map them through.
22106 Mask.push_back(OpMask[OpIdx] * OpRatio +
22107 RootMaskedIdx % OpRatio);
22110 // See if we can recurse into the operand to combine more things.
22111 switch (Op.getOpcode()) {
22112 case X86ISD::PSHUFB:
22114 case X86ISD::PSHUFD:
22115 case X86ISD::PSHUFHW:
22116 case X86ISD::PSHUFLW:
22117 if (Op.getOperand(0).hasOneUse() &&
22118 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22119 HasPSHUFB, DAG, DCI, Subtarget))
22123 case X86ISD::UNPCKL:
22124 case X86ISD::UNPCKH:
22125 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22126 // We can't check for single use, we have to check that this shuffle is the only user.
22127 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22128 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22129 HasPSHUFB, DAG, DCI, Subtarget))
22134 // Minor canonicalization of the accumulated shuffle mask to make it easier
22135 // to match below. All this does is detect masks with squential pairs of
22136 // elements, and shrink them to the half-width mask. It does this in a loop
22137 // so it will reduce the size of the mask to the minimal width mask which
22138 // performs an equivalent shuffle.
22139 SmallVector<int, 16> WidenedMask;
22140 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22141 Mask = std::move(WidenedMask);
22142 WidenedMask.clear();
22145 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22149 /// \brief Get the PSHUF-style mask from PSHUF node.
22151 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22152 /// PSHUF-style masks that can be reused with such instructions.
22153 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22154 SmallVector<int, 4> Mask;
22156 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22160 switch (N.getOpcode()) {
22161 case X86ISD::PSHUFD:
22163 case X86ISD::PSHUFLW:
22166 case X86ISD::PSHUFHW:
22167 Mask.erase(Mask.begin(), Mask.begin() + 4);
22168 for (int &M : Mask)
22172 llvm_unreachable("No valid shuffle instruction found!");
22176 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22178 /// We walk up the chain and look for a combinable shuffle, skipping over
22179 /// shuffles that we could hoist this shuffle's transformation past without
22180 /// altering anything.
22182 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22184 TargetLowering::DAGCombinerInfo &DCI) {
22185 assert(N.getOpcode() == X86ISD::PSHUFD &&
22186 "Called with something other than an x86 128-bit half shuffle!");
22189 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22190 // of the shuffles in the chain so that we can form a fresh chain to replace
22192 SmallVector<SDValue, 8> Chain;
22193 SDValue V = N.getOperand(0);
22194 for (; V.hasOneUse(); V = V.getOperand(0)) {
22195 switch (V.getOpcode()) {
22197 return SDValue(); // Nothing combined!
22200 // Skip bitcasts as we always know the type for the target specific
22204 case X86ISD::PSHUFD:
22205 // Found another dword shuffle.
22208 case X86ISD::PSHUFLW:
22209 // Check that the low words (being shuffled) are the identity in the
22210 // dword shuffle, and the high words are self-contained.
22211 if (Mask[0] != 0 || Mask[1] != 1 ||
22212 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22215 Chain.push_back(V);
22218 case X86ISD::PSHUFHW:
22219 // Check that the high words (being shuffled) are the identity in the
22220 // dword shuffle, and the low words are self-contained.
22221 if (Mask[2] != 2 || Mask[3] != 3 ||
22222 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22225 Chain.push_back(V);
22228 case X86ISD::UNPCKL:
22229 case X86ISD::UNPCKH:
22230 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22231 // shuffle into a preceding word shuffle.
22232 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22235 // Search for a half-shuffle which we can combine with.
22236 unsigned CombineOp =
22237 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22238 if (V.getOperand(0) != V.getOperand(1) ||
22239 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22241 Chain.push_back(V);
22242 V = V.getOperand(0);
22244 switch (V.getOpcode()) {
22246 return SDValue(); // Nothing to combine.
22248 case X86ISD::PSHUFLW:
22249 case X86ISD::PSHUFHW:
22250 if (V.getOpcode() == CombineOp)
22253 Chain.push_back(V);
22257 V = V.getOperand(0);
22261 } while (V.hasOneUse());
22264 // Break out of the loop if we break out of the switch.
22268 if (!V.hasOneUse())
22269 // We fell out of the loop without finding a viable combining instruction.
22272 // Merge this node's mask and our incoming mask.
22273 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22274 for (int &M : Mask)
22276 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22277 getV4X86ShuffleImm8ForMask(Mask, DAG));
22279 // Rebuild the chain around this new shuffle.
22280 while (!Chain.empty()) {
22281 SDValue W = Chain.pop_back_val();
22283 if (V.getValueType() != W.getOperand(0).getValueType())
22284 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22286 switch (W.getOpcode()) {
22288 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22290 case X86ISD::UNPCKL:
22291 case X86ISD::UNPCKH:
22292 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22295 case X86ISD::PSHUFD:
22296 case X86ISD::PSHUFLW:
22297 case X86ISD::PSHUFHW:
22298 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22302 if (V.getValueType() != N.getValueType())
22303 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22305 // Return the new chain to replace N.
22309 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22311 /// We walk up the chain, skipping shuffles of the other half and looking
22312 /// through shuffles which switch halves trying to find a shuffle of the same
22313 /// pair of dwords.
22314 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22316 TargetLowering::DAGCombinerInfo &DCI) {
22318 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22319 "Called with something other than an x86 128-bit half shuffle!");
22321 unsigned CombineOpcode = N.getOpcode();
22323 // Walk up a single-use chain looking for a combinable shuffle.
22324 SDValue V = N.getOperand(0);
22325 for (; V.hasOneUse(); V = V.getOperand(0)) {
22326 switch (V.getOpcode()) {
22328 return false; // Nothing combined!
22331 // Skip bitcasts as we always know the type for the target specific
22335 case X86ISD::PSHUFLW:
22336 case X86ISD::PSHUFHW:
22337 if (V.getOpcode() == CombineOpcode)
22340 // Other-half shuffles are no-ops.
22343 // Break out of the loop if we break out of the switch.
22347 if (!V.hasOneUse())
22348 // We fell out of the loop without finding a viable combining instruction.
22351 // Combine away the bottom node as its shuffle will be accumulated into
22352 // a preceding shuffle.
22353 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22355 // Record the old value.
22358 // Merge this node's mask and our incoming mask (adjusted to account for all
22359 // the pshufd instructions encountered).
22360 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22361 for (int &M : Mask)
22363 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22364 getV4X86ShuffleImm8ForMask(Mask, DAG));
22366 // Check that the shuffles didn't cancel each other out. If not, we need to
22367 // combine to the new one.
22369 // Replace the combinable shuffle with the combined one, updating all users
22370 // so that we re-evaluate the chain here.
22371 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22376 /// \brief Try to combine x86 target specific shuffles.
22377 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22378 TargetLowering::DAGCombinerInfo &DCI,
22379 const X86Subtarget *Subtarget) {
22381 MVT VT = N.getSimpleValueType();
22382 SmallVector<int, 4> Mask;
22384 switch (N.getOpcode()) {
22385 case X86ISD::PSHUFD:
22386 case X86ISD::PSHUFLW:
22387 case X86ISD::PSHUFHW:
22388 Mask = getPSHUFShuffleMask(N);
22389 assert(Mask.size() == 4);
22395 // Nuke no-op shuffles that show up after combining.
22396 if (isNoopShuffleMask(Mask))
22397 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22399 // Look for simplifications involving one or two shuffle instructions.
22400 SDValue V = N.getOperand(0);
22401 switch (N.getOpcode()) {
22404 case X86ISD::PSHUFLW:
22405 case X86ISD::PSHUFHW:
22406 assert(VT == MVT::v8i16);
22409 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22410 return SDValue(); // We combined away this shuffle, so we're done.
22412 // See if this reduces to a PSHUFD which is no more expensive and can
22413 // combine with more operations. Note that it has to at least flip the
22414 // dwords as otherwise it would have been removed as a no-op.
22415 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22416 int DMask[] = {0, 1, 2, 3};
22417 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22418 DMask[DOffset + 0] = DOffset + 1;
22419 DMask[DOffset + 1] = DOffset + 0;
22420 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22421 DCI.AddToWorklist(V.getNode());
22422 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22423 getV4X86ShuffleImm8ForMask(DMask, DAG));
22424 DCI.AddToWorklist(V.getNode());
22425 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22428 // Look for shuffle patterns which can be implemented as a single unpack.
22429 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22430 // only works when we have a PSHUFD followed by two half-shuffles.
22431 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22432 (V.getOpcode() == X86ISD::PSHUFLW ||
22433 V.getOpcode() == X86ISD::PSHUFHW) &&
22434 V.getOpcode() != N.getOpcode() &&
22436 SDValue D = V.getOperand(0);
22437 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22438 D = D.getOperand(0);
22439 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22440 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22441 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22442 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22443 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22445 for (int i = 0; i < 4; ++i) {
22446 WordMask[i + NOffset] = Mask[i] + NOffset;
22447 WordMask[i + VOffset] = VMask[i] + VOffset;
22449 // Map the word mask through the DWord mask.
22451 for (int i = 0; i < 8; ++i)
22452 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22453 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22454 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22455 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22456 std::begin(UnpackLoMask)) ||
22457 std::equal(std::begin(MappedMask), std::end(MappedMask),
22458 std::begin(UnpackHiMask))) {
22459 // We can replace all three shuffles with an unpack.
22460 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22461 DCI.AddToWorklist(V.getNode());
22462 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22464 DL, MVT::v8i16, V, V);
22471 case X86ISD::PSHUFD:
22472 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22481 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22483 /// We combine this directly on the abstract vector shuffle nodes so it is
22484 /// easier to generically match. We also insert dummy vector shuffle nodes for
22485 /// the operands which explicitly discard the lanes which are unused by this
22486 /// operation to try to flow through the rest of the combiner the fact that
22487 /// they're unused.
22488 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22490 EVT VT = N->getValueType(0);
22492 // We only handle target-independent shuffles.
22493 // FIXME: It would be easy and harmless to use the target shuffle mask
22494 // extraction tool to support more.
22495 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22498 auto *SVN = cast<ShuffleVectorSDNode>(N);
22499 ArrayRef<int> Mask = SVN->getMask();
22500 SDValue V1 = N->getOperand(0);
22501 SDValue V2 = N->getOperand(1);
22503 // We require the first shuffle operand to be the SUB node, and the second to
22504 // be the ADD node.
22505 // FIXME: We should support the commuted patterns.
22506 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22509 // If there are other uses of these operations we can't fold them.
22510 if (!V1->hasOneUse() || !V2->hasOneUse())
22513 // Ensure that both operations have the same operands. Note that we can
22514 // commute the FADD operands.
22515 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22516 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22517 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22520 // We're looking for blends between FADD and FSUB nodes. We insist on these
22521 // nodes being lined up in a specific expected pattern.
22522 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22523 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22524 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22527 // Only specific types are legal at this point, assert so we notice if and
22528 // when these change.
22529 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22530 VT == MVT::v4f64) &&
22531 "Unknown vector type encountered!");
22533 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22536 /// PerformShuffleCombine - Performs several different shuffle combines.
22537 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22538 TargetLowering::DAGCombinerInfo &DCI,
22539 const X86Subtarget *Subtarget) {
22541 SDValue N0 = N->getOperand(0);
22542 SDValue N1 = N->getOperand(1);
22543 EVT VT = N->getValueType(0);
22545 // Don't create instructions with illegal types after legalize types has run.
22546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22547 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22550 // If we have legalized the vector types, look for blends of FADD and FSUB
22551 // nodes that we can fuse into an ADDSUB node.
22552 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22553 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22556 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22557 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22558 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22559 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22561 // During Type Legalization, when promoting illegal vector types,
22562 // the backend might introduce new shuffle dag nodes and bitcasts.
22564 // This code performs the following transformation:
22565 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22566 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22568 // We do this only if both the bitcast and the BINOP dag nodes have
22569 // one use. Also, perform this transformation only if the new binary
22570 // operation is legal. This is to avoid introducing dag nodes that
22571 // potentially need to be further expanded (or custom lowered) into a
22572 // less optimal sequence of dag nodes.
22573 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22574 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22575 N0.getOpcode() == ISD::BITCAST) {
22576 SDValue BC0 = N0.getOperand(0);
22577 EVT SVT = BC0.getValueType();
22578 unsigned Opcode = BC0.getOpcode();
22579 unsigned NumElts = VT.getVectorNumElements();
22581 if (BC0.hasOneUse() && SVT.isVector() &&
22582 SVT.getVectorNumElements() * 2 == NumElts &&
22583 TLI.isOperationLegal(Opcode, VT)) {
22584 bool CanFold = false;
22596 unsigned SVTNumElts = SVT.getVectorNumElements();
22597 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22598 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22599 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22600 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22601 CanFold = SVOp->getMaskElt(i) < 0;
22604 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22605 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22606 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22607 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22612 // Only handle 128 wide vector from here on.
22613 if (!VT.is128BitVector())
22616 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22617 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22618 // consecutive, non-overlapping, and in the right order.
22619 SmallVector<SDValue, 16> Elts;
22620 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22621 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22623 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22627 if (isTargetShuffle(N->getOpcode())) {
22629 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22630 if (Shuffle.getNode())
22633 // Try recursively combining arbitrary sequences of x86 shuffle
22634 // instructions into higher-order shuffles. We do this after combining
22635 // specific PSHUF instruction sequences into their minimal form so that we
22636 // can evaluate how many specialized shuffle instructions are involved in
22637 // a particular chain.
22638 SmallVector<int, 1> NonceMask; // Just a placeholder.
22639 NonceMask.push_back(0);
22640 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22641 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22643 return SDValue(); // This routine will use CombineTo to replace N.
22649 /// PerformTruncateCombine - Converts truncate operation to
22650 /// a sequence of vector shuffle operations.
22651 /// It is possible when we truncate 256-bit vector to 128-bit vector
22652 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22653 TargetLowering::DAGCombinerInfo &DCI,
22654 const X86Subtarget *Subtarget) {
22658 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22659 /// specific shuffle of a load can be folded into a single element load.
22660 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22661 /// shuffles have been custom lowered so we need to handle those here.
22662 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22663 TargetLowering::DAGCombinerInfo &DCI) {
22664 if (DCI.isBeforeLegalizeOps())
22667 SDValue InVec = N->getOperand(0);
22668 SDValue EltNo = N->getOperand(1);
22670 if (!isa<ConstantSDNode>(EltNo))
22673 EVT OriginalVT = InVec.getValueType();
22675 if (InVec.getOpcode() == ISD::BITCAST) {
22676 // Don't duplicate a load with other uses.
22677 if (!InVec.hasOneUse())
22679 EVT BCVT = InVec.getOperand(0).getValueType();
22680 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22682 InVec = InVec.getOperand(0);
22685 EVT CurrentVT = InVec.getValueType();
22687 if (!isTargetShuffle(InVec.getOpcode()))
22690 // Don't duplicate a load with other uses.
22691 if (!InVec.hasOneUse())
22694 SmallVector<int, 16> ShuffleMask;
22696 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22697 ShuffleMask, UnaryShuffle))
22700 // Select the input vector, guarding against out of range extract vector.
22701 unsigned NumElems = CurrentVT.getVectorNumElements();
22702 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22703 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22704 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22705 : InVec.getOperand(1);
22707 // If inputs to shuffle are the same for both ops, then allow 2 uses
22708 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22710 if (LdNode.getOpcode() == ISD::BITCAST) {
22711 // Don't duplicate a load with other uses.
22712 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22715 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22716 LdNode = LdNode.getOperand(0);
22719 if (!ISD::isNormalLoad(LdNode.getNode()))
22722 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22724 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22727 EVT EltVT = N->getValueType(0);
22728 // If there's a bitcast before the shuffle, check if the load type and
22729 // alignment is valid.
22730 unsigned Align = LN0->getAlignment();
22731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22732 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22733 EltVT.getTypeForEVT(*DAG.getContext()));
22735 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22738 // All checks match so transform back to vector_shuffle so that DAG combiner
22739 // can finish the job
22742 // Create shuffle node taking into account the case that its a unary shuffle
22743 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22744 : InVec.getOperand(1);
22745 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22746 InVec.getOperand(0), Shuffle,
22748 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22749 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22753 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22754 /// generation and convert it from being a bunch of shuffles and extracts
22755 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22756 /// storing the value and loading scalars back, while for x64 we should
22757 /// use 64-bit extracts and shifts.
22758 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22759 TargetLowering::DAGCombinerInfo &DCI) {
22760 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22761 if (NewOp.getNode())
22764 SDValue InputVector = N->getOperand(0);
22766 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22767 // from mmx to v2i32 has a single usage.
22768 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22769 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22770 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22771 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22772 N->getValueType(0),
22773 InputVector.getNode()->getOperand(0));
22775 // Only operate on vectors of 4 elements, where the alternative shuffling
22776 // gets to be more expensive.
22777 if (InputVector.getValueType() != MVT::v4i32)
22780 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22781 // single use which is a sign-extend or zero-extend, and all elements are
22783 SmallVector<SDNode *, 4> Uses;
22784 unsigned ExtractedElements = 0;
22785 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22786 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22787 if (UI.getUse().getResNo() != InputVector.getResNo())
22790 SDNode *Extract = *UI;
22791 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22794 if (Extract->getValueType(0) != MVT::i32)
22796 if (!Extract->hasOneUse())
22798 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22799 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22801 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22804 // Record which element was extracted.
22805 ExtractedElements |=
22806 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22808 Uses.push_back(Extract);
22811 // If not all the elements were used, this may not be worthwhile.
22812 if (ExtractedElements != 15)
22815 // Ok, we've now decided to do the transformation.
22816 // If 64-bit shifts are legal, use the extract-shift sequence,
22817 // otherwise bounce the vector off the cache.
22818 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22820 SDLoc dl(InputVector);
22822 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22823 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22824 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22825 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22826 DAG.getConstant(0, VecIdxTy));
22827 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22828 DAG.getConstant(1, VecIdxTy));
22830 SDValue ShAmt = DAG.getConstant(32,
22831 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22832 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22833 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22834 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22835 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22836 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22837 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22839 // Store the value to a temporary stack slot.
22840 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22841 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22842 MachinePointerInfo(), false, false, 0);
22844 EVT ElementType = InputVector.getValueType().getVectorElementType();
22845 unsigned EltSize = ElementType.getSizeInBits() / 8;
22847 // Replace each use (extract) with a load of the appropriate element.
22848 for (unsigned i = 0; i < 4; ++i) {
22849 uint64_t Offset = EltSize * i;
22850 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22852 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22853 StackPtr, OffsetVal);
22855 // Load the scalar.
22856 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22857 ScalarAddr, MachinePointerInfo(),
22858 false, false, false, 0);
22863 // Replace the extracts
22864 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22865 UE = Uses.end(); UI != UE; ++UI) {
22866 SDNode *Extract = *UI;
22868 SDValue Idx = Extract->getOperand(1);
22869 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22870 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22873 // The replacement was made in place; don't return anything.
22877 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22878 static std::pair<unsigned, bool>
22879 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22880 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22881 if (!VT.isVector())
22882 return std::make_pair(0, false);
22884 bool NeedSplit = false;
22885 switch (VT.getSimpleVT().SimpleTy) {
22886 default: return std::make_pair(0, false);
22889 if (!Subtarget->hasVLX())
22890 return std::make_pair(0, false);
22894 if (!Subtarget->hasBWI())
22895 return std::make_pair(0, false);
22899 if (!Subtarget->hasAVX512())
22900 return std::make_pair(0, false);
22905 if (!Subtarget->hasAVX2())
22907 if (!Subtarget->hasAVX())
22908 return std::make_pair(0, false);
22913 if (!Subtarget->hasSSE2())
22914 return std::make_pair(0, false);
22917 // SSE2 has only a small subset of the operations.
22918 bool hasUnsigned = Subtarget->hasSSE41() ||
22919 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22920 bool hasSigned = Subtarget->hasSSE41() ||
22921 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22923 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22926 // Check for x CC y ? x : y.
22927 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22928 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22933 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22936 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22939 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22942 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22944 // Check for x CC y ? y : x -- a min/max with reversed arms.
22945 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22946 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22951 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22954 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22957 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22960 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22964 return std::make_pair(Opc, NeedSplit);
22968 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22969 const X86Subtarget *Subtarget) {
22971 SDValue Cond = N->getOperand(0);
22972 SDValue LHS = N->getOperand(1);
22973 SDValue RHS = N->getOperand(2);
22975 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22976 SDValue CondSrc = Cond->getOperand(0);
22977 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22978 Cond = CondSrc->getOperand(0);
22981 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22984 // A vselect where all conditions and data are constants can be optimized into
22985 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22986 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22987 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22990 unsigned MaskValue = 0;
22991 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22994 MVT VT = N->getSimpleValueType(0);
22995 unsigned NumElems = VT.getVectorNumElements();
22996 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22997 for (unsigned i = 0; i < NumElems; ++i) {
22998 // Be sure we emit undef where we can.
22999 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23000 ShuffleMask[i] = -1;
23002 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23005 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23006 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23008 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23011 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23013 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23014 TargetLowering::DAGCombinerInfo &DCI,
23015 const X86Subtarget *Subtarget) {
23017 SDValue Cond = N->getOperand(0);
23018 // Get the LHS/RHS of the select.
23019 SDValue LHS = N->getOperand(1);
23020 SDValue RHS = N->getOperand(2);
23021 EVT VT = LHS.getValueType();
23022 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23024 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23025 // instructions match the semantics of the common C idiom x<y?x:y but not
23026 // x<=y?x:y, because of how they handle negative zero (which can be
23027 // ignored in unsafe-math mode).
23028 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23029 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
23030 (Subtarget->hasSSE2() ||
23031 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23032 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23034 unsigned Opcode = 0;
23035 // Check for x CC y ? x : y.
23036 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23037 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23041 // Converting this to a min would handle NaNs incorrectly, and swapping
23042 // the operands would cause it to handle comparisons between positive
23043 // and negative zero incorrectly.
23044 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23045 if (!DAG.getTarget().Options.UnsafeFPMath &&
23046 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23048 std::swap(LHS, RHS);
23050 Opcode = X86ISD::FMIN;
23053 // Converting this to a min would handle comparisons between positive
23054 // and negative zero incorrectly.
23055 if (!DAG.getTarget().Options.UnsafeFPMath &&
23056 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23058 Opcode = X86ISD::FMIN;
23061 // Converting this to a min would handle both negative zeros and NaNs
23062 // incorrectly, but we can swap the operands to fix both.
23063 std::swap(LHS, RHS);
23067 Opcode = X86ISD::FMIN;
23071 // Converting this to a max would handle comparisons between positive
23072 // and negative zero incorrectly.
23073 if (!DAG.getTarget().Options.UnsafeFPMath &&
23074 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23076 Opcode = X86ISD::FMAX;
23079 // Converting this to a max would handle NaNs incorrectly, and swapping
23080 // the operands would cause it to handle comparisons between positive
23081 // and negative zero incorrectly.
23082 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23083 if (!DAG.getTarget().Options.UnsafeFPMath &&
23084 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23086 std::swap(LHS, RHS);
23088 Opcode = X86ISD::FMAX;
23091 // Converting this to a max would handle both negative zeros and NaNs
23092 // incorrectly, but we can swap the operands to fix both.
23093 std::swap(LHS, RHS);
23097 Opcode = X86ISD::FMAX;
23100 // Check for x CC y ? y : x -- a min/max with reversed arms.
23101 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23102 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23106 // Converting this to a min would handle comparisons between positive
23107 // and negative zero incorrectly, and swapping the operands would
23108 // cause it to handle NaNs incorrectly.
23109 if (!DAG.getTarget().Options.UnsafeFPMath &&
23110 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23111 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23113 std::swap(LHS, RHS);
23115 Opcode = X86ISD::FMIN;
23118 // Converting this to a min would handle NaNs incorrectly.
23119 if (!DAG.getTarget().Options.UnsafeFPMath &&
23120 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23122 Opcode = X86ISD::FMIN;
23125 // Converting this to a min would handle both negative zeros and NaNs
23126 // incorrectly, but we can swap the operands to fix both.
23127 std::swap(LHS, RHS);
23131 Opcode = X86ISD::FMIN;
23135 // Converting this to a max would handle NaNs incorrectly.
23136 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23138 Opcode = X86ISD::FMAX;
23141 // Converting this to a max would handle comparisons between positive
23142 // and negative zero incorrectly, and swapping the operands would
23143 // cause it to handle NaNs incorrectly.
23144 if (!DAG.getTarget().Options.UnsafeFPMath &&
23145 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23146 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23148 std::swap(LHS, RHS);
23150 Opcode = X86ISD::FMAX;
23153 // Converting this to a max would handle both negative zeros and NaNs
23154 // incorrectly, but we can swap the operands to fix both.
23155 std::swap(LHS, RHS);
23159 Opcode = X86ISD::FMAX;
23165 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23168 EVT CondVT = Cond.getValueType();
23169 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23170 CondVT.getVectorElementType() == MVT::i1) {
23171 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23172 // lowering on KNL. In this case we convert it to
23173 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23174 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23175 // Since SKX these selects have a proper lowering.
23176 EVT OpVT = LHS.getValueType();
23177 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23178 (OpVT.getVectorElementType() == MVT::i8 ||
23179 OpVT.getVectorElementType() == MVT::i16) &&
23180 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23181 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23182 DCI.AddToWorklist(Cond.getNode());
23183 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23186 // If this is a select between two integer constants, try to do some
23188 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23189 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23190 // Don't do this for crazy integer types.
23191 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23192 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23193 // so that TrueC (the true value) is larger than FalseC.
23194 bool NeedsCondInvert = false;
23196 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23197 // Efficiently invertible.
23198 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23199 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23200 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23201 NeedsCondInvert = true;
23202 std::swap(TrueC, FalseC);
23205 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23206 if (FalseC->getAPIntValue() == 0 &&
23207 TrueC->getAPIntValue().isPowerOf2()) {
23208 if (NeedsCondInvert) // Invert the condition if needed.
23209 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23210 DAG.getConstant(1, Cond.getValueType()));
23212 // Zero extend the condition if needed.
23213 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23215 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23216 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23217 DAG.getConstant(ShAmt, MVT::i8));
23220 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23221 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23222 if (NeedsCondInvert) // Invert the condition if needed.
23223 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23224 DAG.getConstant(1, Cond.getValueType()));
23226 // Zero extend the condition if needed.
23227 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23228 FalseC->getValueType(0), Cond);
23229 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23230 SDValue(FalseC, 0));
23233 // Optimize cases that will turn into an LEA instruction. This requires
23234 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23235 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23236 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23237 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23239 bool isFastMultiplier = false;
23241 switch ((unsigned char)Diff) {
23243 case 1: // result = add base, cond
23244 case 2: // result = lea base( , cond*2)
23245 case 3: // result = lea base(cond, cond*2)
23246 case 4: // result = lea base( , cond*4)
23247 case 5: // result = lea base(cond, cond*4)
23248 case 8: // result = lea base( , cond*8)
23249 case 9: // result = lea base(cond, cond*8)
23250 isFastMultiplier = true;
23255 if (isFastMultiplier) {
23256 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23257 if (NeedsCondInvert) // Invert the condition if needed.
23258 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23259 DAG.getConstant(1, Cond.getValueType()));
23261 // Zero extend the condition if needed.
23262 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23264 // Scale the condition by the difference.
23266 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23267 DAG.getConstant(Diff, Cond.getValueType()));
23269 // Add the base if non-zero.
23270 if (FalseC->getAPIntValue() != 0)
23271 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23272 SDValue(FalseC, 0));
23279 // Canonicalize max and min:
23280 // (x > y) ? x : y -> (x >= y) ? x : y
23281 // (x < y) ? x : y -> (x <= y) ? x : y
23282 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23283 // the need for an extra compare
23284 // against zero. e.g.
23285 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23287 // testl %edi, %edi
23289 // cmovgl %edi, %eax
23293 // cmovsl %eax, %edi
23294 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23295 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23296 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23297 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23302 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23303 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23304 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23305 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23310 // Early exit check
23311 if (!TLI.isTypeLegal(VT))
23314 // Match VSELECTs into subs with unsigned saturation.
23315 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23316 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23317 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23318 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23319 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23321 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23322 // left side invert the predicate to simplify logic below.
23324 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23326 CC = ISD::getSetCCInverse(CC, true);
23327 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23331 if (Other.getNode() && Other->getNumOperands() == 2 &&
23332 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23333 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23334 SDValue CondRHS = Cond->getOperand(1);
23336 // Look for a general sub with unsigned saturation first.
23337 // x >= y ? x-y : 0 --> subus x, y
23338 // x > y ? x-y : 0 --> subus x, y
23339 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23340 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23341 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23343 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23344 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23345 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23346 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23347 // If the RHS is a constant we have to reverse the const
23348 // canonicalization.
23349 // x > C-1 ? x+-C : 0 --> subus x, C
23350 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23351 CondRHSConst->getAPIntValue() ==
23352 (-OpRHSConst->getAPIntValue() - 1))
23353 return DAG.getNode(
23354 X86ISD::SUBUS, DL, VT, OpLHS,
23355 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23357 // Another special case: If C was a sign bit, the sub has been
23358 // canonicalized into a xor.
23359 // FIXME: Would it be better to use computeKnownBits to determine
23360 // whether it's safe to decanonicalize the xor?
23361 // x s< 0 ? x^C : 0 --> subus x, C
23362 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23363 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23364 OpRHSConst->getAPIntValue().isSignBit())
23365 // Note that we have to rebuild the RHS constant here to ensure we
23366 // don't rely on particular values of undef lanes.
23367 return DAG.getNode(
23368 X86ISD::SUBUS, DL, VT, OpLHS,
23369 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23374 // Try to match a min/max vector operation.
23375 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23376 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23377 unsigned Opc = ret.first;
23378 bool NeedSplit = ret.second;
23380 if (Opc && NeedSplit) {
23381 unsigned NumElems = VT.getVectorNumElements();
23382 // Extract the LHS vectors
23383 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23384 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23386 // Extract the RHS vectors
23387 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23388 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23390 // Create min/max for each subvector
23391 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23392 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23394 // Merge the result
23395 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23397 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23400 // Simplify vector selection if condition value type matches vselect
23402 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23403 assert(Cond.getValueType().isVector() &&
23404 "vector select expects a vector selector!");
23406 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23407 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23409 // Try invert the condition if true value is not all 1s and false value
23411 if (!TValIsAllOnes && !FValIsAllZeros &&
23412 // Check if the selector will be produced by CMPP*/PCMP*
23413 Cond.getOpcode() == ISD::SETCC &&
23414 // Check if SETCC has already been promoted
23415 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23416 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23417 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23419 if (TValIsAllZeros || FValIsAllOnes) {
23420 SDValue CC = Cond.getOperand(2);
23421 ISD::CondCode NewCC =
23422 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23423 Cond.getOperand(0).getValueType().isInteger());
23424 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23425 std::swap(LHS, RHS);
23426 TValIsAllOnes = FValIsAllOnes;
23427 FValIsAllZeros = TValIsAllZeros;
23431 if (TValIsAllOnes || FValIsAllZeros) {
23434 if (TValIsAllOnes && FValIsAllZeros)
23436 else if (TValIsAllOnes)
23437 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23438 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23439 else if (FValIsAllZeros)
23440 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23441 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23443 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23447 // If we know that this node is legal then we know that it is going to be
23448 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23449 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23450 // to simplify previous instructions.
23451 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23452 !DCI.isBeforeLegalize() &&
23453 // We explicitly check against v8i16 and v16i16 because, although
23454 // they're marked as Custom, they might only be legal when Cond is a
23455 // build_vector of constants. This will be taken care in a later
23457 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23458 VT != MVT::v8i16) &&
23459 // Don't optimize vector of constants. Those are handled by
23460 // the generic code and all the bits must be properly set for
23461 // the generic optimizer.
23462 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23463 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23465 // Don't optimize vector selects that map to mask-registers.
23469 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23470 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23472 APInt KnownZero, KnownOne;
23473 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23474 DCI.isBeforeLegalizeOps());
23475 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23476 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23478 // If we changed the computation somewhere in the DAG, this change
23479 // will affect all users of Cond.
23480 // Make sure it is fine and update all the nodes so that we do not
23481 // use the generic VSELECT anymore. Otherwise, we may perform
23482 // wrong optimizations as we messed up with the actual expectation
23483 // for the vector boolean values.
23484 if (Cond != TLO.Old) {
23485 // Check all uses of that condition operand to check whether it will be
23486 // consumed by non-BLEND instructions, which may depend on all bits are
23488 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23490 if (I->getOpcode() != ISD::VSELECT)
23491 // TODO: Add other opcodes eventually lowered into BLEND.
23494 // Update all the users of the condition, before committing the change,
23495 // so that the VSELECT optimizations that expect the correct vector
23496 // boolean value will not be triggered.
23497 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23499 DAG.ReplaceAllUsesOfValueWith(
23501 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23502 Cond, I->getOperand(1), I->getOperand(2)));
23503 DCI.CommitTargetLoweringOpt(TLO);
23506 // At this point, only Cond is changed. Change the condition
23507 // just for N to keep the opportunity to optimize all other
23508 // users their own way.
23509 DAG.ReplaceAllUsesOfValueWith(
23511 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23512 TLO.New, N->getOperand(1), N->getOperand(2)));
23517 // We should generate an X86ISD::BLENDI from a vselect if its argument
23518 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23519 // constants. This specific pattern gets generated when we split a
23520 // selector for a 512 bit vector in a machine without AVX512 (but with
23521 // 256-bit vectors), during legalization:
23523 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23525 // Iff we find this pattern and the build_vectors are built from
23526 // constants, we translate the vselect into a shuffle_vector that we
23527 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23528 if ((N->getOpcode() == ISD::VSELECT ||
23529 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23530 !DCI.isBeforeLegalize()) {
23531 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23532 if (Shuffle.getNode())
23539 // Check whether a boolean test is testing a boolean value generated by
23540 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23543 // Simplify the following patterns:
23544 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23545 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23546 // to (Op EFLAGS Cond)
23548 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23549 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23550 // to (Op EFLAGS !Cond)
23552 // where Op could be BRCOND or CMOV.
23554 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23555 // Quit if not CMP and SUB with its value result used.
23556 if (Cmp.getOpcode() != X86ISD::CMP &&
23557 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23560 // Quit if not used as a boolean value.
23561 if (CC != X86::COND_E && CC != X86::COND_NE)
23564 // Check CMP operands. One of them should be 0 or 1 and the other should be
23565 // an SetCC or extended from it.
23566 SDValue Op1 = Cmp.getOperand(0);
23567 SDValue Op2 = Cmp.getOperand(1);
23570 const ConstantSDNode* C = nullptr;
23571 bool needOppositeCond = (CC == X86::COND_E);
23572 bool checkAgainstTrue = false; // Is it a comparison against 1?
23574 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23576 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23578 else // Quit if all operands are not constants.
23581 if (C->getZExtValue() == 1) {
23582 needOppositeCond = !needOppositeCond;
23583 checkAgainstTrue = true;
23584 } else if (C->getZExtValue() != 0)
23585 // Quit if the constant is neither 0 or 1.
23588 bool truncatedToBoolWithAnd = false;
23589 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23590 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23591 SetCC.getOpcode() == ISD::TRUNCATE ||
23592 SetCC.getOpcode() == ISD::AND) {
23593 if (SetCC.getOpcode() == ISD::AND) {
23595 ConstantSDNode *CS;
23596 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23597 CS->getZExtValue() == 1)
23599 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23600 CS->getZExtValue() == 1)
23604 SetCC = SetCC.getOperand(OpIdx);
23605 truncatedToBoolWithAnd = true;
23607 SetCC = SetCC.getOperand(0);
23610 switch (SetCC.getOpcode()) {
23611 case X86ISD::SETCC_CARRY:
23612 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23613 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23614 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23615 // truncated to i1 using 'and'.
23616 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23618 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23619 "Invalid use of SETCC_CARRY!");
23621 case X86ISD::SETCC:
23622 // Set the condition code or opposite one if necessary.
23623 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23624 if (needOppositeCond)
23625 CC = X86::GetOppositeBranchCondition(CC);
23626 return SetCC.getOperand(1);
23627 case X86ISD::CMOV: {
23628 // Check whether false/true value has canonical one, i.e. 0 or 1.
23629 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23630 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23631 // Quit if true value is not a constant.
23634 // Quit if false value is not a constant.
23636 SDValue Op = SetCC.getOperand(0);
23637 // Skip 'zext' or 'trunc' node.
23638 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23639 Op.getOpcode() == ISD::TRUNCATE)
23640 Op = Op.getOperand(0);
23641 // A special case for rdrand/rdseed, where 0 is set if false cond is
23643 if ((Op.getOpcode() != X86ISD::RDRAND &&
23644 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23647 // Quit if false value is not the constant 0 or 1.
23648 bool FValIsFalse = true;
23649 if (FVal && FVal->getZExtValue() != 0) {
23650 if (FVal->getZExtValue() != 1)
23652 // If FVal is 1, opposite cond is needed.
23653 needOppositeCond = !needOppositeCond;
23654 FValIsFalse = false;
23656 // Quit if TVal is not the constant opposite of FVal.
23657 if (FValIsFalse && TVal->getZExtValue() != 1)
23659 if (!FValIsFalse && TVal->getZExtValue() != 0)
23661 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23662 if (needOppositeCond)
23663 CC = X86::GetOppositeBranchCondition(CC);
23664 return SetCC.getOperand(3);
23671 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23672 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23673 TargetLowering::DAGCombinerInfo &DCI,
23674 const X86Subtarget *Subtarget) {
23677 // If the flag operand isn't dead, don't touch this CMOV.
23678 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23681 SDValue FalseOp = N->getOperand(0);
23682 SDValue TrueOp = N->getOperand(1);
23683 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23684 SDValue Cond = N->getOperand(3);
23686 if (CC == X86::COND_E || CC == X86::COND_NE) {
23687 switch (Cond.getOpcode()) {
23691 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23692 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23693 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23699 Flags = checkBoolTestSetCCCombine(Cond, CC);
23700 if (Flags.getNode() &&
23701 // Extra check as FCMOV only supports a subset of X86 cond.
23702 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23703 SDValue Ops[] = { FalseOp, TrueOp,
23704 DAG.getConstant(CC, MVT::i8), Flags };
23705 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23708 // If this is a select between two integer constants, try to do some
23709 // optimizations. Note that the operands are ordered the opposite of SELECT
23711 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23712 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23713 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23714 // larger than FalseC (the false value).
23715 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23716 CC = X86::GetOppositeBranchCondition(CC);
23717 std::swap(TrueC, FalseC);
23718 std::swap(TrueOp, FalseOp);
23721 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23722 // This is efficient for any integer data type (including i8/i16) and
23724 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23725 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23726 DAG.getConstant(CC, MVT::i8), Cond);
23728 // Zero extend the condition if needed.
23729 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23731 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23732 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23733 DAG.getConstant(ShAmt, MVT::i8));
23734 if (N->getNumValues() == 2) // Dead flag value?
23735 return DCI.CombineTo(N, Cond, SDValue());
23739 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23740 // for any integer data type, including i8/i16.
23741 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23742 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23743 DAG.getConstant(CC, MVT::i8), Cond);
23745 // Zero extend the condition if needed.
23746 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23747 FalseC->getValueType(0), Cond);
23748 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23749 SDValue(FalseC, 0));
23751 if (N->getNumValues() == 2) // Dead flag value?
23752 return DCI.CombineTo(N, Cond, SDValue());
23756 // Optimize cases that will turn into an LEA instruction. This requires
23757 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23758 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23759 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23760 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23762 bool isFastMultiplier = false;
23764 switch ((unsigned char)Diff) {
23766 case 1: // result = add base, cond
23767 case 2: // result = lea base( , cond*2)
23768 case 3: // result = lea base(cond, cond*2)
23769 case 4: // result = lea base( , cond*4)
23770 case 5: // result = lea base(cond, cond*4)
23771 case 8: // result = lea base( , cond*8)
23772 case 9: // result = lea base(cond, cond*8)
23773 isFastMultiplier = true;
23778 if (isFastMultiplier) {
23779 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23780 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23781 DAG.getConstant(CC, MVT::i8), Cond);
23782 // Zero extend the condition if needed.
23783 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23785 // Scale the condition by the difference.
23787 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23788 DAG.getConstant(Diff, Cond.getValueType()));
23790 // Add the base if non-zero.
23791 if (FalseC->getAPIntValue() != 0)
23792 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23793 SDValue(FalseC, 0));
23794 if (N->getNumValues() == 2) // Dead flag value?
23795 return DCI.CombineTo(N, Cond, SDValue());
23802 // Handle these cases:
23803 // (select (x != c), e, c) -> select (x != c), e, x),
23804 // (select (x == c), c, e) -> select (x == c), x, e)
23805 // where the c is an integer constant, and the "select" is the combination
23806 // of CMOV and CMP.
23808 // The rationale for this change is that the conditional-move from a constant
23809 // needs two instructions, however, conditional-move from a register needs
23810 // only one instruction.
23812 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23813 // some instruction-combining opportunities. This opt needs to be
23814 // postponed as late as possible.
23816 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23817 // the DCI.xxxx conditions are provided to postpone the optimization as
23818 // late as possible.
23820 ConstantSDNode *CmpAgainst = nullptr;
23821 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23822 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23823 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23825 if (CC == X86::COND_NE &&
23826 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23827 CC = X86::GetOppositeBranchCondition(CC);
23828 std::swap(TrueOp, FalseOp);
23831 if (CC == X86::COND_E &&
23832 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23833 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23834 DAG.getConstant(CC, MVT::i8), Cond };
23835 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23843 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23844 const X86Subtarget *Subtarget) {
23845 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23847 default: return SDValue();
23848 // SSE/AVX/AVX2 blend intrinsics.
23849 case Intrinsic::x86_avx2_pblendvb:
23850 case Intrinsic::x86_avx2_pblendw:
23851 case Intrinsic::x86_avx2_pblendd_128:
23852 case Intrinsic::x86_avx2_pblendd_256:
23853 // Don't try to simplify this intrinsic if we don't have AVX2.
23854 if (!Subtarget->hasAVX2())
23857 case Intrinsic::x86_avx_blend_pd_256:
23858 case Intrinsic::x86_avx_blend_ps_256:
23859 case Intrinsic::x86_avx_blendv_pd_256:
23860 case Intrinsic::x86_avx_blendv_ps_256:
23861 // Don't try to simplify this intrinsic if we don't have AVX.
23862 if (!Subtarget->hasAVX())
23865 case Intrinsic::x86_sse41_pblendw:
23866 case Intrinsic::x86_sse41_blendpd:
23867 case Intrinsic::x86_sse41_blendps:
23868 case Intrinsic::x86_sse41_blendvps:
23869 case Intrinsic::x86_sse41_blendvpd:
23870 case Intrinsic::x86_sse41_pblendvb: {
23871 SDValue Op0 = N->getOperand(1);
23872 SDValue Op1 = N->getOperand(2);
23873 SDValue Mask = N->getOperand(3);
23875 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23876 if (!Subtarget->hasSSE41())
23879 // fold (blend A, A, Mask) -> A
23882 // fold (blend A, B, allZeros) -> A
23883 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23885 // fold (blend A, B, allOnes) -> B
23886 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23889 // Simplify the case where the mask is a constant i32 value.
23890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23891 if (C->isNullValue())
23893 if (C->isAllOnesValue())
23900 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23901 case Intrinsic::x86_sse2_psrai_w:
23902 case Intrinsic::x86_sse2_psrai_d:
23903 case Intrinsic::x86_avx2_psrai_w:
23904 case Intrinsic::x86_avx2_psrai_d:
23905 case Intrinsic::x86_sse2_psra_w:
23906 case Intrinsic::x86_sse2_psra_d:
23907 case Intrinsic::x86_avx2_psra_w:
23908 case Intrinsic::x86_avx2_psra_d: {
23909 SDValue Op0 = N->getOperand(1);
23910 SDValue Op1 = N->getOperand(2);
23911 EVT VT = Op0.getValueType();
23912 assert(VT.isVector() && "Expected a vector type!");
23914 if (isa<BuildVectorSDNode>(Op1))
23915 Op1 = Op1.getOperand(0);
23917 if (!isa<ConstantSDNode>(Op1))
23920 EVT SVT = VT.getVectorElementType();
23921 unsigned SVTBits = SVT.getSizeInBits();
23923 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23924 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23925 uint64_t ShAmt = C.getZExtValue();
23927 // Don't try to convert this shift into a ISD::SRA if the shift
23928 // count is bigger than or equal to the element size.
23929 if (ShAmt >= SVTBits)
23932 // Trivial case: if the shift count is zero, then fold this
23933 // into the first operand.
23937 // Replace this packed shift intrinsic with a target independent
23939 SDValue Splat = DAG.getConstant(C, VT);
23940 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23945 /// PerformMulCombine - Optimize a single multiply with constant into two
23946 /// in order to implement it with two cheaper instructions, e.g.
23947 /// LEA + SHL, LEA + LEA.
23948 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23949 TargetLowering::DAGCombinerInfo &DCI) {
23950 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23953 EVT VT = N->getValueType(0);
23954 if (VT != MVT::i64)
23957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23960 uint64_t MulAmt = C->getZExtValue();
23961 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23964 uint64_t MulAmt1 = 0;
23965 uint64_t MulAmt2 = 0;
23966 if ((MulAmt % 9) == 0) {
23968 MulAmt2 = MulAmt / 9;
23969 } else if ((MulAmt % 5) == 0) {
23971 MulAmt2 = MulAmt / 5;
23972 } else if ((MulAmt % 3) == 0) {
23974 MulAmt2 = MulAmt / 3;
23977 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23980 if (isPowerOf2_64(MulAmt2) &&
23981 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23982 // If second multiplifer is pow2, issue it first. We want the multiply by
23983 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23985 std::swap(MulAmt1, MulAmt2);
23988 if (isPowerOf2_64(MulAmt1))
23989 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23990 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23992 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23993 DAG.getConstant(MulAmt1, VT));
23995 if (isPowerOf2_64(MulAmt2))
23996 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23997 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23999 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24000 DAG.getConstant(MulAmt2, VT));
24002 // Do not add new nodes to DAG combiner worklist.
24003 DCI.CombineTo(N, NewMul, false);
24008 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24009 SDValue N0 = N->getOperand(0);
24010 SDValue N1 = N->getOperand(1);
24011 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24012 EVT VT = N0.getValueType();
24014 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24015 // since the result of setcc_c is all zero's or all ones.
24016 if (VT.isInteger() && !VT.isVector() &&
24017 N1C && N0.getOpcode() == ISD::AND &&
24018 N0.getOperand(1).getOpcode() == ISD::Constant) {
24019 SDValue N00 = N0.getOperand(0);
24020 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
24021 ((N00.getOpcode() == ISD::ANY_EXTEND ||
24022 N00.getOpcode() == ISD::ZERO_EXTEND) &&
24023 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
24024 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24025 APInt ShAmt = N1C->getAPIntValue();
24026 Mask = Mask.shl(ShAmt);
24028 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24029 N00, DAG.getConstant(Mask, VT));
24033 // Hardware support for vector shifts is sparse which makes us scalarize the
24034 // vector operations in many cases. Also, on sandybridge ADD is faster than
24036 // (shl V, 1) -> add V,V
24037 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24038 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24039 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24040 // We shift all of the values by one. In many cases we do not have
24041 // hardware support for this operation. This is better expressed as an ADD
24043 if (N1SplatC->getZExtValue() == 1)
24044 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24050 /// \brief Returns a vector of 0s if the node in input is a vector logical
24051 /// shift by a constant amount which is known to be bigger than or equal
24052 /// to the vector element size in bits.
24053 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24054 const X86Subtarget *Subtarget) {
24055 EVT VT = N->getValueType(0);
24057 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24058 (!Subtarget->hasInt256() ||
24059 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24062 SDValue Amt = N->getOperand(1);
24064 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24065 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24066 APInt ShiftAmt = AmtSplat->getAPIntValue();
24067 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24069 // SSE2/AVX2 logical shifts always return a vector of 0s
24070 // if the shift amount is bigger than or equal to
24071 // the element size. The constant shift amount will be
24072 // encoded as a 8-bit immediate.
24073 if (ShiftAmt.trunc(8).uge(MaxAmount))
24074 return getZeroVector(VT, Subtarget, DAG, DL);
24080 /// PerformShiftCombine - Combine shifts.
24081 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24082 TargetLowering::DAGCombinerInfo &DCI,
24083 const X86Subtarget *Subtarget) {
24084 if (N->getOpcode() == ISD::SHL) {
24085 SDValue V = PerformSHLCombine(N, DAG);
24086 if (V.getNode()) return V;
24089 if (N->getOpcode() != ISD::SRA) {
24090 // Try to fold this logical shift into a zero vector.
24091 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24092 if (V.getNode()) return V;
24098 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24099 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24100 // and friends. Likewise for OR -> CMPNEQSS.
24101 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24102 TargetLowering::DAGCombinerInfo &DCI,
24103 const X86Subtarget *Subtarget) {
24106 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24107 // we're requiring SSE2 for both.
24108 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24109 SDValue N0 = N->getOperand(0);
24110 SDValue N1 = N->getOperand(1);
24111 SDValue CMP0 = N0->getOperand(1);
24112 SDValue CMP1 = N1->getOperand(1);
24115 // The SETCCs should both refer to the same CMP.
24116 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24119 SDValue CMP00 = CMP0->getOperand(0);
24120 SDValue CMP01 = CMP0->getOperand(1);
24121 EVT VT = CMP00.getValueType();
24123 if (VT == MVT::f32 || VT == MVT::f64) {
24124 bool ExpectingFlags = false;
24125 // Check for any users that want flags:
24126 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24127 !ExpectingFlags && UI != UE; ++UI)
24128 switch (UI->getOpcode()) {
24133 ExpectingFlags = true;
24135 case ISD::CopyToReg:
24136 case ISD::SIGN_EXTEND:
24137 case ISD::ZERO_EXTEND:
24138 case ISD::ANY_EXTEND:
24142 if (!ExpectingFlags) {
24143 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24144 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24146 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24147 X86::CondCode tmp = cc0;
24152 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24153 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24154 // FIXME: need symbolic constants for these magic numbers.
24155 // See X86ATTInstPrinter.cpp:printSSECC().
24156 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24157 if (Subtarget->hasAVX512()) {
24158 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24159 CMP01, DAG.getConstant(x86cc, MVT::i8));
24160 if (N->getValueType(0) != MVT::i1)
24161 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24165 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24166 CMP00.getValueType(), CMP00, CMP01,
24167 DAG.getConstant(x86cc, MVT::i8));
24169 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24170 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24172 if (is64BitFP && !Subtarget->is64Bit()) {
24173 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24174 // 64-bit integer, since that's not a legal type. Since
24175 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24176 // bits, but can do this little dance to extract the lowest 32 bits
24177 // and work with those going forward.
24178 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24180 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24182 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24183 Vector32, DAG.getIntPtrConstant(0));
24187 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24188 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24189 DAG.getConstant(1, IntVT));
24190 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24191 return OneBitOfTruth;
24199 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24200 /// so it can be folded inside ANDNP.
24201 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24202 EVT VT = N->getValueType(0);
24204 // Match direct AllOnes for 128 and 256-bit vectors
24205 if (ISD::isBuildVectorAllOnes(N))
24208 // Look through a bit convert.
24209 if (N->getOpcode() == ISD::BITCAST)
24210 N = N->getOperand(0).getNode();
24212 // Sometimes the operand may come from a insert_subvector building a 256-bit
24214 if (VT.is256BitVector() &&
24215 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24216 SDValue V1 = N->getOperand(0);
24217 SDValue V2 = N->getOperand(1);
24219 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24220 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24221 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24222 ISD::isBuildVectorAllOnes(V2.getNode()))
24229 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24230 // register. In most cases we actually compare or select YMM-sized registers
24231 // and mixing the two types creates horrible code. This method optimizes
24232 // some of the transition sequences.
24233 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24234 TargetLowering::DAGCombinerInfo &DCI,
24235 const X86Subtarget *Subtarget) {
24236 EVT VT = N->getValueType(0);
24237 if (!VT.is256BitVector())
24240 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24241 N->getOpcode() == ISD::ZERO_EXTEND ||
24242 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24244 SDValue Narrow = N->getOperand(0);
24245 EVT NarrowVT = Narrow->getValueType(0);
24246 if (!NarrowVT.is128BitVector())
24249 if (Narrow->getOpcode() != ISD::XOR &&
24250 Narrow->getOpcode() != ISD::AND &&
24251 Narrow->getOpcode() != ISD::OR)
24254 SDValue N0 = Narrow->getOperand(0);
24255 SDValue N1 = Narrow->getOperand(1);
24258 // The Left side has to be a trunc.
24259 if (N0.getOpcode() != ISD::TRUNCATE)
24262 // The type of the truncated inputs.
24263 EVT WideVT = N0->getOperand(0)->getValueType(0);
24267 // The right side has to be a 'trunc' or a constant vector.
24268 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24269 ConstantSDNode *RHSConstSplat = nullptr;
24270 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24271 RHSConstSplat = RHSBV->getConstantSplatNode();
24272 if (!RHSTrunc && !RHSConstSplat)
24275 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24277 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24280 // Set N0 and N1 to hold the inputs to the new wide operation.
24281 N0 = N0->getOperand(0);
24282 if (RHSConstSplat) {
24283 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24284 SDValue(RHSConstSplat, 0));
24285 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24286 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24287 } else if (RHSTrunc) {
24288 N1 = N1->getOperand(0);
24291 // Generate the wide operation.
24292 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24293 unsigned Opcode = N->getOpcode();
24295 case ISD::ANY_EXTEND:
24297 case ISD::ZERO_EXTEND: {
24298 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24299 APInt Mask = APInt::getAllOnesValue(InBits);
24300 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24301 return DAG.getNode(ISD::AND, DL, VT,
24302 Op, DAG.getConstant(Mask, VT));
24304 case ISD::SIGN_EXTEND:
24305 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24306 Op, DAG.getValueType(NarrowVT));
24308 llvm_unreachable("Unexpected opcode");
24312 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24313 TargetLowering::DAGCombinerInfo &DCI,
24314 const X86Subtarget *Subtarget) {
24315 EVT VT = N->getValueType(0);
24316 if (DCI.isBeforeLegalizeOps())
24319 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24323 // Create BEXTR instructions
24324 // BEXTR is ((X >> imm) & (2**size-1))
24325 if (VT == MVT::i32 || VT == MVT::i64) {
24326 SDValue N0 = N->getOperand(0);
24327 SDValue N1 = N->getOperand(1);
24330 // Check for BEXTR.
24331 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24332 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24333 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24334 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24335 if (MaskNode && ShiftNode) {
24336 uint64_t Mask = MaskNode->getZExtValue();
24337 uint64_t Shift = ShiftNode->getZExtValue();
24338 if (isMask_64(Mask)) {
24339 uint64_t MaskSize = CountPopulation_64(Mask);
24340 if (Shift + MaskSize <= VT.getSizeInBits())
24341 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24342 DAG.getConstant(Shift | (MaskSize << 8), VT));
24350 // Want to form ANDNP nodes:
24351 // 1) In the hopes of then easily combining them with OR and AND nodes
24352 // to form PBLEND/PSIGN.
24353 // 2) To match ANDN packed intrinsics
24354 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24357 SDValue N0 = N->getOperand(0);
24358 SDValue N1 = N->getOperand(1);
24361 // Check LHS for vnot
24362 if (N0.getOpcode() == ISD::XOR &&
24363 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24364 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24365 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24367 // Check RHS for vnot
24368 if (N1.getOpcode() == ISD::XOR &&
24369 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24370 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24371 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24376 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24377 TargetLowering::DAGCombinerInfo &DCI,
24378 const X86Subtarget *Subtarget) {
24379 if (DCI.isBeforeLegalizeOps())
24382 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24386 SDValue N0 = N->getOperand(0);
24387 SDValue N1 = N->getOperand(1);
24388 EVT VT = N->getValueType(0);
24390 // look for psign/blend
24391 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24392 if (!Subtarget->hasSSSE3() ||
24393 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24396 // Canonicalize pandn to RHS
24397 if (N0.getOpcode() == X86ISD::ANDNP)
24399 // or (and (m, y), (pandn m, x))
24400 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24401 SDValue Mask = N1.getOperand(0);
24402 SDValue X = N1.getOperand(1);
24404 if (N0.getOperand(0) == Mask)
24405 Y = N0.getOperand(1);
24406 if (N0.getOperand(1) == Mask)
24407 Y = N0.getOperand(0);
24409 // Check to see if the mask appeared in both the AND and ANDNP and
24413 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24414 // Look through mask bitcast.
24415 if (Mask.getOpcode() == ISD::BITCAST)
24416 Mask = Mask.getOperand(0);
24417 if (X.getOpcode() == ISD::BITCAST)
24418 X = X.getOperand(0);
24419 if (Y.getOpcode() == ISD::BITCAST)
24420 Y = Y.getOperand(0);
24422 EVT MaskVT = Mask.getValueType();
24424 // Validate that the Mask operand is a vector sra node.
24425 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24426 // there is no psrai.b
24427 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24428 unsigned SraAmt = ~0;
24429 if (Mask.getOpcode() == ISD::SRA) {
24430 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24431 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24432 SraAmt = AmtConst->getZExtValue();
24433 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24434 SDValue SraC = Mask.getOperand(1);
24435 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24437 if ((SraAmt + 1) != EltBits)
24442 // Now we know we at least have a plendvb with the mask val. See if
24443 // we can form a psignb/w/d.
24444 // psign = x.type == y.type == mask.type && y = sub(0, x);
24445 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24446 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24447 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24448 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24449 "Unsupported VT for PSIGN");
24450 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24451 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24453 // PBLENDVB only available on SSE 4.1
24454 if (!Subtarget->hasSSE41())
24457 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24459 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24460 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24461 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24462 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24463 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24467 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24470 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24471 MachineFunction &MF = DAG.getMachineFunction();
24472 bool OptForSize = MF.getFunction()->getAttributes().
24473 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24475 // SHLD/SHRD instructions have lower register pressure, but on some
24476 // platforms they have higher latency than the equivalent
24477 // series of shifts/or that would otherwise be generated.
24478 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24479 // have higher latencies and we are not optimizing for size.
24480 if (!OptForSize && Subtarget->isSHLDSlow())
24483 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24485 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24487 if (!N0.hasOneUse() || !N1.hasOneUse())
24490 SDValue ShAmt0 = N0.getOperand(1);
24491 if (ShAmt0.getValueType() != MVT::i8)
24493 SDValue ShAmt1 = N1.getOperand(1);
24494 if (ShAmt1.getValueType() != MVT::i8)
24496 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24497 ShAmt0 = ShAmt0.getOperand(0);
24498 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24499 ShAmt1 = ShAmt1.getOperand(0);
24502 unsigned Opc = X86ISD::SHLD;
24503 SDValue Op0 = N0.getOperand(0);
24504 SDValue Op1 = N1.getOperand(0);
24505 if (ShAmt0.getOpcode() == ISD::SUB) {
24506 Opc = X86ISD::SHRD;
24507 std::swap(Op0, Op1);
24508 std::swap(ShAmt0, ShAmt1);
24511 unsigned Bits = VT.getSizeInBits();
24512 if (ShAmt1.getOpcode() == ISD::SUB) {
24513 SDValue Sum = ShAmt1.getOperand(0);
24514 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24515 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24516 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24517 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24518 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24519 return DAG.getNode(Opc, DL, VT,
24521 DAG.getNode(ISD::TRUNCATE, DL,
24524 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24525 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24527 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24528 return DAG.getNode(Opc, DL, VT,
24529 N0.getOperand(0), N1.getOperand(0),
24530 DAG.getNode(ISD::TRUNCATE, DL,
24537 // Generate NEG and CMOV for integer abs.
24538 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24539 EVT VT = N->getValueType(0);
24541 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24542 // 8-bit integer abs to NEG and CMOV.
24543 if (VT.isInteger() && VT.getSizeInBits() == 8)
24546 SDValue N0 = N->getOperand(0);
24547 SDValue N1 = N->getOperand(1);
24550 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24551 // and change it to SUB and CMOV.
24552 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24553 N0.getOpcode() == ISD::ADD &&
24554 N0.getOperand(1) == N1 &&
24555 N1.getOpcode() == ISD::SRA &&
24556 N1.getOperand(0) == N0.getOperand(0))
24557 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24558 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24559 // Generate SUB & CMOV.
24560 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24561 DAG.getConstant(0, VT), N0.getOperand(0));
24563 SDValue Ops[] = { N0.getOperand(0), Neg,
24564 DAG.getConstant(X86::COND_GE, MVT::i8),
24565 SDValue(Neg.getNode(), 1) };
24566 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24571 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24572 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24573 TargetLowering::DAGCombinerInfo &DCI,
24574 const X86Subtarget *Subtarget) {
24575 if (DCI.isBeforeLegalizeOps())
24578 if (Subtarget->hasCMov()) {
24579 SDValue RV = performIntegerAbsCombine(N, DAG);
24587 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24588 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24589 TargetLowering::DAGCombinerInfo &DCI,
24590 const X86Subtarget *Subtarget) {
24591 LoadSDNode *Ld = cast<LoadSDNode>(N);
24592 EVT RegVT = Ld->getValueType(0);
24593 EVT MemVT = Ld->getMemoryVT();
24595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24597 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24598 // into two 16-byte operations.
24599 ISD::LoadExtType Ext = Ld->getExtensionType();
24600 unsigned Alignment = Ld->getAlignment();
24601 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24602 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24603 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24604 unsigned NumElems = RegVT.getVectorNumElements();
24608 SDValue Ptr = Ld->getBasePtr();
24609 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24611 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24613 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24614 Ld->getPointerInfo(), Ld->isVolatile(),
24615 Ld->isNonTemporal(), Ld->isInvariant(),
24617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24618 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24619 Ld->getPointerInfo(), Ld->isVolatile(),
24620 Ld->isNonTemporal(), Ld->isInvariant(),
24621 std::min(16U, Alignment));
24622 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24624 Load2.getValue(1));
24626 SDValue NewVec = DAG.getUNDEF(RegVT);
24627 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24628 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24629 return DCI.CombineTo(N, NewVec, TF, true);
24635 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24636 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24637 const X86Subtarget *Subtarget) {
24638 StoreSDNode *St = cast<StoreSDNode>(N);
24639 EVT VT = St->getValue().getValueType();
24640 EVT StVT = St->getMemoryVT();
24642 SDValue StoredVal = St->getOperand(1);
24643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24645 // If we are saving a concatenation of two XMM registers and 32-byte stores
24646 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24647 unsigned Alignment = St->getAlignment();
24648 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24649 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24650 StVT == VT && !IsAligned) {
24651 unsigned NumElems = VT.getVectorNumElements();
24655 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24656 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24658 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24659 SDValue Ptr0 = St->getBasePtr();
24660 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24662 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24663 St->getPointerInfo(), St->isVolatile(),
24664 St->isNonTemporal(), Alignment);
24665 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24666 St->getPointerInfo(), St->isVolatile(),
24667 St->isNonTemporal(),
24668 std::min(16U, Alignment));
24669 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24672 // Optimize trunc store (of multiple scalars) to shuffle and store.
24673 // First, pack all of the elements in one place. Next, store to memory
24674 // in fewer chunks.
24675 if (St->isTruncatingStore() && VT.isVector()) {
24676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24677 unsigned NumElems = VT.getVectorNumElements();
24678 assert(StVT != VT && "Cannot truncate to the same type");
24679 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24680 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24682 // From, To sizes and ElemCount must be pow of two
24683 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24684 // We are going to use the original vector elt for storing.
24685 // Accumulated smaller vector elements must be a multiple of the store size.
24686 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24688 unsigned SizeRatio = FromSz / ToSz;
24690 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24692 // Create a type on which we perform the shuffle
24693 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24694 StVT.getScalarType(), NumElems*SizeRatio);
24696 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24698 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24699 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24700 for (unsigned i = 0; i != NumElems; ++i)
24701 ShuffleVec[i] = i * SizeRatio;
24703 // Can't shuffle using an illegal type.
24704 if (!TLI.isTypeLegal(WideVecVT))
24707 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24708 DAG.getUNDEF(WideVecVT),
24710 // At this point all of the data is stored at the bottom of the
24711 // register. We now need to save it to mem.
24713 // Find the largest store unit
24714 MVT StoreType = MVT::i8;
24715 for (MVT Tp : MVT::integer_valuetypes()) {
24716 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24720 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24721 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24722 (64 <= NumElems * ToSz))
24723 StoreType = MVT::f64;
24725 // Bitcast the original vector into a vector of store-size units
24726 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24727 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24728 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24729 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24730 SmallVector<SDValue, 8> Chains;
24731 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24732 TLI.getPointerTy());
24733 SDValue Ptr = St->getBasePtr();
24735 // Perform one or more big stores into memory.
24736 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24737 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24738 StoreType, ShuffWide,
24739 DAG.getIntPtrConstant(i));
24740 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24741 St->getPointerInfo(), St->isVolatile(),
24742 St->isNonTemporal(), St->getAlignment());
24743 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24744 Chains.push_back(Ch);
24747 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24750 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24751 // the FP state in cases where an emms may be missing.
24752 // A preferable solution to the general problem is to figure out the right
24753 // places to insert EMMS. This qualifies as a quick hack.
24755 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24756 if (VT.getSizeInBits() != 64)
24759 const Function *F = DAG.getMachineFunction().getFunction();
24760 bool NoImplicitFloatOps = F->getAttributes().
24761 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24762 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24763 && Subtarget->hasSSE2();
24764 if ((VT.isVector() ||
24765 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24766 isa<LoadSDNode>(St->getValue()) &&
24767 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24768 St->getChain().hasOneUse() && !St->isVolatile()) {
24769 SDNode* LdVal = St->getValue().getNode();
24770 LoadSDNode *Ld = nullptr;
24771 int TokenFactorIndex = -1;
24772 SmallVector<SDValue, 8> Ops;
24773 SDNode* ChainVal = St->getChain().getNode();
24774 // Must be a store of a load. We currently handle two cases: the load
24775 // is a direct child, and it's under an intervening TokenFactor. It is
24776 // possible to dig deeper under nested TokenFactors.
24777 if (ChainVal == LdVal)
24778 Ld = cast<LoadSDNode>(St->getChain());
24779 else if (St->getValue().hasOneUse() &&
24780 ChainVal->getOpcode() == ISD::TokenFactor) {
24781 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24782 if (ChainVal->getOperand(i).getNode() == LdVal) {
24783 TokenFactorIndex = i;
24784 Ld = cast<LoadSDNode>(St->getValue());
24786 Ops.push_back(ChainVal->getOperand(i));
24790 if (!Ld || !ISD::isNormalLoad(Ld))
24793 // If this is not the MMX case, i.e. we are just turning i64 load/store
24794 // into f64 load/store, avoid the transformation if there are multiple
24795 // uses of the loaded value.
24796 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24801 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24802 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24804 if (Subtarget->is64Bit() || F64IsLegal) {
24805 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24806 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24807 Ld->getPointerInfo(), Ld->isVolatile(),
24808 Ld->isNonTemporal(), Ld->isInvariant(),
24809 Ld->getAlignment());
24810 SDValue NewChain = NewLd.getValue(1);
24811 if (TokenFactorIndex != -1) {
24812 Ops.push_back(NewChain);
24813 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24815 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24816 St->getPointerInfo(),
24817 St->isVolatile(), St->isNonTemporal(),
24818 St->getAlignment());
24821 // Otherwise, lower to two pairs of 32-bit loads / stores.
24822 SDValue LoAddr = Ld->getBasePtr();
24823 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24824 DAG.getConstant(4, MVT::i32));
24826 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24827 Ld->getPointerInfo(),
24828 Ld->isVolatile(), Ld->isNonTemporal(),
24829 Ld->isInvariant(), Ld->getAlignment());
24830 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24831 Ld->getPointerInfo().getWithOffset(4),
24832 Ld->isVolatile(), Ld->isNonTemporal(),
24834 MinAlign(Ld->getAlignment(), 4));
24836 SDValue NewChain = LoLd.getValue(1);
24837 if (TokenFactorIndex != -1) {
24838 Ops.push_back(LoLd);
24839 Ops.push_back(HiLd);
24840 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24843 LoAddr = St->getBasePtr();
24844 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24845 DAG.getConstant(4, MVT::i32));
24847 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24848 St->getPointerInfo(),
24849 St->isVolatile(), St->isNonTemporal(),
24850 St->getAlignment());
24851 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24852 St->getPointerInfo().getWithOffset(4),
24854 St->isNonTemporal(),
24855 MinAlign(St->getAlignment(), 4));
24856 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24861 /// Return 'true' if this vector operation is "horizontal"
24862 /// and return the operands for the horizontal operation in LHS and RHS. A
24863 /// horizontal operation performs the binary operation on successive elements
24864 /// of its first operand, then on successive elements of its second operand,
24865 /// returning the resulting values in a vector. For example, if
24866 /// A = < float a0, float a1, float a2, float a3 >
24868 /// B = < float b0, float b1, float b2, float b3 >
24869 /// then the result of doing a horizontal operation on A and B is
24870 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24871 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24872 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24873 /// set to A, RHS to B, and the routine returns 'true'.
24874 /// Note that the binary operation should have the property that if one of the
24875 /// operands is UNDEF then the result is UNDEF.
24876 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24877 // Look for the following pattern: if
24878 // A = < float a0, float a1, float a2, float a3 >
24879 // B = < float b0, float b1, float b2, float b3 >
24881 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24882 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24883 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24884 // which is A horizontal-op B.
24886 // At least one of the operands should be a vector shuffle.
24887 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24888 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24891 MVT VT = LHS.getSimpleValueType();
24893 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24894 "Unsupported vector type for horizontal add/sub");
24896 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24897 // operate independently on 128-bit lanes.
24898 unsigned NumElts = VT.getVectorNumElements();
24899 unsigned NumLanes = VT.getSizeInBits()/128;
24900 unsigned NumLaneElts = NumElts / NumLanes;
24901 assert((NumLaneElts % 2 == 0) &&
24902 "Vector type should have an even number of elements in each lane");
24903 unsigned HalfLaneElts = NumLaneElts/2;
24905 // View LHS in the form
24906 // LHS = VECTOR_SHUFFLE A, B, LMask
24907 // If LHS is not a shuffle then pretend it is the shuffle
24908 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24909 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24912 SmallVector<int, 16> LMask(NumElts);
24913 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24914 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24915 A = LHS.getOperand(0);
24916 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24917 B = LHS.getOperand(1);
24918 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24919 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24921 if (LHS.getOpcode() != ISD::UNDEF)
24923 for (unsigned i = 0; i != NumElts; ++i)
24927 // Likewise, view RHS in the form
24928 // RHS = VECTOR_SHUFFLE C, D, RMask
24930 SmallVector<int, 16> RMask(NumElts);
24931 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24932 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24933 C = RHS.getOperand(0);
24934 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24935 D = RHS.getOperand(1);
24936 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24937 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24939 if (RHS.getOpcode() != ISD::UNDEF)
24941 for (unsigned i = 0; i != NumElts; ++i)
24945 // Check that the shuffles are both shuffling the same vectors.
24946 if (!(A == C && B == D) && !(A == D && B == C))
24949 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24950 if (!A.getNode() && !B.getNode())
24953 // If A and B occur in reverse order in RHS, then "swap" them (which means
24954 // rewriting the mask).
24956 CommuteVectorShuffleMask(RMask, NumElts);
24958 // At this point LHS and RHS are equivalent to
24959 // LHS = VECTOR_SHUFFLE A, B, LMask
24960 // RHS = VECTOR_SHUFFLE A, B, RMask
24961 // Check that the masks correspond to performing a horizontal operation.
24962 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24963 for (unsigned i = 0; i != NumLaneElts; ++i) {
24964 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24966 // Ignore any UNDEF components.
24967 if (LIdx < 0 || RIdx < 0 ||
24968 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24969 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24972 // Check that successive elements are being operated on. If not, this is
24973 // not a horizontal operation.
24974 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24975 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24976 if (!(LIdx == Index && RIdx == Index + 1) &&
24977 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24982 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24983 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24987 /// Do target-specific dag combines on floating point adds.
24988 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24989 const X86Subtarget *Subtarget) {
24990 EVT VT = N->getValueType(0);
24991 SDValue LHS = N->getOperand(0);
24992 SDValue RHS = N->getOperand(1);
24994 // Try to synthesize horizontal adds from adds of shuffles.
24995 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24996 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24997 isHorizontalBinOp(LHS, RHS, true))
24998 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25002 /// Do target-specific dag combines on floating point subs.
25003 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25004 const X86Subtarget *Subtarget) {
25005 EVT VT = N->getValueType(0);
25006 SDValue LHS = N->getOperand(0);
25007 SDValue RHS = N->getOperand(1);
25009 // Try to synthesize horizontal subs from subs of shuffles.
25010 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25011 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25012 isHorizontalBinOp(LHS, RHS, false))
25013 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25017 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25018 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25019 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25020 // F[X]OR(0.0, x) -> x
25021 // F[X]OR(x, 0.0) -> x
25022 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25023 if (C->getValueAPF().isPosZero())
25024 return N->getOperand(1);
25025 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25026 if (C->getValueAPF().isPosZero())
25027 return N->getOperand(0);
25031 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25032 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25033 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25035 // Only perform optimizations if UnsafeMath is used.
25036 if (!DAG.getTarget().Options.UnsafeFPMath)
25039 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25040 // into FMINC and FMAXC, which are Commutative operations.
25041 unsigned NewOp = 0;
25042 switch (N->getOpcode()) {
25043 default: llvm_unreachable("unknown opcode");
25044 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25045 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25048 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25049 N->getOperand(0), N->getOperand(1));
25052 /// Do target-specific dag combines on X86ISD::FAND nodes.
25053 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25054 // FAND(0.0, x) -> 0.0
25055 // FAND(x, 0.0) -> 0.0
25056 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25057 if (C->getValueAPF().isPosZero())
25058 return N->getOperand(0);
25059 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25060 if (C->getValueAPF().isPosZero())
25061 return N->getOperand(1);
25065 /// Do target-specific dag combines on X86ISD::FANDN nodes
25066 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25067 // FANDN(x, 0.0) -> 0.0
25068 // FANDN(0.0, x) -> x
25069 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25070 if (C->getValueAPF().isPosZero())
25071 return N->getOperand(1);
25072 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25073 if (C->getValueAPF().isPosZero())
25074 return N->getOperand(1);
25078 static SDValue PerformBTCombine(SDNode *N,
25080 TargetLowering::DAGCombinerInfo &DCI) {
25081 // BT ignores high bits in the bit index operand.
25082 SDValue Op1 = N->getOperand(1);
25083 if (Op1.hasOneUse()) {
25084 unsigned BitWidth = Op1.getValueSizeInBits();
25085 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25086 APInt KnownZero, KnownOne;
25087 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25088 !DCI.isBeforeLegalizeOps());
25089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25090 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25091 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25092 DCI.CommitTargetLoweringOpt(TLO);
25097 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25098 SDValue Op = N->getOperand(0);
25099 if (Op.getOpcode() == ISD::BITCAST)
25100 Op = Op.getOperand(0);
25101 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25102 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25103 VT.getVectorElementType().getSizeInBits() ==
25104 OpVT.getVectorElementType().getSizeInBits()) {
25105 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25110 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25111 const X86Subtarget *Subtarget) {
25112 EVT VT = N->getValueType(0);
25113 if (!VT.isVector())
25116 SDValue N0 = N->getOperand(0);
25117 SDValue N1 = N->getOperand(1);
25118 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25121 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25122 // both SSE and AVX2 since there is no sign-extended shift right
25123 // operation on a vector with 64-bit elements.
25124 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25125 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25126 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25127 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25128 SDValue N00 = N0.getOperand(0);
25130 // EXTLOAD has a better solution on AVX2,
25131 // it may be replaced with X86ISD::VSEXT node.
25132 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25133 if (!ISD::isNormalLoad(N00.getNode()))
25136 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25137 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25139 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25145 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25146 TargetLowering::DAGCombinerInfo &DCI,
25147 const X86Subtarget *Subtarget) {
25148 SDValue N0 = N->getOperand(0);
25149 EVT VT = N->getValueType(0);
25151 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25152 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25153 // This exposes the sext to the sdivrem lowering, so that it directly extends
25154 // from AH (which we otherwise need to do contortions to access).
25155 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25156 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25158 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25159 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25160 N0.getOperand(0), N0.getOperand(1));
25161 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25162 return R.getValue(1);
25165 if (!DCI.isBeforeLegalizeOps())
25168 if (!Subtarget->hasFp256())
25171 if (VT.isVector() && VT.getSizeInBits() == 256) {
25172 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25180 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25181 const X86Subtarget* Subtarget) {
25183 EVT VT = N->getValueType(0);
25185 // Let legalize expand this if it isn't a legal type yet.
25186 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25189 EVT ScalarVT = VT.getScalarType();
25190 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25191 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25194 SDValue A = N->getOperand(0);
25195 SDValue B = N->getOperand(1);
25196 SDValue C = N->getOperand(2);
25198 bool NegA = (A.getOpcode() == ISD::FNEG);
25199 bool NegB = (B.getOpcode() == ISD::FNEG);
25200 bool NegC = (C.getOpcode() == ISD::FNEG);
25202 // Negative multiplication when NegA xor NegB
25203 bool NegMul = (NegA != NegB);
25205 A = A.getOperand(0);
25207 B = B.getOperand(0);
25209 C = C.getOperand(0);
25213 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25215 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25217 return DAG.getNode(Opcode, dl, VT, A, B, C);
25220 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25221 TargetLowering::DAGCombinerInfo &DCI,
25222 const X86Subtarget *Subtarget) {
25223 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25224 // (and (i32 x86isd::setcc_carry), 1)
25225 // This eliminates the zext. This transformation is necessary because
25226 // ISD::SETCC is always legalized to i8.
25228 SDValue N0 = N->getOperand(0);
25229 EVT VT = N->getValueType(0);
25231 if (N0.getOpcode() == ISD::AND &&
25233 N0.getOperand(0).hasOneUse()) {
25234 SDValue N00 = N0.getOperand(0);
25235 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25237 if (!C || C->getZExtValue() != 1)
25239 return DAG.getNode(ISD::AND, dl, VT,
25240 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25241 N00.getOperand(0), N00.getOperand(1)),
25242 DAG.getConstant(1, VT));
25246 if (N0.getOpcode() == ISD::TRUNCATE &&
25248 N0.getOperand(0).hasOneUse()) {
25249 SDValue N00 = N0.getOperand(0);
25250 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25251 return DAG.getNode(ISD::AND, dl, VT,
25252 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25253 N00.getOperand(0), N00.getOperand(1)),
25254 DAG.getConstant(1, VT));
25257 if (VT.is256BitVector()) {
25258 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25263 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25264 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25265 // This exposes the zext to the udivrem lowering, so that it directly extends
25266 // from AH (which we otherwise need to do contortions to access).
25267 if (N0.getOpcode() == ISD::UDIVREM &&
25268 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25269 (VT == MVT::i32 || VT == MVT::i64)) {
25270 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25271 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25272 N0.getOperand(0), N0.getOperand(1));
25273 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25274 return R.getValue(1);
25280 // Optimize x == -y --> x+y == 0
25281 // x != -y --> x+y != 0
25282 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25283 const X86Subtarget* Subtarget) {
25284 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25285 SDValue LHS = N->getOperand(0);
25286 SDValue RHS = N->getOperand(1);
25287 EVT VT = N->getValueType(0);
25290 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25292 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25293 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25294 LHS.getValueType(), RHS, LHS.getOperand(1));
25295 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25296 addV, DAG.getConstant(0, addV.getValueType()), CC);
25298 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25300 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25301 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25302 RHS.getValueType(), LHS, RHS.getOperand(1));
25303 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25304 addV, DAG.getConstant(0, addV.getValueType()), CC);
25307 if (VT.getScalarType() == MVT::i1) {
25308 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25309 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25310 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25311 if (!IsSEXT0 && !IsVZero0)
25313 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25314 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25315 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25317 if (!IsSEXT1 && !IsVZero1)
25320 if (IsSEXT0 && IsVZero1) {
25321 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25322 if (CC == ISD::SETEQ)
25323 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25324 return LHS.getOperand(0);
25326 if (IsSEXT1 && IsVZero0) {
25327 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25328 if (CC == ISD::SETEQ)
25329 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25330 return RHS.getOperand(0);
25337 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25338 const X86Subtarget *Subtarget) {
25340 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25341 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25342 "X86insertps is only defined for v4x32");
25344 SDValue Ld = N->getOperand(1);
25345 if (MayFoldLoad(Ld)) {
25346 // Extract the countS bits from the immediate so we can get the proper
25347 // address when narrowing the vector load to a specific element.
25348 // When the second source op is a memory address, interps doesn't use
25349 // countS and just gets an f32 from that address.
25350 unsigned DestIndex =
25351 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25352 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25356 // Create this as a scalar to vector to match the instruction pattern.
25357 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25358 // countS bits are ignored when loading from memory on insertps, which
25359 // means we don't need to explicitly set them to 0.
25360 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25361 LoadScalarToVector, N->getOperand(2));
25364 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25365 // as "sbb reg,reg", since it can be extended without zext and produces
25366 // an all-ones bit which is more useful than 0/1 in some cases.
25367 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25370 return DAG.getNode(ISD::AND, DL, VT,
25371 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25372 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25373 DAG.getConstant(1, VT));
25374 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25375 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25376 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25377 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25380 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25381 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25382 TargetLowering::DAGCombinerInfo &DCI,
25383 const X86Subtarget *Subtarget) {
25385 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25386 SDValue EFLAGS = N->getOperand(1);
25388 if (CC == X86::COND_A) {
25389 // Try to convert COND_A into COND_B in an attempt to facilitate
25390 // materializing "setb reg".
25392 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25393 // cannot take an immediate as its first operand.
25395 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25396 EFLAGS.getValueType().isInteger() &&
25397 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25398 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25399 EFLAGS.getNode()->getVTList(),
25400 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25401 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25402 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25406 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25407 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25409 if (CC == X86::COND_B)
25410 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25414 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25415 if (Flags.getNode()) {
25416 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25417 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25423 // Optimize branch condition evaluation.
25425 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25426 TargetLowering::DAGCombinerInfo &DCI,
25427 const X86Subtarget *Subtarget) {
25429 SDValue Chain = N->getOperand(0);
25430 SDValue Dest = N->getOperand(1);
25431 SDValue EFLAGS = N->getOperand(3);
25432 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25436 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25437 if (Flags.getNode()) {
25438 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25439 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25446 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25447 SelectionDAG &DAG) {
25448 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25449 // optimize away operation when it's from a constant.
25451 // The general transformation is:
25452 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25453 // AND(VECTOR_CMP(x,y), constant2)
25454 // constant2 = UNARYOP(constant)
25456 // Early exit if this isn't a vector operation, the operand of the
25457 // unary operation isn't a bitwise AND, or if the sizes of the operations
25458 // aren't the same.
25459 EVT VT = N->getValueType(0);
25460 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25461 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25462 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25465 // Now check that the other operand of the AND is a constant. We could
25466 // make the transformation for non-constant splats as well, but it's unclear
25467 // that would be a benefit as it would not eliminate any operations, just
25468 // perform one more step in scalar code before moving to the vector unit.
25469 if (BuildVectorSDNode *BV =
25470 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25471 // Bail out if the vector isn't a constant.
25472 if (!BV->isConstant())
25475 // Everything checks out. Build up the new and improved node.
25477 EVT IntVT = BV->getValueType(0);
25478 // Create a new constant of the appropriate type for the transformed
25480 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25481 // The AND node needs bitcasts to/from an integer vector type around it.
25482 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25483 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25484 N->getOperand(0)->getOperand(0), MaskConst);
25485 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25492 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25493 const X86TargetLowering *XTLI) {
25494 // First try to optimize away the conversion entirely when it's
25495 // conditionally from a constant. Vectors only.
25496 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25497 if (Res != SDValue())
25500 // Now move on to more general possibilities.
25501 SDValue Op0 = N->getOperand(0);
25502 EVT InVT = Op0->getValueType(0);
25504 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25505 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25507 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25508 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25509 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25512 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25513 // a 32-bit target where SSE doesn't support i64->FP operations.
25514 if (Op0.getOpcode() == ISD::LOAD) {
25515 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25516 EVT VT = Ld->getValueType(0);
25517 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25518 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25519 !XTLI->getSubtarget()->is64Bit() &&
25521 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25522 Ld->getChain(), Op0, DAG);
25523 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25530 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25531 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25532 X86TargetLowering::DAGCombinerInfo &DCI) {
25533 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25534 // the result is either zero or one (depending on the input carry bit).
25535 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25536 if (X86::isZeroNode(N->getOperand(0)) &&
25537 X86::isZeroNode(N->getOperand(1)) &&
25538 // We don't have a good way to replace an EFLAGS use, so only do this when
25540 SDValue(N, 1).use_empty()) {
25542 EVT VT = N->getValueType(0);
25543 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25544 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25545 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25546 DAG.getConstant(X86::COND_B,MVT::i8),
25548 DAG.getConstant(1, VT));
25549 return DCI.CombineTo(N, Res1, CarryOut);
25555 // fold (add Y, (sete X, 0)) -> adc 0, Y
25556 // (add Y, (setne X, 0)) -> sbb -1, Y
25557 // (sub (sete X, 0), Y) -> sbb 0, Y
25558 // (sub (setne X, 0), Y) -> adc -1, Y
25559 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25562 // Look through ZExts.
25563 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25564 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25567 SDValue SetCC = Ext.getOperand(0);
25568 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25571 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25572 if (CC != X86::COND_E && CC != X86::COND_NE)
25575 SDValue Cmp = SetCC.getOperand(1);
25576 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25577 !X86::isZeroNode(Cmp.getOperand(1)) ||
25578 !Cmp.getOperand(0).getValueType().isInteger())
25581 SDValue CmpOp0 = Cmp.getOperand(0);
25582 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25583 DAG.getConstant(1, CmpOp0.getValueType()));
25585 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25586 if (CC == X86::COND_NE)
25587 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25588 DL, OtherVal.getValueType(), OtherVal,
25589 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25590 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25591 DL, OtherVal.getValueType(), OtherVal,
25592 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25595 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25596 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25597 const X86Subtarget *Subtarget) {
25598 EVT VT = N->getValueType(0);
25599 SDValue Op0 = N->getOperand(0);
25600 SDValue Op1 = N->getOperand(1);
25602 // Try to synthesize horizontal adds from adds of shuffles.
25603 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25604 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25605 isHorizontalBinOp(Op0, Op1, true))
25606 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25608 return OptimizeConditionalInDecrement(N, DAG);
25611 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25612 const X86Subtarget *Subtarget) {
25613 SDValue Op0 = N->getOperand(0);
25614 SDValue Op1 = N->getOperand(1);
25616 // X86 can't encode an immediate LHS of a sub. See if we can push the
25617 // negation into a preceding instruction.
25618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25619 // If the RHS of the sub is a XOR with one use and a constant, invert the
25620 // immediate. Then add one to the LHS of the sub so we can turn
25621 // X-Y -> X+~Y+1, saving one register.
25622 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25623 isa<ConstantSDNode>(Op1.getOperand(1))) {
25624 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25625 EVT VT = Op0.getValueType();
25626 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25628 DAG.getConstant(~XorC, VT));
25629 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25630 DAG.getConstant(C->getAPIntValue()+1, VT));
25634 // Try to synthesize horizontal adds from adds of shuffles.
25635 EVT VT = N->getValueType(0);
25636 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25637 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25638 isHorizontalBinOp(Op0, Op1, true))
25639 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25641 return OptimizeConditionalInDecrement(N, DAG);
25644 /// performVZEXTCombine - Performs build vector combines
25645 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25646 TargetLowering::DAGCombinerInfo &DCI,
25647 const X86Subtarget *Subtarget) {
25649 MVT VT = N->getSimpleValueType(0);
25650 SDValue Op = N->getOperand(0);
25651 MVT OpVT = Op.getSimpleValueType();
25652 MVT OpEltVT = OpVT.getVectorElementType();
25653 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25655 // (vzext (bitcast (vzext (x)) -> (vzext x)
25657 while (V.getOpcode() == ISD::BITCAST)
25658 V = V.getOperand(0);
25660 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25661 MVT InnerVT = V.getSimpleValueType();
25662 MVT InnerEltVT = InnerVT.getVectorElementType();
25664 // If the element sizes match exactly, we can just do one larger vzext. This
25665 // is always an exact type match as vzext operates on integer types.
25666 if (OpEltVT == InnerEltVT) {
25667 assert(OpVT == InnerVT && "Types must match for vzext!");
25668 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25671 // The only other way we can combine them is if only a single element of the
25672 // inner vzext is used in the input to the outer vzext.
25673 if (InnerEltVT.getSizeInBits() < InputBits)
25676 // In this case, the inner vzext is completely dead because we're going to
25677 // only look at bits inside of the low element. Just do the outer vzext on
25678 // a bitcast of the input to the inner.
25679 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25680 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25683 // Check if we can bypass extracting and re-inserting an element of an input
25684 // vector. Essentialy:
25685 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25686 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25687 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25688 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25689 SDValue ExtractedV = V.getOperand(0);
25690 SDValue OrigV = ExtractedV.getOperand(0);
25691 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25692 if (ExtractIdx->getZExtValue() == 0) {
25693 MVT OrigVT = OrigV.getSimpleValueType();
25694 // Extract a subvector if necessary...
25695 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25696 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25697 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25698 OrigVT.getVectorNumElements() / Ratio);
25699 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25700 DAG.getIntPtrConstant(0));
25702 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25703 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25710 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25711 DAGCombinerInfo &DCI) const {
25712 SelectionDAG &DAG = DCI.DAG;
25713 switch (N->getOpcode()) {
25715 case ISD::EXTRACT_VECTOR_ELT:
25716 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25719 case X86ISD::SHRUNKBLEND:
25720 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25721 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25722 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25723 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25724 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25725 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25728 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25729 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25730 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25731 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25732 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25733 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25734 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25735 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25736 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25738 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25740 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25741 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25742 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25743 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25744 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25745 case ISD::ANY_EXTEND:
25746 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25747 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25748 case ISD::SIGN_EXTEND_INREG:
25749 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25750 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25751 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25752 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25753 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25754 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25755 case X86ISD::SHUFP: // Handle all target specific shuffles
25756 case X86ISD::PALIGNR:
25757 case X86ISD::UNPCKH:
25758 case X86ISD::UNPCKL:
25759 case X86ISD::MOVHLPS:
25760 case X86ISD::MOVLHPS:
25761 case X86ISD::PSHUFB:
25762 case X86ISD::PSHUFD:
25763 case X86ISD::PSHUFHW:
25764 case X86ISD::PSHUFLW:
25765 case X86ISD::MOVSS:
25766 case X86ISD::MOVSD:
25767 case X86ISD::VPERMILPI:
25768 case X86ISD::VPERM2X128:
25769 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25770 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25771 case ISD::INTRINSIC_WO_CHAIN:
25772 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25773 case X86ISD::INSERTPS:
25774 return PerformINSERTPSCombine(N, DAG, Subtarget);
25775 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25781 /// isTypeDesirableForOp - Return true if the target has native support for
25782 /// the specified value type and it is 'desirable' to use the type for the
25783 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25784 /// instruction encodings are longer and some i16 instructions are slow.
25785 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25786 if (!isTypeLegal(VT))
25788 if (VT != MVT::i16)
25795 case ISD::SIGN_EXTEND:
25796 case ISD::ZERO_EXTEND:
25797 case ISD::ANY_EXTEND:
25810 /// IsDesirableToPromoteOp - This method query the target whether it is
25811 /// beneficial for dag combiner to promote the specified node. If true, it
25812 /// should return the desired promotion type by reference.
25813 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25814 EVT VT = Op.getValueType();
25815 if (VT != MVT::i16)
25818 bool Promote = false;
25819 bool Commute = false;
25820 switch (Op.getOpcode()) {
25823 LoadSDNode *LD = cast<LoadSDNode>(Op);
25824 // If the non-extending load has a single use and it's not live out, then it
25825 // might be folded.
25826 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25827 Op.hasOneUse()*/) {
25828 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25829 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25830 // The only case where we'd want to promote LOAD (rather then it being
25831 // promoted as an operand is when it's only use is liveout.
25832 if (UI->getOpcode() != ISD::CopyToReg)
25839 case ISD::SIGN_EXTEND:
25840 case ISD::ZERO_EXTEND:
25841 case ISD::ANY_EXTEND:
25846 SDValue N0 = Op.getOperand(0);
25847 // Look out for (store (shl (load), x)).
25848 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25861 SDValue N0 = Op.getOperand(0);
25862 SDValue N1 = Op.getOperand(1);
25863 if (!Commute && MayFoldLoad(N1))
25865 // Avoid disabling potential load folding opportunities.
25866 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25868 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25878 //===----------------------------------------------------------------------===//
25879 // X86 Inline Assembly Support
25880 //===----------------------------------------------------------------------===//
25883 // Helper to match a string separated by whitespace.
25884 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25885 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25887 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25888 StringRef piece(*args[i]);
25889 if (!s.startswith(piece)) // Check if the piece matches.
25892 s = s.substr(piece.size());
25893 StringRef::size_type pos = s.find_first_not_of(" \t");
25894 if (pos == 0) // We matched a prefix.
25902 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25905 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25907 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25908 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25909 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25910 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25912 if (AsmPieces.size() == 3)
25914 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25921 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25922 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25924 std::string AsmStr = IA->getAsmString();
25926 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25927 if (!Ty || Ty->getBitWidth() % 16 != 0)
25930 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25931 SmallVector<StringRef, 4> AsmPieces;
25932 SplitString(AsmStr, AsmPieces, ";\n");
25934 switch (AsmPieces.size()) {
25935 default: return false;
25937 // FIXME: this should verify that we are targeting a 486 or better. If not,
25938 // we will turn this bswap into something that will be lowered to logical
25939 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25940 // lower so don't worry about this.
25942 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25943 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25944 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25945 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25946 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25947 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25948 // No need to check constraints, nothing other than the equivalent of
25949 // "=r,0" would be valid here.
25950 return IntrinsicLowering::LowerToByteSwap(CI);
25953 // rorw $$8, ${0:w} --> llvm.bswap.i16
25954 if (CI->getType()->isIntegerTy(16) &&
25955 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25956 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25957 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25959 const std::string &ConstraintsStr = IA->getConstraintString();
25960 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25961 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25962 if (clobbersFlagRegisters(AsmPieces))
25963 return IntrinsicLowering::LowerToByteSwap(CI);
25967 if (CI->getType()->isIntegerTy(32) &&
25968 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25969 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25970 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25971 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25973 const std::string &ConstraintsStr = IA->getConstraintString();
25974 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25975 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25976 if (clobbersFlagRegisters(AsmPieces))
25977 return IntrinsicLowering::LowerToByteSwap(CI);
25980 if (CI->getType()->isIntegerTy(64)) {
25981 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25982 if (Constraints.size() >= 2 &&
25983 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25984 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25985 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25986 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25987 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25988 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25989 return IntrinsicLowering::LowerToByteSwap(CI);
25997 /// getConstraintType - Given a constraint letter, return the type of
25998 /// constraint it is for this target.
25999 X86TargetLowering::ConstraintType
26000 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
26001 if (Constraint.size() == 1) {
26002 switch (Constraint[0]) {
26013 return C_RegisterClass;
26037 return TargetLowering::getConstraintType(Constraint);
26040 /// Examine constraint type and operand type and determine a weight value.
26041 /// This object must already have been set up with the operand type
26042 /// and the current alternative constraint selected.
26043 TargetLowering::ConstraintWeight
26044 X86TargetLowering::getSingleConstraintMatchWeight(
26045 AsmOperandInfo &info, const char *constraint) const {
26046 ConstraintWeight weight = CW_Invalid;
26047 Value *CallOperandVal = info.CallOperandVal;
26048 // If we don't have a value, we can't do a match,
26049 // but allow it at the lowest weight.
26050 if (!CallOperandVal)
26052 Type *type = CallOperandVal->getType();
26053 // Look at the constraint type.
26054 switch (*constraint) {
26056 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26067 if (CallOperandVal->getType()->isIntegerTy())
26068 weight = CW_SpecificReg;
26073 if (type->isFloatingPointTy())
26074 weight = CW_SpecificReg;
26077 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26078 weight = CW_SpecificReg;
26082 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26083 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26084 weight = CW_Register;
26087 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26088 if (C->getZExtValue() <= 31)
26089 weight = CW_Constant;
26093 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26094 if (C->getZExtValue() <= 63)
26095 weight = CW_Constant;
26099 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26100 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26101 weight = CW_Constant;
26105 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26106 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26107 weight = CW_Constant;
26111 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26112 if (C->getZExtValue() <= 3)
26113 weight = CW_Constant;
26117 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26118 if (C->getZExtValue() <= 0xff)
26119 weight = CW_Constant;
26124 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26125 weight = CW_Constant;
26129 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26130 if ((C->getSExtValue() >= -0x80000000LL) &&
26131 (C->getSExtValue() <= 0x7fffffffLL))
26132 weight = CW_Constant;
26136 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26137 if (C->getZExtValue() <= 0xffffffff)
26138 weight = CW_Constant;
26145 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26146 /// with another that has more specific requirements based on the type of the
26147 /// corresponding operand.
26148 const char *X86TargetLowering::
26149 LowerXConstraint(EVT ConstraintVT) const {
26150 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26151 // 'f' like normal targets.
26152 if (ConstraintVT.isFloatingPoint()) {
26153 if (Subtarget->hasSSE2())
26155 if (Subtarget->hasSSE1())
26159 return TargetLowering::LowerXConstraint(ConstraintVT);
26162 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26163 /// vector. If it is invalid, don't add anything to Ops.
26164 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26165 std::string &Constraint,
26166 std::vector<SDValue>&Ops,
26167 SelectionDAG &DAG) const {
26170 // Only support length 1 constraints for now.
26171 if (Constraint.length() > 1) return;
26173 char ConstraintLetter = Constraint[0];
26174 switch (ConstraintLetter) {
26177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26178 if (C->getZExtValue() <= 31) {
26179 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26185 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26186 if (C->getZExtValue() <= 63) {
26187 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26193 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26194 if (isInt<8>(C->getSExtValue())) {
26195 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26202 if (C->getZExtValue() <= 255) {
26203 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26209 // 32-bit signed value
26210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26211 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26212 C->getSExtValue())) {
26213 // Widen to 64 bits here to get it sign extended.
26214 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26217 // FIXME gcc accepts some relocatable values here too, but only in certain
26218 // memory models; it's complicated.
26223 // 32-bit unsigned value
26224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26225 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26226 C->getZExtValue())) {
26227 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26231 // FIXME gcc accepts some relocatable values here too, but only in certain
26232 // memory models; it's complicated.
26236 // Literal immediates are always ok.
26237 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26238 // Widen to 64 bits here to get it sign extended.
26239 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26243 // In any sort of PIC mode addresses need to be computed at runtime by
26244 // adding in a register or some sort of table lookup. These can't
26245 // be used as immediates.
26246 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26249 // If we are in non-pic codegen mode, we allow the address of a global (with
26250 // an optional displacement) to be used with 'i'.
26251 GlobalAddressSDNode *GA = nullptr;
26252 int64_t Offset = 0;
26254 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26256 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26257 Offset += GA->getOffset();
26259 } else if (Op.getOpcode() == ISD::ADD) {
26260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26261 Offset += C->getZExtValue();
26262 Op = Op.getOperand(0);
26265 } else if (Op.getOpcode() == ISD::SUB) {
26266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26267 Offset += -C->getZExtValue();
26268 Op = Op.getOperand(0);
26273 // Otherwise, this isn't something we can handle, reject it.
26277 const GlobalValue *GV = GA->getGlobal();
26278 // If we require an extra load to get this address, as in PIC mode, we
26279 // can't accept it.
26280 if (isGlobalStubReference(
26281 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26284 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26285 GA->getValueType(0), Offset);
26290 if (Result.getNode()) {
26291 Ops.push_back(Result);
26294 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26297 std::pair<unsigned, const TargetRegisterClass*>
26298 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26300 // First, see if this is a constraint that directly corresponds to an LLVM
26302 if (Constraint.size() == 1) {
26303 // GCC Constraint Letters
26304 switch (Constraint[0]) {
26306 // TODO: Slight differences here in allocation order and leaving
26307 // RIP in the class. Do they matter any more here than they do
26308 // in the normal allocation?
26309 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26310 if (Subtarget->is64Bit()) {
26311 if (VT == MVT::i32 || VT == MVT::f32)
26312 return std::make_pair(0U, &X86::GR32RegClass);
26313 if (VT == MVT::i16)
26314 return std::make_pair(0U, &X86::GR16RegClass);
26315 if (VT == MVT::i8 || VT == MVT::i1)
26316 return std::make_pair(0U, &X86::GR8RegClass);
26317 if (VT == MVT::i64 || VT == MVT::f64)
26318 return std::make_pair(0U, &X86::GR64RegClass);
26321 // 32-bit fallthrough
26322 case 'Q': // Q_REGS
26323 if (VT == MVT::i32 || VT == MVT::f32)
26324 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26325 if (VT == MVT::i16)
26326 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26327 if (VT == MVT::i8 || VT == MVT::i1)
26328 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26329 if (VT == MVT::i64)
26330 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26332 case 'r': // GENERAL_REGS
26333 case 'l': // INDEX_REGS
26334 if (VT == MVT::i8 || VT == MVT::i1)
26335 return std::make_pair(0U, &X86::GR8RegClass);
26336 if (VT == MVT::i16)
26337 return std::make_pair(0U, &X86::GR16RegClass);
26338 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26339 return std::make_pair(0U, &X86::GR32RegClass);
26340 return std::make_pair(0U, &X86::GR64RegClass);
26341 case 'R': // LEGACY_REGS
26342 if (VT == MVT::i8 || VT == MVT::i1)
26343 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26344 if (VT == MVT::i16)
26345 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26346 if (VT == MVT::i32 || !Subtarget->is64Bit())
26347 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26348 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26349 case 'f': // FP Stack registers.
26350 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26351 // value to the correct fpstack register class.
26352 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26353 return std::make_pair(0U, &X86::RFP32RegClass);
26354 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26355 return std::make_pair(0U, &X86::RFP64RegClass);
26356 return std::make_pair(0U, &X86::RFP80RegClass);
26357 case 'y': // MMX_REGS if MMX allowed.
26358 if (!Subtarget->hasMMX()) break;
26359 return std::make_pair(0U, &X86::VR64RegClass);
26360 case 'Y': // SSE_REGS if SSE2 allowed
26361 if (!Subtarget->hasSSE2()) break;
26363 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26364 if (!Subtarget->hasSSE1()) break;
26366 switch (VT.SimpleTy) {
26368 // Scalar SSE types.
26371 return std::make_pair(0U, &X86::FR32RegClass);
26374 return std::make_pair(0U, &X86::FR64RegClass);
26382 return std::make_pair(0U, &X86::VR128RegClass);
26390 return std::make_pair(0U, &X86::VR256RegClass);
26395 return std::make_pair(0U, &X86::VR512RegClass);
26401 // Use the default implementation in TargetLowering to convert the register
26402 // constraint into a member of a register class.
26403 std::pair<unsigned, const TargetRegisterClass*> Res;
26404 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26406 // Not found as a standard register?
26408 // Map st(0) -> st(7) -> ST0
26409 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26410 tolower(Constraint[1]) == 's' &&
26411 tolower(Constraint[2]) == 't' &&
26412 Constraint[3] == '(' &&
26413 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26414 Constraint[5] == ')' &&
26415 Constraint[6] == '}') {
26417 Res.first = X86::FP0+Constraint[4]-'0';
26418 Res.second = &X86::RFP80RegClass;
26422 // GCC allows "st(0)" to be called just plain "st".
26423 if (StringRef("{st}").equals_lower(Constraint)) {
26424 Res.first = X86::FP0;
26425 Res.second = &X86::RFP80RegClass;
26430 if (StringRef("{flags}").equals_lower(Constraint)) {
26431 Res.first = X86::EFLAGS;
26432 Res.second = &X86::CCRRegClass;
26436 // 'A' means EAX + EDX.
26437 if (Constraint == "A") {
26438 Res.first = X86::EAX;
26439 Res.second = &X86::GR32_ADRegClass;
26445 // Otherwise, check to see if this is a register class of the wrong value
26446 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26447 // turn into {ax},{dx}.
26448 if (Res.second->hasType(VT))
26449 return Res; // Correct type already, nothing to do.
26451 // All of the single-register GCC register classes map their values onto
26452 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26453 // really want an 8-bit or 32-bit register, map to the appropriate register
26454 // class and return the appropriate register.
26455 if (Res.second == &X86::GR16RegClass) {
26456 if (VT == MVT::i8 || VT == MVT::i1) {
26457 unsigned DestReg = 0;
26458 switch (Res.first) {
26460 case X86::AX: DestReg = X86::AL; break;
26461 case X86::DX: DestReg = X86::DL; break;
26462 case X86::CX: DestReg = X86::CL; break;
26463 case X86::BX: DestReg = X86::BL; break;
26466 Res.first = DestReg;
26467 Res.second = &X86::GR8RegClass;
26469 } else if (VT == MVT::i32 || VT == MVT::f32) {
26470 unsigned DestReg = 0;
26471 switch (Res.first) {
26473 case X86::AX: DestReg = X86::EAX; break;
26474 case X86::DX: DestReg = X86::EDX; break;
26475 case X86::CX: DestReg = X86::ECX; break;
26476 case X86::BX: DestReg = X86::EBX; break;
26477 case X86::SI: DestReg = X86::ESI; break;
26478 case X86::DI: DestReg = X86::EDI; break;
26479 case X86::BP: DestReg = X86::EBP; break;
26480 case X86::SP: DestReg = X86::ESP; break;
26483 Res.first = DestReg;
26484 Res.second = &X86::GR32RegClass;
26486 } else if (VT == MVT::i64 || VT == MVT::f64) {
26487 unsigned DestReg = 0;
26488 switch (Res.first) {
26490 case X86::AX: DestReg = X86::RAX; break;
26491 case X86::DX: DestReg = X86::RDX; break;
26492 case X86::CX: DestReg = X86::RCX; break;
26493 case X86::BX: DestReg = X86::RBX; break;
26494 case X86::SI: DestReg = X86::RSI; break;
26495 case X86::DI: DestReg = X86::RDI; break;
26496 case X86::BP: DestReg = X86::RBP; break;
26497 case X86::SP: DestReg = X86::RSP; break;
26500 Res.first = DestReg;
26501 Res.second = &X86::GR64RegClass;
26504 } else if (Res.second == &X86::FR32RegClass ||
26505 Res.second == &X86::FR64RegClass ||
26506 Res.second == &X86::VR128RegClass ||
26507 Res.second == &X86::VR256RegClass ||
26508 Res.second == &X86::FR32XRegClass ||
26509 Res.second == &X86::FR64XRegClass ||
26510 Res.second == &X86::VR128XRegClass ||
26511 Res.second == &X86::VR256XRegClass ||
26512 Res.second == &X86::VR512RegClass) {
26513 // Handle references to XMM physical registers that got mapped into the
26514 // wrong class. This can happen with constraints like {xmm0} where the
26515 // target independent register mapper will just pick the first match it can
26516 // find, ignoring the required type.
26518 if (VT == MVT::f32 || VT == MVT::i32)
26519 Res.second = &X86::FR32RegClass;
26520 else if (VT == MVT::f64 || VT == MVT::i64)
26521 Res.second = &X86::FR64RegClass;
26522 else if (X86::VR128RegClass.hasType(VT))
26523 Res.second = &X86::VR128RegClass;
26524 else if (X86::VR256RegClass.hasType(VT))
26525 Res.second = &X86::VR256RegClass;
26526 else if (X86::VR512RegClass.hasType(VT))
26527 Res.second = &X86::VR512RegClass;
26533 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26535 // Scaling factors are not free at all.
26536 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26537 // will take 2 allocations in the out of order engine instead of 1
26538 // for plain addressing mode, i.e. inst (reg1).
26540 // vaddps (%rsi,%drx), %ymm0, %ymm1
26541 // Requires two allocations (one for the load, one for the computation)
26543 // vaddps (%rsi), %ymm0, %ymm1
26544 // Requires just 1 allocation, i.e., freeing allocations for other operations
26545 // and having less micro operations to execute.
26547 // For some X86 architectures, this is even worse because for instance for
26548 // stores, the complex addressing mode forces the instruction to use the
26549 // "load" ports instead of the dedicated "store" port.
26550 // E.g., on Haswell:
26551 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26552 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26553 if (isLegalAddressingMode(AM, Ty))
26554 // Scale represents reg2 * scale, thus account for 1
26555 // as soon as we use a second register.
26556 return AM.Scale != 0;
26560 bool X86TargetLowering::isTargetFTOL() const {
26561 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();