1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/VectorExtras.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/SmallSet.h"
41 #include "llvm/ADT/StringExtras.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/raw_ostream.h"
47 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
49 // Forward declarations.
50 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
53 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
54 : TargetLowering(TM) {
55 Subtarget = &TM.getSubtarget<X86Subtarget>();
56 X86ScalarSSEf64 = Subtarget->hasSSE2();
57 X86ScalarSSEf32 = Subtarget->hasSSE1();
58 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
60 RegInfo = TM.getRegisterInfo();
63 // Set up the TargetLowering object.
65 // X86 is weird, it always uses i8 for shift amounts and setcc results.
66 setShiftAmountType(MVT::i8);
67 setBooleanContents(ZeroOrOneBooleanContent);
68 setSchedulingPreference(SchedulingForRegPressure);
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
118 } else if (!UseSoftFloat) {
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have an algorithm for SSE2, and we turn this into a 64-bit
124 // FILD for other targets.
125 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
128 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
130 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
134 // SSE has no i16 to fp conversion, only i32
135 if (X86ScalarSSEf32) {
136 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
137 // f32 and f64 cases are Legal, f80 case is not
138 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
141 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
144 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
145 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
148 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
149 // are Legal, f80 is custom lowered.
150 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
151 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
153 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
155 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
156 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
158 if (X86ScalarSSEf32) {
159 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
160 // f32 and f64 cases are Legal, f80 case is not
161 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
163 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
164 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
167 // Handle FP_TO_UINT by promoting the destination to a larger signed
169 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
171 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
173 if (Subtarget->is64Bit()) {
174 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
175 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
176 } else if (!UseSoftFloat) {
177 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
178 // Expand FP_TO_UINT into a select.
179 // FIXME: We would like to use a Custom expander here eventually to do
180 // the optimal thing for SSE vs. the default expansion in the legalizer.
181 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
183 // With SSE3 we can use fisttpll to convert to a signed i64; without
184 // SSE, we're stuck with a fistpll.
185 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
188 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
189 if (!X86ScalarSSEf64) {
190 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
191 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
194 // Scalar integer divide and remainder are lowered to use operations that
195 // produce two results, to match the available instructions. This exposes
196 // the two-result form to trivial CSE, which is able to combine x/y and x%y
197 // into a single instruction.
199 // Scalar integer multiply-high is also lowered to use two-result
200 // operations, to match the available instructions. However, plain multiply
201 // (low) operations are left as Legal, as there are single-result
202 // instructions for this in x86. Using the two-result multiply instructions
203 // when both high and low results are needed must be arranged by dagcombine.
204 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
205 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
206 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
207 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
208 setOperationAction(ISD::SREM , MVT::i8 , Expand);
209 setOperationAction(ISD::UREM , MVT::i8 , Expand);
210 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
211 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
212 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
213 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
214 setOperationAction(ISD::SREM , MVT::i16 , Expand);
215 setOperationAction(ISD::UREM , MVT::i16 , Expand);
216 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
217 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
218 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
219 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
220 setOperationAction(ISD::SREM , MVT::i32 , Expand);
221 setOperationAction(ISD::UREM , MVT::i32 , Expand);
222 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
223 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
224 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
225 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
226 setOperationAction(ISD::SREM , MVT::i64 , Expand);
227 setOperationAction(ISD::UREM , MVT::i64 , Expand);
229 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
230 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
231 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
232 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
233 if (Subtarget->is64Bit())
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
237 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
238 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
239 setOperationAction(ISD::FREM , MVT::f32 , Expand);
240 setOperationAction(ISD::FREM , MVT::f64 , Expand);
241 setOperationAction(ISD::FREM , MVT::f80 , Expand);
242 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
247 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
248 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
249 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
250 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
251 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
252 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
255 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
256 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
259 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
260 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
262 // These should be promoted to a larger select which is supported.
263 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
264 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
265 // X86 wants to expand cmov itself.
266 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
267 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
268 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
269 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
270 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
271 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
274 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
275 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
276 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
277 if (Subtarget->is64Bit()) {
278 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
279 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
281 // X86 ret instruction may pop stack.
282 setOperationAction(ISD::RET , MVT::Other, Custom);
283 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
286 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
287 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
288 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
289 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
290 if (Subtarget->is64Bit())
291 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
292 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
293 if (Subtarget->is64Bit()) {
294 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
295 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
296 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
297 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
299 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
300 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
301 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
302 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
303 if (Subtarget->is64Bit()) {
304 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
305 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
306 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
309 if (Subtarget->hasSSE1())
310 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
312 if (!Subtarget->hasSSE2())
313 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
315 // Expand certain atomics
316 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
317 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
318 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
326 if (!Subtarget->is64Bit()) {
327 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
328 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
329 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
330 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
331 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
332 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
333 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
336 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
337 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
338 // FIXME - use subtarget debug flags
339 if (!Subtarget->isTargetDarwin() &&
340 !Subtarget->isTargetELF() &&
341 !Subtarget->isTargetCygMing()) {
342 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
343 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
346 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
347 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
348 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
349 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
350 if (Subtarget->is64Bit()) {
351 setExceptionPointerRegister(X86::RAX);
352 setExceptionSelectorRegister(X86::RDX);
354 setExceptionPointerRegister(X86::EAX);
355 setExceptionSelectorRegister(X86::EDX);
357 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
358 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
360 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
362 setOperationAction(ISD::TRAP, MVT::Other, Legal);
364 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
365 setOperationAction(ISD::VASTART , MVT::Other, Custom);
366 setOperationAction(ISD::VAEND , MVT::Other, Expand);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::VAARG , MVT::Other, Custom);
369 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
371 setOperationAction(ISD::VAARG , MVT::Other, Expand);
372 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
375 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
376 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
377 if (Subtarget->is64Bit())
378 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
379 if (Subtarget->isTargetCygMing())
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
382 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
384 if (!UseSoftFloat && X86ScalarSSEf64) {
385 // f32 and f64 use SSE.
386 // Set up the FP register classes.
387 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
388 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
390 // Use ANDPD to simulate FABS.
391 setOperationAction(ISD::FABS , MVT::f64, Custom);
392 setOperationAction(ISD::FABS , MVT::f32, Custom);
394 // Use XORP to simulate FNEG.
395 setOperationAction(ISD::FNEG , MVT::f64, Custom);
396 setOperationAction(ISD::FNEG , MVT::f32, Custom);
398 // Use ANDPD and ORPD to simulate FCOPYSIGN.
399 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
400 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
402 // We don't support sin/cos/fmod
403 setOperationAction(ISD::FSIN , MVT::f64, Expand);
404 setOperationAction(ISD::FCOS , MVT::f64, Expand);
405 setOperationAction(ISD::FSIN , MVT::f32, Expand);
406 setOperationAction(ISD::FCOS , MVT::f32, Expand);
408 // Expand FP immediates into loads from the stack, except for the special
410 addLegalFPImmediate(APFloat(+0.0)); // xorpd
411 addLegalFPImmediate(APFloat(+0.0f)); // xorps
412 } else if (!UseSoftFloat && X86ScalarSSEf32) {
413 // Use SSE for f32, x87 for f64.
414 // Set up the FP register classes.
415 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
416 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
418 // Use ANDPS to simulate FABS.
419 setOperationAction(ISD::FABS , MVT::f32, Custom);
421 // Use XORP to simulate FNEG.
422 setOperationAction(ISD::FNEG , MVT::f32, Custom);
424 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
426 // Use ANDPS and ORPS to simulate FCOPYSIGN.
427 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
428 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
430 // We don't support sin/cos/fmod
431 setOperationAction(ISD::FSIN , MVT::f32, Expand);
432 setOperationAction(ISD::FCOS , MVT::f32, Expand);
434 // Special cases we handle for FP constants.
435 addLegalFPImmediate(APFloat(+0.0f)); // xorps
436 addLegalFPImmediate(APFloat(+0.0)); // FLD0
437 addLegalFPImmediate(APFloat(+1.0)); // FLD1
438 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
439 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
442 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
443 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
445 } else if (!UseSoftFloat) {
446 // f32 and f64 in x87.
447 // Set up the FP register classes.
448 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
449 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
451 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
452 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
453 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
454 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
460 addLegalFPImmediate(APFloat(+0.0)); // FLD0
461 addLegalFPImmediate(APFloat(+1.0)); // FLD1
462 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
463 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
464 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
465 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
466 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
467 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
470 // Long double always uses X87.
472 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
473 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
474 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
477 APFloat TmpFlt(+0.0);
478 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
480 addLegalFPImmediate(TmpFlt); // FLD0
482 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
483 APFloat TmpFlt2(+1.0);
484 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
486 addLegalFPImmediate(TmpFlt2); // FLD1
487 TmpFlt2.changeSign();
488 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
492 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
493 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
497 // Always use a library call for pow.
498 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
499 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
500 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
502 setOperationAction(ISD::FLOG, MVT::f80, Expand);
503 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
504 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
505 setOperationAction(ISD::FEXP, MVT::f80, Expand);
506 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
508 // First set operation action for all vector types to either promote
509 // (for widening) or expand (for scalarization). Then we will selectively
510 // turn on ones that can be effectively codegen'd.
511 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
512 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
513 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
528 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
529 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
563 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
564 // with -msoft-float, disable use of MMX as well.
565 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
566 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
567 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
568 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
569 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
570 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
572 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
573 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
574 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
575 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
577 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
578 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
579 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
580 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
582 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
583 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
585 setOperationAction(ISD::AND, MVT::v8i8, Promote);
586 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
587 setOperationAction(ISD::AND, MVT::v4i16, Promote);
588 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
589 setOperationAction(ISD::AND, MVT::v2i32, Promote);
590 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
591 setOperationAction(ISD::AND, MVT::v1i64, Legal);
593 setOperationAction(ISD::OR, MVT::v8i8, Promote);
594 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
595 setOperationAction(ISD::OR, MVT::v4i16, Promote);
596 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
597 setOperationAction(ISD::OR, MVT::v2i32, Promote);
598 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
599 setOperationAction(ISD::OR, MVT::v1i64, Legal);
601 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
602 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
603 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
604 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
605 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
606 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
607 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
609 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
610 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
611 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
612 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
613 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
614 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
615 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
616 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
617 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
621 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
622 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
623 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
628 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
631 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
632 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
633 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
637 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
638 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
639 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
640 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
641 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
642 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
643 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
644 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
645 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
648 if (!UseSoftFloat && Subtarget->hasSSE1()) {
649 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
651 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
652 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
653 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
654 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
655 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
656 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
657 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
659 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
660 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
661 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
662 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
665 if (!UseSoftFloat && Subtarget->hasSSE2()) {
666 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
668 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
669 // registers cannot be used even for integer operations.
670 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
671 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
672 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
673 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
675 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
676 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
677 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
678 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
679 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
680 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
681 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
682 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
683 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
684 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
685 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
686 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
687 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
688 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
689 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
690 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
693 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
694 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
695 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
697 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
698 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
699 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
700 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
701 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
703 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
704 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
705 MVT VT = (MVT::SimpleValueType)i;
706 // Do not attempt to custom lower non-power-of-2 vectors
707 if (!isPowerOf2_32(VT.getVectorNumElements()))
709 // Do not attempt to custom lower non-128-bit vectors
710 if (!VT.is128BitVector())
712 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
713 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
717 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
718 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
719 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
720 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
721 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
724 if (Subtarget->is64Bit()) {
725 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
729 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
730 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
731 MVT VT = (MVT::SimpleValueType)i;
733 // Do not attempt to promote non-128-bit vectors
734 if (!VT.is128BitVector()) {
737 setOperationAction(ISD::AND, VT, Promote);
738 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
739 setOperationAction(ISD::OR, VT, Promote);
740 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
741 setOperationAction(ISD::XOR, VT, Promote);
742 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
743 setOperationAction(ISD::LOAD, VT, Promote);
744 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
745 setOperationAction(ISD::SELECT, VT, Promote);
746 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
749 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
751 // Custom lower v2i64 and v2f64 selects.
752 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
753 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
754 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
755 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
757 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
758 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
759 if (!DisableMMX && Subtarget->hasMMX()) {
760 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
761 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
765 if (Subtarget->hasSSE41()) {
766 // FIXME: Do we need to handle scalar-to-vector here?
767 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
769 // i8 and i16 vectors are custom , because the source register and source
770 // source memory operand types are not the same width. f32 vectors are
771 // custom since the immediate controlling the insert encodes additional
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
774 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
776 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
783 if (Subtarget->is64Bit()) {
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
789 if (Subtarget->hasSSE42()) {
790 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
793 if (!UseSoftFloat && Subtarget->hasAVX()) {
794 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
795 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
796 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
797 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
799 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
800 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
801 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
802 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
803 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
804 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
805 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
806 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
807 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
808 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
809 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
810 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
811 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
812 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
813 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
815 // Operations to consider commented out -v16i16 v32i8
816 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
817 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
818 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
819 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
820 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
822 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
823 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
824 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
825 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
826 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
827 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
828 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
829 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
831 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
832 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
833 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
834 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
836 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
837 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
838 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
842 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
843 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
845 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
850 // Not sure we want to do this since there are no 256-bit integer
853 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
854 // This includes 256-bit vectors
855 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
856 MVT VT = (MVT::SimpleValueType)i;
858 // Do not attempt to custom lower non-power-of-2 vectors
859 if (!isPowerOf2_32(VT.getVectorNumElements()))
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
867 if (Subtarget->is64Bit()) {
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
874 // Not sure we want to do this since there are no 256-bit integer
877 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
878 // Including 256-bit vectors
879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
880 MVT VT = (MVT::SimpleValueType)i;
882 if (!VT.is256BitVector()) {
885 setOperationAction(ISD::AND, VT, Promote);
886 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
887 setOperationAction(ISD::OR, VT, Promote);
888 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
889 setOperationAction(ISD::XOR, VT, Promote);
890 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
891 setOperationAction(ISD::LOAD, VT, Promote);
892 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
893 setOperationAction(ISD::SELECT, VT, Promote);
894 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
897 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
901 // We want to custom lower some of our intrinsics.
902 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
904 // Add/Sub/Mul with overflow operations are custom lowered.
905 setOperationAction(ISD::SADDO, MVT::i32, Custom);
906 setOperationAction(ISD::SADDO, MVT::i64, Custom);
907 setOperationAction(ISD::UADDO, MVT::i32, Custom);
908 setOperationAction(ISD::UADDO, MVT::i64, Custom);
909 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
910 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
911 setOperationAction(ISD::USUBO, MVT::i32, Custom);
912 setOperationAction(ISD::USUBO, MVT::i64, Custom);
913 setOperationAction(ISD::SMULO, MVT::i32, Custom);
914 setOperationAction(ISD::SMULO, MVT::i64, Custom);
916 if (!Subtarget->is64Bit()) {
917 // These libcalls are not available in 32-bit.
918 setLibcallName(RTLIB::SHL_I128, 0);
919 setLibcallName(RTLIB::SRL_I128, 0);
920 setLibcallName(RTLIB::SRA_I128, 0);
923 // We have target-specific dag combine patterns for the following nodes:
924 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
925 setTargetDAGCombine(ISD::BUILD_VECTOR);
926 setTargetDAGCombine(ISD::SELECT);
927 setTargetDAGCombine(ISD::SHL);
928 setTargetDAGCombine(ISD::SRA);
929 setTargetDAGCombine(ISD::SRL);
930 setTargetDAGCombine(ISD::STORE);
931 setTargetDAGCombine(ISD::MEMBARRIER);
932 if (Subtarget->is64Bit())
933 setTargetDAGCombine(ISD::MUL);
935 computeRegisterProperties();
937 // FIXME: These should be based on subtarget info. Plus, the values should
938 // be smaller when we are in optimizing for size mode.
939 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
940 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
941 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
942 allowUnalignedMemoryAccesses = true; // x86 supports it!
943 setPrefLoopAlignment(16);
944 benefitFromCodePlacementOpt = true;
948 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
953 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
954 /// the desired ByVal argument alignment.
955 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
958 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
959 if (VTy->getBitWidth() == 128)
961 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
962 unsigned EltAlign = 0;
963 getMaxByValAlign(ATy->getElementType(), EltAlign);
964 if (EltAlign > MaxAlign)
966 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
967 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
968 unsigned EltAlign = 0;
969 getMaxByValAlign(STy->getElementType(i), EltAlign);
970 if (EltAlign > MaxAlign)
979 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
980 /// function arguments in the caller parameter area. For X86, aggregates
981 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
982 /// are at 4-byte boundaries.
983 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
984 if (Subtarget->is64Bit()) {
985 // Max of 8 and alignment of type.
986 unsigned TyAlign = TD->getABITypeAlignment(Ty);
993 if (Subtarget->hasSSE1())
994 getMaxByValAlign(Ty, Align);
998 /// getOptimalMemOpType - Returns the target specific optimal type for load
999 /// and store operations as a result of memset, memcpy, and memmove
1000 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1003 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1004 bool isSrcConst, bool isSrcStr,
1005 SelectionDAG &DAG) const {
1006 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1007 // linux. This is because the stack realignment code can't handle certain
1008 // cases like PR2962. This should be removed when PR2962 is fixed.
1009 const Function *F = DAG.getMachineFunction().getFunction();
1010 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1011 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1012 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1014 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1017 if (Subtarget->is64Bit() && Size >= 8)
1022 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1024 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1025 SelectionDAG &DAG) const {
1026 if (usesGlobalOffsetTable())
1027 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1028 if (!Subtarget->is64Bit())
1029 // This doesn't have DebugLoc associated with it, but is not really the
1030 // same as a Register.
1031 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1036 /// getFunctionAlignment - Return the Log2 alignment of this function.
1037 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1038 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1041 //===----------------------------------------------------------------------===//
1042 // Return Value Calling Convention Implementation
1043 //===----------------------------------------------------------------------===//
1045 #include "X86GenCallingConv.inc"
1047 /// LowerRET - Lower an ISD::RET node.
1048 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1049 DebugLoc dl = Op.getDebugLoc();
1050 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
1052 SmallVector<CCValAssign, 16> RVLocs;
1053 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1054 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1055 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
1056 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
1058 // If this is the first return lowered for this function, add the regs to the
1059 // liveout set for the function.
1060 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1061 for (unsigned i = 0; i != RVLocs.size(); ++i)
1062 if (RVLocs[i].isRegLoc())
1063 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1065 SDValue Chain = Op.getOperand(0);
1067 // Handle tail call return.
1068 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
1069 if (Chain.getOpcode() == X86ISD::TAILCALL) {
1070 SDValue TailCall = Chain;
1071 SDValue TargetAddress = TailCall.getOperand(1);
1072 SDValue StackAdjustment = TailCall.getOperand(2);
1073 assert(((TargetAddress.getOpcode() == ISD::Register &&
1074 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
1075 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R11)) ||
1076 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
1077 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
1078 "Expecting an global address, external symbol, or register");
1079 assert(StackAdjustment.getOpcode() == ISD::Constant &&
1080 "Expecting a const value");
1082 SmallVector<SDValue,8> Operands;
1083 Operands.push_back(Chain.getOperand(0));
1084 Operands.push_back(TargetAddress);
1085 Operands.push_back(StackAdjustment);
1086 // Copy registers used by the call. Last operand is a flag so it is not
1088 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
1089 Operands.push_back(Chain.getOperand(i));
1091 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
1098 SmallVector<SDValue, 6> RetOps;
1099 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1100 // Operand #1 = Bytes To Pop
1101 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1103 // Copy the result values into the output registers.
1104 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1105 CCValAssign &VA = RVLocs[i];
1106 assert(VA.isRegLoc() && "Can only return in registers!");
1107 SDValue ValToCopy = Op.getOperand(i*2+1);
1109 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1110 // the RET instruction and handled by the FP Stackifier.
1111 if (VA.getLocReg() == X86::ST0 ||
1112 VA.getLocReg() == X86::ST1) {
1113 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1114 // change the value to the FP stack register class.
1115 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1116 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1117 RetOps.push_back(ValToCopy);
1118 // Don't emit a copytoreg.
1122 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1123 // which is returned in RAX / RDX.
1124 if (Subtarget->is64Bit()) {
1125 MVT ValVT = ValToCopy.getValueType();
1126 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1127 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1128 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1129 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1133 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1134 Flag = Chain.getValue(1);
1137 // The x86-64 ABI for returning structs by value requires that we copy
1138 // the sret argument into %rax for the return. We saved the argument into
1139 // a virtual register in the entry block, so now we copy the value out
1141 if (Subtarget->is64Bit() &&
1142 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1143 MachineFunction &MF = DAG.getMachineFunction();
1144 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1145 unsigned Reg = FuncInfo->getSRetReturnReg();
1147 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1148 FuncInfo->setSRetReturnReg(Reg);
1150 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1152 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1153 Flag = Chain.getValue(1);
1156 RetOps[0] = Chain; // Update chain.
1158 // Add the flag if we have it.
1160 RetOps.push_back(Flag);
1162 return DAG.getNode(X86ISD::RET_FLAG, dl,
1163 MVT::Other, &RetOps[0], RetOps.size());
1167 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1168 /// appropriate copies out of appropriate physical registers. This assumes that
1169 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1170 /// being lowered. The returns a SDNode with the same number of values as the
1172 SDNode *X86TargetLowering::
1173 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1174 unsigned CallingConv, SelectionDAG &DAG) {
1176 DebugLoc dl = TheCall->getDebugLoc();
1177 // Assign locations to each value returned by this call.
1178 SmallVector<CCValAssign, 16> RVLocs;
1179 bool isVarArg = TheCall->isVarArg();
1180 bool Is64Bit = Subtarget->is64Bit();
1181 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
1182 RVLocs, *DAG.getContext());
1183 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1185 SmallVector<SDValue, 8> ResultVals;
1187 // Copy all of the result registers out of their specified physreg.
1188 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1189 CCValAssign &VA = RVLocs[i];
1190 MVT CopyVT = VA.getValVT();
1192 // If this is x86-64, and we disabled SSE, we can't return FP values
1193 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1194 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1195 llvm_report_error("SSE register return with SSE disabled");
1198 // If this is a call to a function that returns an fp value on the floating
1199 // point stack, but where we prefer to use the value in xmm registers, copy
1200 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1201 if ((VA.getLocReg() == X86::ST0 ||
1202 VA.getLocReg() == X86::ST1) &&
1203 isScalarFPTypeInSSEReg(VA.getValVT())) {
1208 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1209 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1210 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1211 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1212 MVT::v2i64, InFlag).getValue(1);
1213 Val = Chain.getValue(0);
1214 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1215 Val, DAG.getConstant(0, MVT::i64));
1217 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1218 MVT::i64, InFlag).getValue(1);
1219 Val = Chain.getValue(0);
1221 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1223 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1224 CopyVT, InFlag).getValue(1);
1225 Val = Chain.getValue(0);
1227 InFlag = Chain.getValue(2);
1229 if (CopyVT != VA.getValVT()) {
1230 // Round the F80 the right size, which also moves to the appropriate xmm
1232 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1233 // This truncation won't change the value.
1234 DAG.getIntPtrConstant(1));
1237 ResultVals.push_back(Val);
1240 // Merge everything together with a MERGE_VALUES node.
1241 ResultVals.push_back(Chain);
1242 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1243 &ResultVals[0], ResultVals.size()).getNode();
1247 //===----------------------------------------------------------------------===//
1248 // C & StdCall & Fast Calling Convention implementation
1249 //===----------------------------------------------------------------------===//
1250 // StdCall calling convention seems to be standard for many Windows' API
1251 // routines and around. It differs from C calling convention just a little:
1252 // callee should clean up the stack, not caller. Symbols should be also
1253 // decorated in some fancy way :) It doesn't support any vector arguments.
1254 // For info on fast calling convention see Fast Calling Convention (tail call)
1255 // implementation LowerX86_32FastCCCallTo.
1257 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1259 static bool CallIsStructReturn(CallSDNode *TheCall) {
1260 unsigned NumOps = TheCall->getNumArgs();
1264 return TheCall->getArgFlags(0).isSRet();
1267 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1268 /// return semantics.
1269 static bool ArgsAreStructReturn(SDValue Op) {
1270 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1274 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1277 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1278 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1280 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1284 switch (CallingConv) {
1287 case CallingConv::X86_StdCall:
1288 return !Subtarget->is64Bit();
1289 case CallingConv::X86_FastCall:
1290 return !Subtarget->is64Bit();
1291 case CallingConv::Fast:
1292 return PerformTailCallOpt;
1296 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1297 /// given CallingConvention value.
1298 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1299 if (Subtarget->is64Bit()) {
1300 if (Subtarget->isTargetWin64())
1301 return CC_X86_Win64_C;
1306 if (CC == CallingConv::X86_FastCall)
1307 return CC_X86_32_FastCall;
1308 else if (CC == CallingConv::Fast)
1309 return CC_X86_32_FastCC;
1314 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1315 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1317 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1318 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1319 if (CC == CallingConv::X86_FastCall)
1321 else if (CC == CallingConv::X86_StdCall)
1327 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1328 /// by "Src" to address "Dst" with size and alignment information specified by
1329 /// the specific parameter attribute. The copy will be passed as a byval
1330 /// function parameter.
1332 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1333 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1335 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1336 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1337 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1340 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1341 const CCValAssign &VA,
1342 MachineFrameInfo *MFI,
1344 SDValue Root, unsigned i) {
1345 // Create the nodes corresponding to a load from this parameter slot.
1346 ISD::ArgFlagsTy Flags =
1347 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1348 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1349 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1351 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1352 // changed with more analysis.
1353 // In case of tail call optimization mark all arguments mutable. Since they
1354 // could be overwritten by lowering of arguments in case of a tail call.
1355 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1356 VA.getLocMemOffset(), isImmutable);
1357 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1358 if (Flags.isByVal())
1360 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1361 PseudoSourceValue::getFixedStack(FI), 0);
1365 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1366 MachineFunction &MF = DAG.getMachineFunction();
1367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1368 DebugLoc dl = Op.getDebugLoc();
1370 const Function* Fn = MF.getFunction();
1371 if (Fn->hasExternalLinkage() &&
1372 Subtarget->isTargetCygMing() &&
1373 Fn->getName() == "main")
1374 FuncInfo->setForceFramePointer(true);
1376 // Decorate the function name.
1377 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1379 MachineFrameInfo *MFI = MF.getFrameInfo();
1380 SDValue Root = Op.getOperand(0);
1381 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1382 unsigned CC = MF.getFunction()->getCallingConv();
1383 bool Is64Bit = Subtarget->is64Bit();
1384 bool IsWin64 = Subtarget->isTargetWin64();
1386 assert(!(isVarArg && CC == CallingConv::Fast) &&
1387 "Var args not supported with calling convention fastcc");
1389 // Assign locations to all of the incoming arguments.
1390 SmallVector<CCValAssign, 16> ArgLocs;
1391 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
1392 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1394 SmallVector<SDValue, 8> ArgValues;
1395 unsigned LastVal = ~0U;
1396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1397 CCValAssign &VA = ArgLocs[i];
1398 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1400 assert(VA.getValNo() != LastVal &&
1401 "Don't support value assigned to multiple locs yet");
1402 LastVal = VA.getValNo();
1404 if (VA.isRegLoc()) {
1405 MVT RegVT = VA.getLocVT();
1406 TargetRegisterClass *RC = NULL;
1407 if (RegVT == MVT::i32)
1408 RC = X86::GR32RegisterClass;
1409 else if (Is64Bit && RegVT == MVT::i64)
1410 RC = X86::GR64RegisterClass;
1411 else if (RegVT == MVT::f32)
1412 RC = X86::FR32RegisterClass;
1413 else if (RegVT == MVT::f64)
1414 RC = X86::FR64RegisterClass;
1415 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1416 RC = X86::VR128RegisterClass;
1417 else if (RegVT.isVector()) {
1418 assert(RegVT.getSizeInBits() == 64);
1420 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1422 // Darwin calling convention passes MMX values in either GPRs or
1423 // XMMs in x86-64. Other targets pass them in memory.
1424 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1425 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1428 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1433 llvm_unreachable("Unknown argument type!");
1436 unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
1437 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1439 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1440 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1442 if (VA.getLocInfo() == CCValAssign::SExt)
1443 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1444 DAG.getValueType(VA.getValVT()));
1445 else if (VA.getLocInfo() == CCValAssign::ZExt)
1446 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1447 DAG.getValueType(VA.getValVT()));
1449 if (VA.getLocInfo() != CCValAssign::Full)
1450 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1452 // Handle MMX values passed in GPRs.
1453 if (Is64Bit && RegVT != VA.getLocVT()) {
1454 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1455 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1456 else if (RC == X86::VR128RegisterClass) {
1457 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1458 ArgValue, DAG.getConstant(0, MVT::i64));
1459 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1463 ArgValues.push_back(ArgValue);
1465 assert(VA.isMemLoc());
1466 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1470 // The x86-64 ABI for returning structs by value requires that we copy
1471 // the sret argument into %rax for the return. Save the argument into
1472 // a virtual register so that we can access it from the return points.
1473 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1474 MachineFunction &MF = DAG.getMachineFunction();
1475 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 unsigned Reg = FuncInfo->getSRetReturnReg();
1478 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1479 FuncInfo->setSRetReturnReg(Reg);
1481 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1482 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1485 unsigned StackSize = CCInfo.getNextStackOffset();
1486 // align stack specially for tail calls
1487 if (PerformTailCallOpt && CC == CallingConv::Fast)
1488 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1490 // If the function takes variable number of arguments, make a frame index for
1491 // the start of the first vararg value... for expansion of llvm.va_start.
1493 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1494 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1497 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1499 // FIXME: We should really autogenerate these arrays
1500 static const unsigned GPR64ArgRegsWin64[] = {
1501 X86::RCX, X86::RDX, X86::R8, X86::R9
1503 static const unsigned XMMArgRegsWin64[] = {
1504 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1506 static const unsigned GPR64ArgRegs64Bit[] = {
1507 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1509 static const unsigned XMMArgRegs64Bit[] = {
1510 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1511 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1513 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1516 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1517 GPR64ArgRegs = GPR64ArgRegsWin64;
1518 XMMArgRegs = XMMArgRegsWin64;
1520 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1521 GPR64ArgRegs = GPR64ArgRegs64Bit;
1522 XMMArgRegs = XMMArgRegs64Bit;
1524 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1526 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1529 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1530 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1531 "SSE register cannot be used when SSE is disabled!");
1532 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1533 "SSE register cannot be used when SSE is disabled!");
1534 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1535 // Kernel mode asks for SSE to be disabled, so don't push them
1537 TotalNumXMMRegs = 0;
1539 // For X86-64, if there are vararg parameters that are passed via
1540 // registers, then we must store them to their spots on the stack so they
1541 // may be loaded by deferencing the result of va_next.
1542 VarArgsGPOffset = NumIntRegs * 8;
1543 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1544 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1545 TotalNumXMMRegs * 16, 16);
1547 // Store the integer parameter registers.
1548 SmallVector<SDValue, 8> MemOps;
1549 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1550 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1551 DAG.getIntPtrConstant(VarArgsGPOffset));
1552 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1553 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1554 X86::GR64RegisterClass);
1555 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1557 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1558 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1559 MemOps.push_back(Store);
1560 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1561 DAG.getIntPtrConstant(8));
1564 // Now store the XMM (fp + vector) parameter registers.
1565 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1566 DAG.getIntPtrConstant(VarArgsFPOffset));
1567 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1568 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1569 X86::VR128RegisterClass);
1570 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1572 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1573 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1574 MemOps.push_back(Store);
1575 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1576 DAG.getIntPtrConstant(16));
1578 if (!MemOps.empty())
1579 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1580 &MemOps[0], MemOps.size());
1584 ArgValues.push_back(Root);
1586 // Some CCs need callee pop.
1587 if (IsCalleePop(isVarArg, CC)) {
1588 BytesToPopOnReturn = StackSize; // Callee pops everything.
1589 BytesCallerReserves = 0;
1591 BytesToPopOnReturn = 0; // Callee pops nothing.
1592 // If this is an sret function, the return should pop the hidden pointer.
1593 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1594 BytesToPopOnReturn = 4;
1595 BytesCallerReserves = StackSize;
1599 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1600 if (CC == CallingConv::X86_FastCall)
1601 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1604 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1606 // Return the new list of results.
1607 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1608 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1612 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1613 const SDValue &StackPtr,
1614 const CCValAssign &VA,
1616 SDValue Arg, ISD::ArgFlagsTy Flags) {
1617 DebugLoc dl = TheCall->getDebugLoc();
1618 unsigned LocMemOffset = VA.getLocMemOffset();
1619 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1620 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1621 if (Flags.isByVal()) {
1622 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1624 return DAG.getStore(Chain, dl, Arg, PtrOff,
1625 PseudoSourceValue::getStack(), LocMemOffset);
1628 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1629 /// optimization is performed and it is required.
1631 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1632 SDValue &OutRetAddr,
1638 if (!IsTailCall || FPDiff==0) return Chain;
1640 // Adjust the Return address stack slot.
1641 MVT VT = getPointerTy();
1642 OutRetAddr = getReturnAddressFrameIndex(DAG);
1644 // Load the "old" Return address.
1645 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1646 return SDValue(OutRetAddr.getNode(), 1);
1649 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1650 /// optimization is performed and it is required (FPDiff!=0).
1652 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1653 SDValue Chain, SDValue RetAddrFrIdx,
1654 bool Is64Bit, int FPDiff, DebugLoc dl) {
1655 // Store the return address to the appropriate stack slot.
1656 if (!FPDiff) return Chain;
1657 // Calculate the new stack slot for the return address.
1658 int SlotSize = Is64Bit ? 8 : 4;
1659 int NewReturnAddrFI =
1660 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1661 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1662 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1663 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1664 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1668 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1669 MachineFunction &MF = DAG.getMachineFunction();
1670 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1671 SDValue Chain = TheCall->getChain();
1672 unsigned CC = TheCall->getCallingConv();
1673 bool isVarArg = TheCall->isVarArg();
1674 bool IsTailCall = TheCall->isTailCall() &&
1675 CC == CallingConv::Fast && PerformTailCallOpt;
1676 SDValue Callee = TheCall->getCallee();
1677 bool Is64Bit = Subtarget->is64Bit();
1678 bool IsStructRet = CallIsStructReturn(TheCall);
1679 DebugLoc dl = TheCall->getDebugLoc();
1681 assert(!(isVarArg && CC == CallingConv::Fast) &&
1682 "Var args not supported with calling convention fastcc");
1684 // Analyze operands of the call, assigning locations to each operand.
1685 SmallVector<CCValAssign, 16> ArgLocs;
1686 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
1687 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1689 // Get a count of how many bytes are to be pushed on the stack.
1690 unsigned NumBytes = CCInfo.getNextStackOffset();
1691 if (PerformTailCallOpt && CC == CallingConv::Fast)
1692 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1696 // Lower arguments at fp - stackoffset + fpdiff.
1697 unsigned NumBytesCallerPushed =
1698 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1699 FPDiff = NumBytesCallerPushed - NumBytes;
1701 // Set the delta of movement of the returnaddr stackslot.
1702 // But only set if delta is greater than previous delta.
1703 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1704 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1707 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1709 SDValue RetAddrFrIdx;
1710 // Load return adress for tail calls.
1711 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1714 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1715 SmallVector<SDValue, 8> MemOpChains;
1718 // Walk the register/memloc assignments, inserting copies/loads. In the case
1719 // of tail call optimization arguments are handle later.
1720 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1721 CCValAssign &VA = ArgLocs[i];
1722 SDValue Arg = TheCall->getArg(i);
1723 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1724 bool isByVal = Flags.isByVal();
1726 // Promote the value if needed.
1727 switch (VA.getLocInfo()) {
1728 default: llvm_unreachable("Unknown loc info!");
1729 case CCValAssign::Full: break;
1730 case CCValAssign::SExt:
1731 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1733 case CCValAssign::ZExt:
1734 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1736 case CCValAssign::AExt:
1737 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1741 if (VA.isRegLoc()) {
1743 MVT RegVT = VA.getLocVT();
1744 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1745 switch (VA.getLocReg()) {
1748 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1750 // Special case: passing MMX values in GPR registers.
1751 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1754 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1755 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1756 // Special case: passing MMX values in XMM registers.
1757 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1758 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1759 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1764 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1766 if (!IsTailCall || (IsTailCall && isByVal)) {
1767 assert(VA.isMemLoc());
1768 if (StackPtr.getNode() == 0)
1769 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1771 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1772 Chain, Arg, Flags));
1777 if (!MemOpChains.empty())
1778 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1779 &MemOpChains[0], MemOpChains.size());
1781 // Build a sequence of copy-to-reg nodes chained together with token chain
1782 // and flag operands which copy the outgoing args into registers.
1784 // Tail call byval lowering might overwrite argument registers so in case of
1785 // tail call optimization the copies to registers are lowered later.
1787 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1788 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1789 RegsToPass[i].second, InFlag);
1790 InFlag = Chain.getValue(1);
1794 if (Subtarget->isPICStyleGOT()) {
1795 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1798 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1799 DAG.getNode(X86ISD::GlobalBaseReg,
1800 DebugLoc::getUnknownLoc(),
1803 InFlag = Chain.getValue(1);
1805 // If we are tail calling and generating PIC/GOT style code load the
1806 // address of the callee into ECX. The value in ecx is used as target of
1807 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1808 // for tail calls on PIC/GOT architectures. Normally we would just put the
1809 // address of GOT into ebx and then call target@PLT. But for tail calls
1810 // ebx would be restored (since ebx is callee saved) before jumping to the
1813 // Note: The actual moving to ECX is done further down.
1814 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1815 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1816 !G->getGlobal()->hasProtectedVisibility())
1817 Callee = LowerGlobalAddress(Callee, DAG);
1818 else if (isa<ExternalSymbolSDNode>(Callee))
1819 Callee = LowerExternalSymbol(Callee, DAG);
1823 if (Is64Bit && isVarArg) {
1824 // From AMD64 ABI document:
1825 // For calls that may call functions that use varargs or stdargs
1826 // (prototype-less calls or calls to functions containing ellipsis (...) in
1827 // the declaration) %al is used as hidden argument to specify the number
1828 // of SSE registers used. The contents of %al do not need to match exactly
1829 // the number of registers, but must be an ubound on the number of SSE
1830 // registers used and is in the range 0 - 8 inclusive.
1832 // FIXME: Verify this on Win64
1833 // Count the number of XMM registers allocated.
1834 static const unsigned XMMArgRegs[] = {
1835 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1836 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1838 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1839 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1840 && "SSE registers cannot be used when SSE is disabled");
1842 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1843 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1844 InFlag = Chain.getValue(1);
1848 // For tail calls lower the arguments to the 'real' stack slot.
1850 SmallVector<SDValue, 8> MemOpChains2;
1853 // Do not flag preceeding copytoreg stuff together with the following stuff.
1855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1856 CCValAssign &VA = ArgLocs[i];
1857 if (!VA.isRegLoc()) {
1858 assert(VA.isMemLoc());
1859 SDValue Arg = TheCall->getArg(i);
1860 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1861 // Create frame index.
1862 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1863 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1864 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1865 FIN = DAG.getFrameIndex(FI, getPointerTy());
1867 if (Flags.isByVal()) {
1868 // Copy relative to framepointer.
1869 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1870 if (StackPtr.getNode() == 0)
1871 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1873 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1875 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1878 // Store relative to framepointer.
1879 MemOpChains2.push_back(
1880 DAG.getStore(Chain, dl, Arg, FIN,
1881 PseudoSourceValue::getFixedStack(FI), 0));
1886 if (!MemOpChains2.empty())
1887 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1888 &MemOpChains2[0], MemOpChains2.size());
1890 // Copy arguments to their registers.
1891 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1892 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1893 RegsToPass[i].second, InFlag);
1894 InFlag = Chain.getValue(1);
1898 // Store the return address to the appropriate stack slot.
1899 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1903 // If the callee is a GlobalAddress node (quite common, every direct call is)
1904 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1905 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1906 // We should use extra load for direct calls to dllimported functions in
1908 GlobalValue *GV = G->getGlobal();
1909 if (!GV->hasDLLImportLinkage()) {
1910 unsigned char OpFlags = 0;
1912 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1913 // external symbols most go through the PLT in PIC mode. If the symbol
1914 // has hidden or protected visibility, or if it is static or local, then
1915 // we don't need to use the PLT - we can directly call it.
1916 if (Subtarget->isTargetELF() &&
1917 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1918 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1919 OpFlags = X86II::MO_PLT;
1920 } else if (Subtarget->isPICStyleStubAny() &&
1921 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1922 Subtarget->getDarwinVers() < 9) {
1923 // PC-relative references to external symbols should go through $stub,
1924 // unless we're building with the leopard linker or later, which
1925 // automatically synthesizes these stubs.
1926 OpFlags = X86II::MO_DARWIN_STUB;
1929 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1930 G->getOffset(), OpFlags);
1932 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1933 unsigned char OpFlags = 0;
1935 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1936 // symbols should go through the PLT.
1937 if (Subtarget->isTargetELF() &&
1938 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1939 OpFlags = X86II::MO_PLT;
1940 } else if (Subtarget->isPICStyleStubAny() &&
1941 Subtarget->getDarwinVers() < 9) {
1942 // PC-relative references to external symbols should go through $stub,
1943 // unless we're building with the leopard linker or later, which
1944 // automatically synthesizes these stubs.
1945 OpFlags = X86II::MO_DARWIN_STUB;
1948 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1950 } else if (IsTailCall) {
1951 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1953 Chain = DAG.getCopyToReg(Chain, dl,
1954 DAG.getRegister(Opc, getPointerTy()),
1956 Callee = DAG.getRegister(Opc, getPointerTy());
1957 // Add register as live out.
1958 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1961 // Returns a chain & a flag for retval copy to use.
1962 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1963 SmallVector<SDValue, 8> Ops;
1966 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1967 DAG.getIntPtrConstant(0, true), InFlag);
1968 InFlag = Chain.getValue(1);
1970 // Returns a chain & a flag for retval copy to use.
1971 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1975 Ops.push_back(Chain);
1976 Ops.push_back(Callee);
1979 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1981 // Add argument registers to the end of the list so that they are known live
1983 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1984 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1985 RegsToPass[i].second.getValueType()));
1987 // Add an implicit use GOT pointer in EBX.
1988 if (!IsTailCall && Subtarget->isPICStyleGOT())
1989 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1991 // Add an implicit use of AL for x86 vararg functions.
1992 if (Is64Bit && isVarArg)
1993 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1995 if (InFlag.getNode())
1996 Ops.push_back(InFlag);
1999 assert(InFlag.getNode() &&
2000 "Flag must be set. Depend on flag being set in LowerRET");
2001 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
2002 TheCall->getVTList(), &Ops[0], Ops.size());
2004 return SDValue(Chain.getNode(), Op.getResNo());
2007 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2008 InFlag = Chain.getValue(1);
2010 // Create the CALLSEQ_END node.
2011 unsigned NumBytesForCalleeToPush;
2012 if (IsCalleePop(isVarArg, CC))
2013 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2014 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
2015 // If this is is a call to a struct-return function, the callee
2016 // pops the hidden struct pointer, so we have to push it back.
2017 // This is common for Darwin/X86, Linux & Mingw32 targets.
2018 NumBytesForCalleeToPush = 4;
2020 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2022 // Returns a flag for retval copy to use.
2023 Chain = DAG.getCALLSEQ_END(Chain,
2024 DAG.getIntPtrConstant(NumBytes, true),
2025 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2028 InFlag = Chain.getValue(1);
2030 // Handle result values, copying them out of physregs into vregs that we
2032 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
2037 //===----------------------------------------------------------------------===//
2038 // Fast Calling Convention (tail call) implementation
2039 //===----------------------------------------------------------------------===//
2041 // Like std call, callee cleans arguments, convention except that ECX is
2042 // reserved for storing the tail called function address. Only 2 registers are
2043 // free for argument passing (inreg). Tail call optimization is performed
2045 // * tailcallopt is enabled
2046 // * caller/callee are fastcc
2047 // On X86_64 architecture with GOT-style position independent code only local
2048 // (within module) calls are supported at the moment.
2049 // To keep the stack aligned according to platform abi the function
2050 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2051 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2052 // If a tail called function callee has more arguments than the caller the
2053 // caller needs to make sure that there is room to move the RETADDR to. This is
2054 // achieved by reserving an area the size of the argument delta right after the
2055 // original REtADDR, but before the saved framepointer or the spilled registers
2056 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2068 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2069 /// for a 16 byte align requirement.
2070 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2071 SelectionDAG& DAG) {
2072 MachineFunction &MF = DAG.getMachineFunction();
2073 const TargetMachine &TM = MF.getTarget();
2074 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2075 unsigned StackAlignment = TFI.getStackAlignment();
2076 uint64_t AlignMask = StackAlignment - 1;
2077 int64_t Offset = StackSize;
2078 uint64_t SlotSize = TD->getPointerSize();
2079 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2080 // Number smaller than 12 so just add the difference.
2081 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2083 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2084 Offset = ((~AlignMask) & Offset) + StackAlignment +
2085 (StackAlignment-SlotSize);
2090 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
2091 /// following the call is a return. A function is eligible if caller/callee
2092 /// calling conventions match, currently only fastcc supports tail calls, and
2093 /// the function CALL is immediatly followed by a RET.
2094 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
2096 SelectionDAG& DAG) const {
2097 if (!PerformTailCallOpt)
2100 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
2102 DAG.getMachineFunction().getFunction()->getCallingConv();
2103 unsigned CalleeCC = TheCall->getCallingConv();
2104 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC)
2112 X86TargetLowering::createFastISel(MachineFunction &mf,
2113 MachineModuleInfo *mmo,
2115 DenseMap<const Value *, unsigned> &vm,
2116 DenseMap<const BasicBlock *,
2117 MachineBasicBlock *> &bm,
2118 DenseMap<const AllocaInst *, int> &am
2120 , SmallSet<Instruction*, 8> &cil
2123 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2131 //===----------------------------------------------------------------------===//
2132 // Other Lowering Hooks
2133 //===----------------------------------------------------------------------===//
2136 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2137 MachineFunction &MF = DAG.getMachineFunction();
2138 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2139 int ReturnAddrIndex = FuncInfo->getRAIndex();
2141 if (ReturnAddrIndex == 0) {
2142 // Set up a frame object for the return address.
2143 uint64_t SlotSize = TD->getPointerSize();
2144 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2145 FuncInfo->setRAIndex(ReturnAddrIndex);
2148 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2152 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2153 /// specific condition code, returning the condition code and the LHS/RHS of the
2154 /// comparison to make.
2155 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2156 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2158 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2159 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2160 // X > -1 -> X == 0, jump !sign.
2161 RHS = DAG.getConstant(0, RHS.getValueType());
2162 return X86::COND_NS;
2163 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2164 // X < 0 -> X == 0, jump on sign.
2166 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2168 RHS = DAG.getConstant(0, RHS.getValueType());
2169 return X86::COND_LE;
2173 switch (SetCCOpcode) {
2174 default: llvm_unreachable("Invalid integer condition!");
2175 case ISD::SETEQ: return X86::COND_E;
2176 case ISD::SETGT: return X86::COND_G;
2177 case ISD::SETGE: return X86::COND_GE;
2178 case ISD::SETLT: return X86::COND_L;
2179 case ISD::SETLE: return X86::COND_LE;
2180 case ISD::SETNE: return X86::COND_NE;
2181 case ISD::SETULT: return X86::COND_B;
2182 case ISD::SETUGT: return X86::COND_A;
2183 case ISD::SETULE: return X86::COND_BE;
2184 case ISD::SETUGE: return X86::COND_AE;
2188 // First determine if it is required or is profitable to flip the operands.
2190 // If LHS is a foldable load, but RHS is not, flip the condition.
2191 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2192 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2193 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2194 std::swap(LHS, RHS);
2197 switch (SetCCOpcode) {
2203 std::swap(LHS, RHS);
2207 // On a floating point condition, the flags are set as follows:
2209 // 0 | 0 | 0 | X > Y
2210 // 0 | 0 | 1 | X < Y
2211 // 1 | 0 | 0 | X == Y
2212 // 1 | 1 | 1 | unordered
2213 switch (SetCCOpcode) {
2214 default: llvm_unreachable("Condcode should be pre-legalized away");
2216 case ISD::SETEQ: return X86::COND_E;
2217 case ISD::SETOLT: // flipped
2219 case ISD::SETGT: return X86::COND_A;
2220 case ISD::SETOLE: // flipped
2222 case ISD::SETGE: return X86::COND_AE;
2223 case ISD::SETUGT: // flipped
2225 case ISD::SETLT: return X86::COND_B;
2226 case ISD::SETUGE: // flipped
2228 case ISD::SETLE: return X86::COND_BE;
2230 case ISD::SETNE: return X86::COND_NE;
2231 case ISD::SETUO: return X86::COND_P;
2232 case ISD::SETO: return X86::COND_NP;
2236 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2237 /// code. Current x86 isa includes the following FP cmov instructions:
2238 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2239 static bool hasFPCMov(unsigned X86CC) {
2255 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2256 /// the specified range (L, H].
2257 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2258 return (Val < 0) || (Val >= Low && Val < Hi);
2261 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2262 /// specified value.
2263 static bool isUndefOrEqual(int Val, int CmpVal) {
2264 if (Val < 0 || Val == CmpVal)
2269 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2270 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2271 /// the second operand.
2272 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2273 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2274 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2275 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2276 return (Mask[0] < 2 && Mask[1] < 2);
2280 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2281 SmallVector<int, 8> M;
2283 return ::isPSHUFDMask(M, N->getValueType(0));
2286 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2287 /// is suitable for input to PSHUFHW.
2288 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2289 if (VT != MVT::v8i16)
2292 // Lower quadword copied in order or undef.
2293 for (int i = 0; i != 4; ++i)
2294 if (Mask[i] >= 0 && Mask[i] != i)
2297 // Upper quadword shuffled.
2298 for (int i = 4; i != 8; ++i)
2299 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2305 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2306 SmallVector<int, 8> M;
2308 return ::isPSHUFHWMask(M, N->getValueType(0));
2311 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2312 /// is suitable for input to PSHUFLW.
2313 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2314 if (VT != MVT::v8i16)
2317 // Upper quadword copied in order.
2318 for (int i = 4; i != 8; ++i)
2319 if (Mask[i] >= 0 && Mask[i] != i)
2322 // Lower quadword shuffled.
2323 for (int i = 0; i != 4; ++i)
2330 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2331 SmallVector<int, 8> M;
2333 return ::isPSHUFLWMask(M, N->getValueType(0));
2336 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2337 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2338 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2339 int NumElems = VT.getVectorNumElements();
2340 if (NumElems != 2 && NumElems != 4)
2343 int Half = NumElems / 2;
2344 for (int i = 0; i < Half; ++i)
2345 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2347 for (int i = Half; i < NumElems; ++i)
2348 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2354 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2355 SmallVector<int, 8> M;
2357 return ::isSHUFPMask(M, N->getValueType(0));
2360 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2361 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2362 /// half elements to come from vector 1 (which would equal the dest.) and
2363 /// the upper half to come from vector 2.
2364 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2365 int NumElems = VT.getVectorNumElements();
2367 if (NumElems != 2 && NumElems != 4)
2370 int Half = NumElems / 2;
2371 for (int i = 0; i < Half; ++i)
2372 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2374 for (int i = Half; i < NumElems; ++i)
2375 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2380 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2381 SmallVector<int, 8> M;
2383 return isCommutedSHUFPMask(M, N->getValueType(0));
2386 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2387 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2388 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2389 if (N->getValueType(0).getVectorNumElements() != 4)
2392 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2393 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2394 isUndefOrEqual(N->getMaskElt(1), 7) &&
2395 isUndefOrEqual(N->getMaskElt(2), 2) &&
2396 isUndefOrEqual(N->getMaskElt(3), 3);
2399 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2400 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2401 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2402 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2404 if (NumElems != 2 && NumElems != 4)
2407 for (unsigned i = 0; i < NumElems/2; ++i)
2408 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2411 for (unsigned i = NumElems/2; i < NumElems; ++i)
2412 if (!isUndefOrEqual(N->getMaskElt(i), i))
2418 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2419 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2421 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2422 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2424 if (NumElems != 2 && NumElems != 4)
2427 for (unsigned i = 0; i < NumElems/2; ++i)
2428 if (!isUndefOrEqual(N->getMaskElt(i), i))
2431 for (unsigned i = 0; i < NumElems/2; ++i)
2432 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2438 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2439 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2441 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2442 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2447 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2448 isUndefOrEqual(N->getMaskElt(1), 3) &&
2449 isUndefOrEqual(N->getMaskElt(2), 2) &&
2450 isUndefOrEqual(N->getMaskElt(3), 3);
2453 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2454 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2455 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2456 bool V2IsSplat = false) {
2457 int NumElts = VT.getVectorNumElements();
2458 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2461 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2463 int BitI1 = Mask[i+1];
2464 if (!isUndefOrEqual(BitI, j))
2467 if (!isUndefOrEqual(BitI1, NumElts))
2470 if (!isUndefOrEqual(BitI1, j + NumElts))
2477 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2478 SmallVector<int, 8> M;
2480 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2483 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2484 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2485 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
2486 bool V2IsSplat = false) {
2487 int NumElts = VT.getVectorNumElements();
2488 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2491 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2493 int BitI1 = Mask[i+1];
2494 if (!isUndefOrEqual(BitI, j + NumElts/2))
2497 if (isUndefOrEqual(BitI1, NumElts))
2500 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2507 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2508 SmallVector<int, 8> M;
2510 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2513 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2514 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2516 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2517 int NumElems = VT.getVectorNumElements();
2518 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2521 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2523 int BitI1 = Mask[i+1];
2524 if (!isUndefOrEqual(BitI, j))
2526 if (!isUndefOrEqual(BitI1, j))
2532 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2533 SmallVector<int, 8> M;
2535 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2538 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2539 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2541 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2542 int NumElems = VT.getVectorNumElements();
2543 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2546 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2548 int BitI1 = Mask[i+1];
2549 if (!isUndefOrEqual(BitI, j))
2551 if (!isUndefOrEqual(BitI1, j))
2557 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2558 SmallVector<int, 8> M;
2560 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2563 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2564 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2565 /// MOVSD, and MOVD, i.e. setting the lowest element.
2566 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2567 if (VT.getVectorElementType().getSizeInBits() < 32)
2570 int NumElts = VT.getVectorNumElements();
2572 if (!isUndefOrEqual(Mask[0], NumElts))
2575 for (int i = 1; i < NumElts; ++i)
2576 if (!isUndefOrEqual(Mask[i], i))
2582 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2583 SmallVector<int, 8> M;
2585 return ::isMOVLMask(M, N->getValueType(0));
2588 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2590 /// element of vector 2 and the other elements to come from vector 1 in order.
2591 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2592 bool V2IsSplat = false, bool V2IsUndef = false) {
2593 int NumOps = VT.getVectorNumElements();
2594 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2597 if (!isUndefOrEqual(Mask[0], 0))
2600 for (int i = 1; i < NumOps; ++i)
2601 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2602 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2603 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2609 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2610 bool V2IsUndef = false) {
2611 SmallVector<int, 8> M;
2613 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2616 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2617 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2618 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2619 if (N->getValueType(0).getVectorNumElements() != 4)
2622 // Expect 1, 1, 3, 3
2623 for (unsigned i = 0; i < 2; ++i) {
2624 int Elt = N->getMaskElt(i);
2625 if (Elt >= 0 && Elt != 1)
2630 for (unsigned i = 2; i < 4; ++i) {
2631 int Elt = N->getMaskElt(i);
2632 if (Elt >= 0 && Elt != 3)
2637 // Don't use movshdup if it can be done with a shufps.
2638 // FIXME: verify that matching u, u, 3, 3 is what we want.
2642 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2643 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2644 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2645 if (N->getValueType(0).getVectorNumElements() != 4)
2648 // Expect 0, 0, 2, 2
2649 for (unsigned i = 0; i < 2; ++i)
2650 if (N->getMaskElt(i) > 0)
2654 for (unsigned i = 2; i < 4; ++i) {
2655 int Elt = N->getMaskElt(i);
2656 if (Elt >= 0 && Elt != 2)
2661 // Don't use movsldup if it can be done with a shufps.
2665 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2666 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2667 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2668 int e = N->getValueType(0).getVectorNumElements() / 2;
2670 for (int i = 0; i < e; ++i)
2671 if (!isUndefOrEqual(N->getMaskElt(i), i))
2673 for (int i = 0; i < e; ++i)
2674 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2679 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2680 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2682 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2683 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2684 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2686 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2688 for (int i = 0; i < NumOperands; ++i) {
2689 int Val = SVOp->getMaskElt(NumOperands-i-1);
2690 if (Val < 0) Val = 0;
2691 if (Val >= NumOperands) Val -= NumOperands;
2693 if (i != NumOperands - 1)
2699 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2700 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2702 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2705 // 8 nodes, but we only care about the last 4.
2706 for (unsigned i = 7; i >= 4; --i) {
2707 int Val = SVOp->getMaskElt(i);
2716 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2717 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2719 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2720 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2722 // 8 nodes, but we only care about the first 4.
2723 for (int i = 3; i >= 0; --i) {
2724 int Val = SVOp->getMaskElt(i);
2733 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2734 /// their permute mask.
2735 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2736 SelectionDAG &DAG) {
2737 MVT VT = SVOp->getValueType(0);
2738 unsigned NumElems = VT.getVectorNumElements();
2739 SmallVector<int, 8> MaskVec;
2741 for (unsigned i = 0; i != NumElems; ++i) {
2742 int idx = SVOp->getMaskElt(i);
2744 MaskVec.push_back(idx);
2745 else if (idx < (int)NumElems)
2746 MaskVec.push_back(idx + NumElems);
2748 MaskVec.push_back(idx - NumElems);
2750 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2751 SVOp->getOperand(0), &MaskVec[0]);
2754 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2755 /// the two vector operands have swapped position.
2756 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
2757 unsigned NumElems = VT.getVectorNumElements();
2758 for (unsigned i = 0; i != NumElems; ++i) {
2762 else if (idx < (int)NumElems)
2763 Mask[i] = idx + NumElems;
2765 Mask[i] = idx - NumElems;
2769 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2770 /// match movhlps. The lower half elements should come from upper half of
2771 /// V1 (and in order), and the upper half elements should come from the upper
2772 /// half of V2 (and in order).
2773 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2774 if (Op->getValueType(0).getVectorNumElements() != 4)
2776 for (unsigned i = 0, e = 2; i != e; ++i)
2777 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2779 for (unsigned i = 2; i != 4; ++i)
2780 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2785 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2786 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2788 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2789 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2791 N = N->getOperand(0).getNode();
2792 if (!ISD::isNON_EXTLoad(N))
2795 *LD = cast<LoadSDNode>(N);
2799 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2800 /// match movlp{s|d}. The lower half elements should come from lower half of
2801 /// V1 (and in order), and the upper half elements should come from the upper
2802 /// half of V2 (and in order). And since V1 will become the source of the
2803 /// MOVLP, it must be either a vector load or a scalar load to vector.
2804 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2805 ShuffleVectorSDNode *Op) {
2806 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2808 // Is V2 is a vector load, don't do this transformation. We will try to use
2809 // load folding shufps op.
2810 if (ISD::isNON_EXTLoad(V2))
2813 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2815 if (NumElems != 2 && NumElems != 4)
2817 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2818 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2820 for (unsigned i = NumElems/2; i != NumElems; ++i)
2821 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2826 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2828 static bool isSplatVector(SDNode *N) {
2829 if (N->getOpcode() != ISD::BUILD_VECTOR)
2832 SDValue SplatValue = N->getOperand(0);
2833 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2834 if (N->getOperand(i) != SplatValue)
2839 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2841 static inline bool isZeroNode(SDValue Elt) {
2842 return ((isa<ConstantSDNode>(Elt) &&
2843 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2844 (isa<ConstantFPSDNode>(Elt) &&
2845 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2848 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2849 /// to an zero vector.
2850 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2851 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2852 SDValue V1 = N->getOperand(0);
2853 SDValue V2 = N->getOperand(1);
2854 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2855 for (unsigned i = 0; i != NumElems; ++i) {
2856 int Idx = N->getMaskElt(i);
2857 if (Idx >= (int)NumElems) {
2858 unsigned Opc = V2.getOpcode();
2859 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2861 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems)))
2863 } else if (Idx >= 0) {
2864 unsigned Opc = V1.getOpcode();
2865 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2867 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx)))
2874 /// getZeroVector - Returns a vector of specified type with all zero elements.
2876 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2878 assert(VT.isVector() && "Expected a vector type");
2880 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2881 // type. This ensures they get CSE'd.
2883 if (VT.getSizeInBits() == 64) { // MMX
2884 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2885 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2886 } else if (HasSSE2) { // SSE2
2887 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2888 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2890 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2891 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2893 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2896 /// getOnesVector - Returns a vector of specified type with all bits set.
2898 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2899 assert(VT.isVector() && "Expected a vector type");
2901 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2902 // type. This ensures they get CSE'd.
2903 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2905 if (VT.getSizeInBits() == 64) // MMX
2906 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2908 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2909 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2913 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2914 /// that point to V2 points to its first element.
2915 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2916 MVT VT = SVOp->getValueType(0);
2917 unsigned NumElems = VT.getVectorNumElements();
2919 bool Changed = false;
2920 SmallVector<int, 8> MaskVec;
2921 SVOp->getMask(MaskVec);
2923 for (unsigned i = 0; i != NumElems; ++i) {
2924 if (MaskVec[i] > (int)NumElems) {
2925 MaskVec[i] = NumElems;
2930 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2931 SVOp->getOperand(1), &MaskVec[0]);
2932 return SDValue(SVOp, 0);
2935 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2936 /// operation of specified width.
2937 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2939 unsigned NumElems = VT.getVectorNumElements();
2940 SmallVector<int, 8> Mask;
2941 Mask.push_back(NumElems);
2942 for (unsigned i = 1; i != NumElems; ++i)
2944 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2947 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2948 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2950 unsigned NumElems = VT.getVectorNumElements();
2951 SmallVector<int, 8> Mask;
2952 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2954 Mask.push_back(i + NumElems);
2956 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2959 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2960 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2962 unsigned NumElems = VT.getVectorNumElements();
2963 unsigned Half = NumElems/2;
2964 SmallVector<int, 8> Mask;
2965 for (unsigned i = 0; i != Half; ++i) {
2966 Mask.push_back(i + Half);
2967 Mask.push_back(i + NumElems + Half);
2969 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2972 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2973 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2975 if (SV->getValueType(0).getVectorNumElements() <= 4)
2976 return SDValue(SV, 0);
2978 MVT PVT = MVT::v4f32;
2979 MVT VT = SV->getValueType(0);
2980 DebugLoc dl = SV->getDebugLoc();
2981 SDValue V1 = SV->getOperand(0);
2982 int NumElems = VT.getVectorNumElements();
2983 int EltNo = SV->getSplatIndex();
2985 // unpack elements to the correct location
2986 while (NumElems > 4) {
2987 if (EltNo < NumElems/2) {
2988 V1 = getUnpackl(DAG, dl, VT, V1, V1);
2990 V1 = getUnpackh(DAG, dl, VT, V1, V1);
2991 EltNo -= NumElems/2;
2996 // Perform the splat.
2997 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
2998 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
2999 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3000 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3003 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3004 /// vector of zero or undef vector. This produces a shuffle where the low
3005 /// element of V2 is swizzled into the zero/undef vector, landing at element
3006 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3007 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3008 bool isZero, bool HasSSE2,
3009 SelectionDAG &DAG) {
3010 MVT VT = V2.getValueType();
3012 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3013 unsigned NumElems = VT.getVectorNumElements();
3014 SmallVector<int, 16> MaskVec;
3015 for (unsigned i = 0; i != NumElems; ++i)
3016 // If this is the insertion idx, put the low elt of V2 here.
3017 MaskVec.push_back(i == Idx ? NumElems : i);
3018 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3021 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3022 /// a shuffle that is zero.
3024 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3025 bool Low, SelectionDAG &DAG) {
3026 unsigned NumZeros = 0;
3027 for (int i = 0; i < NumElems; ++i) {
3028 unsigned Index = Low ? i : NumElems-i-1;
3029 int Idx = SVOp->getMaskElt(Index);
3034 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3035 if (Elt.getNode() && isZeroNode(Elt))
3043 /// isVectorShift - Returns true if the shuffle can be implemented as a
3044 /// logical left or right shift of a vector.
3045 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3046 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3047 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3048 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3051 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3054 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3058 bool SeenV1 = false;
3059 bool SeenV2 = false;
3060 for (int i = NumZeros; i < NumElems; ++i) {
3061 int Val = isLeft ? (i - NumZeros) : i;
3062 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3074 if (SeenV1 && SeenV2)
3077 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3083 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3085 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3086 unsigned NumNonZero, unsigned NumZero,
3087 SelectionDAG &DAG, TargetLowering &TLI) {
3091 DebugLoc dl = Op.getDebugLoc();
3094 for (unsigned i = 0; i < 16; ++i) {
3095 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3096 if (ThisIsNonZero && First) {
3098 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3100 V = DAG.getUNDEF(MVT::v8i16);
3105 SDValue ThisElt(0, 0), LastElt(0, 0);
3106 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3107 if (LastIsNonZero) {
3108 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3109 MVT::i16, Op.getOperand(i-1));
3111 if (ThisIsNonZero) {
3112 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3113 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3114 ThisElt, DAG.getConstant(8, MVT::i8));
3116 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3120 if (ThisElt.getNode())
3121 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3122 DAG.getIntPtrConstant(i/2));
3126 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3129 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3131 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3132 unsigned NumNonZero, unsigned NumZero,
3133 SelectionDAG &DAG, TargetLowering &TLI) {
3137 DebugLoc dl = Op.getDebugLoc();
3140 for (unsigned i = 0; i < 8; ++i) {
3141 bool isNonZero = (NonZeros & (1 << i)) != 0;
3145 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3147 V = DAG.getUNDEF(MVT::v8i16);
3150 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3151 MVT::v8i16, V, Op.getOperand(i),
3152 DAG.getIntPtrConstant(i));
3159 /// getVShift - Return a vector logical shift node.
3161 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3162 unsigned NumBits, SelectionDAG &DAG,
3163 const TargetLowering &TLI, DebugLoc dl) {
3164 bool isMMX = VT.getSizeInBits() == 64;
3165 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3166 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3167 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3168 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3169 DAG.getNode(Opc, dl, ShVT, SrcOp,
3170 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3174 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3175 DebugLoc dl = Op.getDebugLoc();
3176 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3177 if (ISD::isBuildVectorAllZeros(Op.getNode())
3178 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3179 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3180 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3181 // eliminated on x86-32 hosts.
3182 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3185 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3186 return getOnesVector(Op.getValueType(), DAG, dl);
3187 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3190 MVT VT = Op.getValueType();
3191 MVT EVT = VT.getVectorElementType();
3192 unsigned EVTBits = EVT.getSizeInBits();
3194 unsigned NumElems = Op.getNumOperands();
3195 unsigned NumZero = 0;
3196 unsigned NumNonZero = 0;
3197 unsigned NonZeros = 0;
3198 bool IsAllConstants = true;
3199 SmallSet<SDValue, 8> Values;
3200 for (unsigned i = 0; i < NumElems; ++i) {
3201 SDValue Elt = Op.getOperand(i);
3202 if (Elt.getOpcode() == ISD::UNDEF)
3205 if (Elt.getOpcode() != ISD::Constant &&
3206 Elt.getOpcode() != ISD::ConstantFP)
3207 IsAllConstants = false;
3208 if (isZeroNode(Elt))
3211 NonZeros |= (1 << i);
3216 if (NumNonZero == 0) {
3217 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3218 return DAG.getUNDEF(VT);
3221 // Special case for single non-zero, non-undef, element.
3222 if (NumNonZero == 1) {
3223 unsigned Idx = CountTrailingZeros_32(NonZeros);
3224 SDValue Item = Op.getOperand(Idx);
3226 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3227 // the value are obviously zero, truncate the value to i32 and do the
3228 // insertion that way. Only do this if the value is non-constant or if the
3229 // value is a constant being inserted into element 0. It is cheaper to do
3230 // a constant pool load than it is to do a movd + shuffle.
3231 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3232 (!IsAllConstants || Idx == 0)) {
3233 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3234 // Handle MMX and SSE both.
3235 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3236 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3238 // Truncate the value (which may itself be a constant) to i32, and
3239 // convert it to a vector with movd (S2V+shuffle to zero extend).
3240 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3241 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3242 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3243 Subtarget->hasSSE2(), DAG);
3245 // Now we have our 32-bit value zero extended in the low element of
3246 // a vector. If Idx != 0, swizzle it into place.
3248 SmallVector<int, 4> Mask;
3249 Mask.push_back(Idx);
3250 for (unsigned i = 1; i != VecElts; ++i)
3252 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3253 DAG.getUNDEF(Item.getValueType()),
3256 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3260 // If we have a constant or non-constant insertion into the low element of
3261 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3262 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3263 // depending on what the source datatype is.
3266 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3267 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
3268 (EVT == MVT::i64 && Subtarget->is64Bit())) {
3269 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3270 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3271 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3273 } else if (EVT == MVT::i16 || EVT == MVT::i8) {
3274 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3275 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3276 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3277 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3278 Subtarget->hasSSE2(), DAG);
3279 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3283 // Is it a vector logical left shift?
3284 if (NumElems == 2 && Idx == 1 &&
3285 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3286 unsigned NumBits = VT.getSizeInBits();
3287 return getVShift(true, VT,
3288 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3289 VT, Op.getOperand(1)),
3290 NumBits/2, DAG, *this, dl);
3293 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3296 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3297 // is a non-constant being inserted into an element other than the low one,
3298 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3299 // movd/movss) to move this into the low element, then shuffle it into
3301 if (EVTBits == 32) {
3302 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3304 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3305 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3306 Subtarget->hasSSE2(), DAG);
3307 SmallVector<int, 8> MaskVec;
3308 for (unsigned i = 0; i < NumElems; i++)
3309 MaskVec.push_back(i == Idx ? 0 : 1);
3310 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3314 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3315 if (Values.size() == 1)
3318 // A vector full of immediates; various special cases are already
3319 // handled, so this is best done with a single constant-pool load.
3323 // Let legalizer expand 2-wide build_vectors.
3324 if (EVTBits == 64) {
3325 if (NumNonZero == 1) {
3326 // One half is zero or undef.
3327 unsigned Idx = CountTrailingZeros_32(NonZeros);
3328 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3329 Op.getOperand(Idx));
3330 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3331 Subtarget->hasSSE2(), DAG);
3336 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3337 if (EVTBits == 8 && NumElems == 16) {
3338 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3340 if (V.getNode()) return V;
3343 if (EVTBits == 16 && NumElems == 8) {
3344 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3346 if (V.getNode()) return V;
3349 // If element VT is == 32 bits, turn it into a number of shuffles.
3350 SmallVector<SDValue, 8> V;
3352 if (NumElems == 4 && NumZero > 0) {
3353 for (unsigned i = 0; i < 4; ++i) {
3354 bool isZero = !(NonZeros & (1 << i));
3356 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3358 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3361 for (unsigned i = 0; i < 2; ++i) {
3362 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3365 V[i] = V[i*2]; // Must be a zero vector.
3368 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3371 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3374 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3379 SmallVector<int, 8> MaskVec;
3380 bool Reverse = (NonZeros & 0x3) == 2;
3381 for (unsigned i = 0; i < 2; ++i)
3382 MaskVec.push_back(Reverse ? 1-i : i);
3383 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3384 for (unsigned i = 0; i < 2; ++i)
3385 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3386 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3389 if (Values.size() > 2) {
3390 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3391 // values to be inserted is equal to the number of elements, in which case
3392 // use the unpack code below in the hopes of matching the consecutive elts
3393 // load merge pattern for shuffles.
3394 // FIXME: We could probably just check that here directly.
3395 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3396 getSubtarget()->hasSSE41()) {
3397 V[0] = DAG.getUNDEF(VT);
3398 for (unsigned i = 0; i < NumElems; ++i)
3399 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3400 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3401 Op.getOperand(i), DAG.getIntPtrConstant(i));
3404 // Expand into a number of unpckl*.
3406 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3407 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3408 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3409 for (unsigned i = 0; i < NumElems; ++i)
3410 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3412 while (NumElems != 0) {
3413 for (unsigned i = 0; i < NumElems; ++i)
3414 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3423 // v8i16 shuffles - Prefer shuffles in the following order:
3424 // 1. [all] pshuflw, pshufhw, optional move
3425 // 2. [ssse3] 1 x pshufb
3426 // 3. [ssse3] 2 x pshufb + 1 x por
3427 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3429 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3430 SelectionDAG &DAG, X86TargetLowering &TLI) {
3431 SDValue V1 = SVOp->getOperand(0);
3432 SDValue V2 = SVOp->getOperand(1);
3433 DebugLoc dl = SVOp->getDebugLoc();
3434 SmallVector<int, 8> MaskVals;
3436 // Determine if more than 1 of the words in each of the low and high quadwords
3437 // of the result come from the same quadword of one of the two inputs. Undef
3438 // mask values count as coming from any quadword, for better codegen.
3439 SmallVector<unsigned, 4> LoQuad(4);
3440 SmallVector<unsigned, 4> HiQuad(4);
3441 BitVector InputQuads(4);
3442 for (unsigned i = 0; i < 8; ++i) {
3443 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3444 int EltIdx = SVOp->getMaskElt(i);
3445 MaskVals.push_back(EltIdx);
3454 InputQuads.set(EltIdx / 4);
3457 int BestLoQuad = -1;
3458 unsigned MaxQuad = 1;
3459 for (unsigned i = 0; i < 4; ++i) {
3460 if (LoQuad[i] > MaxQuad) {
3462 MaxQuad = LoQuad[i];
3466 int BestHiQuad = -1;
3468 for (unsigned i = 0; i < 4; ++i) {
3469 if (HiQuad[i] > MaxQuad) {
3471 MaxQuad = HiQuad[i];
3475 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3476 // of the two input vectors, shuffle them into one input vector so only a
3477 // single pshufb instruction is necessary. If There are more than 2 input
3478 // quads, disable the next transformation since it does not help SSSE3.
3479 bool V1Used = InputQuads[0] || InputQuads[1];
3480 bool V2Used = InputQuads[2] || InputQuads[3];
3481 if (TLI.getSubtarget()->hasSSSE3()) {
3482 if (InputQuads.count() == 2 && V1Used && V2Used) {
3483 BestLoQuad = InputQuads.find_first();
3484 BestHiQuad = InputQuads.find_next(BestLoQuad);
3486 if (InputQuads.count() > 2) {
3492 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3493 // the shuffle mask. If a quad is scored as -1, that means that it contains
3494 // words from all 4 input quadwords.
3496 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3497 SmallVector<int, 8> MaskV;
3498 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3499 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3500 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3501 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3502 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3503 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3505 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3506 // source words for the shuffle, to aid later transformations.
3507 bool AllWordsInNewV = true;
3508 bool InOrder[2] = { true, true };
3509 for (unsigned i = 0; i != 8; ++i) {
3510 int idx = MaskVals[i];
3512 InOrder[i/4] = false;
3513 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3515 AllWordsInNewV = false;
3519 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3520 if (AllWordsInNewV) {
3521 for (int i = 0; i != 8; ++i) {
3522 int idx = MaskVals[i];
3525 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3526 if ((idx != i) && idx < 4)
3528 if ((idx != i) && idx > 3)
3537 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3538 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3539 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3540 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3541 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3545 // If we have SSSE3, and all words of the result are from 1 input vector,
3546 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3547 // is present, fall back to case 4.
3548 if (TLI.getSubtarget()->hasSSSE3()) {
3549 SmallVector<SDValue,16> pshufbMask;
3551 // If we have elements from both input vectors, set the high bit of the
3552 // shuffle mask element to zero out elements that come from V2 in the V1
3553 // mask, and elements that come from V1 in the V2 mask, so that the two
3554 // results can be OR'd together.
3555 bool TwoInputs = V1Used && V2Used;
3556 for (unsigned i = 0; i != 8; ++i) {
3557 int EltIdx = MaskVals[i] * 2;
3558 if (TwoInputs && (EltIdx >= 16)) {
3559 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3560 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3563 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3564 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3566 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3567 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3568 DAG.getNode(ISD::BUILD_VECTOR, dl,
3569 MVT::v16i8, &pshufbMask[0], 16));
3571 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3573 // Calculate the shuffle mask for the second input, shuffle it, and
3574 // OR it with the first shuffled input.
3576 for (unsigned i = 0; i != 8; ++i) {
3577 int EltIdx = MaskVals[i] * 2;
3579 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3580 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3583 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3584 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3586 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3587 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3588 DAG.getNode(ISD::BUILD_VECTOR, dl,
3589 MVT::v16i8, &pshufbMask[0], 16));
3590 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3591 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3594 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3595 // and update MaskVals with new element order.
3596 BitVector InOrder(8);
3597 if (BestLoQuad >= 0) {
3598 SmallVector<int, 8> MaskV;
3599 for (int i = 0; i != 4; ++i) {
3600 int idx = MaskVals[i];
3602 MaskV.push_back(-1);
3604 } else if ((idx / 4) == BestLoQuad) {
3605 MaskV.push_back(idx & 3);
3608 MaskV.push_back(-1);
3611 for (unsigned i = 4; i != 8; ++i)
3613 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3617 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3618 // and update MaskVals with the new element order.
3619 if (BestHiQuad >= 0) {
3620 SmallVector<int, 8> MaskV;
3621 for (unsigned i = 0; i != 4; ++i)
3623 for (unsigned i = 4; i != 8; ++i) {
3624 int idx = MaskVals[i];
3626 MaskV.push_back(-1);
3628 } else if ((idx / 4) == BestHiQuad) {
3629 MaskV.push_back((idx & 3) + 4);
3632 MaskV.push_back(-1);
3635 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3639 // In case BestHi & BestLo were both -1, which means each quadword has a word
3640 // from each of the four input quadwords, calculate the InOrder bitvector now
3641 // before falling through to the insert/extract cleanup.
3642 if (BestLoQuad == -1 && BestHiQuad == -1) {
3644 for (int i = 0; i != 8; ++i)
3645 if (MaskVals[i] < 0 || MaskVals[i] == i)
3649 // The other elements are put in the right place using pextrw and pinsrw.
3650 for (unsigned i = 0; i != 8; ++i) {
3653 int EltIdx = MaskVals[i];
3656 SDValue ExtOp = (EltIdx < 8)
3657 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3658 DAG.getIntPtrConstant(EltIdx))
3659 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3660 DAG.getIntPtrConstant(EltIdx - 8));
3661 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3662 DAG.getIntPtrConstant(i));
3667 // v16i8 shuffles - Prefer shuffles in the following order:
3668 // 1. [ssse3] 1 x pshufb
3669 // 2. [ssse3] 2 x pshufb + 1 x por
3670 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3672 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3673 SelectionDAG &DAG, X86TargetLowering &TLI) {
3674 SDValue V1 = SVOp->getOperand(0);
3675 SDValue V2 = SVOp->getOperand(1);
3676 DebugLoc dl = SVOp->getDebugLoc();
3677 SmallVector<int, 16> MaskVals;
3678 SVOp->getMask(MaskVals);
3680 // If we have SSSE3, case 1 is generated when all result bytes come from
3681 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3682 // present, fall back to case 3.
3683 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3686 for (unsigned i = 0; i < 16; ++i) {
3687 int EltIdx = MaskVals[i];
3696 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3697 if (TLI.getSubtarget()->hasSSSE3()) {
3698 SmallVector<SDValue,16> pshufbMask;
3700 // If all result elements are from one input vector, then only translate
3701 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3703 // Otherwise, we have elements from both input vectors, and must zero out
3704 // elements that come from V2 in the first mask, and V1 in the second mask
3705 // so that we can OR them together.
3706 bool TwoInputs = !(V1Only || V2Only);
3707 for (unsigned i = 0; i != 16; ++i) {
3708 int EltIdx = MaskVals[i];
3709 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3710 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3713 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3715 // If all the elements are from V2, assign it to V1 and return after
3716 // building the first pshufb.
3719 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3720 DAG.getNode(ISD::BUILD_VECTOR, dl,
3721 MVT::v16i8, &pshufbMask[0], 16));
3725 // Calculate the shuffle mask for the second input, shuffle it, and
3726 // OR it with the first shuffled input.
3728 for (unsigned i = 0; i != 16; ++i) {
3729 int EltIdx = MaskVals[i];
3731 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3734 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3736 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3737 DAG.getNode(ISD::BUILD_VECTOR, dl,
3738 MVT::v16i8, &pshufbMask[0], 16));
3739 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3742 // No SSSE3 - Calculate in place words and then fix all out of place words
3743 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3744 // the 16 different words that comprise the two doublequadword input vectors.
3745 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3746 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3747 SDValue NewV = V2Only ? V2 : V1;
3748 for (int i = 0; i != 8; ++i) {
3749 int Elt0 = MaskVals[i*2];
3750 int Elt1 = MaskVals[i*2+1];
3752 // This word of the result is all undef, skip it.
3753 if (Elt0 < 0 && Elt1 < 0)
3756 // This word of the result is already in the correct place, skip it.
3757 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3759 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3762 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3763 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3766 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3767 // using a single extract together, load it and store it.
3768 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3769 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3770 DAG.getIntPtrConstant(Elt1 / 2));
3771 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3772 DAG.getIntPtrConstant(i));
3776 // If Elt1 is defined, extract it from the appropriate source. If the
3777 // source byte is not also odd, shift the extracted word left 8 bits
3778 // otherwise clear the bottom 8 bits if we need to do an or.
3780 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3781 DAG.getIntPtrConstant(Elt1 / 2));
3782 if ((Elt1 & 1) == 0)
3783 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3784 DAG.getConstant(8, TLI.getShiftAmountTy()));
3786 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3787 DAG.getConstant(0xFF00, MVT::i16));
3789 // If Elt0 is defined, extract it from the appropriate source. If the
3790 // source byte is not also even, shift the extracted word right 8 bits. If
3791 // Elt1 was also defined, OR the extracted values together before
3792 // inserting them in the result.
3794 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3795 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3796 if ((Elt0 & 1) != 0)
3797 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3798 DAG.getConstant(8, TLI.getShiftAmountTy()));
3800 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3801 DAG.getConstant(0x00FF, MVT::i16));
3802 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3805 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3806 DAG.getIntPtrConstant(i));
3808 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3811 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3812 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3813 /// done when every pair / quad of shuffle mask elements point to elements in
3814 /// the right sequence. e.g.
3815 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3817 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3819 TargetLowering &TLI, DebugLoc dl) {
3820 MVT VT = SVOp->getValueType(0);
3821 SDValue V1 = SVOp->getOperand(0);
3822 SDValue V2 = SVOp->getOperand(1);
3823 unsigned NumElems = VT.getVectorNumElements();
3824 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3825 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3826 MVT MaskEltVT = MaskVT.getVectorElementType();
3828 switch (VT.getSimpleVT()) {
3829 default: assert(false && "Unexpected!");
3830 case MVT::v4f32: NewVT = MVT::v2f64; break;
3831 case MVT::v4i32: NewVT = MVT::v2i64; break;
3832 case MVT::v8i16: NewVT = MVT::v4i32; break;
3833 case MVT::v16i8: NewVT = MVT::v4i32; break;
3836 if (NewWidth == 2) {
3842 int Scale = NumElems / NewWidth;
3843 SmallVector<int, 8> MaskVec;
3844 for (unsigned i = 0; i < NumElems; i += Scale) {
3846 for (int j = 0; j < Scale; ++j) {
3847 int EltIdx = SVOp->getMaskElt(i+j);
3851 StartIdx = EltIdx - (EltIdx % Scale);
3852 if (EltIdx != StartIdx + j)
3856 MaskVec.push_back(-1);
3858 MaskVec.push_back(StartIdx / Scale);
3861 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3862 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3863 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3866 /// getVZextMovL - Return a zero-extending vector move low node.
3868 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3869 SDValue SrcOp, SelectionDAG &DAG,
3870 const X86Subtarget *Subtarget, DebugLoc dl) {
3871 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3872 LoadSDNode *LD = NULL;
3873 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3874 LD = dyn_cast<LoadSDNode>(SrcOp);
3876 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3878 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3879 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3880 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3881 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3882 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3884 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3885 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3886 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3887 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3895 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3896 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3897 DAG.getNode(ISD::BIT_CONVERT, dl,
3901 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3904 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3905 SDValue V1 = SVOp->getOperand(0);
3906 SDValue V2 = SVOp->getOperand(1);
3907 DebugLoc dl = SVOp->getDebugLoc();
3908 MVT VT = SVOp->getValueType(0);
3910 SmallVector<std::pair<int, int>, 8> Locs;
3912 SmallVector<int, 8> Mask1(4U, -1);
3913 SmallVector<int, 8> PermMask;
3914 SVOp->getMask(PermMask);
3918 for (unsigned i = 0; i != 4; ++i) {
3919 int Idx = PermMask[i];
3921 Locs[i] = std::make_pair(-1, -1);
3923 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3925 Locs[i] = std::make_pair(0, NumLo);
3929 Locs[i] = std::make_pair(1, NumHi);
3931 Mask1[2+NumHi] = Idx;
3937 if (NumLo <= 2 && NumHi <= 2) {
3938 // If no more than two elements come from either vector. This can be
3939 // implemented with two shuffles. First shuffle gather the elements.
3940 // The second shuffle, which takes the first shuffle as both of its
3941 // vector operands, put the elements into the right order.
3942 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3944 SmallVector<int, 8> Mask2(4U, -1);
3946 for (unsigned i = 0; i != 4; ++i) {
3947 if (Locs[i].first == -1)
3950 unsigned Idx = (i < 2) ? 0 : 4;
3951 Idx += Locs[i].first * 2 + Locs[i].second;
3956 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
3957 } else if (NumLo == 3 || NumHi == 3) {
3958 // Otherwise, we must have three elements from one vector, call it X, and
3959 // one element from the other, call it Y. First, use a shufps to build an
3960 // intermediate vector with the one element from Y and the element from X
3961 // that will be in the same half in the final destination (the indexes don't
3962 // matter). Then, use a shufps to build the final vector, taking the half
3963 // containing the element from Y from the intermediate, and the other half
3966 // Normalize it so the 3 elements come from V1.
3967 CommuteVectorShuffleMask(PermMask, VT);
3971 // Find the element from V2.
3973 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3974 int Val = PermMask[HiIndex];
3981 Mask1[0] = PermMask[HiIndex];
3983 Mask1[2] = PermMask[HiIndex^1];
3985 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3988 Mask1[0] = PermMask[0];
3989 Mask1[1] = PermMask[1];
3990 Mask1[2] = HiIndex & 1 ? 6 : 4;
3991 Mask1[3] = HiIndex & 1 ? 4 : 6;
3992 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3994 Mask1[0] = HiIndex & 1 ? 2 : 0;
3995 Mask1[1] = HiIndex & 1 ? 0 : 2;
3996 Mask1[2] = PermMask[2];
3997 Mask1[3] = PermMask[3];
4002 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4006 // Break it into (shuffle shuffle_hi, shuffle_lo).
4008 SmallVector<int,8> LoMask(4U, -1);
4009 SmallVector<int,8> HiMask(4U, -1);
4011 SmallVector<int,8> *MaskPtr = &LoMask;
4012 unsigned MaskIdx = 0;
4015 for (unsigned i = 0; i != 4; ++i) {
4022 int Idx = PermMask[i];
4024 Locs[i] = std::make_pair(-1, -1);
4025 } else if (Idx < 4) {
4026 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4027 (*MaskPtr)[LoIdx] = Idx;
4030 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4031 (*MaskPtr)[HiIdx] = Idx;
4036 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4037 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4038 SmallVector<int, 8> MaskOps;
4039 for (unsigned i = 0; i != 4; ++i) {
4040 if (Locs[i].first == -1) {
4041 MaskOps.push_back(-1);
4043 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4044 MaskOps.push_back(Idx);
4047 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4051 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4053 SDValue V1 = Op.getOperand(0);
4054 SDValue V2 = Op.getOperand(1);
4055 MVT VT = Op.getValueType();
4056 DebugLoc dl = Op.getDebugLoc();
4057 unsigned NumElems = VT.getVectorNumElements();
4058 bool isMMX = VT.getSizeInBits() == 64;
4059 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4060 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4061 bool V1IsSplat = false;
4062 bool V2IsSplat = false;
4064 if (isZeroShuffle(SVOp))
4065 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4067 // Promote splats to v4f32.
4068 if (SVOp->isSplat()) {
4069 if (isMMX || NumElems < 4)
4071 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4074 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4076 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4077 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4078 if (NewOp.getNode())
4079 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4080 LowerVECTOR_SHUFFLE(NewOp, DAG));
4081 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4082 // FIXME: Figure out a cleaner way to do this.
4083 // Try to make use of movq to zero out the top part.
4084 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4085 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4086 if (NewOp.getNode()) {
4087 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4088 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4089 DAG, Subtarget, dl);
4091 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4092 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4093 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4094 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4095 DAG, Subtarget, dl);
4099 if (X86::isPSHUFDMask(SVOp))
4102 // Check if this can be converted into a logical shift.
4103 bool isLeft = false;
4106 bool isShift = getSubtarget()->hasSSE2() &&
4107 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4108 if (isShift && ShVal.hasOneUse()) {
4109 // If the shifted value has multiple uses, it may be cheaper to use
4110 // v_set0 + movlhps or movhlps, etc.
4111 MVT EVT = VT.getVectorElementType();
4112 ShAmt *= EVT.getSizeInBits();
4113 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4116 if (X86::isMOVLMask(SVOp)) {
4119 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4120 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4125 // FIXME: fold these into legal mask.
4126 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4127 X86::isMOVSLDUPMask(SVOp) ||
4128 X86::isMOVHLPSMask(SVOp) ||
4129 X86::isMOVHPMask(SVOp) ||
4130 X86::isMOVLPMask(SVOp)))
4133 if (ShouldXformToMOVHLPS(SVOp) ||
4134 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4135 return CommuteVectorShuffle(SVOp, DAG);
4138 // No better options. Use a vshl / vsrl.
4139 MVT EVT = VT.getVectorElementType();
4140 ShAmt *= EVT.getSizeInBits();
4141 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4144 bool Commuted = false;
4145 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4146 // 1,1,1,1 -> v8i16 though.
4147 V1IsSplat = isSplatVector(V1.getNode());
4148 V2IsSplat = isSplatVector(V2.getNode());
4150 // Canonicalize the splat or undef, if present, to be on the RHS.
4151 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4152 Op = CommuteVectorShuffle(SVOp, DAG);
4153 SVOp = cast<ShuffleVectorSDNode>(Op);
4154 V1 = SVOp->getOperand(0);
4155 V2 = SVOp->getOperand(1);
4156 std::swap(V1IsSplat, V2IsSplat);
4157 std::swap(V1IsUndef, V2IsUndef);
4161 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4162 // Shuffling low element of v1 into undef, just return v1.
4165 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4166 // the instruction selector will not match, so get a canonical MOVL with
4167 // swapped operands to undo the commute.
4168 return getMOVL(DAG, dl, VT, V2, V1);
4171 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4172 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4173 X86::isUNPCKLMask(SVOp) ||
4174 X86::isUNPCKHMask(SVOp))
4178 // Normalize mask so all entries that point to V2 points to its first
4179 // element then try to match unpck{h|l} again. If match, return a
4180 // new vector_shuffle with the corrected mask.
4181 SDValue NewMask = NormalizeMask(SVOp, DAG);
4182 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4183 if (NSVOp != SVOp) {
4184 if (X86::isUNPCKLMask(NSVOp, true)) {
4186 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4193 // Commute is back and try unpck* again.
4194 // FIXME: this seems wrong.
4195 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4196 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4197 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4198 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4199 X86::isUNPCKLMask(NewSVOp) ||
4200 X86::isUNPCKHMask(NewSVOp))
4204 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4206 // Normalize the node to match x86 shuffle ops if needed
4207 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4208 return CommuteVectorShuffle(SVOp, DAG);
4210 // Check for legal shuffle and return?
4211 SmallVector<int, 16> PermMask;
4212 SVOp->getMask(PermMask);
4213 if (isShuffleMaskLegal(PermMask, VT))
4216 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4217 if (VT == MVT::v8i16) {
4218 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4219 if (NewOp.getNode())
4223 if (VT == MVT::v16i8) {
4224 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4225 if (NewOp.getNode())
4229 // Handle all 4 wide cases with a number of shuffles except for MMX.
4230 if (NumElems == 4 && !isMMX)
4231 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4237 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4238 SelectionDAG &DAG) {
4239 MVT VT = Op.getValueType();
4240 DebugLoc dl = Op.getDebugLoc();
4241 if (VT.getSizeInBits() == 8) {
4242 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4243 Op.getOperand(0), Op.getOperand(1));
4244 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4245 DAG.getValueType(VT));
4246 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4247 } else if (VT.getSizeInBits() == 16) {
4248 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4249 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4251 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4252 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4253 DAG.getNode(ISD::BIT_CONVERT, dl,
4257 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4258 Op.getOperand(0), Op.getOperand(1));
4259 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4260 DAG.getValueType(VT));
4261 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4262 } else if (VT == MVT::f32) {
4263 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4264 // the result back to FR32 register. It's only worth matching if the
4265 // result has a single use which is a store or a bitcast to i32. And in
4266 // the case of a store, it's not worth it if the index is a constant 0,
4267 // because a MOVSSmr can be used instead, which is smaller and faster.
4268 if (!Op.hasOneUse())
4270 SDNode *User = *Op.getNode()->use_begin();
4271 if ((User->getOpcode() != ISD::STORE ||
4272 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4273 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4274 (User->getOpcode() != ISD::BIT_CONVERT ||
4275 User->getValueType(0) != MVT::i32))
4277 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4278 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4281 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4282 } else if (VT == MVT::i32) {
4283 // ExtractPS works with constant index.
4284 if (isa<ConstantSDNode>(Op.getOperand(1)))
4292 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4293 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4296 if (Subtarget->hasSSE41()) {
4297 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4302 MVT VT = Op.getValueType();
4303 DebugLoc dl = Op.getDebugLoc();
4304 // TODO: handle v16i8.
4305 if (VT.getSizeInBits() == 16) {
4306 SDValue Vec = Op.getOperand(0);
4307 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4309 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4310 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4311 DAG.getNode(ISD::BIT_CONVERT, dl,
4314 // Transform it so it match pextrw which produces a 32-bit result.
4315 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4316 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4317 Op.getOperand(0), Op.getOperand(1));
4318 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4319 DAG.getValueType(VT));
4320 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4321 } else if (VT.getSizeInBits() == 32) {
4322 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4326 // SHUFPS the element to the lowest double word, then movss.
4327 int Mask[4] = { Idx, -1, -1, -1 };
4328 MVT VVT = Op.getOperand(0).getValueType();
4329 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4330 DAG.getUNDEF(VVT), Mask);
4331 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4332 DAG.getIntPtrConstant(0));
4333 } else if (VT.getSizeInBits() == 64) {
4334 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4335 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4336 // to match extract_elt for f64.
4337 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4341 // UNPCKHPD the element to the lowest double word, then movsd.
4342 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4343 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4344 int Mask[2] = { 1, -1 };
4345 MVT VVT = Op.getOperand(0).getValueType();
4346 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4347 DAG.getUNDEF(VVT), Mask);
4348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4349 DAG.getIntPtrConstant(0));
4356 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4357 MVT VT = Op.getValueType();
4358 MVT EVT = VT.getVectorElementType();
4359 DebugLoc dl = Op.getDebugLoc();
4361 SDValue N0 = Op.getOperand(0);
4362 SDValue N1 = Op.getOperand(1);
4363 SDValue N2 = Op.getOperand(2);
4365 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4366 isa<ConstantSDNode>(N2)) {
4367 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4369 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4371 if (N1.getValueType() != MVT::i32)
4372 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4373 if (N2.getValueType() != MVT::i32)
4374 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4375 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4376 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4377 // Bits [7:6] of the constant are the source select. This will always be
4378 // zero here. The DAG Combiner may combine an extract_elt index into these
4379 // bits. For example (insert (extract, 3), 2) could be matched by putting
4380 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4381 // Bits [5:4] of the constant are the destination select. This is the
4382 // value of the incoming immediate.
4383 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4384 // combine either bitwise AND or insert of float 0.0 to set these bits.
4385 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4386 // Create this as a scalar to vector..
4387 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4388 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4389 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4390 // PINSR* works with constant index.
4397 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4398 MVT VT = Op.getValueType();
4399 MVT EVT = VT.getVectorElementType();
4401 if (Subtarget->hasSSE41())
4402 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4407 DebugLoc dl = Op.getDebugLoc();
4408 SDValue N0 = Op.getOperand(0);
4409 SDValue N1 = Op.getOperand(1);
4410 SDValue N2 = Op.getOperand(2);
4412 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4413 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4414 // as its second argument.
4415 if (N1.getValueType() != MVT::i32)
4416 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4417 if (N2.getValueType() != MVT::i32)
4418 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4419 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4425 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4426 DebugLoc dl = Op.getDebugLoc();
4427 if (Op.getValueType() == MVT::v2f32)
4428 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4429 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4430 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4431 Op.getOperand(0))));
4433 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4434 MVT VT = MVT::v2i32;
4435 switch (Op.getValueType().getSimpleVT()) {
4442 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4443 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4446 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4447 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4448 // one of the above mentioned nodes. It has to be wrapped because otherwise
4449 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4450 // be used to form addressing mode. These wrapped nodes will be selected
4453 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4454 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4456 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4458 unsigned char OpFlag = 0;
4459 unsigned WrapperKind = X86ISD::Wrapper;
4461 if (Subtarget->isPICStyleRIPRel() &&
4462 getTargetMachine().getCodeModel() == CodeModel::Small)
4463 WrapperKind = X86ISD::WrapperRIP;
4464 else if (Subtarget->isPICStyleGOT())
4465 OpFlag = X86II::MO_GOTOFF;
4466 else if (Subtarget->isPICStyleStubPIC())
4467 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4469 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4471 CP->getOffset(), OpFlag);
4472 DebugLoc DL = CP->getDebugLoc();
4473 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4474 // With PIC, the address is actually $g + Offset.
4476 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4477 DAG.getNode(X86ISD::GlobalBaseReg,
4478 DebugLoc::getUnknownLoc(), getPointerTy()),
4485 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4486 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4488 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4490 unsigned char OpFlag = 0;
4491 unsigned WrapperKind = X86ISD::Wrapper;
4493 if (Subtarget->isPICStyleRIPRel() &&
4494 getTargetMachine().getCodeModel() == CodeModel::Small)
4495 WrapperKind = X86ISD::WrapperRIP;
4496 else if (Subtarget->isPICStyleGOT())
4497 OpFlag = X86II::MO_GOTOFF;
4498 else if (Subtarget->isPICStyleStubPIC())
4499 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4501 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4503 DebugLoc DL = JT->getDebugLoc();
4504 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4506 // With PIC, the address is actually $g + Offset.
4508 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4509 DAG.getNode(X86ISD::GlobalBaseReg,
4510 DebugLoc::getUnknownLoc(), getPointerTy()),
4518 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4519 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4521 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4523 unsigned char OpFlag = 0;
4524 unsigned WrapperKind = X86ISD::Wrapper;
4525 if (Subtarget->isPICStyleRIPRel() &&
4526 getTargetMachine().getCodeModel() == CodeModel::Small)
4527 WrapperKind = X86ISD::WrapperRIP;
4528 else if (Subtarget->isPICStyleGOT())
4529 OpFlag = X86II::MO_GOTOFF;
4530 else if (Subtarget->isPICStyleStubPIC())
4531 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4533 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4535 DebugLoc DL = Op.getDebugLoc();
4536 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4539 // With PIC, the address is actually $g + Offset.
4540 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4541 !Subtarget->is64Bit()) {
4542 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4543 DAG.getNode(X86ISD::GlobalBaseReg,
4544 DebugLoc::getUnknownLoc(),
4553 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4555 SelectionDAG &DAG) const {
4556 // Create the TargetGlobalAddress node, folding in the constant
4557 // offset if it is legal.
4558 unsigned char OpFlags =
4559 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4561 if (OpFlags == X86II::MO_NO_FLAG && isInt32(Offset)) {
4562 // A direct static reference to a global.
4563 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4566 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4569 if (Subtarget->isPICStyleRIPRel() &&
4570 getTargetMachine().getCodeModel() == CodeModel::Small)
4571 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4573 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4575 // With PIC, the address is actually $g + Offset.
4576 if (isGlobalRelativeToPICBase(OpFlags)) {
4577 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4578 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4582 // For globals that require a load from a stub to get the address, emit the
4584 if (isGlobalStubReference(OpFlags))
4585 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4586 PseudoSourceValue::getGOT(), 0);
4588 // If there was a non-zero offset that we didn't fold, create an explicit
4591 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4592 DAG.getConstant(Offset, getPointerTy()));
4598 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4599 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4600 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4601 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4605 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4606 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
4607 unsigned char OperandFlags) {
4608 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4609 DebugLoc dl = GA->getDebugLoc();
4610 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4611 GA->getValueType(0),
4615 SDValue Ops[] = { Chain, TGA, *InFlag };
4616 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4618 SDValue Ops[] = { Chain, TGA };
4619 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4621 SDValue Flag = Chain.getValue(1);
4622 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4625 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4627 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4630 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4631 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4632 DAG.getNode(X86ISD::GlobalBaseReg,
4633 DebugLoc::getUnknownLoc(),
4635 InFlag = Chain.getValue(1);
4637 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4640 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4642 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4644 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4645 X86::RAX, X86II::MO_TLSGD);
4648 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4649 // "local exec" model.
4650 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4651 const MVT PtrVT, TLSModel::Model model,
4653 DebugLoc dl = GA->getDebugLoc();
4654 // Get the Thread Pointer
4655 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4656 DebugLoc::getUnknownLoc(), PtrVT,
4657 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4660 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4663 unsigned char OperandFlags = 0;
4664 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4666 unsigned WrapperKind = X86ISD::Wrapper;
4667 if (model == TLSModel::LocalExec) {
4668 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4669 } else if (is64Bit) {
4670 assert(model == TLSModel::InitialExec);
4671 OperandFlags = X86II::MO_GOTTPOFF;
4672 WrapperKind = X86ISD::WrapperRIP;
4674 assert(model == TLSModel::InitialExec);
4675 OperandFlags = X86II::MO_INDNTPOFF;
4678 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4680 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4681 GA->getOffset(), OperandFlags);
4682 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4684 if (model == TLSModel::InitialExec)
4685 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4686 PseudoSourceValue::getGOT(), 0);
4688 // The address of the thread local variable is the add of the thread
4689 // pointer with the offset of the variable.
4690 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4694 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4695 // TODO: implement the "local dynamic" model
4696 // TODO: implement the "initial exec"model for pic executables
4697 assert(Subtarget->isTargetELF() &&
4698 "TLS not implemented for non-ELF targets");
4699 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4700 const GlobalValue *GV = GA->getGlobal();
4702 // If GV is an alias then use the aliasee for determining
4703 // thread-localness.
4704 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4705 GV = GA->resolveAliasedGlobal(false);
4707 TLSModel::Model model = getTLSModel(GV,
4708 getTargetMachine().getRelocationModel());
4711 case TLSModel::GeneralDynamic:
4712 case TLSModel::LocalDynamic: // not implemented
4713 if (Subtarget->is64Bit())
4714 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4715 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4717 case TLSModel::InitialExec:
4718 case TLSModel::LocalExec:
4719 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4720 Subtarget->is64Bit());
4723 llvm_unreachable("Unreachable");
4728 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4729 /// take a 2 x i32 value to shift plus a shift amount.
4730 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4731 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4732 MVT VT = Op.getValueType();
4733 unsigned VTBits = VT.getSizeInBits();
4734 DebugLoc dl = Op.getDebugLoc();
4735 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4736 SDValue ShOpLo = Op.getOperand(0);
4737 SDValue ShOpHi = Op.getOperand(1);
4738 SDValue ShAmt = Op.getOperand(2);
4739 SDValue Tmp1 = isSRA ?
4740 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4741 DAG.getConstant(VTBits - 1, MVT::i8)) :
4742 DAG.getConstant(0, VT);
4745 if (Op.getOpcode() == ISD::SHL_PARTS) {
4746 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4747 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4749 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4750 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4753 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4754 DAG.getConstant(VTBits, MVT::i8));
4755 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4756 AndNode, DAG.getConstant(0, MVT::i8));
4759 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4760 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4761 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4763 if (Op.getOpcode() == ISD::SHL_PARTS) {
4764 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4765 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4767 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4768 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4771 SDValue Ops[2] = { Lo, Hi };
4772 return DAG.getMergeValues(Ops, 2, dl);
4775 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4776 MVT SrcVT = Op.getOperand(0).getValueType();
4778 if (SrcVT.isVector()) {
4779 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4785 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4786 "Unknown SINT_TO_FP to lower!");
4788 // These are really Legal; return the operand so the caller accepts it as
4790 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4792 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4793 Subtarget->is64Bit()) {
4797 DebugLoc dl = Op.getDebugLoc();
4798 unsigned Size = SrcVT.getSizeInBits()/8;
4799 MachineFunction &MF = DAG.getMachineFunction();
4800 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4801 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4802 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4804 PseudoSourceValue::getFixedStack(SSFI), 0);
4805 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4808 SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
4810 SelectionDAG &DAG) {
4812 DebugLoc dl = Op.getDebugLoc();
4814 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4816 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4818 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4819 SmallVector<SDValue, 8> Ops;
4820 Ops.push_back(Chain);
4821 Ops.push_back(StackSlot);
4822 Ops.push_back(DAG.getValueType(SrcVT));
4823 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4824 Tys, &Ops[0], Ops.size());
4827 Chain = Result.getValue(1);
4828 SDValue InFlag = Result.getValue(2);
4830 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4831 // shouldn't be necessary except that RFP cannot be live across
4832 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4833 MachineFunction &MF = DAG.getMachineFunction();
4834 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4835 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4836 Tys = DAG.getVTList(MVT::Other);
4837 SmallVector<SDValue, 8> Ops;
4838 Ops.push_back(Chain);
4839 Ops.push_back(Result);
4840 Ops.push_back(StackSlot);
4841 Ops.push_back(DAG.getValueType(Op.getValueType()));
4842 Ops.push_back(InFlag);
4843 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4844 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4845 PseudoSourceValue::getFixedStack(SSFI), 0);
4851 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4852 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4853 // This algorithm is not obvious. Here it is in C code, more or less:
4855 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4856 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4857 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4859 // Copy ints to xmm registers.
4860 __m128i xh = _mm_cvtsi32_si128( hi );
4861 __m128i xl = _mm_cvtsi32_si128( lo );
4863 // Combine into low half of a single xmm register.
4864 __m128i x = _mm_unpacklo_epi32( xh, xl );
4868 // Merge in appropriate exponents to give the integer bits the right
4870 x = _mm_unpacklo_epi32( x, exp );
4872 // Subtract away the biases to deal with the IEEE-754 double precision
4874 d = _mm_sub_pd( (__m128d) x, bias );
4876 // All conversions up to here are exact. The correctly rounded result is
4877 // calculated using the current rounding mode using the following
4879 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4880 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4881 // store doesn't really need to be here (except
4882 // maybe to zero the other double)
4887 DebugLoc dl = Op.getDebugLoc();
4888 LLVMContext *Context = DAG.getContext();
4890 // Build some magic constants.
4891 std::vector<Constant*> CV0;
4892 CV0.push_back(Context->getConstantInt(APInt(32, 0x45300000)));
4893 CV0.push_back(Context->getConstantInt(APInt(32, 0x43300000)));
4894 CV0.push_back(Context->getConstantInt(APInt(32, 0)));
4895 CV0.push_back(Context->getConstantInt(APInt(32, 0)));
4896 Constant *C0 = Context->getConstantVector(CV0);
4897 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4899 std::vector<Constant*> CV1;
4901 Context->getConstantFP(APFloat(APInt(64, 0x4530000000000000ULL))));
4903 Context->getConstantFP(APFloat(APInt(64, 0x4330000000000000ULL))));
4904 Constant *C1 = Context->getConstantVector(CV1);
4905 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4907 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4908 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4910 DAG.getIntPtrConstant(1)));
4911 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4912 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4914 DAG.getIntPtrConstant(0)));
4915 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4916 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4917 PseudoSourceValue::getConstantPool(), 0,
4919 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4920 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4921 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4922 PseudoSourceValue::getConstantPool(), 0,
4924 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4926 // Add the halves; easiest way is to swap them into another reg first.
4927 int ShufMask[2] = { 1, -1 };
4928 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4929 DAG.getUNDEF(MVT::v2f64), ShufMask);
4930 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4931 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4932 DAG.getIntPtrConstant(0));
4935 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4936 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4937 DebugLoc dl = Op.getDebugLoc();
4938 // FP constant to bias correct the final result.
4939 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4942 // Load the 32-bit value into an XMM register.
4943 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4944 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4946 DAG.getIntPtrConstant(0)));
4948 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4949 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4950 DAG.getIntPtrConstant(0));
4952 // Or the load with the bias.
4953 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4954 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4957 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4958 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4959 MVT::v2f64, Bias)));
4960 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4962 DAG.getIntPtrConstant(0));
4964 // Subtract the bias.
4965 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4967 // Handle final rounding.
4968 MVT DestVT = Op.getValueType();
4970 if (DestVT.bitsLT(MVT::f64)) {
4971 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4972 DAG.getIntPtrConstant(0));
4973 } else if (DestVT.bitsGT(MVT::f64)) {
4974 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4977 // Handle final rounding.
4981 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4982 SDValue N0 = Op.getOperand(0);
4983 DebugLoc dl = Op.getDebugLoc();
4985 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4986 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4987 // the optimization here.
4988 if (DAG.SignBitIsZero(N0))
4989 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
4991 MVT SrcVT = N0.getValueType();
4992 if (SrcVT == MVT::i64) {
4993 // We only handle SSE2 f64 target here; caller can expand the rest.
4994 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4997 return LowerUINT_TO_FP_i64(Op, DAG);
4998 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
4999 return LowerUINT_TO_FP_i32(Op, DAG);
5002 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5004 // Make a 64-bit buffer, and use it to build an FILD.
5005 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5006 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5007 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5008 getPointerTy(), StackSlot, WordOff);
5009 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5010 StackSlot, NULL, 0);
5011 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5012 OffsetSlot, NULL, 0);
5013 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5016 std::pair<SDValue,SDValue> X86TargetLowering::
5017 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5018 DebugLoc dl = Op.getDebugLoc();
5020 MVT DstTy = Op.getValueType();
5023 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5027 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5028 DstTy.getSimpleVT() >= MVT::i16 &&
5029 "Unknown FP_TO_SINT to lower!");
5031 // These are really Legal.
5032 if (DstTy == MVT::i32 &&
5033 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5034 return std::make_pair(SDValue(), SDValue());
5035 if (Subtarget->is64Bit() &&
5036 DstTy == MVT::i64 &&
5037 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5038 return std::make_pair(SDValue(), SDValue());
5040 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5042 MachineFunction &MF = DAG.getMachineFunction();
5043 unsigned MemSize = DstTy.getSizeInBits()/8;
5044 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5045 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5048 switch (DstTy.getSimpleVT()) {
5049 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5050 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5051 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5052 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5055 SDValue Chain = DAG.getEntryNode();
5056 SDValue Value = Op.getOperand(0);
5057 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5058 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5059 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5060 PseudoSourceValue::getFixedStack(SSFI), 0);
5061 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5063 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5065 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5066 Chain = Value.getValue(1);
5067 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5068 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5071 // Build the FP_TO_INT*_IN_MEM
5072 SDValue Ops[] = { Chain, Value, StackSlot };
5073 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5075 return std::make_pair(FIST, StackSlot);
5078 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5079 if (Op.getValueType().isVector()) {
5080 if (Op.getValueType() == MVT::v2i32 &&
5081 Op.getOperand(0).getValueType() == MVT::v2f64) {
5087 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5088 SDValue FIST = Vals.first, StackSlot = Vals.second;
5089 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5090 if (FIST.getNode() == 0) return Op;
5093 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5094 FIST, StackSlot, NULL, 0);
5097 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5098 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5099 SDValue FIST = Vals.first, StackSlot = Vals.second;
5100 assert(FIST.getNode() && "Unexpected failure");
5103 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5104 FIST, StackSlot, NULL, 0);
5107 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5108 LLVMContext *Context = DAG.getContext();
5109 DebugLoc dl = Op.getDebugLoc();
5110 MVT VT = Op.getValueType();
5113 EltVT = VT.getVectorElementType();
5114 std::vector<Constant*> CV;
5115 if (EltVT == MVT::f64) {
5116 Constant *C = Context->getConstantFP(APFloat(APInt(64, ~(1ULL << 63))));
5120 Constant *C = Context->getConstantFP(APFloat(APInt(32, ~(1U << 31))));
5126 Constant *C = Context->getConstantVector(CV);
5127 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5128 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5129 PseudoSourceValue::getConstantPool(), 0,
5131 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5134 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5135 LLVMContext *Context = DAG.getContext();
5136 DebugLoc dl = Op.getDebugLoc();
5137 MVT VT = Op.getValueType();
5139 unsigned EltNum = 1;
5140 if (VT.isVector()) {
5141 EltVT = VT.getVectorElementType();
5142 EltNum = VT.getVectorNumElements();
5144 std::vector<Constant*> CV;
5145 if (EltVT == MVT::f64) {
5146 Constant *C = Context->getConstantFP(APFloat(APInt(64, 1ULL << 63)));
5150 Constant *C = Context->getConstantFP(APFloat(APInt(32, 1U << 31)));
5156 Constant *C = Context->getConstantVector(CV);
5157 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5158 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5159 PseudoSourceValue::getConstantPool(), 0,
5161 if (VT.isVector()) {
5162 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5163 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5164 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5166 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5168 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5172 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5173 LLVMContext *Context = DAG.getContext();
5174 SDValue Op0 = Op.getOperand(0);
5175 SDValue Op1 = Op.getOperand(1);
5176 DebugLoc dl = Op.getDebugLoc();
5177 MVT VT = Op.getValueType();
5178 MVT SrcVT = Op1.getValueType();
5180 // If second operand is smaller, extend it first.
5181 if (SrcVT.bitsLT(VT)) {
5182 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5185 // And if it is bigger, shrink it first.
5186 if (SrcVT.bitsGT(VT)) {
5187 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5191 // At this point the operands and the result should have the same
5192 // type, and that won't be f80 since that is not custom lowered.
5194 // First get the sign bit of second operand.
5195 std::vector<Constant*> CV;
5196 if (SrcVT == MVT::f64) {
5197 CV.push_back(Context->getConstantFP(APFloat(APInt(64, 1ULL << 63))));
5198 CV.push_back(Context->getConstantFP(APFloat(APInt(64, 0))));
5200 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 1U << 31))));
5201 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5202 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5203 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5205 Constant *C = Context->getConstantVector(CV);
5206 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5207 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5208 PseudoSourceValue::getConstantPool(), 0,
5210 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5212 // Shift sign bit right or left if the two operands have different types.
5213 if (SrcVT.bitsGT(VT)) {
5214 // Op0 is MVT::f32, Op1 is MVT::f64.
5215 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5216 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5217 DAG.getConstant(32, MVT::i32));
5218 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5219 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5220 DAG.getIntPtrConstant(0));
5223 // Clear first operand sign bit.
5225 if (VT == MVT::f64) {
5226 CV.push_back(Context->getConstantFP(APFloat(APInt(64, ~(1ULL << 63)))));
5227 CV.push_back(Context->getConstantFP(APFloat(APInt(64, 0))));
5229 CV.push_back(Context->getConstantFP(APFloat(APInt(32, ~(1U << 31)))));
5230 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5231 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5232 CV.push_back(Context->getConstantFP(APFloat(APInt(32, 0))));
5234 C = Context->getConstantVector(CV);
5235 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5236 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5237 PseudoSourceValue::getConstantPool(), 0,
5239 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5241 // Or the value with the sign bit.
5242 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5245 /// Emit nodes that will be selected as "test Op0,Op0", or something
5247 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5248 SelectionDAG &DAG) {
5249 DebugLoc dl = Op.getDebugLoc();
5251 // CF and OF aren't always set the way we want. Determine which
5252 // of these we need.
5253 bool NeedCF = false;
5254 bool NeedOF = false;
5256 case X86::COND_A: case X86::COND_AE:
5257 case X86::COND_B: case X86::COND_BE:
5260 case X86::COND_G: case X86::COND_GE:
5261 case X86::COND_L: case X86::COND_LE:
5262 case X86::COND_O: case X86::COND_NO:
5268 // See if we can use the EFLAGS value from the operand instead of
5269 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5270 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5271 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5272 unsigned Opcode = 0;
5273 unsigned NumOperands = 0;
5274 switch (Op.getNode()->getOpcode()) {
5276 // Due to an isel shortcoming, be conservative if this add is likely to
5277 // be selected as part of a load-modify-store instruction. When the root
5278 // node in a match is a store, isel doesn't know how to remap non-chain
5279 // non-flag uses of other nodes in the match, such as the ADD in this
5280 // case. This leads to the ADD being left around and reselected, with
5281 // the result being two adds in the output.
5282 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5283 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5284 if (UI->getOpcode() == ISD::STORE)
5286 if (ConstantSDNode *C =
5287 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5288 // An add of one will be selected as an INC.
5289 if (C->getAPIntValue() == 1) {
5290 Opcode = X86ISD::INC;
5294 // An add of negative one (subtract of one) will be selected as a DEC.
5295 if (C->getAPIntValue().isAllOnesValue()) {
5296 Opcode = X86ISD::DEC;
5301 // Otherwise use a regular EFLAGS-setting add.
5302 Opcode = X86ISD::ADD;
5306 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5307 // likely to be selected as part of a load-modify-store instruction.
5308 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5309 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5310 if (UI->getOpcode() == ISD::STORE)
5312 // Otherwise use a regular EFLAGS-setting sub.
5313 Opcode = X86ISD::SUB;
5320 return SDValue(Op.getNode(), 1);
5326 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5327 SmallVector<SDValue, 4> Ops;
5328 for (unsigned i = 0; i != NumOperands; ++i)
5329 Ops.push_back(Op.getOperand(i));
5330 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5331 DAG.ReplaceAllUsesWith(Op, New);
5332 return SDValue(New.getNode(), 1);
5336 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5337 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5338 DAG.getConstant(0, Op.getValueType()));
5341 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5343 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5344 SelectionDAG &DAG) {
5345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5346 if (C->getAPIntValue() == 0)
5347 return EmitTest(Op0, X86CC, DAG);
5349 DebugLoc dl = Op0.getDebugLoc();
5350 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5353 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5354 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5355 SDValue Op0 = Op.getOperand(0);
5356 SDValue Op1 = Op.getOperand(1);
5357 DebugLoc dl = Op.getDebugLoc();
5358 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5360 // Lower (X & (1 << N)) == 0 to BT(X, N).
5361 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5362 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5363 if (Op0.getOpcode() == ISD::AND &&
5365 Op1.getOpcode() == ISD::Constant &&
5366 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5367 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5369 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5370 if (ConstantSDNode *Op010C =
5371 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5372 if (Op010C->getZExtValue() == 1) {
5373 LHS = Op0.getOperand(0);
5374 RHS = Op0.getOperand(1).getOperand(1);
5376 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5377 if (ConstantSDNode *Op000C =
5378 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5379 if (Op000C->getZExtValue() == 1) {
5380 LHS = Op0.getOperand(1);
5381 RHS = Op0.getOperand(0).getOperand(1);
5383 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5384 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5385 SDValue AndLHS = Op0.getOperand(0);
5386 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5387 LHS = AndLHS.getOperand(0);
5388 RHS = AndLHS.getOperand(1);
5392 if (LHS.getNode()) {
5393 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5394 // instruction. Since the shift amount is in-range-or-undefined, we know
5395 // that doing a bittest on the i16 value is ok. We extend to i32 because
5396 // the encoding for the i16 version is larger than the i32 version.
5397 if (LHS.getValueType() == MVT::i8)
5398 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5400 // If the operand types disagree, extend the shift amount to match. Since
5401 // BT ignores high bits (like shifts) we can use anyextend.
5402 if (LHS.getValueType() != RHS.getValueType())
5403 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5405 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5406 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5407 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5408 DAG.getConstant(Cond, MVT::i8), BT);
5412 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5413 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5415 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5416 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5417 DAG.getConstant(X86CC, MVT::i8), Cond);
5420 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5422 SDValue Op0 = Op.getOperand(0);
5423 SDValue Op1 = Op.getOperand(1);
5424 SDValue CC = Op.getOperand(2);
5425 MVT VT = Op.getValueType();
5426 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5427 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5428 DebugLoc dl = Op.getDebugLoc();
5432 MVT VT0 = Op0.getValueType();
5433 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5434 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5437 switch (SetCCOpcode) {
5440 case ISD::SETEQ: SSECC = 0; break;
5442 case ISD::SETGT: Swap = true; // Fallthrough
5444 case ISD::SETOLT: SSECC = 1; break;
5446 case ISD::SETGE: Swap = true; // Fallthrough
5448 case ISD::SETOLE: SSECC = 2; break;
5449 case ISD::SETUO: SSECC = 3; break;
5451 case ISD::SETNE: SSECC = 4; break;
5452 case ISD::SETULE: Swap = true;
5453 case ISD::SETUGE: SSECC = 5; break;
5454 case ISD::SETULT: Swap = true;
5455 case ISD::SETUGT: SSECC = 6; break;
5456 case ISD::SETO: SSECC = 7; break;
5459 std::swap(Op0, Op1);
5461 // In the two special cases we can't handle, emit two comparisons.
5463 if (SetCCOpcode == ISD::SETUEQ) {
5465 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5466 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5467 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5469 else if (SetCCOpcode == ISD::SETONE) {
5471 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5472 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5473 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5475 llvm_unreachable("Illegal FP comparison");
5477 // Handle all other FP comparisons here.
5478 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5481 // We are handling one of the integer comparisons here. Since SSE only has
5482 // GT and EQ comparisons for integer, swapping operands and multiple
5483 // operations may be required for some comparisons.
5484 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5485 bool Swap = false, Invert = false, FlipSigns = false;
5487 switch (VT.getSimpleVT()) {
5490 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5492 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5494 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5495 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5498 switch (SetCCOpcode) {
5500 case ISD::SETNE: Invert = true;
5501 case ISD::SETEQ: Opc = EQOpc; break;
5502 case ISD::SETLT: Swap = true;
5503 case ISD::SETGT: Opc = GTOpc; break;
5504 case ISD::SETGE: Swap = true;
5505 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5506 case ISD::SETULT: Swap = true;
5507 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5508 case ISD::SETUGE: Swap = true;
5509 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5512 std::swap(Op0, Op1);
5514 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5515 // bits of the inputs before performing those operations.
5517 MVT EltVT = VT.getVectorElementType();
5518 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5520 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5521 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5523 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5524 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5527 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5529 // If the logical-not of the result is required, perform that now.
5531 Result = DAG.getNOT(dl, Result, VT);
5536 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5537 static bool isX86LogicalCmp(SDValue Op) {
5538 unsigned Opc = Op.getNode()->getOpcode();
5539 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5541 if (Op.getResNo() == 1 &&
5542 (Opc == X86ISD::ADD ||
5543 Opc == X86ISD::SUB ||
5544 Opc == X86ISD::SMUL ||
5545 Opc == X86ISD::UMUL ||
5546 Opc == X86ISD::INC ||
5547 Opc == X86ISD::DEC))
5553 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5554 bool addTest = true;
5555 SDValue Cond = Op.getOperand(0);
5556 DebugLoc dl = Op.getDebugLoc();
5559 if (Cond.getOpcode() == ISD::SETCC)
5560 Cond = LowerSETCC(Cond, DAG);
5562 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5563 // setting operand in place of the X86ISD::SETCC.
5564 if (Cond.getOpcode() == X86ISD::SETCC) {
5565 CC = Cond.getOperand(0);
5567 SDValue Cmp = Cond.getOperand(1);
5568 unsigned Opc = Cmp.getOpcode();
5569 MVT VT = Op.getValueType();
5571 bool IllegalFPCMov = false;
5572 if (VT.isFloatingPoint() && !VT.isVector() &&
5573 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5574 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5576 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5577 Opc == X86ISD::BT) { // FIXME
5584 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5585 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5588 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5589 SmallVector<SDValue, 4> Ops;
5590 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5591 // condition is true.
5592 Ops.push_back(Op.getOperand(2));
5593 Ops.push_back(Op.getOperand(1));
5595 Ops.push_back(Cond);
5596 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5599 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5600 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5601 // from the AND / OR.
5602 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5603 Opc = Op.getOpcode();
5604 if (Opc != ISD::OR && Opc != ISD::AND)
5606 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5607 Op.getOperand(0).hasOneUse() &&
5608 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5609 Op.getOperand(1).hasOneUse());
5612 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5613 // 1 and that the SETCC node has a single use.
5614 static bool isXor1OfSetCC(SDValue Op) {
5615 if (Op.getOpcode() != ISD::XOR)
5617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5618 if (N1C && N1C->getAPIntValue() == 1) {
5619 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5620 Op.getOperand(0).hasOneUse();
5625 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5626 bool addTest = true;
5627 SDValue Chain = Op.getOperand(0);
5628 SDValue Cond = Op.getOperand(1);
5629 SDValue Dest = Op.getOperand(2);
5630 DebugLoc dl = Op.getDebugLoc();
5633 if (Cond.getOpcode() == ISD::SETCC)
5634 Cond = LowerSETCC(Cond, DAG);
5636 // FIXME: LowerXALUO doesn't handle these!!
5637 else if (Cond.getOpcode() == X86ISD::ADD ||
5638 Cond.getOpcode() == X86ISD::SUB ||
5639 Cond.getOpcode() == X86ISD::SMUL ||
5640 Cond.getOpcode() == X86ISD::UMUL)
5641 Cond = LowerXALUO(Cond, DAG);
5644 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5645 // setting operand in place of the X86ISD::SETCC.
5646 if (Cond.getOpcode() == X86ISD::SETCC) {
5647 CC = Cond.getOperand(0);
5649 SDValue Cmp = Cond.getOperand(1);
5650 unsigned Opc = Cmp.getOpcode();
5651 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5652 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5656 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5660 // These can only come from an arithmetic instruction with overflow,
5661 // e.g. SADDO, UADDO.
5662 Cond = Cond.getNode()->getOperand(1);
5669 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5670 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5671 if (CondOpc == ISD::OR) {
5672 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5673 // two branches instead of an explicit OR instruction with a
5675 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5676 isX86LogicalCmp(Cmp)) {
5677 CC = Cond.getOperand(0).getOperand(0);
5678 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5679 Chain, Dest, CC, Cmp);
5680 CC = Cond.getOperand(1).getOperand(0);
5684 } else { // ISD::AND
5685 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5686 // two branches instead of an explicit AND instruction with a
5687 // separate test. However, we only do this if this block doesn't
5688 // have a fall-through edge, because this requires an explicit
5689 // jmp when the condition is false.
5690 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5691 isX86LogicalCmp(Cmp) &&
5692 Op.getNode()->hasOneUse()) {
5693 X86::CondCode CCode =
5694 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5695 CCode = X86::GetOppositeBranchCondition(CCode);
5696 CC = DAG.getConstant(CCode, MVT::i8);
5697 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5698 // Look for an unconditional branch following this conditional branch.
5699 // We need this because we need to reverse the successors in order
5700 // to implement FCMP_OEQ.
5701 if (User.getOpcode() == ISD::BR) {
5702 SDValue FalseBB = User.getOperand(1);
5704 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5705 assert(NewBR == User);
5708 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5709 Chain, Dest, CC, Cmp);
5710 X86::CondCode CCode =
5711 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5712 CCode = X86::GetOppositeBranchCondition(CCode);
5713 CC = DAG.getConstant(CCode, MVT::i8);
5719 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5720 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5721 // It should be transformed during dag combiner except when the condition
5722 // is set by a arithmetics with overflow node.
5723 X86::CondCode CCode =
5724 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5725 CCode = X86::GetOppositeBranchCondition(CCode);
5726 CC = DAG.getConstant(CCode, MVT::i8);
5727 Cond = Cond.getOperand(0).getOperand(1);
5733 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5734 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5736 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5737 Chain, Dest, CC, Cond);
5741 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5742 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5743 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5744 // that the guard pages used by the OS virtual memory manager are allocated in
5745 // correct sequence.
5747 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5748 SelectionDAG &DAG) {
5749 assert(Subtarget->isTargetCygMing() &&
5750 "This should be used only on Cygwin/Mingw targets");
5751 DebugLoc dl = Op.getDebugLoc();
5754 SDValue Chain = Op.getOperand(0);
5755 SDValue Size = Op.getOperand(1);
5756 // FIXME: Ensure alignment here
5760 MVT IntPtr = getPointerTy();
5761 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5763 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5765 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5766 Flag = Chain.getValue(1);
5768 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5769 SDValue Ops[] = { Chain,
5770 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5771 DAG.getRegister(X86::EAX, IntPtr),
5772 DAG.getRegister(X86StackPtr, SPTy),
5774 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5775 Flag = Chain.getValue(1);
5777 Chain = DAG.getCALLSEQ_END(Chain,
5778 DAG.getIntPtrConstant(0, true),
5779 DAG.getIntPtrConstant(0, true),
5782 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5784 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5785 return DAG.getMergeValues(Ops1, 2, dl);
5789 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5791 SDValue Dst, SDValue Src,
5792 SDValue Size, unsigned Align,
5794 uint64_t DstSVOff) {
5795 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5797 // If not DWORD aligned or size is more than the threshold, call the library.
5798 // The libc version is likely to be faster for these cases. It can use the
5799 // address value and run time information about the CPU.
5800 if ((Align & 3) != 0 ||
5802 ConstantSize->getZExtValue() >
5803 getSubtarget()->getMaxInlineSizeThreshold()) {
5804 SDValue InFlag(0, 0);
5806 // Check to see if there is a specialized entry-point for memory zeroing.
5807 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5809 if (const char *bzeroEntry = V &&
5810 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5811 MVT IntPtr = getPointerTy();
5812 const Type *IntPtrTy = TD->getIntPtrType();
5813 TargetLowering::ArgListTy Args;
5814 TargetLowering::ArgListEntry Entry;
5816 Entry.Ty = IntPtrTy;
5817 Args.push_back(Entry);
5819 Args.push_back(Entry);
5820 std::pair<SDValue,SDValue> CallResult =
5821 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5822 0, CallingConv::C, false,
5823 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5824 return CallResult.second;
5827 // Otherwise have the target-independent code call memset.
5831 uint64_t SizeVal = ConstantSize->getZExtValue();
5832 SDValue InFlag(0, 0);
5835 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5836 unsigned BytesLeft = 0;
5837 bool TwoRepStos = false;
5840 uint64_t Val = ValC->getZExtValue() & 255;
5842 // If the value is a constant, then we can potentially use larger sets.
5843 switch (Align & 3) {
5844 case 2: // WORD aligned
5847 Val = (Val << 8) | Val;
5849 case 0: // DWORD aligned
5852 Val = (Val << 8) | Val;
5853 Val = (Val << 16) | Val;
5854 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5857 Val = (Val << 32) | Val;
5860 default: // Byte aligned
5863 Count = DAG.getIntPtrConstant(SizeVal);
5867 if (AVT.bitsGT(MVT::i8)) {
5868 unsigned UBytes = AVT.getSizeInBits() / 8;
5869 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5870 BytesLeft = SizeVal % UBytes;
5873 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5875 InFlag = Chain.getValue(1);
5878 Count = DAG.getIntPtrConstant(SizeVal);
5879 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5880 InFlag = Chain.getValue(1);
5883 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5886 InFlag = Chain.getValue(1);
5887 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5890 InFlag = Chain.getValue(1);
5892 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5893 SmallVector<SDValue, 8> Ops;
5894 Ops.push_back(Chain);
5895 Ops.push_back(DAG.getValueType(AVT));
5896 Ops.push_back(InFlag);
5897 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5900 InFlag = Chain.getValue(1);
5902 MVT CVT = Count.getValueType();
5903 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5904 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5905 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5908 InFlag = Chain.getValue(1);
5909 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5911 Ops.push_back(Chain);
5912 Ops.push_back(DAG.getValueType(MVT::i8));
5913 Ops.push_back(InFlag);
5914 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5915 } else if (BytesLeft) {
5916 // Handle the last 1 - 7 bytes.
5917 unsigned Offset = SizeVal - BytesLeft;
5918 MVT AddrVT = Dst.getValueType();
5919 MVT SizeVT = Size.getValueType();
5921 Chain = DAG.getMemset(Chain, dl,
5922 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5923 DAG.getConstant(Offset, AddrVT)),
5925 DAG.getConstant(BytesLeft, SizeVT),
5926 Align, DstSV, DstSVOff + Offset);
5929 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5934 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5935 SDValue Chain, SDValue Dst, SDValue Src,
5936 SDValue Size, unsigned Align,
5938 const Value *DstSV, uint64_t DstSVOff,
5939 const Value *SrcSV, uint64_t SrcSVOff) {
5940 // This requires the copy size to be a constant, preferrably
5941 // within a subtarget-specific limit.
5942 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5945 uint64_t SizeVal = ConstantSize->getZExtValue();
5946 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5949 /// If not DWORD aligned, call the library.
5950 if ((Align & 3) != 0)
5955 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5958 unsigned UBytes = AVT.getSizeInBits() / 8;
5959 unsigned CountVal = SizeVal / UBytes;
5960 SDValue Count = DAG.getIntPtrConstant(CountVal);
5961 unsigned BytesLeft = SizeVal % UBytes;
5963 SDValue InFlag(0, 0);
5964 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5967 InFlag = Chain.getValue(1);
5968 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5971 InFlag = Chain.getValue(1);
5972 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5975 InFlag = Chain.getValue(1);
5977 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5978 SmallVector<SDValue, 8> Ops;
5979 Ops.push_back(Chain);
5980 Ops.push_back(DAG.getValueType(AVT));
5981 Ops.push_back(InFlag);
5982 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
5984 SmallVector<SDValue, 4> Results;
5985 Results.push_back(RepMovs);
5987 // Handle the last 1 - 7 bytes.
5988 unsigned Offset = SizeVal - BytesLeft;
5989 MVT DstVT = Dst.getValueType();
5990 MVT SrcVT = Src.getValueType();
5991 MVT SizeVT = Size.getValueType();
5992 Results.push_back(DAG.getMemcpy(Chain, dl,
5993 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
5994 DAG.getConstant(Offset, DstVT)),
5995 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
5996 DAG.getConstant(Offset, SrcVT)),
5997 DAG.getConstant(BytesLeft, SizeVT),
5998 Align, AlwaysInline,
5999 DstSV, DstSVOff + Offset,
6000 SrcSV, SrcSVOff + Offset));
6003 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6004 &Results[0], Results.size());
6007 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6009 DebugLoc dl = Op.getDebugLoc();
6011 if (!Subtarget->is64Bit()) {
6012 // vastart just stores the address of the VarArgsFrameIndex slot into the
6013 // memory location argument.
6014 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6015 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6019 // gp_offset (0 - 6 * 8)
6020 // fp_offset (48 - 48 + 8 * 16)
6021 // overflow_arg_area (point to parameters coming in memory).
6023 SmallVector<SDValue, 8> MemOps;
6024 SDValue FIN = Op.getOperand(1);
6026 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6027 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6029 MemOps.push_back(Store);
6032 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6033 FIN, DAG.getIntPtrConstant(4));
6034 Store = DAG.getStore(Op.getOperand(0), dl,
6035 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6037 MemOps.push_back(Store);
6039 // Store ptr to overflow_arg_area
6040 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6041 FIN, DAG.getIntPtrConstant(4));
6042 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6043 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6044 MemOps.push_back(Store);
6046 // Store ptr to reg_save_area.
6047 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6048 FIN, DAG.getIntPtrConstant(8));
6049 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6050 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6051 MemOps.push_back(Store);
6052 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6053 &MemOps[0], MemOps.size());
6056 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6057 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6058 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6059 SDValue Chain = Op.getOperand(0);
6060 SDValue SrcPtr = Op.getOperand(1);
6061 SDValue SrcSV = Op.getOperand(2);
6063 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6067 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6068 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6069 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6070 SDValue Chain = Op.getOperand(0);
6071 SDValue DstPtr = Op.getOperand(1);
6072 SDValue SrcPtr = Op.getOperand(2);
6073 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6074 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6075 DebugLoc dl = Op.getDebugLoc();
6077 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6078 DAG.getIntPtrConstant(24), 8, false,
6079 DstSV, 0, SrcSV, 0);
6083 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6084 DebugLoc dl = Op.getDebugLoc();
6085 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6087 default: return SDValue(); // Don't custom lower most intrinsics.
6088 // Comparison intrinsics.
6089 case Intrinsic::x86_sse_comieq_ss:
6090 case Intrinsic::x86_sse_comilt_ss:
6091 case Intrinsic::x86_sse_comile_ss:
6092 case Intrinsic::x86_sse_comigt_ss:
6093 case Intrinsic::x86_sse_comige_ss:
6094 case Intrinsic::x86_sse_comineq_ss:
6095 case Intrinsic::x86_sse_ucomieq_ss:
6096 case Intrinsic::x86_sse_ucomilt_ss:
6097 case Intrinsic::x86_sse_ucomile_ss:
6098 case Intrinsic::x86_sse_ucomigt_ss:
6099 case Intrinsic::x86_sse_ucomige_ss:
6100 case Intrinsic::x86_sse_ucomineq_ss:
6101 case Intrinsic::x86_sse2_comieq_sd:
6102 case Intrinsic::x86_sse2_comilt_sd:
6103 case Intrinsic::x86_sse2_comile_sd:
6104 case Intrinsic::x86_sse2_comigt_sd:
6105 case Intrinsic::x86_sse2_comige_sd:
6106 case Intrinsic::x86_sse2_comineq_sd:
6107 case Intrinsic::x86_sse2_ucomieq_sd:
6108 case Intrinsic::x86_sse2_ucomilt_sd:
6109 case Intrinsic::x86_sse2_ucomile_sd:
6110 case Intrinsic::x86_sse2_ucomigt_sd:
6111 case Intrinsic::x86_sse2_ucomige_sd:
6112 case Intrinsic::x86_sse2_ucomineq_sd: {
6114 ISD::CondCode CC = ISD::SETCC_INVALID;
6117 case Intrinsic::x86_sse_comieq_ss:
6118 case Intrinsic::x86_sse2_comieq_sd:
6122 case Intrinsic::x86_sse_comilt_ss:
6123 case Intrinsic::x86_sse2_comilt_sd:
6127 case Intrinsic::x86_sse_comile_ss:
6128 case Intrinsic::x86_sse2_comile_sd:
6132 case Intrinsic::x86_sse_comigt_ss:
6133 case Intrinsic::x86_sse2_comigt_sd:
6137 case Intrinsic::x86_sse_comige_ss:
6138 case Intrinsic::x86_sse2_comige_sd:
6142 case Intrinsic::x86_sse_comineq_ss:
6143 case Intrinsic::x86_sse2_comineq_sd:
6147 case Intrinsic::x86_sse_ucomieq_ss:
6148 case Intrinsic::x86_sse2_ucomieq_sd:
6149 Opc = X86ISD::UCOMI;
6152 case Intrinsic::x86_sse_ucomilt_ss:
6153 case Intrinsic::x86_sse2_ucomilt_sd:
6154 Opc = X86ISD::UCOMI;
6157 case Intrinsic::x86_sse_ucomile_ss:
6158 case Intrinsic::x86_sse2_ucomile_sd:
6159 Opc = X86ISD::UCOMI;
6162 case Intrinsic::x86_sse_ucomigt_ss:
6163 case Intrinsic::x86_sse2_ucomigt_sd:
6164 Opc = X86ISD::UCOMI;
6167 case Intrinsic::x86_sse_ucomige_ss:
6168 case Intrinsic::x86_sse2_ucomige_sd:
6169 Opc = X86ISD::UCOMI;
6172 case Intrinsic::x86_sse_ucomineq_ss:
6173 case Intrinsic::x86_sse2_ucomineq_sd:
6174 Opc = X86ISD::UCOMI;
6179 SDValue LHS = Op.getOperand(1);
6180 SDValue RHS = Op.getOperand(2);
6181 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6182 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6183 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6184 DAG.getConstant(X86CC, MVT::i8), Cond);
6185 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6188 // Fix vector shift instructions where the last operand is a non-immediate
6190 case Intrinsic::x86_sse2_pslli_w:
6191 case Intrinsic::x86_sse2_pslli_d:
6192 case Intrinsic::x86_sse2_pslli_q:
6193 case Intrinsic::x86_sse2_psrli_w:
6194 case Intrinsic::x86_sse2_psrli_d:
6195 case Intrinsic::x86_sse2_psrli_q:
6196 case Intrinsic::x86_sse2_psrai_w:
6197 case Intrinsic::x86_sse2_psrai_d:
6198 case Intrinsic::x86_mmx_pslli_w:
6199 case Intrinsic::x86_mmx_pslli_d:
6200 case Intrinsic::x86_mmx_pslli_q:
6201 case Intrinsic::x86_mmx_psrli_w:
6202 case Intrinsic::x86_mmx_psrli_d:
6203 case Intrinsic::x86_mmx_psrli_q:
6204 case Intrinsic::x86_mmx_psrai_w:
6205 case Intrinsic::x86_mmx_psrai_d: {
6206 SDValue ShAmt = Op.getOperand(2);
6207 if (isa<ConstantSDNode>(ShAmt))
6210 unsigned NewIntNo = 0;
6211 MVT ShAmtVT = MVT::v4i32;
6213 case Intrinsic::x86_sse2_pslli_w:
6214 NewIntNo = Intrinsic::x86_sse2_psll_w;
6216 case Intrinsic::x86_sse2_pslli_d:
6217 NewIntNo = Intrinsic::x86_sse2_psll_d;
6219 case Intrinsic::x86_sse2_pslli_q:
6220 NewIntNo = Intrinsic::x86_sse2_psll_q;
6222 case Intrinsic::x86_sse2_psrli_w:
6223 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6225 case Intrinsic::x86_sse2_psrli_d:
6226 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6228 case Intrinsic::x86_sse2_psrli_q:
6229 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6231 case Intrinsic::x86_sse2_psrai_w:
6232 NewIntNo = Intrinsic::x86_sse2_psra_w;
6234 case Intrinsic::x86_sse2_psrai_d:
6235 NewIntNo = Intrinsic::x86_sse2_psra_d;
6238 ShAmtVT = MVT::v2i32;
6240 case Intrinsic::x86_mmx_pslli_w:
6241 NewIntNo = Intrinsic::x86_mmx_psll_w;
6243 case Intrinsic::x86_mmx_pslli_d:
6244 NewIntNo = Intrinsic::x86_mmx_psll_d;
6246 case Intrinsic::x86_mmx_pslli_q:
6247 NewIntNo = Intrinsic::x86_mmx_psll_q;
6249 case Intrinsic::x86_mmx_psrli_w:
6250 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6252 case Intrinsic::x86_mmx_psrli_d:
6253 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6255 case Intrinsic::x86_mmx_psrli_q:
6256 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6258 case Intrinsic::x86_mmx_psrai_w:
6259 NewIntNo = Intrinsic::x86_mmx_psra_w;
6261 case Intrinsic::x86_mmx_psrai_d:
6262 NewIntNo = Intrinsic::x86_mmx_psra_d;
6264 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6269 MVT VT = Op.getValueType();
6270 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6271 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6272 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6273 DAG.getConstant(NewIntNo, MVT::i32),
6274 Op.getOperand(1), ShAmt);
6279 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6280 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6281 DebugLoc dl = Op.getDebugLoc();
6284 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6286 DAG.getConstant(TD->getPointerSize(),
6287 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6288 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6289 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6294 // Just load the return address.
6295 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6296 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6297 RetAddrFI, NULL, 0);
6300 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6301 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6302 MFI->setFrameAddressIsTaken(true);
6303 MVT VT = Op.getValueType();
6304 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6305 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6306 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6307 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6309 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6313 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6314 SelectionDAG &DAG) {
6315 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6318 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6320 MachineFunction &MF = DAG.getMachineFunction();
6321 SDValue Chain = Op.getOperand(0);
6322 SDValue Offset = Op.getOperand(1);
6323 SDValue Handler = Op.getOperand(2);
6324 DebugLoc dl = Op.getDebugLoc();
6326 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6328 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6330 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6331 DAG.getIntPtrConstant(-TD->getPointerSize()));
6332 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6333 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6334 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6335 MF.getRegInfo().addLiveOut(StoreAddrReg);
6337 return DAG.getNode(X86ISD::EH_RETURN, dl,
6339 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6342 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6343 SelectionDAG &DAG) {
6344 SDValue Root = Op.getOperand(0);
6345 SDValue Trmp = Op.getOperand(1); // trampoline
6346 SDValue FPtr = Op.getOperand(2); // nested function
6347 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6348 DebugLoc dl = Op.getDebugLoc();
6350 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6352 const X86InstrInfo *TII =
6353 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6355 if (Subtarget->is64Bit()) {
6356 SDValue OutChains[6];
6358 // Large code-model.
6360 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6361 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6363 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6364 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6366 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6368 // Load the pointer to the nested function into R11.
6369 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6370 SDValue Addr = Trmp;
6371 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6374 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6375 DAG.getConstant(2, MVT::i64));
6376 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6378 // Load the 'nest' parameter value into R10.
6379 // R10 is specified in X86CallingConv.td
6380 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6382 DAG.getConstant(10, MVT::i64));
6383 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6384 Addr, TrmpAddr, 10);
6386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6387 DAG.getConstant(12, MVT::i64));
6388 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6390 // Jump to the nested function.
6391 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6393 DAG.getConstant(20, MVT::i64));
6394 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6395 Addr, TrmpAddr, 20);
6397 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6398 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6399 DAG.getConstant(22, MVT::i64));
6400 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6404 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6405 return DAG.getMergeValues(Ops, 2, dl);
6407 const Function *Func =
6408 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6409 unsigned CC = Func->getCallingConv();
6414 llvm_unreachable("Unsupported calling convention");
6415 case CallingConv::C:
6416 case CallingConv::X86_StdCall: {
6417 // Pass 'nest' parameter in ECX.
6418 // Must be kept in sync with X86CallingConv.td
6421 // Check that ECX wasn't needed by an 'inreg' parameter.
6422 const FunctionType *FTy = Func->getFunctionType();
6423 const AttrListPtr &Attrs = Func->getAttributes();
6425 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6426 unsigned InRegCount = 0;
6429 for (FunctionType::param_iterator I = FTy->param_begin(),
6430 E = FTy->param_end(); I != E; ++I, ++Idx)
6431 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6432 // FIXME: should only count parameters that are lowered to integers.
6433 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6435 if (InRegCount > 2) {
6436 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6441 case CallingConv::X86_FastCall:
6442 case CallingConv::Fast:
6443 // Pass 'nest' parameter in EAX.
6444 // Must be kept in sync with X86CallingConv.td
6449 SDValue OutChains[4];
6452 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6453 DAG.getConstant(10, MVT::i32));
6454 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6456 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6457 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6458 OutChains[0] = DAG.getStore(Root, dl,
6459 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6462 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6463 DAG.getConstant(1, MVT::i32));
6464 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6466 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6468 DAG.getConstant(5, MVT::i32));
6469 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6470 TrmpAddr, 5, false, 1);
6472 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6473 DAG.getConstant(6, MVT::i32));
6474 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6477 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6478 return DAG.getMergeValues(Ops, 2, dl);
6482 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6484 The rounding mode is in bits 11:10 of FPSR, and has the following
6491 FLT_ROUNDS, on the other hand, expects the following:
6498 To perform the conversion, we do:
6499 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6502 MachineFunction &MF = DAG.getMachineFunction();
6503 const TargetMachine &TM = MF.getTarget();
6504 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6505 unsigned StackAlignment = TFI.getStackAlignment();
6506 MVT VT = Op.getValueType();
6507 DebugLoc dl = Op.getDebugLoc();
6509 // Save FP Control Word to stack slot
6510 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6511 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6513 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6514 DAG.getEntryNode(), StackSlot);
6516 // Load FP Control Word from stack slot
6517 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6519 // Transform as necessary
6521 DAG.getNode(ISD::SRL, dl, MVT::i16,
6522 DAG.getNode(ISD::AND, dl, MVT::i16,
6523 CWD, DAG.getConstant(0x800, MVT::i16)),
6524 DAG.getConstant(11, MVT::i8));
6526 DAG.getNode(ISD::SRL, dl, MVT::i16,
6527 DAG.getNode(ISD::AND, dl, MVT::i16,
6528 CWD, DAG.getConstant(0x400, MVT::i16)),
6529 DAG.getConstant(9, MVT::i8));
6532 DAG.getNode(ISD::AND, dl, MVT::i16,
6533 DAG.getNode(ISD::ADD, dl, MVT::i16,
6534 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6535 DAG.getConstant(1, MVT::i16)),
6536 DAG.getConstant(3, MVT::i16));
6539 return DAG.getNode((VT.getSizeInBits() < 16 ?
6540 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6543 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6544 MVT VT = Op.getValueType();
6546 unsigned NumBits = VT.getSizeInBits();
6547 DebugLoc dl = Op.getDebugLoc();
6549 Op = Op.getOperand(0);
6550 if (VT == MVT::i8) {
6551 // Zero extend to i32 since there is not an i8 bsr.
6553 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6556 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6557 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6558 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6560 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6561 SmallVector<SDValue, 4> Ops;
6563 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6564 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6565 Ops.push_back(Op.getValue(1));
6566 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6568 // Finally xor with NumBits-1.
6569 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6572 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6576 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6577 MVT VT = Op.getValueType();
6579 unsigned NumBits = VT.getSizeInBits();
6580 DebugLoc dl = Op.getDebugLoc();
6582 Op = Op.getOperand(0);
6583 if (VT == MVT::i8) {
6585 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6588 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6589 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6590 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6592 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6593 SmallVector<SDValue, 4> Ops;
6595 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6596 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6597 Ops.push_back(Op.getValue(1));
6598 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6601 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6605 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6606 MVT VT = Op.getValueType();
6607 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6608 DebugLoc dl = Op.getDebugLoc();
6610 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6611 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6612 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6613 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6614 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6616 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6617 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6618 // return AloBlo + AloBhi + AhiBlo;
6620 SDValue A = Op.getOperand(0);
6621 SDValue B = Op.getOperand(1);
6623 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6624 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6625 A, DAG.getConstant(32, MVT::i32));
6626 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6627 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6628 B, DAG.getConstant(32, MVT::i32));
6629 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6630 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6632 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6633 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6635 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6636 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6638 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6639 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6640 AloBhi, DAG.getConstant(32, MVT::i32));
6641 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6642 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6643 AhiBlo, DAG.getConstant(32, MVT::i32));
6644 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6645 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6650 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6651 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6652 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6653 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6654 // has only one use.
6655 SDNode *N = Op.getNode();
6656 SDValue LHS = N->getOperand(0);
6657 SDValue RHS = N->getOperand(1);
6658 unsigned BaseOp = 0;
6660 DebugLoc dl = Op.getDebugLoc();
6662 switch (Op.getOpcode()) {
6663 default: llvm_unreachable("Unknown ovf instruction!");
6665 // A subtract of one will be selected as a INC. Note that INC doesn't
6666 // set CF, so we can't do this for UADDO.
6667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6668 if (C->getAPIntValue() == 1) {
6669 BaseOp = X86ISD::INC;
6673 BaseOp = X86ISD::ADD;
6677 BaseOp = X86ISD::ADD;
6681 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6682 // set CF, so we can't do this for USUBO.
6683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6684 if (C->getAPIntValue() == 1) {
6685 BaseOp = X86ISD::DEC;
6689 BaseOp = X86ISD::SUB;
6693 BaseOp = X86ISD::SUB;
6697 BaseOp = X86ISD::SMUL;
6701 BaseOp = X86ISD::UMUL;
6706 // Also sets EFLAGS.
6707 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6708 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6711 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6712 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6714 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6718 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6719 MVT T = Op.getValueType();
6720 DebugLoc dl = Op.getDebugLoc();
6723 switch(T.getSimpleVT()) {
6725 assert(false && "Invalid value type!");
6726 case MVT::i8: Reg = X86::AL; size = 1; break;
6727 case MVT::i16: Reg = X86::AX; size = 2; break;
6728 case MVT::i32: Reg = X86::EAX; size = 4; break;
6730 assert(Subtarget->is64Bit() && "Node not type legal!");
6731 Reg = X86::RAX; size = 8;
6734 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6735 Op.getOperand(2), SDValue());
6736 SDValue Ops[] = { cpIn.getValue(0),
6739 DAG.getTargetConstant(size, MVT::i8),
6741 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6742 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6744 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6748 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6749 SelectionDAG &DAG) {
6750 assert(Subtarget->is64Bit() && "Result not type legalized?");
6751 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6752 SDValue TheChain = Op.getOperand(0);
6753 DebugLoc dl = Op.getDebugLoc();
6754 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6755 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6756 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6758 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6759 DAG.getConstant(32, MVT::i8));
6761 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6764 return DAG.getMergeValues(Ops, 2, dl);
6767 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6768 SDNode *Node = Op.getNode();
6769 DebugLoc dl = Node->getDebugLoc();
6770 MVT T = Node->getValueType(0);
6771 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6772 DAG.getConstant(0, T), Node->getOperand(2));
6773 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6774 cast<AtomicSDNode>(Node)->getMemoryVT(),
6775 Node->getOperand(0),
6776 Node->getOperand(1), negOp,
6777 cast<AtomicSDNode>(Node)->getSrcValue(),
6778 cast<AtomicSDNode>(Node)->getAlignment());
6781 /// LowerOperation - Provide custom lowering hooks for some operations.
6783 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6784 switch (Op.getOpcode()) {
6785 default: llvm_unreachable("Should not custom lower this!");
6786 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6787 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6788 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6789 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6790 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6791 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6792 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6793 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6794 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6795 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6796 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6797 case ISD::SHL_PARTS:
6798 case ISD::SRA_PARTS:
6799 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6800 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6801 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6802 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6803 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6804 case ISD::FABS: return LowerFABS(Op, DAG);
6805 case ISD::FNEG: return LowerFNEG(Op, DAG);
6806 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6807 case ISD::SETCC: return LowerSETCC(Op, DAG);
6808 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6809 case ISD::SELECT: return LowerSELECT(Op, DAG);
6810 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6811 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6812 case ISD::CALL: return LowerCALL(Op, DAG);
6813 case ISD::RET: return LowerRET(Op, DAG);
6814 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6815 case ISD::VASTART: return LowerVASTART(Op, DAG);
6816 case ISD::VAARG: return LowerVAARG(Op, DAG);
6817 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6818 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6819 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6820 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6821 case ISD::FRAME_TO_ARGS_OFFSET:
6822 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6823 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6824 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6825 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6826 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6827 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6828 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6829 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6835 case ISD::UMULO: return LowerXALUO(Op, DAG);
6836 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6840 void X86TargetLowering::
6841 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6842 SelectionDAG &DAG, unsigned NewOp) {
6843 MVT T = Node->getValueType(0);
6844 DebugLoc dl = Node->getDebugLoc();
6845 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6847 SDValue Chain = Node->getOperand(0);
6848 SDValue In1 = Node->getOperand(1);
6849 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6850 Node->getOperand(2), DAG.getIntPtrConstant(0));
6851 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6852 Node->getOperand(2), DAG.getIntPtrConstant(1));
6853 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6854 // have a MemOperand. Pass the info through as a normal operand.
6855 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6856 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6857 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6858 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6859 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6860 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6861 Results.push_back(Result.getValue(2));
6864 /// ReplaceNodeResults - Replace a node with an illegal result type
6865 /// with a new node built out of custom code.
6866 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6867 SmallVectorImpl<SDValue>&Results,
6868 SelectionDAG &DAG) {
6869 DebugLoc dl = N->getDebugLoc();
6870 switch (N->getOpcode()) {
6872 assert(false && "Do not know how to custom type legalize this operation!");
6874 case ISD::FP_TO_SINT: {
6875 std::pair<SDValue,SDValue> Vals =
6876 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6877 SDValue FIST = Vals.first, StackSlot = Vals.second;
6878 if (FIST.getNode() != 0) {
6879 MVT VT = N->getValueType(0);
6880 // Return a load from the stack slot.
6881 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6885 case ISD::READCYCLECOUNTER: {
6886 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6887 SDValue TheChain = N->getOperand(0);
6888 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6889 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6891 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6893 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6894 SDValue Ops[] = { eax, edx };
6895 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6896 Results.push_back(edx.getValue(1));
6899 case ISD::ATOMIC_CMP_SWAP: {
6900 MVT T = N->getValueType(0);
6901 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6902 SDValue cpInL, cpInH;
6903 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6904 DAG.getConstant(0, MVT::i32));
6905 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6906 DAG.getConstant(1, MVT::i32));
6907 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6908 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6910 SDValue swapInL, swapInH;
6911 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6912 DAG.getConstant(0, MVT::i32));
6913 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6914 DAG.getConstant(1, MVT::i32));
6915 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6917 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6918 swapInL.getValue(1));
6919 SDValue Ops[] = { swapInH.getValue(0),
6921 swapInH.getValue(1) };
6922 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6923 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6924 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6925 MVT::i32, Result.getValue(1));
6926 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6927 MVT::i32, cpOutL.getValue(2));
6928 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6929 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6930 Results.push_back(cpOutH.getValue(1));
6933 case ISD::ATOMIC_LOAD_ADD:
6934 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6936 case ISD::ATOMIC_LOAD_AND:
6937 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6939 case ISD::ATOMIC_LOAD_NAND:
6940 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6942 case ISD::ATOMIC_LOAD_OR:
6943 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6945 case ISD::ATOMIC_LOAD_SUB:
6946 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6948 case ISD::ATOMIC_LOAD_XOR:
6949 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6951 case ISD::ATOMIC_SWAP:
6952 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6957 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6959 default: return NULL;
6960 case X86ISD::BSF: return "X86ISD::BSF";
6961 case X86ISD::BSR: return "X86ISD::BSR";
6962 case X86ISD::SHLD: return "X86ISD::SHLD";
6963 case X86ISD::SHRD: return "X86ISD::SHRD";
6964 case X86ISD::FAND: return "X86ISD::FAND";
6965 case X86ISD::FOR: return "X86ISD::FOR";
6966 case X86ISD::FXOR: return "X86ISD::FXOR";
6967 case X86ISD::FSRL: return "X86ISD::FSRL";
6968 case X86ISD::FILD: return "X86ISD::FILD";
6969 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6970 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6971 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6972 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6973 case X86ISD::FLD: return "X86ISD::FLD";
6974 case X86ISD::FST: return "X86ISD::FST";
6975 case X86ISD::CALL: return "X86ISD::CALL";
6976 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6977 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6978 case X86ISD::BT: return "X86ISD::BT";
6979 case X86ISD::CMP: return "X86ISD::CMP";
6980 case X86ISD::COMI: return "X86ISD::COMI";
6981 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6982 case X86ISD::SETCC: return "X86ISD::SETCC";
6983 case X86ISD::CMOV: return "X86ISD::CMOV";
6984 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6985 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6986 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6987 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6988 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6989 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6990 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
6991 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6992 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6993 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6994 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6995 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6996 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
6997 case X86ISD::FMAX: return "X86ISD::FMAX";
6998 case X86ISD::FMIN: return "X86ISD::FMIN";
6999 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7000 case X86ISD::FRCP: return "X86ISD::FRCP";
7001 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7002 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7003 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7004 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7005 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7006 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7007 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7008 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7009 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7010 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7011 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7012 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7013 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7014 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7015 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7016 case X86ISD::VSHL: return "X86ISD::VSHL";
7017 case X86ISD::VSRL: return "X86ISD::VSRL";
7018 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7019 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7020 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7021 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7022 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7023 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7024 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7025 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7026 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7027 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7028 case X86ISD::ADD: return "X86ISD::ADD";
7029 case X86ISD::SUB: return "X86ISD::SUB";
7030 case X86ISD::SMUL: return "X86ISD::SMUL";
7031 case X86ISD::UMUL: return "X86ISD::UMUL";
7032 case X86ISD::INC: return "X86ISD::INC";
7033 case X86ISD::DEC: return "X86ISD::DEC";
7034 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7038 // isLegalAddressingMode - Return true if the addressing mode represented
7039 // by AM is legal for this target, for a load/store of the specified type.
7040 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7041 const Type *Ty) const {
7042 // X86 supports extremely general addressing modes.
7044 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7045 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7050 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7052 // If a reference to this global requires an extra load, we can't fold it.
7053 if (isGlobalStubReference(GVFlags))
7056 // If BaseGV requires a register for the PIC base, we cannot also have a
7057 // BaseReg specified.
7058 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7061 // X86-64 only supports addr of globals in small code model.
7062 if (Subtarget->is64Bit()) {
7063 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7065 // If lower 4G is not available, then we must use rip-relative addressing.
7066 if (AM.BaseOffs || AM.Scale > 1)
7077 // These scales always work.
7082 // These scales are formed with basereg+scalereg. Only accept if there is
7087 default: // Other stuff never works.
7095 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7096 if (!Ty1->isInteger() || !Ty2->isInteger())
7098 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7099 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7100 if (NumBits1 <= NumBits2)
7102 return Subtarget->is64Bit() || NumBits1 < 64;
7105 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7106 if (!VT1.isInteger() || !VT2.isInteger())
7108 unsigned NumBits1 = VT1.getSizeInBits();
7109 unsigned NumBits2 = VT2.getSizeInBits();
7110 if (NumBits1 <= NumBits2)
7112 return Subtarget->is64Bit() || NumBits1 < 64;
7115 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7116 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7117 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
7120 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
7121 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7122 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7125 bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
7126 // i16 instructions are longer (0x66 prefix) and potentially slower.
7127 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7130 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7131 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7132 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7133 /// are assumed to be legal.
7135 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7137 // Only do shuffles on 128-bit vector types for now.
7138 if (VT.getSizeInBits() == 64)
7141 // FIXME: pshufb, blends, palignr, shifts.
7142 return (VT.getVectorNumElements() == 2 ||
7143 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7144 isMOVLMask(M, VT) ||
7145 isSHUFPMask(M, VT) ||
7146 isPSHUFDMask(M, VT) ||
7147 isPSHUFHWMask(M, VT) ||
7148 isPSHUFLWMask(M, VT) ||
7149 isUNPCKLMask(M, VT) ||
7150 isUNPCKHMask(M, VT) ||
7151 isUNPCKL_v_undef_Mask(M, VT) ||
7152 isUNPCKH_v_undef_Mask(M, VT));
7156 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7158 unsigned NumElts = VT.getVectorNumElements();
7159 // FIXME: This collection of masks seems suspect.
7162 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7163 return (isMOVLMask(Mask, VT) ||
7164 isCommutedMOVLMask(Mask, VT, true) ||
7165 isSHUFPMask(Mask, VT) ||
7166 isCommutedSHUFPMask(Mask, VT));
7171 //===----------------------------------------------------------------------===//
7172 // X86 Scheduler Hooks
7173 //===----------------------------------------------------------------------===//
7175 // private utility function
7177 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7178 MachineBasicBlock *MBB,
7186 TargetRegisterClass *RC,
7187 bool invSrc) const {
7188 // For the atomic bitwise operator, we generate
7191 // ld t1 = [bitinstr.addr]
7192 // op t2 = t1, [bitinstr.val]
7194 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7196 // fallthrough -->nextMBB
7197 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7198 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7199 MachineFunction::iterator MBBIter = MBB;
7202 /// First build the CFG
7203 MachineFunction *F = MBB->getParent();
7204 MachineBasicBlock *thisMBB = MBB;
7205 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7206 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7207 F->insert(MBBIter, newMBB);
7208 F->insert(MBBIter, nextMBB);
7210 // Move all successors to thisMBB to nextMBB
7211 nextMBB->transferSuccessors(thisMBB);
7213 // Update thisMBB to fall through to newMBB
7214 thisMBB->addSuccessor(newMBB);
7216 // newMBB jumps to itself and fall through to nextMBB
7217 newMBB->addSuccessor(nextMBB);
7218 newMBB->addSuccessor(newMBB);
7220 // Insert instructions into newMBB based on incoming instruction
7221 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7222 "unexpected number of operands");
7223 DebugLoc dl = bInstr->getDebugLoc();
7224 MachineOperand& destOper = bInstr->getOperand(0);
7225 MachineOperand* argOpers[2 + X86AddrNumOperands];
7226 int numArgs = bInstr->getNumOperands() - 1;
7227 for (int i=0; i < numArgs; ++i)
7228 argOpers[i] = &bInstr->getOperand(i+1);
7230 // x86 address has 4 operands: base, index, scale, and displacement
7231 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7232 int valArgIndx = lastAddrIndx + 1;
7234 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7235 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7236 for (int i=0; i <= lastAddrIndx; ++i)
7237 (*MIB).addOperand(*argOpers[i]);
7239 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7241 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7246 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7247 assert((argOpers[valArgIndx]->isReg() ||
7248 argOpers[valArgIndx]->isImm()) &&
7250 if (argOpers[valArgIndx]->isReg())
7251 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7253 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7255 (*MIB).addOperand(*argOpers[valArgIndx]);
7257 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7260 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7261 for (int i=0; i <= lastAddrIndx; ++i)
7262 (*MIB).addOperand(*argOpers[i]);
7264 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7265 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7267 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7271 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7273 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7277 // private utility function: 64 bit atomics on 32 bit host.
7279 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7280 MachineBasicBlock *MBB,
7285 bool invSrc) const {
7286 // For the atomic bitwise operator, we generate
7287 // thisMBB (instructions are in pairs, except cmpxchg8b)
7288 // ld t1,t2 = [bitinstr.addr]
7290 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7291 // op t5, t6 <- out1, out2, [bitinstr.val]
7292 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7293 // mov ECX, EBX <- t5, t6
7294 // mov EAX, EDX <- t1, t2
7295 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7296 // mov t3, t4 <- EAX, EDX
7298 // result in out1, out2
7299 // fallthrough -->nextMBB
7301 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7302 const unsigned LoadOpc = X86::MOV32rm;
7303 const unsigned copyOpc = X86::MOV32rr;
7304 const unsigned NotOpc = X86::NOT32r;
7305 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7306 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7307 MachineFunction::iterator MBBIter = MBB;
7310 /// First build the CFG
7311 MachineFunction *F = MBB->getParent();
7312 MachineBasicBlock *thisMBB = MBB;
7313 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7314 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7315 F->insert(MBBIter, newMBB);
7316 F->insert(MBBIter, nextMBB);
7318 // Move all successors to thisMBB to nextMBB
7319 nextMBB->transferSuccessors(thisMBB);
7321 // Update thisMBB to fall through to newMBB
7322 thisMBB->addSuccessor(newMBB);
7324 // newMBB jumps to itself and fall through to nextMBB
7325 newMBB->addSuccessor(nextMBB);
7326 newMBB->addSuccessor(newMBB);
7328 DebugLoc dl = bInstr->getDebugLoc();
7329 // Insert instructions into newMBB based on incoming instruction
7330 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7331 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7332 "unexpected number of operands");
7333 MachineOperand& dest1Oper = bInstr->getOperand(0);
7334 MachineOperand& dest2Oper = bInstr->getOperand(1);
7335 MachineOperand* argOpers[2 + X86AddrNumOperands];
7336 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7337 argOpers[i] = &bInstr->getOperand(i+2);
7339 // x86 address has 4 operands: base, index, scale, and displacement
7340 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7342 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7343 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7344 for (int i=0; i <= lastAddrIndx; ++i)
7345 (*MIB).addOperand(*argOpers[i]);
7346 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7347 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7348 // add 4 to displacement.
7349 for (int i=0; i <= lastAddrIndx-2; ++i)
7350 (*MIB).addOperand(*argOpers[i]);
7351 MachineOperand newOp3 = *(argOpers[3]);
7353 newOp3.setImm(newOp3.getImm()+4);
7355 newOp3.setOffset(newOp3.getOffset()+4);
7356 (*MIB).addOperand(newOp3);
7357 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7359 // t3/4 are defined later, at the bottom of the loop
7360 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7361 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7362 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7363 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7364 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7365 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7367 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7368 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7370 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7371 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7377 int valArgIndx = lastAddrIndx + 1;
7378 assert((argOpers[valArgIndx]->isReg() ||
7379 argOpers[valArgIndx]->isImm()) &&
7381 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7382 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7383 if (argOpers[valArgIndx]->isReg())
7384 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7386 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7387 if (regOpcL != X86::MOV32rr)
7389 (*MIB).addOperand(*argOpers[valArgIndx]);
7390 assert(argOpers[valArgIndx + 1]->isReg() ==
7391 argOpers[valArgIndx]->isReg());
7392 assert(argOpers[valArgIndx + 1]->isImm() ==
7393 argOpers[valArgIndx]->isImm());
7394 if (argOpers[valArgIndx + 1]->isReg())
7395 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7397 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7398 if (regOpcH != X86::MOV32rr)
7400 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7402 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7404 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7407 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7409 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7412 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7413 for (int i=0; i <= lastAddrIndx; ++i)
7414 (*MIB).addOperand(*argOpers[i]);
7416 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7417 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7419 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7420 MIB.addReg(X86::EAX);
7421 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7422 MIB.addReg(X86::EDX);
7425 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7427 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7431 // private utility function
7433 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7434 MachineBasicBlock *MBB,
7435 unsigned cmovOpc) const {
7436 // For the atomic min/max operator, we generate
7439 // ld t1 = [min/max.addr]
7440 // mov t2 = [min/max.val]
7442 // cmov[cond] t2 = t1
7444 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7446 // fallthrough -->nextMBB
7448 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7449 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7450 MachineFunction::iterator MBBIter = MBB;
7453 /// First build the CFG
7454 MachineFunction *F = MBB->getParent();
7455 MachineBasicBlock *thisMBB = MBB;
7456 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7457 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7458 F->insert(MBBIter, newMBB);
7459 F->insert(MBBIter, nextMBB);
7461 // Move all successors to thisMBB to nextMBB
7462 nextMBB->transferSuccessors(thisMBB);
7464 // Update thisMBB to fall through to newMBB
7465 thisMBB->addSuccessor(newMBB);
7467 // newMBB jumps to newMBB and fall through to nextMBB
7468 newMBB->addSuccessor(nextMBB);
7469 newMBB->addSuccessor(newMBB);
7471 DebugLoc dl = mInstr->getDebugLoc();
7472 // Insert instructions into newMBB based on incoming instruction
7473 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7474 "unexpected number of operands");
7475 MachineOperand& destOper = mInstr->getOperand(0);
7476 MachineOperand* argOpers[2 + X86AddrNumOperands];
7477 int numArgs = mInstr->getNumOperands() - 1;
7478 for (int i=0; i < numArgs; ++i)
7479 argOpers[i] = &mInstr->getOperand(i+1);
7481 // x86 address has 4 operands: base, index, scale, and displacement
7482 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7483 int valArgIndx = lastAddrIndx + 1;
7485 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7486 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7487 for (int i=0; i <= lastAddrIndx; ++i)
7488 (*MIB).addOperand(*argOpers[i]);
7490 // We only support register and immediate values
7491 assert((argOpers[valArgIndx]->isReg() ||
7492 argOpers[valArgIndx]->isImm()) &&
7495 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7496 if (argOpers[valArgIndx]->isReg())
7497 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7499 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7500 (*MIB).addOperand(*argOpers[valArgIndx]);
7502 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7505 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7510 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7511 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7515 // Cmp and exchange if none has modified the memory location
7516 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7517 for (int i=0; i <= lastAddrIndx; ++i)
7518 (*MIB).addOperand(*argOpers[i]);
7520 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7521 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7523 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7524 MIB.addReg(X86::EAX);
7527 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7529 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7535 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7536 MachineBasicBlock *BB) const {
7537 DebugLoc dl = MI->getDebugLoc();
7538 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7539 switch (MI->getOpcode()) {
7540 default: assert(false && "Unexpected instr type to insert");
7541 case X86::CMOV_V1I64:
7542 case X86::CMOV_FR32:
7543 case X86::CMOV_FR64:
7544 case X86::CMOV_V4F32:
7545 case X86::CMOV_V2F64:
7546 case X86::CMOV_V2I64: {
7547 // To "insert" a SELECT_CC instruction, we actually have to insert the
7548 // diamond control-flow pattern. The incoming instruction knows the
7549 // destination vreg to set, the condition code register to branch on, the
7550 // true/false values to select between, and a branch opcode to use.
7551 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7552 MachineFunction::iterator It = BB;
7558 // cmpTY ccX, r1, r2
7560 // fallthrough --> copy0MBB
7561 MachineBasicBlock *thisMBB = BB;
7562 MachineFunction *F = BB->getParent();
7563 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7564 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7566 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7567 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7568 F->insert(It, copy0MBB);
7569 F->insert(It, sinkMBB);
7570 // Update machine-CFG edges by transferring all successors of the current
7571 // block to the new block which will contain the Phi node for the select.
7572 sinkMBB->transferSuccessors(BB);
7574 // Add the true and fallthrough blocks as its successors.
7575 BB->addSuccessor(copy0MBB);
7576 BB->addSuccessor(sinkMBB);
7579 // %FalseValue = ...
7580 // # fallthrough to sinkMBB
7583 // Update machine-CFG edges
7584 BB->addSuccessor(sinkMBB);
7587 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7590 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7591 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7592 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7594 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7598 case X86::FP32_TO_INT16_IN_MEM:
7599 case X86::FP32_TO_INT32_IN_MEM:
7600 case X86::FP32_TO_INT64_IN_MEM:
7601 case X86::FP64_TO_INT16_IN_MEM:
7602 case X86::FP64_TO_INT32_IN_MEM:
7603 case X86::FP64_TO_INT64_IN_MEM:
7604 case X86::FP80_TO_INT16_IN_MEM:
7605 case X86::FP80_TO_INT32_IN_MEM:
7606 case X86::FP80_TO_INT64_IN_MEM: {
7607 // Change the floating point control register to use "round towards zero"
7608 // mode when truncating to an integer value.
7609 MachineFunction *F = BB->getParent();
7610 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7611 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7613 // Load the old value of the high byte of the control word...
7615 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7616 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7619 // Set the high part to be round to zero...
7620 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7623 // Reload the modified control word now...
7624 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7626 // Restore the memory image of control word to original value
7627 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7630 // Get the X86 opcode to use.
7632 switch (MI->getOpcode()) {
7633 default: llvm_unreachable("illegal opcode!");
7634 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7635 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7636 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7637 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7638 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7639 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7640 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7641 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7642 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7646 MachineOperand &Op = MI->getOperand(0);
7648 AM.BaseType = X86AddressMode::RegBase;
7649 AM.Base.Reg = Op.getReg();
7651 AM.BaseType = X86AddressMode::FrameIndexBase;
7652 AM.Base.FrameIndex = Op.getIndex();
7654 Op = MI->getOperand(1);
7656 AM.Scale = Op.getImm();
7657 Op = MI->getOperand(2);
7659 AM.IndexReg = Op.getImm();
7660 Op = MI->getOperand(3);
7661 if (Op.isGlobal()) {
7662 AM.GV = Op.getGlobal();
7664 AM.Disp = Op.getImm();
7666 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7667 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7669 // Reload the original control word now.
7670 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7672 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7675 case X86::ATOMAND32:
7676 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7677 X86::AND32ri, X86::MOV32rm,
7678 X86::LCMPXCHG32, X86::MOV32rr,
7679 X86::NOT32r, X86::EAX,
7680 X86::GR32RegisterClass);
7682 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7683 X86::OR32ri, X86::MOV32rm,
7684 X86::LCMPXCHG32, X86::MOV32rr,
7685 X86::NOT32r, X86::EAX,
7686 X86::GR32RegisterClass);
7687 case X86::ATOMXOR32:
7688 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7689 X86::XOR32ri, X86::MOV32rm,
7690 X86::LCMPXCHG32, X86::MOV32rr,
7691 X86::NOT32r, X86::EAX,
7692 X86::GR32RegisterClass);
7693 case X86::ATOMNAND32:
7694 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7695 X86::AND32ri, X86::MOV32rm,
7696 X86::LCMPXCHG32, X86::MOV32rr,
7697 X86::NOT32r, X86::EAX,
7698 X86::GR32RegisterClass, true);
7699 case X86::ATOMMIN32:
7700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7701 case X86::ATOMMAX32:
7702 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7703 case X86::ATOMUMIN32:
7704 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7705 case X86::ATOMUMAX32:
7706 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7708 case X86::ATOMAND16:
7709 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7710 X86::AND16ri, X86::MOV16rm,
7711 X86::LCMPXCHG16, X86::MOV16rr,
7712 X86::NOT16r, X86::AX,
7713 X86::GR16RegisterClass);
7715 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7716 X86::OR16ri, X86::MOV16rm,
7717 X86::LCMPXCHG16, X86::MOV16rr,
7718 X86::NOT16r, X86::AX,
7719 X86::GR16RegisterClass);
7720 case X86::ATOMXOR16:
7721 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7722 X86::XOR16ri, X86::MOV16rm,
7723 X86::LCMPXCHG16, X86::MOV16rr,
7724 X86::NOT16r, X86::AX,
7725 X86::GR16RegisterClass);
7726 case X86::ATOMNAND16:
7727 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7728 X86::AND16ri, X86::MOV16rm,
7729 X86::LCMPXCHG16, X86::MOV16rr,
7730 X86::NOT16r, X86::AX,
7731 X86::GR16RegisterClass, true);
7732 case X86::ATOMMIN16:
7733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7734 case X86::ATOMMAX16:
7735 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7736 case X86::ATOMUMIN16:
7737 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7738 case X86::ATOMUMAX16:
7739 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7742 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7743 X86::AND8ri, X86::MOV8rm,
7744 X86::LCMPXCHG8, X86::MOV8rr,
7745 X86::NOT8r, X86::AL,
7746 X86::GR8RegisterClass);
7748 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7749 X86::OR8ri, X86::MOV8rm,
7750 X86::LCMPXCHG8, X86::MOV8rr,
7751 X86::NOT8r, X86::AL,
7752 X86::GR8RegisterClass);
7754 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7755 X86::XOR8ri, X86::MOV8rm,
7756 X86::LCMPXCHG8, X86::MOV8rr,
7757 X86::NOT8r, X86::AL,
7758 X86::GR8RegisterClass);
7759 case X86::ATOMNAND8:
7760 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7761 X86::AND8ri, X86::MOV8rm,
7762 X86::LCMPXCHG8, X86::MOV8rr,
7763 X86::NOT8r, X86::AL,
7764 X86::GR8RegisterClass, true);
7765 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7766 // This group is for 64-bit host.
7767 case X86::ATOMAND64:
7768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7769 X86::AND64ri32, X86::MOV64rm,
7770 X86::LCMPXCHG64, X86::MOV64rr,
7771 X86::NOT64r, X86::RAX,
7772 X86::GR64RegisterClass);
7774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7775 X86::OR64ri32, X86::MOV64rm,
7776 X86::LCMPXCHG64, X86::MOV64rr,
7777 X86::NOT64r, X86::RAX,
7778 X86::GR64RegisterClass);
7779 case X86::ATOMXOR64:
7780 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7781 X86::XOR64ri32, X86::MOV64rm,
7782 X86::LCMPXCHG64, X86::MOV64rr,
7783 X86::NOT64r, X86::RAX,
7784 X86::GR64RegisterClass);
7785 case X86::ATOMNAND64:
7786 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7787 X86::AND64ri32, X86::MOV64rm,
7788 X86::LCMPXCHG64, X86::MOV64rr,
7789 X86::NOT64r, X86::RAX,
7790 X86::GR64RegisterClass, true);
7791 case X86::ATOMMIN64:
7792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7793 case X86::ATOMMAX64:
7794 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7795 case X86::ATOMUMIN64:
7796 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7797 case X86::ATOMUMAX64:
7798 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7800 // This group does 64-bit operations on a 32-bit host.
7801 case X86::ATOMAND6432:
7802 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7803 X86::AND32rr, X86::AND32rr,
7804 X86::AND32ri, X86::AND32ri,
7806 case X86::ATOMOR6432:
7807 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7808 X86::OR32rr, X86::OR32rr,
7809 X86::OR32ri, X86::OR32ri,
7811 case X86::ATOMXOR6432:
7812 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7813 X86::XOR32rr, X86::XOR32rr,
7814 X86::XOR32ri, X86::XOR32ri,
7816 case X86::ATOMNAND6432:
7817 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7818 X86::AND32rr, X86::AND32rr,
7819 X86::AND32ri, X86::AND32ri,
7821 case X86::ATOMADD6432:
7822 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7823 X86::ADD32rr, X86::ADC32rr,
7824 X86::ADD32ri, X86::ADC32ri,
7826 case X86::ATOMSUB6432:
7827 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7828 X86::SUB32rr, X86::SBB32rr,
7829 X86::SUB32ri, X86::SBB32ri,
7831 case X86::ATOMSWAP6432:
7832 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7833 X86::MOV32rr, X86::MOV32rr,
7834 X86::MOV32ri, X86::MOV32ri,
7839 //===----------------------------------------------------------------------===//
7840 // X86 Optimization Hooks
7841 //===----------------------------------------------------------------------===//
7843 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7847 const SelectionDAG &DAG,
7848 unsigned Depth) const {
7849 unsigned Opc = Op.getOpcode();
7850 assert((Opc >= ISD::BUILTIN_OP_END ||
7851 Opc == ISD::INTRINSIC_WO_CHAIN ||
7852 Opc == ISD::INTRINSIC_W_CHAIN ||
7853 Opc == ISD::INTRINSIC_VOID) &&
7854 "Should use MaskedValueIsZero if you don't know whether Op"
7855 " is a target node!");
7857 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7866 // These nodes' second result is a boolean.
7867 if (Op.getResNo() == 0)
7871 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7872 Mask.getBitWidth() - 1);
7877 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7878 /// node is a GlobalAddress + offset.
7879 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7880 GlobalValue* &GA, int64_t &Offset) const{
7881 if (N->getOpcode() == X86ISD::Wrapper) {
7882 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7883 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7884 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7888 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7891 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7892 const TargetLowering &TLI) {
7895 if (TLI.isGAPlusOffset(Base, GV, Offset))
7896 return (GV->getAlignment() >= N && (Offset % N) == 0);
7897 // DAG combine handles the stack object case.
7901 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7902 MVT EVT, LoadSDNode *&LDBase,
7903 unsigned &LastLoadedElt,
7904 SelectionDAG &DAG, MachineFrameInfo *MFI,
7905 const TargetLowering &TLI) {
7907 LastLoadedElt = -1U;
7908 for (unsigned i = 0; i < NumElems; ++i) {
7909 if (N->getMaskElt(i) < 0) {
7915 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7916 if (!Elt.getNode() ||
7917 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7920 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7922 LDBase = cast<LoadSDNode>(Elt.getNode());
7926 if (Elt.getOpcode() == ISD::UNDEF)
7929 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7930 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7937 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7938 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7939 /// if the load addresses are consecutive, non-overlapping, and in the right
7940 /// order. In the case of v2i64, it will see if it can rewrite the
7941 /// shuffle to be an appropriate build vector so it can take advantage of
7942 // performBuildVectorCombine.
7943 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7944 const TargetLowering &TLI) {
7945 DebugLoc dl = N->getDebugLoc();
7946 MVT VT = N->getValueType(0);
7947 MVT EVT = VT.getVectorElementType();
7948 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7949 unsigned NumElems = VT.getVectorNumElements();
7951 if (VT.getSizeInBits() != 128)
7954 // Try to combine a vector_shuffle into a 128-bit load.
7955 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7956 LoadSDNode *LD = NULL;
7957 unsigned LastLoadedElt;
7958 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
7962 if (LastLoadedElt == NumElems - 1) {
7963 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
7964 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7965 LD->getSrcValue(), LD->getSrcValueOffset(),
7967 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7968 LD->getSrcValue(), LD->getSrcValueOffset(),
7969 LD->isVolatile(), LD->getAlignment());
7970 } else if (NumElems == 4 && LastLoadedElt == 1) {
7971 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
7972 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7973 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
7974 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
7979 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7980 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7981 const X86Subtarget *Subtarget) {
7982 DebugLoc DL = N->getDebugLoc();
7983 SDValue Cond = N->getOperand(0);
7984 // Get the LHS/RHS of the select.
7985 SDValue LHS = N->getOperand(1);
7986 SDValue RHS = N->getOperand(2);
7988 // If we have SSE[12] support, try to form min/max nodes.
7989 if (Subtarget->hasSSE2() &&
7990 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
7991 Cond.getOpcode() == ISD::SETCC) {
7992 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7994 unsigned Opcode = 0;
7995 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7998 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8001 if (!UnsafeFPMath) break;
8003 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8005 Opcode = X86ISD::FMIN;
8008 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8011 if (!UnsafeFPMath) break;
8013 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8015 Opcode = X86ISD::FMAX;
8018 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8021 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8024 if (!UnsafeFPMath) break;
8026 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8028 Opcode = X86ISD::FMIN;
8031 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8034 if (!UnsafeFPMath) break;
8036 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8038 Opcode = X86ISD::FMAX;
8044 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8047 // If this is a select between two integer constants, try to do some
8049 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8050 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8051 // Don't do this for crazy integer types.
8052 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8053 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8054 // so that TrueC (the true value) is larger than FalseC.
8055 bool NeedsCondInvert = false;
8057 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8058 // Efficiently invertible.
8059 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8060 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8061 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8062 NeedsCondInvert = true;
8063 std::swap(TrueC, FalseC);
8066 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8067 if (FalseC->getAPIntValue() == 0 &&
8068 TrueC->getAPIntValue().isPowerOf2()) {
8069 if (NeedsCondInvert) // Invert the condition if needed.
8070 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8071 DAG.getConstant(1, Cond.getValueType()));
8073 // Zero extend the condition if needed.
8074 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8076 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8077 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8078 DAG.getConstant(ShAmt, MVT::i8));
8081 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8082 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8083 if (NeedsCondInvert) // Invert the condition if needed.
8084 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8085 DAG.getConstant(1, Cond.getValueType()));
8087 // Zero extend the condition if needed.
8088 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8089 FalseC->getValueType(0), Cond);
8090 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8091 SDValue(FalseC, 0));
8094 // Optimize cases that will turn into an LEA instruction. This requires
8095 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8096 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8097 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8098 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8100 bool isFastMultiplier = false;
8102 switch ((unsigned char)Diff) {
8104 case 1: // result = add base, cond
8105 case 2: // result = lea base( , cond*2)
8106 case 3: // result = lea base(cond, cond*2)
8107 case 4: // result = lea base( , cond*4)
8108 case 5: // result = lea base(cond, cond*4)
8109 case 8: // result = lea base( , cond*8)
8110 case 9: // result = lea base(cond, cond*8)
8111 isFastMultiplier = true;
8116 if (isFastMultiplier) {
8117 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8118 if (NeedsCondInvert) // Invert the condition if needed.
8119 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8120 DAG.getConstant(1, Cond.getValueType()));
8122 // Zero extend the condition if needed.
8123 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8125 // Scale the condition by the difference.
8127 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8128 DAG.getConstant(Diff, Cond.getValueType()));
8130 // Add the base if non-zero.
8131 if (FalseC->getAPIntValue() != 0)
8132 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8133 SDValue(FalseC, 0));
8143 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8144 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8145 TargetLowering::DAGCombinerInfo &DCI) {
8146 DebugLoc DL = N->getDebugLoc();
8148 // If the flag operand isn't dead, don't touch this CMOV.
8149 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8152 // If this is a select between two integer constants, try to do some
8153 // optimizations. Note that the operands are ordered the opposite of SELECT
8155 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8156 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8157 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8158 // larger than FalseC (the false value).
8159 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8161 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8162 CC = X86::GetOppositeBranchCondition(CC);
8163 std::swap(TrueC, FalseC);
8166 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8167 // This is efficient for any integer data type (including i8/i16) and
8169 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8170 SDValue Cond = N->getOperand(3);
8171 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8172 DAG.getConstant(CC, MVT::i8), Cond);
8174 // Zero extend the condition if needed.
8175 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8177 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8178 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8179 DAG.getConstant(ShAmt, MVT::i8));
8180 if (N->getNumValues() == 2) // Dead flag value?
8181 return DCI.CombineTo(N, Cond, SDValue());
8185 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8186 // for any integer data type, including i8/i16.
8187 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8188 SDValue Cond = N->getOperand(3);
8189 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8190 DAG.getConstant(CC, MVT::i8), Cond);
8192 // Zero extend the condition if needed.
8193 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8194 FalseC->getValueType(0), Cond);
8195 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8196 SDValue(FalseC, 0));
8198 if (N->getNumValues() == 2) // Dead flag value?
8199 return DCI.CombineTo(N, Cond, SDValue());
8203 // Optimize cases that will turn into an LEA instruction. This requires
8204 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8205 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8206 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8207 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8209 bool isFastMultiplier = false;
8211 switch ((unsigned char)Diff) {
8213 case 1: // result = add base, cond
8214 case 2: // result = lea base( , cond*2)
8215 case 3: // result = lea base(cond, cond*2)
8216 case 4: // result = lea base( , cond*4)
8217 case 5: // result = lea base(cond, cond*4)
8218 case 8: // result = lea base( , cond*8)
8219 case 9: // result = lea base(cond, cond*8)
8220 isFastMultiplier = true;
8225 if (isFastMultiplier) {
8226 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8227 SDValue Cond = N->getOperand(3);
8228 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8229 DAG.getConstant(CC, MVT::i8), Cond);
8230 // Zero extend the condition if needed.
8231 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8233 // Scale the condition by the difference.
8235 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8236 DAG.getConstant(Diff, Cond.getValueType()));
8238 // Add the base if non-zero.
8239 if (FalseC->getAPIntValue() != 0)
8240 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8241 SDValue(FalseC, 0));
8242 if (N->getNumValues() == 2) // Dead flag value?
8243 return DCI.CombineTo(N, Cond, SDValue());
8253 /// PerformMulCombine - Optimize a single multiply with constant into two
8254 /// in order to implement it with two cheaper instructions, e.g.
8255 /// LEA + SHL, LEA + LEA.
8256 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8257 TargetLowering::DAGCombinerInfo &DCI) {
8258 if (DAG.getMachineFunction().
8259 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8262 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8265 MVT VT = N->getValueType(0);
8269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8272 uint64_t MulAmt = C->getZExtValue();
8273 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8276 uint64_t MulAmt1 = 0;
8277 uint64_t MulAmt2 = 0;
8278 if ((MulAmt % 9) == 0) {
8280 MulAmt2 = MulAmt / 9;
8281 } else if ((MulAmt % 5) == 0) {
8283 MulAmt2 = MulAmt / 5;
8284 } else if ((MulAmt % 3) == 0) {
8286 MulAmt2 = MulAmt / 3;
8289 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8290 DebugLoc DL = N->getDebugLoc();
8292 if (isPowerOf2_64(MulAmt2) &&
8293 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8294 // If second multiplifer is pow2, issue it first. We want the multiply by
8295 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8297 std::swap(MulAmt1, MulAmt2);
8300 if (isPowerOf2_64(MulAmt1))
8301 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8302 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8304 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8305 DAG.getConstant(MulAmt1, VT));
8307 if (isPowerOf2_64(MulAmt2))
8308 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8309 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8311 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8312 DAG.getConstant(MulAmt2, VT));
8314 // Do not add new nodes to DAG combiner worklist.
8315 DCI.CombineTo(N, NewMul, false);
8321 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8323 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8324 const X86Subtarget *Subtarget) {
8325 // On X86 with SSE2 support, we can transform this to a vector shift if
8326 // all elements are shifted by the same amount. We can't do this in legalize
8327 // because the a constant vector is typically transformed to a constant pool
8328 // so we have no knowledge of the shift amount.
8329 if (!Subtarget->hasSSE2())
8332 MVT VT = N->getValueType(0);
8333 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8336 SDValue ShAmtOp = N->getOperand(1);
8337 MVT EltVT = VT.getVectorElementType();
8338 DebugLoc DL = N->getDebugLoc();
8340 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8341 unsigned NumElts = VT.getVectorNumElements();
8343 for (; i != NumElts; ++i) {
8344 SDValue Arg = ShAmtOp.getOperand(i);
8345 if (Arg.getOpcode() == ISD::UNDEF) continue;
8349 for (; i != NumElts; ++i) {
8350 SDValue Arg = ShAmtOp.getOperand(i);
8351 if (Arg.getOpcode() == ISD::UNDEF) continue;
8352 if (Arg != BaseShAmt) {
8356 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8357 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8358 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8359 DAG.getIntPtrConstant(0));
8363 if (EltVT.bitsGT(MVT::i32))
8364 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8365 else if (EltVT.bitsLT(MVT::i32))
8366 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8368 // The shift amount is identical so we can do a vector shift.
8369 SDValue ValOp = N->getOperand(0);
8370 switch (N->getOpcode()) {
8372 llvm_unreachable("Unknown shift opcode!");
8375 if (VT == MVT::v2i64)
8376 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8377 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8379 if (VT == MVT::v4i32)
8380 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8381 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8383 if (VT == MVT::v8i16)
8384 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8385 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8389 if (VT == MVT::v4i32)
8390 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8391 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8393 if (VT == MVT::v8i16)
8394 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8395 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8399 if (VT == MVT::v2i64)
8400 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8401 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8403 if (VT == MVT::v4i32)
8404 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8405 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8407 if (VT == MVT::v8i16)
8408 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8409 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8416 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8417 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8418 const X86Subtarget *Subtarget) {
8419 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8420 // the FP state in cases where an emms may be missing.
8421 // A preferable solution to the general problem is to figure out the right
8422 // places to insert EMMS. This qualifies as a quick hack.
8424 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8425 StoreSDNode *St = cast<StoreSDNode>(N);
8426 MVT VT = St->getValue().getValueType();
8427 if (VT.getSizeInBits() != 64)
8430 const Function *F = DAG.getMachineFunction().getFunction();
8431 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8432 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8433 && Subtarget->hasSSE2();
8434 if ((VT.isVector() ||
8435 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8436 isa<LoadSDNode>(St->getValue()) &&
8437 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8438 St->getChain().hasOneUse() && !St->isVolatile()) {
8439 SDNode* LdVal = St->getValue().getNode();
8441 int TokenFactorIndex = -1;
8442 SmallVector<SDValue, 8> Ops;
8443 SDNode* ChainVal = St->getChain().getNode();
8444 // Must be a store of a load. We currently handle two cases: the load
8445 // is a direct child, and it's under an intervening TokenFactor. It is
8446 // possible to dig deeper under nested TokenFactors.
8447 if (ChainVal == LdVal)
8448 Ld = cast<LoadSDNode>(St->getChain());
8449 else if (St->getValue().hasOneUse() &&
8450 ChainVal->getOpcode() == ISD::TokenFactor) {
8451 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8452 if (ChainVal->getOperand(i).getNode() == LdVal) {
8453 TokenFactorIndex = i;
8454 Ld = cast<LoadSDNode>(St->getValue());
8456 Ops.push_back(ChainVal->getOperand(i));
8460 if (!Ld || !ISD::isNormalLoad(Ld))
8463 // If this is not the MMX case, i.e. we are just turning i64 load/store
8464 // into f64 load/store, avoid the transformation if there are multiple
8465 // uses of the loaded value.
8466 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8469 DebugLoc LdDL = Ld->getDebugLoc();
8470 DebugLoc StDL = N->getDebugLoc();
8471 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8472 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8474 if (Subtarget->is64Bit() || F64IsLegal) {
8475 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8476 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8477 Ld->getBasePtr(), Ld->getSrcValue(),
8478 Ld->getSrcValueOffset(), Ld->isVolatile(),
8479 Ld->getAlignment());
8480 SDValue NewChain = NewLd.getValue(1);
8481 if (TokenFactorIndex != -1) {
8482 Ops.push_back(NewChain);
8483 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8486 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8487 St->getSrcValue(), St->getSrcValueOffset(),
8488 St->isVolatile(), St->getAlignment());
8491 // Otherwise, lower to two pairs of 32-bit loads / stores.
8492 SDValue LoAddr = Ld->getBasePtr();
8493 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8494 DAG.getConstant(4, MVT::i32));
8496 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8497 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8498 Ld->isVolatile(), Ld->getAlignment());
8499 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8500 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8502 MinAlign(Ld->getAlignment(), 4));
8504 SDValue NewChain = LoLd.getValue(1);
8505 if (TokenFactorIndex != -1) {
8506 Ops.push_back(LoLd);
8507 Ops.push_back(HiLd);
8508 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8512 LoAddr = St->getBasePtr();
8513 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8514 DAG.getConstant(4, MVT::i32));
8516 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8517 St->getSrcValue(), St->getSrcValueOffset(),
8518 St->isVolatile(), St->getAlignment());
8519 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8521 St->getSrcValueOffset() + 4,
8523 MinAlign(St->getAlignment(), 4));
8524 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8529 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8530 /// X86ISD::FXOR nodes.
8531 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8532 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8533 // F[X]OR(0.0, x) -> x
8534 // F[X]OR(x, 0.0) -> x
8535 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8536 if (C->getValueAPF().isPosZero())
8537 return N->getOperand(1);
8538 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8539 if (C->getValueAPF().isPosZero())
8540 return N->getOperand(0);
8544 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8545 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8546 // FAND(0.0, x) -> 0.0
8547 // FAND(x, 0.0) -> 0.0
8548 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8549 if (C->getValueAPF().isPosZero())
8550 return N->getOperand(0);
8551 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8552 if (C->getValueAPF().isPosZero())
8553 return N->getOperand(1);
8557 static SDValue PerformBTCombine(SDNode *N,
8559 TargetLowering::DAGCombinerInfo &DCI) {
8560 // BT ignores high bits in the bit index operand.
8561 SDValue Op1 = N->getOperand(1);
8562 if (Op1.hasOneUse()) {
8563 unsigned BitWidth = Op1.getValueSizeInBits();
8564 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8565 APInt KnownZero, KnownOne;
8566 TargetLowering::TargetLoweringOpt TLO(DAG);
8567 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8568 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8569 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8570 DCI.CommitTargetLoweringOpt(TLO);
8575 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8576 SDValue Op = N->getOperand(0);
8577 if (Op.getOpcode() == ISD::BIT_CONVERT)
8578 Op = Op.getOperand(0);
8579 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8580 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8581 VT.getVectorElementType().getSizeInBits() ==
8582 OpVT.getVectorElementType().getSizeInBits()) {
8583 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8588 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8589 // Locked instructions, in turn, have implicit fence semantics (all memory
8590 // operations are flushed before issuing the locked instruction, and the
8591 // are not buffered), so we can fold away the common pattern of
8592 // fence-atomic-fence.
8593 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8594 SDValue atomic = N->getOperand(0);
8595 switch (atomic.getOpcode()) {
8596 case ISD::ATOMIC_CMP_SWAP:
8597 case ISD::ATOMIC_SWAP:
8598 case ISD::ATOMIC_LOAD_ADD:
8599 case ISD::ATOMIC_LOAD_SUB:
8600 case ISD::ATOMIC_LOAD_AND:
8601 case ISD::ATOMIC_LOAD_OR:
8602 case ISD::ATOMIC_LOAD_XOR:
8603 case ISD::ATOMIC_LOAD_NAND:
8604 case ISD::ATOMIC_LOAD_MIN:
8605 case ISD::ATOMIC_LOAD_MAX:
8606 case ISD::ATOMIC_LOAD_UMIN:
8607 case ISD::ATOMIC_LOAD_UMAX:
8613 SDValue fence = atomic.getOperand(0);
8614 if (fence.getOpcode() != ISD::MEMBARRIER)
8617 switch (atomic.getOpcode()) {
8618 case ISD::ATOMIC_CMP_SWAP:
8619 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8620 atomic.getOperand(1), atomic.getOperand(2),
8621 atomic.getOperand(3));
8622 case ISD::ATOMIC_SWAP:
8623 case ISD::ATOMIC_LOAD_ADD:
8624 case ISD::ATOMIC_LOAD_SUB:
8625 case ISD::ATOMIC_LOAD_AND:
8626 case ISD::ATOMIC_LOAD_OR:
8627 case ISD::ATOMIC_LOAD_XOR:
8628 case ISD::ATOMIC_LOAD_NAND:
8629 case ISD::ATOMIC_LOAD_MIN:
8630 case ISD::ATOMIC_LOAD_MAX:
8631 case ISD::ATOMIC_LOAD_UMIN:
8632 case ISD::ATOMIC_LOAD_UMAX:
8633 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8634 atomic.getOperand(1), atomic.getOperand(2));
8640 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8641 DAGCombinerInfo &DCI) const {
8642 SelectionDAG &DAG = DCI.DAG;
8643 switch (N->getOpcode()) {
8645 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8646 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8647 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8648 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8651 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8652 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8654 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8655 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8656 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8657 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8658 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8664 //===----------------------------------------------------------------------===//
8665 // X86 Inline Assembly Support
8666 //===----------------------------------------------------------------------===//
8668 static bool LowerToBSwap(CallInst *CI) {
8669 // FIXME: this should verify that we are targetting a 486 or better. If not,
8670 // we will turn this bswap into something that will be lowered to logical ops
8671 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8672 // so don't worry about this.
8674 // Verify this is a simple bswap.
8675 if (CI->getNumOperands() != 2 ||
8676 CI->getType() != CI->getOperand(1)->getType() ||
8677 !CI->getType()->isInteger())
8680 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8681 if (!Ty || Ty->getBitWidth() % 16 != 0)
8684 // Okay, we can do this xform, do so now.
8685 const Type *Tys[] = { Ty };
8686 Module *M = CI->getParent()->getParent()->getParent();
8687 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8689 Value *Op = CI->getOperand(1);
8690 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8692 CI->replaceAllUsesWith(Op);
8693 CI->eraseFromParent();
8697 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
8698 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8699 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
8701 std::string AsmStr = IA->getAsmString();
8703 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
8704 std::vector<std::string> AsmPieces;
8705 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
8707 switch (AsmPieces.size()) {
8708 default: return false;
8710 AsmStr = AsmPieces[0];
8712 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
8715 if (AsmPieces.size() == 2 &&
8716 (AsmPieces[0] == "bswap" ||
8717 AsmPieces[0] == "bswapq" ||
8718 AsmPieces[0] == "bswapl") &&
8719 (AsmPieces[1] == "$0" ||
8720 AsmPieces[1] == "${0:q}")) {
8721 // No need to check constraints, nothing other than the equivalent of
8722 // "=r,0" would be valid here.
8723 return LowerToBSwap(CI);
8725 // rorw $$8, ${0:w} --> llvm.bswap.i16
8726 if (CI->getType() == Type::Int16Ty &&
8727 AsmPieces.size() == 3 &&
8728 AsmPieces[0] == "rorw" &&
8729 AsmPieces[1] == "$$8," &&
8730 AsmPieces[2] == "${0:w}" &&
8731 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
8732 return LowerToBSwap(CI);
8736 if (CI->getType() == Type::Int64Ty && Constraints.size() >= 2 &&
8737 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
8738 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
8739 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
8740 std::vector<std::string> Words;
8741 SplitString(AsmPieces[0], Words, " \t");
8742 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
8744 SplitString(AsmPieces[1], Words, " \t");
8745 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
8747 SplitString(AsmPieces[2], Words, " \t,");
8748 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
8749 Words[2] == "%edx") {
8750 return LowerToBSwap(CI);
8762 /// getConstraintType - Given a constraint letter, return the type of
8763 /// constraint it is for this target.
8764 X86TargetLowering::ConstraintType
8765 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8766 if (Constraint.size() == 1) {
8767 switch (Constraint[0]) {
8779 return C_RegisterClass;
8787 return TargetLowering::getConstraintType(Constraint);
8790 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8791 /// with another that has more specific requirements based on the type of the
8792 /// corresponding operand.
8793 const char *X86TargetLowering::
8794 LowerXConstraint(MVT ConstraintVT) const {
8795 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8796 // 'f' like normal targets.
8797 if (ConstraintVT.isFloatingPoint()) {
8798 if (Subtarget->hasSSE2())
8800 if (Subtarget->hasSSE1())
8804 return TargetLowering::LowerXConstraint(ConstraintVT);
8807 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8808 /// vector. If it is invalid, don't add anything to Ops.
8809 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8812 std::vector<SDValue>&Ops,
8813 SelectionDAG &DAG) const {
8814 SDValue Result(0, 0);
8816 switch (Constraint) {
8819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8820 if (C->getZExtValue() <= 31) {
8821 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8828 if (C->getZExtValue() <= 63) {
8829 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8836 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
8837 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8844 if (C->getZExtValue() <= 255) {
8845 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8851 // 32-bit signed value
8852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8853 const ConstantInt *CI = C->getConstantIntValue();
8854 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8855 // Widen to 64 bits here to get it sign extended.
8856 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8859 // FIXME gcc accepts some relocatable values here too, but only in certain
8860 // memory models; it's complicated.
8865 // 32-bit unsigned value
8866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8867 const ConstantInt *CI = C->getConstantIntValue();
8868 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8869 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8873 // FIXME gcc accepts some relocatable values here too, but only in certain
8874 // memory models; it's complicated.
8878 // Literal immediates are always ok.
8879 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8880 // Widen to 64 bits here to get it sign extended.
8881 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8885 // If we are in non-pic codegen mode, we allow the address of a global (with
8886 // an optional displacement) to be used with 'i'.
8887 GlobalAddressSDNode *GA = 0;
8890 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8892 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8893 Offset += GA->getOffset();
8895 } else if (Op.getOpcode() == ISD::ADD) {
8896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8897 Offset += C->getZExtValue();
8898 Op = Op.getOperand(0);
8901 } else if (Op.getOpcode() == ISD::SUB) {
8902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8903 Offset += -C->getZExtValue();
8904 Op = Op.getOperand(0);
8909 // Otherwise, this isn't something we can handle, reject it.
8913 GlobalValue *GV = GA->getGlobal();
8914 // If we require an extra load to get this address, as in PIC mode, we
8916 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
8917 getTargetMachine())))
8921 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
8923 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
8929 if (Result.getNode()) {
8930 Ops.push_back(Result);
8933 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8937 std::vector<unsigned> X86TargetLowering::
8938 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8940 if (Constraint.size() == 1) {
8941 // FIXME: not handling fp-stack yet!
8942 switch (Constraint[0]) { // GCC X86 Constraint Letters
8943 default: break; // Unknown constraint letter
8944 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
8945 if (Subtarget->is64Bit()) {
8947 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
8948 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
8949 X86::R10D,X86::R11D,X86::R12D,
8950 X86::R13D,X86::R14D,X86::R15D,
8951 X86::EBP, X86::ESP, 0);
8952 else if (VT == MVT::i16)
8953 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
8954 X86::SI, X86::DI, X86::R8W,X86::R9W,
8955 X86::R10W,X86::R11W,X86::R12W,
8956 X86::R13W,X86::R14W,X86::R15W,
8957 X86::BP, X86::SP, 0);
8958 else if (VT == MVT::i8)
8959 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
8960 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
8961 X86::R10B,X86::R11B,X86::R12B,
8962 X86::R13B,X86::R14B,X86::R15B,
8963 X86::BPL, X86::SPL, 0);
8965 else if (VT == MVT::i64)
8966 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
8967 X86::RSI, X86::RDI, X86::R8, X86::R9,
8968 X86::R10, X86::R11, X86::R12,
8969 X86::R13, X86::R14, X86::R15,
8970 X86::RBP, X86::RSP, 0);
8974 // 32-bit fallthrough
8977 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8978 else if (VT == MVT::i16)
8979 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8980 else if (VT == MVT::i8)
8981 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8982 else if (VT == MVT::i64)
8983 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8988 return std::vector<unsigned>();
8991 std::pair<unsigned, const TargetRegisterClass*>
8992 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8994 // First, see if this is a constraint that directly corresponds to an LLVM
8996 if (Constraint.size() == 1) {
8997 // GCC Constraint Letters
8998 switch (Constraint[0]) {
9000 case 'r': // GENERAL_REGS
9001 case 'R': // LEGACY_REGS
9002 case 'l': // INDEX_REGS
9004 return std::make_pair(0U, X86::GR8RegisterClass);
9006 return std::make_pair(0U, X86::GR16RegisterClass);
9007 if (VT == MVT::i32 || !Subtarget->is64Bit())
9008 return std::make_pair(0U, X86::GR32RegisterClass);
9009 return std::make_pair(0U, X86::GR64RegisterClass);
9010 case 'f': // FP Stack registers.
9011 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9012 // value to the correct fpstack register class.
9013 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9014 return std::make_pair(0U, X86::RFP32RegisterClass);
9015 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9016 return std::make_pair(0U, X86::RFP64RegisterClass);
9017 return std::make_pair(0U, X86::RFP80RegisterClass);
9018 case 'y': // MMX_REGS if MMX allowed.
9019 if (!Subtarget->hasMMX()) break;
9020 return std::make_pair(0U, X86::VR64RegisterClass);
9021 case 'Y': // SSE_REGS if SSE2 allowed
9022 if (!Subtarget->hasSSE2()) break;
9024 case 'x': // SSE_REGS if SSE1 allowed
9025 if (!Subtarget->hasSSE1()) break;
9027 switch (VT.getSimpleVT()) {
9029 // Scalar SSE types.
9032 return std::make_pair(0U, X86::FR32RegisterClass);
9035 return std::make_pair(0U, X86::FR64RegisterClass);
9043 return std::make_pair(0U, X86::VR128RegisterClass);
9049 // Use the default implementation in TargetLowering to convert the register
9050 // constraint into a member of a register class.
9051 std::pair<unsigned, const TargetRegisterClass*> Res;
9052 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9054 // Not found as a standard register?
9055 if (Res.second == 0) {
9056 // GCC calls "st(0)" just plain "st".
9057 if (StringsEqualNoCase("{st}", Constraint)) {
9058 Res.first = X86::ST0;
9059 Res.second = X86::RFP80RegisterClass;
9061 // 'A' means EAX + EDX.
9062 if (Constraint == "A") {
9063 Res.first = X86::EAX;
9064 Res.second = X86::GRADRegisterClass;
9069 // Otherwise, check to see if this is a register class of the wrong value
9070 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9071 // turn into {ax},{dx}.
9072 if (Res.second->hasType(VT))
9073 return Res; // Correct type already, nothing to do.
9075 // All of the single-register GCC register classes map their values onto
9076 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9077 // really want an 8-bit or 32-bit register, map to the appropriate register
9078 // class and return the appropriate register.
9079 if (Res.second == X86::GR16RegisterClass) {
9080 if (VT == MVT::i8) {
9081 unsigned DestReg = 0;
9082 switch (Res.first) {
9084 case X86::AX: DestReg = X86::AL; break;
9085 case X86::DX: DestReg = X86::DL; break;
9086 case X86::CX: DestReg = X86::CL; break;
9087 case X86::BX: DestReg = X86::BL; break;
9090 Res.first = DestReg;
9091 Res.second = X86::GR8RegisterClass;
9093 } else if (VT == MVT::i32) {
9094 unsigned DestReg = 0;
9095 switch (Res.first) {
9097 case X86::AX: DestReg = X86::EAX; break;
9098 case X86::DX: DestReg = X86::EDX; break;
9099 case X86::CX: DestReg = X86::ECX; break;
9100 case X86::BX: DestReg = X86::EBX; break;
9101 case X86::SI: DestReg = X86::ESI; break;
9102 case X86::DI: DestReg = X86::EDI; break;
9103 case X86::BP: DestReg = X86::EBP; break;
9104 case X86::SP: DestReg = X86::ESP; break;
9107 Res.first = DestReg;
9108 Res.second = X86::GR32RegisterClass;
9110 } else if (VT == MVT::i64) {
9111 unsigned DestReg = 0;
9112 switch (Res.first) {
9114 case X86::AX: DestReg = X86::RAX; break;
9115 case X86::DX: DestReg = X86::RDX; break;
9116 case X86::CX: DestReg = X86::RCX; break;
9117 case X86::BX: DestReg = X86::RBX; break;
9118 case X86::SI: DestReg = X86::RSI; break;
9119 case X86::DI: DestReg = X86::RDI; break;
9120 case X86::BP: DestReg = X86::RBP; break;
9121 case X86::SP: DestReg = X86::RSP; break;
9124 Res.first = DestReg;
9125 Res.second = X86::GR64RegisterClass;
9128 } else if (Res.second == X86::FR32RegisterClass ||
9129 Res.second == X86::FR64RegisterClass ||
9130 Res.second == X86::VR128RegisterClass) {
9131 // Handle references to XMM physical registers that got mapped into the
9132 // wrong class. This can happen with constraints like {xmm0} where the
9133 // target independent register mapper will just pick the first match it can
9134 // find, ignoring the required type.
9136 Res.second = X86::FR32RegisterClass;
9137 else if (VT == MVT::f64)
9138 Res.second = X86::FR64RegisterClass;
9139 else if (X86::VR128RegisterClass->hasType(VT))
9140 Res.second = X86::VR128RegisterClass;
9146 //===----------------------------------------------------------------------===//
9147 // X86 Widen vector type
9148 //===----------------------------------------------------------------------===//
9150 /// getWidenVectorType: given a vector type, returns the type to widen
9151 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9152 /// If there is no vector type that we want to widen to, returns MVT::Other
9153 /// When and where to widen is target dependent based on the cost of
9154 /// scalarizing vs using the wider vector type.
9156 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
9157 assert(VT.isVector());
9158 if (isTypeLegal(VT))
9161 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9162 // type based on element type. This would speed up our search (though
9163 // it may not be worth it since the size of the list is relatively
9165 MVT EltVT = VT.getVectorElementType();
9166 unsigned NElts = VT.getVectorNumElements();
9168 // On X86, it make sense to widen any vector wider than 1
9172 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9173 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9174 MVT SVT = (MVT::SimpleValueType)nVT;
9176 if (isTypeLegal(SVT) &&
9177 SVT.getVectorElementType() == EltVT &&
9178 SVT.getVectorNumElements() > NElts)