1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
814 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
815 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
817 // First set operation action for all vector types to either promote
818 // (for widening) or expand (for scalarization). Then we will selectively
819 // turn on ones that can be effectively codegen'd.
820 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
821 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
822 MVT VT = (MVT::SimpleValueType)i;
823 setOperationAction(ISD::ADD , VT, Expand);
824 setOperationAction(ISD::SUB , VT, Expand);
825 setOperationAction(ISD::FADD, VT, Expand);
826 setOperationAction(ISD::FNEG, VT, Expand);
827 setOperationAction(ISD::FSUB, VT, Expand);
828 setOperationAction(ISD::MUL , VT, Expand);
829 setOperationAction(ISD::FMUL, VT, Expand);
830 setOperationAction(ISD::SDIV, VT, Expand);
831 setOperationAction(ISD::UDIV, VT, Expand);
832 setOperationAction(ISD::FDIV, VT, Expand);
833 setOperationAction(ISD::SREM, VT, Expand);
834 setOperationAction(ISD::UREM, VT, Expand);
835 setOperationAction(ISD::LOAD, VT, Expand);
836 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
838 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
839 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
840 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
841 setOperationAction(ISD::FABS, VT, Expand);
842 setOperationAction(ISD::FSIN, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FCOS, VT, Expand);
845 setOperationAction(ISD::FSINCOS, VT, Expand);
846 setOperationAction(ISD::FREM, VT, Expand);
847 setOperationAction(ISD::FMA, VT, Expand);
848 setOperationAction(ISD::FPOWI, VT, Expand);
849 setOperationAction(ISD::FSQRT, VT, Expand);
850 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
851 setOperationAction(ISD::FFLOOR, VT, Expand);
852 setOperationAction(ISD::FCEIL, VT, Expand);
853 setOperationAction(ISD::FTRUNC, VT, Expand);
854 setOperationAction(ISD::FRINT, VT, Expand);
855 setOperationAction(ISD::FNEARBYINT, VT, Expand);
856 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHS, VT, Expand);
858 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
859 setOperationAction(ISD::MULHU, VT, Expand);
860 setOperationAction(ISD::SDIVREM, VT, Expand);
861 setOperationAction(ISD::UDIVREM, VT, Expand);
862 setOperationAction(ISD::FPOW, VT, Expand);
863 setOperationAction(ISD::CTPOP, VT, Expand);
864 setOperationAction(ISD::CTTZ, VT, Expand);
865 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::CTLZ, VT, Expand);
867 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
868 setOperationAction(ISD::SHL, VT, Expand);
869 setOperationAction(ISD::SRA, VT, Expand);
870 setOperationAction(ISD::SRL, VT, Expand);
871 setOperationAction(ISD::ROTL, VT, Expand);
872 setOperationAction(ISD::ROTR, VT, Expand);
873 setOperationAction(ISD::BSWAP, VT, Expand);
874 setOperationAction(ISD::SETCC, VT, Expand);
875 setOperationAction(ISD::FLOG, VT, Expand);
876 setOperationAction(ISD::FLOG2, VT, Expand);
877 setOperationAction(ISD::FLOG10, VT, Expand);
878 setOperationAction(ISD::FEXP, VT, Expand);
879 setOperationAction(ISD::FEXP2, VT, Expand);
880 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
881 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
882 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
883 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
885 setOperationAction(ISD::TRUNCATE, VT, Expand);
886 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
887 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
888 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
889 setOperationAction(ISD::VSELECT, VT, Expand);
890 setOperationAction(ISD::SELECT_CC, VT, Expand);
891 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
892 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
893 setTruncStoreAction(VT,
894 (MVT::SimpleValueType)InnerVT, Expand);
895 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
896 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
898 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
899 // we have to deal with them whether we ask for Expansion or not. Setting
900 // Expand causes its own optimisation problems though, so leave them legal.
901 if (VT.getVectorElementType() == MVT::i1)
902 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
905 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
906 // with -msoft-float, disable use of MMX as well.
907 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
908 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
909 // No operations on x86mmx supported, everything uses intrinsics.
912 // MMX-sized vectors (other than x86mmx) are expected to be expanded
913 // into smaller operations.
914 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
915 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
916 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
917 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
918 setOperationAction(ISD::AND, MVT::v8i8, Expand);
919 setOperationAction(ISD::AND, MVT::v4i16, Expand);
920 setOperationAction(ISD::AND, MVT::v2i32, Expand);
921 setOperationAction(ISD::AND, MVT::v1i64, Expand);
922 setOperationAction(ISD::OR, MVT::v8i8, Expand);
923 setOperationAction(ISD::OR, MVT::v4i16, Expand);
924 setOperationAction(ISD::OR, MVT::v2i32, Expand);
925 setOperationAction(ISD::OR, MVT::v1i64, Expand);
926 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
927 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
928 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
929 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
932 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
933 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
935 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
936 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
937 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
938 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
941 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
942 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
944 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
945 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
947 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
948 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
949 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
950 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
951 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
952 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
953 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
954 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
955 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
956 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
958 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
961 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
962 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
964 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
965 // registers cannot be used even for integer operations.
966 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
967 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
968 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
969 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
971 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
972 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
973 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
974 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
976 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
977 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
978 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
979 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
980 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
982 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
983 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
984 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
985 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
986 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
987 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
988 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
989 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
990 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
991 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
992 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
994 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
995 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
996 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
997 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
999 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
1000 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1006 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1007 MVT VT = (MVT::SimpleValueType)i;
1008 // Do not attempt to custom lower non-power-of-2 vectors
1009 if (!isPowerOf2_32(VT.getVectorNumElements()))
1011 // Do not attempt to custom lower non-128-bit vectors
1012 if (!VT.is128BitVector())
1014 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1015 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1019 // We support custom legalizing of sext and anyext loads for specific
1020 // memory vector types which we can load as a scalar (or sequence of
1021 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1022 // loads these must work with a single scalar load.
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1024 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1025 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1033 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1034 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1035 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1036 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1040 if (Subtarget->is64Bit()) {
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1045 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1046 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1047 MVT VT = (MVT::SimpleValueType)i;
1049 // Do not attempt to promote non-128-bit vectors
1050 if (!VT.is128BitVector())
1053 setOperationAction(ISD::AND, VT, Promote);
1054 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1055 setOperationAction(ISD::OR, VT, Promote);
1056 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1057 setOperationAction(ISD::XOR, VT, Promote);
1058 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1059 setOperationAction(ISD::LOAD, VT, Promote);
1060 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1061 setOperationAction(ISD::SELECT, VT, Promote);
1062 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1065 // Custom lower v2i64 and v2f64 selects.
1066 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1067 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1068 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1069 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1071 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1076 // As there is no 64-bit GPR available, we need build a special custom
1077 // sequence to convert from v2i32 to v2f32.
1078 if (!Subtarget->is64Bit())
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1081 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1082 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1084 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1086 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1087 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1088 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1091 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1092 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1103 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1114 // FIXME: Do we need to handle scalar-to-vector here?
1115 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1117 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1121 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1122 // There is no BLENDI for byte vectors. We don't need to custom lower
1123 // some vselects for now.
1124 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1126 // SSE41 brings specific instructions for doing vector sign extend even in
1127 // cases where we don't have SRA.
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1130 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1132 // i8 and i16 vectors are custom because the source register and source
1133 // source memory operand types are not the same width. f32 vectors are
1134 // custom since the immediate controlling the insert encodes additional
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1146 // FIXME: these should be Legal, but that's only for the case where
1147 // the index is constant. For now custom expand to deal with that.
1148 if (Subtarget->is64Bit()) {
1149 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1154 if (Subtarget->hasSSE2()) {
1155 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1156 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1158 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1159 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1161 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1162 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1164 // In the customized shift lowering, the legal cases in AVX2 will be
1166 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1167 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1169 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1170 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1172 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1175 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1176 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1181 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1183 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1185 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1187 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1200 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1211 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1213 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1214 // even though v8i16 is a legal type.
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1217 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1220 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1221 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1224 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1226 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1228 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1235 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1249 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1259 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1262 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1264 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1265 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1269 setOperationAction(ISD::FMA, MVT::f32, Legal);
1270 setOperationAction(ISD::FMA, MVT::f64, Legal);
1273 if (Subtarget->hasInt256()) {
1274 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1275 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1276 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1277 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1279 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1280 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1281 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1282 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1284 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1286 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1287 // Don't lower v32i8 because there is no 128-bit byte mul
1289 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1291 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1292 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1294 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1295 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1297 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1298 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1299 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1300 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1302 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1303 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1304 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1305 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1307 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1309 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1310 // Don't lower v32i8 because there is no 128-bit byte mul
1313 // In the customized shift lowering, the legal cases in AVX2 will be
1315 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1316 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1319 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1321 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1323 // Custom lower several nodes for 256-bit types.
1324 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1325 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1326 MVT VT = (MVT::SimpleValueType)i;
1328 // Extract subvector is special because the value type
1329 // (result) is 128-bit but the source is 256-bit wide.
1330 if (VT.is128BitVector())
1331 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1333 // Do not attempt to custom lower other non-256-bit vectors
1334 if (!VT.is256BitVector())
1337 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1338 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1339 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1341 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1342 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1343 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1346 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1347 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1348 MVT VT = (MVT::SimpleValueType)i;
1350 // Do not attempt to promote non-256-bit vectors
1351 if (!VT.is256BitVector())
1354 setOperationAction(ISD::AND, VT, Promote);
1355 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1356 setOperationAction(ISD::OR, VT, Promote);
1357 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1358 setOperationAction(ISD::XOR, VT, Promote);
1359 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1360 setOperationAction(ISD::LOAD, VT, Promote);
1361 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1362 setOperationAction(ISD::SELECT, VT, Promote);
1363 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1367 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1368 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1374 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1375 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1377 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1378 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1379 setOperationAction(ISD::XOR, MVT::i1, Legal);
1380 setOperationAction(ISD::OR, MVT::i1, Legal);
1381 setOperationAction(ISD::AND, MVT::i1, Legal);
1382 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1389 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1396 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1402 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1407 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1409 if (Subtarget->is64Bit()) {
1410 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1423 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1426 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1447 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1448 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1450 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1462 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1463 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1465 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1466 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1468 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1470 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1476 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1477 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1479 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1480 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1481 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1482 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1483 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1484 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1486 if (Subtarget->hasCDI()) {
1487 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1488 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1491 // Custom lower several nodes.
1492 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1493 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1494 MVT VT = (MVT::SimpleValueType)i;
1496 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1497 // Extract subvector is special because the value type
1498 // (result) is 256/128-bit but the source is 512-bit wide.
1499 if (VT.is128BitVector() || VT.is256BitVector())
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1502 if (VT.getVectorElementType() == MVT::i1)
1503 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1505 // Do not attempt to custom lower other non-512-bit vectors
1506 if (!VT.is512BitVector())
1509 if ( EltSize >= 32) {
1510 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1511 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1513 setOperationAction(ISD::VSELECT, VT, Legal);
1514 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1515 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1516 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1519 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1520 MVT VT = (MVT::SimpleValueType)i;
1522 // Do not attempt to promote non-256-bit vectors
1523 if (!VT.is512BitVector())
1526 setOperationAction(ISD::SELECT, VT, Promote);
1527 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1531 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1532 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1535 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1536 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1538 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1539 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1540 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1541 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1543 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1544 const MVT VT = (MVT::SimpleValueType)i;
1546 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1548 // Do not attempt to promote non-256-bit vectors
1549 if (!VT.is512BitVector())
1552 if ( EltSize < 32) {
1553 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1554 setOperationAction(ISD::VSELECT, VT, Legal);
1559 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1560 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1561 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1563 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1564 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1568 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1569 // of this type with custom code.
1570 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1571 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1572 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1576 // We want to custom lower some of our intrinsics.
1577 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1579 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1580 if (!Subtarget->is64Bit())
1581 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1583 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1584 // handle type legalization for these operations here.
1586 // FIXME: We really should do custom legalization for addition and
1587 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1588 // than generic legalization for 64-bit multiplication-with-overflow, though.
1589 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1590 // Add/Sub/Mul with overflow operations are custom lowered.
1592 setOperationAction(ISD::SADDO, VT, Custom);
1593 setOperationAction(ISD::UADDO, VT, Custom);
1594 setOperationAction(ISD::SSUBO, VT, Custom);
1595 setOperationAction(ISD::USUBO, VT, Custom);
1596 setOperationAction(ISD::SMULO, VT, Custom);
1597 setOperationAction(ISD::UMULO, VT, Custom);
1600 // There are no 8-bit 3-address imul/mul instructions
1601 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1602 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1604 if (!Subtarget->is64Bit()) {
1605 // These libcalls are not available in 32-bit.
1606 setLibcallName(RTLIB::SHL_I128, nullptr);
1607 setLibcallName(RTLIB::SRL_I128, nullptr);
1608 setLibcallName(RTLIB::SRA_I128, nullptr);
1611 // Combine sin / cos into one node or libcall if possible.
1612 if (Subtarget->hasSinCos()) {
1613 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1614 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1615 if (Subtarget->isTargetDarwin()) {
1616 // For MacOSX, we don't want to the normal expansion of a libcall to
1617 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1619 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1620 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1624 if (Subtarget->isTargetWin64()) {
1625 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1626 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1627 setOperationAction(ISD::SREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UREM, MVT::i128, Custom);
1629 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1630 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1633 // We have target-specific dag combine patterns for the following nodes:
1634 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1635 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1636 setTargetDAGCombine(ISD::VSELECT);
1637 setTargetDAGCombine(ISD::SELECT);
1638 setTargetDAGCombine(ISD::SHL);
1639 setTargetDAGCombine(ISD::SRA);
1640 setTargetDAGCombine(ISD::SRL);
1641 setTargetDAGCombine(ISD::OR);
1642 setTargetDAGCombine(ISD::AND);
1643 setTargetDAGCombine(ISD::ADD);
1644 setTargetDAGCombine(ISD::FADD);
1645 setTargetDAGCombine(ISD::FSUB);
1646 setTargetDAGCombine(ISD::FMA);
1647 setTargetDAGCombine(ISD::SUB);
1648 setTargetDAGCombine(ISD::LOAD);
1649 setTargetDAGCombine(ISD::STORE);
1650 setTargetDAGCombine(ISD::ZERO_EXTEND);
1651 setTargetDAGCombine(ISD::ANY_EXTEND);
1652 setTargetDAGCombine(ISD::SIGN_EXTEND);
1653 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1654 setTargetDAGCombine(ISD::TRUNCATE);
1655 setTargetDAGCombine(ISD::SINT_TO_FP);
1656 setTargetDAGCombine(ISD::SETCC);
1657 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1658 setTargetDAGCombine(ISD::BUILD_VECTOR);
1659 if (Subtarget->is64Bit())
1660 setTargetDAGCombine(ISD::MUL);
1661 setTargetDAGCombine(ISD::XOR);
1663 computeRegisterProperties();
1665 // On Darwin, -Os means optimize for size without hurting performance,
1666 // do not reduce the limit.
1667 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1668 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1669 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1670 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1672 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1673 setPrefLoopAlignment(4); // 2^4 bytes.
1675 // Predictable cmov don't hurt on atom because it's in-order.
1676 PredictableSelectIsExpensive = !Subtarget->isAtom();
1678 setPrefFunctionAlignment(4); // 2^4 bytes.
1680 verifyIntrinsicTables();
1683 // This has so far only been implemented for 64-bit MachO.
1684 bool X86TargetLowering::useLoadStackGuardNode() const {
1685 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1686 Subtarget->is64Bit();
1689 TargetLoweringBase::LegalizeTypeAction
1690 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1691 if (ExperimentalVectorWideningLegalization &&
1692 VT.getVectorNumElements() != 1 &&
1693 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1694 return TypeWidenVector;
1696 return TargetLoweringBase::getPreferredVectorAction(VT);
1699 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1701 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1703 const unsigned NumElts = VT.getVectorNumElements();
1704 const EVT EltVT = VT.getVectorElementType();
1705 if (VT.is512BitVector()) {
1706 if (Subtarget->hasAVX512())
1707 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1708 EltVT == MVT::f32 || EltVT == MVT::f64)
1710 case 8: return MVT::v8i1;
1711 case 16: return MVT::v16i1;
1713 if (Subtarget->hasBWI())
1714 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1716 case 32: return MVT::v32i1;
1717 case 64: return MVT::v64i1;
1721 if (VT.is256BitVector() || VT.is128BitVector()) {
1722 if (Subtarget->hasVLX())
1723 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1724 EltVT == MVT::f32 || EltVT == MVT::f64)
1726 case 2: return MVT::v2i1;
1727 case 4: return MVT::v4i1;
1728 case 8: return MVT::v8i1;
1730 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1731 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1733 case 8: return MVT::v8i1;
1734 case 16: return MVT::v16i1;
1735 case 32: return MVT::v32i1;
1739 return VT.changeVectorElementTypeToInteger();
1742 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1743 /// the desired ByVal argument alignment.
1744 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1747 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1748 if (VTy->getBitWidth() == 128)
1750 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(ATy->getElementType(), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1755 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1756 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1757 unsigned EltAlign = 0;
1758 getMaxByValAlign(STy->getElementType(i), EltAlign);
1759 if (EltAlign > MaxAlign)
1760 MaxAlign = EltAlign;
1767 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1768 /// function arguments in the caller parameter area. For X86, aggregates
1769 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1770 /// are at 4-byte boundaries.
1771 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1772 if (Subtarget->is64Bit()) {
1773 // Max of 8 and alignment of type.
1774 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1781 if (Subtarget->hasSSE1())
1782 getMaxByValAlign(Ty, Align);
1786 /// getOptimalMemOpType - Returns the target specific optimal type for load
1787 /// and store operations as a result of memset, memcpy, and memmove
1788 /// lowering. If DstAlign is zero that means it's safe to destination
1789 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1790 /// means there isn't a need to check it against alignment requirement,
1791 /// probably because the source does not need to be loaded. If 'IsMemset' is
1792 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1793 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1794 /// source is constant so it does not need to be loaded.
1795 /// It returns EVT::Other if the type should be determined using generic
1796 /// target-independent logic.
1798 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1799 unsigned DstAlign, unsigned SrcAlign,
1800 bool IsMemset, bool ZeroMemset,
1802 MachineFunction &MF) const {
1803 const Function *F = MF.getFunction();
1804 if ((!IsMemset || ZeroMemset) &&
1805 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1806 Attribute::NoImplicitFloat)) {
1808 (Subtarget->isUnalignedMemAccessFast() ||
1809 ((DstAlign == 0 || DstAlign >= 16) &&
1810 (SrcAlign == 0 || SrcAlign >= 16)))) {
1812 if (Subtarget->hasInt256())
1814 if (Subtarget->hasFp256())
1817 if (Subtarget->hasSSE2())
1819 if (Subtarget->hasSSE1())
1821 } else if (!MemcpyStrSrc && Size >= 8 &&
1822 !Subtarget->is64Bit() &&
1823 Subtarget->hasSSE2()) {
1824 // Do not use f64 to lower memcpy if source is string constant. It's
1825 // better to use i32 to avoid the loads.
1829 if (Subtarget->is64Bit() && Size >= 8)
1834 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1836 return X86ScalarSSEf32;
1837 else if (VT == MVT::f64)
1838 return X86ScalarSSEf64;
1843 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1848 *Fast = Subtarget->isUnalignedMemAccessFast();
1852 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1853 /// current function. The returned value is a member of the
1854 /// MachineJumpTableInfo::JTEntryKind enum.
1855 unsigned X86TargetLowering::getJumpTableEncoding() const {
1856 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1858 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1859 Subtarget->isPICStyleGOT())
1860 return MachineJumpTableInfo::EK_Custom32;
1862 // Otherwise, use the normal jump table encoding heuristics.
1863 return TargetLowering::getJumpTableEncoding();
1867 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1868 const MachineBasicBlock *MBB,
1869 unsigned uid,MCContext &Ctx) const{
1870 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1871 Subtarget->isPICStyleGOT());
1872 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1874 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1875 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1878 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1880 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1881 SelectionDAG &DAG) const {
1882 if (!Subtarget->is64Bit())
1883 // This doesn't have SDLoc associated with it, but is not really the
1884 // same as a Register.
1885 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1889 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1890 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1892 const MCExpr *X86TargetLowering::
1893 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1894 MCContext &Ctx) const {
1895 // X86-64 uses RIP relative addressing based on the jump table label.
1896 if (Subtarget->isPICStyleRIPRel())
1897 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1899 // Otherwise, the reference is relative to the PIC base.
1900 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1903 // FIXME: Why this routine is here? Move to RegInfo!
1904 std::pair<const TargetRegisterClass*, uint8_t>
1905 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1906 const TargetRegisterClass *RRC = nullptr;
1908 switch (VT.SimpleTy) {
1910 return TargetLowering::findRepresentativeClass(VT);
1911 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1912 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1915 RRC = &X86::VR64RegClass;
1917 case MVT::f32: case MVT::f64:
1918 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1919 case MVT::v4f32: case MVT::v2f64:
1920 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1922 RRC = &X86::VR128RegClass;
1925 return std::make_pair(RRC, Cost);
1928 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1929 unsigned &Offset) const {
1930 if (!Subtarget->isTargetLinux())
1933 if (Subtarget->is64Bit()) {
1934 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1936 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1948 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1949 unsigned DestAS) const {
1950 assert(SrcAS != DestAS && "Expected different address spaces!");
1952 return SrcAS < 256 && DestAS < 256;
1955 //===----------------------------------------------------------------------===//
1956 // Return Value Calling Convention Implementation
1957 //===----------------------------------------------------------------------===//
1959 #include "X86GenCallingConv.inc"
1962 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1963 MachineFunction &MF, bool isVarArg,
1964 const SmallVectorImpl<ISD::OutputArg> &Outs,
1965 LLVMContext &Context) const {
1966 SmallVector<CCValAssign, 16> RVLocs;
1967 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1968 return CCInfo.CheckReturn(Outs, RetCC_X86);
1971 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1972 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1977 X86TargetLowering::LowerReturn(SDValue Chain,
1978 CallingConv::ID CallConv, bool isVarArg,
1979 const SmallVectorImpl<ISD::OutputArg> &Outs,
1980 const SmallVectorImpl<SDValue> &OutVals,
1981 SDLoc dl, SelectionDAG &DAG) const {
1982 MachineFunction &MF = DAG.getMachineFunction();
1983 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1985 SmallVector<CCValAssign, 16> RVLocs;
1986 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1987 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1990 SmallVector<SDValue, 6> RetOps;
1991 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1992 // Operand #1 = Bytes To Pop
1993 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1996 // Copy the result values into the output registers.
1997 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1998 CCValAssign &VA = RVLocs[i];
1999 assert(VA.isRegLoc() && "Can only return in registers!");
2000 SDValue ValToCopy = OutVals[i];
2001 EVT ValVT = ValToCopy.getValueType();
2003 // Promote values to the appropriate types
2004 if (VA.getLocInfo() == CCValAssign::SExt)
2005 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::ZExt)
2007 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::AExt)
2009 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2010 else if (VA.getLocInfo() == CCValAssign::BCvt)
2011 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2013 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2014 "Unexpected FP-extend for return value.");
2016 // If this is x86-64, and we disabled SSE, we can't return FP values,
2017 // or SSE or MMX vectors.
2018 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2019 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2020 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2021 report_fatal_error("SSE register return with SSE disabled");
2023 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2024 // llvm-gcc has never done it right and no one has noticed, so this
2025 // should be OK for now.
2026 if (ValVT == MVT::f64 &&
2027 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2028 report_fatal_error("SSE2 register return with SSE2 disabled");
2030 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2031 // the RET instruction and handled by the FP Stackifier.
2032 if (VA.getLocReg() == X86::FP0 ||
2033 VA.getLocReg() == X86::FP1) {
2034 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2035 // change the value to the FP stack register class.
2036 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2037 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2038 RetOps.push_back(ValToCopy);
2039 // Don't emit a copytoreg.
2043 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2044 // which is returned in RAX / RDX.
2045 if (Subtarget->is64Bit()) {
2046 if (ValVT == MVT::x86mmx) {
2047 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2049 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2051 // If we don't have SSE2 available, convert to v4f32 so the generated
2052 // register is legal.
2053 if (!Subtarget->hasSSE2())
2054 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2059 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2060 Flag = Chain.getValue(1);
2061 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2064 // The x86-64 ABIs require that for returning structs by value we copy
2065 // the sret argument into %rax/%eax (depending on ABI) for the return.
2066 // Win32 requires us to put the sret argument to %eax as well.
2067 // We saved the argument into a virtual register in the entry block,
2068 // so now we copy the value out and into %rax/%eax.
2069 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2070 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2071 MachineFunction &MF = DAG.getMachineFunction();
2072 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2073 unsigned Reg = FuncInfo->getSRetReturnReg();
2075 "SRetReturnReg should have been set in LowerFormalArguments().");
2076 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2079 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2080 X86::RAX : X86::EAX;
2081 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2082 Flag = Chain.getValue(1);
2084 // RAX/EAX now acts like a return value.
2085 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2088 RetOps[0] = Chain; // Update chain.
2090 // Add the flag if we have it.
2092 RetOps.push_back(Flag);
2094 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2097 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2098 if (N->getNumValues() != 1)
2100 if (!N->hasNUsesOfValue(1, 0))
2103 SDValue TCChain = Chain;
2104 SDNode *Copy = *N->use_begin();
2105 if (Copy->getOpcode() == ISD::CopyToReg) {
2106 // If the copy has a glue operand, we conservatively assume it isn't safe to
2107 // perform a tail call.
2108 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2110 TCChain = Copy->getOperand(0);
2111 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2114 bool HasRet = false;
2115 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2117 if (UI->getOpcode() != X86ISD::RET_FLAG)
2119 // If we are returning more than one value, we can definitely
2120 // not make a tail call see PR19530
2121 if (UI->getNumOperands() > 4)
2123 if (UI->getNumOperands() == 4 &&
2124 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2137 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2138 ISD::NodeType ExtendKind) const {
2140 // TODO: Is this also valid on 32-bit?
2141 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2142 ReturnMVT = MVT::i8;
2144 ReturnMVT = MVT::i32;
2146 EVT MinVT = getRegisterType(Context, ReturnMVT);
2147 return VT.bitsLT(MinVT) ? MinVT : VT;
2150 /// LowerCallResult - Lower the result values of a call into the
2151 /// appropriate copies out of appropriate physical registers.
2154 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2155 CallingConv::ID CallConv, bool isVarArg,
2156 const SmallVectorImpl<ISD::InputArg> &Ins,
2157 SDLoc dl, SelectionDAG &DAG,
2158 SmallVectorImpl<SDValue> &InVals) const {
2160 // Assign locations to each value returned by this call.
2161 SmallVector<CCValAssign, 16> RVLocs;
2162 bool Is64Bit = Subtarget->is64Bit();
2163 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2165 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2167 // Copy all of the result registers out of their specified physreg.
2168 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2169 CCValAssign &VA = RVLocs[i];
2170 EVT CopyVT = VA.getValVT();
2172 // If this is x86-64, and we disabled SSE, we can't return FP values
2173 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2174 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2175 report_fatal_error("SSE register return with SSE disabled");
2178 // If we prefer to use the value in xmm registers, copy it out as f80 and
2179 // use a truncate to move it from fp stack reg to xmm reg.
2180 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2181 isScalarFPTypeInSSEReg(VA.getValVT()))
2184 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2185 CopyVT, InFlag).getValue(1);
2186 SDValue Val = Chain.getValue(0);
2188 if (CopyVT != VA.getValVT())
2189 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2190 // This truncation won't change the value.
2191 DAG.getIntPtrConstant(1));
2193 InFlag = Chain.getValue(2);
2194 InVals.push_back(Val);
2200 //===----------------------------------------------------------------------===//
2201 // C & StdCall & Fast Calling Convention implementation
2202 //===----------------------------------------------------------------------===//
2203 // StdCall calling convention seems to be standard for many Windows' API
2204 // routines and around. It differs from C calling convention just a little:
2205 // callee should clean up the stack, not caller. Symbols should be also
2206 // decorated in some fancy way :) It doesn't support any vector arguments.
2207 // For info on fast calling convention see Fast Calling Convention (tail call)
2208 // implementation LowerX86_32FastCCCallTo.
2210 /// CallIsStructReturn - Determines whether a call uses struct return
2212 enum StructReturnType {
2217 static StructReturnType
2218 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2220 return NotStructReturn;
2222 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2223 if (!Flags.isSRet())
2224 return NotStructReturn;
2225 if (Flags.isInReg())
2226 return RegStructReturn;
2227 return StackStructReturn;
2230 /// ArgsAreStructReturn - Determines whether a function uses struct
2231 /// return semantics.
2232 static StructReturnType
2233 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2235 return NotStructReturn;
2237 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2238 if (!Flags.isSRet())
2239 return NotStructReturn;
2240 if (Flags.isInReg())
2241 return RegStructReturn;
2242 return StackStructReturn;
2245 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2246 /// by "Src" to address "Dst" with size and alignment information specified by
2247 /// the specific parameter attribute. The copy will be passed as a byval
2248 /// function parameter.
2250 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2251 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2253 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2255 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2256 /*isVolatile*/false, /*AlwaysInline=*/true,
2257 MachinePointerInfo(), MachinePointerInfo());
2260 /// IsTailCallConvention - Return true if the calling convention is one that
2261 /// supports tail call optimization.
2262 static bool IsTailCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2264 CC == CallingConv::HiPE);
2267 /// \brief Return true if the calling convention is a C calling convention.
2268 static bool IsCCallConvention(CallingConv::ID CC) {
2269 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2270 CC == CallingConv::X86_64_SysV);
2273 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2274 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2278 CallingConv::ID CalleeCC = CS.getCallingConv();
2279 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2285 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2286 /// a tailcall target by changing its ABI.
2287 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2288 bool GuaranteedTailCallOpt) {
2289 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2293 X86TargetLowering::LowerMemArgument(SDValue Chain,
2294 CallingConv::ID CallConv,
2295 const SmallVectorImpl<ISD::InputArg> &Ins,
2296 SDLoc dl, SelectionDAG &DAG,
2297 const CCValAssign &VA,
2298 MachineFrameInfo *MFI,
2300 // Create the nodes corresponding to a load from this parameter slot.
2301 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2302 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2303 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2304 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2307 // If value is passed by pointer we have address passed instead of the value
2309 if (VA.getLocInfo() == CCValAssign::Indirect)
2310 ValVT = VA.getLocVT();
2312 ValVT = VA.getValVT();
2314 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2315 // changed with more analysis.
2316 // In case of tail call optimization mark all arguments mutable. Since they
2317 // could be overwritten by lowering of arguments in case of a tail call.
2318 if (Flags.isByVal()) {
2319 unsigned Bytes = Flags.getByValSize();
2320 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2321 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2322 return DAG.getFrameIndex(FI, getPointerTy());
2324 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2325 VA.getLocMemOffset(), isImmutable);
2326 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2327 return DAG.getLoad(ValVT, dl, Chain, FIN,
2328 MachinePointerInfo::getFixedStack(FI),
2329 false, false, false, 0);
2333 // FIXME: Get this from tablegen.
2334 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2335 const X86Subtarget *Subtarget) {
2336 assert(Subtarget->is64Bit());
2338 if (Subtarget->isCallingConvWin64(CallConv)) {
2339 static const MCPhysReg GPR64ArgRegsWin64[] = {
2340 X86::RCX, X86::RDX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2345 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2346 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2348 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2351 // FIXME: Get this from tablegen.
2352 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2353 CallingConv::ID CallConv,
2354 const X86Subtarget *Subtarget) {
2355 assert(Subtarget->is64Bit());
2356 if (Subtarget->isCallingConvWin64(CallConv)) {
2357 // The XMM registers which might contain var arg parameters are shadowed
2358 // in their paired GPR. So we only need to save the GPR to their home
2360 // TODO: __vectorcall will change this.
2364 const Function *Fn = MF.getFunction();
2365 bool NoImplicitFloatOps = Fn->getAttributes().
2366 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2367 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2368 "SSE register cannot be used when SSE is disabled!");
2369 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2370 !Subtarget->hasSSE1())
2371 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2375 static const MCPhysReg XMMArgRegs64Bit[] = {
2376 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2377 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2379 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2383 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2384 CallingConv::ID CallConv,
2386 const SmallVectorImpl<ISD::InputArg> &Ins,
2389 SmallVectorImpl<SDValue> &InVals)
2391 MachineFunction &MF = DAG.getMachineFunction();
2392 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2394 const Function* Fn = MF.getFunction();
2395 if (Fn->hasExternalLinkage() &&
2396 Subtarget->isTargetCygMing() &&
2397 Fn->getName() == "main")
2398 FuncInfo->setForceFramePointer(true);
2400 MachineFrameInfo *MFI = MF.getFrameInfo();
2401 bool Is64Bit = Subtarget->is64Bit();
2402 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2404 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2405 "Var args not supported with calling convention fastcc, ghc or hipe");
2407 // Assign locations to all of the incoming arguments.
2408 SmallVector<CCValAssign, 16> ArgLocs;
2409 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2411 // Allocate shadow area for Win64
2413 CCInfo.AllocateStack(32, 8);
2415 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2417 unsigned LastVal = ~0U;
2419 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2420 CCValAssign &VA = ArgLocs[i];
2421 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2423 assert(VA.getValNo() != LastVal &&
2424 "Don't support value assigned to multiple locs yet");
2426 LastVal = VA.getValNo();
2428 if (VA.isRegLoc()) {
2429 EVT RegVT = VA.getLocVT();
2430 const TargetRegisterClass *RC;
2431 if (RegVT == MVT::i32)
2432 RC = &X86::GR32RegClass;
2433 else if (Is64Bit && RegVT == MVT::i64)
2434 RC = &X86::GR64RegClass;
2435 else if (RegVT == MVT::f32)
2436 RC = &X86::FR32RegClass;
2437 else if (RegVT == MVT::f64)
2438 RC = &X86::FR64RegClass;
2439 else if (RegVT.is512BitVector())
2440 RC = &X86::VR512RegClass;
2441 else if (RegVT.is256BitVector())
2442 RC = &X86::VR256RegClass;
2443 else if (RegVT.is128BitVector())
2444 RC = &X86::VR128RegClass;
2445 else if (RegVT == MVT::x86mmx)
2446 RC = &X86::VR64RegClass;
2447 else if (RegVT == MVT::i1)
2448 RC = &X86::VK1RegClass;
2449 else if (RegVT == MVT::v8i1)
2450 RC = &X86::VK8RegClass;
2451 else if (RegVT == MVT::v16i1)
2452 RC = &X86::VK16RegClass;
2453 else if (RegVT == MVT::v32i1)
2454 RC = &X86::VK32RegClass;
2455 else if (RegVT == MVT::v64i1)
2456 RC = &X86::VK64RegClass;
2458 llvm_unreachable("Unknown argument type!");
2460 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2461 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2463 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2464 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2466 if (VA.getLocInfo() == CCValAssign::SExt)
2467 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::ZExt)
2470 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2471 DAG.getValueType(VA.getValVT()));
2472 else if (VA.getLocInfo() == CCValAssign::BCvt)
2473 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2475 if (VA.isExtInLoc()) {
2476 // Handle MMX values passed in XMM regs.
2477 if (RegVT.isVector())
2478 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2480 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2483 assert(VA.isMemLoc());
2484 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2487 // If value is passed via pointer - do a load.
2488 if (VA.getLocInfo() == CCValAssign::Indirect)
2489 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2490 MachinePointerInfo(), false, false, false, 0);
2492 InVals.push_back(ArgValue);
2495 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2496 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2497 // The x86-64 ABIs require that for returning structs by value we copy
2498 // the sret argument into %rax/%eax (depending on ABI) for the return.
2499 // Win32 requires us to put the sret argument to %eax as well.
2500 // Save the argument into a virtual register so that we can access it
2501 // from the return points.
2502 if (Ins[i].Flags.isSRet()) {
2503 unsigned Reg = FuncInfo->getSRetReturnReg();
2505 MVT PtrTy = getPointerTy();
2506 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2507 FuncInfo->setSRetReturnReg(Reg);
2509 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2510 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2516 unsigned StackSize = CCInfo.getNextStackOffset();
2517 // Align stack specially for tail calls.
2518 if (FuncIsMadeTailCallSafe(CallConv,
2519 MF.getTarget().Options.GuaranteedTailCallOpt))
2520 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2522 // If the function takes variable number of arguments, make a frame index for
2523 // the start of the first vararg value... for expansion of llvm.va_start. We
2524 // can skip this if there are no va_start calls.
2525 if (MFI->hasVAStart() &&
2526 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2527 CallConv != CallingConv::X86_ThisCall))) {
2528 FuncInfo->setVarArgsFrameIndex(
2529 MFI->CreateFixedObject(1, StackSize, true));
2532 // 64-bit calling conventions support varargs and register parameters, so we
2533 // have to do extra work to spill them in the prologue or forward them to
2535 if (Is64Bit && isVarArg &&
2536 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2537 // Find the first unallocated argument registers.
2538 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2539 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2540 unsigned NumIntRegs =
2541 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2542 unsigned NumXMMRegs =
2543 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2544 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2545 "SSE register cannot be used when SSE is disabled!");
2547 // Gather all the live in physical registers.
2548 SmallVector<SDValue, 6> LiveGPRs;
2549 SmallVector<SDValue, 8> LiveXMMRegs;
2551 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2552 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2554 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2556 if (!ArgXMMs.empty()) {
2557 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2558 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2559 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2560 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2561 LiveXMMRegs.push_back(
2562 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2566 // Store them to the va_list returned by va_start.
2567 if (MFI->hasVAStart()) {
2569 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2570 // Get to the caller-allocated home save location. Add 8 to account
2571 // for the return address.
2572 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2573 FuncInfo->setRegSaveFrameIndex(
2574 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2575 // Fixup to set vararg frame on shadow area (4 x i64).
2577 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2579 // For X86-64, if there are vararg parameters that are passed via
2580 // registers, then we must store them to their spots on the stack so
2581 // they may be loaded by deferencing the result of va_next.
2582 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2583 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2584 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2585 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2588 // Store the integer parameter registers.
2589 SmallVector<SDValue, 8> MemOps;
2590 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2592 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2593 for (SDValue Val : LiveGPRs) {
2594 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2595 DAG.getIntPtrConstant(Offset));
2597 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2598 MachinePointerInfo::getFixedStack(
2599 FuncInfo->getRegSaveFrameIndex(), Offset),
2601 MemOps.push_back(Store);
2605 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2606 // Now store the XMM (fp + vector) parameter registers.
2607 SmallVector<SDValue, 12> SaveXMMOps;
2608 SaveXMMOps.push_back(Chain);
2609 SaveXMMOps.push_back(ALVal);
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getRegSaveFrameIndex()));
2612 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2613 FuncInfo->getVarArgsFPOffset()));
2614 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2616 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2617 MVT::Other, SaveXMMOps));
2620 if (!MemOps.empty())
2621 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2623 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2624 // to the liveout set on a musttail call.
2625 assert(MFI->hasMustTailInVarArgFunc());
2626 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2627 typedef X86MachineFunctionInfo::Forward Forward;
2629 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2631 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2632 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2633 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2636 if (!ArgXMMs.empty()) {
2638 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2640 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2642 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2644 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2645 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2647 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2653 // Some CCs need callee pop.
2654 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2655 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2656 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2658 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2659 // If this is an sret function, the return should pop the hidden pointer.
2660 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2661 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2662 argsAreStructReturn(Ins) == StackStructReturn)
2663 FuncInfo->setBytesToPopOnReturn(4);
2667 // RegSaveFrameIndex is X86-64 only.
2668 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2669 if (CallConv == CallingConv::X86_FastCall ||
2670 CallConv == CallingConv::X86_ThisCall)
2671 // fastcc functions can't have varargs.
2672 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2675 FuncInfo->setArgumentStackSize(StackSize);
2681 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2682 SDValue StackPtr, SDValue Arg,
2683 SDLoc dl, SelectionDAG &DAG,
2684 const CCValAssign &VA,
2685 ISD::ArgFlagsTy Flags) const {
2686 unsigned LocMemOffset = VA.getLocMemOffset();
2687 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2688 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2689 if (Flags.isByVal())
2690 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2692 return DAG.getStore(Chain, dl, Arg, PtrOff,
2693 MachinePointerInfo::getStack(LocMemOffset),
2697 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2698 /// optimization is performed and it is required.
2700 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2701 SDValue &OutRetAddr, SDValue Chain,
2702 bool IsTailCall, bool Is64Bit,
2703 int FPDiff, SDLoc dl) const {
2704 // Adjust the Return address stack slot.
2705 EVT VT = getPointerTy();
2706 OutRetAddr = getReturnAddressFrameIndex(DAG);
2708 // Load the "old" Return address.
2709 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2710 false, false, false, 0);
2711 return SDValue(OutRetAddr.getNode(), 1);
2714 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2715 /// optimization is performed and it is required (FPDiff!=0).
2716 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2717 SDValue Chain, SDValue RetAddrFrIdx,
2718 EVT PtrVT, unsigned SlotSize,
2719 int FPDiff, SDLoc dl) {
2720 // Store the return address to the appropriate stack slot.
2721 if (!FPDiff) return Chain;
2722 // Calculate the new stack slot for the return address.
2723 int NewReturnAddrFI =
2724 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2726 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2727 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2728 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2734 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2735 SmallVectorImpl<SDValue> &InVals) const {
2736 SelectionDAG &DAG = CLI.DAG;
2738 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2739 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2740 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2741 SDValue Chain = CLI.Chain;
2742 SDValue Callee = CLI.Callee;
2743 CallingConv::ID CallConv = CLI.CallConv;
2744 bool &isTailCall = CLI.IsTailCall;
2745 bool isVarArg = CLI.IsVarArg;
2747 MachineFunction &MF = DAG.getMachineFunction();
2748 bool Is64Bit = Subtarget->is64Bit();
2749 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2750 StructReturnType SR = callIsStructReturn(Outs);
2751 bool IsSibcall = false;
2752 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2754 if (MF.getTarget().Options.DisableTailCalls)
2757 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2759 // Force this to be a tail call. The verifier rules are enough to ensure
2760 // that we can lower this successfully without moving the return address
2763 } else if (isTailCall) {
2764 // Check if it's really possible to do a tail call.
2765 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2766 isVarArg, SR != NotStructReturn,
2767 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2768 Outs, OutVals, Ins, DAG);
2770 // Sibcalls are automatically detected tailcalls which do not require
2772 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2779 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2780 "Var args not supported with calling convention fastcc, ghc or hipe");
2782 // Analyze operands of the call, assigning locations to each operand.
2783 SmallVector<CCValAssign, 16> ArgLocs;
2784 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2786 // Allocate shadow area for Win64
2788 CCInfo.AllocateStack(32, 8);
2790 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2792 // Get a count of how many bytes are to be pushed on the stack.
2793 unsigned NumBytes = CCInfo.getNextStackOffset();
2795 // This is a sibcall. The memory operands are available in caller's
2796 // own caller's stack.
2798 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2799 IsTailCallConvention(CallConv))
2800 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2803 if (isTailCall && !IsSibcall && !IsMustTail) {
2804 // Lower arguments at fp - stackoffset + fpdiff.
2805 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2807 FPDiff = NumBytesCallerPushed - NumBytes;
2809 // Set the delta of movement of the returnaddr stackslot.
2810 // But only set if delta is greater than previous delta.
2811 if (FPDiff < X86Info->getTCReturnAddrDelta())
2812 X86Info->setTCReturnAddrDelta(FPDiff);
2815 unsigned NumBytesToPush = NumBytes;
2816 unsigned NumBytesToPop = NumBytes;
2818 // If we have an inalloca argument, all stack space has already been allocated
2819 // for us and be right at the top of the stack. We don't support multiple
2820 // arguments passed in memory when using inalloca.
2821 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2823 if (!ArgLocs.back().isMemLoc())
2824 report_fatal_error("cannot use inalloca attribute on a register "
2826 if (ArgLocs.back().getLocMemOffset() != 0)
2827 report_fatal_error("any parameter with the inalloca attribute must be "
2828 "the only memory argument");
2832 Chain = DAG.getCALLSEQ_START(
2833 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2835 SDValue RetAddrFrIdx;
2836 // Load return address for tail calls.
2837 if (isTailCall && FPDiff)
2838 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2839 Is64Bit, FPDiff, dl);
2841 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2842 SmallVector<SDValue, 8> MemOpChains;
2845 // Walk the register/memloc assignments, inserting copies/loads. In the case
2846 // of tail call optimization arguments are handle later.
2847 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2848 DAG.getSubtarget().getRegisterInfo());
2849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2850 // Skip inalloca arguments, they have already been written.
2851 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2852 if (Flags.isInAlloca())
2855 CCValAssign &VA = ArgLocs[i];
2856 EVT RegVT = VA.getLocVT();
2857 SDValue Arg = OutVals[i];
2858 bool isByVal = Flags.isByVal();
2860 // Promote the value if needed.
2861 switch (VA.getLocInfo()) {
2862 default: llvm_unreachable("Unknown loc info!");
2863 case CCValAssign::Full: break;
2864 case CCValAssign::SExt:
2865 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::ZExt:
2868 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2870 case CCValAssign::AExt:
2871 if (RegVT.is128BitVector()) {
2872 // Special case: passing MMX values in XMM registers.
2873 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2874 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2875 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2877 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2879 case CCValAssign::BCvt:
2880 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2882 case CCValAssign::Indirect: {
2883 // Store the argument.
2884 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2885 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2886 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2887 MachinePointerInfo::getFixedStack(FI),
2894 if (VA.isRegLoc()) {
2895 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2896 if (isVarArg && IsWin64) {
2897 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2898 // shadow reg if callee is a varargs function.
2899 unsigned ShadowReg = 0;
2900 switch (VA.getLocReg()) {
2901 case X86::XMM0: ShadowReg = X86::RCX; break;
2902 case X86::XMM1: ShadowReg = X86::RDX; break;
2903 case X86::XMM2: ShadowReg = X86::R8; break;
2904 case X86::XMM3: ShadowReg = X86::R9; break;
2907 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2909 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2910 assert(VA.isMemLoc());
2911 if (!StackPtr.getNode())
2912 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2914 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2915 dl, DAG, VA, Flags));
2919 if (!MemOpChains.empty())
2920 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2922 if (Subtarget->isPICStyleGOT()) {
2923 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2926 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2927 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2929 // If we are tail calling and generating PIC/GOT style code load the
2930 // address of the callee into ECX. The value in ecx is used as target of
2931 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2932 // for tail calls on PIC/GOT architectures. Normally we would just put the
2933 // address of GOT into ebx and then call target@PLT. But for tail calls
2934 // ebx would be restored (since ebx is callee saved) before jumping to the
2937 // Note: The actual moving to ECX is done further down.
2938 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2939 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2940 !G->getGlobal()->hasProtectedVisibility())
2941 Callee = LowerGlobalAddress(Callee, DAG);
2942 else if (isa<ExternalSymbolSDNode>(Callee))
2943 Callee = LowerExternalSymbol(Callee, DAG);
2947 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2948 // From AMD64 ABI document:
2949 // For calls that may call functions that use varargs or stdargs
2950 // (prototype-less calls or calls to functions containing ellipsis (...) in
2951 // the declaration) %al is used as hidden argument to specify the number
2952 // of SSE registers used. The contents of %al do not need to match exactly
2953 // the number of registers, but must be an ubound on the number of SSE
2954 // registers used and is in the range 0 - 8 inclusive.
2956 // Count the number of XMM registers allocated.
2957 static const MCPhysReg XMMArgRegs[] = {
2958 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2959 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2961 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2962 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2963 && "SSE registers cannot be used when SSE is disabled");
2965 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2966 DAG.getConstant(NumXMMRegs, MVT::i8)));
2969 if (Is64Bit && isVarArg && IsMustTail) {
2970 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2971 for (const auto &F : Forwards) {
2972 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2973 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2977 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2978 // don't need this because the eligibility check rejects calls that require
2979 // shuffling arguments passed in memory.
2980 if (!IsSibcall && isTailCall) {
2981 // Force all the incoming stack arguments to be loaded from the stack
2982 // before any new outgoing arguments are stored to the stack, because the
2983 // outgoing stack slots may alias the incoming argument stack slots, and
2984 // the alias isn't otherwise explicit. This is slightly more conservative
2985 // than necessary, because it means that each store effectively depends
2986 // on every argument instead of just those arguments it would clobber.
2987 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2989 SmallVector<SDValue, 8> MemOpChains2;
2992 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2993 CCValAssign &VA = ArgLocs[i];
2996 assert(VA.isMemLoc());
2997 SDValue Arg = OutVals[i];
2998 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2999 // Skip inalloca arguments. They don't require any work.
3000 if (Flags.isInAlloca())
3002 // Create frame index.
3003 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3004 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3005 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3006 FIN = DAG.getFrameIndex(FI, getPointerTy());
3008 if (Flags.isByVal()) {
3009 // Copy relative to framepointer.
3010 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3011 if (!StackPtr.getNode())
3012 StackPtr = DAG.getCopyFromReg(Chain, dl,
3013 RegInfo->getStackRegister(),
3015 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3017 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3021 // Store relative to framepointer.
3022 MemOpChains2.push_back(
3023 DAG.getStore(ArgChain, dl, Arg, FIN,
3024 MachinePointerInfo::getFixedStack(FI),
3029 if (!MemOpChains2.empty())
3030 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3032 // Store the return address to the appropriate stack slot.
3033 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3034 getPointerTy(), RegInfo->getSlotSize(),
3038 // Build a sequence of copy-to-reg nodes chained together with token chain
3039 // and flag operands which copy the outgoing args into registers.
3041 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3042 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3043 RegsToPass[i].second, InFlag);
3044 InFlag = Chain.getValue(1);
3047 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3048 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3049 // In the 64-bit large code model, we have to make all calls
3050 // through a register, since the call instruction's 32-bit
3051 // pc-relative offset may not be large enough to hold the whole
3053 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3054 // If the callee is a GlobalAddress node (quite common, every direct call
3055 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3058 // We should use extra load for direct calls to dllimported functions in
3060 const GlobalValue *GV = G->getGlobal();
3061 if (!GV->hasDLLImportStorageClass()) {
3062 unsigned char OpFlags = 0;
3063 bool ExtraLoad = false;
3064 unsigned WrapperKind = ISD::DELETED_NODE;
3066 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3067 // external symbols most go through the PLT in PIC mode. If the symbol
3068 // has hidden or protected visibility, or if it is static or local, then
3069 // we don't need to use the PLT - we can directly call it.
3070 if (Subtarget->isTargetELF() &&
3071 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3072 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3073 OpFlags = X86II::MO_PLT;
3074 } else if (Subtarget->isPICStyleStubAny() &&
3075 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3076 (!Subtarget->getTargetTriple().isMacOSX() ||
3077 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3078 // PC-relative references to external symbols should go through $stub,
3079 // unless we're building with the leopard linker or later, which
3080 // automatically synthesizes these stubs.
3081 OpFlags = X86II::MO_DARWIN_STUB;
3082 } else if (Subtarget->isPICStyleRIPRel() &&
3083 isa<Function>(GV) &&
3084 cast<Function>(GV)->getAttributes().
3085 hasAttribute(AttributeSet::FunctionIndex,
3086 Attribute::NonLazyBind)) {
3087 // If the function is marked as non-lazy, generate an indirect call
3088 // which loads from the GOT directly. This avoids runtime overhead
3089 // at the cost of eager binding (and one extra byte of encoding).
3090 OpFlags = X86II::MO_GOTPCREL;
3091 WrapperKind = X86ISD::WrapperRIP;
3095 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3096 G->getOffset(), OpFlags);
3098 // Add a wrapper if needed.
3099 if (WrapperKind != ISD::DELETED_NODE)
3100 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3101 // Add extra indirection if needed.
3103 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3104 MachinePointerInfo::getGOT(),
3105 false, false, false, 0);
3107 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3108 unsigned char OpFlags = 0;
3110 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3111 // external symbols should go through the PLT.
3112 if (Subtarget->isTargetELF() &&
3113 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3114 OpFlags = X86II::MO_PLT;
3115 } else if (Subtarget->isPICStyleStubAny() &&
3116 (!Subtarget->getTargetTriple().isMacOSX() ||
3117 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3118 // PC-relative references to external symbols should go through $stub,
3119 // unless we're building with the leopard linker or later, which
3120 // automatically synthesizes these stubs.
3121 OpFlags = X86II::MO_DARWIN_STUB;
3124 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3126 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3127 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3128 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3131 // Returns a chain & a flag for retval copy to use.
3132 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3133 SmallVector<SDValue, 8> Ops;
3135 if (!IsSibcall && isTailCall) {
3136 Chain = DAG.getCALLSEQ_END(Chain,
3137 DAG.getIntPtrConstant(NumBytesToPop, true),
3138 DAG.getIntPtrConstant(0, true), InFlag, dl);
3139 InFlag = Chain.getValue(1);
3142 Ops.push_back(Chain);
3143 Ops.push_back(Callee);
3146 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3148 // Add argument registers to the end of the list so that they are known live
3150 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3151 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3152 RegsToPass[i].second.getValueType()));
3154 // Add a register mask operand representing the call-preserved registers.
3155 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3156 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3157 assert(Mask && "Missing call preserved mask for calling convention");
3158 Ops.push_back(DAG.getRegisterMask(Mask));
3160 if (InFlag.getNode())
3161 Ops.push_back(InFlag);
3165 //// If this is the first return lowered for this function, add the regs
3166 //// to the liveout set for the function.
3167 // This isn't right, although it's probably harmless on x86; liveouts
3168 // should be computed from returns not tail calls. Consider a void
3169 // function making a tail call to a function returning int.
3170 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3173 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3174 InFlag = Chain.getValue(1);
3176 // Create the CALLSEQ_END node.
3177 unsigned NumBytesForCalleeToPop;
3178 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3179 DAG.getTarget().Options.GuaranteedTailCallOpt))
3180 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3181 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3182 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3183 SR == StackStructReturn)
3184 // If this is a call to a struct-return function, the callee
3185 // pops the hidden struct pointer, so we have to push it back.
3186 // This is common for Darwin/X86, Linux & Mingw32 targets.
3187 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3188 NumBytesForCalleeToPop = 4;
3190 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3192 // Returns a flag for retval copy to use.
3194 Chain = DAG.getCALLSEQ_END(Chain,
3195 DAG.getIntPtrConstant(NumBytesToPop, true),
3196 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3199 InFlag = Chain.getValue(1);
3202 // Handle result values, copying them out of physregs into vregs that we
3204 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3205 Ins, dl, DAG, InVals);
3208 //===----------------------------------------------------------------------===//
3209 // Fast Calling Convention (tail call) implementation
3210 //===----------------------------------------------------------------------===//
3212 // Like std call, callee cleans arguments, convention except that ECX is
3213 // reserved for storing the tail called function address. Only 2 registers are
3214 // free for argument passing (inreg). Tail call optimization is performed
3216 // * tailcallopt is enabled
3217 // * caller/callee are fastcc
3218 // On X86_64 architecture with GOT-style position independent code only local
3219 // (within module) calls are supported at the moment.
3220 // To keep the stack aligned according to platform abi the function
3221 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3222 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3223 // If a tail called function callee has more arguments than the caller the
3224 // caller needs to make sure that there is room to move the RETADDR to. This is
3225 // achieved by reserving an area the size of the argument delta right after the
3226 // original RETADDR, but before the saved framepointer or the spilled registers
3227 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3239 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3240 /// for a 16 byte align requirement.
3242 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3243 SelectionDAG& DAG) const {
3244 MachineFunction &MF = DAG.getMachineFunction();
3245 const TargetMachine &TM = MF.getTarget();
3246 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3247 TM.getSubtargetImpl()->getRegisterInfo());
3248 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3249 unsigned StackAlignment = TFI.getStackAlignment();
3250 uint64_t AlignMask = StackAlignment - 1;
3251 int64_t Offset = StackSize;
3252 unsigned SlotSize = RegInfo->getSlotSize();
3253 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3254 // Number smaller than 12 so just add the difference.
3255 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3257 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3258 Offset = ((~AlignMask) & Offset) + StackAlignment +
3259 (StackAlignment-SlotSize);
3264 /// MatchingStackOffset - Return true if the given stack call argument is
3265 /// already available in the same position (relatively) of the caller's
3266 /// incoming argument stack.
3268 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3269 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3270 const X86InstrInfo *TII) {
3271 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3273 if (Arg.getOpcode() == ISD::CopyFromReg) {
3274 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3275 if (!TargetRegisterInfo::isVirtualRegister(VR))
3277 MachineInstr *Def = MRI->getVRegDef(VR);
3280 if (!Flags.isByVal()) {
3281 if (!TII->isLoadFromStackSlot(Def, FI))
3284 unsigned Opcode = Def->getOpcode();
3285 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3286 Def->getOperand(1).isFI()) {
3287 FI = Def->getOperand(1).getIndex();
3288 Bytes = Flags.getByValSize();
3292 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3293 if (Flags.isByVal())
3294 // ByVal argument is passed in as a pointer but it's now being
3295 // dereferenced. e.g.
3296 // define @foo(%struct.X* %A) {
3297 // tail call @bar(%struct.X* byval %A)
3300 SDValue Ptr = Ld->getBasePtr();
3301 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3304 FI = FINode->getIndex();
3305 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3306 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3307 FI = FINode->getIndex();
3308 Bytes = Flags.getByValSize();
3312 assert(FI != INT_MAX);
3313 if (!MFI->isFixedObjectIndex(FI))
3315 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3318 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3319 /// for tail call optimization. Targets which want to do tail call
3320 /// optimization should implement this function.
3322 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3323 CallingConv::ID CalleeCC,
3325 bool isCalleeStructRet,
3326 bool isCallerStructRet,
3328 const SmallVectorImpl<ISD::OutputArg> &Outs,
3329 const SmallVectorImpl<SDValue> &OutVals,
3330 const SmallVectorImpl<ISD::InputArg> &Ins,
3331 SelectionDAG &DAG) const {
3332 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3335 // If -tailcallopt is specified, make fastcc functions tail-callable.
3336 const MachineFunction &MF = DAG.getMachineFunction();
3337 const Function *CallerF = MF.getFunction();
3339 // If the function return type is x86_fp80 and the callee return type is not,
3340 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3341 // perform a tailcall optimization here.
3342 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3345 CallingConv::ID CallerCC = CallerF->getCallingConv();
3346 bool CCMatch = CallerCC == CalleeCC;
3347 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3348 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3350 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3351 if (IsTailCallConvention(CalleeCC) && CCMatch)
3356 // Look for obvious safe cases to perform tail call optimization that do not
3357 // require ABI changes. This is what gcc calls sibcall.
3359 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3360 // emit a special epilogue.
3361 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3362 DAG.getSubtarget().getRegisterInfo());
3363 if (RegInfo->needsStackRealignment(MF))
3366 // Also avoid sibcall optimization if either caller or callee uses struct
3367 // return semantics.
3368 if (isCalleeStructRet || isCallerStructRet)
3371 // An stdcall/thiscall caller is expected to clean up its arguments; the
3372 // callee isn't going to do that.
3373 // FIXME: this is more restrictive than needed. We could produce a tailcall
3374 // when the stack adjustment matches. For example, with a thiscall that takes
3375 // only one argument.
3376 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3377 CallerCC == CallingConv::X86_ThisCall))
3380 // Do not sibcall optimize vararg calls unless all arguments are passed via
3382 if (isVarArg && !Outs.empty()) {
3384 // Optimizing for varargs on Win64 is unlikely to be safe without
3385 // additional testing.
3386 if (IsCalleeWin64 || IsCallerWin64)
3389 SmallVector<CCValAssign, 16> ArgLocs;
3390 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3393 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3394 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3395 if (!ArgLocs[i].isRegLoc())
3399 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3400 // stack. Therefore, if it's not used by the call it is not safe to optimize
3401 // this into a sibcall.
3402 bool Unused = false;
3403 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3410 SmallVector<CCValAssign, 16> RVLocs;
3411 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3413 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3414 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3415 CCValAssign &VA = RVLocs[i];
3416 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3421 // If the calling conventions do not match, then we'd better make sure the
3422 // results are returned in the same way as what the caller expects.
3424 SmallVector<CCValAssign, 16> RVLocs1;
3425 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3427 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3429 SmallVector<CCValAssign, 16> RVLocs2;
3430 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3432 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3434 if (RVLocs1.size() != RVLocs2.size())
3436 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3437 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3439 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3441 if (RVLocs1[i].isRegLoc()) {
3442 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3445 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3451 // If the callee takes no arguments then go on to check the results of the
3453 if (!Outs.empty()) {
3454 // Check if stack adjustment is needed. For now, do not do this if any
3455 // argument is passed on the stack.
3456 SmallVector<CCValAssign, 16> ArgLocs;
3457 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3460 // Allocate shadow area for Win64
3462 CCInfo.AllocateStack(32, 8);
3464 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3465 if (CCInfo.getNextStackOffset()) {
3466 MachineFunction &MF = DAG.getMachineFunction();
3467 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3470 // Check if the arguments are already laid out in the right way as
3471 // the caller's fixed stack objects.
3472 MachineFrameInfo *MFI = MF.getFrameInfo();
3473 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3474 const X86InstrInfo *TII =
3475 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3476 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3477 CCValAssign &VA = ArgLocs[i];
3478 SDValue Arg = OutVals[i];
3479 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3480 if (VA.getLocInfo() == CCValAssign::Indirect)
3482 if (!VA.isRegLoc()) {
3483 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3490 // If the tailcall address may be in a register, then make sure it's
3491 // possible to register allocate for it. In 32-bit, the call address can
3492 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3493 // callee-saved registers are restored. These happen to be the same
3494 // registers used to pass 'inreg' arguments so watch out for those.
3495 if (!Subtarget->is64Bit() &&
3496 ((!isa<GlobalAddressSDNode>(Callee) &&
3497 !isa<ExternalSymbolSDNode>(Callee)) ||
3498 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3499 unsigned NumInRegs = 0;
3500 // In PIC we need an extra register to formulate the address computation
3502 unsigned MaxInRegs =
3503 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3505 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3506 CCValAssign &VA = ArgLocs[i];
3509 unsigned Reg = VA.getLocReg();
3512 case X86::EAX: case X86::EDX: case X86::ECX:
3513 if (++NumInRegs == MaxInRegs)
3525 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3526 const TargetLibraryInfo *libInfo) const {
3527 return X86::createFastISel(funcInfo, libInfo);
3530 //===----------------------------------------------------------------------===//
3531 // Other Lowering Hooks
3532 //===----------------------------------------------------------------------===//
3534 static bool MayFoldLoad(SDValue Op) {
3535 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3538 static bool MayFoldIntoStore(SDValue Op) {
3539 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3542 static bool isTargetShuffle(unsigned Opcode) {
3544 default: return false;
3545 case X86ISD::BLENDI:
3546 case X86ISD::PSHUFB:
3547 case X86ISD::PSHUFD:
3548 case X86ISD::PSHUFHW:
3549 case X86ISD::PSHUFLW:
3551 case X86ISD::PALIGNR:
3552 case X86ISD::MOVLHPS:
3553 case X86ISD::MOVLHPD:
3554 case X86ISD::MOVHLPS:
3555 case X86ISD::MOVLPS:
3556 case X86ISD::MOVLPD:
3557 case X86ISD::MOVSHDUP:
3558 case X86ISD::MOVSLDUP:
3559 case X86ISD::MOVDDUP:
3562 case X86ISD::UNPCKL:
3563 case X86ISD::UNPCKH:
3564 case X86ISD::VPERMILPI:
3565 case X86ISD::VPERM2X128:
3566 case X86ISD::VPERMI:
3571 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3572 SDValue V1, SelectionDAG &DAG) {
3574 default: llvm_unreachable("Unknown x86 shuffle node");
3575 case X86ISD::MOVSHDUP:
3576 case X86ISD::MOVSLDUP:
3577 case X86ISD::MOVDDUP:
3578 return DAG.getNode(Opc, dl, VT, V1);
3582 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3583 SDValue V1, unsigned TargetMask,
3584 SelectionDAG &DAG) {
3586 default: llvm_unreachable("Unknown x86 shuffle node");
3587 case X86ISD::PSHUFD:
3588 case X86ISD::PSHUFHW:
3589 case X86ISD::PSHUFLW:
3590 case X86ISD::VPERMILPI:
3591 case X86ISD::VPERMI:
3592 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3596 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3597 SDValue V1, SDValue V2, unsigned TargetMask,
3598 SelectionDAG &DAG) {
3600 default: llvm_unreachable("Unknown x86 shuffle node");
3601 case X86ISD::PALIGNR:
3602 case X86ISD::VALIGN:
3604 case X86ISD::VPERM2X128:
3605 return DAG.getNode(Opc, dl, VT, V1, V2,
3606 DAG.getConstant(TargetMask, MVT::i8));
3610 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3611 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3613 default: llvm_unreachable("Unknown x86 shuffle node");
3614 case X86ISD::MOVLHPS:
3615 case X86ISD::MOVLHPD:
3616 case X86ISD::MOVHLPS:
3617 case X86ISD::MOVLPS:
3618 case X86ISD::MOVLPD:
3621 case X86ISD::UNPCKL:
3622 case X86ISD::UNPCKH:
3623 return DAG.getNode(Opc, dl, VT, V1, V2);
3627 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3628 MachineFunction &MF = DAG.getMachineFunction();
3629 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3630 DAG.getSubtarget().getRegisterInfo());
3631 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3632 int ReturnAddrIndex = FuncInfo->getRAIndex();
3634 if (ReturnAddrIndex == 0) {
3635 // Set up a frame object for the return address.
3636 unsigned SlotSize = RegInfo->getSlotSize();
3637 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3640 FuncInfo->setRAIndex(ReturnAddrIndex);
3643 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3646 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3647 bool hasSymbolicDisplacement) {
3648 // Offset should fit into 32 bit immediate field.
3649 if (!isInt<32>(Offset))
3652 // If we don't have a symbolic displacement - we don't have any extra
3654 if (!hasSymbolicDisplacement)
3657 // FIXME: Some tweaks might be needed for medium code model.
3658 if (M != CodeModel::Small && M != CodeModel::Kernel)
3661 // For small code model we assume that latest object is 16MB before end of 31
3662 // bits boundary. We may also accept pretty large negative constants knowing
3663 // that all objects are in the positive half of address space.
3664 if (M == CodeModel::Small && Offset < 16*1024*1024)
3667 // For kernel code model we know that all object resist in the negative half
3668 // of 32bits address space. We may not accept negative offsets, since they may
3669 // be just off and we may accept pretty large positive ones.
3670 if (M == CodeModel::Kernel && Offset > 0)
3676 /// isCalleePop - Determines whether the callee is required to pop its
3677 /// own arguments. Callee pop is necessary to support tail calls.
3678 bool X86::isCalleePop(CallingConv::ID CallingConv,
3679 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3680 switch (CallingConv) {
3683 case CallingConv::X86_StdCall:
3684 case CallingConv::X86_FastCall:
3685 case CallingConv::X86_ThisCall:
3687 case CallingConv::Fast:
3688 case CallingConv::GHC:
3689 case CallingConv::HiPE:
3696 /// \brief Return true if the condition is an unsigned comparison operation.
3697 static bool isX86CCUnsigned(unsigned X86CC) {
3699 default: llvm_unreachable("Invalid integer condition!");
3700 case X86::COND_E: return true;
3701 case X86::COND_G: return false;
3702 case X86::COND_GE: return false;
3703 case X86::COND_L: return false;
3704 case X86::COND_LE: return false;
3705 case X86::COND_NE: return true;
3706 case X86::COND_B: return true;
3707 case X86::COND_A: return true;
3708 case X86::COND_BE: return true;
3709 case X86::COND_AE: return true;
3711 llvm_unreachable("covered switch fell through?!");
3714 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3715 /// specific condition code, returning the condition code and the LHS/RHS of the
3716 /// comparison to make.
3717 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3718 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3720 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3721 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3722 // X > -1 -> X == 0, jump !sign.
3723 RHS = DAG.getConstant(0, RHS.getValueType());
3724 return X86::COND_NS;
3726 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3727 // X < 0 -> X == 0, jump on sign.
3730 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3732 RHS = DAG.getConstant(0, RHS.getValueType());
3733 return X86::COND_LE;
3737 switch (SetCCOpcode) {
3738 default: llvm_unreachable("Invalid integer condition!");
3739 case ISD::SETEQ: return X86::COND_E;
3740 case ISD::SETGT: return X86::COND_G;
3741 case ISD::SETGE: return X86::COND_GE;
3742 case ISD::SETLT: return X86::COND_L;
3743 case ISD::SETLE: return X86::COND_LE;
3744 case ISD::SETNE: return X86::COND_NE;
3745 case ISD::SETULT: return X86::COND_B;
3746 case ISD::SETUGT: return X86::COND_A;
3747 case ISD::SETULE: return X86::COND_BE;
3748 case ISD::SETUGE: return X86::COND_AE;
3752 // First determine if it is required or is profitable to flip the operands.
3754 // If LHS is a foldable load, but RHS is not, flip the condition.
3755 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3756 !ISD::isNON_EXTLoad(RHS.getNode())) {
3757 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3758 std::swap(LHS, RHS);
3761 switch (SetCCOpcode) {
3767 std::swap(LHS, RHS);
3771 // On a floating point condition, the flags are set as follows:
3773 // 0 | 0 | 0 | X > Y
3774 // 0 | 0 | 1 | X < Y
3775 // 1 | 0 | 0 | X == Y
3776 // 1 | 1 | 1 | unordered
3777 switch (SetCCOpcode) {
3778 default: llvm_unreachable("Condcode should be pre-legalized away");
3780 case ISD::SETEQ: return X86::COND_E;
3781 case ISD::SETOLT: // flipped
3783 case ISD::SETGT: return X86::COND_A;
3784 case ISD::SETOLE: // flipped
3786 case ISD::SETGE: return X86::COND_AE;
3787 case ISD::SETUGT: // flipped
3789 case ISD::SETLT: return X86::COND_B;
3790 case ISD::SETUGE: // flipped
3792 case ISD::SETLE: return X86::COND_BE;
3794 case ISD::SETNE: return X86::COND_NE;
3795 case ISD::SETUO: return X86::COND_P;
3796 case ISD::SETO: return X86::COND_NP;
3798 case ISD::SETUNE: return X86::COND_INVALID;
3802 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3803 /// code. Current x86 isa includes the following FP cmov instructions:
3804 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3805 static bool hasFPCMov(unsigned X86CC) {
3821 /// isFPImmLegal - Returns true if the target can instruction select the
3822 /// specified FP immediate natively. If false, the legalizer will
3823 /// materialize the FP immediate as a load from a constant pool.
3824 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3825 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3826 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3832 /// \brief Returns true if it is beneficial to convert a load of a constant
3833 /// to just the constant itself.
3834 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3836 assert(Ty->isIntegerTy());
3838 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3839 if (BitSize == 0 || BitSize > 64)
3844 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3845 /// the specified range (L, H].
3846 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3847 return (Val < 0) || (Val >= Low && Val < Hi);
3850 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3851 /// specified value.
3852 static bool isUndefOrEqual(int Val, int CmpVal) {
3853 return (Val < 0 || Val == CmpVal);
3856 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3857 /// from position Pos and ending in Pos+Size, falls within the specified
3858 /// sequential range (L, L+Pos]. or is undef.
3859 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3860 unsigned Pos, unsigned Size, int Low) {
3861 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3862 if (!isUndefOrEqual(Mask[i], Low))
3867 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3868 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3869 /// the second operand.
3870 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3871 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3872 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3873 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3874 return (Mask[0] < 2 && Mask[1] < 2);
3878 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3879 /// is suitable for input to PSHUFHW.
3880 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3881 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3884 // Lower quadword copied in order or undef.
3885 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3888 // Upper quadword shuffled.
3889 for (unsigned i = 4; i != 8; ++i)
3890 if (!isUndefOrInRange(Mask[i], 4, 8))
3893 if (VT == MVT::v16i16) {
3894 // Lower quadword copied in order or undef.
3895 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3898 // Upper quadword shuffled.
3899 for (unsigned i = 12; i != 16; ++i)
3900 if (!isUndefOrInRange(Mask[i], 12, 16))
3907 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3908 /// is suitable for input to PSHUFLW.
3909 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3910 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3913 // Upper quadword copied in order.
3914 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3917 // Lower quadword shuffled.
3918 for (unsigned i = 0; i != 4; ++i)
3919 if (!isUndefOrInRange(Mask[i], 0, 4))
3922 if (VT == MVT::v16i16) {
3923 // Upper quadword copied in order.
3924 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3927 // Lower quadword shuffled.
3928 for (unsigned i = 8; i != 12; ++i)
3929 if (!isUndefOrInRange(Mask[i], 8, 12))
3936 /// \brief Return true if the mask specifies a shuffle of elements that is
3937 /// suitable for input to intralane (palignr) or interlane (valign) vector
3939 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3940 unsigned NumElts = VT.getVectorNumElements();
3941 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3942 unsigned NumLaneElts = NumElts/NumLanes;
3944 // Do not handle 64-bit element shuffles with palignr.
3945 if (NumLaneElts == 2)
3948 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3950 for (i = 0; i != NumLaneElts; ++i) {
3955 // Lane is all undef, go to next lane
3956 if (i == NumLaneElts)
3959 int Start = Mask[i+l];
3961 // Make sure its in this lane in one of the sources
3962 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3963 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3966 // If not lane 0, then we must match lane 0
3967 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3970 // Correct second source to be contiguous with first source
3971 if (Start >= (int)NumElts)
3972 Start -= NumElts - NumLaneElts;
3974 // Make sure we're shifting in the right direction.
3975 if (Start <= (int)(i+l))
3980 // Check the rest of the elements to see if they are consecutive.
3981 for (++i; i != NumLaneElts; ++i) {
3982 int Idx = Mask[i+l];
3984 // Make sure its in this lane
3985 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3986 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3989 // If not lane 0, then we must match lane 0
3990 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3993 if (Idx >= (int)NumElts)
3994 Idx -= NumElts - NumLaneElts;
3996 if (!isUndefOrEqual(Idx, Start+i))
4005 /// \brief Return true if the node specifies a shuffle of elements that is
4006 /// suitable for input to PALIGNR.
4007 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4008 const X86Subtarget *Subtarget) {
4009 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4010 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4011 VT.is512BitVector())
4012 // FIXME: Add AVX512BW.
4015 return isAlignrMask(Mask, VT, false);
4018 /// \brief Return true if the node specifies a shuffle of elements that is
4019 /// suitable for input to VALIGN.
4020 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4021 const X86Subtarget *Subtarget) {
4022 // FIXME: Add AVX512VL.
4023 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4025 return isAlignrMask(Mask, VT, true);
4028 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4029 /// the two vector operands have swapped position.
4030 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4031 unsigned NumElems) {
4032 for (unsigned i = 0; i != NumElems; ++i) {
4036 else if (idx < (int)NumElems)
4037 Mask[i] = idx + NumElems;
4039 Mask[i] = idx - NumElems;
4043 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4044 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4045 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4046 /// reverse of what x86 shuffles want.
4047 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4049 unsigned NumElems = VT.getVectorNumElements();
4050 unsigned NumLanes = VT.getSizeInBits()/128;
4051 unsigned NumLaneElems = NumElems/NumLanes;
4053 if (NumLaneElems != 2 && NumLaneElems != 4)
4056 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4057 bool symetricMaskRequired =
4058 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4060 // VSHUFPSY divides the resulting vector into 4 chunks.
4061 // The sources are also splitted into 4 chunks, and each destination
4062 // chunk must come from a different source chunk.
4064 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4065 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4067 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4068 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4070 // VSHUFPDY divides the resulting vector into 4 chunks.
4071 // The sources are also splitted into 4 chunks, and each destination
4072 // chunk must come from a different source chunk.
4074 // SRC1 => X3 X2 X1 X0
4075 // SRC2 => Y3 Y2 Y1 Y0
4077 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4079 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4080 unsigned HalfLaneElems = NumLaneElems/2;
4081 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4082 for (unsigned i = 0; i != NumLaneElems; ++i) {
4083 int Idx = Mask[i+l];
4084 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4085 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4087 // For VSHUFPSY, the mask of the second half must be the same as the
4088 // first but with the appropriate offsets. This works in the same way as
4089 // VPERMILPS works with masks.
4090 if (!symetricMaskRequired || Idx < 0)
4092 if (MaskVal[i] < 0) {
4093 MaskVal[i] = Idx - l;
4096 if ((signed)(Idx - l) != MaskVal[i])
4104 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4105 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4106 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4107 if (!VT.is128BitVector())
4110 unsigned NumElems = VT.getVectorNumElements();
4115 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4116 return isUndefOrEqual(Mask[0], 6) &&
4117 isUndefOrEqual(Mask[1], 7) &&
4118 isUndefOrEqual(Mask[2], 2) &&
4119 isUndefOrEqual(Mask[3], 3);
4122 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4123 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4125 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4126 if (!VT.is128BitVector())
4129 unsigned NumElems = VT.getVectorNumElements();
4134 return isUndefOrEqual(Mask[0], 2) &&
4135 isUndefOrEqual(Mask[1], 3) &&
4136 isUndefOrEqual(Mask[2], 2) &&
4137 isUndefOrEqual(Mask[3], 3);
4140 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4141 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4142 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4143 if (!VT.is128BitVector())
4146 unsigned NumElems = VT.getVectorNumElements();
4148 if (NumElems != 2 && NumElems != 4)
4151 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i + NumElems))
4155 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4156 if (!isUndefOrEqual(Mask[i], i))
4162 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4163 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4164 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4165 if (!VT.is128BitVector())
4168 unsigned NumElems = VT.getVectorNumElements();
4170 if (NumElems != 2 && NumElems != 4)
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i], i))
4177 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4178 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4184 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4185 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4186 /// i. e: If all but one element come from the same vector.
4187 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4188 // TODO: Deal with AVX's VINSERTPS
4189 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4192 unsigned CorrectPosV1 = 0;
4193 unsigned CorrectPosV2 = 0;
4194 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4195 if (Mask[i] == -1) {
4203 else if (Mask[i] == i + 4)
4207 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4208 // We have 3 elements (undefs count as elements from any vector) from one
4209 // vector, and one from another.
4216 // Some special combinations that can be optimized.
4219 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4220 SelectionDAG &DAG) {
4221 MVT VT = SVOp->getSimpleValueType(0);
4224 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4227 ArrayRef<int> Mask = SVOp->getMask();
4229 // These are the special masks that may be optimized.
4230 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4231 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4232 bool MatchEvenMask = true;
4233 bool MatchOddMask = true;
4234 for (int i=0; i<8; ++i) {
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4236 MatchEvenMask = false;
4237 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4238 MatchOddMask = false;
4241 if (!MatchEvenMask && !MatchOddMask)
4244 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4246 SDValue Op0 = SVOp->getOperand(0);
4247 SDValue Op1 = SVOp->getOperand(1);
4249 if (MatchEvenMask) {
4250 // Shift the second operand right to 32 bits.
4251 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4252 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4254 // Shift the first operand left to 32 bits.
4255 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4256 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4258 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4259 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4262 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4263 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4264 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4265 bool HasInt256, bool V2IsSplat = false) {
4267 assert(VT.getSizeInBits() >= 128 &&
4268 "Unsupported vector type for unpckl");
4270 unsigned NumElts = VT.getVectorNumElements();
4271 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4272 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4275 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4276 "Unsupported vector type for unpckh");
4278 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4279 unsigned NumLanes = VT.getSizeInBits()/128;
4280 unsigned NumLaneElts = NumElts/NumLanes;
4282 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4283 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4284 int BitI = Mask[l+i];
4285 int BitI1 = Mask[l+i+1];
4286 if (!isUndefOrEqual(BitI, j))
4289 if (!isUndefOrEqual(BitI1, NumElts))
4292 if (!isUndefOrEqual(BitI1, j + NumElts))
4301 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4302 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4303 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4304 bool HasInt256, bool V2IsSplat = false) {
4305 assert(VT.getSizeInBits() >= 128 &&
4306 "Unsupported vector type for unpckh");
4308 unsigned NumElts = VT.getVectorNumElements();
4309 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4310 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4313 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4314 "Unsupported vector type for unpckh");
4316 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4317 unsigned NumLanes = VT.getSizeInBits()/128;
4318 unsigned NumLaneElts = NumElts/NumLanes;
4320 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4321 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4322 int BitI = Mask[l+i];
4323 int BitI1 = Mask[l+i+1];
4324 if (!isUndefOrEqual(BitI, j))
4327 if (isUndefOrEqual(BitI1, NumElts))
4330 if (!isUndefOrEqual(BitI1, j+NumElts))
4338 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4339 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4341 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4342 unsigned NumElts = VT.getVectorNumElements();
4343 bool Is256BitVec = VT.is256BitVector();
4345 if (VT.is512BitVector())
4347 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4348 "Unsupported vector type for unpckh");
4350 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4351 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4354 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4355 // FIXME: Need a better way to get rid of this, there's no latency difference
4356 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4357 // the former later. We should also remove the "_undef" special mask.
4358 if (NumElts == 4 && Is256BitVec)
4361 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4362 // independently on 128-bit lanes.
4363 unsigned NumLanes = VT.getSizeInBits()/128;
4364 unsigned NumLaneElts = NumElts/NumLanes;
4366 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4367 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4368 int BitI = Mask[l+i];
4369 int BitI1 = Mask[l+i+1];
4371 if (!isUndefOrEqual(BitI, j))
4373 if (!isUndefOrEqual(BitI1, j))
4381 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4382 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4384 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4385 unsigned NumElts = VT.getVectorNumElements();
4387 if (VT.is512BitVector())
4390 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4391 "Unsupported vector type for unpckh");
4393 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4394 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4397 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4398 // independently on 128-bit lanes.
4399 unsigned NumLanes = VT.getSizeInBits()/128;
4400 unsigned NumLaneElts = NumElts/NumLanes;
4402 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4403 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4404 int BitI = Mask[l+i];
4405 int BitI1 = Mask[l+i+1];
4406 if (!isUndefOrEqual(BitI, j))
4408 if (!isUndefOrEqual(BitI1, j))
4415 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4416 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4417 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4418 if (!VT.is512BitVector())
4421 unsigned NumElts = VT.getVectorNumElements();
4422 unsigned HalfSize = NumElts/2;
4423 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4424 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4429 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4430 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4438 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4439 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4440 /// MOVSD, and MOVD, i.e. setting the lowest element.
4441 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4442 if (VT.getVectorElementType().getSizeInBits() < 32)
4444 if (!VT.is128BitVector())
4447 unsigned NumElts = VT.getVectorNumElements();
4449 if (!isUndefOrEqual(Mask[0], NumElts))
4452 for (unsigned i = 1; i != NumElts; ++i)
4453 if (!isUndefOrEqual(Mask[i], i))
4459 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4460 /// as permutations between 128-bit chunks or halves. As an example: this
4462 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4463 /// The first half comes from the second half of V1 and the second half from the
4464 /// the second half of V2.
4465 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4466 if (!HasFp256 || !VT.is256BitVector())
4469 // The shuffle result is divided into half A and half B. In total the two
4470 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4471 // B must come from C, D, E or F.
4472 unsigned HalfSize = VT.getVectorNumElements()/2;
4473 bool MatchA = false, MatchB = false;
4475 // Check if A comes from one of C, D, E, F.
4476 for (unsigned Half = 0; Half != 4; ++Half) {
4477 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4483 // Check if B comes from one of C, D, E, F.
4484 for (unsigned Half = 0; Half != 4; ++Half) {
4485 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4491 return MatchA && MatchB;
4494 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4495 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4496 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4497 MVT VT = SVOp->getSimpleValueType(0);
4499 unsigned HalfSize = VT.getVectorNumElements()/2;
4501 unsigned FstHalf = 0, SndHalf = 0;
4502 for (unsigned i = 0; i < HalfSize; ++i) {
4503 if (SVOp->getMaskElt(i) > 0) {
4504 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4508 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4509 if (SVOp->getMaskElt(i) > 0) {
4510 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4515 return (FstHalf | (SndHalf << 4));
4518 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4519 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4520 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4524 unsigned NumElts = VT.getVectorNumElements();
4526 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4527 for (unsigned i = 0; i != NumElts; ++i) {
4530 Imm8 |= Mask[i] << (i*2);
4535 unsigned LaneSize = 4;
4536 SmallVector<int, 4> MaskVal(LaneSize, -1);
4538 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4539 for (unsigned i = 0; i != LaneSize; ++i) {
4540 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4544 if (MaskVal[i] < 0) {
4545 MaskVal[i] = Mask[i+l] - l;
4546 Imm8 |= MaskVal[i] << (i*2);
4549 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4556 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4557 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4558 /// Note that VPERMIL mask matching is different depending whether theunderlying
4559 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4560 /// to the same elements of the low, but to the higher half of the source.
4561 /// In VPERMILPD the two lanes could be shuffled independently of each other
4562 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4563 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4564 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4565 if (VT.getSizeInBits() < 256 || EltSize < 32)
4567 bool symetricMaskRequired = (EltSize == 32);
4568 unsigned NumElts = VT.getVectorNumElements();
4570 unsigned NumLanes = VT.getSizeInBits()/128;
4571 unsigned LaneSize = NumElts/NumLanes;
4572 // 2 or 4 elements in one lane
4574 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4575 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4576 for (unsigned i = 0; i != LaneSize; ++i) {
4577 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4579 if (symetricMaskRequired) {
4580 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4581 ExpectedMaskVal[i] = Mask[i+l] - l;
4584 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4592 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4593 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4594 /// element of vector 2 and the other elements to come from vector 1 in order.
4595 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4596 bool V2IsSplat = false, bool V2IsUndef = false) {
4597 if (!VT.is128BitVector())
4600 unsigned NumOps = VT.getVectorNumElements();
4601 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4604 if (!isUndefOrEqual(Mask[0], 0))
4607 for (unsigned i = 1; i != NumOps; ++i)
4608 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4609 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4610 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4616 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4617 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4618 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4619 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4620 const X86Subtarget *Subtarget) {
4621 if (!Subtarget->hasSSE3())
4624 unsigned NumElems = VT.getVectorNumElements();
4626 if ((VT.is128BitVector() && NumElems != 4) ||
4627 (VT.is256BitVector() && NumElems != 8) ||
4628 (VT.is512BitVector() && NumElems != 16))
4631 // "i+1" is the value the indexed mask element must have
4632 for (unsigned i = 0; i != NumElems; i += 2)
4633 if (!isUndefOrEqual(Mask[i], i+1) ||
4634 !isUndefOrEqual(Mask[i+1], i+1))
4640 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4641 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4642 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4643 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4644 const X86Subtarget *Subtarget) {
4645 if (!Subtarget->hasSSE3())
4648 unsigned NumElems = VT.getVectorNumElements();
4650 if ((VT.is128BitVector() && NumElems != 4) ||
4651 (VT.is256BitVector() && NumElems != 8) ||
4652 (VT.is512BitVector() && NumElems != 16))
4655 // "i" is the value the indexed mask element must have
4656 for (unsigned i = 0; i != NumElems; i += 2)
4657 if (!isUndefOrEqual(Mask[i], i) ||
4658 !isUndefOrEqual(Mask[i+1], i))
4664 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4665 /// specifies a shuffle of elements that is suitable for input to 256-bit
4666 /// version of MOVDDUP.
4667 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4668 if (!HasFp256 || !VT.is256BitVector())
4671 unsigned NumElts = VT.getVectorNumElements();
4675 for (unsigned i = 0; i != NumElts/2; ++i)
4676 if (!isUndefOrEqual(Mask[i], 0))
4678 for (unsigned i = NumElts/2; i != NumElts; ++i)
4679 if (!isUndefOrEqual(Mask[i], NumElts/2))
4684 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4685 /// specifies a shuffle of elements that is suitable for input to 128-bit
4686 /// version of MOVDDUP.
4687 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4688 if (!VT.is128BitVector())
4691 unsigned e = VT.getVectorNumElements() / 2;
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[i], i))
4695 for (unsigned i = 0; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[e+i], i))
4701 /// isVEXTRACTIndex - Return true if the specified
4702 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4703 /// suitable for instruction that extract 128 or 256 bit vectors
4704 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4705 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4706 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4709 // The index should be aligned on a vecWidth-bit boundary.
4711 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4713 MVT VT = N->getSimpleValueType(0);
4714 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4715 bool Result = (Index * ElSize) % vecWidth == 0;
4720 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4721 /// operand specifies a subvector insert that is suitable for input to
4722 /// insertion of 128 or 256-bit subvectors
4723 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4724 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4725 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4727 // The index should be aligned on a vecWidth-bit boundary.
4729 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4731 MVT VT = N->getSimpleValueType(0);
4732 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4733 bool Result = (Index * ElSize) % vecWidth == 0;
4738 bool X86::isVINSERT128Index(SDNode *N) {
4739 return isVINSERTIndex(N, 128);
4742 bool X86::isVINSERT256Index(SDNode *N) {
4743 return isVINSERTIndex(N, 256);
4746 bool X86::isVEXTRACT128Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 128);
4750 bool X86::isVEXTRACT256Index(SDNode *N) {
4751 return isVEXTRACTIndex(N, 256);
4754 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4755 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4756 /// Handles 128-bit and 256-bit.
4757 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4758 MVT VT = N->getSimpleValueType(0);
4760 assert((VT.getSizeInBits() >= 128) &&
4761 "Unsupported vector type for PSHUF/SHUFP");
4763 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4764 // independently on 128-bit lanes.
4765 unsigned NumElts = VT.getVectorNumElements();
4766 unsigned NumLanes = VT.getSizeInBits()/128;
4767 unsigned NumLaneElts = NumElts/NumLanes;
4769 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4770 "Only supports 2, 4 or 8 elements per lane");
4772 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4774 for (unsigned i = 0; i != NumElts; ++i) {
4775 int Elt = N->getMaskElt(i);
4776 if (Elt < 0) continue;
4777 Elt &= NumLaneElts - 1;
4778 unsigned ShAmt = (i << Shift) % 8;
4779 Mask |= Elt << ShAmt;
4785 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4786 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4787 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4788 MVT VT = N->getSimpleValueType(0);
4790 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4791 "Unsupported vector type for PSHUFHW");
4793 unsigned NumElts = VT.getVectorNumElements();
4796 for (unsigned l = 0; l != NumElts; l += 8) {
4797 // 8 nodes per lane, but we only care about the last 4.
4798 for (unsigned i = 0; i < 4; ++i) {
4799 int Elt = N->getMaskElt(l+i+4);
4800 if (Elt < 0) continue;
4801 Elt &= 0x3; // only 2-bits.
4802 Mask |= Elt << (i * 2);
4809 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4810 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4811 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4812 MVT VT = N->getSimpleValueType(0);
4814 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4815 "Unsupported vector type for PSHUFHW");
4817 unsigned NumElts = VT.getVectorNumElements();
4820 for (unsigned l = 0; l != NumElts; l += 8) {
4821 // 8 nodes per lane, but we only care about the first 4.
4822 for (unsigned i = 0; i < 4; ++i) {
4823 int Elt = N->getMaskElt(l+i);
4824 if (Elt < 0) continue;
4825 Elt &= 0x3; // only 2-bits
4826 Mask |= Elt << (i * 2);
4833 /// \brief Return the appropriate immediate to shuffle the specified
4834 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4835 /// VALIGN (if Interlane is true) instructions.
4836 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4838 MVT VT = SVOp->getSimpleValueType(0);
4839 unsigned EltSize = InterLane ? 1 :
4840 VT.getVectorElementType().getSizeInBits() >> 3;
4842 unsigned NumElts = VT.getVectorNumElements();
4843 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4844 unsigned NumLaneElts = NumElts/NumLanes;
4848 for (i = 0; i != NumElts; ++i) {
4849 Val = SVOp->getMaskElt(i);
4853 if (Val >= (int)NumElts)
4854 Val -= NumElts - NumLaneElts;
4856 assert(Val - i > 0 && "PALIGNR imm should be positive");
4857 return (Val - i) * EltSize;
4860 /// \brief Return the appropriate immediate to shuffle the specified
4861 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4862 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4863 return getShuffleAlignrImmediate(SVOp, false);
4866 /// \brief Return the appropriate immediate to shuffle the specified
4867 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4868 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4869 return getShuffleAlignrImmediate(SVOp, true);
4873 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4874 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4875 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4876 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4879 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4881 MVT VecVT = N->getOperand(0).getSimpleValueType();
4882 MVT ElVT = VecVT.getVectorElementType();
4884 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4885 return Index / NumElemsPerChunk;
4888 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4889 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4890 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4891 llvm_unreachable("Illegal insert subvector for VINSERT");
4894 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4896 MVT VecVT = N->getSimpleValueType(0);
4897 MVT ElVT = VecVT.getVectorElementType();
4899 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4900 return Index / NumElemsPerChunk;
4903 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4904 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4905 /// and VINSERTI128 instructions.
4906 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4907 return getExtractVEXTRACTImmediate(N, 128);
4910 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4911 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4912 /// and VINSERTI64x4 instructions.
4913 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4914 return getExtractVEXTRACTImmediate(N, 256);
4917 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4918 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4919 /// and VINSERTI128 instructions.
4920 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4921 return getInsertVINSERTImmediate(N, 128);
4924 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4925 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4926 /// and VINSERTI64x4 instructions.
4927 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4928 return getInsertVINSERTImmediate(N, 256);
4931 /// isZero - Returns true if Elt is a constant integer zero
4932 static bool isZero(SDValue V) {
4933 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4934 return C && C->isNullValue();
4937 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4939 bool X86::isZeroNode(SDValue Elt) {
4942 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4943 return CFP->getValueAPF().isPosZero();
4947 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4948 /// match movhlps. The lower half elements should come from upper half of
4949 /// V1 (and in order), and the upper half elements should come from the upper
4950 /// half of V2 (and in order).
4951 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4952 if (!VT.is128BitVector())
4954 if (VT.getVectorNumElements() != 4)
4956 for (unsigned i = 0, e = 2; i != e; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+2))
4959 for (unsigned i = 2; i != 4; ++i)
4960 if (!isUndefOrEqual(Mask[i], i+4))
4965 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4966 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4968 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4969 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4971 N = N->getOperand(0).getNode();
4972 if (!ISD::isNON_EXTLoad(N))
4975 *LD = cast<LoadSDNode>(N);
4979 // Test whether the given value is a vector value which will be legalized
4981 static bool WillBeConstantPoolLoad(SDNode *N) {
4982 if (N->getOpcode() != ISD::BUILD_VECTOR)
4985 // Check for any non-constant elements.
4986 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4987 switch (N->getOperand(i).getNode()->getOpcode()) {
4989 case ISD::ConstantFP:
4996 // Vectors of all-zeros and all-ones are materialized with special
4997 // instructions rather than being loaded.
4998 return !ISD::isBuildVectorAllZeros(N) &&
4999 !ISD::isBuildVectorAllOnes(N);
5002 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5003 /// match movlp{s|d}. The lower half elements should come from lower half of
5004 /// V1 (and in order), and the upper half elements should come from the upper
5005 /// half of V2 (and in order). And since V1 will become the source of the
5006 /// MOVLP, it must be either a vector load or a scalar load to vector.
5007 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5008 ArrayRef<int> Mask, MVT VT) {
5009 if (!VT.is128BitVector())
5012 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5014 // Is V2 is a vector load, don't do this transformation. We will try to use
5015 // load folding shufps op.
5016 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5019 unsigned NumElems = VT.getVectorNumElements();
5021 if (NumElems != 2 && NumElems != 4)
5023 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i))
5026 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5027 if (!isUndefOrEqual(Mask[i], i+NumElems))
5032 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5033 /// to an zero vector.
5034 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5035 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5036 SDValue V1 = N->getOperand(0);
5037 SDValue V2 = N->getOperand(1);
5038 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5039 for (unsigned i = 0; i != NumElems; ++i) {
5040 int Idx = N->getMaskElt(i);
5041 if (Idx >= (int)NumElems) {
5042 unsigned Opc = V2.getOpcode();
5043 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5045 if (Opc != ISD::BUILD_VECTOR ||
5046 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5048 } else if (Idx >= 0) {
5049 unsigned Opc = V1.getOpcode();
5050 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5052 if (Opc != ISD::BUILD_VECTOR ||
5053 !X86::isZeroNode(V1.getOperand(Idx)))
5060 /// getZeroVector - Returns a vector of specified type with all zero elements.
5062 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5063 SelectionDAG &DAG, SDLoc dl) {
5064 assert(VT.isVector() && "Expected a vector type");
5066 // Always build SSE zero vectors as <4 x i32> bitcasted
5067 // to their dest type. This ensures they get CSE'd.
5069 if (VT.is128BitVector()) { // SSE
5070 if (Subtarget->hasSSE2()) { // SSE2
5071 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5074 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5077 } else if (VT.is256BitVector()) { // AVX
5078 if (Subtarget->hasInt256()) { // AVX2
5079 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5080 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5081 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5083 // 256-bit logic and arithmetic instructions in AVX are all
5084 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5085 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5086 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5087 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5089 } else if (VT.is512BitVector()) { // AVX-512
5090 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5091 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5092 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5094 } else if (VT.getScalarType() == MVT::i1) {
5095 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5096 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5097 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5098 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5100 llvm_unreachable("Unexpected vector type");
5102 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5105 /// getOnesVector - Returns a vector of specified type with all bits set.
5106 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5107 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5108 /// Then bitcast to their original type, ensuring they get CSE'd.
5109 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5111 assert(VT.isVector() && "Expected a vector type");
5113 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5115 if (VT.is256BitVector()) {
5116 if (HasInt256) { // AVX2
5117 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5121 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5123 } else if (VT.is128BitVector()) {
5124 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5126 llvm_unreachable("Unexpected vector type");
5128 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5131 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5132 /// that point to V2 points to its first element.
5133 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5134 for (unsigned i = 0; i != NumElems; ++i) {
5135 if (Mask[i] > (int)NumElems) {
5141 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5142 /// operation of specified width.
5143 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5145 unsigned NumElems = VT.getVectorNumElements();
5146 SmallVector<int, 8> Mask;
5147 Mask.push_back(NumElems);
5148 for (unsigned i = 1; i != NumElems; ++i)
5150 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5153 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5154 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5156 unsigned NumElems = VT.getVectorNumElements();
5157 SmallVector<int, 8> Mask;
5158 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5160 Mask.push_back(i + NumElems);
5162 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5165 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5166 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5168 unsigned NumElems = VT.getVectorNumElements();
5169 SmallVector<int, 8> Mask;
5170 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5171 Mask.push_back(i + Half);
5172 Mask.push_back(i + NumElems + Half);
5174 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5177 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5178 // a generic shuffle instruction because the target has no such instructions.
5179 // Generate shuffles which repeat i16 and i8 several times until they can be
5180 // represented by v4f32 and then be manipulated by target suported shuffles.
5181 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5182 MVT VT = V.getSimpleValueType();
5183 int NumElems = VT.getVectorNumElements();
5186 while (NumElems > 4) {
5187 if (EltNo < NumElems/2) {
5188 V = getUnpackl(DAG, dl, VT, V, V);
5190 V = getUnpackh(DAG, dl, VT, V, V);
5191 EltNo -= NumElems/2;
5198 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5199 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5200 MVT VT = V.getSimpleValueType();
5203 if (VT.is128BitVector()) {
5204 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5205 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5206 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5208 } else if (VT.is256BitVector()) {
5209 // To use VPERMILPS to splat scalars, the second half of indicies must
5210 // refer to the higher part, which is a duplication of the lower one,
5211 // because VPERMILPS can only handle in-lane permutations.
5212 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5213 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5215 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5216 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5219 llvm_unreachable("Vector size not supported");
5221 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5224 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5225 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5226 MVT SrcVT = SV->getSimpleValueType(0);
5227 SDValue V1 = SV->getOperand(0);
5230 int EltNo = SV->getSplatIndex();
5231 int NumElems = SrcVT.getVectorNumElements();
5232 bool Is256BitVec = SrcVT.is256BitVector();
5234 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5235 "Unknown how to promote splat for type");
5237 // Extract the 128-bit part containing the splat element and update
5238 // the splat element index when it refers to the higher register.
5240 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5241 if (EltNo >= NumElems/2)
5242 EltNo -= NumElems/2;
5245 // All i16 and i8 vector types can't be used directly by a generic shuffle
5246 // instruction because the target has no such instruction. Generate shuffles
5247 // which repeat i16 and i8 several times until they fit in i32, and then can
5248 // be manipulated by target suported shuffles.
5249 MVT EltVT = SrcVT.getVectorElementType();
5250 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5251 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5253 // Recreate the 256-bit vector and place the same 128-bit vector
5254 // into the low and high part. This is necessary because we want
5255 // to use VPERM* to shuffle the vectors
5257 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5260 return getLegalSplat(DAG, V1, EltNo);
5263 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5264 /// vector of zero or undef vector. This produces a shuffle where the low
5265 /// element of V2 is swizzled into the zero/undef vector, landing at element
5266 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5267 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5269 const X86Subtarget *Subtarget,
5270 SelectionDAG &DAG) {
5271 MVT VT = V2.getSimpleValueType();
5273 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5274 unsigned NumElems = VT.getVectorNumElements();
5275 SmallVector<int, 16> MaskVec;
5276 for (unsigned i = 0; i != NumElems; ++i)
5277 // If this is the insertion idx, put the low elt of V2 here.
5278 MaskVec.push_back(i == Idx ? NumElems : i);
5279 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5282 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5283 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5284 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5285 /// shuffles which use a single input multiple times, and in those cases it will
5286 /// adjust the mask to only have indices within that single input.
5287 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5288 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5289 unsigned NumElems = VT.getVectorNumElements();
5293 bool IsFakeUnary = false;
5294 switch(N->getOpcode()) {
5295 case X86ISD::BLENDI:
5296 ImmN = N->getOperand(N->getNumOperands()-1);
5297 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 ImmN = N->getOperand(N->getNumOperands()-1);
5301 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::UNPCKH:
5305 DecodeUNPCKHMask(VT, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::UNPCKL:
5309 DecodeUNPCKLMask(VT, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::MOVHLPS:
5313 DecodeMOVHLPSMask(NumElems, Mask);
5314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 case X86ISD::MOVLHPS:
5317 DecodeMOVLHPSMask(NumElems, Mask);
5318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5320 case X86ISD::PALIGNR:
5321 ImmN = N->getOperand(N->getNumOperands()-1);
5322 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5324 case X86ISD::PSHUFD:
5325 case X86ISD::VPERMILPI:
5326 ImmN = N->getOperand(N->getNumOperands()-1);
5327 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5330 case X86ISD::PSHUFHW:
5331 ImmN = N->getOperand(N->getNumOperands()-1);
5332 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5335 case X86ISD::PSHUFLW:
5336 ImmN = N->getOperand(N->getNumOperands()-1);
5337 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5340 case X86ISD::PSHUFB: {
5342 SDValue MaskNode = N->getOperand(1);
5343 while (MaskNode->getOpcode() == ISD::BITCAST)
5344 MaskNode = MaskNode->getOperand(0);
5346 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5347 // If we have a build-vector, then things are easy.
5348 EVT VT = MaskNode.getValueType();
5349 assert(VT.isVector() &&
5350 "Can't produce a non-vector with a build_vector!");
5351 if (!VT.isInteger())
5354 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5356 SmallVector<uint64_t, 32> RawMask;
5357 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5358 SDValue Op = MaskNode->getOperand(i);
5359 if (Op->getOpcode() == ISD::UNDEF) {
5360 RawMask.push_back((uint64_t)SM_SentinelUndef);
5363 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5366 APInt MaskElement = CN->getAPIntValue();
5368 // We now have to decode the element which could be any integer size and
5369 // extract each byte of it.
5370 for (int j = 0; j < NumBytesPerElement; ++j) {
5371 // Note that this is x86 and so always little endian: the low byte is
5372 // the first byte of the mask.
5373 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5374 MaskElement = MaskElement.lshr(8);
5377 DecodePSHUFBMask(RawMask, Mask);
5381 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5385 SDValue Ptr = MaskLoad->getBasePtr();
5386 if (Ptr->getOpcode() == X86ISD::Wrapper)
5387 Ptr = Ptr->getOperand(0);
5389 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5390 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5393 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5394 // FIXME: Support AVX-512 here.
5395 Type *Ty = C->getType();
5396 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5397 Ty->getVectorNumElements() != 32))
5400 DecodePSHUFBMask(C, Mask);
5406 case X86ISD::VPERMI:
5407 ImmN = N->getOperand(N->getNumOperands()-1);
5408 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 case X86ISD::MOVSD: {
5413 // The index 0 always comes from the first element of the second source,
5414 // this is why MOVSS and MOVSD are used in the first place. The other
5415 // elements come from the other positions of the first source vector
5416 Mask.push_back(NumElems);
5417 for (unsigned i = 1; i != NumElems; ++i) {
5422 case X86ISD::VPERM2X128:
5423 ImmN = N->getOperand(N->getNumOperands()-1);
5424 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5425 if (Mask.empty()) return false;
5427 case X86ISD::MOVSLDUP:
5428 DecodeMOVSLDUPMask(VT, Mask);
5430 case X86ISD::MOVSHDUP:
5431 DecodeMOVSHDUPMask(VT, Mask);
5433 case X86ISD::MOVDDUP:
5434 case X86ISD::MOVLHPD:
5435 case X86ISD::MOVLPD:
5436 case X86ISD::MOVLPS:
5437 // Not yet implemented
5439 default: llvm_unreachable("unknown target shuffle node");
5442 // If we have a fake unary shuffle, the shuffle mask is spread across two
5443 // inputs that are actually the same node. Re-map the mask to always point
5444 // into the first input.
5447 if (M >= (int)Mask.size())
5453 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5454 /// element of the result of the vector shuffle.
5455 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5458 return SDValue(); // Limit search depth.
5460 SDValue V = SDValue(N, 0);
5461 EVT VT = V.getValueType();
5462 unsigned Opcode = V.getOpcode();
5464 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5465 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5466 int Elt = SV->getMaskElt(Index);
5469 return DAG.getUNDEF(VT.getVectorElementType());
5471 unsigned NumElems = VT.getVectorNumElements();
5472 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5473 : SV->getOperand(1);
5474 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5477 // Recurse into target specific vector shuffles to find scalars.
5478 if (isTargetShuffle(Opcode)) {
5479 MVT ShufVT = V.getSimpleValueType();
5480 unsigned NumElems = ShufVT.getVectorNumElements();
5481 SmallVector<int, 16> ShuffleMask;
5484 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5487 int Elt = ShuffleMask[Index];
5489 return DAG.getUNDEF(ShufVT.getVectorElementType());
5491 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5493 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5497 // Actual nodes that may contain scalar elements
5498 if (Opcode == ISD::BITCAST) {
5499 V = V.getOperand(0);
5500 EVT SrcVT = V.getValueType();
5501 unsigned NumElems = VT.getVectorNumElements();
5503 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5507 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5508 return (Index == 0) ? V.getOperand(0)
5509 : DAG.getUNDEF(VT.getVectorElementType());
5511 if (V.getOpcode() == ISD::BUILD_VECTOR)
5512 return V.getOperand(Index);
5517 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5518 /// shuffle operation which come from a consecutively from a zero. The
5519 /// search can start in two different directions, from left or right.
5520 /// We count undefs as zeros until PreferredNum is reached.
5521 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5522 unsigned NumElems, bool ZerosFromLeft,
5524 unsigned PreferredNum = -1U) {
5525 unsigned NumZeros = 0;
5526 for (unsigned i = 0; i != NumElems; ++i) {
5527 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5528 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5532 if (X86::isZeroNode(Elt))
5534 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5535 NumZeros = std::min(NumZeros + 1, PreferredNum);
5543 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5544 /// correspond consecutively to elements from one of the vector operands,
5545 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5547 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5548 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5549 unsigned NumElems, unsigned &OpNum) {
5550 bool SeenV1 = false;
5551 bool SeenV2 = false;
5553 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5554 int Idx = SVOp->getMaskElt(i);
5555 // Ignore undef indicies
5559 if (Idx < (int)NumElems)
5564 // Only accept consecutive elements from the same vector
5565 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5569 OpNum = SeenV1 ? 0 : 1;
5573 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5574 /// logical left shift of a vector.
5575 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5576 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5578 SVOp->getSimpleValueType(0).getVectorNumElements();
5579 unsigned NumZeros = getNumOfConsecutiveZeros(
5580 SVOp, NumElems, false /* check zeros from right */, DAG,
5581 SVOp->getMaskElt(0));
5587 // Considering the elements in the mask that are not consecutive zeros,
5588 // check if they consecutively come from only one of the source vectors.
5590 // V1 = {X, A, B, C} 0
5592 // vector_shuffle V1, V2 <1, 2, 3, X>
5594 if (!isShuffleMaskConsecutive(SVOp,
5595 0, // Mask Start Index
5596 NumElems-NumZeros, // Mask End Index(exclusive)
5597 NumZeros, // Where to start looking in the src vector
5598 NumElems, // Number of elements in vector
5599 OpSrc)) // Which source operand ?
5604 ShVal = SVOp->getOperand(OpSrc);
5608 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5609 /// logical left shift of a vector.
5610 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5611 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5613 SVOp->getSimpleValueType(0).getVectorNumElements();
5614 unsigned NumZeros = getNumOfConsecutiveZeros(
5615 SVOp, NumElems, true /* check zeros from left */, DAG,
5616 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5622 // Considering the elements in the mask that are not consecutive zeros,
5623 // check if they consecutively come from only one of the source vectors.
5625 // 0 { A, B, X, X } = V2
5627 // vector_shuffle V1, V2 <X, X, 4, 5>
5629 if (!isShuffleMaskConsecutive(SVOp,
5630 NumZeros, // Mask Start Index
5631 NumElems, // Mask End Index(exclusive)
5632 0, // Where to start looking in the src vector
5633 NumElems, // Number of elements in vector
5634 OpSrc)) // Which source operand ?
5639 ShVal = SVOp->getOperand(OpSrc);
5643 /// isVectorShift - Returns true if the shuffle can be implemented as a
5644 /// logical left or right shift of a vector.
5645 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5646 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5647 // Although the logic below support any bitwidth size, there are no
5648 // shift instructions which handle more than 128-bit vectors.
5649 if (!SVOp->getSimpleValueType(0).is128BitVector())
5652 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5653 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5659 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5661 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5662 unsigned NumNonZero, unsigned NumZero,
5664 const X86Subtarget* Subtarget,
5665 const TargetLowering &TLI) {
5672 for (unsigned i = 0; i < 16; ++i) {
5673 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5674 if (ThisIsNonZero && First) {
5676 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5678 V = DAG.getUNDEF(MVT::v8i16);
5683 SDValue ThisElt, LastElt;
5684 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5685 if (LastIsNonZero) {
5686 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5687 MVT::i16, Op.getOperand(i-1));
5689 if (ThisIsNonZero) {
5690 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5691 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5692 ThisElt, DAG.getConstant(8, MVT::i8));
5694 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5698 if (ThisElt.getNode())
5699 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5700 DAG.getIntPtrConstant(i/2));
5704 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5707 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5709 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5710 unsigned NumNonZero, unsigned NumZero,
5712 const X86Subtarget* Subtarget,
5713 const TargetLowering &TLI) {
5720 for (unsigned i = 0; i < 8; ++i) {
5721 bool isNonZero = (NonZeros & (1 << i)) != 0;
5725 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5727 V = DAG.getUNDEF(MVT::v8i16);
5730 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5731 MVT::v8i16, V, Op.getOperand(i),
5732 DAG.getIntPtrConstant(i));
5739 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5740 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5741 unsigned NonZeros, unsigned NumNonZero,
5742 unsigned NumZero, SelectionDAG &DAG,
5743 const X86Subtarget *Subtarget,
5744 const TargetLowering &TLI) {
5745 // We know there's at least one non-zero element
5746 unsigned FirstNonZeroIdx = 0;
5747 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5748 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5749 X86::isZeroNode(FirstNonZero)) {
5751 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5754 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5755 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5758 SDValue V = FirstNonZero.getOperand(0);
5759 MVT VVT = V.getSimpleValueType();
5760 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5763 unsigned FirstNonZeroDst =
5764 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5765 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5766 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5767 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5769 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5770 SDValue Elem = Op.getOperand(Idx);
5771 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5774 // TODO: What else can be here? Deal with it.
5775 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5778 // TODO: Some optimizations are still possible here
5779 // ex: Getting one element from a vector, and the rest from another.
5780 if (Elem.getOperand(0) != V)
5783 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5786 else if (IncorrectIdx == -1U) {
5790 // There was already one element with an incorrect index.
5791 // We can't optimize this case to an insertps.
5795 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5797 EVT VT = Op.getSimpleValueType();
5798 unsigned ElementMoveMask = 0;
5799 if (IncorrectIdx == -1U)
5800 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5802 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5804 SDValue InsertpsMask =
5805 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5806 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5812 /// getVShift - Return a vector logical shift node.
5814 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5815 unsigned NumBits, SelectionDAG &DAG,
5816 const TargetLowering &TLI, SDLoc dl) {
5817 assert(VT.is128BitVector() && "Unknown type for VShift");
5818 EVT ShVT = MVT::v2i64;
5819 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5820 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5821 return DAG.getNode(ISD::BITCAST, dl, VT,
5822 DAG.getNode(Opc, dl, ShVT, SrcOp,
5823 DAG.getConstant(NumBits,
5824 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5828 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5830 // Check if the scalar load can be widened into a vector load. And if
5831 // the address is "base + cst" see if the cst can be "absorbed" into
5832 // the shuffle mask.
5833 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5834 SDValue Ptr = LD->getBasePtr();
5835 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5837 EVT PVT = LD->getValueType(0);
5838 if (PVT != MVT::i32 && PVT != MVT::f32)
5843 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5844 FI = FINode->getIndex();
5846 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5847 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5848 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5849 Offset = Ptr.getConstantOperandVal(1);
5850 Ptr = Ptr.getOperand(0);
5855 // FIXME: 256-bit vector instructions don't require a strict alignment,
5856 // improve this code to support it better.
5857 unsigned RequiredAlign = VT.getSizeInBits()/8;
5858 SDValue Chain = LD->getChain();
5859 // Make sure the stack object alignment is at least 16 or 32.
5860 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5861 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5862 if (MFI->isFixedObjectIndex(FI)) {
5863 // Can't change the alignment. FIXME: It's possible to compute
5864 // the exact stack offset and reference FI + adjust offset instead.
5865 // If someone *really* cares about this. That's the way to implement it.
5868 MFI->setObjectAlignment(FI, RequiredAlign);
5872 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5873 // Ptr + (Offset & ~15).
5876 if ((Offset % RequiredAlign) & 3)
5878 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5880 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5881 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5883 int EltNo = (Offset - StartOffset) >> 2;
5884 unsigned NumElems = VT.getVectorNumElements();
5886 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5887 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5888 LD->getPointerInfo().getWithOffset(StartOffset),
5889 false, false, false, 0);
5891 SmallVector<int, 8> Mask;
5892 for (unsigned i = 0; i != NumElems; ++i)
5893 Mask.push_back(EltNo);
5895 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5901 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5902 /// vector of type 'VT', see if the elements can be replaced by a single large
5903 /// load which has the same value as a build_vector whose operands are 'elts'.
5905 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5907 /// FIXME: we'd also like to handle the case where the last elements are zero
5908 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5909 /// There's even a handy isZeroNode for that purpose.
5910 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5911 SDLoc &DL, SelectionDAG &DAG,
5912 bool isAfterLegalize) {
5913 EVT EltVT = VT.getVectorElementType();
5914 unsigned NumElems = Elts.size();
5916 LoadSDNode *LDBase = nullptr;
5917 unsigned LastLoadedElt = -1U;
5919 // For each element in the initializer, see if we've found a load or an undef.
5920 // If we don't find an initial load element, or later load elements are
5921 // non-consecutive, bail out.
5922 for (unsigned i = 0; i < NumElems; ++i) {
5923 SDValue Elt = Elts[i];
5925 if (!Elt.getNode() ||
5926 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5929 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5931 LDBase = cast<LoadSDNode>(Elt.getNode());
5935 if (Elt.getOpcode() == ISD::UNDEF)
5938 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5939 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5944 // If we have found an entire vector of loads and undefs, then return a large
5945 // load of the entire vector width starting at the base pointer. If we found
5946 // consecutive loads for the low half, generate a vzext_load node.
5947 if (LastLoadedElt == NumElems - 1) {
5949 if (isAfterLegalize &&
5950 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5953 SDValue NewLd = SDValue();
5955 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5956 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5957 LDBase->getPointerInfo(),
5958 LDBase->isVolatile(), LDBase->isNonTemporal(),
5959 LDBase->isInvariant(), 0);
5960 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5961 LDBase->getPointerInfo(),
5962 LDBase->isVolatile(), LDBase->isNonTemporal(),
5963 LDBase->isInvariant(), LDBase->getAlignment());
5965 if (LDBase->hasAnyUseOfValue(1)) {
5966 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5968 SDValue(NewLd.getNode(), 1));
5969 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5970 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5971 SDValue(NewLd.getNode(), 1));
5976 if (NumElems == 4 && LastLoadedElt == 1 &&
5977 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5978 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5979 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5981 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5982 LDBase->getPointerInfo(),
5983 LDBase->getAlignment(),
5984 false/*isVolatile*/, true/*ReadMem*/,
5987 // Make sure the newly-created LOAD is in the same position as LDBase in
5988 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5989 // update uses of LDBase's output chain to use the TokenFactor.
5990 if (LDBase->hasAnyUseOfValue(1)) {
5991 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5992 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5993 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5994 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5995 SDValue(ResNode.getNode(), 1));
5998 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6003 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6004 /// to generate a splat value for the following cases:
6005 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6006 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6007 /// a scalar load, or a constant.
6008 /// The VBROADCAST node is returned when a pattern is found,
6009 /// or SDValue() otherwise.
6010 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6011 SelectionDAG &DAG) {
6012 // VBROADCAST requires AVX.
6013 // TODO: Splats could be generated for non-AVX CPUs using SSE
6014 // instructions, but there's less potential gain for only 128-bit vectors.
6015 if (!Subtarget->hasAVX())
6018 MVT VT = Op.getSimpleValueType();
6021 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6022 "Unsupported vector type for broadcast.");
6027 switch (Op.getOpcode()) {
6029 // Unknown pattern found.
6032 case ISD::BUILD_VECTOR: {
6033 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6034 BitVector UndefElements;
6035 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6037 // We need a splat of a single value to use broadcast, and it doesn't
6038 // make any sense if the value is only in one element of the vector.
6039 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6043 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6044 Ld.getOpcode() == ISD::ConstantFP);
6046 // Make sure that all of the users of a non-constant load are from the
6047 // BUILD_VECTOR node.
6048 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6053 case ISD::VECTOR_SHUFFLE: {
6054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6056 // Shuffles must have a splat mask where the first element is
6058 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6061 SDValue Sc = Op.getOperand(0);
6062 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6063 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6065 if (!Subtarget->hasInt256())
6068 // Use the register form of the broadcast instruction available on AVX2.
6069 if (VT.getSizeInBits() >= 256)
6070 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6071 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6074 Ld = Sc.getOperand(0);
6075 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6076 Ld.getOpcode() == ISD::ConstantFP);
6078 // The scalar_to_vector node and the suspected
6079 // load node must have exactly one user.
6080 // Constants may have multiple users.
6082 // AVX-512 has register version of the broadcast
6083 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6084 Ld.getValueType().getSizeInBits() >= 32;
6085 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6092 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6093 bool IsGE256 = (VT.getSizeInBits() >= 256);
6095 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6096 // instruction to save 8 or more bytes of constant pool data.
6097 // TODO: If multiple splats are generated to load the same constant,
6098 // it may be detrimental to overall size. There needs to be a way to detect
6099 // that condition to know if this is truly a size win.
6100 const Function *F = DAG.getMachineFunction().getFunction();
6101 bool OptForSize = F->getAttributes().
6102 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6104 // Handle broadcasting a single constant scalar from the constant pool
6106 // On Sandybridge (no AVX2), it is still better to load a constant vector
6107 // from the constant pool and not to broadcast it from a scalar.
6108 // But override that restriction when optimizing for size.
6109 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6110 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6111 EVT CVT = Ld.getValueType();
6112 assert(!CVT.isVector() && "Must not broadcast a vector type");
6114 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6115 // For size optimization, also splat v2f64 and v2i64, and for size opt
6116 // with AVX2, also splat i8 and i16.
6117 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6118 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6119 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6120 const Constant *C = nullptr;
6121 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6122 C = CI->getConstantIntValue();
6123 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6124 C = CF->getConstantFPValue();
6126 assert(C && "Invalid constant type");
6128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6129 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6130 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6131 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6132 MachinePointerInfo::getConstantPool(),
6133 false, false, false, Alignment);
6135 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6139 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6141 // Handle AVX2 in-register broadcasts.
6142 if (!IsLoad && Subtarget->hasInt256() &&
6143 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6144 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6146 // The scalar source must be a normal load.
6150 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6151 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6153 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6154 // double since there is no vbroadcastsd xmm
6155 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6156 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6157 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6160 // Unsupported broadcast.
6164 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6165 /// underlying vector and index.
6167 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6169 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6171 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6172 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6175 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6177 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6179 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6180 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6183 // In this case the vector is the extract_subvector expression and the index
6184 // is 2, as specified by the shuffle.
6185 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6186 SDValue ShuffleVec = SVOp->getOperand(0);
6187 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6188 assert(ShuffleVecVT.getVectorElementType() ==
6189 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6191 int ShuffleIdx = SVOp->getMaskElt(Idx);
6192 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6193 ExtractedFromVec = ShuffleVec;
6199 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6200 MVT VT = Op.getSimpleValueType();
6202 // Skip if insert_vec_elt is not supported.
6203 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6204 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6208 unsigned NumElems = Op.getNumOperands();
6212 SmallVector<unsigned, 4> InsertIndices;
6213 SmallVector<int, 8> Mask(NumElems, -1);
6215 for (unsigned i = 0; i != NumElems; ++i) {
6216 unsigned Opc = Op.getOperand(i).getOpcode();
6218 if (Opc == ISD::UNDEF)
6221 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6222 // Quit if more than 1 elements need inserting.
6223 if (InsertIndices.size() > 1)
6226 InsertIndices.push_back(i);
6230 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6231 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6232 // Quit if non-constant index.
6233 if (!isa<ConstantSDNode>(ExtIdx))
6235 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6237 // Quit if extracted from vector of different type.
6238 if (ExtractedFromVec.getValueType() != VT)
6241 if (!VecIn1.getNode())
6242 VecIn1 = ExtractedFromVec;
6243 else if (VecIn1 != ExtractedFromVec) {
6244 if (!VecIn2.getNode())
6245 VecIn2 = ExtractedFromVec;
6246 else if (VecIn2 != ExtractedFromVec)
6247 // Quit if more than 2 vectors to shuffle
6251 if (ExtractedFromVec == VecIn1)
6253 else if (ExtractedFromVec == VecIn2)
6254 Mask[i] = Idx + NumElems;
6257 if (!VecIn1.getNode())
6260 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6261 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6262 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6263 unsigned Idx = InsertIndices[i];
6264 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6265 DAG.getIntPtrConstant(Idx));
6271 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6273 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6275 MVT VT = Op.getSimpleValueType();
6276 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6277 "Unexpected type in LowerBUILD_VECTORvXi1!");
6280 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6281 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6282 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6283 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6286 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6287 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6288 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6289 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6292 bool AllContants = true;
6293 uint64_t Immediate = 0;
6294 int NonConstIdx = -1;
6295 bool IsSplat = true;
6296 unsigned NumNonConsts = 0;
6297 unsigned NumConsts = 0;
6298 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6299 SDValue In = Op.getOperand(idx);
6300 if (In.getOpcode() == ISD::UNDEF)
6302 if (!isa<ConstantSDNode>(In)) {
6303 AllContants = false;
6309 if (cast<ConstantSDNode>(In)->getZExtValue())
6310 Immediate |= (1ULL << idx);
6312 if (In != Op.getOperand(0))
6317 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6318 DAG.getConstant(Immediate, MVT::i16));
6319 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6320 DAG.getIntPtrConstant(0));
6323 if (NumNonConsts == 1 && NonConstIdx != 0) {
6326 SDValue VecAsImm = DAG.getConstant(Immediate,
6327 MVT::getIntegerVT(VT.getSizeInBits()));
6328 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6331 DstVec = DAG.getUNDEF(VT);
6332 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6333 Op.getOperand(NonConstIdx),
6334 DAG.getIntPtrConstant(NonConstIdx));
6336 if (!IsSplat && (NonConstIdx != 0))
6337 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6338 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6341 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6342 DAG.getConstant(-1, SelectVT),
6343 DAG.getConstant(0, SelectVT));
6345 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6346 DAG.getConstant((Immediate | 1), SelectVT),
6347 DAG.getConstant(Immediate, SelectVT));
6348 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6351 /// \brief Return true if \p N implements a horizontal binop and return the
6352 /// operands for the horizontal binop into V0 and V1.
6354 /// This is a helper function of PerformBUILD_VECTORCombine.
6355 /// This function checks that the build_vector \p N in input implements a
6356 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6357 /// operation to match.
6358 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6359 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6360 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6363 /// This function only analyzes elements of \p N whose indices are
6364 /// in range [BaseIdx, LastIdx).
6365 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6367 unsigned BaseIdx, unsigned LastIdx,
6368 SDValue &V0, SDValue &V1) {
6369 EVT VT = N->getValueType(0);
6371 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6372 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6373 "Invalid Vector in input!");
6375 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6376 bool CanFold = true;
6377 unsigned ExpectedVExtractIdx = BaseIdx;
6378 unsigned NumElts = LastIdx - BaseIdx;
6379 V0 = DAG.getUNDEF(VT);
6380 V1 = DAG.getUNDEF(VT);
6382 // Check if N implements a horizontal binop.
6383 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6384 SDValue Op = N->getOperand(i + BaseIdx);
6387 if (Op->getOpcode() == ISD::UNDEF) {
6388 // Update the expected vector extract index.
6389 if (i * 2 == NumElts)
6390 ExpectedVExtractIdx = BaseIdx;
6391 ExpectedVExtractIdx += 2;
6395 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6400 SDValue Op0 = Op.getOperand(0);
6401 SDValue Op1 = Op.getOperand(1);
6403 // Try to match the following pattern:
6404 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6405 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6406 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6407 Op0.getOperand(0) == Op1.getOperand(0) &&
6408 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6409 isa<ConstantSDNode>(Op1.getOperand(1)));
6413 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6414 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6416 if (i * 2 < NumElts) {
6417 if (V0.getOpcode() == ISD::UNDEF)
6418 V0 = Op0.getOperand(0);
6420 if (V1.getOpcode() == ISD::UNDEF)
6421 V1 = Op0.getOperand(0);
6422 if (i * 2 == NumElts)
6423 ExpectedVExtractIdx = BaseIdx;
6426 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6427 if (I0 == ExpectedVExtractIdx)
6428 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6429 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6430 // Try to match the following dag sequence:
6431 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6432 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6436 ExpectedVExtractIdx += 2;
6442 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6443 /// a concat_vector.
6445 /// This is a helper function of PerformBUILD_VECTORCombine.
6446 /// This function expects two 256-bit vectors called V0 and V1.
6447 /// At first, each vector is split into two separate 128-bit vectors.
6448 /// Then, the resulting 128-bit vectors are used to implement two
6449 /// horizontal binary operations.
6451 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6453 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6454 /// the two new horizontal binop.
6455 /// When Mode is set, the first horizontal binop dag node would take as input
6456 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6457 /// horizontal binop dag node would take as input the lower 128-bit of V1
6458 /// and the upper 128-bit of V1.
6460 /// HADD V0_LO, V0_HI
6461 /// HADD V1_LO, V1_HI
6463 /// Otherwise, the first horizontal binop dag node takes as input the lower
6464 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6465 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6467 /// HADD V0_LO, V1_LO
6468 /// HADD V0_HI, V1_HI
6470 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6471 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6472 /// the upper 128-bits of the result.
6473 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6474 SDLoc DL, SelectionDAG &DAG,
6475 unsigned X86Opcode, bool Mode,
6476 bool isUndefLO, bool isUndefHI) {
6477 EVT VT = V0.getValueType();
6478 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6479 "Invalid nodes in input!");
6481 unsigned NumElts = VT.getVectorNumElements();
6482 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6483 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6484 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6485 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6486 EVT NewVT = V0_LO.getValueType();
6488 SDValue LO = DAG.getUNDEF(NewVT);
6489 SDValue HI = DAG.getUNDEF(NewVT);
6492 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6493 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6494 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6495 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6496 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6498 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6499 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6500 V1_LO->getOpcode() != ISD::UNDEF))
6501 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6503 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6504 V1_HI->getOpcode() != ISD::UNDEF))
6505 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6508 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6511 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6512 /// sequence of 'vadd + vsub + blendi'.
6513 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6514 const X86Subtarget *Subtarget) {
6516 EVT VT = BV->getValueType(0);
6517 unsigned NumElts = VT.getVectorNumElements();
6518 SDValue InVec0 = DAG.getUNDEF(VT);
6519 SDValue InVec1 = DAG.getUNDEF(VT);
6521 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6522 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6524 // Odd-numbered elements in the input build vector are obtained from
6525 // adding two integer/float elements.
6526 // Even-numbered elements in the input build vector are obtained from
6527 // subtracting two integer/float elements.
6528 unsigned ExpectedOpcode = ISD::FSUB;
6529 unsigned NextExpectedOpcode = ISD::FADD;
6530 bool AddFound = false;
6531 bool SubFound = false;
6533 for (unsigned i = 0, e = NumElts; i != e; i++) {
6534 SDValue Op = BV->getOperand(i);
6536 // Skip 'undef' values.
6537 unsigned Opcode = Op.getOpcode();
6538 if (Opcode == ISD::UNDEF) {
6539 std::swap(ExpectedOpcode, NextExpectedOpcode);
6543 // Early exit if we found an unexpected opcode.
6544 if (Opcode != ExpectedOpcode)
6547 SDValue Op0 = Op.getOperand(0);
6548 SDValue Op1 = Op.getOperand(1);
6550 // Try to match the following pattern:
6551 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6552 // Early exit if we cannot match that sequence.
6553 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6554 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6555 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6556 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6557 Op0.getOperand(1) != Op1.getOperand(1))
6560 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6564 // We found a valid add/sub node. Update the information accordingly.
6570 // Update InVec0 and InVec1.
6571 if (InVec0.getOpcode() == ISD::UNDEF)
6572 InVec0 = Op0.getOperand(0);
6573 if (InVec1.getOpcode() == ISD::UNDEF)
6574 InVec1 = Op1.getOperand(0);
6576 // Make sure that operands in input to each add/sub node always
6577 // come from a same pair of vectors.
6578 if (InVec0 != Op0.getOperand(0)) {
6579 if (ExpectedOpcode == ISD::FSUB)
6582 // FADD is commutable. Try to commute the operands
6583 // and then test again.
6584 std::swap(Op0, Op1);
6585 if (InVec0 != Op0.getOperand(0))
6589 if (InVec1 != Op1.getOperand(0))
6592 // Update the pair of expected opcodes.
6593 std::swap(ExpectedOpcode, NextExpectedOpcode);
6596 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6597 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6598 InVec1.getOpcode() != ISD::UNDEF)
6599 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6604 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6605 const X86Subtarget *Subtarget) {
6607 EVT VT = N->getValueType(0);
6608 unsigned NumElts = VT.getVectorNumElements();
6609 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6610 SDValue InVec0, InVec1;
6612 // Try to match an ADDSUB.
6613 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6614 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6615 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6616 if (Value.getNode())
6620 // Try to match horizontal ADD/SUB.
6621 unsigned NumUndefsLO = 0;
6622 unsigned NumUndefsHI = 0;
6623 unsigned Half = NumElts/2;
6625 // Count the number of UNDEF operands in the build_vector in input.
6626 for (unsigned i = 0, e = Half; i != e; ++i)
6627 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6630 for (unsigned i = Half, e = NumElts; i != e; ++i)
6631 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6634 // Early exit if this is either a build_vector of all UNDEFs or all the
6635 // operands but one are UNDEF.
6636 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6639 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6640 // Try to match an SSE3 float HADD/HSUB.
6641 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6644 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6645 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6646 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6647 // Try to match an SSSE3 integer HADD/HSUB.
6648 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6651 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6652 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6655 if (!Subtarget->hasAVX())
6658 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6659 // Try to match an AVX horizontal add/sub of packed single/double
6660 // precision floating point values from 256-bit vectors.
6661 SDValue InVec2, InVec3;
6662 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6663 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6664 ((InVec0.getOpcode() == ISD::UNDEF ||
6665 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6666 ((InVec1.getOpcode() == ISD::UNDEF ||
6667 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6668 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6670 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6671 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6672 ((InVec0.getOpcode() == ISD::UNDEF ||
6673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6674 ((InVec1.getOpcode() == ISD::UNDEF ||
6675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6676 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6677 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6678 // Try to match an AVX2 horizontal add/sub of signed integers.
6679 SDValue InVec2, InVec3;
6681 bool CanFold = true;
6683 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6684 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6685 ((InVec0.getOpcode() == ISD::UNDEF ||
6686 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6687 ((InVec1.getOpcode() == ISD::UNDEF ||
6688 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6689 X86Opcode = X86ISD::HADD;
6690 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6691 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6692 ((InVec0.getOpcode() == ISD::UNDEF ||
6693 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6694 ((InVec1.getOpcode() == ISD::UNDEF ||
6695 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6696 X86Opcode = X86ISD::HSUB;
6701 // Fold this build_vector into a single horizontal add/sub.
6702 // Do this only if the target has AVX2.
6703 if (Subtarget->hasAVX2())
6704 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6706 // Do not try to expand this build_vector into a pair of horizontal
6707 // add/sub if we can emit a pair of scalar add/sub.
6708 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6711 // Convert this build_vector into a pair of horizontal binop followed by
6713 bool isUndefLO = NumUndefsLO == Half;
6714 bool isUndefHI = NumUndefsHI == Half;
6715 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6716 isUndefLO, isUndefHI);
6720 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6721 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6723 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HADD;
6725 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::HSUB;
6727 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHADD;
6729 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6730 X86Opcode = X86ISD::FHSUB;
6734 // Don't try to expand this build_vector into a pair of horizontal add/sub
6735 // if we can simply emit a pair of scalar add/sub.
6736 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6739 // Convert this build_vector into two horizontal add/sub followed by
6741 bool isUndefLO = NumUndefsLO == Half;
6742 bool isUndefHI = NumUndefsHI == Half;
6743 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6744 isUndefLO, isUndefHI);
6751 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6754 MVT VT = Op.getSimpleValueType();
6755 MVT ExtVT = VT.getVectorElementType();
6756 unsigned NumElems = Op.getNumOperands();
6758 // Generate vectors for predicate vectors.
6759 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6760 return LowerBUILD_VECTORvXi1(Op, DAG);
6762 // Vectors containing all zeros can be matched by pxor and xorps later
6763 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6764 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6765 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6766 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6769 return getZeroVector(VT, Subtarget, DAG, dl);
6772 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6773 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6774 // vpcmpeqd on 256-bit vectors.
6775 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6776 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6779 if (!VT.is512BitVector())
6780 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6783 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6784 if (Broadcast.getNode())
6787 unsigned EVTBits = ExtVT.getSizeInBits();
6789 unsigned NumZero = 0;
6790 unsigned NumNonZero = 0;
6791 unsigned NonZeros = 0;
6792 bool IsAllConstants = true;
6793 SmallSet<SDValue, 8> Values;
6794 for (unsigned i = 0; i < NumElems; ++i) {
6795 SDValue Elt = Op.getOperand(i);
6796 if (Elt.getOpcode() == ISD::UNDEF)
6799 if (Elt.getOpcode() != ISD::Constant &&
6800 Elt.getOpcode() != ISD::ConstantFP)
6801 IsAllConstants = false;
6802 if (X86::isZeroNode(Elt))
6805 NonZeros |= (1 << i);
6810 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6811 if (NumNonZero == 0)
6812 return DAG.getUNDEF(VT);
6814 // Special case for single non-zero, non-undef, element.
6815 if (NumNonZero == 1) {
6816 unsigned Idx = countTrailingZeros(NonZeros);
6817 SDValue Item = Op.getOperand(Idx);
6819 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6820 // the value are obviously zero, truncate the value to i32 and do the
6821 // insertion that way. Only do this if the value is non-constant or if the
6822 // value is a constant being inserted into element 0. It is cheaper to do
6823 // a constant pool load than it is to do a movd + shuffle.
6824 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6825 (!IsAllConstants || Idx == 0)) {
6826 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6828 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6829 EVT VecVT = MVT::v4i32;
6830 unsigned VecElts = 4;
6832 // Truncate the value (which may itself be a constant) to i32, and
6833 // convert it to a vector with movd (S2V+shuffle to zero extend).
6834 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6835 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6837 // If using the new shuffle lowering, just directly insert this.
6838 if (ExperimentalVectorShuffleLowering)
6840 ISD::BITCAST, dl, VT,
6841 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6843 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6845 // Now we have our 32-bit value zero extended in the low element of
6846 // a vector. If Idx != 0, swizzle it into place.
6848 SmallVector<int, 4> Mask;
6849 Mask.push_back(Idx);
6850 for (unsigned i = 1; i != VecElts; ++i)
6852 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6855 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6859 // If we have a constant or non-constant insertion into the low element of
6860 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6861 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6862 // depending on what the source datatype is.
6865 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6867 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6868 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6869 if (VT.is256BitVector() || VT.is512BitVector()) {
6870 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6871 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6872 Item, DAG.getIntPtrConstant(0));
6874 assert(VT.is128BitVector() && "Expected an SSE value type!");
6875 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6876 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6877 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6880 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6881 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6883 if (VT.is256BitVector()) {
6884 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6885 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6887 assert(VT.is128BitVector() && "Expected an SSE value type!");
6888 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6890 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6894 // Is it a vector logical left shift?
6895 if (NumElems == 2 && Idx == 1 &&
6896 X86::isZeroNode(Op.getOperand(0)) &&
6897 !X86::isZeroNode(Op.getOperand(1))) {
6898 unsigned NumBits = VT.getSizeInBits();
6899 return getVShift(true, VT,
6900 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6901 VT, Op.getOperand(1)),
6902 NumBits/2, DAG, *this, dl);
6905 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6908 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6909 // is a non-constant being inserted into an element other than the low one,
6910 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6911 // movd/movss) to move this into the low element, then shuffle it into
6913 if (EVTBits == 32) {
6914 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6916 // If using the new shuffle lowering, just directly insert this.
6917 if (ExperimentalVectorShuffleLowering)
6918 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6920 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6921 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6922 SmallVector<int, 8> MaskVec;
6923 for (unsigned i = 0; i != NumElems; ++i)
6924 MaskVec.push_back(i == Idx ? 0 : 1);
6925 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6929 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6930 if (Values.size() == 1) {
6931 if (EVTBits == 32) {
6932 // Instead of a shuffle like this:
6933 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6934 // Check if it's possible to issue this instead.
6935 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6936 unsigned Idx = countTrailingZeros(NonZeros);
6937 SDValue Item = Op.getOperand(Idx);
6938 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6939 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6944 // A vector full of immediates; various special cases are already
6945 // handled, so this is best done with a single constant-pool load.
6949 // For AVX-length vectors, build the individual 128-bit pieces and use
6950 // shuffles to put them in place.
6951 if (VT.is256BitVector() || VT.is512BitVector()) {
6952 SmallVector<SDValue, 64> V;
6953 for (unsigned i = 0; i != NumElems; ++i)
6954 V.push_back(Op.getOperand(i));
6956 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6958 // Build both the lower and upper subvector.
6959 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[0], NumElems/2));
6961 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6962 makeArrayRef(&V[NumElems / 2], NumElems/2));
6964 // Recreate the wider vector with the lower and upper part.
6965 if (VT.is256BitVector())
6966 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6970 // Let legalizer expand 2-wide build_vectors.
6971 if (EVTBits == 64) {
6972 if (NumNonZero == 1) {
6973 // One half is zero or undef.
6974 unsigned Idx = countTrailingZeros(NonZeros);
6975 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6976 Op.getOperand(Idx));
6977 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6982 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6983 if (EVTBits == 8 && NumElems == 16) {
6984 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6986 if (V.getNode()) return V;
6989 if (EVTBits == 16 && NumElems == 8) {
6990 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6992 if (V.getNode()) return V;
6995 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6996 if (EVTBits == 32 && NumElems == 4) {
6997 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6998 NumZero, DAG, Subtarget, *this);
7003 // If element VT is == 32 bits, turn it into a number of shuffles.
7004 SmallVector<SDValue, 8> V(NumElems);
7005 if (NumElems == 4 && NumZero > 0) {
7006 for (unsigned i = 0; i < 4; ++i) {
7007 bool isZero = !(NonZeros & (1 << i));
7009 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7011 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7014 for (unsigned i = 0; i < 2; ++i) {
7015 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7018 V[i] = V[i*2]; // Must be a zero vector.
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7024 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7027 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7032 bool Reverse1 = (NonZeros & 0x3) == 2;
7033 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7037 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7038 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7040 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7043 if (Values.size() > 1 && VT.is128BitVector()) {
7044 // Check for a build vector of consecutive loads.
7045 for (unsigned i = 0; i < NumElems; ++i)
7046 V[i] = Op.getOperand(i);
7048 // Check for elements which are consecutive loads.
7049 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7053 // Check for a build vector from mostly shuffle plus few inserting.
7054 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7058 // For SSE 4.1, use insertps to put the high elements into the low element.
7059 if (getSubtarget()->hasSSE41()) {
7061 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7062 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7064 Result = DAG.getUNDEF(VT);
7066 for (unsigned i = 1; i < NumElems; ++i) {
7067 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7068 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7069 Op.getOperand(i), DAG.getIntPtrConstant(i));
7074 // Otherwise, expand into a number of unpckl*, start by extending each of
7075 // our (non-undef) elements to the full vector width with the element in the
7076 // bottom slot of the vector (which generates no code for SSE).
7077 for (unsigned i = 0; i < NumElems; ++i) {
7078 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7079 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7081 V[i] = DAG.getUNDEF(VT);
7084 // Next, we iteratively mix elements, e.g. for v4f32:
7085 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7086 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7087 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7088 unsigned EltStride = NumElems >> 1;
7089 while (EltStride != 0) {
7090 for (unsigned i = 0; i < EltStride; ++i) {
7091 // If V[i+EltStride] is undef and this is the first round of mixing,
7092 // then it is safe to just drop this shuffle: V[i] is already in the
7093 // right place, the one element (since it's the first round) being
7094 // inserted as undef can be dropped. This isn't safe for successive
7095 // rounds because they will permute elements within both vectors.
7096 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7097 EltStride == NumElems/2)
7100 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7109 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7110 // to create 256-bit vectors from two other 128-bit ones.
7111 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7113 MVT ResVT = Op.getSimpleValueType();
7115 assert((ResVT.is256BitVector() ||
7116 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7118 SDValue V1 = Op.getOperand(0);
7119 SDValue V2 = Op.getOperand(1);
7120 unsigned NumElems = ResVT.getVectorNumElements();
7121 if(ResVT.is256BitVector())
7122 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7124 if (Op.getNumOperands() == 4) {
7125 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7126 ResVT.getVectorNumElements()/2);
7127 SDValue V3 = Op.getOperand(2);
7128 SDValue V4 = Op.getOperand(3);
7129 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7130 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7132 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7135 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7136 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7137 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7138 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7139 Op.getNumOperands() == 4)));
7141 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7142 // from two other 128-bit ones.
7144 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7145 return LowerAVXCONCAT_VECTORS(Op, DAG);
7149 //===----------------------------------------------------------------------===//
7150 // Vector shuffle lowering
7152 // This is an experimental code path for lowering vector shuffles on x86. It is
7153 // designed to handle arbitrary vector shuffles and blends, gracefully
7154 // degrading performance as necessary. It works hard to recognize idiomatic
7155 // shuffles and lower them to optimal instruction patterns without leaving
7156 // a framework that allows reasonably efficient handling of all vector shuffle
7158 //===----------------------------------------------------------------------===//
7160 /// \brief Tiny helper function to identify a no-op mask.
7162 /// This is a somewhat boring predicate function. It checks whether the mask
7163 /// array input, which is assumed to be a single-input shuffle mask of the kind
7164 /// used by the X86 shuffle instructions (not a fully general
7165 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7166 /// in-place shuffle are 'no-op's.
7167 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7168 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7169 if (Mask[i] != -1 && Mask[i] != i)
7174 /// \brief Helper function to classify a mask as a single-input mask.
7176 /// This isn't a generic single-input test because in the vector shuffle
7177 /// lowering we canonicalize single inputs to be the first input operand. This
7178 /// means we can more quickly test for a single input by only checking whether
7179 /// an input from the second operand exists. We also assume that the size of
7180 /// mask corresponds to the size of the input vectors which isn't true in the
7181 /// fully general case.
7182 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7184 if (M >= (int)Mask.size())
7189 /// \brief Test whether there are elements crossing 128-bit lanes in this
7192 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7193 /// and we routinely test for these.
7194 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7195 int LaneSize = 128 / VT.getScalarSizeInBits();
7196 int Size = Mask.size();
7197 for (int i = 0; i < Size; ++i)
7198 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7203 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7205 /// This checks a shuffle mask to see if it is performing the same
7206 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7207 /// that it is also not lane-crossing. It may however involve a blend from the
7208 /// same lane of a second vector.
7210 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7211 /// non-trivial to compute in the face of undef lanes. The representation is
7212 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7213 /// entries from both V1 and V2 inputs to the wider mask.
7215 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7216 SmallVectorImpl<int> &RepeatedMask) {
7217 int LaneSize = 128 / VT.getScalarSizeInBits();
7218 RepeatedMask.resize(LaneSize, -1);
7219 int Size = Mask.size();
7220 for (int i = 0; i < Size; ++i) {
7223 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7224 // This entry crosses lanes, so there is no way to model this shuffle.
7227 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7228 if (RepeatedMask[i % LaneSize] == -1)
7229 // This is the first non-undef entry in this slot of a 128-bit lane.
7230 RepeatedMask[i % LaneSize] =
7231 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7232 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7233 // Found a mismatch with the repeated mask.
7239 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7240 // 2013 will allow us to use it as a non-type template parameter.
7243 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7245 /// See its documentation for details.
7246 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7247 if (Mask.size() != Args.size())
7249 for (int i = 0, e = Mask.size(); i < e; ++i) {
7250 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7251 if (Mask[i] != -1 && Mask[i] != *Args[i])
7259 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7262 /// This is a fast way to test a shuffle mask against a fixed pattern:
7264 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7266 /// It returns true if the mask is exactly as wide as the argument list, and
7267 /// each element of the mask is either -1 (signifying undef) or the value given
7268 /// in the argument.
7269 static const VariadicFunction1<
7270 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7272 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7274 /// This helper function produces an 8-bit shuffle immediate corresponding to
7275 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7276 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7279 /// NB: We rely heavily on "undef" masks preserving the input lane.
7280 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7281 SelectionDAG &DAG) {
7282 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7283 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7284 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7285 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7286 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7289 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7290 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7291 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7292 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7293 return DAG.getConstant(Imm, MVT::i8);
7296 /// \brief Try to emit a blend instruction for a shuffle.
7298 /// This doesn't do any checks for the availability of instructions for blending
7299 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7300 /// be matched in the backend with the type given. What it does check for is
7301 /// that the shuffle mask is in fact a blend.
7302 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7303 SDValue V2, ArrayRef<int> Mask,
7304 const X86Subtarget *Subtarget,
7305 SelectionDAG &DAG) {
7307 unsigned BlendMask = 0;
7308 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7309 if (Mask[i] >= Size) {
7310 if (Mask[i] != i + Size)
7311 return SDValue(); // Shuffled V2 input!
7312 BlendMask |= 1u << i;
7315 if (Mask[i] >= 0 && Mask[i] != i)
7316 return SDValue(); // Shuffled V1 input!
7318 switch (VT.SimpleTy) {
7323 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7324 DAG.getConstant(BlendMask, MVT::i8));
7328 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7332 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7333 // that instruction.
7334 if (Subtarget->hasAVX2()) {
7335 // Scale the blend by the number of 32-bit dwords per element.
7336 int Scale = VT.getScalarSizeInBits() / 32;
7338 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7339 if (Mask[i] >= Size)
7340 for (int j = 0; j < Scale; ++j)
7341 BlendMask |= 1u << (i * Scale + j);
7343 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7344 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7345 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7346 return DAG.getNode(ISD::BITCAST, DL, VT,
7347 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7348 DAG.getConstant(BlendMask, MVT::i8)));
7352 // For integer shuffles we need to expand the mask and cast the inputs to
7353 // v8i16s prior to blending.
7354 int Scale = 8 / VT.getVectorNumElements();
7356 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7357 if (Mask[i] >= Size)
7358 for (int j = 0; j < Scale; ++j)
7359 BlendMask |= 1u << (i * Scale + j);
7361 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7362 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7363 return DAG.getNode(ISD::BITCAST, DL, VT,
7364 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7365 DAG.getConstant(BlendMask, MVT::i8)));
7369 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7370 SmallVector<int, 8> RepeatedMask;
7371 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7372 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7373 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7375 for (int i = 0; i < 8; ++i)
7376 if (RepeatedMask[i] >= 16)
7377 BlendMask |= 1u << i;
7378 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7379 DAG.getConstant(BlendMask, MVT::i8));
7384 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7385 // Scale the blend by the number of bytes per element.
7386 int Scale = VT.getScalarSizeInBits() / 8;
7387 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7389 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7390 // mix of LLVM's code generator and the x86 backend. We tell the code
7391 // generator that boolean values in the elements of an x86 vector register
7392 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7393 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7394 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7395 // of the element (the remaining are ignored) and 0 in that high bit would
7396 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7397 // the LLVM model for boolean values in vector elements gets the relevant
7398 // bit set, it is set backwards and over constrained relative to x86's
7400 SDValue VSELECTMask[32];
7401 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7402 for (int j = 0; j < Scale; ++j)
7403 VSELECTMask[Scale * i + j] =
7404 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7405 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7407 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7408 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7410 ISD::BITCAST, DL, VT,
7411 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7412 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7417 llvm_unreachable("Not a supported integer vector type!");
7421 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7422 /// unblended shuffles followed by an unshuffled blend.
7424 /// This matches the extremely common pattern for handling combined
7425 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7427 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7431 SelectionDAG &DAG) {
7432 // Shuffle the input elements into the desired positions in V1 and V2 and
7433 // blend them together.
7434 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7435 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7436 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7437 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7438 if (Mask[i] >= 0 && Mask[i] < Size) {
7439 V1Mask[i] = Mask[i];
7441 } else if (Mask[i] >= Size) {
7442 V2Mask[i] = Mask[i] - Size;
7443 BlendMask[i] = i + Size;
7446 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7447 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7448 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7451 /// \brief Try to lower a vector shuffle as a byte rotation.
7453 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7454 /// byte-rotation of the concatenation of two vectors. This routine will
7455 /// try to generically lower a vector shuffle through such an instruction. It
7456 /// does not check for the availability of PALIGNR-based lowerings, only the
7457 /// applicability of this strategy to the given mask. This matches shuffle
7458 /// vectors that look like:
7460 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7462 /// Essentially it concatenates V1 and V2, shifts right by some number of
7463 /// elements, and takes the low elements as the result. Note that while this is
7464 /// specified as a *right shift* because x86 is little-endian, it is a *left
7465 /// rotate* of the vector lanes.
7467 /// Note that this only handles 128-bit vector widths currently.
7468 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7471 SelectionDAG &DAG) {
7472 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7474 // We need to detect various ways of spelling a rotation:
7475 // [11, 12, 13, 14, 15, 0, 1, 2]
7476 // [-1, 12, 13, 14, -1, -1, 1, -1]
7477 // [-1, -1, -1, -1, -1, -1, 1, 2]
7478 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7479 // [-1, 4, 5, 6, -1, -1, 9, -1]
7480 // [-1, 4, 5, 6, -1, -1, -1, -1]
7483 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7486 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7488 // Based on the mod-Size value of this mask element determine where
7489 // a rotated vector would have started.
7490 int StartIdx = i - (Mask[i] % Size);
7492 // The identity rotation isn't interesting, stop.
7495 // If we found the tail of a vector the rotation must be the missing
7496 // front. If we found the head of a vector, it must be how much of the head.
7497 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7500 Rotation = CandidateRotation;
7501 else if (Rotation != CandidateRotation)
7502 // The rotations don't match, so we can't match this mask.
7505 // Compute which value this mask is pointing at.
7506 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7508 // Compute which of the two target values this index should be assigned to.
7509 // This reflects whether the high elements are remaining or the low elements
7511 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7513 // Either set up this value if we've not encountered it before, or check
7514 // that it remains consistent.
7517 else if (TargetV != MaskV)
7518 // This may be a rotation, but it pulls from the inputs in some
7519 // unsupported interleaving.
7523 // Check that we successfully analyzed the mask, and normalize the results.
7524 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7525 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7531 // Cast the inputs to v16i8 to match PALIGNR.
7532 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7533 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7535 assert(VT.getSizeInBits() == 128 &&
7536 "Rotate-based lowering only supports 128-bit lowering!");
7537 assert(Mask.size() <= 16 &&
7538 "Can shuffle at most 16 bytes in a 128-bit vector!");
7539 // The actual rotate instruction rotates bytes, so we need to scale the
7540 // rotation based on how many bytes are in the vector.
7541 int Scale = 16 / Mask.size();
7543 return DAG.getNode(ISD::BITCAST, DL, VT,
7544 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7545 DAG.getConstant(Rotation * Scale, MVT::i8)));
7548 /// \brief Compute whether each element of a shuffle is zeroable.
7550 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7551 /// Either it is an undef element in the shuffle mask, the element of the input
7552 /// referenced is undef, or the element of the input referenced is known to be
7553 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7554 /// as many lanes with this technique as possible to simplify the remaining
7556 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7557 SDValue V1, SDValue V2) {
7558 SmallBitVector Zeroable(Mask.size(), false);
7560 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7561 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7563 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7565 // Handle the easy cases.
7566 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7571 // If this is an index into a build_vector node, dig out the input value and
7573 SDValue V = M < Size ? V1 : V2;
7574 if (V.getOpcode() != ISD::BUILD_VECTOR)
7577 SDValue Input = V.getOperand(M % Size);
7578 // The UNDEF opcode check really should be dead code here, but not quite
7579 // worth asserting on (it isn't invalid, just unexpected).
7580 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7587 /// \brief Lower a vector shuffle as a zero or any extension.
7589 /// Given a specific number of elements, element bit width, and extension
7590 /// stride, produce either a zero or any extension based on the available
7591 /// features of the subtarget.
7592 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7593 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7594 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7595 assert(Scale > 1 && "Need a scale to extend.");
7596 int EltBits = VT.getSizeInBits() / NumElements;
7597 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7598 "Only 8, 16, and 32 bit elements can be extended.");
7599 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7601 // Found a valid zext mask! Try various lowering strategies based on the
7602 // input type and available ISA extensions.
7603 if (Subtarget->hasSSE41()) {
7604 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7605 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7606 NumElements / Scale);
7607 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7608 return DAG.getNode(ISD::BITCAST, DL, VT,
7609 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7612 // For any extends we can cheat for larger element sizes and use shuffle
7613 // instructions that can fold with a load and/or copy.
7614 if (AnyExt && EltBits == 32) {
7615 int PSHUFDMask[4] = {0, -1, 1, -1};
7617 ISD::BITCAST, DL, VT,
7618 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7619 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7620 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7622 if (AnyExt && EltBits == 16 && Scale > 2) {
7623 int PSHUFDMask[4] = {0, -1, 0, -1};
7624 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7625 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7626 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7627 int PSHUFHWMask[4] = {1, -1, -1, -1};
7629 ISD::BITCAST, DL, VT,
7630 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7631 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7632 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7635 // If this would require more than 2 unpack instructions to expand, use
7636 // pshufb when available. We can only use more than 2 unpack instructions
7637 // when zero extending i8 elements which also makes it easier to use pshufb.
7638 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7639 assert(NumElements == 16 && "Unexpected byte vector width!");
7640 SDValue PSHUFBMask[16];
7641 for (int i = 0; i < 16; ++i)
7643 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7644 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7645 return DAG.getNode(ISD::BITCAST, DL, VT,
7646 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7647 DAG.getNode(ISD::BUILD_VECTOR, DL,
7648 MVT::v16i8, PSHUFBMask)));
7651 // Otherwise emit a sequence of unpacks.
7653 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7654 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7655 : getZeroVector(InputVT, Subtarget, DAG, DL);
7656 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7657 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7661 } while (Scale > 1);
7662 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7665 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7667 /// This routine will try to do everything in its power to cleverly lower
7668 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7669 /// check for the profitability of this lowering, it tries to aggressively
7670 /// match this pattern. It will use all of the micro-architectural details it
7671 /// can to emit an efficient lowering. It handles both blends with all-zero
7672 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7673 /// masking out later).
7675 /// The reason we have dedicated lowering for zext-style shuffles is that they
7676 /// are both incredibly common and often quite performance sensitive.
7677 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7678 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7679 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7680 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7682 int Bits = VT.getSizeInBits();
7683 int NumElements = Mask.size();
7685 // Define a helper function to check a particular ext-scale and lower to it if
7687 auto Lower = [&](int Scale) -> SDValue {
7690 for (int i = 0; i < NumElements; ++i) {
7692 continue; // Valid anywhere but doesn't tell us anything.
7693 if (i % Scale != 0) {
7694 // Each of the extend elements needs to be zeroable.
7698 // We no lorger are in the anyext case.
7703 // Each of the base elements needs to be consecutive indices into the
7704 // same input vector.
7705 SDValue V = Mask[i] < NumElements ? V1 : V2;
7708 else if (InputV != V)
7709 return SDValue(); // Flip-flopping inputs.
7711 if (Mask[i] % NumElements != i / Scale)
7712 return SDValue(); // Non-consecutive strided elemenst.
7715 // If we fail to find an input, we have a zero-shuffle which should always
7716 // have already been handled.
7717 // FIXME: Maybe handle this here in case during blending we end up with one?
7721 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7722 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7725 // The widest scale possible for extending is to a 64-bit integer.
7726 assert(Bits % 64 == 0 &&
7727 "The number of bits in a vector must be divisible by 64 on x86!");
7728 int NumExtElements = Bits / 64;
7730 // Each iteration, try extending the elements half as much, but into twice as
7732 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7733 assert(NumElements % NumExtElements == 0 &&
7734 "The input vector size must be divisble by the extended size.");
7735 if (SDValue V = Lower(NumElements / NumExtElements))
7739 // No viable ext lowering found.
7743 /// \brief Try to get a scalar value for a specific element of a vector.
7745 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7746 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7747 SelectionDAG &DAG) {
7748 MVT VT = V.getSimpleValueType();
7749 MVT EltVT = VT.getVectorElementType();
7750 while (V.getOpcode() == ISD::BITCAST)
7751 V = V.getOperand(0);
7752 // If the bitcasts shift the element size, we can't extract an equivalent
7754 MVT NewVT = V.getSimpleValueType();
7755 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7758 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7759 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7760 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7765 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7767 /// This is particularly important because the set of instructions varies
7768 /// significantly based on whether the operand is a load or not.
7769 static bool isShuffleFoldableLoad(SDValue V) {
7770 while (V.getOpcode() == ISD::BITCAST)
7771 V = V.getOperand(0);
7773 return ISD::isNON_EXTLoad(V.getNode());
7776 /// \brief Try to lower insertion of a single element into a zero vector.
7778 /// This is a common pattern that we have especially efficient patterns to lower
7779 /// across all subtarget feature sets.
7780 static SDValue lowerVectorShuffleAsElementInsertion(
7781 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7782 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7783 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7785 MVT EltVT = VT.getVectorElementType();
7787 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7788 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7790 bool IsV1Zeroable = true;
7791 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7792 if (i != V2Index && !Zeroable[i]) {
7793 IsV1Zeroable = false;
7797 // Check for a single input from a SCALAR_TO_VECTOR node.
7798 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7799 // all the smarts here sunk into that routine. However, the current
7800 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7801 // vector shuffle lowering is dead.
7802 if (SDValue V2S = getScalarValueForVectorElement(
7803 V2, Mask[V2Index] - Mask.size(), DAG)) {
7804 // We need to zext the scalar if it is smaller than an i32.
7805 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7806 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7807 // Using zext to expand a narrow element won't work for non-zero
7812 // Zero-extend directly to i32.
7814 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7816 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7817 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7818 EltVT == MVT::i16) {
7819 // Either not inserting from the low element of the input or the input
7820 // element size is too small to use VZEXT_MOVL to clear the high bits.
7824 if (!IsV1Zeroable) {
7825 // If V1 can't be treated as a zero vector we have fewer options to lower
7826 // this. We can't support integer vectors or non-zero targets cheaply, and
7827 // the V1 elements can't be permuted in any way.
7828 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7829 if (!VT.isFloatingPoint() || V2Index != 0)
7831 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7832 V1Mask[V2Index] = -1;
7833 if (!isNoopShuffleMask(V1Mask))
7835 // This is essentially a special case blend operation, but if we have
7836 // general purpose blend operations, they are always faster. Bail and let
7837 // the rest of the lowering handle these as blends.
7838 if (Subtarget->hasSSE41())
7841 // Otherwise, use MOVSD or MOVSS.
7842 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7843 "Only two types of floating point element types to handle!");
7844 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7848 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7850 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7853 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7854 // the desired position. Otherwise it is more efficient to do a vector
7855 // shift left. We know that we can do a vector shift left because all
7856 // the inputs are zero.
7857 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7858 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7859 V2Shuffle[V2Index] = 0;
7860 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7862 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7864 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7866 V2Index * EltVT.getSizeInBits(),
7867 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7868 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7874 /// \brief Try to lower broadcast of a single element.
7876 /// For convenience, this code also bundles all of the subtarget feature set
7877 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7878 /// a convenient way to factor it out.
7879 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7881 const X86Subtarget *Subtarget,
7882 SelectionDAG &DAG) {
7883 if (!Subtarget->hasAVX())
7885 if (VT.isInteger() && !Subtarget->hasAVX2())
7888 // Check that the mask is a broadcast.
7889 int BroadcastIdx = -1;
7891 if (M >= 0 && BroadcastIdx == -1)
7893 else if (M >= 0 && M != BroadcastIdx)
7896 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7897 "a sorted mask where the broadcast "
7900 // Go up the chain of (vector) values to try and find a scalar load that
7901 // we can combine with the broadcast.
7903 switch (V.getOpcode()) {
7904 case ISD::CONCAT_VECTORS: {
7905 int OperandSize = Mask.size() / V.getNumOperands();
7906 V = V.getOperand(BroadcastIdx / OperandSize);
7907 BroadcastIdx %= OperandSize;
7911 case ISD::INSERT_SUBVECTOR: {
7912 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7913 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7917 int BeginIdx = (int)ConstantIdx->getZExtValue();
7919 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7920 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7921 BroadcastIdx -= BeginIdx;
7932 // Check if this is a broadcast of a scalar. We special case lowering
7933 // for scalars so that we can more effectively fold with loads.
7934 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7935 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7936 V = V.getOperand(BroadcastIdx);
7938 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7940 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7942 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7943 // We can't broadcast from a vector register w/o AVX2, and we can only
7944 // broadcast from the zero-element of a vector register.
7948 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7951 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7953 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7954 /// support for floating point shuffles but not integer shuffles. These
7955 /// instructions will incur a domain crossing penalty on some chips though so
7956 /// it is better to avoid lowering through this for integer vectors where
7958 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7959 const X86Subtarget *Subtarget,
7960 SelectionDAG &DAG) {
7962 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7963 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7964 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7965 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7966 ArrayRef<int> Mask = SVOp->getMask();
7967 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7969 if (isSingleInputShuffleMask(Mask)) {
7970 // Straight shuffle of a single input vector. Simulate this by using the
7971 // single input as both of the "inputs" to this instruction..
7972 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7974 if (Subtarget->hasAVX()) {
7975 // If we have AVX, we can use VPERMILPS which will allow folding a load
7976 // into the shuffle.
7977 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7978 DAG.getConstant(SHUFPDMask, MVT::i8));
7981 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7982 DAG.getConstant(SHUFPDMask, MVT::i8));
7984 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7985 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7987 // Use dedicated unpack instructions for masks that match their pattern.
7988 if (isShuffleEquivalent(Mask, 0, 2))
7989 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7990 if (isShuffleEquivalent(Mask, 1, 3))
7991 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7993 // If we have a single input, insert that into V1 if we can do so cheaply.
7994 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7995 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7996 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7998 // Try inverting the insertion since for v2 masks it is easy to do and we
7999 // can't reliably sort the mask one way or the other.
8000 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8001 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8002 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8003 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8007 // Try to use one of the special instruction patterns to handle two common
8008 // blend patterns if a zero-blend above didn't work.
8009 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8010 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8011 // We can either use a special instruction to load over the low double or
8012 // to move just the low double.
8014 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8016 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8018 if (Subtarget->hasSSE41())
8019 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8023 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8024 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8025 DAG.getConstant(SHUFPDMask, MVT::i8));
8028 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8030 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8031 /// the integer unit to minimize domain crossing penalties. However, for blends
8032 /// it falls back to the floating point shuffle operation with appropriate bit
8034 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8035 const X86Subtarget *Subtarget,
8036 SelectionDAG &DAG) {
8038 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8039 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8040 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8042 ArrayRef<int> Mask = SVOp->getMask();
8043 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8045 if (isSingleInputShuffleMask(Mask)) {
8046 // Check for being able to broadcast a single element.
8047 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8048 Mask, Subtarget, DAG))
8051 // Straight shuffle of a single input vector. For everything from SSE2
8052 // onward this has a single fast instruction with no scary immediates.
8053 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8054 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8055 int WidenedMask[4] = {
8056 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8057 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8059 ISD::BITCAST, DL, MVT::v2i64,
8060 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8061 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8064 // If we have a single input from V2 insert that into V1 if we can do so
8066 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8067 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8068 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8070 // Try inverting the insertion since for v2 masks it is easy to do and we
8071 // can't reliably sort the mask one way or the other.
8072 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8073 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8074 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8075 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8079 // Use dedicated unpack instructions for masks that match their pattern.
8080 if (isShuffleEquivalent(Mask, 0, 2))
8081 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8082 if (isShuffleEquivalent(Mask, 1, 3))
8083 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8085 if (Subtarget->hasSSE41())
8086 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8090 // Try to use rotation instructions if available.
8091 if (Subtarget->hasSSSE3())
8092 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8093 DL, MVT::v2i64, V1, V2, Mask, DAG))
8096 // We implement this with SHUFPD which is pretty lame because it will likely
8097 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8098 // However, all the alternatives are still more cycles and newer chips don't
8099 // have this problem. It would be really nice if x86 had better shuffles here.
8100 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8101 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8102 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8103 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8106 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8108 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8109 /// It makes no assumptions about whether this is the *best* lowering, it simply
8111 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8112 ArrayRef<int> Mask, SDValue V1,
8113 SDValue V2, SelectionDAG &DAG) {
8114 SDValue LowV = V1, HighV = V2;
8115 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8118 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8120 if (NumV2Elements == 1) {
8122 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8125 // Compute the index adjacent to V2Index and in the same half by toggling
8127 int V2AdjIndex = V2Index ^ 1;
8129 if (Mask[V2AdjIndex] == -1) {
8130 // Handles all the cases where we have a single V2 element and an undef.
8131 // This will only ever happen in the high lanes because we commute the
8132 // vector otherwise.
8134 std::swap(LowV, HighV);
8135 NewMask[V2Index] -= 4;
8137 // Handle the case where the V2 element ends up adjacent to a V1 element.
8138 // To make this work, blend them together as the first step.
8139 int V1Index = V2AdjIndex;
8140 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8141 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8142 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8144 // Now proceed to reconstruct the final blend as we have the necessary
8145 // high or low half formed.
8152 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8153 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8155 } else if (NumV2Elements == 2) {
8156 if (Mask[0] < 4 && Mask[1] < 4) {
8157 // Handle the easy case where we have V1 in the low lanes and V2 in the
8161 } else if (Mask[2] < 4 && Mask[3] < 4) {
8162 // We also handle the reversed case because this utility may get called
8163 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8164 // arrange things in the right direction.
8170 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8171 // trying to place elements directly, just blend them and set up the final
8172 // shuffle to place them.
8174 // The first two blend mask elements are for V1, the second two are for
8176 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8177 Mask[2] < 4 ? Mask[2] : Mask[3],
8178 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8179 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8180 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8181 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8183 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8186 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8187 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8188 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8189 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8192 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8193 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8196 /// \brief Lower 4-lane 32-bit floating point shuffles.
8198 /// Uses instructions exclusively from the floating point unit to minimize
8199 /// domain crossing penalties, as these are sufficient to implement all v4f32
8201 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8202 const X86Subtarget *Subtarget,
8203 SelectionDAG &DAG) {
8205 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8206 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8207 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8209 ArrayRef<int> Mask = SVOp->getMask();
8210 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8213 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8215 if (NumV2Elements == 0) {
8216 // Check for being able to broadcast a single element.
8217 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8218 Mask, Subtarget, DAG))
8221 if (Subtarget->hasAVX()) {
8222 // If we have AVX, we can use VPERMILPS which will allow folding a load
8223 // into the shuffle.
8224 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8225 getV4X86ShuffleImm8ForMask(Mask, DAG));
8228 // Otherwise, use a straight shuffle of a single input vector. We pass the
8229 // input vector to both operands to simulate this with a SHUFPS.
8230 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8231 getV4X86ShuffleImm8ForMask(Mask, DAG));
8234 // Use dedicated unpack instructions for masks that match their pattern.
8235 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8236 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8237 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8238 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8240 // There are special ways we can lower some single-element blends. However, we
8241 // have custom ways we can lower more complex single-element blends below that
8242 // we defer to if both this and BLENDPS fail to match, so restrict this to
8243 // when the V2 input is targeting element 0 of the mask -- that is the fast
8245 if (NumV2Elements == 1 && Mask[0] >= 4)
8246 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8247 Mask, Subtarget, DAG))
8250 if (Subtarget->hasSSE41())
8251 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8255 // Check for whether we can use INSERTPS to perform the blend. We only use
8256 // INSERTPS when the V1 elements are already in the correct locations
8257 // because otherwise we can just always use two SHUFPS instructions which
8258 // are much smaller to encode than a SHUFPS and an INSERTPS.
8259 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8261 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8264 // When using INSERTPS we can zero any lane of the destination. Collect
8265 // the zero inputs into a mask and drop them from the lanes of V1 which
8266 // actually need to be present as inputs to the INSERTPS.
8267 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8269 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8270 bool InsertNeedsShuffle = false;
8272 for (int i = 0; i < 4; ++i)
8276 } else if (Mask[i] != i) {
8277 InsertNeedsShuffle = true;
8282 // We don't want to use INSERTPS or other insertion techniques if it will
8283 // require shuffling anyways.
8284 if (!InsertNeedsShuffle) {
8285 // If all of V1 is zeroable, replace it with undef.
8286 if ((ZMask | 1 << V2Index) == 0xF)
8287 V1 = DAG.getUNDEF(MVT::v4f32);
8289 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8290 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8292 // Insert the V2 element into the desired position.
8293 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8294 DAG.getConstant(InsertPSMask, MVT::i8));
8298 // Otherwise fall back to a SHUFPS lowering strategy.
8299 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8302 /// \brief Lower 4-lane i32 vector shuffles.
8304 /// We try to handle these with integer-domain shuffles where we can, but for
8305 /// blends we use the floating point domain blend instructions.
8306 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8307 const X86Subtarget *Subtarget,
8308 SelectionDAG &DAG) {
8310 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8311 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8312 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8314 ArrayRef<int> Mask = SVOp->getMask();
8315 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8317 // Whenever we can lower this as a zext, that instruction is strictly faster
8318 // than any alternative. It also allows us to fold memory operands into the
8319 // shuffle in many cases.
8320 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8321 Mask, Subtarget, DAG))
8325 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8327 if (NumV2Elements == 0) {
8328 // Check for being able to broadcast a single element.
8329 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8330 Mask, Subtarget, DAG))
8333 // Straight shuffle of a single input vector. For everything from SSE2
8334 // onward this has a single fast instruction with no scary immediates.
8335 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8336 // but we aren't actually going to use the UNPCK instruction because doing
8337 // so prevents folding a load into this instruction or making a copy.
8338 const int UnpackLoMask[] = {0, 0, 1, 1};
8339 const int UnpackHiMask[] = {2, 2, 3, 3};
8340 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8341 Mask = UnpackLoMask;
8342 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8343 Mask = UnpackHiMask;
8345 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8346 getV4X86ShuffleImm8ForMask(Mask, DAG));
8349 // There are special ways we can lower some single-element blends.
8350 if (NumV2Elements == 1)
8351 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8352 Mask, Subtarget, DAG))
8355 // Use dedicated unpack instructions for masks that match their pattern.
8356 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8357 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8358 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8359 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8361 if (Subtarget->hasSSE41())
8362 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8366 // Try to use rotation instructions if available.
8367 if (Subtarget->hasSSSE3())
8368 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8369 DL, MVT::v4i32, V1, V2, Mask, DAG))
8372 // We implement this with SHUFPS because it can blend from two vectors.
8373 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8374 // up the inputs, bypassing domain shift penalties that we would encur if we
8375 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8377 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8378 DAG.getVectorShuffle(
8380 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8381 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8384 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8385 /// shuffle lowering, and the most complex part.
8387 /// The lowering strategy is to try to form pairs of input lanes which are
8388 /// targeted at the same half of the final vector, and then use a dword shuffle
8389 /// to place them onto the right half, and finally unpack the paired lanes into
8390 /// their final position.
8392 /// The exact breakdown of how to form these dword pairs and align them on the
8393 /// correct sides is really tricky. See the comments within the function for
8394 /// more of the details.
8395 static SDValue lowerV8I16SingleInputVectorShuffle(
8396 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8397 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8398 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8399 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8400 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8402 SmallVector<int, 4> LoInputs;
8403 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8404 [](int M) { return M >= 0; });
8405 std::sort(LoInputs.begin(), LoInputs.end());
8406 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8407 SmallVector<int, 4> HiInputs;
8408 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8409 [](int M) { return M >= 0; });
8410 std::sort(HiInputs.begin(), HiInputs.end());
8411 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8413 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8414 int NumHToL = LoInputs.size() - NumLToL;
8416 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8417 int NumHToH = HiInputs.size() - NumLToH;
8418 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8419 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8420 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8421 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8423 // Check for being able to broadcast a single element.
8424 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8425 Mask, Subtarget, DAG))
8428 // Use dedicated unpack instructions for masks that match their pattern.
8429 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8430 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8431 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8432 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8434 // Try to use rotation instructions if available.
8435 if (Subtarget->hasSSSE3())
8436 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8437 DL, MVT::v8i16, V, V, Mask, DAG))
8440 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8441 // such inputs we can swap two of the dwords across the half mark and end up
8442 // with <=2 inputs to each half in each half. Once there, we can fall through
8443 // to the generic code below. For example:
8445 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8446 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8448 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8449 // and an existing 2-into-2 on the other half. In this case we may have to
8450 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8451 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8452 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8453 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8454 // half than the one we target for fixing) will be fixed when we re-enter this
8455 // path. We will also combine away any sequence of PSHUFD instructions that
8456 // result into a single instruction. Here is an example of the tricky case:
8458 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8459 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8461 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8463 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8464 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8466 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8467 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8469 // The result is fine to be handled by the generic logic.
8470 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8471 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8472 int AOffset, int BOffset) {
8473 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8474 "Must call this with A having 3 or 1 inputs from the A half.");
8475 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8476 "Must call this with B having 1 or 3 inputs from the B half.");
8477 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8478 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8480 // Compute the index of dword with only one word among the three inputs in
8481 // a half by taking the sum of the half with three inputs and subtracting
8482 // the sum of the actual three inputs. The difference is the remaining
8485 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8486 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8487 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8488 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8489 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8490 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8491 int TripleNonInputIdx =
8492 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8493 TripleDWord = TripleNonInputIdx / 2;
8495 // We use xor with one to compute the adjacent DWord to whichever one the
8497 OneInputDWord = (OneInput / 2) ^ 1;
8499 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8500 // and BToA inputs. If there is also such a problem with the BToB and AToB
8501 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8502 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8503 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8504 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8505 // Compute how many inputs will be flipped by swapping these DWords. We
8507 // to balance this to ensure we don't form a 3-1 shuffle in the other
8509 int NumFlippedAToBInputs =
8510 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8511 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8512 int NumFlippedBToBInputs =
8513 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8514 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8515 if ((NumFlippedAToBInputs == 1 &&
8516 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8517 (NumFlippedBToBInputs == 1 &&
8518 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8519 // We choose whether to fix the A half or B half based on whether that
8520 // half has zero flipped inputs. At zero, we may not be able to fix it
8521 // with that half. We also bias towards fixing the B half because that
8522 // will more commonly be the high half, and we have to bias one way.
8523 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8524 ArrayRef<int> Inputs) {
8525 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8526 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8527 PinnedIdx ^ 1) != Inputs.end();
8528 // Determine whether the free index is in the flipped dword or the
8529 // unflipped dword based on where the pinned index is. We use this bit
8530 // in an xor to conditionally select the adjacent dword.
8531 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8532 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8533 FixFreeIdx) != Inputs.end();
8534 if (IsFixIdxInput == IsFixFreeIdxInput)
8536 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8537 FixFreeIdx) != Inputs.end();
8538 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8539 "We need to be changing the number of flipped inputs!");
8540 int PSHUFHalfMask[] = {0, 1, 2, 3};
8541 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8542 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8544 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8547 if (M != -1 && M == FixIdx)
8549 else if (M != -1 && M == FixFreeIdx)
8552 if (NumFlippedBToBInputs != 0) {
8554 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8555 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8557 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8559 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8560 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8565 int PSHUFDMask[] = {0, 1, 2, 3};
8566 PSHUFDMask[ADWord] = BDWord;
8567 PSHUFDMask[BDWord] = ADWord;
8568 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8569 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8570 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8571 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8573 // Adjust the mask to match the new locations of A and B.
8575 if (M != -1 && M/2 == ADWord)
8576 M = 2 * BDWord + M % 2;
8577 else if (M != -1 && M/2 == BDWord)
8578 M = 2 * ADWord + M % 2;
8580 // Recurse back into this routine to re-compute state now that this isn't
8581 // a 3 and 1 problem.
8582 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8585 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8586 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8587 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8588 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8590 // At this point there are at most two inputs to the low and high halves from
8591 // each half. That means the inputs can always be grouped into dwords and
8592 // those dwords can then be moved to the correct half with a dword shuffle.
8593 // We use at most one low and one high word shuffle to collect these paired
8594 // inputs into dwords, and finally a dword shuffle to place them.
8595 int PSHUFLMask[4] = {-1, -1, -1, -1};
8596 int PSHUFHMask[4] = {-1, -1, -1, -1};
8597 int PSHUFDMask[4] = {-1, -1, -1, -1};
8599 // First fix the masks for all the inputs that are staying in their
8600 // original halves. This will then dictate the targets of the cross-half
8602 auto fixInPlaceInputs =
8603 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8604 MutableArrayRef<int> SourceHalfMask,
8605 MutableArrayRef<int> HalfMask, int HalfOffset) {
8606 if (InPlaceInputs.empty())
8608 if (InPlaceInputs.size() == 1) {
8609 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8610 InPlaceInputs[0] - HalfOffset;
8611 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8614 if (IncomingInputs.empty()) {
8615 // Just fix all of the in place inputs.
8616 for (int Input : InPlaceInputs) {
8617 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8618 PSHUFDMask[Input / 2] = Input / 2;
8623 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8624 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8625 InPlaceInputs[0] - HalfOffset;
8626 // Put the second input next to the first so that they are packed into
8627 // a dword. We find the adjacent index by toggling the low bit.
8628 int AdjIndex = InPlaceInputs[0] ^ 1;
8629 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8630 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8631 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8633 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8634 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8636 // Now gather the cross-half inputs and place them into a free dword of
8637 // their target half.
8638 // FIXME: This operation could almost certainly be simplified dramatically to
8639 // look more like the 3-1 fixing operation.
8640 auto moveInputsToRightHalf = [&PSHUFDMask](
8641 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8642 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8643 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8645 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8646 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8648 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8650 int LowWord = Word & ~1;
8651 int HighWord = Word | 1;
8652 return isWordClobbered(SourceHalfMask, LowWord) ||
8653 isWordClobbered(SourceHalfMask, HighWord);
8656 if (IncomingInputs.empty())
8659 if (ExistingInputs.empty()) {
8660 // Map any dwords with inputs from them into the right half.
8661 for (int Input : IncomingInputs) {
8662 // If the source half mask maps over the inputs, turn those into
8663 // swaps and use the swapped lane.
8664 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8665 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8666 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8667 Input - SourceOffset;
8668 // We have to swap the uses in our half mask in one sweep.
8669 for (int &M : HalfMask)
8670 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8672 else if (M == Input)
8673 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8675 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8676 Input - SourceOffset &&
8677 "Previous placement doesn't match!");
8679 // Note that this correctly re-maps both when we do a swap and when
8680 // we observe the other side of the swap above. We rely on that to
8681 // avoid swapping the members of the input list directly.
8682 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8685 // Map the input's dword into the correct half.
8686 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8687 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8689 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8691 "Previous placement doesn't match!");
8694 // And just directly shift any other-half mask elements to be same-half
8695 // as we will have mirrored the dword containing the element into the
8696 // same position within that half.
8697 for (int &M : HalfMask)
8698 if (M >= SourceOffset && M < SourceOffset + 4) {
8699 M = M - SourceOffset + DestOffset;
8700 assert(M >= 0 && "This should never wrap below zero!");
8705 // Ensure we have the input in a viable dword of its current half. This
8706 // is particularly tricky because the original position may be clobbered
8707 // by inputs being moved and *staying* in that half.
8708 if (IncomingInputs.size() == 1) {
8709 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8710 int InputFixed = std::find(std::begin(SourceHalfMask),
8711 std::end(SourceHalfMask), -1) -
8712 std::begin(SourceHalfMask) + SourceOffset;
8713 SourceHalfMask[InputFixed - SourceOffset] =
8714 IncomingInputs[0] - SourceOffset;
8715 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8717 IncomingInputs[0] = InputFixed;
8719 } else if (IncomingInputs.size() == 2) {
8720 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8721 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8722 // We have two non-adjacent or clobbered inputs we need to extract from
8723 // the source half. To do this, we need to map them into some adjacent
8724 // dword slot in the source mask.
8725 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8726 IncomingInputs[1] - SourceOffset};
8728 // If there is a free slot in the source half mask adjacent to one of
8729 // the inputs, place the other input in it. We use (Index XOR 1) to
8730 // compute an adjacent index.
8731 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8732 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8733 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8734 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8735 InputsFixed[1] = InputsFixed[0] ^ 1;
8736 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8737 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8738 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8739 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8740 InputsFixed[0] = InputsFixed[1] ^ 1;
8741 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8742 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8743 // The two inputs are in the same DWord but it is clobbered and the
8744 // adjacent DWord isn't used at all. Move both inputs to the free
8746 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8747 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8748 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8749 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8751 // The only way we hit this point is if there is no clobbering
8752 // (because there are no off-half inputs to this half) and there is no
8753 // free slot adjacent to one of the inputs. In this case, we have to
8754 // swap an input with a non-input.
8755 for (int i = 0; i < 4; ++i)
8756 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8757 "We can't handle any clobbers here!");
8758 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8759 "Cannot have adjacent inputs here!");
8761 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8762 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8764 // We also have to update the final source mask in this case because
8765 // it may need to undo the above swap.
8766 for (int &M : FinalSourceHalfMask)
8767 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8768 M = InputsFixed[1] + SourceOffset;
8769 else if (M == InputsFixed[1] + SourceOffset)
8770 M = (InputsFixed[0] ^ 1) + SourceOffset;
8772 InputsFixed[1] = InputsFixed[0] ^ 1;
8775 // Point everything at the fixed inputs.
8776 for (int &M : HalfMask)
8777 if (M == IncomingInputs[0])
8778 M = InputsFixed[0] + SourceOffset;
8779 else if (M == IncomingInputs[1])
8780 M = InputsFixed[1] + SourceOffset;
8782 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8783 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8786 llvm_unreachable("Unhandled input size!");
8789 // Now hoist the DWord down to the right half.
8790 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8791 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8792 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8793 for (int &M : HalfMask)
8794 for (int Input : IncomingInputs)
8796 M = FreeDWord * 2 + Input % 2;
8798 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8799 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8800 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8801 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8803 // Now enact all the shuffles we've computed to move the inputs into their
8805 if (!isNoopShuffleMask(PSHUFLMask))
8806 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8807 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8808 if (!isNoopShuffleMask(PSHUFHMask))
8809 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8810 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8811 if (!isNoopShuffleMask(PSHUFDMask))
8812 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8813 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8814 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8815 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8817 // At this point, each half should contain all its inputs, and we can then
8818 // just shuffle them into their final position.
8819 assert(std::count_if(LoMask.begin(), LoMask.end(),
8820 [](int M) { return M >= 4; }) == 0 &&
8821 "Failed to lift all the high half inputs to the low mask!");
8822 assert(std::count_if(HiMask.begin(), HiMask.end(),
8823 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8824 "Failed to lift all the low half inputs to the high mask!");
8826 // Do a half shuffle for the low mask.
8827 if (!isNoopShuffleMask(LoMask))
8828 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8829 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8831 // Do a half shuffle with the high mask after shifting its values down.
8832 for (int &M : HiMask)
8835 if (!isNoopShuffleMask(HiMask))
8836 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8837 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8842 /// \brief Detect whether the mask pattern should be lowered through
8845 /// This essentially tests whether viewing the mask as an interleaving of two
8846 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8847 /// lowering it through interleaving is a significantly better strategy.
8848 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8849 int NumEvenInputs[2] = {0, 0};
8850 int NumOddInputs[2] = {0, 0};
8851 int NumLoInputs[2] = {0, 0};
8852 int NumHiInputs[2] = {0, 0};
8853 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8857 int InputIdx = Mask[i] >= Size;
8860 ++NumLoInputs[InputIdx];
8862 ++NumHiInputs[InputIdx];
8865 ++NumEvenInputs[InputIdx];
8867 ++NumOddInputs[InputIdx];
8870 // The minimum number of cross-input results for both the interleaved and
8871 // split cases. If interleaving results in fewer cross-input results, return
8873 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8874 NumEvenInputs[0] + NumOddInputs[1]);
8875 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8876 NumLoInputs[0] + NumHiInputs[1]);
8877 return InterleavedCrosses < SplitCrosses;
8880 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8882 /// This strategy only works when the inputs from each vector fit into a single
8883 /// half of that vector, and generally there are not so many inputs as to leave
8884 /// the in-place shuffles required highly constrained (and thus expensive). It
8885 /// shifts all the inputs into a single side of both input vectors and then
8886 /// uses an unpack to interleave these inputs in a single vector. At that
8887 /// point, we will fall back on the generic single input shuffle lowering.
8888 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8890 MutableArrayRef<int> Mask,
8891 const X86Subtarget *Subtarget,
8892 SelectionDAG &DAG) {
8893 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8894 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8895 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8896 for (int i = 0; i < 8; ++i)
8897 if (Mask[i] >= 0 && Mask[i] < 4)
8898 LoV1Inputs.push_back(i);
8899 else if (Mask[i] >= 4 && Mask[i] < 8)
8900 HiV1Inputs.push_back(i);
8901 else if (Mask[i] >= 8 && Mask[i] < 12)
8902 LoV2Inputs.push_back(i);
8903 else if (Mask[i] >= 12)
8904 HiV2Inputs.push_back(i);
8906 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8907 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8910 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8911 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8912 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8914 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8915 HiV1Inputs.size() + HiV2Inputs.size();
8917 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8918 ArrayRef<int> HiInputs, bool MoveToLo,
8920 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8921 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8922 if (BadInputs.empty())
8925 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8926 int MoveOffset = MoveToLo ? 0 : 4;
8928 if (GoodInputs.empty()) {
8929 for (int BadInput : BadInputs) {
8930 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8931 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8934 if (GoodInputs.size() == 2) {
8935 // If the low inputs are spread across two dwords, pack them into
8937 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8938 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8939 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8940 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8942 // Otherwise pin the good inputs.
8943 for (int GoodInput : GoodInputs)
8944 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8947 if (BadInputs.size() == 2) {
8948 // If we have two bad inputs then there may be either one or two good
8949 // inputs fixed in place. Find a fixed input, and then find the *other*
8950 // two adjacent indices by using modular arithmetic.
8952 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8953 [](int M) { return M >= 0; }) -
8954 std::begin(MoveMask);
8956 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8957 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8958 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8959 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8960 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8961 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8962 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8964 assert(BadInputs.size() == 1 && "All sizes handled");
8965 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8966 std::end(MoveMask), -1) -
8967 std::begin(MoveMask);
8968 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8969 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8973 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8976 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8978 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8981 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8982 // cross-half traffic in the final shuffle.
8984 // Munge the mask to be a single-input mask after the unpack merges the
8988 M = 2 * (M % 4) + (M / 8);
8990 return DAG.getVectorShuffle(
8991 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8992 DL, MVT::v8i16, V1, V2),
8993 DAG.getUNDEF(MVT::v8i16), Mask);
8996 /// \brief Generic lowering of 8-lane i16 shuffles.
8998 /// This handles both single-input shuffles and combined shuffle/blends with
8999 /// two inputs. The single input shuffles are immediately delegated to
9000 /// a dedicated lowering routine.
9002 /// The blends are lowered in one of three fundamental ways. If there are few
9003 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9004 /// of the input is significantly cheaper when lowered as an interleaving of
9005 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9006 /// halves of the inputs separately (making them have relatively few inputs)
9007 /// and then concatenate them.
9008 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9009 const X86Subtarget *Subtarget,
9010 SelectionDAG &DAG) {
9012 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9013 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9014 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9015 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9016 ArrayRef<int> OrigMask = SVOp->getMask();
9017 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9018 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9019 MutableArrayRef<int> Mask(MaskStorage);
9021 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9023 // Whenever we can lower this as a zext, that instruction is strictly faster
9024 // than any alternative.
9025 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9026 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9029 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9030 auto isV2 = [](int M) { return M >= 8; };
9032 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9033 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9035 if (NumV2Inputs == 0)
9036 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9038 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9039 "to be V1-input shuffles.");
9041 // There are special ways we can lower some single-element blends.
9042 if (NumV2Inputs == 1)
9043 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9044 Mask, Subtarget, DAG))
9047 if (Subtarget->hasSSE41())
9048 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9052 // Try to use rotation instructions if available.
9053 if (Subtarget->hasSSSE3())
9054 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9055 DL, MVT::v8i16, V1, V2, Mask, DAG))
9058 if (NumV1Inputs + NumV2Inputs <= 4)
9059 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9061 // Check whether an interleaving lowering is likely to be more efficient.
9062 // This isn't perfect but it is a strong heuristic that tends to work well on
9063 // the kinds of shuffles that show up in practice.
9065 // FIXME: Handle 1x, 2x, and 4x interleaving.
9066 if (shouldLowerAsInterleaving(Mask)) {
9067 // FIXME: Figure out whether we should pack these into the low or high
9070 int EMask[8], OMask[8];
9071 for (int i = 0; i < 4; ++i) {
9072 EMask[i] = Mask[2*i];
9073 OMask[i] = Mask[2*i + 1];
9078 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9079 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9081 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9084 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9085 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9087 for (int i = 0; i < 4; ++i) {
9088 LoBlendMask[i] = Mask[i];
9089 HiBlendMask[i] = Mask[i + 4];
9092 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9093 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9094 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9095 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9097 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9098 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9101 /// \brief Check whether a compaction lowering can be done by dropping even
9102 /// elements and compute how many times even elements must be dropped.
9104 /// This handles shuffles which take every Nth element where N is a power of
9105 /// two. Example shuffle masks:
9107 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9108 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9109 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9110 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9111 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9112 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9114 /// Any of these lanes can of course be undef.
9116 /// This routine only supports N <= 3.
9117 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9120 /// \returns N above, or the number of times even elements must be dropped if
9121 /// there is such a number. Otherwise returns zero.
9122 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9123 // Figure out whether we're looping over two inputs or just one.
9124 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9126 // The modulus for the shuffle vector entries is based on whether this is
9127 // a single input or not.
9128 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9129 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9130 "We should only be called with masks with a power-of-2 size!");
9132 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9134 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9135 // and 2^3 simultaneously. This is because we may have ambiguity with
9136 // partially undef inputs.
9137 bool ViableForN[3] = {true, true, true};
9139 for (int i = 0, e = Mask.size(); i < e; ++i) {
9140 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9145 bool IsAnyViable = false;
9146 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9147 if (ViableForN[j]) {
9150 // The shuffle mask must be equal to (i * 2^N) % M.
9151 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9154 ViableForN[j] = false;
9156 // Early exit if we exhaust the possible powers of two.
9161 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9165 // Return 0 as there is no viable power of two.
9169 /// \brief Generic lowering of v16i8 shuffles.
9171 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9172 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9173 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9174 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9176 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9177 const X86Subtarget *Subtarget,
9178 SelectionDAG &DAG) {
9180 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9181 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9182 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9184 ArrayRef<int> OrigMask = SVOp->getMask();
9185 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9187 // Try to use rotation instructions if available.
9188 if (Subtarget->hasSSSE3())
9189 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9190 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9193 // Try to use a zext lowering.
9194 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9195 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9198 int MaskStorage[16] = {
9199 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9200 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9201 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9202 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9203 MutableArrayRef<int> Mask(MaskStorage);
9204 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9205 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9208 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9210 // For single-input shuffles, there are some nicer lowering tricks we can use.
9211 if (NumV2Elements == 0) {
9212 // Check for being able to broadcast a single element.
9213 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9214 Mask, Subtarget, DAG))
9217 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9218 // Notably, this handles splat and partial-splat shuffles more efficiently.
9219 // However, it only makes sense if the pre-duplication shuffle simplifies
9220 // things significantly. Currently, this means we need to be able to
9221 // express the pre-duplication shuffle as an i16 shuffle.
9223 // FIXME: We should check for other patterns which can be widened into an
9224 // i16 shuffle as well.
9225 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9226 for (int i = 0; i < 16; i += 2)
9227 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9232 auto tryToWidenViaDuplication = [&]() -> SDValue {
9233 if (!canWidenViaDuplication(Mask))
9235 SmallVector<int, 4> LoInputs;
9236 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9237 [](int M) { return M >= 0 && M < 8; });
9238 std::sort(LoInputs.begin(), LoInputs.end());
9239 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9241 SmallVector<int, 4> HiInputs;
9242 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9243 [](int M) { return M >= 8; });
9244 std::sort(HiInputs.begin(), HiInputs.end());
9245 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9248 bool TargetLo = LoInputs.size() >= HiInputs.size();
9249 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9250 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9252 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9253 SmallDenseMap<int, int, 8> LaneMap;
9254 for (int I : InPlaceInputs) {
9255 PreDupI16Shuffle[I/2] = I/2;
9258 int j = TargetLo ? 0 : 4, je = j + 4;
9259 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9260 // Check if j is already a shuffle of this input. This happens when
9261 // there are two adjacent bytes after we move the low one.
9262 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9263 // If we haven't yet mapped the input, search for a slot into which
9265 while (j < je && PreDupI16Shuffle[j] != -1)
9269 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9272 // Map this input with the i16 shuffle.
9273 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9276 // Update the lane map based on the mapping we ended up with.
9277 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9280 ISD::BITCAST, DL, MVT::v16i8,
9281 DAG.getVectorShuffle(MVT::v8i16, DL,
9282 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9283 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9285 // Unpack the bytes to form the i16s that will be shuffled into place.
9286 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9287 MVT::v16i8, V1, V1);
9289 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9290 for (int i = 0; i < 16; ++i)
9291 if (Mask[i] != -1) {
9292 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9293 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9294 if (PostDupI16Shuffle[i / 2] == -1)
9295 PostDupI16Shuffle[i / 2] = MappedMask;
9297 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9298 "Conflicting entrties in the original shuffle!");
9301 ISD::BITCAST, DL, MVT::v16i8,
9302 DAG.getVectorShuffle(MVT::v8i16, DL,
9303 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9304 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9306 if (SDValue V = tryToWidenViaDuplication())
9310 // Check whether an interleaving lowering is likely to be more efficient.
9311 // This isn't perfect but it is a strong heuristic that tends to work well on
9312 // the kinds of shuffles that show up in practice.
9314 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9315 if (shouldLowerAsInterleaving(Mask)) {
9316 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9317 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9319 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9320 return (M >= 8 && M < 16) || M >= 24;
9322 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9323 -1, -1, -1, -1, -1, -1, -1, -1};
9324 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9325 -1, -1, -1, -1, -1, -1, -1, -1};
9326 bool UnpackLo = NumLoHalf >= NumHiHalf;
9327 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9328 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9329 for (int i = 0; i < 8; ++i) {
9330 TargetEMask[i] = Mask[2 * i];
9331 TargetOMask[i] = Mask[2 * i + 1];
9334 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9335 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9337 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9338 MVT::v16i8, Evens, Odds);
9341 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9342 // with PSHUFB. It is important to do this before we attempt to generate any
9343 // blends but after all of the single-input lowerings. If the single input
9344 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9345 // want to preserve that and we can DAG combine any longer sequences into
9346 // a PSHUFB in the end. But once we start blending from multiple inputs,
9347 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9348 // and there are *very* few patterns that would actually be faster than the
9349 // PSHUFB approach because of its ability to zero lanes.
9351 // FIXME: The only exceptions to the above are blends which are exact
9352 // interleavings with direct instructions supporting them. We currently don't
9353 // handle those well here.
9354 if (Subtarget->hasSSSE3()) {
9357 for (int i = 0; i < 16; ++i)
9358 if (Mask[i] == -1) {
9359 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9361 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9363 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9365 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9366 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9367 if (isSingleInputShuffleMask(Mask))
9368 return V1; // Single inputs are easy.
9370 // Otherwise, blend the two.
9371 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9372 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9373 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9376 // There are special ways we can lower some single-element blends.
9377 if (NumV2Elements == 1)
9378 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9379 Mask, Subtarget, DAG))
9382 // Check whether a compaction lowering can be done. This handles shuffles
9383 // which take every Nth element for some even N. See the helper function for
9386 // We special case these as they can be particularly efficiently handled with
9387 // the PACKUSB instruction on x86 and they show up in common patterns of
9388 // rearranging bytes to truncate wide elements.
9389 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9390 // NumEvenDrops is the power of two stride of the elements. Another way of
9391 // thinking about it is that we need to drop the even elements this many
9392 // times to get the original input.
9393 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9395 // First we need to zero all the dropped bytes.
9396 assert(NumEvenDrops <= 3 &&
9397 "No support for dropping even elements more than 3 times.");
9398 // We use the mask type to pick which bytes are preserved based on how many
9399 // elements are dropped.
9400 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9401 SDValue ByteClearMask =
9402 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9403 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9404 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9406 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9408 // Now pack things back together.
9409 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9410 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9411 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9412 for (int i = 1; i < NumEvenDrops; ++i) {
9413 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9414 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9420 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9425 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9426 MutableArrayRef<int> V1HalfBlendMask,
9427 MutableArrayRef<int> V2HalfBlendMask) {
9428 for (int i = 0; i < 8; ++i)
9429 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9430 V1HalfBlendMask[i] = HalfMask[i];
9432 } else if (HalfMask[i] >= 16) {
9433 V2HalfBlendMask[i] = HalfMask[i] - 16;
9434 HalfMask[i] = i + 8;
9437 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9438 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9440 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9442 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9443 MutableArrayRef<int> HiBlendMask) {
9445 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9446 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9448 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9449 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9450 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9451 [](int M) { return M >= 0 && M % 2 == 1; })) {
9452 // Use a mask to drop the high bytes.
9453 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9454 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9455 DAG.getConstant(0x00FF, MVT::v8i16));
9457 // This will be a single vector shuffle instead of a blend so nuke V2.
9458 V2 = DAG.getUNDEF(MVT::v8i16);
9460 // Squash the masks to point directly into V1.
9461 for (int &M : LoBlendMask)
9464 for (int &M : HiBlendMask)
9468 // Otherwise just unpack the low half of V into V1 and the high half into
9469 // V2 so that we can blend them as i16s.
9470 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9471 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9472 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9473 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9476 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9477 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9478 return std::make_pair(BlendedLo, BlendedHi);
9480 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9481 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9482 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9484 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9485 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9487 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9490 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9492 /// This routine breaks down the specific type of 128-bit shuffle and
9493 /// dispatches to the lowering routines accordingly.
9494 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9495 MVT VT, const X86Subtarget *Subtarget,
9496 SelectionDAG &DAG) {
9497 switch (VT.SimpleTy) {
9499 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9501 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9503 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9505 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9507 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9509 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9512 llvm_unreachable("Unimplemented!");
9516 /// \brief Helper function to test whether a shuffle mask could be
9517 /// simplified by widening the elements being shuffled.
9519 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9520 /// leaves it in an unspecified state.
9522 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9523 /// shuffle masks. The latter have the special property of a '-2' representing
9524 /// a zero-ed lane of a vector.
9525 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9526 SmallVectorImpl<int> &WidenedMask) {
9527 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9528 // If both elements are undef, its trivial.
9529 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9530 WidenedMask.push_back(SM_SentinelUndef);
9534 // Check for an undef mask and a mask value properly aligned to fit with
9535 // a pair of values. If we find such a case, use the non-undef mask's value.
9536 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9537 WidenedMask.push_back(Mask[i + 1] / 2);
9540 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9541 WidenedMask.push_back(Mask[i] / 2);
9545 // When zeroing, we need to spread the zeroing across both lanes to widen.
9546 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9547 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9548 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9549 WidenedMask.push_back(SM_SentinelZero);
9555 // Finally check if the two mask values are adjacent and aligned with
9557 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9558 WidenedMask.push_back(Mask[i] / 2);
9562 // Otherwise we can't safely widen the elements used in this shuffle.
9565 assert(WidenedMask.size() == Mask.size() / 2 &&
9566 "Incorrect size of mask after widening the elements!");
9571 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9573 /// This routine just extracts two subvectors, shuffles them independently, and
9574 /// then concatenates them back together. This should work effectively with all
9575 /// AVX vector shuffle types.
9576 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9577 SDValue V2, ArrayRef<int> Mask,
9578 SelectionDAG &DAG) {
9579 assert(VT.getSizeInBits() >= 256 &&
9580 "Only for 256-bit or wider vector shuffles!");
9581 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9582 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9584 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9585 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9587 int NumElements = VT.getVectorNumElements();
9588 int SplitNumElements = NumElements / 2;
9589 MVT ScalarVT = VT.getScalarType();
9590 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9592 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9593 DAG.getIntPtrConstant(0));
9594 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9595 DAG.getIntPtrConstant(SplitNumElements));
9596 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9597 DAG.getIntPtrConstant(0));
9598 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9599 DAG.getIntPtrConstant(SplitNumElements));
9601 // Now create two 4-way blends of these half-width vectors.
9602 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9603 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9604 for (int i = 0; i < SplitNumElements; ++i) {
9605 int M = HalfMask[i];
9606 if (M >= NumElements) {
9607 V2BlendMask.push_back(M - NumElements);
9608 V1BlendMask.push_back(-1);
9609 BlendMask.push_back(SplitNumElements + i);
9610 } else if (M >= 0) {
9611 V2BlendMask.push_back(-1);
9612 V1BlendMask.push_back(M);
9613 BlendMask.push_back(i);
9615 V2BlendMask.push_back(-1);
9616 V1BlendMask.push_back(-1);
9617 BlendMask.push_back(-1);
9621 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9623 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9624 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9626 SDValue Lo = HalfBlend(LoMask);
9627 SDValue Hi = HalfBlend(HiMask);
9628 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9631 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9632 /// a permutation and blend of those lanes.
9634 /// This essentially blends the out-of-lane inputs to each lane into the lane
9635 /// from a permuted copy of the vector. This lowering strategy results in four
9636 /// instructions in the worst case for a single-input cross lane shuffle which
9637 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9638 /// of. Special cases for each particular shuffle pattern should be handled
9639 /// prior to trying this lowering.
9640 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9641 SDValue V1, SDValue V2,
9643 SelectionDAG &DAG) {
9644 // FIXME: This should probably be generalized for 512-bit vectors as well.
9645 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9646 int LaneSize = Mask.size() / 2;
9648 // If there are only inputs from one 128-bit lane, splitting will in fact be
9649 // less expensive. The flags track wether the given lane contains an element
9650 // that crosses to another lane.
9651 bool LaneCrossing[2] = {false, false};
9652 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9653 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9654 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9655 if (!LaneCrossing[0] || !LaneCrossing[1])
9656 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9658 if (isSingleInputShuffleMask(Mask)) {
9659 SmallVector<int, 32> FlippedBlendMask;
9660 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9661 FlippedBlendMask.push_back(
9662 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9664 : Mask[i] % LaneSize +
9665 (i / LaneSize) * LaneSize + Size));
9667 // Flip the vector, and blend the results which should now be in-lane. The
9668 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9669 // 5 for the high source. The value 3 selects the high half of source 2 and
9670 // the value 2 selects the low half of source 2. We only use source 2 to
9671 // allow folding it into a memory operand.
9672 unsigned PERMMask = 3 | 2 << 4;
9673 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9674 V1, DAG.getConstant(PERMMask, MVT::i8));
9675 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9678 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9679 // will be handled by the above logic and a blend of the results, much like
9680 // other patterns in AVX.
9681 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9684 /// \brief Handle lowering 2-lane 128-bit shuffles.
9685 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9686 SDValue V2, ArrayRef<int> Mask,
9687 const X86Subtarget *Subtarget,
9688 SelectionDAG &DAG) {
9689 // Blends are faster and handle all the non-lane-crossing cases.
9690 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9694 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9695 VT.getVectorNumElements() / 2);
9696 // Check for patterns which can be matched with a single insert of a 128-bit
9698 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9699 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9700 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9701 DAG.getIntPtrConstant(0));
9702 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9703 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9704 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9706 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9707 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9708 DAG.getIntPtrConstant(0));
9709 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9710 DAG.getIntPtrConstant(2));
9711 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9714 // Otherwise form a 128-bit permutation.
9715 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9716 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9717 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9718 DAG.getConstant(PermMask, MVT::i8));
9721 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9723 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9724 /// isn't available.
9725 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9726 const X86Subtarget *Subtarget,
9727 SelectionDAG &DAG) {
9729 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9730 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9732 ArrayRef<int> Mask = SVOp->getMask();
9733 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9735 SmallVector<int, 4> WidenedMask;
9736 if (canWidenShuffleElements(Mask, WidenedMask))
9737 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9740 if (isSingleInputShuffleMask(Mask)) {
9741 // Check for being able to broadcast a single element.
9742 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9743 Mask, Subtarget, DAG))
9746 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9747 // Non-half-crossing single input shuffles can be lowerid with an
9748 // interleaved permutation.
9749 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9750 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9751 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9752 DAG.getConstant(VPERMILPMask, MVT::i8));
9755 // With AVX2 we have direct support for this permutation.
9756 if (Subtarget->hasAVX2())
9757 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9758 getV4X86ShuffleImm8ForMask(Mask, DAG));
9760 // Otherwise, fall back.
9761 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9765 // X86 has dedicated unpack instructions that can handle specific blend
9766 // operations: UNPCKH and UNPCKL.
9767 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9768 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9769 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9770 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9772 // If we have a single input to the zero element, insert that into V1 if we
9773 // can do so cheaply.
9775 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9776 if (NumV2Elements == 1 && Mask[0] >= 4)
9777 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9778 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9781 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9785 // Check if the blend happens to exactly fit that of SHUFPD.
9786 if ((Mask[0] == -1 || Mask[0] < 2) &&
9787 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9788 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9789 (Mask[3] == -1 || Mask[3] >= 6)) {
9790 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9791 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9792 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9793 DAG.getConstant(SHUFPDMask, MVT::i8));
9795 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9796 (Mask[1] == -1 || Mask[1] < 2) &&
9797 (Mask[2] == -1 || Mask[2] >= 6) &&
9798 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9799 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9800 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9801 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9802 DAG.getConstant(SHUFPDMask, MVT::i8));
9805 // Otherwise fall back on generic blend lowering.
9806 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9810 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9812 /// This routine is only called when we have AVX2 and thus a reasonable
9813 /// instruction set for v4i64 shuffling..
9814 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9815 const X86Subtarget *Subtarget,
9816 SelectionDAG &DAG) {
9818 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9819 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9821 ArrayRef<int> Mask = SVOp->getMask();
9822 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9823 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9825 SmallVector<int, 4> WidenedMask;
9826 if (canWidenShuffleElements(Mask, WidenedMask))
9827 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9830 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9834 // Check for being able to broadcast a single element.
9835 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9836 Mask, Subtarget, DAG))
9839 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9840 // use lower latency instructions that will operate on both 128-bit lanes.
9841 SmallVector<int, 2> RepeatedMask;
9842 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9843 if (isSingleInputShuffleMask(Mask)) {
9844 int PSHUFDMask[] = {-1, -1, -1, -1};
9845 for (int i = 0; i < 2; ++i)
9846 if (RepeatedMask[i] >= 0) {
9847 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9848 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9851 ISD::BITCAST, DL, MVT::v4i64,
9852 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9853 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9854 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9857 // Use dedicated unpack instructions for masks that match their pattern.
9858 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9859 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9860 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9861 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9864 // AVX2 provides a direct instruction for permuting a single input across
9866 if (isSingleInputShuffleMask(Mask))
9867 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9868 getV4X86ShuffleImm8ForMask(Mask, DAG));
9870 // Otherwise fall back on generic blend lowering.
9871 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9875 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9877 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9878 /// isn't available.
9879 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9880 const X86Subtarget *Subtarget,
9881 SelectionDAG &DAG) {
9883 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9884 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9886 ArrayRef<int> Mask = SVOp->getMask();
9887 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9889 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9893 // Check for being able to broadcast a single element.
9894 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9895 Mask, Subtarget, DAG))
9898 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9899 // options to efficiently lower the shuffle.
9900 SmallVector<int, 4> RepeatedMask;
9901 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9902 assert(RepeatedMask.size() == 4 &&
9903 "Repeated masks must be half the mask width!");
9904 if (isSingleInputShuffleMask(Mask))
9905 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9906 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9908 // Use dedicated unpack instructions for masks that match their pattern.
9909 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9910 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9911 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9912 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9914 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9915 // have already handled any direct blends. We also need to squash the
9916 // repeated mask into a simulated v4f32 mask.
9917 for (int i = 0; i < 4; ++i)
9918 if (RepeatedMask[i] >= 8)
9919 RepeatedMask[i] -= 4;
9920 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9923 // If we have a single input shuffle with different shuffle patterns in the
9924 // two 128-bit lanes use the variable mask to VPERMILPS.
9925 if (isSingleInputShuffleMask(Mask)) {
9926 SDValue VPermMask[8];
9927 for (int i = 0; i < 8; ++i)
9928 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9929 : DAG.getConstant(Mask[i], MVT::i32);
9930 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9932 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9933 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9935 if (Subtarget->hasAVX2())
9936 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9937 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9938 DAG.getNode(ISD::BUILD_VECTOR, DL,
9939 MVT::v8i32, VPermMask)),
9942 // Otherwise, fall back.
9943 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9947 // Otherwise fall back on generic blend lowering.
9948 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9952 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9954 /// This routine is only called when we have AVX2 and thus a reasonable
9955 /// instruction set for v8i32 shuffling..
9956 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9957 const X86Subtarget *Subtarget,
9958 SelectionDAG &DAG) {
9960 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9961 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9963 ArrayRef<int> Mask = SVOp->getMask();
9964 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9965 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9967 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9971 // Check for being able to broadcast a single element.
9972 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9973 Mask, Subtarget, DAG))
9976 // If the shuffle mask is repeated in each 128-bit lane we can use more
9977 // efficient instructions that mirror the shuffles across the two 128-bit
9979 SmallVector<int, 4> RepeatedMask;
9980 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9981 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9982 if (isSingleInputShuffleMask(Mask))
9983 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9984 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9986 // Use dedicated unpack instructions for masks that match their pattern.
9987 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9988 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9989 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9990 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9993 // If the shuffle patterns aren't repeated but it is a single input, directly
9994 // generate a cross-lane VPERMD instruction.
9995 if (isSingleInputShuffleMask(Mask)) {
9996 SDValue VPermMask[8];
9997 for (int i = 0; i < 8; ++i)
9998 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9999 : DAG.getConstant(Mask[i], MVT::i32);
10000 return DAG.getNode(
10001 X86ISD::VPERMV, DL, MVT::v8i32,
10002 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10005 // Otherwise fall back on generic blend lowering.
10006 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10010 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10012 /// This routine is only called when we have AVX2 and thus a reasonable
10013 /// instruction set for v16i16 shuffling..
10014 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10015 const X86Subtarget *Subtarget,
10016 SelectionDAG &DAG) {
10018 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10019 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10021 ArrayRef<int> Mask = SVOp->getMask();
10022 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10023 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10025 // Check for being able to broadcast a single element.
10026 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10027 Mask, Subtarget, DAG))
10030 // There are no generalized cross-lane shuffle operations available on i16
10032 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10033 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10036 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10040 // Use dedicated unpack instructions for masks that match their pattern.
10041 if (isShuffleEquivalent(Mask,
10042 // First 128-bit lane:
10043 0, 16, 1, 17, 2, 18, 3, 19,
10044 // Second 128-bit lane:
10045 8, 24, 9, 25, 10, 26, 11, 27))
10046 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10047 if (isShuffleEquivalent(Mask,
10048 // First 128-bit lane:
10049 4, 20, 5, 21, 6, 22, 7, 23,
10050 // Second 128-bit lane:
10051 12, 28, 13, 29, 14, 30, 15, 31))
10052 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10054 if (isSingleInputShuffleMask(Mask)) {
10055 SDValue PSHUFBMask[32];
10056 for (int i = 0; i < 16; ++i) {
10057 if (Mask[i] == -1) {
10058 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10062 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10063 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10064 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10065 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10067 return DAG.getNode(
10068 ISD::BITCAST, DL, MVT::v16i16,
10070 X86ISD::PSHUFB, DL, MVT::v32i8,
10071 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10072 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10075 // Otherwise fall back on generic blend lowering.
10076 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
10080 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10082 /// This routine is only called when we have AVX2 and thus a reasonable
10083 /// instruction set for v32i8 shuffling..
10084 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10085 const X86Subtarget *Subtarget,
10086 SelectionDAG &DAG) {
10088 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10089 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10091 ArrayRef<int> Mask = SVOp->getMask();
10092 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10093 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10095 // Check for being able to broadcast a single element.
10096 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10097 Mask, Subtarget, DAG))
10100 // There are no generalized cross-lane shuffle operations available on i8
10102 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10103 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10106 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10110 // Use dedicated unpack instructions for masks that match their pattern.
10111 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10113 if (isShuffleEquivalent(
10115 // First 128-bit lane:
10116 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10117 // Second 128-bit lane:
10118 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10119 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10120 if (isShuffleEquivalent(
10122 // First 128-bit lane:
10123 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10124 // Second 128-bit lane:
10125 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10126 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10128 if (isSingleInputShuffleMask(Mask)) {
10129 SDValue PSHUFBMask[32];
10130 for (int i = 0; i < 32; ++i)
10133 ? DAG.getUNDEF(MVT::i8)
10134 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10136 return DAG.getNode(
10137 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10138 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10141 // Otherwise fall back on generic blend lowering.
10142 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10146 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10148 /// This routine either breaks down the specific type of a 256-bit x86 vector
10149 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10150 /// together based on the available instructions.
10151 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10152 MVT VT, const X86Subtarget *Subtarget,
10153 SelectionDAG &DAG) {
10155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10156 ArrayRef<int> Mask = SVOp->getMask();
10158 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10159 // check for those subtargets here and avoid much of the subtarget querying in
10160 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10161 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10162 // floating point types there eventually, just immediately cast everything to
10163 // a float and operate entirely in that domain.
10164 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10165 int ElementBits = VT.getScalarSizeInBits();
10166 if (ElementBits < 32)
10167 // No floating point type available, decompose into 128-bit vectors.
10168 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10170 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10171 VT.getVectorNumElements());
10172 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10173 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10174 return DAG.getNode(ISD::BITCAST, DL, VT,
10175 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10178 switch (VT.SimpleTy) {
10180 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10182 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10184 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10186 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10188 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10190 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10193 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10197 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10198 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10199 const X86Subtarget *Subtarget,
10200 SelectionDAG &DAG) {
10202 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10203 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10204 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10205 ArrayRef<int> Mask = SVOp->getMask();
10206 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10208 // FIXME: Implement direct support for this type!
10209 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10212 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10213 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10214 const X86Subtarget *Subtarget,
10215 SelectionDAG &DAG) {
10217 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10218 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10219 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10220 ArrayRef<int> Mask = SVOp->getMask();
10221 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10223 // FIXME: Implement direct support for this type!
10224 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10227 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10228 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10229 const X86Subtarget *Subtarget,
10230 SelectionDAG &DAG) {
10232 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10233 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10234 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10235 ArrayRef<int> Mask = SVOp->getMask();
10236 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10237 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10239 // FIXME: Implement direct support for this type!
10240 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10243 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10244 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10245 const X86Subtarget *Subtarget,
10246 SelectionDAG &DAG) {
10248 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10249 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10251 ArrayRef<int> Mask = SVOp->getMask();
10252 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10253 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10255 // FIXME: Implement direct support for this type!
10256 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10259 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10260 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10261 const X86Subtarget *Subtarget,
10262 SelectionDAG &DAG) {
10264 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10265 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10266 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10267 ArrayRef<int> Mask = SVOp->getMask();
10268 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10269 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10271 // FIXME: Implement direct support for this type!
10272 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10275 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10276 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10277 const X86Subtarget *Subtarget,
10278 SelectionDAG &DAG) {
10280 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10281 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10282 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10283 ArrayRef<int> Mask = SVOp->getMask();
10284 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10285 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10287 // FIXME: Implement direct support for this type!
10288 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10291 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10293 /// This routine either breaks down the specific type of a 512-bit x86 vector
10294 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10295 /// together based on the available instructions.
10296 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10297 MVT VT, const X86Subtarget *Subtarget,
10298 SelectionDAG &DAG) {
10300 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10301 ArrayRef<int> Mask = SVOp->getMask();
10302 assert(Subtarget->hasAVX512() &&
10303 "Cannot lower 512-bit vectors w/ basic ISA!");
10305 // Dispatch to each element type for lowering. If we don't have supprot for
10306 // specific element type shuffles at 512 bits, immediately split them and
10307 // lower them. Each lowering routine of a given type is allowed to assume that
10308 // the requisite ISA extensions for that element type are available.
10309 switch (VT.SimpleTy) {
10311 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10313 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10315 if (Subtarget->hasDQI())
10316 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10319 if (Subtarget->hasDQI())
10320 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10323 if (Subtarget->hasBWI())
10324 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10327 if (Subtarget->hasBWI())
10328 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10332 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10335 // Otherwise fall back on splitting.
10336 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10339 /// \brief Top-level lowering for x86 vector shuffles.
10341 /// This handles decomposition, canonicalization, and lowering of all x86
10342 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10343 /// above in helper routines. The canonicalization attempts to widen shuffles
10344 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10345 /// s.t. only one of the two inputs needs to be tested, etc.
10346 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10347 SelectionDAG &DAG) {
10348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10349 ArrayRef<int> Mask = SVOp->getMask();
10350 SDValue V1 = Op.getOperand(0);
10351 SDValue V2 = Op.getOperand(1);
10352 MVT VT = Op.getSimpleValueType();
10353 int NumElements = VT.getVectorNumElements();
10356 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10358 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10359 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10360 if (V1IsUndef && V2IsUndef)
10361 return DAG.getUNDEF(VT);
10363 // When we create a shuffle node we put the UNDEF node to second operand,
10364 // but in some cases the first operand may be transformed to UNDEF.
10365 // In this case we should just commute the node.
10367 return DAG.getCommutedVectorShuffle(*SVOp);
10369 // Check for non-undef masks pointing at an undef vector and make the masks
10370 // undef as well. This makes it easier to match the shuffle based solely on
10374 if (M >= NumElements) {
10375 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10376 for (int &M : NewMask)
10377 if (M >= NumElements)
10379 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10382 // Try to collapse shuffles into using a vector type with fewer elements but
10383 // wider element types. We cap this to not form integers or floating point
10384 // elements wider than 64 bits, but it might be interesting to form i128
10385 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10386 SmallVector<int, 16> WidenedMask;
10387 if (VT.getScalarSizeInBits() < 64 &&
10388 canWidenShuffleElements(Mask, WidenedMask)) {
10389 MVT NewEltVT = VT.isFloatingPoint()
10390 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10391 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10392 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10393 // Make sure that the new vector type is legal. For example, v2f64 isn't
10395 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10396 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10397 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10398 return DAG.getNode(ISD::BITCAST, dl, VT,
10399 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10403 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10404 for (int M : SVOp->getMask())
10406 ++NumUndefElements;
10407 else if (M < NumElements)
10412 // Commute the shuffle as needed such that more elements come from V1 than
10413 // V2. This allows us to match the shuffle pattern strictly on how many
10414 // elements come from V1 without handling the symmetric cases.
10415 if (NumV2Elements > NumV1Elements)
10416 return DAG.getCommutedVectorShuffle(*SVOp);
10418 // When the number of V1 and V2 elements are the same, try to minimize the
10419 // number of uses of V2 in the low half of the vector. When that is tied,
10420 // ensure that the sum of indices for V1 is equal to or lower than the sum
10422 if (NumV1Elements == NumV2Elements) {
10423 int LowV1Elements = 0, LowV2Elements = 0;
10424 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10425 if (M >= NumElements)
10429 if (LowV2Elements > LowV1Elements) {
10430 return DAG.getCommutedVectorShuffle(*SVOp);
10431 } else if (LowV2Elements == LowV1Elements) {
10432 int SumV1Indices = 0, SumV2Indices = 0;
10433 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10434 if (SVOp->getMask()[i] >= NumElements)
10436 else if (SVOp->getMask()[i] >= 0)
10438 if (SumV2Indices < SumV1Indices)
10439 return DAG.getCommutedVectorShuffle(*SVOp);
10443 // For each vector width, delegate to a specialized lowering routine.
10444 if (VT.getSizeInBits() == 128)
10445 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10447 if (VT.getSizeInBits() == 256)
10448 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10450 // Force AVX-512 vectors to be scalarized for now.
10451 // FIXME: Implement AVX-512 support!
10452 if (VT.getSizeInBits() == 512)
10453 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10455 llvm_unreachable("Unimplemented!");
10459 //===----------------------------------------------------------------------===//
10460 // Legacy vector shuffle lowering
10462 // This code is the legacy code handling vector shuffles until the above
10463 // replaces its functionality and performance.
10464 //===----------------------------------------------------------------------===//
10466 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10467 bool hasInt256, unsigned *MaskOut = nullptr) {
10468 MVT EltVT = VT.getVectorElementType();
10470 // There is no blend with immediate in AVX-512.
10471 if (VT.is512BitVector())
10474 if (!hasSSE41 || EltVT == MVT::i8)
10476 if (!hasInt256 && VT == MVT::v16i16)
10479 unsigned MaskValue = 0;
10480 unsigned NumElems = VT.getVectorNumElements();
10481 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10482 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10483 unsigned NumElemsInLane = NumElems / NumLanes;
10485 // Blend for v16i16 should be symetric for the both lanes.
10486 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10488 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10489 int EltIdx = MaskVals[i];
10491 if ((EltIdx < 0 || EltIdx == (int)i) &&
10492 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10495 if (((unsigned)EltIdx == (i + NumElems)) &&
10496 (SndLaneEltIdx < 0 ||
10497 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10498 MaskValue |= (1 << i);
10504 *MaskOut = MaskValue;
10508 // Try to lower a shuffle node into a simple blend instruction.
10509 // This function assumes isBlendMask returns true for this
10510 // SuffleVectorSDNode
10511 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10512 unsigned MaskValue,
10513 const X86Subtarget *Subtarget,
10514 SelectionDAG &DAG) {
10515 MVT VT = SVOp->getSimpleValueType(0);
10516 MVT EltVT = VT.getVectorElementType();
10517 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10518 Subtarget->hasInt256() && "Trying to lower a "
10519 "VECTOR_SHUFFLE to a Blend but "
10520 "with the wrong mask"));
10521 SDValue V1 = SVOp->getOperand(0);
10522 SDValue V2 = SVOp->getOperand(1);
10524 unsigned NumElems = VT.getVectorNumElements();
10526 // Convert i32 vectors to floating point if it is not AVX2.
10527 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10529 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10530 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10532 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10533 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10536 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10537 DAG.getConstant(MaskValue, MVT::i32));
10538 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10541 /// In vector type \p VT, return true if the element at index \p InputIdx
10542 /// falls on a different 128-bit lane than \p OutputIdx.
10543 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10544 unsigned OutputIdx) {
10545 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10546 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10549 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10550 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10551 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10552 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10554 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10555 SelectionDAG &DAG) {
10556 MVT VT = V1.getSimpleValueType();
10557 assert(VT.is128BitVector() || VT.is256BitVector());
10559 MVT EltVT = VT.getVectorElementType();
10560 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10561 unsigned NumElts = VT.getVectorNumElements();
10563 SmallVector<SDValue, 32> PshufbMask;
10564 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10565 int InputIdx = MaskVals[OutputIdx];
10566 unsigned InputByteIdx;
10568 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10569 InputByteIdx = 0x80;
10571 // Cross lane is not allowed.
10572 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10574 InputByteIdx = InputIdx * EltSizeInBytes;
10575 // Index is an byte offset within the 128-bit lane.
10576 InputByteIdx &= 0xf;
10579 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10580 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10581 if (InputByteIdx != 0x80)
10586 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10588 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10589 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10590 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10593 // v8i16 shuffles - Prefer shuffles in the following order:
10594 // 1. [all] pshuflw, pshufhw, optional move
10595 // 2. [ssse3] 1 x pshufb
10596 // 3. [ssse3] 2 x pshufb + 1 x por
10597 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10599 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10600 SelectionDAG &DAG) {
10601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10602 SDValue V1 = SVOp->getOperand(0);
10603 SDValue V2 = SVOp->getOperand(1);
10605 SmallVector<int, 8> MaskVals;
10607 // Determine if more than 1 of the words in each of the low and high quadwords
10608 // of the result come from the same quadword of one of the two inputs. Undef
10609 // mask values count as coming from any quadword, for better codegen.
10611 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10612 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10613 unsigned LoQuad[] = { 0, 0, 0, 0 };
10614 unsigned HiQuad[] = { 0, 0, 0, 0 };
10615 // Indices of quads used.
10616 std::bitset<4> InputQuads;
10617 for (unsigned i = 0; i < 8; ++i) {
10618 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10619 int EltIdx = SVOp->getMaskElt(i);
10620 MaskVals.push_back(EltIdx);
10628 ++Quad[EltIdx / 4];
10629 InputQuads.set(EltIdx / 4);
10632 int BestLoQuad = -1;
10633 unsigned MaxQuad = 1;
10634 for (unsigned i = 0; i < 4; ++i) {
10635 if (LoQuad[i] > MaxQuad) {
10637 MaxQuad = LoQuad[i];
10641 int BestHiQuad = -1;
10643 for (unsigned i = 0; i < 4; ++i) {
10644 if (HiQuad[i] > MaxQuad) {
10646 MaxQuad = HiQuad[i];
10650 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10651 // of the two input vectors, shuffle them into one input vector so only a
10652 // single pshufb instruction is necessary. If there are more than 2 input
10653 // quads, disable the next transformation since it does not help SSSE3.
10654 bool V1Used = InputQuads[0] || InputQuads[1];
10655 bool V2Used = InputQuads[2] || InputQuads[3];
10656 if (Subtarget->hasSSSE3()) {
10657 if (InputQuads.count() == 2 && V1Used && V2Used) {
10658 BestLoQuad = InputQuads[0] ? 0 : 1;
10659 BestHiQuad = InputQuads[2] ? 2 : 3;
10661 if (InputQuads.count() > 2) {
10667 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10668 // the shuffle mask. If a quad is scored as -1, that means that it contains
10669 // words from all 4 input quadwords.
10671 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10673 BestLoQuad < 0 ? 0 : BestLoQuad,
10674 BestHiQuad < 0 ? 1 : BestHiQuad
10676 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10678 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10679 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10681 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10682 // source words for the shuffle, to aid later transformations.
10683 bool AllWordsInNewV = true;
10684 bool InOrder[2] = { true, true };
10685 for (unsigned i = 0; i != 8; ++i) {
10686 int idx = MaskVals[i];
10688 InOrder[i/4] = false;
10689 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10691 AllWordsInNewV = false;
10695 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10696 if (AllWordsInNewV) {
10697 for (int i = 0; i != 8; ++i) {
10698 int idx = MaskVals[i];
10701 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10702 if ((idx != i) && idx < 4)
10704 if ((idx != i) && idx > 3)
10713 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10714 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10715 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10716 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10717 unsigned TargetMask = 0;
10718 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10719 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10720 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10721 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10722 getShufflePSHUFLWImmediate(SVOp);
10723 V1 = NewV.getOperand(0);
10724 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10728 // Promote splats to a larger type which usually leads to more efficient code.
10729 // FIXME: Is this true if pshufb is available?
10730 if (SVOp->isSplat())
10731 return PromoteSplat(SVOp, DAG);
10733 // If we have SSSE3, and all words of the result are from 1 input vector,
10734 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10735 // is present, fall back to case 4.
10736 if (Subtarget->hasSSSE3()) {
10737 SmallVector<SDValue,16> pshufbMask;
10739 // If we have elements from both input vectors, set the high bit of the
10740 // shuffle mask element to zero out elements that come from V2 in the V1
10741 // mask, and elements that come from V1 in the V2 mask, so that the two
10742 // results can be OR'd together.
10743 bool TwoInputs = V1Used && V2Used;
10744 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10746 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10748 // Calculate the shuffle mask for the second input, shuffle it, and
10749 // OR it with the first shuffled input.
10750 CommuteVectorShuffleMask(MaskVals, 8);
10751 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10752 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10753 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10756 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10757 // and update MaskVals with new element order.
10758 std::bitset<8> InOrder;
10759 if (BestLoQuad >= 0) {
10760 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10761 for (int i = 0; i != 4; ++i) {
10762 int idx = MaskVals[i];
10765 } else if ((idx / 4) == BestLoQuad) {
10766 MaskV[i] = idx & 3;
10770 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10773 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10775 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10776 NewV.getOperand(0),
10777 getShufflePSHUFLWImmediate(SVOp), DAG);
10781 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10782 // and update MaskVals with the new element order.
10783 if (BestHiQuad >= 0) {
10784 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10785 for (unsigned i = 4; i != 8; ++i) {
10786 int idx = MaskVals[i];
10789 } else if ((idx / 4) == BestHiQuad) {
10790 MaskV[i] = (idx & 3) + 4;
10794 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10797 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10799 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10800 NewV.getOperand(0),
10801 getShufflePSHUFHWImmediate(SVOp), DAG);
10805 // In case BestHi & BestLo were both -1, which means each quadword has a word
10806 // from each of the four input quadwords, calculate the InOrder bitvector now
10807 // before falling through to the insert/extract cleanup.
10808 if (BestLoQuad == -1 && BestHiQuad == -1) {
10810 for (int i = 0; i != 8; ++i)
10811 if (MaskVals[i] < 0 || MaskVals[i] == i)
10815 // The other elements are put in the right place using pextrw and pinsrw.
10816 for (unsigned i = 0; i != 8; ++i) {
10819 int EltIdx = MaskVals[i];
10822 SDValue ExtOp = (EltIdx < 8) ?
10823 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10824 DAG.getIntPtrConstant(EltIdx)) :
10825 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10826 DAG.getIntPtrConstant(EltIdx - 8));
10827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10828 DAG.getIntPtrConstant(i));
10833 /// \brief v16i16 shuffles
10835 /// FIXME: We only support generation of a single pshufb currently. We can
10836 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10837 /// well (e.g 2 x pshufb + 1 x por).
10839 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10840 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10841 SDValue V1 = SVOp->getOperand(0);
10842 SDValue V2 = SVOp->getOperand(1);
10845 if (V2.getOpcode() != ISD::UNDEF)
10848 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10849 return getPSHUFB(MaskVals, V1, dl, DAG);
10852 // v16i8 shuffles - Prefer shuffles in the following order:
10853 // 1. [ssse3] 1 x pshufb
10854 // 2. [ssse3] 2 x pshufb + 1 x por
10855 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10856 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10857 const X86Subtarget* Subtarget,
10858 SelectionDAG &DAG) {
10859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10860 SDValue V1 = SVOp->getOperand(0);
10861 SDValue V2 = SVOp->getOperand(1);
10863 ArrayRef<int> MaskVals = SVOp->getMask();
10865 // Promote splats to a larger type which usually leads to more efficient code.
10866 // FIXME: Is this true if pshufb is available?
10867 if (SVOp->isSplat())
10868 return PromoteSplat(SVOp, DAG);
10870 // If we have SSSE3, case 1 is generated when all result bytes come from
10871 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10872 // present, fall back to case 3.
10874 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10875 if (Subtarget->hasSSSE3()) {
10876 SmallVector<SDValue,16> pshufbMask;
10878 // If all result elements are from one input vector, then only translate
10879 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10881 // Otherwise, we have elements from both input vectors, and must zero out
10882 // elements that come from V2 in the first mask, and V1 in the second mask
10883 // so that we can OR them together.
10884 for (unsigned i = 0; i != 16; ++i) {
10885 int EltIdx = MaskVals[i];
10886 if (EltIdx < 0 || EltIdx >= 16)
10888 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10890 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10891 DAG.getNode(ISD::BUILD_VECTOR, dl,
10892 MVT::v16i8, pshufbMask));
10894 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10895 // the 2nd operand if it's undefined or zero.
10896 if (V2.getOpcode() == ISD::UNDEF ||
10897 ISD::isBuildVectorAllZeros(V2.getNode()))
10900 // Calculate the shuffle mask for the second input, shuffle it, and
10901 // OR it with the first shuffled input.
10902 pshufbMask.clear();
10903 for (unsigned i = 0; i != 16; ++i) {
10904 int EltIdx = MaskVals[i];
10905 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10906 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10908 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10909 DAG.getNode(ISD::BUILD_VECTOR, dl,
10910 MVT::v16i8, pshufbMask));
10911 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10914 // No SSSE3 - Calculate in place words and then fix all out of place words
10915 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10916 // the 16 different words that comprise the two doublequadword input vectors.
10917 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10918 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10920 for (int i = 0; i != 8; ++i) {
10921 int Elt0 = MaskVals[i*2];
10922 int Elt1 = MaskVals[i*2+1];
10924 // This word of the result is all undef, skip it.
10925 if (Elt0 < 0 && Elt1 < 0)
10928 // This word of the result is already in the correct place, skip it.
10929 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10932 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10933 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10936 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10937 // using a single extract together, load it and store it.
10938 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10939 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10940 DAG.getIntPtrConstant(Elt1 / 2));
10941 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10942 DAG.getIntPtrConstant(i));
10946 // If Elt1 is defined, extract it from the appropriate source. If the
10947 // source byte is not also odd, shift the extracted word left 8 bits
10948 // otherwise clear the bottom 8 bits if we need to do an or.
10950 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10951 DAG.getIntPtrConstant(Elt1 / 2));
10952 if ((Elt1 & 1) == 0)
10953 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10955 TLI.getShiftAmountTy(InsElt.getValueType())));
10956 else if (Elt0 >= 0)
10957 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10958 DAG.getConstant(0xFF00, MVT::i16));
10960 // If Elt0 is defined, extract it from the appropriate source. If the
10961 // source byte is not also even, shift the extracted word right 8 bits. If
10962 // Elt1 was also defined, OR the extracted values together before
10963 // inserting them in the result.
10965 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10966 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10967 if ((Elt0 & 1) != 0)
10968 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10970 TLI.getShiftAmountTy(InsElt0.getValueType())));
10971 else if (Elt1 >= 0)
10972 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10973 DAG.getConstant(0x00FF, MVT::i16));
10974 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10977 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10978 DAG.getIntPtrConstant(i));
10980 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10983 // v32i8 shuffles - Translate to VPSHUFB if possible.
10985 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10986 const X86Subtarget *Subtarget,
10987 SelectionDAG &DAG) {
10988 MVT VT = SVOp->getSimpleValueType(0);
10989 SDValue V1 = SVOp->getOperand(0);
10990 SDValue V2 = SVOp->getOperand(1);
10992 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10994 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10995 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10996 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10998 // VPSHUFB may be generated if
10999 // (1) one of input vector is undefined or zeroinitializer.
11000 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11001 // And (2) the mask indexes don't cross the 128-bit lane.
11002 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11003 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11006 if (V1IsAllZero && !V2IsAllZero) {
11007 CommuteVectorShuffleMask(MaskVals, 32);
11010 return getPSHUFB(MaskVals, V1, dl, DAG);
11013 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11014 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11015 /// done when every pair / quad of shuffle mask elements point to elements in
11016 /// the right sequence. e.g.
11017 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11019 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11020 SelectionDAG &DAG) {
11021 MVT VT = SVOp->getSimpleValueType(0);
11023 unsigned NumElems = VT.getVectorNumElements();
11026 switch (VT.SimpleTy) {
11027 default: llvm_unreachable("Unexpected!");
11030 return SDValue(SVOp, 0);
11031 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11032 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11033 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11034 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11035 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11036 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11039 SmallVector<int, 8> MaskVec;
11040 for (unsigned i = 0; i != NumElems; i += Scale) {
11042 for (unsigned j = 0; j != Scale; ++j) {
11043 int EltIdx = SVOp->getMaskElt(i+j);
11047 StartIdx = (EltIdx / Scale);
11048 if (EltIdx != (int)(StartIdx*Scale + j))
11051 MaskVec.push_back(StartIdx);
11054 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11055 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11056 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11059 /// getVZextMovL - Return a zero-extending vector move low node.
11061 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11062 SDValue SrcOp, SelectionDAG &DAG,
11063 const X86Subtarget *Subtarget, SDLoc dl) {
11064 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11065 LoadSDNode *LD = nullptr;
11066 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11067 LD = dyn_cast<LoadSDNode>(SrcOp);
11069 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11071 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11072 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11073 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11074 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11075 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11077 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11078 return DAG.getNode(ISD::BITCAST, dl, VT,
11079 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11080 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11082 SrcOp.getOperand(0)
11088 return DAG.getNode(ISD::BITCAST, dl, VT,
11089 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11090 DAG.getNode(ISD::BITCAST, dl,
11094 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11095 /// which could not be matched by any known target speficic shuffle
11097 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11099 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11100 if (NewOp.getNode())
11103 MVT VT = SVOp->getSimpleValueType(0);
11105 unsigned NumElems = VT.getVectorNumElements();
11106 unsigned NumLaneElems = NumElems / 2;
11109 MVT EltVT = VT.getVectorElementType();
11110 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11113 SmallVector<int, 16> Mask;
11114 for (unsigned l = 0; l < 2; ++l) {
11115 // Build a shuffle mask for the output, discovering on the fly which
11116 // input vectors to use as shuffle operands (recorded in InputUsed).
11117 // If building a suitable shuffle vector proves too hard, then bail
11118 // out with UseBuildVector set.
11119 bool UseBuildVector = false;
11120 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11121 unsigned LaneStart = l * NumLaneElems;
11122 for (unsigned i = 0; i != NumLaneElems; ++i) {
11123 // The mask element. This indexes into the input.
11124 int Idx = SVOp->getMaskElt(i+LaneStart);
11126 // the mask element does not index into any input vector.
11127 Mask.push_back(-1);
11131 // The input vector this mask element indexes into.
11132 int Input = Idx / NumLaneElems;
11134 // Turn the index into an offset from the start of the input vector.
11135 Idx -= Input * NumLaneElems;
11137 // Find or create a shuffle vector operand to hold this input.
11139 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11140 if (InputUsed[OpNo] == Input)
11141 // This input vector is already an operand.
11143 if (InputUsed[OpNo] < 0) {
11144 // Create a new operand for this input vector.
11145 InputUsed[OpNo] = Input;
11150 if (OpNo >= array_lengthof(InputUsed)) {
11151 // More than two input vectors used! Give up on trying to create a
11152 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11153 UseBuildVector = true;
11157 // Add the mask index for the new shuffle vector.
11158 Mask.push_back(Idx + OpNo * NumLaneElems);
11161 if (UseBuildVector) {
11162 SmallVector<SDValue, 16> SVOps;
11163 for (unsigned i = 0; i != NumLaneElems; ++i) {
11164 // The mask element. This indexes into the input.
11165 int Idx = SVOp->getMaskElt(i+LaneStart);
11167 SVOps.push_back(DAG.getUNDEF(EltVT));
11171 // The input vector this mask element indexes into.
11172 int Input = Idx / NumElems;
11174 // Turn the index into an offset from the start of the input vector.
11175 Idx -= Input * NumElems;
11177 // Extract the vector element by hand.
11178 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11179 SVOp->getOperand(Input),
11180 DAG.getIntPtrConstant(Idx)));
11183 // Construct the output using a BUILD_VECTOR.
11184 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11185 } else if (InputUsed[0] < 0) {
11186 // No input vectors were used! The result is undefined.
11187 Output[l] = DAG.getUNDEF(NVT);
11189 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11190 (InputUsed[0] % 2) * NumLaneElems,
11192 // If only one input was used, use an undefined vector for the other.
11193 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11194 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11195 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11196 // At least one input vector was used. Create a new shuffle vector.
11197 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11203 // Concatenate the result back
11204 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11207 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11208 /// 4 elements, and match them with several different shuffle types.
11210 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11211 SDValue V1 = SVOp->getOperand(0);
11212 SDValue V2 = SVOp->getOperand(1);
11214 MVT VT = SVOp->getSimpleValueType(0);
11216 assert(VT.is128BitVector() && "Unsupported vector size");
11218 std::pair<int, int> Locs[4];
11219 int Mask1[] = { -1, -1, -1, -1 };
11220 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11222 unsigned NumHi = 0;
11223 unsigned NumLo = 0;
11224 for (unsigned i = 0; i != 4; ++i) {
11225 int Idx = PermMask[i];
11227 Locs[i] = std::make_pair(-1, -1);
11229 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11231 Locs[i] = std::make_pair(0, NumLo);
11232 Mask1[NumLo] = Idx;
11235 Locs[i] = std::make_pair(1, NumHi);
11237 Mask1[2+NumHi] = Idx;
11243 if (NumLo <= 2 && NumHi <= 2) {
11244 // If no more than two elements come from either vector. This can be
11245 // implemented with two shuffles. First shuffle gather the elements.
11246 // The second shuffle, which takes the first shuffle as both of its
11247 // vector operands, put the elements into the right order.
11248 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11250 int Mask2[] = { -1, -1, -1, -1 };
11252 for (unsigned i = 0; i != 4; ++i)
11253 if (Locs[i].first != -1) {
11254 unsigned Idx = (i < 2) ? 0 : 4;
11255 Idx += Locs[i].first * 2 + Locs[i].second;
11259 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11262 if (NumLo == 3 || NumHi == 3) {
11263 // Otherwise, we must have three elements from one vector, call it X, and
11264 // one element from the other, call it Y. First, use a shufps to build an
11265 // intermediate vector with the one element from Y and the element from X
11266 // that will be in the same half in the final destination (the indexes don't
11267 // matter). Then, use a shufps to build the final vector, taking the half
11268 // containing the element from Y from the intermediate, and the other half
11271 // Normalize it so the 3 elements come from V1.
11272 CommuteVectorShuffleMask(PermMask, 4);
11276 // Find the element from V2.
11278 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11279 int Val = PermMask[HiIndex];
11286 Mask1[0] = PermMask[HiIndex];
11288 Mask1[2] = PermMask[HiIndex^1];
11290 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11292 if (HiIndex >= 2) {
11293 Mask1[0] = PermMask[0];
11294 Mask1[1] = PermMask[1];
11295 Mask1[2] = HiIndex & 1 ? 6 : 4;
11296 Mask1[3] = HiIndex & 1 ? 4 : 6;
11297 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11300 Mask1[0] = HiIndex & 1 ? 2 : 0;
11301 Mask1[1] = HiIndex & 1 ? 0 : 2;
11302 Mask1[2] = PermMask[2];
11303 Mask1[3] = PermMask[3];
11308 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11311 // Break it into (shuffle shuffle_hi, shuffle_lo).
11312 int LoMask[] = { -1, -1, -1, -1 };
11313 int HiMask[] = { -1, -1, -1, -1 };
11315 int *MaskPtr = LoMask;
11316 unsigned MaskIdx = 0;
11317 unsigned LoIdx = 0;
11318 unsigned HiIdx = 2;
11319 for (unsigned i = 0; i != 4; ++i) {
11326 int Idx = PermMask[i];
11328 Locs[i] = std::make_pair(-1, -1);
11329 } else if (Idx < 4) {
11330 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11331 MaskPtr[LoIdx] = Idx;
11334 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11335 MaskPtr[HiIdx] = Idx;
11340 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11341 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11342 int MaskOps[] = { -1, -1, -1, -1 };
11343 for (unsigned i = 0; i != 4; ++i)
11344 if (Locs[i].first != -1)
11345 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11346 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11349 static bool MayFoldVectorLoad(SDValue V) {
11350 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11351 V = V.getOperand(0);
11353 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11354 V = V.getOperand(0);
11355 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11356 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11357 // BUILD_VECTOR (load), undef
11358 V = V.getOperand(0);
11360 return MayFoldLoad(V);
11364 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11365 MVT VT = Op.getSimpleValueType();
11367 // Canonizalize to v2f64.
11368 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11369 return DAG.getNode(ISD::BITCAST, dl, VT,
11370 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11375 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11377 SDValue V1 = Op.getOperand(0);
11378 SDValue V2 = Op.getOperand(1);
11379 MVT VT = Op.getSimpleValueType();
11381 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11383 if (HasSSE2 && VT == MVT::v2f64)
11384 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11386 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11387 return DAG.getNode(ISD::BITCAST, dl, VT,
11388 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11389 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11390 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11394 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11395 SDValue V1 = Op.getOperand(0);
11396 SDValue V2 = Op.getOperand(1);
11397 MVT VT = Op.getSimpleValueType();
11399 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11400 "unsupported shuffle type");
11402 if (V2.getOpcode() == ISD::UNDEF)
11406 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11410 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11411 SDValue V1 = Op.getOperand(0);
11412 SDValue V2 = Op.getOperand(1);
11413 MVT VT = Op.getSimpleValueType();
11414 unsigned NumElems = VT.getVectorNumElements();
11416 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11417 // operand of these instructions is only memory, so check if there's a
11418 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11420 bool CanFoldLoad = false;
11422 // Trivial case, when V2 comes from a load.
11423 if (MayFoldVectorLoad(V2))
11424 CanFoldLoad = true;
11426 // When V1 is a load, it can be folded later into a store in isel, example:
11427 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11429 // (MOVLPSmr addr:$src1, VR128:$src2)
11430 // So, recognize this potential and also use MOVLPS or MOVLPD
11431 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11432 CanFoldLoad = true;
11434 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11436 if (HasSSE2 && NumElems == 2)
11437 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11440 // If we don't care about the second element, proceed to use movss.
11441 if (SVOp->getMaskElt(1) != -1)
11442 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11445 // movl and movlp will both match v2i64, but v2i64 is never matched by
11446 // movl earlier because we make it strict to avoid messing with the movlp load
11447 // folding logic (see the code above getMOVLP call). Match it here then,
11448 // this is horrible, but will stay like this until we move all shuffle
11449 // matching to x86 specific nodes. Note that for the 1st condition all
11450 // types are matched with movsd.
11452 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11453 // as to remove this logic from here, as much as possible
11454 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11455 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11456 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11459 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11461 // Invert the operand order and use SHUFPS to match it.
11462 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11463 getShuffleSHUFImmediate(SVOp), DAG);
11466 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11467 SelectionDAG &DAG) {
11469 MVT VT = Load->getSimpleValueType(0);
11470 MVT EVT = VT.getVectorElementType();
11471 SDValue Addr = Load->getOperand(1);
11472 SDValue NewAddr = DAG.getNode(
11473 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11474 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11477 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11478 DAG.getMachineFunction().getMachineMemOperand(
11479 Load->getMemOperand(), 0, EVT.getStoreSize()));
11483 // It is only safe to call this function if isINSERTPSMask is true for
11484 // this shufflevector mask.
11485 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11486 SelectionDAG &DAG) {
11487 // Generate an insertps instruction when inserting an f32 from memory onto a
11488 // v4f32 or when copying a member from one v4f32 to another.
11489 // We also use it for transferring i32 from one register to another,
11490 // since it simply copies the same bits.
11491 // If we're transferring an i32 from memory to a specific element in a
11492 // register, we output a generic DAG that will match the PINSRD
11494 MVT VT = SVOp->getSimpleValueType(0);
11495 MVT EVT = VT.getVectorElementType();
11496 SDValue V1 = SVOp->getOperand(0);
11497 SDValue V2 = SVOp->getOperand(1);
11498 auto Mask = SVOp->getMask();
11499 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11500 "unsupported vector type for insertps/pinsrd");
11502 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11503 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11504 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11508 unsigned DestIndex;
11512 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11515 // If we have 1 element from each vector, we have to check if we're
11516 // changing V1's element's place. If so, we're done. Otherwise, we
11517 // should assume we're changing V2's element's place and behave
11519 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11520 assert(DestIndex <= INT32_MAX && "truncated destination index");
11521 if (FromV1 == FromV2 &&
11522 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11526 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11529 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11530 "More than one element from V1 and from V2, or no elements from one "
11531 "of the vectors. This case should not have returned true from "
11536 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11539 // Get an index into the source vector in the range [0,4) (the mask is
11540 // in the range [0,8) because it can address V1 and V2)
11541 unsigned SrcIndex = Mask[DestIndex] % 4;
11542 if (MayFoldLoad(From)) {
11543 // Trivial case, when From comes from a load and is only used by the
11544 // shuffle. Make it use insertps from the vector that we need from that
11547 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11548 if (!NewLoad.getNode())
11551 if (EVT == MVT::f32) {
11552 // Create this as a scalar to vector to match the instruction pattern.
11553 SDValue LoadScalarToVector =
11554 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11555 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11556 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11558 } else { // EVT == MVT::i32
11559 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11560 // instruction, to match the PINSRD instruction, which loads an i32 to a
11561 // certain vector element.
11562 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11563 DAG.getConstant(DestIndex, MVT::i32));
11567 // Vector-element-to-vector
11568 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11569 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11572 // Reduce a vector shuffle to zext.
11573 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11574 SelectionDAG &DAG) {
11575 // PMOVZX is only available from SSE41.
11576 if (!Subtarget->hasSSE41())
11579 MVT VT = Op.getSimpleValueType();
11581 // Only AVX2 support 256-bit vector integer extending.
11582 if (!Subtarget->hasInt256() && VT.is256BitVector())
11585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11587 SDValue V1 = Op.getOperand(0);
11588 SDValue V2 = Op.getOperand(1);
11589 unsigned NumElems = VT.getVectorNumElements();
11591 // Extending is an unary operation and the element type of the source vector
11592 // won't be equal to or larger than i64.
11593 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11594 VT.getVectorElementType() == MVT::i64)
11597 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11598 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11599 while ((1U << Shift) < NumElems) {
11600 if (SVOp->getMaskElt(1U << Shift) == 1)
11603 // The maximal ratio is 8, i.e. from i8 to i64.
11608 // Check the shuffle mask.
11609 unsigned Mask = (1U << Shift) - 1;
11610 for (unsigned i = 0; i != NumElems; ++i) {
11611 int EltIdx = SVOp->getMaskElt(i);
11612 if ((i & Mask) != 0 && EltIdx != -1)
11614 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11618 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11619 MVT NeVT = MVT::getIntegerVT(NBits);
11620 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11622 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11625 return DAG.getNode(ISD::BITCAST, DL, VT,
11626 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11629 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11630 SelectionDAG &DAG) {
11631 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11632 MVT VT = Op.getSimpleValueType();
11634 SDValue V1 = Op.getOperand(0);
11635 SDValue V2 = Op.getOperand(1);
11637 if (isZeroShuffle(SVOp))
11638 return getZeroVector(VT, Subtarget, DAG, dl);
11640 // Handle splat operations
11641 if (SVOp->isSplat()) {
11642 // Use vbroadcast whenever the splat comes from a foldable load
11643 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11644 if (Broadcast.getNode())
11648 // Check integer expanding shuffles.
11649 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11650 if (NewOp.getNode())
11653 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11655 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11656 VT == MVT::v32i8) {
11657 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11658 if (NewOp.getNode())
11659 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11660 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11661 // FIXME: Figure out a cleaner way to do this.
11662 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11663 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11664 if (NewOp.getNode()) {
11665 MVT NewVT = NewOp.getSimpleValueType();
11666 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11667 NewVT, true, false))
11668 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11671 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11672 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11673 if (NewOp.getNode()) {
11674 MVT NewVT = NewOp.getSimpleValueType();
11675 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11676 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11685 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11686 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11687 SDValue V1 = Op.getOperand(0);
11688 SDValue V2 = Op.getOperand(1);
11689 MVT VT = Op.getSimpleValueType();
11691 unsigned NumElems = VT.getVectorNumElements();
11692 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11693 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11694 bool V1IsSplat = false;
11695 bool V2IsSplat = false;
11696 bool HasSSE2 = Subtarget->hasSSE2();
11697 bool HasFp256 = Subtarget->hasFp256();
11698 bool HasInt256 = Subtarget->hasInt256();
11699 MachineFunction &MF = DAG.getMachineFunction();
11700 bool OptForSize = MF.getFunction()->getAttributes().
11701 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11703 // Check if we should use the experimental vector shuffle lowering. If so,
11704 // delegate completely to that code path.
11705 if (ExperimentalVectorShuffleLowering)
11706 return lowerVectorShuffle(Op, Subtarget, DAG);
11708 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11710 if (V1IsUndef && V2IsUndef)
11711 return DAG.getUNDEF(VT);
11713 // When we create a shuffle node we put the UNDEF node to second operand,
11714 // but in some cases the first operand may be transformed to UNDEF.
11715 // In this case we should just commute the node.
11717 return DAG.getCommutedVectorShuffle(*SVOp);
11719 // Vector shuffle lowering takes 3 steps:
11721 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11722 // narrowing and commutation of operands should be handled.
11723 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11725 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11726 // so the shuffle can be broken into other shuffles and the legalizer can
11727 // try the lowering again.
11729 // The general idea is that no vector_shuffle operation should be left to
11730 // be matched during isel, all of them must be converted to a target specific
11733 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11734 // narrowing and commutation of operands should be handled. The actual code
11735 // doesn't include all of those, work in progress...
11736 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11737 if (NewOp.getNode())
11740 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11742 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11743 // unpckh_undef). Only use pshufd if speed is more important than size.
11744 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11745 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11746 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11747 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11749 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11750 V2IsUndef && MayFoldVectorLoad(V1))
11751 return getMOVDDup(Op, dl, V1, DAG);
11753 if (isMOVHLPS_v_undef_Mask(M, VT))
11754 return getMOVHighToLow(Op, dl, DAG);
11756 // Use to match splats
11757 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11758 (VT == MVT::v2f64 || VT == MVT::v2i64))
11759 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11761 if (isPSHUFDMask(M, VT)) {
11762 // The actual implementation will match the mask in the if above and then
11763 // during isel it can match several different instructions, not only pshufd
11764 // as its name says, sad but true, emulate the behavior for now...
11765 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11766 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11768 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11770 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11771 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11773 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11774 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11777 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11781 if (isPALIGNRMask(M, VT, Subtarget))
11782 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11783 getShufflePALIGNRImmediate(SVOp),
11786 if (isVALIGNMask(M, VT, Subtarget))
11787 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11788 getShuffleVALIGNImmediate(SVOp),
11791 // Check if this can be converted into a logical shift.
11792 bool isLeft = false;
11793 unsigned ShAmt = 0;
11795 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11796 if (isShift && ShVal.hasOneUse()) {
11797 // If the shifted value has multiple uses, it may be cheaper to use
11798 // v_set0 + movlhps or movhlps, etc.
11799 MVT EltVT = VT.getVectorElementType();
11800 ShAmt *= EltVT.getSizeInBits();
11801 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11804 if (isMOVLMask(M, VT)) {
11805 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11806 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11807 if (!isMOVLPMask(M, VT)) {
11808 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11809 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11811 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11812 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11816 // FIXME: fold these into legal mask.
11817 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11818 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11820 if (isMOVHLPSMask(M, VT))
11821 return getMOVHighToLow(Op, dl, DAG);
11823 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11824 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11826 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11827 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11829 if (isMOVLPMask(M, VT))
11830 return getMOVLP(Op, dl, DAG, HasSSE2);
11832 if (ShouldXformToMOVHLPS(M, VT) ||
11833 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11834 return DAG.getCommutedVectorShuffle(*SVOp);
11837 // No better options. Use a vshldq / vsrldq.
11838 MVT EltVT = VT.getVectorElementType();
11839 ShAmt *= EltVT.getSizeInBits();
11840 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11843 bool Commuted = false;
11844 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11845 // 1,1,1,1 -> v8i16 though.
11846 BitVector UndefElements;
11847 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11848 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11850 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11851 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11854 // Canonicalize the splat or undef, if present, to be on the RHS.
11855 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11856 CommuteVectorShuffleMask(M, NumElems);
11858 std::swap(V1IsSplat, V2IsSplat);
11862 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11863 // Shuffling low element of v1 into undef, just return v1.
11866 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11867 // the instruction selector will not match, so get a canonical MOVL with
11868 // swapped operands to undo the commute.
11869 return getMOVL(DAG, dl, VT, V2, V1);
11872 if (isUNPCKLMask(M, VT, HasInt256))
11873 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11875 if (isUNPCKHMask(M, VT, HasInt256))
11876 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11879 // Normalize mask so all entries that point to V2 points to its first
11880 // element then try to match unpck{h|l} again. If match, return a
11881 // new vector_shuffle with the corrected mask.p
11882 SmallVector<int, 8> NewMask(M.begin(), M.end());
11883 NormalizeMask(NewMask, NumElems);
11884 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11885 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11886 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11887 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11891 // Commute is back and try unpck* again.
11892 // FIXME: this seems wrong.
11893 CommuteVectorShuffleMask(M, NumElems);
11895 std::swap(V1IsSplat, V2IsSplat);
11897 if (isUNPCKLMask(M, VT, HasInt256))
11898 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11900 if (isUNPCKHMask(M, VT, HasInt256))
11901 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11904 // Normalize the node to match x86 shuffle ops if needed
11905 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11906 return DAG.getCommutedVectorShuffle(*SVOp);
11908 // The checks below are all present in isShuffleMaskLegal, but they are
11909 // inlined here right now to enable us to directly emit target specific
11910 // nodes, and remove one by one until they don't return Op anymore.
11912 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11913 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11914 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11915 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11918 if (isPSHUFHWMask(M, VT, HasInt256))
11919 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11920 getShufflePSHUFHWImmediate(SVOp),
11923 if (isPSHUFLWMask(M, VT, HasInt256))
11924 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11925 getShufflePSHUFLWImmediate(SVOp),
11928 unsigned MaskValue;
11929 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11931 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11933 if (isSHUFPMask(M, VT))
11934 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11935 getShuffleSHUFImmediate(SVOp), DAG);
11937 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11938 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11939 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11940 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11942 //===--------------------------------------------------------------------===//
11943 // Generate target specific nodes for 128 or 256-bit shuffles only
11944 // supported in the AVX instruction set.
11947 // Handle VMOVDDUPY permutations
11948 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11949 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11951 // Handle VPERMILPS/D* permutations
11952 if (isVPERMILPMask(M, VT)) {
11953 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11954 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11955 getShuffleSHUFImmediate(SVOp), DAG);
11956 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11957 getShuffleSHUFImmediate(SVOp), DAG);
11961 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11962 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11963 Idx*(NumElems/2), DAG, dl);
11965 // Handle VPERM2F128/VPERM2I128 permutations
11966 if (isVPERM2X128Mask(M, VT, HasFp256))
11967 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11968 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11970 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11971 return getINSERTPS(SVOp, dl, DAG);
11974 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11975 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11977 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11978 VT.is512BitVector()) {
11979 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11980 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11981 SmallVector<SDValue, 16> permclMask;
11982 for (unsigned i = 0; i != NumElems; ++i) {
11983 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11986 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11988 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11989 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11990 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11991 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11992 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11995 //===--------------------------------------------------------------------===//
11996 // Since no target specific shuffle was selected for this generic one,
11997 // lower it into other known shuffles. FIXME: this isn't true yet, but
11998 // this is the plan.
12001 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12002 if (VT == MVT::v8i16) {
12003 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12004 if (NewOp.getNode())
12008 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12009 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12010 if (NewOp.getNode())
12014 if (VT == MVT::v16i8) {
12015 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12016 if (NewOp.getNode())
12020 if (VT == MVT::v32i8) {
12021 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12022 if (NewOp.getNode())
12026 // Handle all 128-bit wide vectors with 4 elements, and match them with
12027 // several different shuffle types.
12028 if (NumElems == 4 && VT.is128BitVector())
12029 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12031 // Handle general 256-bit shuffles
12032 if (VT.is256BitVector())
12033 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12038 // This function assumes its argument is a BUILD_VECTOR of constants or
12039 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12041 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12042 unsigned &MaskValue) {
12044 unsigned NumElems = BuildVector->getNumOperands();
12045 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12046 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12047 unsigned NumElemsInLane = NumElems / NumLanes;
12049 // Blend for v16i16 should be symetric for the both lanes.
12050 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12051 SDValue EltCond = BuildVector->getOperand(i);
12052 SDValue SndLaneEltCond =
12053 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12055 int Lane1Cond = -1, Lane2Cond = -1;
12056 if (isa<ConstantSDNode>(EltCond))
12057 Lane1Cond = !isZero(EltCond);
12058 if (isa<ConstantSDNode>(SndLaneEltCond))
12059 Lane2Cond = !isZero(SndLaneEltCond);
12061 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12062 // Lane1Cond != 0, means we want the first argument.
12063 // Lane1Cond == 0, means we want the second argument.
12064 // The encoding of this argument is 0 for the first argument, 1
12065 // for the second. Therefore, invert the condition.
12066 MaskValue |= !Lane1Cond << i;
12067 else if (Lane1Cond < 0)
12068 MaskValue |= !Lane2Cond << i;
12075 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12077 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12078 SelectionDAG &DAG) {
12079 SDValue Cond = Op.getOperand(0);
12080 SDValue LHS = Op.getOperand(1);
12081 SDValue RHS = Op.getOperand(2);
12083 MVT VT = Op.getSimpleValueType();
12084 MVT EltVT = VT.getVectorElementType();
12085 unsigned NumElems = VT.getVectorNumElements();
12087 // There is no blend with immediate in AVX-512.
12088 if (VT.is512BitVector())
12091 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12093 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12096 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12099 // Check the mask for BLEND and build the value.
12100 unsigned MaskValue = 0;
12101 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12104 // Convert i32 vectors to floating point if it is not AVX2.
12105 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12107 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12108 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12110 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12111 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12114 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12115 DAG.getConstant(MaskValue, MVT::i32));
12116 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12119 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12120 // A vselect where all conditions and data are constants can be optimized into
12121 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12122 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12123 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12124 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12127 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12128 if (BlendOp.getNode())
12131 // Some types for vselect were previously set to Expand, not Legal or
12132 // Custom. Return an empty SDValue so we fall-through to Expand, after
12133 // the Custom lowering phase.
12134 MVT VT = Op.getSimpleValueType();
12135 switch (VT.SimpleTy) {
12140 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12145 // We couldn't create a "Blend with immediate" node.
12146 // This node should still be legal, but we'll have to emit a blendv*
12151 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12152 MVT VT = Op.getSimpleValueType();
12155 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12158 if (VT.getSizeInBits() == 8) {
12159 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12160 Op.getOperand(0), Op.getOperand(1));
12161 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12162 DAG.getValueType(VT));
12163 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12166 if (VT.getSizeInBits() == 16) {
12167 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12168 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12170 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12171 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12172 DAG.getNode(ISD::BITCAST, dl,
12175 Op.getOperand(1)));
12176 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12177 Op.getOperand(0), Op.getOperand(1));
12178 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12179 DAG.getValueType(VT));
12180 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12183 if (VT == MVT::f32) {
12184 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12185 // the result back to FR32 register. It's only worth matching if the
12186 // result has a single use which is a store or a bitcast to i32. And in
12187 // the case of a store, it's not worth it if the index is a constant 0,
12188 // because a MOVSSmr can be used instead, which is smaller and faster.
12189 if (!Op.hasOneUse())
12191 SDNode *User = *Op.getNode()->use_begin();
12192 if ((User->getOpcode() != ISD::STORE ||
12193 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12194 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12195 (User->getOpcode() != ISD::BITCAST ||
12196 User->getValueType(0) != MVT::i32))
12198 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12199 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12202 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12205 if (VT == MVT::i32 || VT == MVT::i64) {
12206 // ExtractPS/pextrq works with constant index.
12207 if (isa<ConstantSDNode>(Op.getOperand(1)))
12213 /// Extract one bit from mask vector, like v16i1 or v8i1.
12214 /// AVX-512 feature.
12216 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12217 SDValue Vec = Op.getOperand(0);
12219 MVT VecVT = Vec.getSimpleValueType();
12220 SDValue Idx = Op.getOperand(1);
12221 MVT EltVT = Op.getSimpleValueType();
12223 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12225 // variable index can't be handled in mask registers,
12226 // extend vector to VR512
12227 if (!isa<ConstantSDNode>(Idx)) {
12228 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12229 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12230 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12231 ExtVT.getVectorElementType(), Ext, Idx);
12232 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12235 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12236 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12237 unsigned MaxSift = rc->getSize()*8 - 1;
12238 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12239 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12240 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12241 DAG.getConstant(MaxSift, MVT::i8));
12242 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12243 DAG.getIntPtrConstant(0));
12247 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12248 SelectionDAG &DAG) const {
12250 SDValue Vec = Op.getOperand(0);
12251 MVT VecVT = Vec.getSimpleValueType();
12252 SDValue Idx = Op.getOperand(1);
12254 if (Op.getSimpleValueType() == MVT::i1)
12255 return ExtractBitFromMaskVector(Op, DAG);
12257 if (!isa<ConstantSDNode>(Idx)) {
12258 if (VecVT.is512BitVector() ||
12259 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12260 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12263 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12264 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12265 MaskEltVT.getSizeInBits());
12267 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12268 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12269 getZeroVector(MaskVT, Subtarget, DAG, dl),
12270 Idx, DAG.getConstant(0, getPointerTy()));
12271 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12272 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12273 Perm, DAG.getConstant(0, getPointerTy()));
12278 // If this is a 256-bit vector result, first extract the 128-bit vector and
12279 // then extract the element from the 128-bit vector.
12280 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12282 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12283 // Get the 128-bit vector.
12284 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12285 MVT EltVT = VecVT.getVectorElementType();
12287 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12289 //if (IdxVal >= NumElems/2)
12290 // IdxVal -= NumElems/2;
12291 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12292 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12293 DAG.getConstant(IdxVal, MVT::i32));
12296 assert(VecVT.is128BitVector() && "Unexpected vector length");
12298 if (Subtarget->hasSSE41()) {
12299 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12304 MVT VT = Op.getSimpleValueType();
12305 // TODO: handle v16i8.
12306 if (VT.getSizeInBits() == 16) {
12307 SDValue Vec = Op.getOperand(0);
12308 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12310 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12311 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12312 DAG.getNode(ISD::BITCAST, dl,
12314 Op.getOperand(1)));
12315 // Transform it so it match pextrw which produces a 32-bit result.
12316 MVT EltVT = MVT::i32;
12317 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12318 Op.getOperand(0), Op.getOperand(1));
12319 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12320 DAG.getValueType(VT));
12321 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12324 if (VT.getSizeInBits() == 32) {
12325 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12329 // SHUFPS the element to the lowest double word, then movss.
12330 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12331 MVT VVT = Op.getOperand(0).getSimpleValueType();
12332 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12333 DAG.getUNDEF(VVT), Mask);
12334 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12335 DAG.getIntPtrConstant(0));
12338 if (VT.getSizeInBits() == 64) {
12339 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12340 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12341 // to match extract_elt for f64.
12342 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12346 // UNPCKHPD the element to the lowest double word, then movsd.
12347 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12348 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12349 int Mask[2] = { 1, -1 };
12350 MVT VVT = Op.getOperand(0).getSimpleValueType();
12351 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12352 DAG.getUNDEF(VVT), Mask);
12353 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12354 DAG.getIntPtrConstant(0));
12360 /// Insert one bit to mask vector, like v16i1 or v8i1.
12361 /// AVX-512 feature.
12363 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12365 SDValue Vec = Op.getOperand(0);
12366 SDValue Elt = Op.getOperand(1);
12367 SDValue Idx = Op.getOperand(2);
12368 MVT VecVT = Vec.getSimpleValueType();
12370 if (!isa<ConstantSDNode>(Idx)) {
12371 // Non constant index. Extend source and destination,
12372 // insert element and then truncate the result.
12373 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12374 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12375 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12376 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12377 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12378 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12381 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12382 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12383 if (Vec.getOpcode() == ISD::UNDEF)
12384 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12385 DAG.getConstant(IdxVal, MVT::i8));
12386 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12387 unsigned MaxSift = rc->getSize()*8 - 1;
12388 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12389 DAG.getConstant(MaxSift, MVT::i8));
12390 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12391 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12392 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12395 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12396 SelectionDAG &DAG) const {
12397 MVT VT = Op.getSimpleValueType();
12398 MVT EltVT = VT.getVectorElementType();
12400 if (EltVT == MVT::i1)
12401 return InsertBitToMaskVector(Op, DAG);
12404 SDValue N0 = Op.getOperand(0);
12405 SDValue N1 = Op.getOperand(1);
12406 SDValue N2 = Op.getOperand(2);
12407 if (!isa<ConstantSDNode>(N2))
12409 auto *N2C = cast<ConstantSDNode>(N2);
12410 unsigned IdxVal = N2C->getZExtValue();
12412 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12413 // into that, and then insert the subvector back into the result.
12414 if (VT.is256BitVector() || VT.is512BitVector()) {
12415 // Get the desired 128-bit vector half.
12416 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12418 // Insert the element into the desired half.
12419 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12420 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12422 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12423 DAG.getConstant(IdxIn128, MVT::i32));
12425 // Insert the changed part back to the 256-bit vector
12426 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12428 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12430 if (Subtarget->hasSSE41()) {
12431 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12433 if (VT == MVT::v8i16) {
12434 Opc = X86ISD::PINSRW;
12436 assert(VT == MVT::v16i8);
12437 Opc = X86ISD::PINSRB;
12440 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12442 if (N1.getValueType() != MVT::i32)
12443 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12444 if (N2.getValueType() != MVT::i32)
12445 N2 = DAG.getIntPtrConstant(IdxVal);
12446 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12449 if (EltVT == MVT::f32) {
12450 // Bits [7:6] of the constant are the source select. This will always be
12451 // zero here. The DAG Combiner may combine an extract_elt index into
12453 // bits. For example (insert (extract, 3), 2) could be matched by
12455 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12456 // Bits [5:4] of the constant are the destination select. This is the
12457 // value of the incoming immediate.
12458 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12459 // combine either bitwise AND or insert of float 0.0 to set these bits.
12460 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12461 // Create this as a scalar to vector..
12462 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12463 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12466 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12467 // PINSR* works with constant index.
12472 if (EltVT == MVT::i8)
12475 if (EltVT.getSizeInBits() == 16) {
12476 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12477 // as its second argument.
12478 if (N1.getValueType() != MVT::i32)
12479 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12480 if (N2.getValueType() != MVT::i32)
12481 N2 = DAG.getIntPtrConstant(IdxVal);
12482 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12487 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12489 MVT OpVT = Op.getSimpleValueType();
12491 // If this is a 256-bit vector result, first insert into a 128-bit
12492 // vector and then insert into the 256-bit vector.
12493 if (!OpVT.is128BitVector()) {
12494 // Insert into a 128-bit vector.
12495 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12496 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12497 OpVT.getVectorNumElements() / SizeFactor);
12499 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12501 // Insert the 128-bit vector.
12502 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12505 if (OpVT == MVT::v1i64 &&
12506 Op.getOperand(0).getValueType() == MVT::i64)
12507 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12509 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12510 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12511 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12512 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12515 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12516 // a simple subregister reference or explicit instructions to grab
12517 // upper bits of a vector.
12518 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12519 SelectionDAG &DAG) {
12521 SDValue In = Op.getOperand(0);
12522 SDValue Idx = Op.getOperand(1);
12523 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12524 MVT ResVT = Op.getSimpleValueType();
12525 MVT InVT = In.getSimpleValueType();
12527 if (Subtarget->hasFp256()) {
12528 if (ResVT.is128BitVector() &&
12529 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12530 isa<ConstantSDNode>(Idx)) {
12531 return Extract128BitVector(In, IdxVal, DAG, dl);
12533 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12534 isa<ConstantSDNode>(Idx)) {
12535 return Extract256BitVector(In, IdxVal, DAG, dl);
12541 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12542 // simple superregister reference or explicit instructions to insert
12543 // the upper bits of a vector.
12544 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12545 SelectionDAG &DAG) {
12546 if (Subtarget->hasFp256()) {
12547 SDLoc dl(Op.getNode());
12548 SDValue Vec = Op.getNode()->getOperand(0);
12549 SDValue SubVec = Op.getNode()->getOperand(1);
12550 SDValue Idx = Op.getNode()->getOperand(2);
12552 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12553 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12554 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12555 isa<ConstantSDNode>(Idx)) {
12556 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12557 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12560 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12561 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12562 isa<ConstantSDNode>(Idx)) {
12563 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12564 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12570 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12571 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12572 // one of the above mentioned nodes. It has to be wrapped because otherwise
12573 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12574 // be used to form addressing mode. These wrapped nodes will be selected
12577 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12578 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12580 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12581 // global base reg.
12582 unsigned char OpFlag = 0;
12583 unsigned WrapperKind = X86ISD::Wrapper;
12584 CodeModel::Model M = DAG.getTarget().getCodeModel();
12586 if (Subtarget->isPICStyleRIPRel() &&
12587 (M == CodeModel::Small || M == CodeModel::Kernel))
12588 WrapperKind = X86ISD::WrapperRIP;
12589 else if (Subtarget->isPICStyleGOT())
12590 OpFlag = X86II::MO_GOTOFF;
12591 else if (Subtarget->isPICStyleStubPIC())
12592 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12594 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12595 CP->getAlignment(),
12596 CP->getOffset(), OpFlag);
12598 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12599 // With PIC, the address is actually $g + Offset.
12601 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12602 DAG.getNode(X86ISD::GlobalBaseReg,
12603 SDLoc(), getPointerTy()),
12610 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12611 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12613 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12614 // global base reg.
12615 unsigned char OpFlag = 0;
12616 unsigned WrapperKind = X86ISD::Wrapper;
12617 CodeModel::Model M = DAG.getTarget().getCodeModel();
12619 if (Subtarget->isPICStyleRIPRel() &&
12620 (M == CodeModel::Small || M == CodeModel::Kernel))
12621 WrapperKind = X86ISD::WrapperRIP;
12622 else if (Subtarget->isPICStyleGOT())
12623 OpFlag = X86II::MO_GOTOFF;
12624 else if (Subtarget->isPICStyleStubPIC())
12625 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12627 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12630 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12632 // With PIC, the address is actually $g + Offset.
12634 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12635 DAG.getNode(X86ISD::GlobalBaseReg,
12636 SDLoc(), getPointerTy()),
12643 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12644 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12646 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12647 // global base reg.
12648 unsigned char OpFlag = 0;
12649 unsigned WrapperKind = X86ISD::Wrapper;
12650 CodeModel::Model M = DAG.getTarget().getCodeModel();
12652 if (Subtarget->isPICStyleRIPRel() &&
12653 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12654 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12655 OpFlag = X86II::MO_GOTPCREL;
12656 WrapperKind = X86ISD::WrapperRIP;
12657 } else if (Subtarget->isPICStyleGOT()) {
12658 OpFlag = X86II::MO_GOT;
12659 } else if (Subtarget->isPICStyleStubPIC()) {
12660 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12661 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12662 OpFlag = X86II::MO_DARWIN_NONLAZY;
12665 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12668 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12670 // With PIC, the address is actually $g + Offset.
12671 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12672 !Subtarget->is64Bit()) {
12673 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12674 DAG.getNode(X86ISD::GlobalBaseReg,
12675 SDLoc(), getPointerTy()),
12679 // For symbols that require a load from a stub to get the address, emit the
12681 if (isGlobalStubReference(OpFlag))
12682 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12683 MachinePointerInfo::getGOT(), false, false, false, 0);
12689 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12690 // Create the TargetBlockAddressAddress node.
12691 unsigned char OpFlags =
12692 Subtarget->ClassifyBlockAddressReference();
12693 CodeModel::Model M = DAG.getTarget().getCodeModel();
12694 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12695 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12697 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12700 if (Subtarget->isPICStyleRIPRel() &&
12701 (M == CodeModel::Small || M == CodeModel::Kernel))
12702 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12704 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12706 // With PIC, the address is actually $g + Offset.
12707 if (isGlobalRelativeToPICBase(OpFlags)) {
12708 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12709 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12717 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12718 int64_t Offset, SelectionDAG &DAG) const {
12719 // Create the TargetGlobalAddress node, folding in the constant
12720 // offset if it is legal.
12721 unsigned char OpFlags =
12722 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12723 CodeModel::Model M = DAG.getTarget().getCodeModel();
12725 if (OpFlags == X86II::MO_NO_FLAG &&
12726 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12727 // A direct static reference to a global.
12728 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12731 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12734 if (Subtarget->isPICStyleRIPRel() &&
12735 (M == CodeModel::Small || M == CodeModel::Kernel))
12736 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12738 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12740 // With PIC, the address is actually $g + Offset.
12741 if (isGlobalRelativeToPICBase(OpFlags)) {
12742 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12743 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12747 // For globals that require a load from a stub to get the address, emit the
12749 if (isGlobalStubReference(OpFlags))
12750 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12751 MachinePointerInfo::getGOT(), false, false, false, 0);
12753 // If there was a non-zero offset that we didn't fold, create an explicit
12754 // addition for it.
12756 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12757 DAG.getConstant(Offset, getPointerTy()));
12763 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12764 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12765 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12766 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12770 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12771 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12772 unsigned char OperandFlags, bool LocalDynamic = false) {
12773 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12774 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12776 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12777 GA->getValueType(0),
12781 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12785 SDValue Ops[] = { Chain, TGA, *InFlag };
12786 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12788 SDValue Ops[] = { Chain, TGA };
12789 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12792 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12793 MFI->setAdjustsStack(true);
12795 SDValue Flag = Chain.getValue(1);
12796 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12799 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12801 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12804 SDLoc dl(GA); // ? function entry point might be better
12805 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12806 DAG.getNode(X86ISD::GlobalBaseReg,
12807 SDLoc(), PtrVT), InFlag);
12808 InFlag = Chain.getValue(1);
12810 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12813 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12815 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12817 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12818 X86::RAX, X86II::MO_TLSGD);
12821 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12827 // Get the start address of the TLS block for this module.
12828 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12829 .getInfo<X86MachineFunctionInfo>();
12830 MFI->incNumLocalDynamicTLSAccesses();
12834 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12835 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12838 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12839 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12840 InFlag = Chain.getValue(1);
12841 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12842 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12845 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12849 unsigned char OperandFlags = X86II::MO_DTPOFF;
12850 unsigned WrapperKind = X86ISD::Wrapper;
12851 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12852 GA->getValueType(0),
12853 GA->getOffset(), OperandFlags);
12854 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12856 // Add x@dtpoff with the base.
12857 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12860 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12861 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12862 const EVT PtrVT, TLSModel::Model model,
12863 bool is64Bit, bool isPIC) {
12866 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12867 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12868 is64Bit ? 257 : 256));
12870 SDValue ThreadPointer =
12871 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12872 MachinePointerInfo(Ptr), false, false, false, 0);
12874 unsigned char OperandFlags = 0;
12875 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12877 unsigned WrapperKind = X86ISD::Wrapper;
12878 if (model == TLSModel::LocalExec) {
12879 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12880 } else if (model == TLSModel::InitialExec) {
12882 OperandFlags = X86II::MO_GOTTPOFF;
12883 WrapperKind = X86ISD::WrapperRIP;
12885 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12888 llvm_unreachable("Unexpected model");
12891 // emit "addl x@ntpoff,%eax" (local exec)
12892 // or "addl x@indntpoff,%eax" (initial exec)
12893 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12895 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12896 GA->getOffset(), OperandFlags);
12897 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12899 if (model == TLSModel::InitialExec) {
12900 if (isPIC && !is64Bit) {
12901 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12902 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12906 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12907 MachinePointerInfo::getGOT(), false, false, false, 0);
12910 // The address of the thread local variable is the add of the thread
12911 // pointer with the offset of the variable.
12912 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12916 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12918 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12919 const GlobalValue *GV = GA->getGlobal();
12921 if (Subtarget->isTargetELF()) {
12922 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12925 case TLSModel::GeneralDynamic:
12926 if (Subtarget->is64Bit())
12927 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12928 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12929 case TLSModel::LocalDynamic:
12930 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12931 Subtarget->is64Bit());
12932 case TLSModel::InitialExec:
12933 case TLSModel::LocalExec:
12934 return LowerToTLSExecModel(
12935 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12936 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12938 llvm_unreachable("Unknown TLS model.");
12941 if (Subtarget->isTargetDarwin()) {
12942 // Darwin only has one model of TLS. Lower to that.
12943 unsigned char OpFlag = 0;
12944 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12945 X86ISD::WrapperRIP : X86ISD::Wrapper;
12947 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12948 // global base reg.
12949 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12950 !Subtarget->is64Bit();
12952 OpFlag = X86II::MO_TLVP_PIC_BASE;
12954 OpFlag = X86II::MO_TLVP;
12956 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12957 GA->getValueType(0),
12958 GA->getOffset(), OpFlag);
12959 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12961 // With PIC32, the address is actually $g + Offset.
12963 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12964 DAG.getNode(X86ISD::GlobalBaseReg,
12965 SDLoc(), getPointerTy()),
12968 // Lowering the machine isd will make sure everything is in the right
12970 SDValue Chain = DAG.getEntryNode();
12971 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12972 SDValue Args[] = { Chain, Offset };
12973 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12975 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12976 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12977 MFI->setAdjustsStack(true);
12979 // And our return value (tls address) is in the standard call return value
12981 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12982 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12983 Chain.getValue(1));
12986 if (Subtarget->isTargetKnownWindowsMSVC() ||
12987 Subtarget->isTargetWindowsGNU()) {
12988 // Just use the implicit TLS architecture
12989 // Need to generate someting similar to:
12990 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12992 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12993 // mov rcx, qword [rdx+rcx*8]
12994 // mov eax, .tls$:tlsvar
12995 // [rax+rcx] contains the address
12996 // Windows 64bit: gs:0x58
12997 // Windows 32bit: fs:__tls_array
13000 SDValue Chain = DAG.getEntryNode();
13002 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13003 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13004 // use its literal value of 0x2C.
13005 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13006 ? Type::getInt8PtrTy(*DAG.getContext(),
13008 : Type::getInt32PtrTy(*DAG.getContext(),
13012 Subtarget->is64Bit()
13013 ? DAG.getIntPtrConstant(0x58)
13014 : (Subtarget->isTargetWindowsGNU()
13015 ? DAG.getIntPtrConstant(0x2C)
13016 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13018 SDValue ThreadPointer =
13019 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13020 MachinePointerInfo(Ptr), false, false, false, 0);
13022 // Load the _tls_index variable
13023 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13024 if (Subtarget->is64Bit())
13025 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13026 IDX, MachinePointerInfo(), MVT::i32,
13027 false, false, false, 0);
13029 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13030 false, false, false, 0);
13032 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13034 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13036 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13037 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13038 false, false, false, 0);
13040 // Get the offset of start of .tls section
13041 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13042 GA->getValueType(0),
13043 GA->getOffset(), X86II::MO_SECREL);
13044 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13046 // The address of the thread local variable is the add of the thread
13047 // pointer with the offset of the variable.
13048 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13051 llvm_unreachable("TLS not implemented for this target.");
13054 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13055 /// and take a 2 x i32 value to shift plus a shift amount.
13056 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13057 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13058 MVT VT = Op.getSimpleValueType();
13059 unsigned VTBits = VT.getSizeInBits();
13061 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13062 SDValue ShOpLo = Op.getOperand(0);
13063 SDValue ShOpHi = Op.getOperand(1);
13064 SDValue ShAmt = Op.getOperand(2);
13065 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13066 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13068 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13069 DAG.getConstant(VTBits - 1, MVT::i8));
13070 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13071 DAG.getConstant(VTBits - 1, MVT::i8))
13072 : DAG.getConstant(0, VT);
13074 SDValue Tmp2, Tmp3;
13075 if (Op.getOpcode() == ISD::SHL_PARTS) {
13076 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13077 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13079 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13080 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13083 // If the shift amount is larger or equal than the width of a part we can't
13084 // rely on the results of shld/shrd. Insert a test and select the appropriate
13085 // values for large shift amounts.
13086 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13087 DAG.getConstant(VTBits, MVT::i8));
13088 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13089 AndNode, DAG.getConstant(0, MVT::i8));
13092 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13093 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13094 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13096 if (Op.getOpcode() == ISD::SHL_PARTS) {
13097 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13098 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13100 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13101 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13104 SDValue Ops[2] = { Lo, Hi };
13105 return DAG.getMergeValues(Ops, dl);
13108 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13109 SelectionDAG &DAG) const {
13110 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13112 if (SrcVT.isVector())
13115 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13116 "Unknown SINT_TO_FP to lower!");
13118 // These are really Legal; return the operand so the caller accepts it as
13120 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13122 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13123 Subtarget->is64Bit()) {
13128 unsigned Size = SrcVT.getSizeInBits()/8;
13129 MachineFunction &MF = DAG.getMachineFunction();
13130 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13131 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13132 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13134 MachinePointerInfo::getFixedStack(SSFI),
13136 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13139 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13141 SelectionDAG &DAG) const {
13145 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13147 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13149 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13151 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13153 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13154 MachineMemOperand *MMO;
13156 int SSFI = FI->getIndex();
13158 DAG.getMachineFunction()
13159 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13160 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13162 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13163 StackSlot = StackSlot.getOperand(1);
13165 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13166 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13168 Tys, Ops, SrcVT, MMO);
13171 Chain = Result.getValue(1);
13172 SDValue InFlag = Result.getValue(2);
13174 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13175 // shouldn't be necessary except that RFP cannot be live across
13176 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13177 MachineFunction &MF = DAG.getMachineFunction();
13178 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13179 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13180 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13181 Tys = DAG.getVTList(MVT::Other);
13183 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13185 MachineMemOperand *MMO =
13186 DAG.getMachineFunction()
13187 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13188 MachineMemOperand::MOStore, SSFISize, SSFISize);
13190 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13191 Ops, Op.getValueType(), MMO);
13192 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13193 MachinePointerInfo::getFixedStack(SSFI),
13194 false, false, false, 0);
13200 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13201 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13202 SelectionDAG &DAG) const {
13203 // This algorithm is not obvious. Here it is what we're trying to output:
13206 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13207 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13209 haddpd %xmm0, %xmm0
13211 pshufd $0x4e, %xmm0, %xmm1
13217 LLVMContext *Context = DAG.getContext();
13219 // Build some magic constants.
13220 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13221 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13222 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13224 SmallVector<Constant*,2> CV1;
13226 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13227 APInt(64, 0x4330000000000000ULL))));
13229 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13230 APInt(64, 0x4530000000000000ULL))));
13231 Constant *C1 = ConstantVector::get(CV1);
13232 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13234 // Load the 64-bit value into an XMM register.
13235 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13237 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13238 MachinePointerInfo::getConstantPool(),
13239 false, false, false, 16);
13240 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13241 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13244 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13245 MachinePointerInfo::getConstantPool(),
13246 false, false, false, 16);
13247 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13248 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13251 if (Subtarget->hasSSE3()) {
13252 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13253 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13255 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13256 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13258 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13259 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13263 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13264 DAG.getIntPtrConstant(0));
13267 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13268 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13269 SelectionDAG &DAG) const {
13271 // FP constant to bias correct the final result.
13272 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13275 // Load the 32-bit value into an XMM register.
13276 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13279 // Zero out the upper parts of the register.
13280 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13282 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13283 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13284 DAG.getIntPtrConstant(0));
13286 // Or the load with the bias.
13287 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13288 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13289 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13290 MVT::v2f64, Load)),
13291 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13292 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13293 MVT::v2f64, Bias)));
13294 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13295 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13296 DAG.getIntPtrConstant(0));
13298 // Subtract the bias.
13299 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13301 // Handle final rounding.
13302 EVT DestVT = Op.getValueType();
13304 if (DestVT.bitsLT(MVT::f64))
13305 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13306 DAG.getIntPtrConstant(0));
13307 if (DestVT.bitsGT(MVT::f64))
13308 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13310 // Handle final rounding.
13314 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13315 SelectionDAG &DAG) const {
13316 SDValue N0 = Op.getOperand(0);
13317 MVT SVT = N0.getSimpleValueType();
13320 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13321 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13322 "Custom UINT_TO_FP is not supported!");
13324 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13325 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13326 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13329 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13330 SelectionDAG &DAG) const {
13331 SDValue N0 = Op.getOperand(0);
13334 if (Op.getValueType().isVector())
13335 return lowerUINT_TO_FP_vec(Op, DAG);
13337 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13338 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13339 // the optimization here.
13340 if (DAG.SignBitIsZero(N0))
13341 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13343 MVT SrcVT = N0.getSimpleValueType();
13344 MVT DstVT = Op.getSimpleValueType();
13345 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13346 return LowerUINT_TO_FP_i64(Op, DAG);
13347 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13348 return LowerUINT_TO_FP_i32(Op, DAG);
13349 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13352 // Make a 64-bit buffer, and use it to build an FILD.
13353 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13354 if (SrcVT == MVT::i32) {
13355 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13356 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13357 getPointerTy(), StackSlot, WordOff);
13358 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13359 StackSlot, MachinePointerInfo(),
13361 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13362 OffsetSlot, MachinePointerInfo(),
13364 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13368 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13369 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13370 StackSlot, MachinePointerInfo(),
13372 // For i64 source, we need to add the appropriate power of 2 if the input
13373 // was negative. This is the same as the optimization in
13374 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13375 // we must be careful to do the computation in x87 extended precision, not
13376 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13377 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13378 MachineMemOperand *MMO =
13379 DAG.getMachineFunction()
13380 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13381 MachineMemOperand::MOLoad, 8, 8);
13383 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13384 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13385 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13388 APInt FF(32, 0x5F800000ULL);
13390 // Check whether the sign bit is set.
13391 SDValue SignSet = DAG.getSetCC(dl,
13392 getSetCCResultType(*DAG.getContext(), MVT::i64),
13393 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13396 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13397 SDValue FudgePtr = DAG.getConstantPool(
13398 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13401 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13402 SDValue Zero = DAG.getIntPtrConstant(0);
13403 SDValue Four = DAG.getIntPtrConstant(4);
13404 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13406 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13408 // Load the value out, extending it from f32 to f80.
13409 // FIXME: Avoid the extend by constructing the right constant pool?
13410 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13411 FudgePtr, MachinePointerInfo::getConstantPool(),
13412 MVT::f32, false, false, false, 4);
13413 // Extend everything to 80 bits to force it to be done on x87.
13414 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13415 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13418 std::pair<SDValue,SDValue>
13419 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13420 bool IsSigned, bool IsReplace) const {
13423 EVT DstTy = Op.getValueType();
13425 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13426 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13430 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13431 DstTy.getSimpleVT() >= MVT::i16 &&
13432 "Unknown FP_TO_INT to lower!");
13434 // These are really Legal.
13435 if (DstTy == MVT::i32 &&
13436 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13437 return std::make_pair(SDValue(), SDValue());
13438 if (Subtarget->is64Bit() &&
13439 DstTy == MVT::i64 &&
13440 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13441 return std::make_pair(SDValue(), SDValue());
13443 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13444 // stack slot, or into the FTOL runtime function.
13445 MachineFunction &MF = DAG.getMachineFunction();
13446 unsigned MemSize = DstTy.getSizeInBits()/8;
13447 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13448 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13451 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13452 Opc = X86ISD::WIN_FTOL;
13454 switch (DstTy.getSimpleVT().SimpleTy) {
13455 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13456 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13457 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13458 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13461 SDValue Chain = DAG.getEntryNode();
13462 SDValue Value = Op.getOperand(0);
13463 EVT TheVT = Op.getOperand(0).getValueType();
13464 // FIXME This causes a redundant load/store if the SSE-class value is already
13465 // in memory, such as if it is on the callstack.
13466 if (isScalarFPTypeInSSEReg(TheVT)) {
13467 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13468 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13469 MachinePointerInfo::getFixedStack(SSFI),
13471 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13473 Chain, StackSlot, DAG.getValueType(TheVT)
13476 MachineMemOperand *MMO =
13477 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13478 MachineMemOperand::MOLoad, MemSize, MemSize);
13479 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13480 Chain = Value.getValue(1);
13481 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13482 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13485 MachineMemOperand *MMO =
13486 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13487 MachineMemOperand::MOStore, MemSize, MemSize);
13489 if (Opc != X86ISD::WIN_FTOL) {
13490 // Build the FP_TO_INT*_IN_MEM
13491 SDValue Ops[] = { Chain, Value, StackSlot };
13492 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13494 return std::make_pair(FIST, StackSlot);
13496 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13497 DAG.getVTList(MVT::Other, MVT::Glue),
13499 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13500 MVT::i32, ftol.getValue(1));
13501 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13502 MVT::i32, eax.getValue(2));
13503 SDValue Ops[] = { eax, edx };
13504 SDValue pair = IsReplace
13505 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13506 : DAG.getMergeValues(Ops, DL);
13507 return std::make_pair(pair, SDValue());
13511 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13512 const X86Subtarget *Subtarget) {
13513 MVT VT = Op->getSimpleValueType(0);
13514 SDValue In = Op->getOperand(0);
13515 MVT InVT = In.getSimpleValueType();
13518 // Optimize vectors in AVX mode:
13521 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13522 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13523 // Concat upper and lower parts.
13526 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13527 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13528 // Concat upper and lower parts.
13531 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13532 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13533 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13536 if (Subtarget->hasInt256())
13537 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13539 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13540 SDValue Undef = DAG.getUNDEF(InVT);
13541 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13542 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13543 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13545 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13546 VT.getVectorNumElements()/2);
13548 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13549 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13551 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13554 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13555 SelectionDAG &DAG) {
13556 MVT VT = Op->getSimpleValueType(0);
13557 SDValue In = Op->getOperand(0);
13558 MVT InVT = In.getSimpleValueType();
13560 unsigned int NumElts = VT.getVectorNumElements();
13561 if (NumElts != 8 && NumElts != 16)
13564 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13565 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13567 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13568 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13569 // Now we have only mask extension
13570 assert(InVT.getVectorElementType() == MVT::i1);
13571 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13572 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13573 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13574 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13575 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13576 MachinePointerInfo::getConstantPool(),
13577 false, false, false, Alignment);
13579 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13580 if (VT.is512BitVector())
13582 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13585 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13586 SelectionDAG &DAG) {
13587 if (Subtarget->hasFp256()) {
13588 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13596 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13597 SelectionDAG &DAG) {
13599 MVT VT = Op.getSimpleValueType();
13600 SDValue In = Op.getOperand(0);
13601 MVT SVT = In.getSimpleValueType();
13603 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13604 return LowerZERO_EXTEND_AVX512(Op, DAG);
13606 if (Subtarget->hasFp256()) {
13607 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13612 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13613 VT.getVectorNumElements() != SVT.getVectorNumElements());
13617 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13619 MVT VT = Op.getSimpleValueType();
13620 SDValue In = Op.getOperand(0);
13621 MVT InVT = In.getSimpleValueType();
13623 if (VT == MVT::i1) {
13624 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13625 "Invalid scalar TRUNCATE operation");
13626 if (InVT.getSizeInBits() >= 32)
13628 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13629 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13631 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13632 "Invalid TRUNCATE operation");
13634 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13635 if (VT.getVectorElementType().getSizeInBits() >=8)
13636 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13638 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13639 unsigned NumElts = InVT.getVectorNumElements();
13640 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13641 if (InVT.getSizeInBits() < 512) {
13642 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13643 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13647 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13648 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13649 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13650 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13651 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13652 MachinePointerInfo::getConstantPool(),
13653 false, false, false, Alignment);
13654 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13655 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13656 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13659 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13660 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13661 if (Subtarget->hasInt256()) {
13662 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13663 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13664 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13666 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13667 DAG.getIntPtrConstant(0));
13670 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13671 DAG.getIntPtrConstant(0));
13672 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13673 DAG.getIntPtrConstant(2));
13674 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13675 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13676 static const int ShufMask[] = {0, 2, 4, 6};
13677 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13680 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13681 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13682 if (Subtarget->hasInt256()) {
13683 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13685 SmallVector<SDValue,32> pshufbMask;
13686 for (unsigned i = 0; i < 2; ++i) {
13687 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13688 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13689 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13690 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13691 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13692 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13693 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13694 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13695 for (unsigned j = 0; j < 8; ++j)
13696 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13698 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13699 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13700 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13702 static const int ShufMask[] = {0, 2, -1, -1};
13703 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13705 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13706 DAG.getIntPtrConstant(0));
13707 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13710 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13711 DAG.getIntPtrConstant(0));
13713 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13714 DAG.getIntPtrConstant(4));
13716 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13717 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13719 // The PSHUFB mask:
13720 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13721 -1, -1, -1, -1, -1, -1, -1, -1};
13723 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13724 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13725 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13727 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13728 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13730 // The MOVLHPS Mask:
13731 static const int ShufMask2[] = {0, 1, 4, 5};
13732 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13733 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13736 // Handle truncation of V256 to V128 using shuffles.
13737 if (!VT.is128BitVector() || !InVT.is256BitVector())
13740 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13742 unsigned NumElems = VT.getVectorNumElements();
13743 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13745 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13746 // Prepare truncation shuffle mask
13747 for (unsigned i = 0; i != NumElems; ++i)
13748 MaskVec[i] = i * 2;
13749 SDValue V = DAG.getVectorShuffle(NVT, DL,
13750 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13751 DAG.getUNDEF(NVT), &MaskVec[0]);
13752 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13753 DAG.getIntPtrConstant(0));
13756 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13757 SelectionDAG &DAG) const {
13758 assert(!Op.getSimpleValueType().isVector());
13760 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13761 /*IsSigned=*/ true, /*IsReplace=*/ false);
13762 SDValue FIST = Vals.first, StackSlot = Vals.second;
13763 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13764 if (!FIST.getNode()) return Op;
13766 if (StackSlot.getNode())
13767 // Load the result.
13768 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13769 FIST, StackSlot, MachinePointerInfo(),
13770 false, false, false, 0);
13772 // The node is the result.
13776 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13777 SelectionDAG &DAG) const {
13778 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13779 /*IsSigned=*/ false, /*IsReplace=*/ false);
13780 SDValue FIST = Vals.first, StackSlot = Vals.second;
13781 assert(FIST.getNode() && "Unexpected failure");
13783 if (StackSlot.getNode())
13784 // Load the result.
13785 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13786 FIST, StackSlot, MachinePointerInfo(),
13787 false, false, false, 0);
13789 // The node is the result.
13793 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13795 MVT VT = Op.getSimpleValueType();
13796 SDValue In = Op.getOperand(0);
13797 MVT SVT = In.getSimpleValueType();
13799 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13801 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13802 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13803 In, DAG.getUNDEF(SVT)));
13806 /// The only differences between FABS and FNEG are the mask and the logic op.
13807 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13808 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13809 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13810 "Wrong opcode for lowering FABS or FNEG.");
13812 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13814 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13815 // into an FNABS. We'll lower the FABS after that if it is still in use.
13817 for (SDNode *User : Op->uses())
13818 if (User->getOpcode() == ISD::FNEG)
13821 SDValue Op0 = Op.getOperand(0);
13822 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13825 MVT VT = Op.getSimpleValueType();
13826 // Assume scalar op for initialization; update for vector if needed.
13827 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13828 // generate a 16-byte vector constant and logic op even for the scalar case.
13829 // Using a 16-byte mask allows folding the load of the mask with
13830 // the logic op, so it can save (~4 bytes) on code size.
13832 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13833 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13834 // decide if we should generate a 16-byte constant mask when we only need 4 or
13835 // 8 bytes for the scalar case.
13836 if (VT.isVector()) {
13837 EltVT = VT.getVectorElementType();
13838 NumElts = VT.getVectorNumElements();
13841 unsigned EltBits = EltVT.getSizeInBits();
13842 LLVMContext *Context = DAG.getContext();
13843 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13845 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13846 Constant *C = ConstantInt::get(*Context, MaskElt);
13847 C = ConstantVector::getSplat(NumElts, C);
13848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13849 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13850 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13851 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13852 MachinePointerInfo::getConstantPool(),
13853 false, false, false, Alignment);
13855 if (VT.isVector()) {
13856 // For a vector, cast operands to a vector type, perform the logic op,
13857 // and cast the result back to the original value type.
13858 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13859 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13860 SDValue Operand = IsFNABS ?
13861 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13862 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13863 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13864 return DAG.getNode(ISD::BITCAST, dl, VT,
13865 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13868 // If not vector, then scalar.
13869 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13870 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13871 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13874 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13876 LLVMContext *Context = DAG.getContext();
13877 SDValue Op0 = Op.getOperand(0);
13878 SDValue Op1 = Op.getOperand(1);
13880 MVT VT = Op.getSimpleValueType();
13881 MVT SrcVT = Op1.getSimpleValueType();
13883 // If second operand is smaller, extend it first.
13884 if (SrcVT.bitsLT(VT)) {
13885 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13888 // And if it is bigger, shrink it first.
13889 if (SrcVT.bitsGT(VT)) {
13890 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13894 // At this point the operands and the result should have the same
13895 // type, and that won't be f80 since that is not custom lowered.
13897 // First get the sign bit of second operand.
13898 SmallVector<Constant*,4> CV;
13899 if (SrcVT == MVT::f64) {
13900 const fltSemantics &Sem = APFloat::IEEEdouble;
13901 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13902 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13904 const fltSemantics &Sem = APFloat::IEEEsingle;
13905 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13906 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13907 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13908 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13910 Constant *C = ConstantVector::get(CV);
13911 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13912 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13913 MachinePointerInfo::getConstantPool(),
13914 false, false, false, 16);
13915 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13917 // Shift sign bit right or left if the two operands have different types.
13918 if (SrcVT.bitsGT(VT)) {
13919 // Op0 is MVT::f32, Op1 is MVT::f64.
13920 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13921 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13922 DAG.getConstant(32, MVT::i32));
13923 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13924 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13925 DAG.getIntPtrConstant(0));
13928 // Clear first operand sign bit.
13930 if (VT == MVT::f64) {
13931 const fltSemantics &Sem = APFloat::IEEEdouble;
13932 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13933 APInt(64, ~(1ULL << 63)))));
13934 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13936 const fltSemantics &Sem = APFloat::IEEEsingle;
13937 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13938 APInt(32, ~(1U << 31)))));
13939 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13940 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13941 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13943 C = ConstantVector::get(CV);
13944 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13945 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13946 MachinePointerInfo::getConstantPool(),
13947 false, false, false, 16);
13948 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13950 // Or the value with the sign bit.
13951 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13954 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13955 SDValue N0 = Op.getOperand(0);
13957 MVT VT = Op.getSimpleValueType();
13959 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13960 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13961 DAG.getConstant(1, VT));
13962 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13965 // Check whether an OR'd tree is PTEST-able.
13966 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13967 SelectionDAG &DAG) {
13968 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13970 if (!Subtarget->hasSSE41())
13973 if (!Op->hasOneUse())
13976 SDNode *N = Op.getNode();
13979 SmallVector<SDValue, 8> Opnds;
13980 DenseMap<SDValue, unsigned> VecInMap;
13981 SmallVector<SDValue, 8> VecIns;
13982 EVT VT = MVT::Other;
13984 // Recognize a special case where a vector is casted into wide integer to
13986 Opnds.push_back(N->getOperand(0));
13987 Opnds.push_back(N->getOperand(1));
13989 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13990 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13991 // BFS traverse all OR'd operands.
13992 if (I->getOpcode() == ISD::OR) {
13993 Opnds.push_back(I->getOperand(0));
13994 Opnds.push_back(I->getOperand(1));
13995 // Re-evaluate the number of nodes to be traversed.
13996 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14000 // Quit if a non-EXTRACT_VECTOR_ELT
14001 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14004 // Quit if without a constant index.
14005 SDValue Idx = I->getOperand(1);
14006 if (!isa<ConstantSDNode>(Idx))
14009 SDValue ExtractedFromVec = I->getOperand(0);
14010 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14011 if (M == VecInMap.end()) {
14012 VT = ExtractedFromVec.getValueType();
14013 // Quit if not 128/256-bit vector.
14014 if (!VT.is128BitVector() && !VT.is256BitVector())
14016 // Quit if not the same type.
14017 if (VecInMap.begin() != VecInMap.end() &&
14018 VT != VecInMap.begin()->first.getValueType())
14020 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14021 VecIns.push_back(ExtractedFromVec);
14023 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14026 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14027 "Not extracted from 128-/256-bit vector.");
14029 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14031 for (DenseMap<SDValue, unsigned>::const_iterator
14032 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14033 // Quit if not all elements are used.
14034 if (I->second != FullMask)
14038 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14040 // Cast all vectors into TestVT for PTEST.
14041 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14042 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14044 // If more than one full vectors are evaluated, OR them first before PTEST.
14045 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14046 // Each iteration will OR 2 nodes and append the result until there is only
14047 // 1 node left, i.e. the final OR'd value of all vectors.
14048 SDValue LHS = VecIns[Slot];
14049 SDValue RHS = VecIns[Slot + 1];
14050 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14053 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14054 VecIns.back(), VecIns.back());
14057 /// \brief return true if \c Op has a use that doesn't just read flags.
14058 static bool hasNonFlagsUse(SDValue Op) {
14059 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14061 SDNode *User = *UI;
14062 unsigned UOpNo = UI.getOperandNo();
14063 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14064 // Look pass truncate.
14065 UOpNo = User->use_begin().getOperandNo();
14066 User = *User->use_begin();
14069 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14070 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14076 /// Emit nodes that will be selected as "test Op0,Op0", or something
14078 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14079 SelectionDAG &DAG) const {
14080 if (Op.getValueType() == MVT::i1)
14081 // KORTEST instruction should be selected
14082 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14083 DAG.getConstant(0, Op.getValueType()));
14085 // CF and OF aren't always set the way we want. Determine which
14086 // of these we need.
14087 bool NeedCF = false;
14088 bool NeedOF = false;
14091 case X86::COND_A: case X86::COND_AE:
14092 case X86::COND_B: case X86::COND_BE:
14095 case X86::COND_G: case X86::COND_GE:
14096 case X86::COND_L: case X86::COND_LE:
14097 case X86::COND_O: case X86::COND_NO: {
14098 // Check if we really need to set the
14099 // Overflow flag. If NoSignedWrap is present
14100 // that is not actually needed.
14101 switch (Op->getOpcode()) {
14106 const BinaryWithFlagsSDNode *BinNode =
14107 cast<BinaryWithFlagsSDNode>(Op.getNode());
14108 if (BinNode->hasNoSignedWrap())
14118 // See if we can use the EFLAGS value from the operand instead of
14119 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14120 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14121 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14122 // Emit a CMP with 0, which is the TEST pattern.
14123 //if (Op.getValueType() == MVT::i1)
14124 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14125 // DAG.getConstant(0, MVT::i1));
14126 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14127 DAG.getConstant(0, Op.getValueType()));
14129 unsigned Opcode = 0;
14130 unsigned NumOperands = 0;
14132 // Truncate operations may prevent the merge of the SETCC instruction
14133 // and the arithmetic instruction before it. Attempt to truncate the operands
14134 // of the arithmetic instruction and use a reduced bit-width instruction.
14135 bool NeedTruncation = false;
14136 SDValue ArithOp = Op;
14137 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14138 SDValue Arith = Op->getOperand(0);
14139 // Both the trunc and the arithmetic op need to have one user each.
14140 if (Arith->hasOneUse())
14141 switch (Arith.getOpcode()) {
14148 NeedTruncation = true;
14154 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14155 // which may be the result of a CAST. We use the variable 'Op', which is the
14156 // non-casted variable when we check for possible users.
14157 switch (ArithOp.getOpcode()) {
14159 // Due to an isel shortcoming, be conservative if this add is likely to be
14160 // selected as part of a load-modify-store instruction. When the root node
14161 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14162 // uses of other nodes in the match, such as the ADD in this case. This
14163 // leads to the ADD being left around and reselected, with the result being
14164 // two adds in the output. Alas, even if none our users are stores, that
14165 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14166 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14167 // climbing the DAG back to the root, and it doesn't seem to be worth the
14169 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14170 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14171 if (UI->getOpcode() != ISD::CopyToReg &&
14172 UI->getOpcode() != ISD::SETCC &&
14173 UI->getOpcode() != ISD::STORE)
14176 if (ConstantSDNode *C =
14177 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14178 // An add of one will be selected as an INC.
14179 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14180 Opcode = X86ISD::INC;
14185 // An add of negative one (subtract of one) will be selected as a DEC.
14186 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14187 Opcode = X86ISD::DEC;
14193 // Otherwise use a regular EFLAGS-setting add.
14194 Opcode = X86ISD::ADD;
14199 // If we have a constant logical shift that's only used in a comparison
14200 // against zero turn it into an equivalent AND. This allows turning it into
14201 // a TEST instruction later.
14202 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14203 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14204 EVT VT = Op.getValueType();
14205 unsigned BitWidth = VT.getSizeInBits();
14206 unsigned ShAmt = Op->getConstantOperandVal(1);
14207 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14209 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14210 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14211 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14212 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14214 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14215 DAG.getConstant(Mask, VT));
14216 DAG.ReplaceAllUsesWith(Op, New);
14222 // If the primary and result isn't used, don't bother using X86ISD::AND,
14223 // because a TEST instruction will be better.
14224 if (!hasNonFlagsUse(Op))
14230 // Due to the ISEL shortcoming noted above, be conservative if this op is
14231 // likely to be selected as part of a load-modify-store instruction.
14232 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14233 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14234 if (UI->getOpcode() == ISD::STORE)
14237 // Otherwise use a regular EFLAGS-setting instruction.
14238 switch (ArithOp.getOpcode()) {
14239 default: llvm_unreachable("unexpected operator!");
14240 case ISD::SUB: Opcode = X86ISD::SUB; break;
14241 case ISD::XOR: Opcode = X86ISD::XOR; break;
14242 case ISD::AND: Opcode = X86ISD::AND; break;
14244 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14245 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14246 if (EFLAGS.getNode())
14249 Opcode = X86ISD::OR;
14263 return SDValue(Op.getNode(), 1);
14269 // If we found that truncation is beneficial, perform the truncation and
14271 if (NeedTruncation) {
14272 EVT VT = Op.getValueType();
14273 SDValue WideVal = Op->getOperand(0);
14274 EVT WideVT = WideVal.getValueType();
14275 unsigned ConvertedOp = 0;
14276 // Use a target machine opcode to prevent further DAGCombine
14277 // optimizations that may separate the arithmetic operations
14278 // from the setcc node.
14279 switch (WideVal.getOpcode()) {
14281 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14282 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14283 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14284 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14285 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14290 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14291 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14292 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14293 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14299 // Emit a CMP with 0, which is the TEST pattern.
14300 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14301 DAG.getConstant(0, Op.getValueType()));
14303 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14304 SmallVector<SDValue, 4> Ops;
14305 for (unsigned i = 0; i != NumOperands; ++i)
14306 Ops.push_back(Op.getOperand(i));
14308 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14309 DAG.ReplaceAllUsesWith(Op, New);
14310 return SDValue(New.getNode(), 1);
14313 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14315 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14316 SDLoc dl, SelectionDAG &DAG) const {
14317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14318 if (C->getAPIntValue() == 0)
14319 return EmitTest(Op0, X86CC, dl, DAG);
14321 if (Op0.getValueType() == MVT::i1)
14322 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14325 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14326 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14327 // Do the comparison at i32 if it's smaller, besides the Atom case.
14328 // This avoids subregister aliasing issues. Keep the smaller reference
14329 // if we're optimizing for size, however, as that'll allow better folding
14330 // of memory operations.
14331 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14332 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14333 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14334 !Subtarget->isAtom()) {
14335 unsigned ExtendOp =
14336 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14337 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14338 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14340 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14341 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14342 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14344 return SDValue(Sub.getNode(), 1);
14346 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14349 /// Convert a comparison if required by the subtarget.
14350 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14351 SelectionDAG &DAG) const {
14352 // If the subtarget does not support the FUCOMI instruction, floating-point
14353 // comparisons have to be converted.
14354 if (Subtarget->hasCMov() ||
14355 Cmp.getOpcode() != X86ISD::CMP ||
14356 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14357 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14360 // The instruction selector will select an FUCOM instruction instead of
14361 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14362 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14363 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14365 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14366 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14367 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14368 DAG.getConstant(8, MVT::i8));
14369 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14370 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14373 static bool isAllOnes(SDValue V) {
14374 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14375 return C && C->isAllOnesValue();
14378 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14379 /// if it's possible.
14380 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14381 SDLoc dl, SelectionDAG &DAG) const {
14382 SDValue Op0 = And.getOperand(0);
14383 SDValue Op1 = And.getOperand(1);
14384 if (Op0.getOpcode() == ISD::TRUNCATE)
14385 Op0 = Op0.getOperand(0);
14386 if (Op1.getOpcode() == ISD::TRUNCATE)
14387 Op1 = Op1.getOperand(0);
14390 if (Op1.getOpcode() == ISD::SHL)
14391 std::swap(Op0, Op1);
14392 if (Op0.getOpcode() == ISD::SHL) {
14393 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14394 if (And00C->getZExtValue() == 1) {
14395 // If we looked past a truncate, check that it's only truncating away
14397 unsigned BitWidth = Op0.getValueSizeInBits();
14398 unsigned AndBitWidth = And.getValueSizeInBits();
14399 if (BitWidth > AndBitWidth) {
14401 DAG.computeKnownBits(Op0, Zeros, Ones);
14402 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14406 RHS = Op0.getOperand(1);
14408 } else if (Op1.getOpcode() == ISD::Constant) {
14409 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14410 uint64_t AndRHSVal = AndRHS->getZExtValue();
14411 SDValue AndLHS = Op0;
14413 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14414 LHS = AndLHS.getOperand(0);
14415 RHS = AndLHS.getOperand(1);
14418 // Use BT if the immediate can't be encoded in a TEST instruction.
14419 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14421 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14425 if (LHS.getNode()) {
14426 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14427 // instruction. Since the shift amount is in-range-or-undefined, we know
14428 // that doing a bittest on the i32 value is ok. We extend to i32 because
14429 // the encoding for the i16 version is larger than the i32 version.
14430 // Also promote i16 to i32 for performance / code size reason.
14431 if (LHS.getValueType() == MVT::i8 ||
14432 LHS.getValueType() == MVT::i16)
14433 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14435 // If the operand types disagree, extend the shift amount to match. Since
14436 // BT ignores high bits (like shifts) we can use anyextend.
14437 if (LHS.getValueType() != RHS.getValueType())
14438 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14440 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14441 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14442 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14443 DAG.getConstant(Cond, MVT::i8), BT);
14449 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14451 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14456 // SSE Condition code mapping:
14465 switch (SetCCOpcode) {
14466 default: llvm_unreachable("Unexpected SETCC condition");
14468 case ISD::SETEQ: SSECC = 0; break;
14470 case ISD::SETGT: Swap = true; // Fallthrough
14472 case ISD::SETOLT: SSECC = 1; break;
14474 case ISD::SETGE: Swap = true; // Fallthrough
14476 case ISD::SETOLE: SSECC = 2; break;
14477 case ISD::SETUO: SSECC = 3; break;
14479 case ISD::SETNE: SSECC = 4; break;
14480 case ISD::SETULE: Swap = true; // Fallthrough
14481 case ISD::SETUGE: SSECC = 5; break;
14482 case ISD::SETULT: Swap = true; // Fallthrough
14483 case ISD::SETUGT: SSECC = 6; break;
14484 case ISD::SETO: SSECC = 7; break;
14486 case ISD::SETONE: SSECC = 8; break;
14489 std::swap(Op0, Op1);
14494 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14495 // ones, and then concatenate the result back.
14496 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14497 MVT VT = Op.getSimpleValueType();
14499 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14500 "Unsupported value type for operation");
14502 unsigned NumElems = VT.getVectorNumElements();
14504 SDValue CC = Op.getOperand(2);
14506 // Extract the LHS vectors
14507 SDValue LHS = Op.getOperand(0);
14508 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14509 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14511 // Extract the RHS vectors
14512 SDValue RHS = Op.getOperand(1);
14513 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14514 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14516 // Issue the operation on the smaller types and concatenate the result back
14517 MVT EltVT = VT.getVectorElementType();
14518 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14519 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14520 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14521 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14524 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14525 const X86Subtarget *Subtarget) {
14526 SDValue Op0 = Op.getOperand(0);
14527 SDValue Op1 = Op.getOperand(1);
14528 SDValue CC = Op.getOperand(2);
14529 MVT VT = Op.getSimpleValueType();
14532 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14533 Op.getValueType().getScalarType() == MVT::i1 &&
14534 "Cannot set masked compare for this operation");
14536 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14538 bool Unsigned = false;
14541 switch (SetCCOpcode) {
14542 default: llvm_unreachable("Unexpected SETCC condition");
14543 case ISD::SETNE: SSECC = 4; break;
14544 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14545 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14546 case ISD::SETLT: Swap = true; //fall-through
14547 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14548 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14549 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14550 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14551 case ISD::SETULE: Unsigned = true; //fall-through
14552 case ISD::SETLE: SSECC = 2; break;
14556 std::swap(Op0, Op1);
14558 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14559 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14560 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14561 DAG.getConstant(SSECC, MVT::i8));
14564 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14565 /// operand \p Op1. If non-trivial (for example because it's not constant)
14566 /// return an empty value.
14567 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14569 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14573 MVT VT = Op1.getSimpleValueType();
14574 MVT EVT = VT.getVectorElementType();
14575 unsigned n = VT.getVectorNumElements();
14576 SmallVector<SDValue, 8> ULTOp1;
14578 for (unsigned i = 0; i < n; ++i) {
14579 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14580 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14583 // Avoid underflow.
14584 APInt Val = Elt->getAPIntValue();
14588 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14591 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14594 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14595 SelectionDAG &DAG) {
14596 SDValue Op0 = Op.getOperand(0);
14597 SDValue Op1 = Op.getOperand(1);
14598 SDValue CC = Op.getOperand(2);
14599 MVT VT = Op.getSimpleValueType();
14600 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14601 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14606 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14607 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14610 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14611 unsigned Opc = X86ISD::CMPP;
14612 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14613 assert(VT.getVectorNumElements() <= 16);
14614 Opc = X86ISD::CMPM;
14616 // In the two special cases we can't handle, emit two comparisons.
14619 unsigned CombineOpc;
14620 if (SetCCOpcode == ISD::SETUEQ) {
14621 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14623 assert(SetCCOpcode == ISD::SETONE);
14624 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14627 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14628 DAG.getConstant(CC0, MVT::i8));
14629 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14630 DAG.getConstant(CC1, MVT::i8));
14631 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14633 // Handle all other FP comparisons here.
14634 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14635 DAG.getConstant(SSECC, MVT::i8));
14638 // Break 256-bit integer vector compare into smaller ones.
14639 if (VT.is256BitVector() && !Subtarget->hasInt256())
14640 return Lower256IntVSETCC(Op, DAG);
14642 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14643 EVT OpVT = Op1.getValueType();
14644 if (Subtarget->hasAVX512()) {
14645 if (Op1.getValueType().is512BitVector() ||
14646 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14647 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14648 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14650 // In AVX-512 architecture setcc returns mask with i1 elements,
14651 // But there is no compare instruction for i8 and i16 elements in KNL.
14652 // We are not talking about 512-bit operands in this case, these
14653 // types are illegal.
14655 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14656 OpVT.getVectorElementType().getSizeInBits() >= 8))
14657 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14658 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14661 // We are handling one of the integer comparisons here. Since SSE only has
14662 // GT and EQ comparisons for integer, swapping operands and multiple
14663 // operations may be required for some comparisons.
14665 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14666 bool Subus = false;
14668 switch (SetCCOpcode) {
14669 default: llvm_unreachable("Unexpected SETCC condition");
14670 case ISD::SETNE: Invert = true;
14671 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14672 case ISD::SETLT: Swap = true;
14673 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14674 case ISD::SETGE: Swap = true;
14675 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14676 Invert = true; break;
14677 case ISD::SETULT: Swap = true;
14678 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14679 FlipSigns = true; break;
14680 case ISD::SETUGE: Swap = true;
14681 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14682 FlipSigns = true; Invert = true; break;
14685 // Special case: Use min/max operations for SETULE/SETUGE
14686 MVT VET = VT.getVectorElementType();
14688 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14689 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14692 switch (SetCCOpcode) {
14694 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14695 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14698 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14701 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14702 if (!MinMax && hasSubus) {
14703 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14705 // t = psubus Op0, Op1
14706 // pcmpeq t, <0..0>
14707 switch (SetCCOpcode) {
14709 case ISD::SETULT: {
14710 // If the comparison is against a constant we can turn this into a
14711 // setule. With psubus, setule does not require a swap. This is
14712 // beneficial because the constant in the register is no longer
14713 // destructed as the destination so it can be hoisted out of a loop.
14714 // Only do this pre-AVX since vpcmp* is no longer destructive.
14715 if (Subtarget->hasAVX())
14717 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14718 if (ULEOp1.getNode()) {
14720 Subus = true; Invert = false; Swap = false;
14724 // Psubus is better than flip-sign because it requires no inversion.
14725 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14726 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14730 Opc = X86ISD::SUBUS;
14736 std::swap(Op0, Op1);
14738 // Check that the operation in question is available (most are plain SSE2,
14739 // but PCMPGTQ and PCMPEQQ have different requirements).
14740 if (VT == MVT::v2i64) {
14741 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14742 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14744 // First cast everything to the right type.
14745 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14746 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14748 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14749 // bits of the inputs before performing those operations. The lower
14750 // compare is always unsigned.
14753 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14755 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14756 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14757 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14758 Sign, Zero, Sign, Zero);
14760 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14761 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14763 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14764 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14765 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14767 // Create masks for only the low parts/high parts of the 64 bit integers.
14768 static const int MaskHi[] = { 1, 1, 3, 3 };
14769 static const int MaskLo[] = { 0, 0, 2, 2 };
14770 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14771 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14772 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14774 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14775 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14778 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14780 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14783 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14784 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14785 // pcmpeqd + pshufd + pand.
14786 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14788 // First cast everything to the right type.
14789 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14790 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14793 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14795 // Make sure the lower and upper halves are both all-ones.
14796 static const int Mask[] = { 1, 0, 3, 2 };
14797 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14798 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14801 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14803 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14807 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14808 // bits of the inputs before performing those operations.
14810 EVT EltVT = VT.getVectorElementType();
14811 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14812 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14813 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14816 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14818 // If the logical-not of the result is required, perform that now.
14820 Result = DAG.getNOT(dl, Result, VT);
14823 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14826 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14827 getZeroVector(VT, Subtarget, DAG, dl));
14832 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14834 MVT VT = Op.getSimpleValueType();
14836 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14838 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14839 && "SetCC type must be 8-bit or 1-bit integer");
14840 SDValue Op0 = Op.getOperand(0);
14841 SDValue Op1 = Op.getOperand(1);
14843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14845 // Optimize to BT if possible.
14846 // Lower (X & (1 << N)) == 0 to BT(X, N).
14847 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14848 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14849 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14850 Op1.getOpcode() == ISD::Constant &&
14851 cast<ConstantSDNode>(Op1)->isNullValue() &&
14852 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14853 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14854 if (NewSetCC.getNode())
14858 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14860 if (Op1.getOpcode() == ISD::Constant &&
14861 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14862 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14863 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14865 // If the input is a setcc, then reuse the input setcc or use a new one with
14866 // the inverted condition.
14867 if (Op0.getOpcode() == X86ISD::SETCC) {
14868 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14869 bool Invert = (CC == ISD::SETNE) ^
14870 cast<ConstantSDNode>(Op1)->isNullValue();
14874 CCode = X86::GetOppositeBranchCondition(CCode);
14875 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14876 DAG.getConstant(CCode, MVT::i8),
14877 Op0.getOperand(1));
14879 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14883 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14884 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14885 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14887 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14888 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14891 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14892 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14893 if (X86CC == X86::COND_INVALID)
14896 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14897 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14898 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14899 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14901 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14905 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14906 static bool isX86LogicalCmp(SDValue Op) {
14907 unsigned Opc = Op.getNode()->getOpcode();
14908 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14909 Opc == X86ISD::SAHF)
14911 if (Op.getResNo() == 1 &&
14912 (Opc == X86ISD::ADD ||
14913 Opc == X86ISD::SUB ||
14914 Opc == X86ISD::ADC ||
14915 Opc == X86ISD::SBB ||
14916 Opc == X86ISD::SMUL ||
14917 Opc == X86ISD::UMUL ||
14918 Opc == X86ISD::INC ||
14919 Opc == X86ISD::DEC ||
14920 Opc == X86ISD::OR ||
14921 Opc == X86ISD::XOR ||
14922 Opc == X86ISD::AND))
14925 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14931 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14932 if (V.getOpcode() != ISD::TRUNCATE)
14935 SDValue VOp0 = V.getOperand(0);
14936 unsigned InBits = VOp0.getValueSizeInBits();
14937 unsigned Bits = V.getValueSizeInBits();
14938 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14941 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14942 bool addTest = true;
14943 SDValue Cond = Op.getOperand(0);
14944 SDValue Op1 = Op.getOperand(1);
14945 SDValue Op2 = Op.getOperand(2);
14947 EVT VT = Op1.getValueType();
14950 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14951 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14952 // sequence later on.
14953 if (Cond.getOpcode() == ISD::SETCC &&
14954 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14955 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14956 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14957 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14958 int SSECC = translateX86FSETCC(
14959 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14962 if (Subtarget->hasAVX512()) {
14963 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14964 DAG.getConstant(SSECC, MVT::i8));
14965 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14967 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14968 DAG.getConstant(SSECC, MVT::i8));
14969 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14970 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14971 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14975 if (Cond.getOpcode() == ISD::SETCC) {
14976 SDValue NewCond = LowerSETCC(Cond, DAG);
14977 if (NewCond.getNode())
14981 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14982 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14983 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14984 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14985 if (Cond.getOpcode() == X86ISD::SETCC &&
14986 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14987 isZero(Cond.getOperand(1).getOperand(1))) {
14988 SDValue Cmp = Cond.getOperand(1);
14990 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14992 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14993 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14994 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14996 SDValue CmpOp0 = Cmp.getOperand(0);
14997 // Apply further optimizations for special cases
14998 // (select (x != 0), -1, 0) -> neg & sbb
14999 // (select (x == 0), 0, -1) -> neg & sbb
15000 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15001 if (YC->isNullValue() &&
15002 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15003 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15004 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15005 DAG.getConstant(0, CmpOp0.getValueType()),
15007 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15008 DAG.getConstant(X86::COND_B, MVT::i8),
15009 SDValue(Neg.getNode(), 1));
15013 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15014 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15015 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15017 SDValue Res = // Res = 0 or -1.
15018 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15019 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15021 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15022 Res = DAG.getNOT(DL, Res, Res.getValueType());
15024 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15025 if (!N2C || !N2C->isNullValue())
15026 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15031 // Look past (and (setcc_carry (cmp ...)), 1).
15032 if (Cond.getOpcode() == ISD::AND &&
15033 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15034 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15035 if (C && C->getAPIntValue() == 1)
15036 Cond = Cond.getOperand(0);
15039 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15040 // setting operand in place of the X86ISD::SETCC.
15041 unsigned CondOpcode = Cond.getOpcode();
15042 if (CondOpcode == X86ISD::SETCC ||
15043 CondOpcode == X86ISD::SETCC_CARRY) {
15044 CC = Cond.getOperand(0);
15046 SDValue Cmp = Cond.getOperand(1);
15047 unsigned Opc = Cmp.getOpcode();
15048 MVT VT = Op.getSimpleValueType();
15050 bool IllegalFPCMov = false;
15051 if (VT.isFloatingPoint() && !VT.isVector() &&
15052 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15053 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15055 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15056 Opc == X86ISD::BT) { // FIXME
15060 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15061 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15062 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15063 Cond.getOperand(0).getValueType() != MVT::i8)) {
15064 SDValue LHS = Cond.getOperand(0);
15065 SDValue RHS = Cond.getOperand(1);
15066 unsigned X86Opcode;
15069 switch (CondOpcode) {
15070 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15071 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15072 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15073 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15074 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15075 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15076 default: llvm_unreachable("unexpected overflowing operator");
15078 if (CondOpcode == ISD::UMULO)
15079 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15082 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15084 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15086 if (CondOpcode == ISD::UMULO)
15087 Cond = X86Op.getValue(2);
15089 Cond = X86Op.getValue(1);
15091 CC = DAG.getConstant(X86Cond, MVT::i8);
15096 // Look pass the truncate if the high bits are known zero.
15097 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15098 Cond = Cond.getOperand(0);
15100 // We know the result of AND is compared against zero. Try to match
15102 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15103 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15104 if (NewSetCC.getNode()) {
15105 CC = NewSetCC.getOperand(0);
15106 Cond = NewSetCC.getOperand(1);
15113 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15114 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15117 // a < b ? -1 : 0 -> RES = ~setcc_carry
15118 // a < b ? 0 : -1 -> RES = setcc_carry
15119 // a >= b ? -1 : 0 -> RES = setcc_carry
15120 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15121 if (Cond.getOpcode() == X86ISD::SUB) {
15122 Cond = ConvertCmpIfNecessary(Cond, DAG);
15123 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15125 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15126 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15127 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15128 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15129 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15130 return DAG.getNOT(DL, Res, Res.getValueType());
15135 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15136 // widen the cmov and push the truncate through. This avoids introducing a new
15137 // branch during isel and doesn't add any extensions.
15138 if (Op.getValueType() == MVT::i8 &&
15139 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15140 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15141 if (T1.getValueType() == T2.getValueType() &&
15142 // Blacklist CopyFromReg to avoid partial register stalls.
15143 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15144 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15145 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15146 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15150 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15151 // condition is true.
15152 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15153 SDValue Ops[] = { Op2, Op1, CC, Cond };
15154 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15157 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15158 SelectionDAG &DAG) {
15159 MVT VT = Op->getSimpleValueType(0);
15160 SDValue In = Op->getOperand(0);
15161 MVT InVT = In.getSimpleValueType();
15162 MVT VTElt = VT.getVectorElementType();
15163 MVT InVTElt = InVT.getVectorElementType();
15167 if ((InVTElt == MVT::i1) &&
15168 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15169 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15171 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15172 VTElt.getSizeInBits() <= 16)) ||
15174 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15175 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15177 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15178 VTElt.getSizeInBits() >= 32))))
15179 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15181 unsigned int NumElts = VT.getVectorNumElements();
15183 if (NumElts != 8 && NumElts != 16)
15186 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15187 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15190 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15192 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15193 Constant *C = ConstantInt::get(*DAG.getContext(),
15194 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15196 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15197 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15198 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15199 MachinePointerInfo::getConstantPool(),
15200 false, false, false, Alignment);
15201 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15202 if (VT.is512BitVector())
15204 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15207 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15208 SelectionDAG &DAG) {
15209 MVT VT = Op->getSimpleValueType(0);
15210 SDValue In = Op->getOperand(0);
15211 MVT InVT = In.getSimpleValueType();
15214 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15215 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15217 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15218 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15219 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15222 if (Subtarget->hasInt256())
15223 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15225 // Optimize vectors in AVX mode
15226 // Sign extend v8i16 to v8i32 and
15229 // Divide input vector into two parts
15230 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15231 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15232 // concat the vectors to original VT
15234 unsigned NumElems = InVT.getVectorNumElements();
15235 SDValue Undef = DAG.getUNDEF(InVT);
15237 SmallVector<int,8> ShufMask1(NumElems, -1);
15238 for (unsigned i = 0; i != NumElems/2; ++i)
15241 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15243 SmallVector<int,8> ShufMask2(NumElems, -1);
15244 for (unsigned i = 0; i != NumElems/2; ++i)
15245 ShufMask2[i] = i + NumElems/2;
15247 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15249 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15250 VT.getVectorNumElements()/2);
15252 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15253 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15255 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15258 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15259 // may emit an illegal shuffle but the expansion is still better than scalar
15260 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15261 // we'll emit a shuffle and a arithmetic shift.
15262 // TODO: It is possible to support ZExt by zeroing the undef values during
15263 // the shuffle phase or after the shuffle.
15264 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15265 SelectionDAG &DAG) {
15266 MVT RegVT = Op.getSimpleValueType();
15267 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15268 assert(RegVT.isInteger() &&
15269 "We only custom lower integer vector sext loads.");
15271 // Nothing useful we can do without SSE2 shuffles.
15272 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15274 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15276 EVT MemVT = Ld->getMemoryVT();
15277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15278 unsigned RegSz = RegVT.getSizeInBits();
15280 ISD::LoadExtType Ext = Ld->getExtensionType();
15282 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15283 && "Only anyext and sext are currently implemented.");
15284 assert(MemVT != RegVT && "Cannot extend to the same type");
15285 assert(MemVT.isVector() && "Must load a vector from memory");
15287 unsigned NumElems = RegVT.getVectorNumElements();
15288 unsigned MemSz = MemVT.getSizeInBits();
15289 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15291 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15292 // The only way in which we have a legal 256-bit vector result but not the
15293 // integer 256-bit operations needed to directly lower a sextload is if we
15294 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15295 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15296 // correctly legalized. We do this late to allow the canonical form of
15297 // sextload to persist throughout the rest of the DAG combiner -- it wants
15298 // to fold together any extensions it can, and so will fuse a sign_extend
15299 // of an sextload into a sextload targeting a wider value.
15301 if (MemSz == 128) {
15302 // Just switch this to a normal load.
15303 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15304 "it must be a legal 128-bit vector "
15306 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15307 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15308 Ld->isInvariant(), Ld->getAlignment());
15310 assert(MemSz < 128 &&
15311 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15312 // Do an sext load to a 128-bit vector type. We want to use the same
15313 // number of elements, but elements half as wide. This will end up being
15314 // recursively lowered by this routine, but will succeed as we definitely
15315 // have all the necessary features if we're using AVX1.
15317 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15318 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15320 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15321 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15322 Ld->isNonTemporal(), Ld->isInvariant(),
15323 Ld->getAlignment());
15326 // Replace chain users with the new chain.
15327 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15328 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15330 // Finally, do a normal sign-extend to the desired register.
15331 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15334 // All sizes must be a power of two.
15335 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15336 "Non-power-of-two elements are not custom lowered!");
15338 // Attempt to load the original value using scalar loads.
15339 // Find the largest scalar type that divides the total loaded size.
15340 MVT SclrLoadTy = MVT::i8;
15341 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15342 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15343 MVT Tp = (MVT::SimpleValueType)tp;
15344 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15349 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15350 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15352 SclrLoadTy = MVT::f64;
15354 // Calculate the number of scalar loads that we need to perform
15355 // in order to load our vector from memory.
15356 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15358 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15359 "Can only lower sext loads with a single scalar load!");
15361 unsigned loadRegZize = RegSz;
15362 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15365 // Represent our vector as a sequence of elements which are the
15366 // largest scalar that we can load.
15367 EVT LoadUnitVecVT = EVT::getVectorVT(
15368 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15370 // Represent the data using the same element type that is stored in
15371 // memory. In practice, we ''widen'' MemVT.
15373 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15374 loadRegZize / MemVT.getScalarType().getSizeInBits());
15376 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15377 "Invalid vector type");
15379 // We can't shuffle using an illegal type.
15380 assert(TLI.isTypeLegal(WideVecVT) &&
15381 "We only lower types that form legal widened vector types");
15383 SmallVector<SDValue, 8> Chains;
15384 SDValue Ptr = Ld->getBasePtr();
15385 SDValue Increment =
15386 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15387 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15389 for (unsigned i = 0; i < NumLoads; ++i) {
15390 // Perform a single load.
15391 SDValue ScalarLoad =
15392 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15393 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15394 Ld->getAlignment());
15395 Chains.push_back(ScalarLoad.getValue(1));
15396 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15397 // another round of DAGCombining.
15399 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15401 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15402 ScalarLoad, DAG.getIntPtrConstant(i));
15404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15407 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15409 // Bitcast the loaded value to a vector of the original element type, in
15410 // the size of the target vector type.
15411 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15412 unsigned SizeRatio = RegSz / MemSz;
15414 if (Ext == ISD::SEXTLOAD) {
15415 // If we have SSE4.1, we can directly emit a VSEXT node.
15416 if (Subtarget->hasSSE41()) {
15417 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15418 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15422 // Otherwise we'll shuffle the small elements in the high bits of the
15423 // larger type and perform an arithmetic shift. If the shift is not legal
15424 // it's better to scalarize.
15425 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15426 "We can't implement a sext load without an arithmetic right shift!");
15428 // Redistribute the loaded elements into the different locations.
15429 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15430 for (unsigned i = 0; i != NumElems; ++i)
15431 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15433 SDValue Shuff = DAG.getVectorShuffle(
15434 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15436 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15438 // Build the arithmetic shift.
15439 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15440 MemVT.getVectorElementType().getSizeInBits();
15442 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15444 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15448 // Redistribute the loaded elements into the different locations.
15449 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15450 for (unsigned i = 0; i != NumElems; ++i)
15451 ShuffleVec[i * SizeRatio] = i;
15453 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15454 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15456 // Bitcast to the requested type.
15457 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15458 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15462 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15463 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15464 // from the AND / OR.
15465 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15466 Opc = Op.getOpcode();
15467 if (Opc != ISD::OR && Opc != ISD::AND)
15469 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15470 Op.getOperand(0).hasOneUse() &&
15471 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15472 Op.getOperand(1).hasOneUse());
15475 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15476 // 1 and that the SETCC node has a single use.
15477 static bool isXor1OfSetCC(SDValue Op) {
15478 if (Op.getOpcode() != ISD::XOR)
15480 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15481 if (N1C && N1C->getAPIntValue() == 1) {
15482 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15483 Op.getOperand(0).hasOneUse();
15488 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15489 bool addTest = true;
15490 SDValue Chain = Op.getOperand(0);
15491 SDValue Cond = Op.getOperand(1);
15492 SDValue Dest = Op.getOperand(2);
15495 bool Inverted = false;
15497 if (Cond.getOpcode() == ISD::SETCC) {
15498 // Check for setcc([su]{add,sub,mul}o == 0).
15499 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15500 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15501 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15502 Cond.getOperand(0).getResNo() == 1 &&
15503 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15504 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15505 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15506 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15507 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15508 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15510 Cond = Cond.getOperand(0);
15512 SDValue NewCond = LowerSETCC(Cond, DAG);
15513 if (NewCond.getNode())
15518 // FIXME: LowerXALUO doesn't handle these!!
15519 else if (Cond.getOpcode() == X86ISD::ADD ||
15520 Cond.getOpcode() == X86ISD::SUB ||
15521 Cond.getOpcode() == X86ISD::SMUL ||
15522 Cond.getOpcode() == X86ISD::UMUL)
15523 Cond = LowerXALUO(Cond, DAG);
15526 // Look pass (and (setcc_carry (cmp ...)), 1).
15527 if (Cond.getOpcode() == ISD::AND &&
15528 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15529 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15530 if (C && C->getAPIntValue() == 1)
15531 Cond = Cond.getOperand(0);
15534 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15535 // setting operand in place of the X86ISD::SETCC.
15536 unsigned CondOpcode = Cond.getOpcode();
15537 if (CondOpcode == X86ISD::SETCC ||
15538 CondOpcode == X86ISD::SETCC_CARRY) {
15539 CC = Cond.getOperand(0);
15541 SDValue Cmp = Cond.getOperand(1);
15542 unsigned Opc = Cmp.getOpcode();
15543 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15544 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15548 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15552 // These can only come from an arithmetic instruction with overflow,
15553 // e.g. SADDO, UADDO.
15554 Cond = Cond.getNode()->getOperand(1);
15560 CondOpcode = Cond.getOpcode();
15561 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15562 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15563 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15564 Cond.getOperand(0).getValueType() != MVT::i8)) {
15565 SDValue LHS = Cond.getOperand(0);
15566 SDValue RHS = Cond.getOperand(1);
15567 unsigned X86Opcode;
15570 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15571 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15573 switch (CondOpcode) {
15574 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15576 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15578 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15581 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15582 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15586 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15589 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15590 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15591 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15592 default: llvm_unreachable("unexpected overflowing operator");
15595 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15596 if (CondOpcode == ISD::UMULO)
15597 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15600 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15602 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15604 if (CondOpcode == ISD::UMULO)
15605 Cond = X86Op.getValue(2);
15607 Cond = X86Op.getValue(1);
15609 CC = DAG.getConstant(X86Cond, MVT::i8);
15613 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15614 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15615 if (CondOpc == ISD::OR) {
15616 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15617 // two branches instead of an explicit OR instruction with a
15619 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15620 isX86LogicalCmp(Cmp)) {
15621 CC = Cond.getOperand(0).getOperand(0);
15622 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15623 Chain, Dest, CC, Cmp);
15624 CC = Cond.getOperand(1).getOperand(0);
15628 } else { // ISD::AND
15629 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15630 // two branches instead of an explicit AND instruction with a
15631 // separate test. However, we only do this if this block doesn't
15632 // have a fall-through edge, because this requires an explicit
15633 // jmp when the condition is false.
15634 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15635 isX86LogicalCmp(Cmp) &&
15636 Op.getNode()->hasOneUse()) {
15637 X86::CondCode CCode =
15638 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15639 CCode = X86::GetOppositeBranchCondition(CCode);
15640 CC = DAG.getConstant(CCode, MVT::i8);
15641 SDNode *User = *Op.getNode()->use_begin();
15642 // Look for an unconditional branch following this conditional branch.
15643 // We need this because we need to reverse the successors in order
15644 // to implement FCMP_OEQ.
15645 if (User->getOpcode() == ISD::BR) {
15646 SDValue FalseBB = User->getOperand(1);
15648 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15649 assert(NewBR == User);
15653 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15654 Chain, Dest, CC, Cmp);
15655 X86::CondCode CCode =
15656 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15657 CCode = X86::GetOppositeBranchCondition(CCode);
15658 CC = DAG.getConstant(CCode, MVT::i8);
15664 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15665 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15666 // It should be transformed during dag combiner except when the condition
15667 // is set by a arithmetics with overflow node.
15668 X86::CondCode CCode =
15669 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15670 CCode = X86::GetOppositeBranchCondition(CCode);
15671 CC = DAG.getConstant(CCode, MVT::i8);
15672 Cond = Cond.getOperand(0).getOperand(1);
15674 } else if (Cond.getOpcode() == ISD::SETCC &&
15675 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15676 // For FCMP_OEQ, we can emit
15677 // two branches instead of an explicit AND instruction with a
15678 // separate test. However, we only do this if this block doesn't
15679 // have a fall-through edge, because this requires an explicit
15680 // jmp when the condition is false.
15681 if (Op.getNode()->hasOneUse()) {
15682 SDNode *User = *Op.getNode()->use_begin();
15683 // Look for an unconditional branch following this conditional branch.
15684 // We need this because we need to reverse the successors in order
15685 // to implement FCMP_OEQ.
15686 if (User->getOpcode() == ISD::BR) {
15687 SDValue FalseBB = User->getOperand(1);
15689 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15690 assert(NewBR == User);
15694 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15695 Cond.getOperand(0), Cond.getOperand(1));
15696 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15697 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15698 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15699 Chain, Dest, CC, Cmp);
15700 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15705 } else if (Cond.getOpcode() == ISD::SETCC &&
15706 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15707 // For FCMP_UNE, we can emit
15708 // two branches instead of an explicit AND instruction with a
15709 // separate test. However, we only do this if this block doesn't
15710 // have a fall-through edge, because this requires an explicit
15711 // jmp when the condition is false.
15712 if (Op.getNode()->hasOneUse()) {
15713 SDNode *User = *Op.getNode()->use_begin();
15714 // Look for an unconditional branch following this conditional branch.
15715 // We need this because we need to reverse the successors in order
15716 // to implement FCMP_UNE.
15717 if (User->getOpcode() == ISD::BR) {
15718 SDValue FalseBB = User->getOperand(1);
15720 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15721 assert(NewBR == User);
15724 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15725 Cond.getOperand(0), Cond.getOperand(1));
15726 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15727 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15728 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15729 Chain, Dest, CC, Cmp);
15730 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15740 // Look pass the truncate if the high bits are known zero.
15741 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15742 Cond = Cond.getOperand(0);
15744 // We know the result of AND is compared against zero. Try to match
15746 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15747 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15748 if (NewSetCC.getNode()) {
15749 CC = NewSetCC.getOperand(0);
15750 Cond = NewSetCC.getOperand(1);
15757 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15758 CC = DAG.getConstant(X86Cond, MVT::i8);
15759 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15761 Cond = ConvertCmpIfNecessary(Cond, DAG);
15762 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15763 Chain, Dest, CC, Cond);
15766 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15767 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15768 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15769 // that the guard pages used by the OS virtual memory manager are allocated in
15770 // correct sequence.
15772 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15773 SelectionDAG &DAG) const {
15774 MachineFunction &MF = DAG.getMachineFunction();
15775 bool SplitStack = MF.shouldSplitStack();
15776 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15782 SDNode* Node = Op.getNode();
15784 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15785 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15786 " not tell us which reg is the stack pointer!");
15787 EVT VT = Node->getValueType(0);
15788 SDValue Tmp1 = SDValue(Node, 0);
15789 SDValue Tmp2 = SDValue(Node, 1);
15790 SDValue Tmp3 = Node->getOperand(2);
15791 SDValue Chain = Tmp1.getOperand(0);
15793 // Chain the dynamic stack allocation so that it doesn't modify the stack
15794 // pointer when other instructions are using the stack.
15795 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15798 SDValue Size = Tmp2.getOperand(1);
15799 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15800 Chain = SP.getValue(1);
15801 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15802 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15803 unsigned StackAlign = TFI.getStackAlignment();
15804 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15805 if (Align > StackAlign)
15806 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15807 DAG.getConstant(-(uint64_t)Align, VT));
15808 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15810 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15811 DAG.getIntPtrConstant(0, true), SDValue(),
15814 SDValue Ops[2] = { Tmp1, Tmp2 };
15815 return DAG.getMergeValues(Ops, dl);
15819 SDValue Chain = Op.getOperand(0);
15820 SDValue Size = Op.getOperand(1);
15821 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15822 EVT VT = Op.getNode()->getValueType(0);
15824 bool Is64Bit = Subtarget->is64Bit();
15825 EVT SPTy = getPointerTy();
15828 MachineRegisterInfo &MRI = MF.getRegInfo();
15831 // The 64 bit implementation of segmented stacks needs to clobber both r10
15832 // r11. This makes it impossible to use it along with nested parameters.
15833 const Function *F = MF.getFunction();
15835 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15837 if (I->hasNestAttr())
15838 report_fatal_error("Cannot use segmented stacks with functions that "
15839 "have nested arguments.");
15842 const TargetRegisterClass *AddrRegClass =
15843 getRegClassFor(getPointerTy());
15844 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15845 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15846 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15847 DAG.getRegister(Vreg, SPTy));
15848 SDValue Ops1[2] = { Value, Chain };
15849 return DAG.getMergeValues(Ops1, dl);
15852 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15854 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15855 Flag = Chain.getValue(1);
15856 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15858 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15860 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15861 DAG.getSubtarget().getRegisterInfo());
15862 unsigned SPReg = RegInfo->getStackRegister();
15863 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15864 Chain = SP.getValue(1);
15867 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15868 DAG.getConstant(-(uint64_t)Align, VT));
15869 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15872 SDValue Ops1[2] = { SP, Chain };
15873 return DAG.getMergeValues(Ops1, dl);
15877 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15878 MachineFunction &MF = DAG.getMachineFunction();
15879 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15881 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15884 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15885 // vastart just stores the address of the VarArgsFrameIndex slot into the
15886 // memory location argument.
15887 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15889 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15890 MachinePointerInfo(SV), false, false, 0);
15894 // gp_offset (0 - 6 * 8)
15895 // fp_offset (48 - 48 + 8 * 16)
15896 // overflow_arg_area (point to parameters coming in memory).
15898 SmallVector<SDValue, 8> MemOps;
15899 SDValue FIN = Op.getOperand(1);
15901 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15902 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15904 FIN, MachinePointerInfo(SV), false, false, 0);
15905 MemOps.push_back(Store);
15908 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15909 FIN, DAG.getIntPtrConstant(4));
15910 Store = DAG.getStore(Op.getOperand(0), DL,
15911 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15913 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15914 MemOps.push_back(Store);
15916 // Store ptr to overflow_arg_area
15917 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15918 FIN, DAG.getIntPtrConstant(4));
15919 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15921 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15922 MachinePointerInfo(SV, 8),
15924 MemOps.push_back(Store);
15926 // Store ptr to reg_save_area.
15927 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15928 FIN, DAG.getIntPtrConstant(8));
15929 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15931 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15932 MachinePointerInfo(SV, 16), false, false, 0);
15933 MemOps.push_back(Store);
15934 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15937 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15938 assert(Subtarget->is64Bit() &&
15939 "LowerVAARG only handles 64-bit va_arg!");
15940 assert((Subtarget->isTargetLinux() ||
15941 Subtarget->isTargetDarwin()) &&
15942 "Unhandled target in LowerVAARG");
15943 assert(Op.getNode()->getNumOperands() == 4);
15944 SDValue Chain = Op.getOperand(0);
15945 SDValue SrcPtr = Op.getOperand(1);
15946 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15947 unsigned Align = Op.getConstantOperandVal(3);
15950 EVT ArgVT = Op.getNode()->getValueType(0);
15951 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15952 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15955 // Decide which area this value should be read from.
15956 // TODO: Implement the AMD64 ABI in its entirety. This simple
15957 // selection mechanism works only for the basic types.
15958 if (ArgVT == MVT::f80) {
15959 llvm_unreachable("va_arg for f80 not yet implemented");
15960 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15961 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15962 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15963 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15965 llvm_unreachable("Unhandled argument type in LowerVAARG");
15968 if (ArgMode == 2) {
15969 // Sanity Check: Make sure using fp_offset makes sense.
15970 assert(!DAG.getTarget().Options.UseSoftFloat &&
15971 !(DAG.getMachineFunction()
15972 .getFunction()->getAttributes()
15973 .hasAttribute(AttributeSet::FunctionIndex,
15974 Attribute::NoImplicitFloat)) &&
15975 Subtarget->hasSSE1());
15978 // Insert VAARG_64 node into the DAG
15979 // VAARG_64 returns two values: Variable Argument Address, Chain
15980 SmallVector<SDValue, 11> InstOps;
15981 InstOps.push_back(Chain);
15982 InstOps.push_back(SrcPtr);
15983 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15984 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15985 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15986 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15987 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15988 VTs, InstOps, MVT::i64,
15989 MachinePointerInfo(SV),
15991 /*Volatile=*/false,
15993 /*WriteMem=*/true);
15994 Chain = VAARG.getValue(1);
15996 // Load the next argument and return it
15997 return DAG.getLoad(ArgVT, dl,
16000 MachinePointerInfo(),
16001 false, false, false, 0);
16004 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16005 SelectionDAG &DAG) {
16006 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16007 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16008 SDValue Chain = Op.getOperand(0);
16009 SDValue DstPtr = Op.getOperand(1);
16010 SDValue SrcPtr = Op.getOperand(2);
16011 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16012 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16015 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16016 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16018 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16021 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16022 // amount is a constant. Takes immediate version of shift as input.
16023 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16024 SDValue SrcOp, uint64_t ShiftAmt,
16025 SelectionDAG &DAG) {
16026 MVT ElementType = VT.getVectorElementType();
16028 // Fold this packed shift into its first operand if ShiftAmt is 0.
16032 // Check for ShiftAmt >= element width
16033 if (ShiftAmt >= ElementType.getSizeInBits()) {
16034 if (Opc == X86ISD::VSRAI)
16035 ShiftAmt = ElementType.getSizeInBits() - 1;
16037 return DAG.getConstant(0, VT);
16040 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16041 && "Unknown target vector shift-by-constant node");
16043 // Fold this packed vector shift into a build vector if SrcOp is a
16044 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16045 if (VT == SrcOp.getSimpleValueType() &&
16046 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16047 SmallVector<SDValue, 8> Elts;
16048 unsigned NumElts = SrcOp->getNumOperands();
16049 ConstantSDNode *ND;
16052 default: llvm_unreachable(nullptr);
16053 case X86ISD::VSHLI:
16054 for (unsigned i=0; i!=NumElts; ++i) {
16055 SDValue CurrentOp = SrcOp->getOperand(i);
16056 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16057 Elts.push_back(CurrentOp);
16060 ND = cast<ConstantSDNode>(CurrentOp);
16061 const APInt &C = ND->getAPIntValue();
16062 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16065 case X86ISD::VSRLI:
16066 for (unsigned i=0; i!=NumElts; ++i) {
16067 SDValue CurrentOp = SrcOp->getOperand(i);
16068 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16069 Elts.push_back(CurrentOp);
16072 ND = cast<ConstantSDNode>(CurrentOp);
16073 const APInt &C = ND->getAPIntValue();
16074 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16077 case X86ISD::VSRAI:
16078 for (unsigned i=0; i!=NumElts; ++i) {
16079 SDValue CurrentOp = SrcOp->getOperand(i);
16080 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16081 Elts.push_back(CurrentOp);
16084 ND = cast<ConstantSDNode>(CurrentOp);
16085 const APInt &C = ND->getAPIntValue();
16086 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16091 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16094 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16097 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16098 // may or may not be a constant. Takes immediate version of shift as input.
16099 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16100 SDValue SrcOp, SDValue ShAmt,
16101 SelectionDAG &DAG) {
16102 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16104 // Catch shift-by-constant.
16105 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16106 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16107 CShAmt->getZExtValue(), DAG);
16109 // Change opcode to non-immediate version
16111 default: llvm_unreachable("Unknown target vector shift node");
16112 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16113 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16114 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16117 // Need to build a vector containing shift amount
16118 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16121 ShOps[1] = DAG.getConstant(0, MVT::i32);
16122 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16123 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16125 // The return type has to be a 128-bit type with the same element
16126 // type as the input type.
16127 MVT EltVT = VT.getVectorElementType();
16128 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16130 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16131 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16134 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16135 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16136 /// necessary casting for \p Mask when lowering masking intrinsics.
16137 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16138 SDValue PreservedSrc, SelectionDAG &DAG) {
16139 EVT VT = Op.getValueType();
16140 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16141 MVT::i1, VT.getVectorNumElements());
16142 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16143 Mask.getValueType().getSizeInBits());
16146 assert(MaskVT.isSimple() && "invalid mask type");
16148 if (isAllOnes(Mask))
16151 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16152 // are extracted by EXTRACT_SUBVECTOR.
16153 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16154 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16155 DAG.getIntPtrConstant(0));
16157 switch (Op.getOpcode()) {
16159 case X86ISD::PCMPEQM:
16160 case X86ISD::PCMPGTM:
16162 case X86ISD::CMPMU:
16163 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16166 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16169 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16171 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16172 case Intrinsic::x86_fma_vfmadd_ps:
16173 case Intrinsic::x86_fma_vfmadd_pd:
16174 case Intrinsic::x86_fma_vfmadd_ps_256:
16175 case Intrinsic::x86_fma_vfmadd_pd_256:
16176 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16177 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16178 return X86ISD::FMADD;
16179 case Intrinsic::x86_fma_vfmsub_ps:
16180 case Intrinsic::x86_fma_vfmsub_pd:
16181 case Intrinsic::x86_fma_vfmsub_ps_256:
16182 case Intrinsic::x86_fma_vfmsub_pd_256:
16183 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16184 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16185 return X86ISD::FMSUB;
16186 case Intrinsic::x86_fma_vfnmadd_ps:
16187 case Intrinsic::x86_fma_vfnmadd_pd:
16188 case Intrinsic::x86_fma_vfnmadd_ps_256:
16189 case Intrinsic::x86_fma_vfnmadd_pd_256:
16190 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16191 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16192 return X86ISD::FNMADD;
16193 case Intrinsic::x86_fma_vfnmsub_ps:
16194 case Intrinsic::x86_fma_vfnmsub_pd:
16195 case Intrinsic::x86_fma_vfnmsub_ps_256:
16196 case Intrinsic::x86_fma_vfnmsub_pd_256:
16197 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16198 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16199 return X86ISD::FNMSUB;
16200 case Intrinsic::x86_fma_vfmaddsub_ps:
16201 case Intrinsic::x86_fma_vfmaddsub_pd:
16202 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16203 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16204 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16205 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16206 return X86ISD::FMADDSUB;
16207 case Intrinsic::x86_fma_vfmsubadd_ps:
16208 case Intrinsic::x86_fma_vfmsubadd_pd:
16209 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16210 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16211 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16212 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16213 return X86ISD::FMSUBADD;
16217 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16219 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16221 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16223 switch(IntrData->Type) {
16224 case INTR_TYPE_1OP:
16225 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16226 case INTR_TYPE_2OP:
16227 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16229 case INTR_TYPE_3OP:
16230 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16231 Op.getOperand(2), Op.getOperand(3));
16233 case CMP_MASK_CC: {
16234 // Comparison intrinsics with masks.
16235 // Example of transformation:
16236 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16237 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16239 // (v8i1 (insert_subvector undef,
16240 // (v2i1 (and (PCMPEQM %a, %b),
16241 // (extract_subvector
16242 // (v8i1 (bitcast %mask)), 0))), 0))))
16243 EVT VT = Op.getOperand(1).getValueType();
16244 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16245 VT.getVectorNumElements());
16246 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16247 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16248 Mask.getValueType().getSizeInBits());
16250 if (IntrData->Type == CMP_MASK_CC) {
16251 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16252 Op.getOperand(2), Op.getOperand(3));
16254 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16255 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16258 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16259 DAG.getTargetConstant(0, MaskVT), DAG);
16260 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16261 DAG.getUNDEF(BitcastVT), CmpMask,
16262 DAG.getIntPtrConstant(0));
16263 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16265 case COMI: { // Comparison intrinsics
16266 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16267 SDValue LHS = Op.getOperand(1);
16268 SDValue RHS = Op.getOperand(2);
16269 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16270 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16271 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16272 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16273 DAG.getConstant(X86CC, MVT::i8), Cond);
16274 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16277 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16278 Op.getOperand(1), Op.getOperand(2), DAG);
16285 default: return SDValue(); // Don't custom lower most intrinsics.
16287 // Arithmetic intrinsics.
16288 case Intrinsic::x86_sse2_pmulu_dq:
16289 case Intrinsic::x86_avx2_pmulu_dq:
16290 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16291 Op.getOperand(1), Op.getOperand(2));
16293 case Intrinsic::x86_sse41_pmuldq:
16294 case Intrinsic::x86_avx2_pmul_dq:
16295 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16296 Op.getOperand(1), Op.getOperand(2));
16298 case Intrinsic::x86_sse2_pmulhu_w:
16299 case Intrinsic::x86_avx2_pmulhu_w:
16300 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16301 Op.getOperand(1), Op.getOperand(2));
16303 case Intrinsic::x86_sse2_pmulh_w:
16304 case Intrinsic::x86_avx2_pmulh_w:
16305 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16306 Op.getOperand(1), Op.getOperand(2));
16308 // SSE/SSE2/AVX floating point max/min intrinsics.
16309 case Intrinsic::x86_sse_max_ps:
16310 case Intrinsic::x86_sse2_max_pd:
16311 case Intrinsic::x86_avx_max_ps_256:
16312 case Intrinsic::x86_avx_max_pd_256:
16313 case Intrinsic::x86_sse_min_ps:
16314 case Intrinsic::x86_sse2_min_pd:
16315 case Intrinsic::x86_avx_min_ps_256:
16316 case Intrinsic::x86_avx_min_pd_256: {
16319 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16320 case Intrinsic::x86_sse_max_ps:
16321 case Intrinsic::x86_sse2_max_pd:
16322 case Intrinsic::x86_avx_max_ps_256:
16323 case Intrinsic::x86_avx_max_pd_256:
16324 Opcode = X86ISD::FMAX;
16326 case Intrinsic::x86_sse_min_ps:
16327 case Intrinsic::x86_sse2_min_pd:
16328 case Intrinsic::x86_avx_min_ps_256:
16329 case Intrinsic::x86_avx_min_pd_256:
16330 Opcode = X86ISD::FMIN;
16333 return DAG.getNode(Opcode, dl, Op.getValueType(),
16334 Op.getOperand(1), Op.getOperand(2));
16337 // AVX2 variable shift intrinsics
16338 case Intrinsic::x86_avx2_psllv_d:
16339 case Intrinsic::x86_avx2_psllv_q:
16340 case Intrinsic::x86_avx2_psllv_d_256:
16341 case Intrinsic::x86_avx2_psllv_q_256:
16342 case Intrinsic::x86_avx2_psrlv_d:
16343 case Intrinsic::x86_avx2_psrlv_q:
16344 case Intrinsic::x86_avx2_psrlv_d_256:
16345 case Intrinsic::x86_avx2_psrlv_q_256:
16346 case Intrinsic::x86_avx2_psrav_d:
16347 case Intrinsic::x86_avx2_psrav_d_256: {
16350 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16351 case Intrinsic::x86_avx2_psllv_d:
16352 case Intrinsic::x86_avx2_psllv_q:
16353 case Intrinsic::x86_avx2_psllv_d_256:
16354 case Intrinsic::x86_avx2_psllv_q_256:
16357 case Intrinsic::x86_avx2_psrlv_d:
16358 case Intrinsic::x86_avx2_psrlv_q:
16359 case Intrinsic::x86_avx2_psrlv_d_256:
16360 case Intrinsic::x86_avx2_psrlv_q_256:
16363 case Intrinsic::x86_avx2_psrav_d:
16364 case Intrinsic::x86_avx2_psrav_d_256:
16368 return DAG.getNode(Opcode, dl, Op.getValueType(),
16369 Op.getOperand(1), Op.getOperand(2));
16372 case Intrinsic::x86_sse2_packssdw_128:
16373 case Intrinsic::x86_sse2_packsswb_128:
16374 case Intrinsic::x86_avx2_packssdw:
16375 case Intrinsic::x86_avx2_packsswb:
16376 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16377 Op.getOperand(1), Op.getOperand(2));
16379 case Intrinsic::x86_sse2_packuswb_128:
16380 case Intrinsic::x86_sse41_packusdw:
16381 case Intrinsic::x86_avx2_packuswb:
16382 case Intrinsic::x86_avx2_packusdw:
16383 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16384 Op.getOperand(1), Op.getOperand(2));
16386 case Intrinsic::x86_ssse3_pshuf_b_128:
16387 case Intrinsic::x86_avx2_pshuf_b:
16388 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16389 Op.getOperand(1), Op.getOperand(2));
16391 case Intrinsic::x86_sse2_pshuf_d:
16392 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16393 Op.getOperand(1), Op.getOperand(2));
16395 case Intrinsic::x86_sse2_pshufl_w:
16396 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16397 Op.getOperand(1), Op.getOperand(2));
16399 case Intrinsic::x86_sse2_pshufh_w:
16400 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16401 Op.getOperand(1), Op.getOperand(2));
16403 case Intrinsic::x86_ssse3_psign_b_128:
16404 case Intrinsic::x86_ssse3_psign_w_128:
16405 case Intrinsic::x86_ssse3_psign_d_128:
16406 case Intrinsic::x86_avx2_psign_b:
16407 case Intrinsic::x86_avx2_psign_w:
16408 case Intrinsic::x86_avx2_psign_d:
16409 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16410 Op.getOperand(1), Op.getOperand(2));
16412 case Intrinsic::x86_avx2_permd:
16413 case Intrinsic::x86_avx2_permps:
16414 // Operands intentionally swapped. Mask is last operand to intrinsic,
16415 // but second operand for node/instruction.
16416 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16417 Op.getOperand(2), Op.getOperand(1));
16419 case Intrinsic::x86_avx512_mask_valign_q_512:
16420 case Intrinsic::x86_avx512_mask_valign_d_512:
16421 // Vector source operands are swapped.
16422 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16423 Op.getValueType(), Op.getOperand(2),
16426 Op.getOperand(5), Op.getOperand(4), DAG);
16428 // ptest and testp intrinsics. The intrinsic these come from are designed to
16429 // return an integer value, not just an instruction so lower it to the ptest
16430 // or testp pattern and a setcc for the result.
16431 case Intrinsic::x86_sse41_ptestz:
16432 case Intrinsic::x86_sse41_ptestc:
16433 case Intrinsic::x86_sse41_ptestnzc:
16434 case Intrinsic::x86_avx_ptestz_256:
16435 case Intrinsic::x86_avx_ptestc_256:
16436 case Intrinsic::x86_avx_ptestnzc_256:
16437 case Intrinsic::x86_avx_vtestz_ps:
16438 case Intrinsic::x86_avx_vtestc_ps:
16439 case Intrinsic::x86_avx_vtestnzc_ps:
16440 case Intrinsic::x86_avx_vtestz_pd:
16441 case Intrinsic::x86_avx_vtestc_pd:
16442 case Intrinsic::x86_avx_vtestnzc_pd:
16443 case Intrinsic::x86_avx_vtestz_ps_256:
16444 case Intrinsic::x86_avx_vtestc_ps_256:
16445 case Intrinsic::x86_avx_vtestnzc_ps_256:
16446 case Intrinsic::x86_avx_vtestz_pd_256:
16447 case Intrinsic::x86_avx_vtestc_pd_256:
16448 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16449 bool IsTestPacked = false;
16452 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16453 case Intrinsic::x86_avx_vtestz_ps:
16454 case Intrinsic::x86_avx_vtestz_pd:
16455 case Intrinsic::x86_avx_vtestz_ps_256:
16456 case Intrinsic::x86_avx_vtestz_pd_256:
16457 IsTestPacked = true; // Fallthrough
16458 case Intrinsic::x86_sse41_ptestz:
16459 case Intrinsic::x86_avx_ptestz_256:
16461 X86CC = X86::COND_E;
16463 case Intrinsic::x86_avx_vtestc_ps:
16464 case Intrinsic::x86_avx_vtestc_pd:
16465 case Intrinsic::x86_avx_vtestc_ps_256:
16466 case Intrinsic::x86_avx_vtestc_pd_256:
16467 IsTestPacked = true; // Fallthrough
16468 case Intrinsic::x86_sse41_ptestc:
16469 case Intrinsic::x86_avx_ptestc_256:
16471 X86CC = X86::COND_B;
16473 case Intrinsic::x86_avx_vtestnzc_ps:
16474 case Intrinsic::x86_avx_vtestnzc_pd:
16475 case Intrinsic::x86_avx_vtestnzc_ps_256:
16476 case Intrinsic::x86_avx_vtestnzc_pd_256:
16477 IsTestPacked = true; // Fallthrough
16478 case Intrinsic::x86_sse41_ptestnzc:
16479 case Intrinsic::x86_avx_ptestnzc_256:
16481 X86CC = X86::COND_A;
16485 SDValue LHS = Op.getOperand(1);
16486 SDValue RHS = Op.getOperand(2);
16487 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16488 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16489 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16490 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16491 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16493 case Intrinsic::x86_avx512_kortestz_w:
16494 case Intrinsic::x86_avx512_kortestc_w: {
16495 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16496 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16497 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16498 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16499 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16500 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16501 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16504 case Intrinsic::x86_sse42_pcmpistria128:
16505 case Intrinsic::x86_sse42_pcmpestria128:
16506 case Intrinsic::x86_sse42_pcmpistric128:
16507 case Intrinsic::x86_sse42_pcmpestric128:
16508 case Intrinsic::x86_sse42_pcmpistrio128:
16509 case Intrinsic::x86_sse42_pcmpestrio128:
16510 case Intrinsic::x86_sse42_pcmpistris128:
16511 case Intrinsic::x86_sse42_pcmpestris128:
16512 case Intrinsic::x86_sse42_pcmpistriz128:
16513 case Intrinsic::x86_sse42_pcmpestriz128: {
16517 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16518 case Intrinsic::x86_sse42_pcmpistria128:
16519 Opcode = X86ISD::PCMPISTRI;
16520 X86CC = X86::COND_A;
16522 case Intrinsic::x86_sse42_pcmpestria128:
16523 Opcode = X86ISD::PCMPESTRI;
16524 X86CC = X86::COND_A;
16526 case Intrinsic::x86_sse42_pcmpistric128:
16527 Opcode = X86ISD::PCMPISTRI;
16528 X86CC = X86::COND_B;
16530 case Intrinsic::x86_sse42_pcmpestric128:
16531 Opcode = X86ISD::PCMPESTRI;
16532 X86CC = X86::COND_B;
16534 case Intrinsic::x86_sse42_pcmpistrio128:
16535 Opcode = X86ISD::PCMPISTRI;
16536 X86CC = X86::COND_O;
16538 case Intrinsic::x86_sse42_pcmpestrio128:
16539 Opcode = X86ISD::PCMPESTRI;
16540 X86CC = X86::COND_O;
16542 case Intrinsic::x86_sse42_pcmpistris128:
16543 Opcode = X86ISD::PCMPISTRI;
16544 X86CC = X86::COND_S;
16546 case Intrinsic::x86_sse42_pcmpestris128:
16547 Opcode = X86ISD::PCMPESTRI;
16548 X86CC = X86::COND_S;
16550 case Intrinsic::x86_sse42_pcmpistriz128:
16551 Opcode = X86ISD::PCMPISTRI;
16552 X86CC = X86::COND_E;
16554 case Intrinsic::x86_sse42_pcmpestriz128:
16555 Opcode = X86ISD::PCMPESTRI;
16556 X86CC = X86::COND_E;
16559 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16560 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16561 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16562 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16563 DAG.getConstant(X86CC, MVT::i8),
16564 SDValue(PCMP.getNode(), 1));
16565 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16568 case Intrinsic::x86_sse42_pcmpistri128:
16569 case Intrinsic::x86_sse42_pcmpestri128: {
16571 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16572 Opcode = X86ISD::PCMPISTRI;
16574 Opcode = X86ISD::PCMPESTRI;
16576 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16577 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16578 return DAG.getNode(Opcode, dl, VTs, NewOps);
16581 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16582 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16583 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16584 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16585 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16586 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16587 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16588 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16589 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16590 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16591 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16592 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16593 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16594 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16595 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16596 dl, Op.getValueType(),
16600 Op.getOperand(4), Op.getOperand(1), DAG);
16605 case Intrinsic::x86_fma_vfmadd_ps:
16606 case Intrinsic::x86_fma_vfmadd_pd:
16607 case Intrinsic::x86_fma_vfmsub_ps:
16608 case Intrinsic::x86_fma_vfmsub_pd:
16609 case Intrinsic::x86_fma_vfnmadd_ps:
16610 case Intrinsic::x86_fma_vfnmadd_pd:
16611 case Intrinsic::x86_fma_vfnmsub_ps:
16612 case Intrinsic::x86_fma_vfnmsub_pd:
16613 case Intrinsic::x86_fma_vfmaddsub_ps:
16614 case Intrinsic::x86_fma_vfmaddsub_pd:
16615 case Intrinsic::x86_fma_vfmsubadd_ps:
16616 case Intrinsic::x86_fma_vfmsubadd_pd:
16617 case Intrinsic::x86_fma_vfmadd_ps_256:
16618 case Intrinsic::x86_fma_vfmadd_pd_256:
16619 case Intrinsic::x86_fma_vfmsub_ps_256:
16620 case Intrinsic::x86_fma_vfmsub_pd_256:
16621 case Intrinsic::x86_fma_vfnmadd_ps_256:
16622 case Intrinsic::x86_fma_vfnmadd_pd_256:
16623 case Intrinsic::x86_fma_vfnmsub_ps_256:
16624 case Intrinsic::x86_fma_vfnmsub_pd_256:
16625 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16626 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16627 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16628 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16629 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16630 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16634 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16635 SDValue Src, SDValue Mask, SDValue Base,
16636 SDValue Index, SDValue ScaleOp, SDValue Chain,
16637 const X86Subtarget * Subtarget) {
16639 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16640 assert(C && "Invalid scale type");
16641 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16642 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16643 Index.getSimpleValueType().getVectorNumElements());
16645 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16647 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16649 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16650 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16651 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16652 SDValue Segment = DAG.getRegister(0, MVT::i32);
16653 if (Src.getOpcode() == ISD::UNDEF)
16654 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16655 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16656 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16657 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16658 return DAG.getMergeValues(RetOps, dl);
16661 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16662 SDValue Src, SDValue Mask, SDValue Base,
16663 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16665 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16666 assert(C && "Invalid scale type");
16667 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16668 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16669 SDValue Segment = DAG.getRegister(0, MVT::i32);
16670 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16671 Index.getSimpleValueType().getVectorNumElements());
16673 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16675 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16677 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16678 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16679 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16680 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16681 return SDValue(Res, 1);
16684 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16685 SDValue Mask, SDValue Base, SDValue Index,
16686 SDValue ScaleOp, SDValue Chain) {
16688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16689 assert(C && "Invalid scale type");
16690 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16691 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16692 SDValue Segment = DAG.getRegister(0, MVT::i32);
16694 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16696 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16698 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16700 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16701 //SDVTList VTs = DAG.getVTList(MVT::Other);
16702 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16703 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16704 return SDValue(Res, 0);
16707 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16708 // read performance monitor counters (x86_rdpmc).
16709 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16710 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16711 SmallVectorImpl<SDValue> &Results) {
16712 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16713 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16716 // The ECX register is used to select the index of the performance counter
16718 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16720 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16722 // Reads the content of a 64-bit performance counter and returns it in the
16723 // registers EDX:EAX.
16724 if (Subtarget->is64Bit()) {
16725 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16726 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16729 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16730 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16733 Chain = HI.getValue(1);
16735 if (Subtarget->is64Bit()) {
16736 // The EAX register is loaded with the low-order 32 bits. The EDX register
16737 // is loaded with the supported high-order bits of the counter.
16738 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16739 DAG.getConstant(32, MVT::i8));
16740 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16741 Results.push_back(Chain);
16745 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16746 SDValue Ops[] = { LO, HI };
16747 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16748 Results.push_back(Pair);
16749 Results.push_back(Chain);
16752 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16753 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16754 // also used to custom lower READCYCLECOUNTER nodes.
16755 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16756 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16757 SmallVectorImpl<SDValue> &Results) {
16758 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16759 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16762 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16763 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16764 // and the EAX register is loaded with the low-order 32 bits.
16765 if (Subtarget->is64Bit()) {
16766 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16767 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16770 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16771 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16774 SDValue Chain = HI.getValue(1);
16776 if (Opcode == X86ISD::RDTSCP_DAG) {
16777 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16779 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16780 // the ECX register. Add 'ecx' explicitly to the chain.
16781 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16783 // Explicitly store the content of ECX at the location passed in input
16784 // to the 'rdtscp' intrinsic.
16785 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16786 MachinePointerInfo(), false, false, 0);
16789 if (Subtarget->is64Bit()) {
16790 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16791 // the EAX register is loaded with the low-order 32 bits.
16792 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16793 DAG.getConstant(32, MVT::i8));
16794 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16795 Results.push_back(Chain);
16799 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16800 SDValue Ops[] = { LO, HI };
16801 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16802 Results.push_back(Pair);
16803 Results.push_back(Chain);
16806 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16807 SelectionDAG &DAG) {
16808 SmallVector<SDValue, 2> Results;
16810 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16812 return DAG.getMergeValues(Results, DL);
16816 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16817 SelectionDAG &DAG) {
16818 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16820 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16825 switch(IntrData->Type) {
16827 llvm_unreachable("Unknown Intrinsic Type");
16831 // Emit the node with the right value type.
16832 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16833 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16835 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16836 // Otherwise return the value from Rand, which is always 0, casted to i32.
16837 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16838 DAG.getConstant(1, Op->getValueType(1)),
16839 DAG.getConstant(X86::COND_B, MVT::i32),
16840 SDValue(Result.getNode(), 1) };
16841 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16842 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16845 // Return { result, isValid, chain }.
16846 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16847 SDValue(Result.getNode(), 2));
16850 //gather(v1, mask, index, base, scale);
16851 SDValue Chain = Op.getOperand(0);
16852 SDValue Src = Op.getOperand(2);
16853 SDValue Base = Op.getOperand(3);
16854 SDValue Index = Op.getOperand(4);
16855 SDValue Mask = Op.getOperand(5);
16856 SDValue Scale = Op.getOperand(6);
16857 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16861 //scatter(base, mask, index, v1, scale);
16862 SDValue Chain = Op.getOperand(0);
16863 SDValue Base = Op.getOperand(2);
16864 SDValue Mask = Op.getOperand(3);
16865 SDValue Index = Op.getOperand(4);
16866 SDValue Src = Op.getOperand(5);
16867 SDValue Scale = Op.getOperand(6);
16868 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16871 SDValue Hint = Op.getOperand(6);
16873 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16874 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16875 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16876 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16877 SDValue Chain = Op.getOperand(0);
16878 SDValue Mask = Op.getOperand(2);
16879 SDValue Index = Op.getOperand(3);
16880 SDValue Base = Op.getOperand(4);
16881 SDValue Scale = Op.getOperand(5);
16882 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16884 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16886 SmallVector<SDValue, 2> Results;
16887 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16888 return DAG.getMergeValues(Results, dl);
16890 // Read Performance Monitoring Counters.
16892 SmallVector<SDValue, 2> Results;
16893 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16894 return DAG.getMergeValues(Results, dl);
16896 // XTEST intrinsics.
16898 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16899 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16900 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16901 DAG.getConstant(X86::COND_NE, MVT::i8),
16903 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16904 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16905 Ret, SDValue(InTrans.getNode(), 1));
16909 SmallVector<SDValue, 2> Results;
16910 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16911 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16912 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16913 DAG.getConstant(-1, MVT::i8));
16914 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16915 Op.getOperand(4), GenCF.getValue(1));
16916 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16917 Op.getOperand(5), MachinePointerInfo(),
16919 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16920 DAG.getConstant(X86::COND_B, MVT::i8),
16922 Results.push_back(SetCC);
16923 Results.push_back(Store);
16924 return DAG.getMergeValues(Results, dl);
16929 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16930 SelectionDAG &DAG) const {
16931 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16932 MFI->setReturnAddressIsTaken(true);
16934 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16937 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16939 EVT PtrVT = getPointerTy();
16942 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16943 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16944 DAG.getSubtarget().getRegisterInfo());
16945 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16946 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16947 DAG.getNode(ISD::ADD, dl, PtrVT,
16948 FrameAddr, Offset),
16949 MachinePointerInfo(), false, false, false, 0);
16952 // Just load the return address.
16953 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16954 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16955 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16958 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16959 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16960 MFI->setFrameAddressIsTaken(true);
16962 EVT VT = Op.getValueType();
16963 SDLoc dl(Op); // FIXME probably not meaningful
16964 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16965 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16966 DAG.getSubtarget().getRegisterInfo());
16967 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16968 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16969 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16970 "Invalid Frame Register!");
16971 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16973 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16974 MachinePointerInfo(),
16975 false, false, false, 0);
16979 // FIXME? Maybe this could be a TableGen attribute on some registers and
16980 // this table could be generated automatically from RegInfo.
16981 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16983 unsigned Reg = StringSwitch<unsigned>(RegName)
16984 .Case("esp", X86::ESP)
16985 .Case("rsp", X86::RSP)
16989 report_fatal_error("Invalid register name global variable");
16992 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16993 SelectionDAG &DAG) const {
16994 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16995 DAG.getSubtarget().getRegisterInfo());
16996 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16999 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17000 SDValue Chain = Op.getOperand(0);
17001 SDValue Offset = Op.getOperand(1);
17002 SDValue Handler = Op.getOperand(2);
17005 EVT PtrVT = getPointerTy();
17006 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17007 DAG.getSubtarget().getRegisterInfo());
17008 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17009 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17010 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17011 "Invalid Frame Register!");
17012 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17013 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17015 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17016 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17017 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17018 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17020 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17022 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17023 DAG.getRegister(StoreAddrReg, PtrVT));
17026 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17027 SelectionDAG &DAG) const {
17029 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17030 DAG.getVTList(MVT::i32, MVT::Other),
17031 Op.getOperand(0), Op.getOperand(1));
17034 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17035 SelectionDAG &DAG) const {
17037 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17038 Op.getOperand(0), Op.getOperand(1));
17041 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17042 return Op.getOperand(0);
17045 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17046 SelectionDAG &DAG) const {
17047 SDValue Root = Op.getOperand(0);
17048 SDValue Trmp = Op.getOperand(1); // trampoline
17049 SDValue FPtr = Op.getOperand(2); // nested function
17050 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17053 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17054 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17056 if (Subtarget->is64Bit()) {
17057 SDValue OutChains[6];
17059 // Large code-model.
17060 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17061 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17063 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17064 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17066 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17068 // Load the pointer to the nested function into R11.
17069 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17070 SDValue Addr = Trmp;
17071 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17072 Addr, MachinePointerInfo(TrmpAddr),
17075 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17076 DAG.getConstant(2, MVT::i64));
17077 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17078 MachinePointerInfo(TrmpAddr, 2),
17081 // Load the 'nest' parameter value into R10.
17082 // R10 is specified in X86CallingConv.td
17083 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17084 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17085 DAG.getConstant(10, MVT::i64));
17086 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17087 Addr, MachinePointerInfo(TrmpAddr, 10),
17090 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17091 DAG.getConstant(12, MVT::i64));
17092 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17093 MachinePointerInfo(TrmpAddr, 12),
17096 // Jump to the nested function.
17097 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17098 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17099 DAG.getConstant(20, MVT::i64));
17100 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17101 Addr, MachinePointerInfo(TrmpAddr, 20),
17104 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17105 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17106 DAG.getConstant(22, MVT::i64));
17107 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17108 MachinePointerInfo(TrmpAddr, 22),
17111 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17113 const Function *Func =
17114 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17115 CallingConv::ID CC = Func->getCallingConv();
17120 llvm_unreachable("Unsupported calling convention");
17121 case CallingConv::C:
17122 case CallingConv::X86_StdCall: {
17123 // Pass 'nest' parameter in ECX.
17124 // Must be kept in sync with X86CallingConv.td
17125 NestReg = X86::ECX;
17127 // Check that ECX wasn't needed by an 'inreg' parameter.
17128 FunctionType *FTy = Func->getFunctionType();
17129 const AttributeSet &Attrs = Func->getAttributes();
17131 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17132 unsigned InRegCount = 0;
17135 for (FunctionType::param_iterator I = FTy->param_begin(),
17136 E = FTy->param_end(); I != E; ++I, ++Idx)
17137 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17138 // FIXME: should only count parameters that are lowered to integers.
17139 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17141 if (InRegCount > 2) {
17142 report_fatal_error("Nest register in use - reduce number of inreg"
17148 case CallingConv::X86_FastCall:
17149 case CallingConv::X86_ThisCall:
17150 case CallingConv::Fast:
17151 // Pass 'nest' parameter in EAX.
17152 // Must be kept in sync with X86CallingConv.td
17153 NestReg = X86::EAX;
17157 SDValue OutChains[4];
17158 SDValue Addr, Disp;
17160 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17161 DAG.getConstant(10, MVT::i32));
17162 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17164 // This is storing the opcode for MOV32ri.
17165 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17166 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17167 OutChains[0] = DAG.getStore(Root, dl,
17168 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17169 Trmp, MachinePointerInfo(TrmpAddr),
17172 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17173 DAG.getConstant(1, MVT::i32));
17174 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17175 MachinePointerInfo(TrmpAddr, 1),
17178 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17180 DAG.getConstant(5, MVT::i32));
17181 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17182 MachinePointerInfo(TrmpAddr, 5),
17185 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17186 DAG.getConstant(6, MVT::i32));
17187 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17188 MachinePointerInfo(TrmpAddr, 6),
17191 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17195 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17196 SelectionDAG &DAG) const {
17198 The rounding mode is in bits 11:10 of FPSR, and has the following
17200 00 Round to nearest
17205 FLT_ROUNDS, on the other hand, expects the following:
17212 To perform the conversion, we do:
17213 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17216 MachineFunction &MF = DAG.getMachineFunction();
17217 const TargetMachine &TM = MF.getTarget();
17218 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17219 unsigned StackAlignment = TFI.getStackAlignment();
17220 MVT VT = Op.getSimpleValueType();
17223 // Save FP Control Word to stack slot
17224 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17225 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17227 MachineMemOperand *MMO =
17228 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17229 MachineMemOperand::MOStore, 2, 2);
17231 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17232 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17233 DAG.getVTList(MVT::Other),
17234 Ops, MVT::i16, MMO);
17236 // Load FP Control Word from stack slot
17237 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17238 MachinePointerInfo(), false, false, false, 0);
17240 // Transform as necessary
17242 DAG.getNode(ISD::SRL, DL, MVT::i16,
17243 DAG.getNode(ISD::AND, DL, MVT::i16,
17244 CWD, DAG.getConstant(0x800, MVT::i16)),
17245 DAG.getConstant(11, MVT::i8));
17247 DAG.getNode(ISD::SRL, DL, MVT::i16,
17248 DAG.getNode(ISD::AND, DL, MVT::i16,
17249 CWD, DAG.getConstant(0x400, MVT::i16)),
17250 DAG.getConstant(9, MVT::i8));
17253 DAG.getNode(ISD::AND, DL, MVT::i16,
17254 DAG.getNode(ISD::ADD, DL, MVT::i16,
17255 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17256 DAG.getConstant(1, MVT::i16)),
17257 DAG.getConstant(3, MVT::i16));
17259 return DAG.getNode((VT.getSizeInBits() < 16 ?
17260 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17263 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17264 MVT VT = Op.getSimpleValueType();
17266 unsigned NumBits = VT.getSizeInBits();
17269 Op = Op.getOperand(0);
17270 if (VT == MVT::i8) {
17271 // Zero extend to i32 since there is not an i8 bsr.
17273 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17276 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17277 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17278 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17280 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17283 DAG.getConstant(NumBits+NumBits-1, OpVT),
17284 DAG.getConstant(X86::COND_E, MVT::i8),
17287 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17289 // Finally xor with NumBits-1.
17290 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17293 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17297 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17298 MVT VT = Op.getSimpleValueType();
17300 unsigned NumBits = VT.getSizeInBits();
17303 Op = Op.getOperand(0);
17304 if (VT == MVT::i8) {
17305 // Zero extend to i32 since there is not an i8 bsr.
17307 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17310 // Issue a bsr (scan bits in reverse).
17311 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17312 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17314 // And xor with NumBits-1.
17315 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17318 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17322 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17323 MVT VT = Op.getSimpleValueType();
17324 unsigned NumBits = VT.getSizeInBits();
17326 Op = Op.getOperand(0);
17328 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17329 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17330 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17332 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17335 DAG.getConstant(NumBits, VT),
17336 DAG.getConstant(X86::COND_E, MVT::i8),
17339 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17342 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17343 // ones, and then concatenate the result back.
17344 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17345 MVT VT = Op.getSimpleValueType();
17347 assert(VT.is256BitVector() && VT.isInteger() &&
17348 "Unsupported value type for operation");
17350 unsigned NumElems = VT.getVectorNumElements();
17353 // Extract the LHS vectors
17354 SDValue LHS = Op.getOperand(0);
17355 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17356 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17358 // Extract the RHS vectors
17359 SDValue RHS = Op.getOperand(1);
17360 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17361 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17363 MVT EltVT = VT.getVectorElementType();
17364 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17367 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17368 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17371 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17372 assert(Op.getSimpleValueType().is256BitVector() &&
17373 Op.getSimpleValueType().isInteger() &&
17374 "Only handle AVX 256-bit vector integer operation");
17375 return Lower256IntArith(Op, DAG);
17378 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17379 assert(Op.getSimpleValueType().is256BitVector() &&
17380 Op.getSimpleValueType().isInteger() &&
17381 "Only handle AVX 256-bit vector integer operation");
17382 return Lower256IntArith(Op, DAG);
17385 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17386 SelectionDAG &DAG) {
17388 MVT VT = Op.getSimpleValueType();
17390 // Decompose 256-bit ops into smaller 128-bit ops.
17391 if (VT.is256BitVector() && !Subtarget->hasInt256())
17392 return Lower256IntArith(Op, DAG);
17394 SDValue A = Op.getOperand(0);
17395 SDValue B = Op.getOperand(1);
17397 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17398 if (VT == MVT::v4i32) {
17399 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17400 "Should not custom lower when pmuldq is available!");
17402 // Extract the odd parts.
17403 static const int UnpackMask[] = { 1, -1, 3, -1 };
17404 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17405 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17407 // Multiply the even parts.
17408 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17409 // Now multiply odd parts.
17410 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17412 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17413 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17415 // Merge the two vectors back together with a shuffle. This expands into 2
17417 static const int ShufMask[] = { 0, 4, 2, 6 };
17418 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17421 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17422 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17424 // Ahi = psrlqi(a, 32);
17425 // Bhi = psrlqi(b, 32);
17427 // AloBlo = pmuludq(a, b);
17428 // AloBhi = pmuludq(a, Bhi);
17429 // AhiBlo = pmuludq(Ahi, b);
17431 // AloBhi = psllqi(AloBhi, 32);
17432 // AhiBlo = psllqi(AhiBlo, 32);
17433 // return AloBlo + AloBhi + AhiBlo;
17435 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17436 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17438 // Bit cast to 32-bit vectors for MULUDQ
17439 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17440 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17441 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17442 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17443 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17444 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17446 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17447 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17448 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17450 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17451 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17453 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17454 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17457 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17458 assert(Subtarget->isTargetWin64() && "Unexpected target");
17459 EVT VT = Op.getValueType();
17460 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17461 "Unexpected return type for lowering");
17465 switch (Op->getOpcode()) {
17466 default: llvm_unreachable("Unexpected request for libcall!");
17467 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17468 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17469 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17470 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17471 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17472 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17476 SDValue InChain = DAG.getEntryNode();
17478 TargetLowering::ArgListTy Args;
17479 TargetLowering::ArgListEntry Entry;
17480 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17481 EVT ArgVT = Op->getOperand(i).getValueType();
17482 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17483 "Unexpected argument type for lowering");
17484 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17485 Entry.Node = StackPtr;
17486 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17488 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17489 Entry.Ty = PointerType::get(ArgTy,0);
17490 Entry.isSExt = false;
17491 Entry.isZExt = false;
17492 Args.push_back(Entry);
17495 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17498 TargetLowering::CallLoweringInfo CLI(DAG);
17499 CLI.setDebugLoc(dl).setChain(InChain)
17500 .setCallee(getLibcallCallingConv(LC),
17501 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17502 Callee, std::move(Args), 0)
17503 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17505 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17506 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17509 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17510 SelectionDAG &DAG) {
17511 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17512 EVT VT = Op0.getValueType();
17515 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17516 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17518 // PMULxD operations multiply each even value (starting at 0) of LHS with
17519 // the related value of RHS and produce a widen result.
17520 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17521 // => <2 x i64> <ae|cg>
17523 // In other word, to have all the results, we need to perform two PMULxD:
17524 // 1. one with the even values.
17525 // 2. one with the odd values.
17526 // To achieve #2, with need to place the odd values at an even position.
17528 // Place the odd value at an even position (basically, shift all values 1
17529 // step to the left):
17530 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17531 // <a|b|c|d> => <b|undef|d|undef>
17532 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17533 // <e|f|g|h> => <f|undef|h|undef>
17534 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17536 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17538 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17539 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17541 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17542 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17543 // => <2 x i64> <ae|cg>
17544 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17545 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17546 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17547 // => <2 x i64> <bf|dh>
17548 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17549 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17551 // Shuffle it back into the right order.
17552 SDValue Highs, Lows;
17553 if (VT == MVT::v8i32) {
17554 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17555 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17556 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17557 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17559 const int HighMask[] = {1, 5, 3, 7};
17560 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17561 const int LowMask[] = {0, 4, 2, 6};
17562 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17565 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17566 // unsigned multiply.
17567 if (IsSigned && !Subtarget->hasSSE41()) {
17569 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17570 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17571 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17572 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17573 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17575 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17576 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17579 // The first result of MUL_LOHI is actually the low value, followed by the
17581 SDValue Ops[] = {Lows, Highs};
17582 return DAG.getMergeValues(Ops, dl);
17585 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17586 const X86Subtarget *Subtarget) {
17587 MVT VT = Op.getSimpleValueType();
17589 SDValue R = Op.getOperand(0);
17590 SDValue Amt = Op.getOperand(1);
17592 // Optimize shl/srl/sra with constant shift amount.
17593 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17594 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17595 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17597 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17598 (Subtarget->hasInt256() &&
17599 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17600 (Subtarget->hasAVX512() &&
17601 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17602 if (Op.getOpcode() == ISD::SHL)
17603 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17605 if (Op.getOpcode() == ISD::SRL)
17606 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17608 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17609 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17613 if (VT == MVT::v16i8) {
17614 if (Op.getOpcode() == ISD::SHL) {
17615 // Make a large shift.
17616 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17617 MVT::v8i16, R, ShiftAmt,
17619 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17620 // Zero out the rightmost bits.
17621 SmallVector<SDValue, 16> V(16,
17622 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17624 return DAG.getNode(ISD::AND, dl, VT, SHL,
17625 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17627 if (Op.getOpcode() == ISD::SRL) {
17628 // Make a large shift.
17629 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17630 MVT::v8i16, R, ShiftAmt,
17632 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17633 // Zero out the leftmost bits.
17634 SmallVector<SDValue, 16> V(16,
17635 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17637 return DAG.getNode(ISD::AND, dl, VT, SRL,
17638 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17640 if (Op.getOpcode() == ISD::SRA) {
17641 if (ShiftAmt == 7) {
17642 // R s>> 7 === R s< 0
17643 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17644 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17647 // R s>> a === ((R u>> a) ^ m) - m
17648 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17649 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17651 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17652 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17653 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17656 llvm_unreachable("Unknown shift opcode.");
17659 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17660 if (Op.getOpcode() == ISD::SHL) {
17661 // Make a large shift.
17662 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17663 MVT::v16i16, R, ShiftAmt,
17665 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17666 // Zero out the rightmost bits.
17667 SmallVector<SDValue, 32> V(32,
17668 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17670 return DAG.getNode(ISD::AND, dl, VT, SHL,
17671 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17673 if (Op.getOpcode() == ISD::SRL) {
17674 // Make a large shift.
17675 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17676 MVT::v16i16, R, ShiftAmt,
17678 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17679 // Zero out the leftmost bits.
17680 SmallVector<SDValue, 32> V(32,
17681 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17683 return DAG.getNode(ISD::AND, dl, VT, SRL,
17684 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17686 if (Op.getOpcode() == ISD::SRA) {
17687 if (ShiftAmt == 7) {
17688 // R s>> 7 === R s< 0
17689 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17690 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17693 // R s>> a === ((R u>> a) ^ m) - m
17694 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17695 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17697 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17698 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17699 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17702 llvm_unreachable("Unknown shift opcode.");
17707 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17708 if (!Subtarget->is64Bit() &&
17709 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17710 Amt.getOpcode() == ISD::BITCAST &&
17711 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17712 Amt = Amt.getOperand(0);
17713 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17714 VT.getVectorNumElements();
17715 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17716 uint64_t ShiftAmt = 0;
17717 for (unsigned i = 0; i != Ratio; ++i) {
17718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17722 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17724 // Check remaining shift amounts.
17725 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17726 uint64_t ShAmt = 0;
17727 for (unsigned j = 0; j != Ratio; ++j) {
17728 ConstantSDNode *C =
17729 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17733 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17735 if (ShAmt != ShiftAmt)
17738 switch (Op.getOpcode()) {
17740 llvm_unreachable("Unknown shift opcode!");
17742 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17745 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17748 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17756 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17757 const X86Subtarget* Subtarget) {
17758 MVT VT = Op.getSimpleValueType();
17760 SDValue R = Op.getOperand(0);
17761 SDValue Amt = Op.getOperand(1);
17763 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17764 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17765 (Subtarget->hasInt256() &&
17766 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17767 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17768 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17770 EVT EltVT = VT.getVectorElementType();
17772 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17773 unsigned NumElts = VT.getVectorNumElements();
17775 for (i = 0; i != NumElts; ++i) {
17776 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17780 for (j = i; j != NumElts; ++j) {
17781 SDValue Arg = Amt.getOperand(j);
17782 if (Arg.getOpcode() == ISD::UNDEF) continue;
17783 if (Arg != Amt.getOperand(i))
17786 if (i != NumElts && j == NumElts)
17787 BaseShAmt = Amt.getOperand(i);
17789 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17790 Amt = Amt.getOperand(0);
17791 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17792 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17793 SDValue InVec = Amt.getOperand(0);
17794 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17795 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17797 for (; i != NumElts; ++i) {
17798 SDValue Arg = InVec.getOperand(i);
17799 if (Arg.getOpcode() == ISD::UNDEF) continue;
17803 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17804 if (ConstantSDNode *C =
17805 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17806 unsigned SplatIdx =
17807 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17808 if (C->getZExtValue() == SplatIdx)
17809 BaseShAmt = InVec.getOperand(1);
17812 if (!BaseShAmt.getNode())
17813 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17814 DAG.getIntPtrConstant(0));
17818 if (BaseShAmt.getNode()) {
17819 if (EltVT.bitsGT(MVT::i32))
17820 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17821 else if (EltVT.bitsLT(MVT::i32))
17822 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17824 switch (Op.getOpcode()) {
17826 llvm_unreachable("Unknown shift opcode!");
17828 switch (VT.SimpleTy) {
17829 default: return SDValue();
17838 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17841 switch (VT.SimpleTy) {
17842 default: return SDValue();
17849 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17852 switch (VT.SimpleTy) {
17853 default: return SDValue();
17862 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17868 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17869 if (!Subtarget->is64Bit() &&
17870 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17871 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17872 Amt.getOpcode() == ISD::BITCAST &&
17873 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17874 Amt = Amt.getOperand(0);
17875 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17876 VT.getVectorNumElements();
17877 std::vector<SDValue> Vals(Ratio);
17878 for (unsigned i = 0; i != Ratio; ++i)
17879 Vals[i] = Amt.getOperand(i);
17880 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17881 for (unsigned j = 0; j != Ratio; ++j)
17882 if (Vals[j] != Amt.getOperand(i + j))
17885 switch (Op.getOpcode()) {
17887 llvm_unreachable("Unknown shift opcode!");
17889 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17891 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17893 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17900 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17901 SelectionDAG &DAG) {
17902 MVT VT = Op.getSimpleValueType();
17904 SDValue R = Op.getOperand(0);
17905 SDValue Amt = Op.getOperand(1);
17908 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17909 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17911 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17915 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17919 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17921 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17922 if (Subtarget->hasInt256()) {
17923 if (Op.getOpcode() == ISD::SRL &&
17924 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17925 VT == MVT::v4i64 || VT == MVT::v8i32))
17927 if (Op.getOpcode() == ISD::SHL &&
17928 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17929 VT == MVT::v4i64 || VT == MVT::v8i32))
17931 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17935 // If possible, lower this packed shift into a vector multiply instead of
17936 // expanding it into a sequence of scalar shifts.
17937 // Do this only if the vector shift count is a constant build_vector.
17938 if (Op.getOpcode() == ISD::SHL &&
17939 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17940 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17941 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17942 SmallVector<SDValue, 8> Elts;
17943 EVT SVT = VT.getScalarType();
17944 unsigned SVTBits = SVT.getSizeInBits();
17945 const APInt &One = APInt(SVTBits, 1);
17946 unsigned NumElems = VT.getVectorNumElements();
17948 for (unsigned i=0; i !=NumElems; ++i) {
17949 SDValue Op = Amt->getOperand(i);
17950 if (Op->getOpcode() == ISD::UNDEF) {
17951 Elts.push_back(Op);
17955 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17956 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17957 uint64_t ShAmt = C.getZExtValue();
17958 if (ShAmt >= SVTBits) {
17959 Elts.push_back(DAG.getUNDEF(SVT));
17962 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17964 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17965 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17968 // Lower SHL with variable shift amount.
17969 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17970 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17972 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17973 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17974 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17975 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17978 // If possible, lower this shift as a sequence of two shifts by
17979 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17981 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17983 // Could be rewritten as:
17984 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17986 // The advantage is that the two shifts from the example would be
17987 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17988 // the vector shift into four scalar shifts plus four pairs of vector
17990 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17991 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17992 unsigned TargetOpcode = X86ISD::MOVSS;
17993 bool CanBeSimplified;
17994 // The splat value for the first packed shift (the 'X' from the example).
17995 SDValue Amt1 = Amt->getOperand(0);
17996 // The splat value for the second packed shift (the 'Y' from the example).
17997 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17998 Amt->getOperand(2);
18000 // See if it is possible to replace this node with a sequence of
18001 // two shifts followed by a MOVSS/MOVSD
18002 if (VT == MVT::v4i32) {
18003 // Check if it is legal to use a MOVSS.
18004 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18005 Amt2 == Amt->getOperand(3);
18006 if (!CanBeSimplified) {
18007 // Otherwise, check if we can still simplify this node using a MOVSD.
18008 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18009 Amt->getOperand(2) == Amt->getOperand(3);
18010 TargetOpcode = X86ISD::MOVSD;
18011 Amt2 = Amt->getOperand(2);
18014 // Do similar checks for the case where the machine value type
18016 CanBeSimplified = Amt1 == Amt->getOperand(1);
18017 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18018 CanBeSimplified = Amt2 == Amt->getOperand(i);
18020 if (!CanBeSimplified) {
18021 TargetOpcode = X86ISD::MOVSD;
18022 CanBeSimplified = true;
18023 Amt2 = Amt->getOperand(4);
18024 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18025 CanBeSimplified = Amt1 == Amt->getOperand(i);
18026 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18027 CanBeSimplified = Amt2 == Amt->getOperand(j);
18031 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18032 isa<ConstantSDNode>(Amt2)) {
18033 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18034 EVT CastVT = MVT::v4i32;
18036 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18037 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18039 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18040 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18041 if (TargetOpcode == X86ISD::MOVSD)
18042 CastVT = MVT::v2i64;
18043 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18044 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18045 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18047 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18051 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18052 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18055 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18056 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18058 // Turn 'a' into a mask suitable for VSELECT
18059 SDValue VSelM = DAG.getConstant(0x80, VT);
18060 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18061 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18063 SDValue CM1 = DAG.getConstant(0x0f, VT);
18064 SDValue CM2 = DAG.getConstant(0x3f, VT);
18066 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18067 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18068 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18069 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18070 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18073 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18074 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18075 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18077 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18078 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18079 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18080 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18081 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18084 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18085 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18086 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18088 // return VSELECT(r, r+r, a);
18089 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18090 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18094 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18095 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18096 // solution better.
18097 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18098 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18100 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18101 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18102 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18103 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18104 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18107 // Decompose 256-bit shifts into smaller 128-bit shifts.
18108 if (VT.is256BitVector()) {
18109 unsigned NumElems = VT.getVectorNumElements();
18110 MVT EltVT = VT.getVectorElementType();
18111 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18113 // Extract the two vectors
18114 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18115 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18117 // Recreate the shift amount vectors
18118 SDValue Amt1, Amt2;
18119 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18120 // Constant shift amount
18121 SmallVector<SDValue, 4> Amt1Csts;
18122 SmallVector<SDValue, 4> Amt2Csts;
18123 for (unsigned i = 0; i != NumElems/2; ++i)
18124 Amt1Csts.push_back(Amt->getOperand(i));
18125 for (unsigned i = NumElems/2; i != NumElems; ++i)
18126 Amt2Csts.push_back(Amt->getOperand(i));
18128 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18129 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18131 // Variable shift amount
18132 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18133 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18136 // Issue new vector shifts for the smaller types
18137 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18138 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18140 // Concatenate the result back
18141 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18147 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18148 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18149 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18150 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18151 // has only one use.
18152 SDNode *N = Op.getNode();
18153 SDValue LHS = N->getOperand(0);
18154 SDValue RHS = N->getOperand(1);
18155 unsigned BaseOp = 0;
18158 switch (Op.getOpcode()) {
18159 default: llvm_unreachable("Unknown ovf instruction!");
18161 // A subtract of one will be selected as a INC. Note that INC doesn't
18162 // set CF, so we can't do this for UADDO.
18163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18165 BaseOp = X86ISD::INC;
18166 Cond = X86::COND_O;
18169 BaseOp = X86ISD::ADD;
18170 Cond = X86::COND_O;
18173 BaseOp = X86ISD::ADD;
18174 Cond = X86::COND_B;
18177 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18178 // set CF, so we can't do this for USUBO.
18179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18181 BaseOp = X86ISD::DEC;
18182 Cond = X86::COND_O;
18185 BaseOp = X86ISD::SUB;
18186 Cond = X86::COND_O;
18189 BaseOp = X86ISD::SUB;
18190 Cond = X86::COND_B;
18193 BaseOp = X86ISD::SMUL;
18194 Cond = X86::COND_O;
18196 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18197 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18199 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18202 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18203 DAG.getConstant(X86::COND_O, MVT::i32),
18204 SDValue(Sum.getNode(), 2));
18206 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18210 // Also sets EFLAGS.
18211 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18212 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18215 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18216 DAG.getConstant(Cond, MVT::i32),
18217 SDValue(Sum.getNode(), 1));
18219 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18222 // Sign extension of the low part of vector elements. This may be used either
18223 // when sign extend instructions are not available or if the vector element
18224 // sizes already match the sign-extended size. If the vector elements are in
18225 // their pre-extended size and sign extend instructions are available, that will
18226 // be handled by LowerSIGN_EXTEND.
18227 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18228 SelectionDAG &DAG) const {
18230 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18231 MVT VT = Op.getSimpleValueType();
18233 if (!Subtarget->hasSSE2() || !VT.isVector())
18236 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18237 ExtraVT.getScalarType().getSizeInBits();
18239 switch (VT.SimpleTy) {
18240 default: return SDValue();
18243 if (!Subtarget->hasFp256())
18245 if (!Subtarget->hasInt256()) {
18246 // needs to be split
18247 unsigned NumElems = VT.getVectorNumElements();
18249 // Extract the LHS vectors
18250 SDValue LHS = Op.getOperand(0);
18251 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18252 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18254 MVT EltVT = VT.getVectorElementType();
18255 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18257 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18258 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18259 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18261 SDValue Extra = DAG.getValueType(ExtraVT);
18263 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18264 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18266 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18271 SDValue Op0 = Op.getOperand(0);
18273 // This is a sign extension of some low part of vector elements without
18274 // changing the size of the vector elements themselves:
18275 // Shift-Left + Shift-Right-Algebraic.
18276 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18278 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18284 /// Returns true if the operand type is exactly twice the native width, and
18285 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18286 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18287 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18288 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18289 const X86Subtarget &Subtarget =
18290 getTargetMachine().getSubtarget<X86Subtarget>();
18291 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18294 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18295 else if (OpWidth == 128)
18296 return Subtarget.hasCmpxchg16b();
18301 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18302 return needsCmpXchgNb(SI->getValueOperand()->getType());
18305 // Note: this turns large loads into lock cmpxchg8b/16b.
18306 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18307 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18308 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18309 return needsCmpXchgNb(PTy->getElementType());
18312 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18313 const X86Subtarget &Subtarget =
18314 getTargetMachine().getSubtarget<X86Subtarget>();
18315 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18316 const Type *MemType = AI->getType();
18318 // If the operand is too big, we must see if cmpxchg8/16b is available
18319 // and default to library calls otherwise.
18320 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18321 return needsCmpXchgNb(MemType);
18323 AtomicRMWInst::BinOp Op = AI->getOperation();
18326 llvm_unreachable("Unknown atomic operation");
18327 case AtomicRMWInst::Xchg:
18328 case AtomicRMWInst::Add:
18329 case AtomicRMWInst::Sub:
18330 // It's better to use xadd, xsub or xchg for these in all cases.
18332 case AtomicRMWInst::Or:
18333 case AtomicRMWInst::And:
18334 case AtomicRMWInst::Xor:
18335 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18336 // prefix to a normal instruction for these operations.
18337 return !AI->use_empty();
18338 case AtomicRMWInst::Nand:
18339 case AtomicRMWInst::Max:
18340 case AtomicRMWInst::Min:
18341 case AtomicRMWInst::UMax:
18342 case AtomicRMWInst::UMin:
18343 // These always require a non-trivial set of data operations on x86. We must
18344 // use a cmpxchg loop.
18349 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18350 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18351 // no-sse2). There isn't any reason to disable it if the target processor
18353 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18357 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18358 const X86Subtarget &Subtarget =
18359 getTargetMachine().getSubtarget<X86Subtarget>();
18360 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18361 const Type *MemType = AI->getType();
18362 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18363 // there is no benefit in turning such RMWs into loads, and it is actually
18364 // harmful as it introduces a mfence.
18365 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18368 auto Builder = IRBuilder<>(AI);
18369 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18370 auto SynchScope = AI->getSynchScope();
18371 // We must restrict the ordering to avoid generating loads with Release or
18372 // ReleaseAcquire orderings.
18373 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18374 auto Ptr = AI->getPointerOperand();
18376 // Before the load we need a fence. Here is an example lifted from
18377 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18380 // x.store(1, relaxed);
18381 // r1 = y.fetch_add(0, release);
18383 // y.fetch_add(42, acquire);
18384 // r2 = x.load(relaxed);
18385 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18386 // lowered to just a load without a fence. A mfence flushes the store buffer,
18387 // making the optimization clearly correct.
18388 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18389 // otherwise, we might be able to be more agressive on relaxed idempotent
18390 // rmw. In practice, they do not look useful, so we don't try to be
18391 // especially clever.
18392 if (SynchScope == SingleThread) {
18393 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18394 // the IR level, so we must wrap it in an intrinsic.
18396 } else if (hasMFENCE(Subtarget)) {
18397 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18398 Intrinsic::x86_sse2_mfence);
18399 Builder.CreateCall(MFence);
18401 // FIXME: it might make sense to use a locked operation here but on a
18402 // different cache-line to prevent cache-line bouncing. In practice it
18403 // is probably a small win, and x86 processors without mfence are rare
18404 // enough that we do not bother.
18408 // Finally we can emit the atomic load.
18409 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18410 AI->getType()->getPrimitiveSizeInBits());
18411 Loaded->setAtomic(Order, SynchScope);
18412 AI->replaceAllUsesWith(Loaded);
18413 AI->eraseFromParent();
18417 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18418 SelectionDAG &DAG) {
18420 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18421 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18422 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18423 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18425 // The only fence that needs an instruction is a sequentially-consistent
18426 // cross-thread fence.
18427 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18428 if (hasMFENCE(*Subtarget))
18429 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18431 SDValue Chain = Op.getOperand(0);
18432 SDValue Zero = DAG.getConstant(0, MVT::i32);
18434 DAG.getRegister(X86::ESP, MVT::i32), // Base
18435 DAG.getTargetConstant(1, MVT::i8), // Scale
18436 DAG.getRegister(0, MVT::i32), // Index
18437 DAG.getTargetConstant(0, MVT::i32), // Disp
18438 DAG.getRegister(0, MVT::i32), // Segment.
18442 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18443 return SDValue(Res, 0);
18446 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18447 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18450 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18451 SelectionDAG &DAG) {
18452 MVT T = Op.getSimpleValueType();
18456 switch(T.SimpleTy) {
18457 default: llvm_unreachable("Invalid value type!");
18458 case MVT::i8: Reg = X86::AL; size = 1; break;
18459 case MVT::i16: Reg = X86::AX; size = 2; break;
18460 case MVT::i32: Reg = X86::EAX; size = 4; break;
18462 assert(Subtarget->is64Bit() && "Node not type legal!");
18463 Reg = X86::RAX; size = 8;
18466 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18467 Op.getOperand(2), SDValue());
18468 SDValue Ops[] = { cpIn.getValue(0),
18471 DAG.getTargetConstant(size, MVT::i8),
18472 cpIn.getValue(1) };
18473 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18474 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18475 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18479 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18480 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18481 MVT::i32, cpOut.getValue(2));
18482 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18483 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18485 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18486 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18487 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18491 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18492 SelectionDAG &DAG) {
18493 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18494 MVT DstVT = Op.getSimpleValueType();
18496 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18497 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18498 if (DstVT != MVT::f64)
18499 // This conversion needs to be expanded.
18502 SDValue InVec = Op->getOperand(0);
18504 unsigned NumElts = SrcVT.getVectorNumElements();
18505 EVT SVT = SrcVT.getVectorElementType();
18507 // Widen the vector in input in the case of MVT::v2i32.
18508 // Example: from MVT::v2i32 to MVT::v4i32.
18509 SmallVector<SDValue, 16> Elts;
18510 for (unsigned i = 0, e = NumElts; i != e; ++i)
18511 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18512 DAG.getIntPtrConstant(i)));
18514 // Explicitly mark the extra elements as Undef.
18515 SDValue Undef = DAG.getUNDEF(SVT);
18516 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18517 Elts.push_back(Undef);
18519 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18520 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18521 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18522 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18523 DAG.getIntPtrConstant(0));
18526 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18527 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18528 assert((DstVT == MVT::i64 ||
18529 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18530 "Unexpected custom BITCAST");
18531 // i64 <=> MMX conversions are Legal.
18532 if (SrcVT==MVT::i64 && DstVT.isVector())
18534 if (DstVT==MVT::i64 && SrcVT.isVector())
18536 // MMX <=> MMX conversions are Legal.
18537 if (SrcVT.isVector() && DstVT.isVector())
18539 // All other conversions need to be expanded.
18543 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18544 SDNode *Node = Op.getNode();
18546 EVT T = Node->getValueType(0);
18547 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18548 DAG.getConstant(0, T), Node->getOperand(2));
18549 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18550 cast<AtomicSDNode>(Node)->getMemoryVT(),
18551 Node->getOperand(0),
18552 Node->getOperand(1), negOp,
18553 cast<AtomicSDNode>(Node)->getMemOperand(),
18554 cast<AtomicSDNode>(Node)->getOrdering(),
18555 cast<AtomicSDNode>(Node)->getSynchScope());
18558 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18559 SDNode *Node = Op.getNode();
18561 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18563 // Convert seq_cst store -> xchg
18564 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18565 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18566 // (The only way to get a 16-byte store is cmpxchg16b)
18567 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18568 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18569 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18570 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18571 cast<AtomicSDNode>(Node)->getMemoryVT(),
18572 Node->getOperand(0),
18573 Node->getOperand(1), Node->getOperand(2),
18574 cast<AtomicSDNode>(Node)->getMemOperand(),
18575 cast<AtomicSDNode>(Node)->getOrdering(),
18576 cast<AtomicSDNode>(Node)->getSynchScope());
18577 return Swap.getValue(1);
18579 // Other atomic stores have a simple pattern.
18583 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18584 EVT VT = Op.getNode()->getSimpleValueType(0);
18586 // Let legalize expand this if it isn't a legal type yet.
18587 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18590 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18593 bool ExtraOp = false;
18594 switch (Op.getOpcode()) {
18595 default: llvm_unreachable("Invalid code");
18596 case ISD::ADDC: Opc = X86ISD::ADD; break;
18597 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18598 case ISD::SUBC: Opc = X86ISD::SUB; break;
18599 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18603 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18605 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18606 Op.getOperand(1), Op.getOperand(2));
18609 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18610 SelectionDAG &DAG) {
18611 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18613 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18614 // which returns the values as { float, float } (in XMM0) or
18615 // { double, double } (which is returned in XMM0, XMM1).
18617 SDValue Arg = Op.getOperand(0);
18618 EVT ArgVT = Arg.getValueType();
18619 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18621 TargetLowering::ArgListTy Args;
18622 TargetLowering::ArgListEntry Entry;
18626 Entry.isSExt = false;
18627 Entry.isZExt = false;
18628 Args.push_back(Entry);
18630 bool isF64 = ArgVT == MVT::f64;
18631 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18632 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18633 // the results are returned via SRet in memory.
18634 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18635 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18636 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18638 Type *RetTy = isF64
18639 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18640 : (Type*)VectorType::get(ArgTy, 4);
18642 TargetLowering::CallLoweringInfo CLI(DAG);
18643 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18644 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18646 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18649 // Returned in xmm0 and xmm1.
18650 return CallResult.first;
18652 // Returned in bits 0:31 and 32:64 xmm0.
18653 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18654 CallResult.first, DAG.getIntPtrConstant(0));
18655 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18656 CallResult.first, DAG.getIntPtrConstant(1));
18657 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18658 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18661 /// LowerOperation - Provide custom lowering hooks for some operations.
18663 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18664 switch (Op.getOpcode()) {
18665 default: llvm_unreachable("Should not custom lower this!");
18666 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18667 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18668 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18669 return LowerCMP_SWAP(Op, Subtarget, DAG);
18670 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18671 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18672 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18673 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18674 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18675 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18676 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18677 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18678 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18679 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18680 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18681 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18682 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18683 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18684 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18685 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18686 case ISD::SHL_PARTS:
18687 case ISD::SRA_PARTS:
18688 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18689 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18690 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18691 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18692 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18693 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18694 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18695 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18696 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18697 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18698 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18700 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18701 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18702 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18703 case ISD::SETCC: return LowerSETCC(Op, DAG);
18704 case ISD::SELECT: return LowerSELECT(Op, DAG);
18705 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18706 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18707 case ISD::VASTART: return LowerVASTART(Op, DAG);
18708 case ISD::VAARG: return LowerVAARG(Op, DAG);
18709 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18710 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18711 case ISD::INTRINSIC_VOID:
18712 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18713 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18714 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18715 case ISD::FRAME_TO_ARGS_OFFSET:
18716 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18717 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18718 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18719 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18720 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18721 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18722 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18723 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18724 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18725 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18726 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18727 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18728 case ISD::UMUL_LOHI:
18729 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18732 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18738 case ISD::UMULO: return LowerXALUO(Op, DAG);
18739 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18740 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18744 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18745 case ISD::ADD: return LowerADD(Op, DAG);
18746 case ISD::SUB: return LowerSUB(Op, DAG);
18747 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18751 /// ReplaceNodeResults - Replace a node with an illegal result type
18752 /// with a new node built out of custom code.
18753 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18754 SmallVectorImpl<SDValue>&Results,
18755 SelectionDAG &DAG) const {
18757 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18758 switch (N->getOpcode()) {
18760 llvm_unreachable("Do not know how to custom type legalize this operation!");
18761 case ISD::SIGN_EXTEND_INREG:
18766 // We don't want to expand or promote these.
18773 case ISD::UDIVREM: {
18774 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18775 Results.push_back(V);
18778 case ISD::FP_TO_SINT:
18779 case ISD::FP_TO_UINT: {
18780 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18782 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18785 std::pair<SDValue,SDValue> Vals =
18786 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18787 SDValue FIST = Vals.first, StackSlot = Vals.second;
18788 if (FIST.getNode()) {
18789 EVT VT = N->getValueType(0);
18790 // Return a load from the stack slot.
18791 if (StackSlot.getNode())
18792 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18793 MachinePointerInfo(),
18794 false, false, false, 0));
18796 Results.push_back(FIST);
18800 case ISD::UINT_TO_FP: {
18801 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18802 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18803 N->getValueType(0) != MVT::v2f32)
18805 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18807 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18809 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18810 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18811 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18812 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18813 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18814 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18817 case ISD::FP_ROUND: {
18818 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18820 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18821 Results.push_back(V);
18824 case ISD::INTRINSIC_W_CHAIN: {
18825 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18827 default : llvm_unreachable("Do not know how to custom type "
18828 "legalize this intrinsic operation!");
18829 case Intrinsic::x86_rdtsc:
18830 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18832 case Intrinsic::x86_rdtscp:
18833 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18835 case Intrinsic::x86_rdpmc:
18836 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18839 case ISD::READCYCLECOUNTER: {
18840 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18843 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18844 EVT T = N->getValueType(0);
18845 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18846 bool Regs64bit = T == MVT::i128;
18847 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18848 SDValue cpInL, cpInH;
18849 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18850 DAG.getConstant(0, HalfT));
18851 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18852 DAG.getConstant(1, HalfT));
18853 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18854 Regs64bit ? X86::RAX : X86::EAX,
18856 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18857 Regs64bit ? X86::RDX : X86::EDX,
18858 cpInH, cpInL.getValue(1));
18859 SDValue swapInL, swapInH;
18860 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18861 DAG.getConstant(0, HalfT));
18862 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18863 DAG.getConstant(1, HalfT));
18864 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18865 Regs64bit ? X86::RBX : X86::EBX,
18866 swapInL, cpInH.getValue(1));
18867 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18868 Regs64bit ? X86::RCX : X86::ECX,
18869 swapInH, swapInL.getValue(1));
18870 SDValue Ops[] = { swapInH.getValue(0),
18872 swapInH.getValue(1) };
18873 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18874 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18875 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18876 X86ISD::LCMPXCHG8_DAG;
18877 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18878 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18879 Regs64bit ? X86::RAX : X86::EAX,
18880 HalfT, Result.getValue(1));
18881 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18882 Regs64bit ? X86::RDX : X86::EDX,
18883 HalfT, cpOutL.getValue(2));
18884 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18886 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18887 MVT::i32, cpOutH.getValue(2));
18889 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18890 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18891 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18893 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18894 Results.push_back(Success);
18895 Results.push_back(EFLAGS.getValue(1));
18898 case ISD::ATOMIC_SWAP:
18899 case ISD::ATOMIC_LOAD_ADD:
18900 case ISD::ATOMIC_LOAD_SUB:
18901 case ISD::ATOMIC_LOAD_AND:
18902 case ISD::ATOMIC_LOAD_OR:
18903 case ISD::ATOMIC_LOAD_XOR:
18904 case ISD::ATOMIC_LOAD_NAND:
18905 case ISD::ATOMIC_LOAD_MIN:
18906 case ISD::ATOMIC_LOAD_MAX:
18907 case ISD::ATOMIC_LOAD_UMIN:
18908 case ISD::ATOMIC_LOAD_UMAX:
18909 case ISD::ATOMIC_LOAD: {
18910 // Delegate to generic TypeLegalization. Situations we can really handle
18911 // should have already been dealt with by AtomicExpandPass.cpp.
18914 case ISD::BITCAST: {
18915 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18916 EVT DstVT = N->getValueType(0);
18917 EVT SrcVT = N->getOperand(0)->getValueType(0);
18919 if (SrcVT != MVT::f64 ||
18920 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18923 unsigned NumElts = DstVT.getVectorNumElements();
18924 EVT SVT = DstVT.getVectorElementType();
18925 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18926 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18927 MVT::v2f64, N->getOperand(0));
18928 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18930 if (ExperimentalVectorWideningLegalization) {
18931 // If we are legalizing vectors by widening, we already have the desired
18932 // legal vector type, just return it.
18933 Results.push_back(ToVecInt);
18937 SmallVector<SDValue, 8> Elts;
18938 for (unsigned i = 0, e = NumElts; i != e; ++i)
18939 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18940 ToVecInt, DAG.getIntPtrConstant(i)));
18942 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18947 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18949 default: return nullptr;
18950 case X86ISD::BSF: return "X86ISD::BSF";
18951 case X86ISD::BSR: return "X86ISD::BSR";
18952 case X86ISD::SHLD: return "X86ISD::SHLD";
18953 case X86ISD::SHRD: return "X86ISD::SHRD";
18954 case X86ISD::FAND: return "X86ISD::FAND";
18955 case X86ISD::FANDN: return "X86ISD::FANDN";
18956 case X86ISD::FOR: return "X86ISD::FOR";
18957 case X86ISD::FXOR: return "X86ISD::FXOR";
18958 case X86ISD::FSRL: return "X86ISD::FSRL";
18959 case X86ISD::FILD: return "X86ISD::FILD";
18960 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18961 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18962 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18963 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18964 case X86ISD::FLD: return "X86ISD::FLD";
18965 case X86ISD::FST: return "X86ISD::FST";
18966 case X86ISD::CALL: return "X86ISD::CALL";
18967 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18968 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18969 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18970 case X86ISD::BT: return "X86ISD::BT";
18971 case X86ISD::CMP: return "X86ISD::CMP";
18972 case X86ISD::COMI: return "X86ISD::COMI";
18973 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18974 case X86ISD::CMPM: return "X86ISD::CMPM";
18975 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18976 case X86ISD::SETCC: return "X86ISD::SETCC";
18977 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18978 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18979 case X86ISD::CMOV: return "X86ISD::CMOV";
18980 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18981 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18982 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18983 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18984 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18985 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18986 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18987 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18988 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18989 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18990 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18991 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18992 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18993 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18994 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18995 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18996 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18997 case X86ISD::HADD: return "X86ISD::HADD";
18998 case X86ISD::HSUB: return "X86ISD::HSUB";
18999 case X86ISD::FHADD: return "X86ISD::FHADD";
19000 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19001 case X86ISD::UMAX: return "X86ISD::UMAX";
19002 case X86ISD::UMIN: return "X86ISD::UMIN";
19003 case X86ISD::SMAX: return "X86ISD::SMAX";
19004 case X86ISD::SMIN: return "X86ISD::SMIN";
19005 case X86ISD::FMAX: return "X86ISD::FMAX";
19006 case X86ISD::FMIN: return "X86ISD::FMIN";
19007 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19008 case X86ISD::FMINC: return "X86ISD::FMINC";
19009 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19010 case X86ISD::FRCP: return "X86ISD::FRCP";
19011 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19012 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19013 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19014 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19015 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19016 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19017 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19018 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19019 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19020 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19021 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19022 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19023 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19024 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19025 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19026 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19027 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19028 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19029 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19030 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19031 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19032 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19033 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19034 case X86ISD::VSHL: return "X86ISD::VSHL";
19035 case X86ISD::VSRL: return "X86ISD::VSRL";
19036 case X86ISD::VSRA: return "X86ISD::VSRA";
19037 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19038 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19039 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19040 case X86ISD::CMPP: return "X86ISD::CMPP";
19041 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19042 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19043 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19044 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19045 case X86ISD::ADD: return "X86ISD::ADD";
19046 case X86ISD::SUB: return "X86ISD::SUB";
19047 case X86ISD::ADC: return "X86ISD::ADC";
19048 case X86ISD::SBB: return "X86ISD::SBB";
19049 case X86ISD::SMUL: return "X86ISD::SMUL";
19050 case X86ISD::UMUL: return "X86ISD::UMUL";
19051 case X86ISD::INC: return "X86ISD::INC";
19052 case X86ISD::DEC: return "X86ISD::DEC";
19053 case X86ISD::OR: return "X86ISD::OR";
19054 case X86ISD::XOR: return "X86ISD::XOR";
19055 case X86ISD::AND: return "X86ISD::AND";
19056 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19057 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19058 case X86ISD::PTEST: return "X86ISD::PTEST";
19059 case X86ISD::TESTP: return "X86ISD::TESTP";
19060 case X86ISD::TESTM: return "X86ISD::TESTM";
19061 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19062 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19063 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19064 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19065 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19066 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19067 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19068 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19069 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19070 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19071 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19072 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19073 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19074 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19075 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19076 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19077 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19078 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19079 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19080 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19081 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19082 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19083 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19084 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19085 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19086 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19087 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19088 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19089 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19090 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19091 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19092 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19093 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19094 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19095 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19096 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19097 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19098 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19099 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19100 case X86ISD::SAHF: return "X86ISD::SAHF";
19101 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19102 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19103 case X86ISD::FMADD: return "X86ISD::FMADD";
19104 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19105 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19106 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19107 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19108 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19109 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19110 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19111 case X86ISD::XTEST: return "X86ISD::XTEST";
19115 // isLegalAddressingMode - Return true if the addressing mode represented
19116 // by AM is legal for this target, for a load/store of the specified type.
19117 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19119 // X86 supports extremely general addressing modes.
19120 CodeModel::Model M = getTargetMachine().getCodeModel();
19121 Reloc::Model R = getTargetMachine().getRelocationModel();
19123 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19124 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19129 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19131 // If a reference to this global requires an extra load, we can't fold it.
19132 if (isGlobalStubReference(GVFlags))
19135 // If BaseGV requires a register for the PIC base, we cannot also have a
19136 // BaseReg specified.
19137 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19140 // If lower 4G is not available, then we must use rip-relative addressing.
19141 if ((M != CodeModel::Small || R != Reloc::Static) &&
19142 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19146 switch (AM.Scale) {
19152 // These scales always work.
19157 // These scales are formed with basereg+scalereg. Only accept if there is
19162 default: // Other stuff never works.
19169 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19170 unsigned Bits = Ty->getScalarSizeInBits();
19172 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19173 // particularly cheaper than those without.
19177 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19178 // variable shifts just as cheap as scalar ones.
19179 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19182 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19183 // fully general vector.
19187 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19188 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19190 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19191 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19192 return NumBits1 > NumBits2;
19195 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19196 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19199 if (!isTypeLegal(EVT::getEVT(Ty1)))
19202 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19204 // Assuming the caller doesn't have a zeroext or signext return parameter,
19205 // truncation all the way down to i1 is valid.
19209 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19210 return isInt<32>(Imm);
19213 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19214 // Can also use sub to handle negated immediates.
19215 return isInt<32>(Imm);
19218 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19219 if (!VT1.isInteger() || !VT2.isInteger())
19221 unsigned NumBits1 = VT1.getSizeInBits();
19222 unsigned NumBits2 = VT2.getSizeInBits();
19223 return NumBits1 > NumBits2;
19226 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19227 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19228 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19231 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19232 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19233 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19236 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19237 EVT VT1 = Val.getValueType();
19238 if (isZExtFree(VT1, VT2))
19241 if (Val.getOpcode() != ISD::LOAD)
19244 if (!VT1.isSimple() || !VT1.isInteger() ||
19245 !VT2.isSimple() || !VT2.isInteger())
19248 switch (VT1.getSimpleVT().SimpleTy) {
19253 // X86 has 8, 16, and 32-bit zero-extending loads.
19261 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19262 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19265 VT = VT.getScalarType();
19267 if (!VT.isSimple())
19270 switch (VT.getSimpleVT().SimpleTy) {
19281 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19282 // i16 instructions are longer (0x66 prefix) and potentially slower.
19283 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19286 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19287 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19288 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19289 /// are assumed to be legal.
19291 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19293 if (!VT.isSimple())
19296 MVT SVT = VT.getSimpleVT();
19298 // Very little shuffling can be done for 64-bit vectors right now.
19299 if (VT.getSizeInBits() == 64)
19302 // If this is a single-input shuffle with no 128 bit lane crossings we can
19303 // lower it into pshufb.
19304 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19305 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19306 bool isLegal = true;
19307 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19308 if (M[I] >= (int)SVT.getVectorNumElements() ||
19309 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19318 // FIXME: blends, shifts.
19319 return (SVT.getVectorNumElements() == 2 ||
19320 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19321 isMOVLMask(M, SVT) ||
19322 isMOVHLPSMask(M, SVT) ||
19323 isSHUFPMask(M, SVT) ||
19324 isPSHUFDMask(M, SVT) ||
19325 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19326 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19327 isPALIGNRMask(M, SVT, Subtarget) ||
19328 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19329 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19330 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19331 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19332 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19336 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19338 if (!VT.isSimple())
19341 MVT SVT = VT.getSimpleVT();
19342 unsigned NumElts = SVT.getVectorNumElements();
19343 // FIXME: This collection of masks seems suspect.
19346 if (NumElts == 4 && SVT.is128BitVector()) {
19347 return (isMOVLMask(Mask, SVT) ||
19348 isCommutedMOVLMask(Mask, SVT, true) ||
19349 isSHUFPMask(Mask, SVT) ||
19350 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19355 //===----------------------------------------------------------------------===//
19356 // X86 Scheduler Hooks
19357 //===----------------------------------------------------------------------===//
19359 /// Utility function to emit xbegin specifying the start of an RTM region.
19360 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19361 const TargetInstrInfo *TII) {
19362 DebugLoc DL = MI->getDebugLoc();
19364 const BasicBlock *BB = MBB->getBasicBlock();
19365 MachineFunction::iterator I = MBB;
19368 // For the v = xbegin(), we generate
19379 MachineBasicBlock *thisMBB = MBB;
19380 MachineFunction *MF = MBB->getParent();
19381 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19382 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19383 MF->insert(I, mainMBB);
19384 MF->insert(I, sinkMBB);
19386 // Transfer the remainder of BB and its successor edges to sinkMBB.
19387 sinkMBB->splice(sinkMBB->begin(), MBB,
19388 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19389 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19393 // # fallthrough to mainMBB
19394 // # abortion to sinkMBB
19395 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19396 thisMBB->addSuccessor(mainMBB);
19397 thisMBB->addSuccessor(sinkMBB);
19401 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19402 mainMBB->addSuccessor(sinkMBB);
19405 // EAX is live into the sinkMBB
19406 sinkMBB->addLiveIn(X86::EAX);
19407 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19408 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19411 MI->eraseFromParent();
19415 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19416 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19417 // in the .td file.
19418 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19419 const TargetInstrInfo *TII) {
19421 switch (MI->getOpcode()) {
19422 default: llvm_unreachable("illegal opcode!");
19423 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19424 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19425 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19426 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19427 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19428 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19429 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19430 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19433 DebugLoc dl = MI->getDebugLoc();
19434 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19436 unsigned NumArgs = MI->getNumOperands();
19437 for (unsigned i = 1; i < NumArgs; ++i) {
19438 MachineOperand &Op = MI->getOperand(i);
19439 if (!(Op.isReg() && Op.isImplicit()))
19440 MIB.addOperand(Op);
19442 if (MI->hasOneMemOperand())
19443 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19445 BuildMI(*BB, MI, dl,
19446 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19447 .addReg(X86::XMM0);
19449 MI->eraseFromParent();
19453 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19454 // defs in an instruction pattern
19455 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19456 const TargetInstrInfo *TII) {
19458 switch (MI->getOpcode()) {
19459 default: llvm_unreachable("illegal opcode!");
19460 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19461 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19462 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19463 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19464 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19465 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19466 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19467 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19470 DebugLoc dl = MI->getDebugLoc();
19471 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19473 unsigned NumArgs = MI->getNumOperands(); // remove the results
19474 for (unsigned i = 1; i < NumArgs; ++i) {
19475 MachineOperand &Op = MI->getOperand(i);
19476 if (!(Op.isReg() && Op.isImplicit()))
19477 MIB.addOperand(Op);
19479 if (MI->hasOneMemOperand())
19480 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19482 BuildMI(*BB, MI, dl,
19483 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19486 MI->eraseFromParent();
19490 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19491 const TargetInstrInfo *TII,
19492 const X86Subtarget* Subtarget) {
19493 DebugLoc dl = MI->getDebugLoc();
19495 // Address into RAX/EAX, other two args into ECX, EDX.
19496 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19497 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19498 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19499 for (int i = 0; i < X86::AddrNumOperands; ++i)
19500 MIB.addOperand(MI->getOperand(i));
19502 unsigned ValOps = X86::AddrNumOperands;
19503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19504 .addReg(MI->getOperand(ValOps).getReg());
19505 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19506 .addReg(MI->getOperand(ValOps+1).getReg());
19508 // The instruction doesn't actually take any operands though.
19509 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19511 MI->eraseFromParent(); // The pseudo is gone now.
19515 MachineBasicBlock *
19516 X86TargetLowering::EmitVAARG64WithCustomInserter(
19518 MachineBasicBlock *MBB) const {
19519 // Emit va_arg instruction on X86-64.
19521 // Operands to this pseudo-instruction:
19522 // 0 ) Output : destination address (reg)
19523 // 1-5) Input : va_list address (addr, i64mem)
19524 // 6 ) ArgSize : Size (in bytes) of vararg type
19525 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19526 // 8 ) Align : Alignment of type
19527 // 9 ) EFLAGS (implicit-def)
19529 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19530 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19532 unsigned DestReg = MI->getOperand(0).getReg();
19533 MachineOperand &Base = MI->getOperand(1);
19534 MachineOperand &Scale = MI->getOperand(2);
19535 MachineOperand &Index = MI->getOperand(3);
19536 MachineOperand &Disp = MI->getOperand(4);
19537 MachineOperand &Segment = MI->getOperand(5);
19538 unsigned ArgSize = MI->getOperand(6).getImm();
19539 unsigned ArgMode = MI->getOperand(7).getImm();
19540 unsigned Align = MI->getOperand(8).getImm();
19542 // Memory Reference
19543 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19544 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19545 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19547 // Machine Information
19548 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19549 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19550 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19551 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19552 DebugLoc DL = MI->getDebugLoc();
19554 // struct va_list {
19557 // i64 overflow_area (address)
19558 // i64 reg_save_area (address)
19560 // sizeof(va_list) = 24
19561 // alignment(va_list) = 8
19563 unsigned TotalNumIntRegs = 6;
19564 unsigned TotalNumXMMRegs = 8;
19565 bool UseGPOffset = (ArgMode == 1);
19566 bool UseFPOffset = (ArgMode == 2);
19567 unsigned MaxOffset = TotalNumIntRegs * 8 +
19568 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19570 /* Align ArgSize to a multiple of 8 */
19571 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19572 bool NeedsAlign = (Align > 8);
19574 MachineBasicBlock *thisMBB = MBB;
19575 MachineBasicBlock *overflowMBB;
19576 MachineBasicBlock *offsetMBB;
19577 MachineBasicBlock *endMBB;
19579 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19580 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19581 unsigned OffsetReg = 0;
19583 if (!UseGPOffset && !UseFPOffset) {
19584 // If we only pull from the overflow region, we don't create a branch.
19585 // We don't need to alter control flow.
19586 OffsetDestReg = 0; // unused
19587 OverflowDestReg = DestReg;
19589 offsetMBB = nullptr;
19590 overflowMBB = thisMBB;
19593 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19594 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19595 // If not, pull from overflow_area. (branch to overflowMBB)
19600 // offsetMBB overflowMBB
19605 // Registers for the PHI in endMBB
19606 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19607 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19609 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19610 MachineFunction *MF = MBB->getParent();
19611 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19612 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19613 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19615 MachineFunction::iterator MBBIter = MBB;
19618 // Insert the new basic blocks
19619 MF->insert(MBBIter, offsetMBB);
19620 MF->insert(MBBIter, overflowMBB);
19621 MF->insert(MBBIter, endMBB);
19623 // Transfer the remainder of MBB and its successor edges to endMBB.
19624 endMBB->splice(endMBB->begin(), thisMBB,
19625 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19626 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19628 // Make offsetMBB and overflowMBB successors of thisMBB
19629 thisMBB->addSuccessor(offsetMBB);
19630 thisMBB->addSuccessor(overflowMBB);
19632 // endMBB is a successor of both offsetMBB and overflowMBB
19633 offsetMBB->addSuccessor(endMBB);
19634 overflowMBB->addSuccessor(endMBB);
19636 // Load the offset value into a register
19637 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19638 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19642 .addDisp(Disp, UseFPOffset ? 4 : 0)
19643 .addOperand(Segment)
19644 .setMemRefs(MMOBegin, MMOEnd);
19646 // Check if there is enough room left to pull this argument.
19647 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19649 .addImm(MaxOffset + 8 - ArgSizeA8);
19651 // Branch to "overflowMBB" if offset >= max
19652 // Fall through to "offsetMBB" otherwise
19653 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19654 .addMBB(overflowMBB);
19657 // In offsetMBB, emit code to use the reg_save_area.
19659 assert(OffsetReg != 0);
19661 // Read the reg_save_area address.
19662 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19663 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19668 .addOperand(Segment)
19669 .setMemRefs(MMOBegin, MMOEnd);
19671 // Zero-extend the offset
19672 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19673 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19676 .addImm(X86::sub_32bit);
19678 // Add the offset to the reg_save_area to get the final address.
19679 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19680 .addReg(OffsetReg64)
19681 .addReg(RegSaveReg);
19683 // Compute the offset for the next argument
19684 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19685 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19687 .addImm(UseFPOffset ? 16 : 8);
19689 // Store it back into the va_list.
19690 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19694 .addDisp(Disp, UseFPOffset ? 4 : 0)
19695 .addOperand(Segment)
19696 .addReg(NextOffsetReg)
19697 .setMemRefs(MMOBegin, MMOEnd);
19700 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19705 // Emit code to use overflow area
19708 // Load the overflow_area address into a register.
19709 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19710 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19715 .addOperand(Segment)
19716 .setMemRefs(MMOBegin, MMOEnd);
19718 // If we need to align it, do so. Otherwise, just copy the address
19719 // to OverflowDestReg.
19721 // Align the overflow address
19722 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19723 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19725 // aligned_addr = (addr + (align-1)) & ~(align-1)
19726 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19727 .addReg(OverflowAddrReg)
19730 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19732 .addImm(~(uint64_t)(Align-1));
19734 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19735 .addReg(OverflowAddrReg);
19738 // Compute the next overflow address after this argument.
19739 // (the overflow address should be kept 8-byte aligned)
19740 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19741 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19742 .addReg(OverflowDestReg)
19743 .addImm(ArgSizeA8);
19745 // Store the new overflow address.
19746 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19751 .addOperand(Segment)
19752 .addReg(NextAddrReg)
19753 .setMemRefs(MMOBegin, MMOEnd);
19755 // If we branched, emit the PHI to the front of endMBB.
19757 BuildMI(*endMBB, endMBB->begin(), DL,
19758 TII->get(X86::PHI), DestReg)
19759 .addReg(OffsetDestReg).addMBB(offsetMBB)
19760 .addReg(OverflowDestReg).addMBB(overflowMBB);
19763 // Erase the pseudo instruction
19764 MI->eraseFromParent();
19769 MachineBasicBlock *
19770 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19772 MachineBasicBlock *MBB) const {
19773 // Emit code to save XMM registers to the stack. The ABI says that the
19774 // number of registers to save is given in %al, so it's theoretically
19775 // possible to do an indirect jump trick to avoid saving all of them,
19776 // however this code takes a simpler approach and just executes all
19777 // of the stores if %al is non-zero. It's less code, and it's probably
19778 // easier on the hardware branch predictor, and stores aren't all that
19779 // expensive anyway.
19781 // Create the new basic blocks. One block contains all the XMM stores,
19782 // and one block is the final destination regardless of whether any
19783 // stores were performed.
19784 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19785 MachineFunction *F = MBB->getParent();
19786 MachineFunction::iterator MBBIter = MBB;
19788 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19789 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19790 F->insert(MBBIter, XMMSaveMBB);
19791 F->insert(MBBIter, EndMBB);
19793 // Transfer the remainder of MBB and its successor edges to EndMBB.
19794 EndMBB->splice(EndMBB->begin(), MBB,
19795 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19796 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19798 // The original block will now fall through to the XMM save block.
19799 MBB->addSuccessor(XMMSaveMBB);
19800 // The XMMSaveMBB will fall through to the end block.
19801 XMMSaveMBB->addSuccessor(EndMBB);
19803 // Now add the instructions.
19804 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19805 DebugLoc DL = MI->getDebugLoc();
19807 unsigned CountReg = MI->getOperand(0).getReg();
19808 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19809 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19811 if (!Subtarget->isTargetWin64()) {
19812 // If %al is 0, branch around the XMM save block.
19813 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19814 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19815 MBB->addSuccessor(EndMBB);
19818 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19819 // that was just emitted, but clearly shouldn't be "saved".
19820 assert((MI->getNumOperands() <= 3 ||
19821 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19822 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19823 && "Expected last argument to be EFLAGS");
19824 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19825 // In the XMM save block, save all the XMM argument registers.
19826 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19827 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19828 MachineMemOperand *MMO =
19829 F->getMachineMemOperand(
19830 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19831 MachineMemOperand::MOStore,
19832 /*Size=*/16, /*Align=*/16);
19833 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19834 .addFrameIndex(RegSaveFrameIndex)
19835 .addImm(/*Scale=*/1)
19836 .addReg(/*IndexReg=*/0)
19837 .addImm(/*Disp=*/Offset)
19838 .addReg(/*Segment=*/0)
19839 .addReg(MI->getOperand(i).getReg())
19840 .addMemOperand(MMO);
19843 MI->eraseFromParent(); // The pseudo instruction is gone now.
19848 // The EFLAGS operand of SelectItr might be missing a kill marker
19849 // because there were multiple uses of EFLAGS, and ISel didn't know
19850 // which to mark. Figure out whether SelectItr should have had a
19851 // kill marker, and set it if it should. Returns the correct kill
19853 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19854 MachineBasicBlock* BB,
19855 const TargetRegisterInfo* TRI) {
19856 // Scan forward through BB for a use/def of EFLAGS.
19857 MachineBasicBlock::iterator miI(std::next(SelectItr));
19858 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19859 const MachineInstr& mi = *miI;
19860 if (mi.readsRegister(X86::EFLAGS))
19862 if (mi.definesRegister(X86::EFLAGS))
19863 break; // Should have kill-flag - update below.
19866 // If we hit the end of the block, check whether EFLAGS is live into a
19868 if (miI == BB->end()) {
19869 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19870 sEnd = BB->succ_end();
19871 sItr != sEnd; ++sItr) {
19872 MachineBasicBlock* succ = *sItr;
19873 if (succ->isLiveIn(X86::EFLAGS))
19878 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19879 // out. SelectMI should have a kill flag on EFLAGS.
19880 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19884 MachineBasicBlock *
19885 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19886 MachineBasicBlock *BB) const {
19887 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19888 DebugLoc DL = MI->getDebugLoc();
19890 // To "insert" a SELECT_CC instruction, we actually have to insert the
19891 // diamond control-flow pattern. The incoming instruction knows the
19892 // destination vreg to set, the condition code register to branch on, the
19893 // true/false values to select between, and a branch opcode to use.
19894 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19895 MachineFunction::iterator It = BB;
19901 // cmpTY ccX, r1, r2
19903 // fallthrough --> copy0MBB
19904 MachineBasicBlock *thisMBB = BB;
19905 MachineFunction *F = BB->getParent();
19906 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19907 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19908 F->insert(It, copy0MBB);
19909 F->insert(It, sinkMBB);
19911 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19912 // live into the sink and copy blocks.
19913 const TargetRegisterInfo *TRI =
19914 BB->getParent()->getSubtarget().getRegisterInfo();
19915 if (!MI->killsRegister(X86::EFLAGS) &&
19916 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19917 copy0MBB->addLiveIn(X86::EFLAGS);
19918 sinkMBB->addLiveIn(X86::EFLAGS);
19921 // Transfer the remainder of BB and its successor edges to sinkMBB.
19922 sinkMBB->splice(sinkMBB->begin(), BB,
19923 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19924 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19926 // Add the true and fallthrough blocks as its successors.
19927 BB->addSuccessor(copy0MBB);
19928 BB->addSuccessor(sinkMBB);
19930 // Create the conditional branch instruction.
19932 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19933 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19936 // %FalseValue = ...
19937 // # fallthrough to sinkMBB
19938 copy0MBB->addSuccessor(sinkMBB);
19941 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19943 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19944 TII->get(X86::PHI), MI->getOperand(0).getReg())
19945 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19946 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19948 MI->eraseFromParent(); // The pseudo instruction is gone now.
19952 MachineBasicBlock *
19953 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19954 MachineBasicBlock *BB) const {
19955 MachineFunction *MF = BB->getParent();
19956 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19957 DebugLoc DL = MI->getDebugLoc();
19958 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19960 assert(MF->shouldSplitStack());
19962 const bool Is64Bit = Subtarget->is64Bit();
19963 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19965 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19966 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19969 // ... [Till the alloca]
19970 // If stacklet is not large enough, jump to mallocMBB
19973 // Allocate by subtracting from RSP
19974 // Jump to continueMBB
19977 // Allocate by call to runtime
19981 // [rest of original BB]
19984 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19985 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19986 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19988 MachineRegisterInfo &MRI = MF->getRegInfo();
19989 const TargetRegisterClass *AddrRegClass =
19990 getRegClassFor(getPointerTy());
19992 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19993 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19994 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19995 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19996 sizeVReg = MI->getOperand(1).getReg(),
19997 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19999 MachineFunction::iterator MBBIter = BB;
20002 MF->insert(MBBIter, bumpMBB);
20003 MF->insert(MBBIter, mallocMBB);
20004 MF->insert(MBBIter, continueMBB);
20006 continueMBB->splice(continueMBB->begin(), BB,
20007 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20008 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20010 // Add code to the main basic block to check if the stack limit has been hit,
20011 // and if so, jump to mallocMBB otherwise to bumpMBB.
20012 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20013 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20014 .addReg(tmpSPVReg).addReg(sizeVReg);
20015 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20016 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20017 .addReg(SPLimitVReg);
20018 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20020 // bumpMBB simply decreases the stack pointer, since we know the current
20021 // stacklet has enough space.
20022 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20023 .addReg(SPLimitVReg);
20024 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20025 .addReg(SPLimitVReg);
20026 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20028 // Calls into a routine in libgcc to allocate more space from the heap.
20029 const uint32_t *RegMask = MF->getTarget()
20030 .getSubtargetImpl()
20031 ->getRegisterInfo()
20032 ->getCallPreservedMask(CallingConv::C);
20034 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20036 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20037 .addExternalSymbol("__morestack_allocate_stack_space")
20038 .addRegMask(RegMask)
20039 .addReg(X86::RDI, RegState::Implicit)
20040 .addReg(X86::RAX, RegState::ImplicitDefine);
20041 } else if (Is64Bit) {
20042 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20044 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20045 .addExternalSymbol("__morestack_allocate_stack_space")
20046 .addRegMask(RegMask)
20047 .addReg(X86::EDI, RegState::Implicit)
20048 .addReg(X86::EAX, RegState::ImplicitDefine);
20050 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20052 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20053 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20054 .addExternalSymbol("__morestack_allocate_stack_space")
20055 .addRegMask(RegMask)
20056 .addReg(X86::EAX, RegState::ImplicitDefine);
20060 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20063 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20064 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20065 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20067 // Set up the CFG correctly.
20068 BB->addSuccessor(bumpMBB);
20069 BB->addSuccessor(mallocMBB);
20070 mallocMBB->addSuccessor(continueMBB);
20071 bumpMBB->addSuccessor(continueMBB);
20073 // Take care of the PHI nodes.
20074 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20075 MI->getOperand(0).getReg())
20076 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20077 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20079 // Delete the original pseudo instruction.
20080 MI->eraseFromParent();
20083 return continueMBB;
20086 MachineBasicBlock *
20087 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20088 MachineBasicBlock *BB) const {
20089 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20090 DebugLoc DL = MI->getDebugLoc();
20092 assert(!Subtarget->isTargetMacho());
20094 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20095 // non-trivial part is impdef of ESP.
20097 if (Subtarget->isTargetWin64()) {
20098 if (Subtarget->isTargetCygMing()) {
20099 // ___chkstk(Mingw64):
20100 // Clobbers R10, R11, RAX and EFLAGS.
20102 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20103 .addExternalSymbol("___chkstk")
20104 .addReg(X86::RAX, RegState::Implicit)
20105 .addReg(X86::RSP, RegState::Implicit)
20106 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20107 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20108 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20110 // __chkstk(MSVCRT): does not update stack pointer.
20111 // Clobbers R10, R11 and EFLAGS.
20112 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20113 .addExternalSymbol("__chkstk")
20114 .addReg(X86::RAX, RegState::Implicit)
20115 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20116 // RAX has the offset to be subtracted from RSP.
20117 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20122 const char *StackProbeSymbol =
20123 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20125 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20126 .addExternalSymbol(StackProbeSymbol)
20127 .addReg(X86::EAX, RegState::Implicit)
20128 .addReg(X86::ESP, RegState::Implicit)
20129 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20130 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20131 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20134 MI->eraseFromParent(); // The pseudo instruction is gone now.
20138 MachineBasicBlock *
20139 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20140 MachineBasicBlock *BB) const {
20141 // This is pretty easy. We're taking the value that we received from
20142 // our load from the relocation, sticking it in either RDI (x86-64)
20143 // or EAX and doing an indirect call. The return value will then
20144 // be in the normal return register.
20145 MachineFunction *F = BB->getParent();
20146 const X86InstrInfo *TII =
20147 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20148 DebugLoc DL = MI->getDebugLoc();
20150 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20151 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20153 // Get a register mask for the lowered call.
20154 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20155 // proper register mask.
20156 const uint32_t *RegMask = F->getTarget()
20157 .getSubtargetImpl()
20158 ->getRegisterInfo()
20159 ->getCallPreservedMask(CallingConv::C);
20160 if (Subtarget->is64Bit()) {
20161 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20162 TII->get(X86::MOV64rm), X86::RDI)
20164 .addImm(0).addReg(0)
20165 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20166 MI->getOperand(3).getTargetFlags())
20168 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20169 addDirectMem(MIB, X86::RDI);
20170 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20171 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20172 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20173 TII->get(X86::MOV32rm), X86::EAX)
20175 .addImm(0).addReg(0)
20176 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20177 MI->getOperand(3).getTargetFlags())
20179 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20180 addDirectMem(MIB, X86::EAX);
20181 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20183 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20184 TII->get(X86::MOV32rm), X86::EAX)
20185 .addReg(TII->getGlobalBaseReg(F))
20186 .addImm(0).addReg(0)
20187 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20188 MI->getOperand(3).getTargetFlags())
20190 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20191 addDirectMem(MIB, X86::EAX);
20192 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20195 MI->eraseFromParent(); // The pseudo instruction is gone now.
20199 MachineBasicBlock *
20200 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20201 MachineBasicBlock *MBB) const {
20202 DebugLoc DL = MI->getDebugLoc();
20203 MachineFunction *MF = MBB->getParent();
20204 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20205 MachineRegisterInfo &MRI = MF->getRegInfo();
20207 const BasicBlock *BB = MBB->getBasicBlock();
20208 MachineFunction::iterator I = MBB;
20211 // Memory Reference
20212 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20213 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20216 unsigned MemOpndSlot = 0;
20218 unsigned CurOp = 0;
20220 DstReg = MI->getOperand(CurOp++).getReg();
20221 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20222 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20223 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20224 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20226 MemOpndSlot = CurOp;
20228 MVT PVT = getPointerTy();
20229 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20230 "Invalid Pointer Size!");
20232 // For v = setjmp(buf), we generate
20235 // buf[LabelOffset] = restoreMBB
20236 // SjLjSetup restoreMBB
20242 // v = phi(main, restore)
20247 MachineBasicBlock *thisMBB = MBB;
20248 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20249 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20250 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20251 MF->insert(I, mainMBB);
20252 MF->insert(I, sinkMBB);
20253 MF->push_back(restoreMBB);
20255 MachineInstrBuilder MIB;
20257 // Transfer the remainder of BB and its successor edges to sinkMBB.
20258 sinkMBB->splice(sinkMBB->begin(), MBB,
20259 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20260 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20263 unsigned PtrStoreOpc = 0;
20264 unsigned LabelReg = 0;
20265 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20266 Reloc::Model RM = MF->getTarget().getRelocationModel();
20267 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20268 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20270 // Prepare IP either in reg or imm.
20271 if (!UseImmLabel) {
20272 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20273 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20274 LabelReg = MRI.createVirtualRegister(PtrRC);
20275 if (Subtarget->is64Bit()) {
20276 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20280 .addMBB(restoreMBB)
20283 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20284 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20285 .addReg(XII->getGlobalBaseReg(MF))
20288 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20292 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20294 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20295 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20296 if (i == X86::AddrDisp)
20297 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20299 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20302 MIB.addReg(LabelReg);
20304 MIB.addMBB(restoreMBB);
20305 MIB.setMemRefs(MMOBegin, MMOEnd);
20307 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20308 .addMBB(restoreMBB);
20310 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20311 MF->getSubtarget().getRegisterInfo());
20312 MIB.addRegMask(RegInfo->getNoPreservedMask());
20313 thisMBB->addSuccessor(mainMBB);
20314 thisMBB->addSuccessor(restoreMBB);
20318 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20319 mainMBB->addSuccessor(sinkMBB);
20322 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20323 TII->get(X86::PHI), DstReg)
20324 .addReg(mainDstReg).addMBB(mainMBB)
20325 .addReg(restoreDstReg).addMBB(restoreMBB);
20328 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20329 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20330 restoreMBB->addSuccessor(sinkMBB);
20332 MI->eraseFromParent();
20336 MachineBasicBlock *
20337 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20338 MachineBasicBlock *MBB) const {
20339 DebugLoc DL = MI->getDebugLoc();
20340 MachineFunction *MF = MBB->getParent();
20341 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20342 MachineRegisterInfo &MRI = MF->getRegInfo();
20344 // Memory Reference
20345 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20346 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20348 MVT PVT = getPointerTy();
20349 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20350 "Invalid Pointer Size!");
20352 const TargetRegisterClass *RC =
20353 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20354 unsigned Tmp = MRI.createVirtualRegister(RC);
20355 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20356 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20357 MF->getSubtarget().getRegisterInfo());
20358 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20359 unsigned SP = RegInfo->getStackRegister();
20361 MachineInstrBuilder MIB;
20363 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20364 const int64_t SPOffset = 2 * PVT.getStoreSize();
20366 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20367 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20370 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20371 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20372 MIB.addOperand(MI->getOperand(i));
20373 MIB.setMemRefs(MMOBegin, MMOEnd);
20375 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20376 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20377 if (i == X86::AddrDisp)
20378 MIB.addDisp(MI->getOperand(i), LabelOffset);
20380 MIB.addOperand(MI->getOperand(i));
20382 MIB.setMemRefs(MMOBegin, MMOEnd);
20384 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20385 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20386 if (i == X86::AddrDisp)
20387 MIB.addDisp(MI->getOperand(i), SPOffset);
20389 MIB.addOperand(MI->getOperand(i));
20391 MIB.setMemRefs(MMOBegin, MMOEnd);
20393 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20395 MI->eraseFromParent();
20399 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20400 // accumulator loops. Writing back to the accumulator allows the coalescer
20401 // to remove extra copies in the loop.
20402 MachineBasicBlock *
20403 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20404 MachineBasicBlock *MBB) const {
20405 MachineOperand &AddendOp = MI->getOperand(3);
20407 // Bail out early if the addend isn't a register - we can't switch these.
20408 if (!AddendOp.isReg())
20411 MachineFunction &MF = *MBB->getParent();
20412 MachineRegisterInfo &MRI = MF.getRegInfo();
20414 // Check whether the addend is defined by a PHI:
20415 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20416 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20417 if (!AddendDef.isPHI())
20420 // Look for the following pattern:
20422 // %addend = phi [%entry, 0], [%loop, %result]
20424 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20428 // %addend = phi [%entry, 0], [%loop, %result]
20430 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20432 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20433 assert(AddendDef.getOperand(i).isReg());
20434 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20435 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20436 if (&PHISrcInst == MI) {
20437 // Found a matching instruction.
20438 unsigned NewFMAOpc = 0;
20439 switch (MI->getOpcode()) {
20440 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20441 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20442 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20443 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20444 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20445 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20446 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20447 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20448 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20449 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20450 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20451 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20452 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20453 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20454 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20455 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20456 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20457 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20458 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20459 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20460 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20461 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20462 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20463 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20464 default: llvm_unreachable("Unrecognized FMA variant.");
20467 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20468 MachineInstrBuilder MIB =
20469 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20470 .addOperand(MI->getOperand(0))
20471 .addOperand(MI->getOperand(3))
20472 .addOperand(MI->getOperand(2))
20473 .addOperand(MI->getOperand(1));
20474 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20475 MI->eraseFromParent();
20482 MachineBasicBlock *
20483 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20484 MachineBasicBlock *BB) const {
20485 switch (MI->getOpcode()) {
20486 default: llvm_unreachable("Unexpected instr type to insert");
20487 case X86::TAILJMPd64:
20488 case X86::TAILJMPr64:
20489 case X86::TAILJMPm64:
20490 llvm_unreachable("TAILJMP64 would not be touched here.");
20491 case X86::TCRETURNdi64:
20492 case X86::TCRETURNri64:
20493 case X86::TCRETURNmi64:
20495 case X86::WIN_ALLOCA:
20496 return EmitLoweredWinAlloca(MI, BB);
20497 case X86::SEG_ALLOCA_32:
20498 case X86::SEG_ALLOCA_64:
20499 return EmitLoweredSegAlloca(MI, BB);
20500 case X86::TLSCall_32:
20501 case X86::TLSCall_64:
20502 return EmitLoweredTLSCall(MI, BB);
20503 case X86::CMOV_GR8:
20504 case X86::CMOV_FR32:
20505 case X86::CMOV_FR64:
20506 case X86::CMOV_V4F32:
20507 case X86::CMOV_V2F64:
20508 case X86::CMOV_V2I64:
20509 case X86::CMOV_V8F32:
20510 case X86::CMOV_V4F64:
20511 case X86::CMOV_V4I64:
20512 case X86::CMOV_V16F32:
20513 case X86::CMOV_V8F64:
20514 case X86::CMOV_V8I64:
20515 case X86::CMOV_GR16:
20516 case X86::CMOV_GR32:
20517 case X86::CMOV_RFP32:
20518 case X86::CMOV_RFP64:
20519 case X86::CMOV_RFP80:
20520 return EmitLoweredSelect(MI, BB);
20522 case X86::FP32_TO_INT16_IN_MEM:
20523 case X86::FP32_TO_INT32_IN_MEM:
20524 case X86::FP32_TO_INT64_IN_MEM:
20525 case X86::FP64_TO_INT16_IN_MEM:
20526 case X86::FP64_TO_INT32_IN_MEM:
20527 case X86::FP64_TO_INT64_IN_MEM:
20528 case X86::FP80_TO_INT16_IN_MEM:
20529 case X86::FP80_TO_INT32_IN_MEM:
20530 case X86::FP80_TO_INT64_IN_MEM: {
20531 MachineFunction *F = BB->getParent();
20532 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20533 DebugLoc DL = MI->getDebugLoc();
20535 // Change the floating point control register to use "round towards zero"
20536 // mode when truncating to an integer value.
20537 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20538 addFrameReference(BuildMI(*BB, MI, DL,
20539 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20541 // Load the old value of the high byte of the control word...
20543 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20544 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20547 // Set the high part to be round to zero...
20548 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20551 // Reload the modified control word now...
20552 addFrameReference(BuildMI(*BB, MI, DL,
20553 TII->get(X86::FLDCW16m)), CWFrameIdx);
20555 // Restore the memory image of control word to original value
20556 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20559 // Get the X86 opcode to use.
20561 switch (MI->getOpcode()) {
20562 default: llvm_unreachable("illegal opcode!");
20563 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20564 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20565 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20566 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20567 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20568 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20569 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20570 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20571 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20575 MachineOperand &Op = MI->getOperand(0);
20577 AM.BaseType = X86AddressMode::RegBase;
20578 AM.Base.Reg = Op.getReg();
20580 AM.BaseType = X86AddressMode::FrameIndexBase;
20581 AM.Base.FrameIndex = Op.getIndex();
20583 Op = MI->getOperand(1);
20585 AM.Scale = Op.getImm();
20586 Op = MI->getOperand(2);
20588 AM.IndexReg = Op.getImm();
20589 Op = MI->getOperand(3);
20590 if (Op.isGlobal()) {
20591 AM.GV = Op.getGlobal();
20593 AM.Disp = Op.getImm();
20595 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20596 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20598 // Reload the original control word now.
20599 addFrameReference(BuildMI(*BB, MI, DL,
20600 TII->get(X86::FLDCW16m)), CWFrameIdx);
20602 MI->eraseFromParent(); // The pseudo instruction is gone now.
20605 // String/text processing lowering.
20606 case X86::PCMPISTRM128REG:
20607 case X86::VPCMPISTRM128REG:
20608 case X86::PCMPISTRM128MEM:
20609 case X86::VPCMPISTRM128MEM:
20610 case X86::PCMPESTRM128REG:
20611 case X86::VPCMPESTRM128REG:
20612 case X86::PCMPESTRM128MEM:
20613 case X86::VPCMPESTRM128MEM:
20614 assert(Subtarget->hasSSE42() &&
20615 "Target must have SSE4.2 or AVX features enabled");
20616 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20618 // String/text processing lowering.
20619 case X86::PCMPISTRIREG:
20620 case X86::VPCMPISTRIREG:
20621 case X86::PCMPISTRIMEM:
20622 case X86::VPCMPISTRIMEM:
20623 case X86::PCMPESTRIREG:
20624 case X86::VPCMPESTRIREG:
20625 case X86::PCMPESTRIMEM:
20626 case X86::VPCMPESTRIMEM:
20627 assert(Subtarget->hasSSE42() &&
20628 "Target must have SSE4.2 or AVX features enabled");
20629 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20631 // Thread synchronization.
20633 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20638 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20640 case X86::VASTART_SAVE_XMM_REGS:
20641 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20643 case X86::VAARG_64:
20644 return EmitVAARG64WithCustomInserter(MI, BB);
20646 case X86::EH_SjLj_SetJmp32:
20647 case X86::EH_SjLj_SetJmp64:
20648 return emitEHSjLjSetJmp(MI, BB);
20650 case X86::EH_SjLj_LongJmp32:
20651 case X86::EH_SjLj_LongJmp64:
20652 return emitEHSjLjLongJmp(MI, BB);
20654 case TargetOpcode::STACKMAP:
20655 case TargetOpcode::PATCHPOINT:
20656 return emitPatchPoint(MI, BB);
20658 case X86::VFMADDPDr213r:
20659 case X86::VFMADDPSr213r:
20660 case X86::VFMADDSDr213r:
20661 case X86::VFMADDSSr213r:
20662 case X86::VFMSUBPDr213r:
20663 case X86::VFMSUBPSr213r:
20664 case X86::VFMSUBSDr213r:
20665 case X86::VFMSUBSSr213r:
20666 case X86::VFNMADDPDr213r:
20667 case X86::VFNMADDPSr213r:
20668 case X86::VFNMADDSDr213r:
20669 case X86::VFNMADDSSr213r:
20670 case X86::VFNMSUBPDr213r:
20671 case X86::VFNMSUBPSr213r:
20672 case X86::VFNMSUBSDr213r:
20673 case X86::VFNMSUBSSr213r:
20674 case X86::VFMADDPDr213rY:
20675 case X86::VFMADDPSr213rY:
20676 case X86::VFMSUBPDr213rY:
20677 case X86::VFMSUBPSr213rY:
20678 case X86::VFNMADDPDr213rY:
20679 case X86::VFNMADDPSr213rY:
20680 case X86::VFNMSUBPDr213rY:
20681 case X86::VFNMSUBPSr213rY:
20682 return emitFMA3Instr(MI, BB);
20686 //===----------------------------------------------------------------------===//
20687 // X86 Optimization Hooks
20688 //===----------------------------------------------------------------------===//
20690 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20693 const SelectionDAG &DAG,
20694 unsigned Depth) const {
20695 unsigned BitWidth = KnownZero.getBitWidth();
20696 unsigned Opc = Op.getOpcode();
20697 assert((Opc >= ISD::BUILTIN_OP_END ||
20698 Opc == ISD::INTRINSIC_WO_CHAIN ||
20699 Opc == ISD::INTRINSIC_W_CHAIN ||
20700 Opc == ISD::INTRINSIC_VOID) &&
20701 "Should use MaskedValueIsZero if you don't know whether Op"
20702 " is a target node!");
20704 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20718 // These nodes' second result is a boolean.
20719 if (Op.getResNo() == 0)
20722 case X86ISD::SETCC:
20723 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20725 case ISD::INTRINSIC_WO_CHAIN: {
20726 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20727 unsigned NumLoBits = 0;
20730 case Intrinsic::x86_sse_movmsk_ps:
20731 case Intrinsic::x86_avx_movmsk_ps_256:
20732 case Intrinsic::x86_sse2_movmsk_pd:
20733 case Intrinsic::x86_avx_movmsk_pd_256:
20734 case Intrinsic::x86_mmx_pmovmskb:
20735 case Intrinsic::x86_sse2_pmovmskb_128:
20736 case Intrinsic::x86_avx2_pmovmskb: {
20737 // High bits of movmskp{s|d}, pmovmskb are known zero.
20739 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20740 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20741 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20742 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20743 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20744 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20745 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20746 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20748 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20757 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20759 const SelectionDAG &,
20760 unsigned Depth) const {
20761 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20762 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20763 return Op.getValueType().getScalarType().getSizeInBits();
20769 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20770 /// node is a GlobalAddress + offset.
20771 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20772 const GlobalValue* &GA,
20773 int64_t &Offset) const {
20774 if (N->getOpcode() == X86ISD::Wrapper) {
20775 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20776 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20777 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20781 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20784 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20785 /// same as extracting the high 128-bit part of 256-bit vector and then
20786 /// inserting the result into the low part of a new 256-bit vector
20787 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20788 EVT VT = SVOp->getValueType(0);
20789 unsigned NumElems = VT.getVectorNumElements();
20791 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20792 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20793 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20794 SVOp->getMaskElt(j) >= 0)
20800 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20801 /// same as extracting the low 128-bit part of 256-bit vector and then
20802 /// inserting the result into the high part of a new 256-bit vector
20803 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20804 EVT VT = SVOp->getValueType(0);
20805 unsigned NumElems = VT.getVectorNumElements();
20807 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20808 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20809 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20810 SVOp->getMaskElt(j) >= 0)
20816 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20817 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20818 TargetLowering::DAGCombinerInfo &DCI,
20819 const X86Subtarget* Subtarget) {
20821 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20822 SDValue V1 = SVOp->getOperand(0);
20823 SDValue V2 = SVOp->getOperand(1);
20824 EVT VT = SVOp->getValueType(0);
20825 unsigned NumElems = VT.getVectorNumElements();
20827 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20828 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20832 // V UNDEF BUILD_VECTOR UNDEF
20834 // CONCAT_VECTOR CONCAT_VECTOR
20837 // RESULT: V + zero extended
20839 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20840 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20841 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20844 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20847 // To match the shuffle mask, the first half of the mask should
20848 // be exactly the first vector, and all the rest a splat with the
20849 // first element of the second one.
20850 for (unsigned i = 0; i != NumElems/2; ++i)
20851 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20852 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20855 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20856 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20857 if (Ld->hasNUsesOfValue(1, 0)) {
20858 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20859 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20861 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20863 Ld->getPointerInfo(),
20864 Ld->getAlignment(),
20865 false/*isVolatile*/, true/*ReadMem*/,
20866 false/*WriteMem*/);
20868 // Make sure the newly-created LOAD is in the same position as Ld in
20869 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20870 // and update uses of Ld's output chain to use the TokenFactor.
20871 if (Ld->hasAnyUseOfValue(1)) {
20872 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20873 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20874 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20875 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20876 SDValue(ResNode.getNode(), 1));
20879 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20883 // Emit a zeroed vector and insert the desired subvector on its
20885 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20886 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20887 return DCI.CombineTo(N, InsV);
20890 //===--------------------------------------------------------------------===//
20891 // Combine some shuffles into subvector extracts and inserts:
20894 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20895 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20896 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20897 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20898 return DCI.CombineTo(N, InsV);
20901 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20902 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20903 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20904 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20905 return DCI.CombineTo(N, InsV);
20911 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20914 /// This is the leaf of the recursive combinine below. When we have found some
20915 /// chain of single-use x86 shuffle instructions and accumulated the combined
20916 /// shuffle mask represented by them, this will try to pattern match that mask
20917 /// into either a single instruction if there is a special purpose instruction
20918 /// for this operation, or into a PSHUFB instruction which is a fully general
20919 /// instruction but should only be used to replace chains over a certain depth.
20920 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20921 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20922 TargetLowering::DAGCombinerInfo &DCI,
20923 const X86Subtarget *Subtarget) {
20924 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20926 // Find the operand that enters the chain. Note that multiple uses are OK
20927 // here, we're not going to remove the operand we find.
20928 SDValue Input = Op.getOperand(0);
20929 while (Input.getOpcode() == ISD::BITCAST)
20930 Input = Input.getOperand(0);
20932 MVT VT = Input.getSimpleValueType();
20933 MVT RootVT = Root.getSimpleValueType();
20936 // Just remove no-op shuffle masks.
20937 if (Mask.size() == 1) {
20938 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20943 // Use the float domain if the operand type is a floating point type.
20944 bool FloatDomain = VT.isFloatingPoint();
20946 // For floating point shuffles, we don't have free copies in the shuffle
20947 // instructions or the ability to load as part of the instruction, so
20948 // canonicalize their shuffles to UNPCK or MOV variants.
20950 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20951 // vectors because it can have a load folded into it that UNPCK cannot. This
20952 // doesn't preclude something switching to the shorter encoding post-RA.
20954 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20955 bool Lo = Mask.equals(0, 0);
20958 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20959 // is no slower than UNPCKLPD but has the option to fold the input operand
20960 // into even an unaligned memory load.
20961 if (Lo && Subtarget->hasSSE3()) {
20962 Shuffle = X86ISD::MOVDDUP;
20963 ShuffleVT = MVT::v2f64;
20965 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20966 // than the UNPCK variants.
20967 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20968 ShuffleVT = MVT::v4f32;
20970 if (Depth == 1 && Root->getOpcode() == Shuffle)
20971 return false; // Nothing to do!
20972 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20973 DCI.AddToWorklist(Op.getNode());
20974 if (Shuffle == X86ISD::MOVDDUP)
20975 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20977 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20978 DCI.AddToWorklist(Op.getNode());
20979 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20983 if (Subtarget->hasSSE3() &&
20984 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20985 bool Lo = Mask.equals(0, 0, 2, 2);
20986 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20987 MVT ShuffleVT = MVT::v4f32;
20988 if (Depth == 1 && Root->getOpcode() == Shuffle)
20989 return false; // Nothing to do!
20990 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20991 DCI.AddToWorklist(Op.getNode());
20992 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20993 DCI.AddToWorklist(Op.getNode());
20994 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20998 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20999 bool Lo = Mask.equals(0, 0, 1, 1);
21000 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21001 MVT ShuffleVT = MVT::v4f32;
21002 if (Depth == 1 && Root->getOpcode() == Shuffle)
21003 return false; // Nothing to do!
21004 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21005 DCI.AddToWorklist(Op.getNode());
21006 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21007 DCI.AddToWorklist(Op.getNode());
21008 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21014 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21015 // variants as none of these have single-instruction variants that are
21016 // superior to the UNPCK formulation.
21017 if (!FloatDomain &&
21018 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21019 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21020 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21021 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21023 bool Lo = Mask[0] == 0;
21024 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21025 if (Depth == 1 && Root->getOpcode() == Shuffle)
21026 return false; // Nothing to do!
21028 switch (Mask.size()) {
21030 ShuffleVT = MVT::v8i16;
21033 ShuffleVT = MVT::v16i8;
21036 llvm_unreachable("Impossible mask size!");
21038 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21039 DCI.AddToWorklist(Op.getNode());
21040 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21041 DCI.AddToWorklist(Op.getNode());
21042 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21047 // Don't try to re-form single instruction chains under any circumstances now
21048 // that we've done encoding canonicalization for them.
21052 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21053 // can replace them with a single PSHUFB instruction profitably. Intel's
21054 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21055 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21056 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21057 SmallVector<SDValue, 16> PSHUFBMask;
21058 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21059 int Ratio = 16 / Mask.size();
21060 for (unsigned i = 0; i < 16; ++i) {
21061 if (Mask[i / Ratio] == SM_SentinelUndef) {
21062 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21065 int M = Mask[i / Ratio] != SM_SentinelZero
21066 ? Ratio * Mask[i / Ratio] + i % Ratio
21068 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21070 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21071 DCI.AddToWorklist(Op.getNode());
21072 SDValue PSHUFBMaskOp =
21073 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21074 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21075 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21076 DCI.AddToWorklist(Op.getNode());
21077 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21082 // Failed to find any combines.
21086 /// \brief Fully generic combining of x86 shuffle instructions.
21088 /// This should be the last combine run over the x86 shuffle instructions. Once
21089 /// they have been fully optimized, this will recursively consider all chains
21090 /// of single-use shuffle instructions, build a generic model of the cumulative
21091 /// shuffle operation, and check for simpler instructions which implement this
21092 /// operation. We use this primarily for two purposes:
21094 /// 1) Collapse generic shuffles to specialized single instructions when
21095 /// equivalent. In most cases, this is just an encoding size win, but
21096 /// sometimes we will collapse multiple generic shuffles into a single
21097 /// special-purpose shuffle.
21098 /// 2) Look for sequences of shuffle instructions with 3 or more total
21099 /// instructions, and replace them with the slightly more expensive SSSE3
21100 /// PSHUFB instruction if available. We do this as the last combining step
21101 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21102 /// a suitable short sequence of other instructions. The PHUFB will either
21103 /// use a register or have to read from memory and so is slightly (but only
21104 /// slightly) more expensive than the other shuffle instructions.
21106 /// Because this is inherently a quadratic operation (for each shuffle in
21107 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21108 /// This should never be an issue in practice as the shuffle lowering doesn't
21109 /// produce sequences of more than 8 instructions.
21111 /// FIXME: We will currently miss some cases where the redundant shuffling
21112 /// would simplify under the threshold for PSHUFB formation because of
21113 /// combine-ordering. To fix this, we should do the redundant instruction
21114 /// combining in this recursive walk.
21115 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21116 ArrayRef<int> RootMask,
21117 int Depth, bool HasPSHUFB,
21119 TargetLowering::DAGCombinerInfo &DCI,
21120 const X86Subtarget *Subtarget) {
21121 // Bound the depth of our recursive combine because this is ultimately
21122 // quadratic in nature.
21126 // Directly rip through bitcasts to find the underlying operand.
21127 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21128 Op = Op.getOperand(0);
21130 MVT VT = Op.getSimpleValueType();
21131 if (!VT.isVector())
21132 return false; // Bail if we hit a non-vector.
21133 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21134 // version should be added.
21135 if (VT.getSizeInBits() != 128)
21138 assert(Root.getSimpleValueType().isVector() &&
21139 "Shuffles operate on vector types!");
21140 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21141 "Can only combine shuffles of the same vector register size.");
21143 if (!isTargetShuffle(Op.getOpcode()))
21145 SmallVector<int, 16> OpMask;
21147 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21148 // We only can combine unary shuffles which we can decode the mask for.
21149 if (!HaveMask || !IsUnary)
21152 assert(VT.getVectorNumElements() == OpMask.size() &&
21153 "Different mask size from vector size!");
21154 assert(((RootMask.size() > OpMask.size() &&
21155 RootMask.size() % OpMask.size() == 0) ||
21156 (OpMask.size() > RootMask.size() &&
21157 OpMask.size() % RootMask.size() == 0) ||
21158 OpMask.size() == RootMask.size()) &&
21159 "The smaller number of elements must divide the larger.");
21160 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21161 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21162 assert(((RootRatio == 1 && OpRatio == 1) ||
21163 (RootRatio == 1) != (OpRatio == 1)) &&
21164 "Must not have a ratio for both incoming and op masks!");
21166 SmallVector<int, 16> Mask;
21167 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21169 // Merge this shuffle operation's mask into our accumulated mask. Note that
21170 // this shuffle's mask will be the first applied to the input, followed by the
21171 // root mask to get us all the way to the root value arrangement. The reason
21172 // for this order is that we are recursing up the operation chain.
21173 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21174 int RootIdx = i / RootRatio;
21175 if (RootMask[RootIdx] < 0) {
21176 // This is a zero or undef lane, we're done.
21177 Mask.push_back(RootMask[RootIdx]);
21181 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21182 int OpIdx = RootMaskedIdx / OpRatio;
21183 if (OpMask[OpIdx] < 0) {
21184 // The incoming lanes are zero or undef, it doesn't matter which ones we
21186 Mask.push_back(OpMask[OpIdx]);
21190 // Ok, we have non-zero lanes, map them through.
21191 Mask.push_back(OpMask[OpIdx] * OpRatio +
21192 RootMaskedIdx % OpRatio);
21195 // See if we can recurse into the operand to combine more things.
21196 switch (Op.getOpcode()) {
21197 case X86ISD::PSHUFB:
21199 case X86ISD::PSHUFD:
21200 case X86ISD::PSHUFHW:
21201 case X86ISD::PSHUFLW:
21202 if (Op.getOperand(0).hasOneUse() &&
21203 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21204 HasPSHUFB, DAG, DCI, Subtarget))
21208 case X86ISD::UNPCKL:
21209 case X86ISD::UNPCKH:
21210 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21211 // We can't check for single use, we have to check that this shuffle is the only user.
21212 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21213 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21214 HasPSHUFB, DAG, DCI, Subtarget))
21219 // Minor canonicalization of the accumulated shuffle mask to make it easier
21220 // to match below. All this does is detect masks with squential pairs of
21221 // elements, and shrink them to the half-width mask. It does this in a loop
21222 // so it will reduce the size of the mask to the minimal width mask which
21223 // performs an equivalent shuffle.
21224 SmallVector<int, 16> WidenedMask;
21225 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21226 Mask = std::move(WidenedMask);
21227 WidenedMask.clear();
21230 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21234 /// \brief Get the PSHUF-style mask from PSHUF node.
21236 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21237 /// PSHUF-style masks that can be reused with such instructions.
21238 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21239 SmallVector<int, 4> Mask;
21241 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21245 switch (N.getOpcode()) {
21246 case X86ISD::PSHUFD:
21248 case X86ISD::PSHUFLW:
21251 case X86ISD::PSHUFHW:
21252 Mask.erase(Mask.begin(), Mask.begin() + 4);
21253 for (int &M : Mask)
21257 llvm_unreachable("No valid shuffle instruction found!");
21261 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21263 /// We walk up the chain and look for a combinable shuffle, skipping over
21264 /// shuffles that we could hoist this shuffle's transformation past without
21265 /// altering anything.
21267 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21269 TargetLowering::DAGCombinerInfo &DCI) {
21270 assert(N.getOpcode() == X86ISD::PSHUFD &&
21271 "Called with something other than an x86 128-bit half shuffle!");
21274 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21275 // of the shuffles in the chain so that we can form a fresh chain to replace
21277 SmallVector<SDValue, 8> Chain;
21278 SDValue V = N.getOperand(0);
21279 for (; V.hasOneUse(); V = V.getOperand(0)) {
21280 switch (V.getOpcode()) {
21282 return SDValue(); // Nothing combined!
21285 // Skip bitcasts as we always know the type for the target specific
21289 case X86ISD::PSHUFD:
21290 // Found another dword shuffle.
21293 case X86ISD::PSHUFLW:
21294 // Check that the low words (being shuffled) are the identity in the
21295 // dword shuffle, and the high words are self-contained.
21296 if (Mask[0] != 0 || Mask[1] != 1 ||
21297 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21300 Chain.push_back(V);
21303 case X86ISD::PSHUFHW:
21304 // Check that the high words (being shuffled) are the identity in the
21305 // dword shuffle, and the low words are self-contained.
21306 if (Mask[2] != 2 || Mask[3] != 3 ||
21307 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21310 Chain.push_back(V);
21313 case X86ISD::UNPCKL:
21314 case X86ISD::UNPCKH:
21315 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21316 // shuffle into a preceding word shuffle.
21317 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21320 // Search for a half-shuffle which we can combine with.
21321 unsigned CombineOp =
21322 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21323 if (V.getOperand(0) != V.getOperand(1) ||
21324 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21326 Chain.push_back(V);
21327 V = V.getOperand(0);
21329 switch (V.getOpcode()) {
21331 return SDValue(); // Nothing to combine.
21333 case X86ISD::PSHUFLW:
21334 case X86ISD::PSHUFHW:
21335 if (V.getOpcode() == CombineOp)
21338 Chain.push_back(V);
21342 V = V.getOperand(0);
21346 } while (V.hasOneUse());
21349 // Break out of the loop if we break out of the switch.
21353 if (!V.hasOneUse())
21354 // We fell out of the loop without finding a viable combining instruction.
21357 // Merge this node's mask and our incoming mask.
21358 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21359 for (int &M : Mask)
21361 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21362 getV4X86ShuffleImm8ForMask(Mask, DAG));
21364 // Rebuild the chain around this new shuffle.
21365 while (!Chain.empty()) {
21366 SDValue W = Chain.pop_back_val();
21368 if (V.getValueType() != W.getOperand(0).getValueType())
21369 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21371 switch (W.getOpcode()) {
21373 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21375 case X86ISD::UNPCKL:
21376 case X86ISD::UNPCKH:
21377 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21380 case X86ISD::PSHUFD:
21381 case X86ISD::PSHUFLW:
21382 case X86ISD::PSHUFHW:
21383 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21387 if (V.getValueType() != N.getValueType())
21388 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21390 // Return the new chain to replace N.
21394 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21396 /// We walk up the chain, skipping shuffles of the other half and looking
21397 /// through shuffles which switch halves trying to find a shuffle of the same
21398 /// pair of dwords.
21399 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21401 TargetLowering::DAGCombinerInfo &DCI) {
21403 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21404 "Called with something other than an x86 128-bit half shuffle!");
21406 unsigned CombineOpcode = N.getOpcode();
21408 // Walk up a single-use chain looking for a combinable shuffle.
21409 SDValue V = N.getOperand(0);
21410 for (; V.hasOneUse(); V = V.getOperand(0)) {
21411 switch (V.getOpcode()) {
21413 return false; // Nothing combined!
21416 // Skip bitcasts as we always know the type for the target specific
21420 case X86ISD::PSHUFLW:
21421 case X86ISD::PSHUFHW:
21422 if (V.getOpcode() == CombineOpcode)
21425 // Other-half shuffles are no-ops.
21428 // Break out of the loop if we break out of the switch.
21432 if (!V.hasOneUse())
21433 // We fell out of the loop without finding a viable combining instruction.
21436 // Combine away the bottom node as its shuffle will be accumulated into
21437 // a preceding shuffle.
21438 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21440 // Record the old value.
21443 // Merge this node's mask and our incoming mask (adjusted to account for all
21444 // the pshufd instructions encountered).
21445 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21446 for (int &M : Mask)
21448 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21449 getV4X86ShuffleImm8ForMask(Mask, DAG));
21451 // Check that the shuffles didn't cancel each other out. If not, we need to
21452 // combine to the new one.
21454 // Replace the combinable shuffle with the combined one, updating all users
21455 // so that we re-evaluate the chain here.
21456 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21461 /// \brief Try to combine x86 target specific shuffles.
21462 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21463 TargetLowering::DAGCombinerInfo &DCI,
21464 const X86Subtarget *Subtarget) {
21466 MVT VT = N.getSimpleValueType();
21467 SmallVector<int, 4> Mask;
21469 switch (N.getOpcode()) {
21470 case X86ISD::PSHUFD:
21471 case X86ISD::PSHUFLW:
21472 case X86ISD::PSHUFHW:
21473 Mask = getPSHUFShuffleMask(N);
21474 assert(Mask.size() == 4);
21480 // Nuke no-op shuffles that show up after combining.
21481 if (isNoopShuffleMask(Mask))
21482 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21484 // Look for simplifications involving one or two shuffle instructions.
21485 SDValue V = N.getOperand(0);
21486 switch (N.getOpcode()) {
21489 case X86ISD::PSHUFLW:
21490 case X86ISD::PSHUFHW:
21491 assert(VT == MVT::v8i16);
21494 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21495 return SDValue(); // We combined away this shuffle, so we're done.
21497 // See if this reduces to a PSHUFD which is no more expensive and can
21498 // combine with more operations. Note that it has to at least flip the
21499 // dwords as otherwise it would have been removed as a no-op.
21500 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21501 int DMask[] = {0, 1, 2, 3};
21502 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21503 DMask[DOffset + 0] = DOffset + 1;
21504 DMask[DOffset + 1] = DOffset + 0;
21505 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21506 DCI.AddToWorklist(V.getNode());
21507 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21508 getV4X86ShuffleImm8ForMask(DMask, DAG));
21509 DCI.AddToWorklist(V.getNode());
21510 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21513 // Look for shuffle patterns which can be implemented as a single unpack.
21514 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21515 // only works when we have a PSHUFD followed by two half-shuffles.
21516 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21517 (V.getOpcode() == X86ISD::PSHUFLW ||
21518 V.getOpcode() == X86ISD::PSHUFHW) &&
21519 V.getOpcode() != N.getOpcode() &&
21521 SDValue D = V.getOperand(0);
21522 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21523 D = D.getOperand(0);
21524 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21525 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21526 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21527 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21528 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21530 for (int i = 0; i < 4; ++i) {
21531 WordMask[i + NOffset] = Mask[i] + NOffset;
21532 WordMask[i + VOffset] = VMask[i] + VOffset;
21534 // Map the word mask through the DWord mask.
21536 for (int i = 0; i < 8; ++i)
21537 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21538 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21539 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21540 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21541 std::begin(UnpackLoMask)) ||
21542 std::equal(std::begin(MappedMask), std::end(MappedMask),
21543 std::begin(UnpackHiMask))) {
21544 // We can replace all three shuffles with an unpack.
21545 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21546 DCI.AddToWorklist(V.getNode());
21547 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21549 DL, MVT::v8i16, V, V);
21556 case X86ISD::PSHUFD:
21557 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21566 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21568 /// We combine this directly on the abstract vector shuffle nodes so it is
21569 /// easier to generically match. We also insert dummy vector shuffle nodes for
21570 /// the operands which explicitly discard the lanes which are unused by this
21571 /// operation to try to flow through the rest of the combiner the fact that
21572 /// they're unused.
21573 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21575 EVT VT = N->getValueType(0);
21577 // We only handle target-independent shuffles.
21578 // FIXME: It would be easy and harmless to use the target shuffle mask
21579 // extraction tool to support more.
21580 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21583 auto *SVN = cast<ShuffleVectorSDNode>(N);
21584 ArrayRef<int> Mask = SVN->getMask();
21585 SDValue V1 = N->getOperand(0);
21586 SDValue V2 = N->getOperand(1);
21588 // We require the first shuffle operand to be the SUB node, and the second to
21589 // be the ADD node.
21590 // FIXME: We should support the commuted patterns.
21591 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21594 // If there are other uses of these operations we can't fold them.
21595 if (!V1->hasOneUse() || !V2->hasOneUse())
21598 // Ensure that both operations have the same operands. Note that we can
21599 // commute the FADD operands.
21600 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21601 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21602 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21605 // We're looking for blends between FADD and FSUB nodes. We insist on these
21606 // nodes being lined up in a specific expected pattern.
21607 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21608 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21609 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21612 // Only specific types are legal at this point, assert so we notice if and
21613 // when these change.
21614 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21615 VT == MVT::v4f64) &&
21616 "Unknown vector type encountered!");
21618 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21621 /// PerformShuffleCombine - Performs several different shuffle combines.
21622 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21623 TargetLowering::DAGCombinerInfo &DCI,
21624 const X86Subtarget *Subtarget) {
21626 SDValue N0 = N->getOperand(0);
21627 SDValue N1 = N->getOperand(1);
21628 EVT VT = N->getValueType(0);
21630 // Don't create instructions with illegal types after legalize types has run.
21631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21632 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21635 // If we have legalized the vector types, look for blends of FADD and FSUB
21636 // nodes that we can fuse into an ADDSUB node.
21637 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21638 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21641 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21642 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21643 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21644 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21646 // During Type Legalization, when promoting illegal vector types,
21647 // the backend might introduce new shuffle dag nodes and bitcasts.
21649 // This code performs the following transformation:
21650 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21651 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21653 // We do this only if both the bitcast and the BINOP dag nodes have
21654 // one use. Also, perform this transformation only if the new binary
21655 // operation is legal. This is to avoid introducing dag nodes that
21656 // potentially need to be further expanded (or custom lowered) into a
21657 // less optimal sequence of dag nodes.
21658 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21659 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21660 N0.getOpcode() == ISD::BITCAST) {
21661 SDValue BC0 = N0.getOperand(0);
21662 EVT SVT = BC0.getValueType();
21663 unsigned Opcode = BC0.getOpcode();
21664 unsigned NumElts = VT.getVectorNumElements();
21666 if (BC0.hasOneUse() && SVT.isVector() &&
21667 SVT.getVectorNumElements() * 2 == NumElts &&
21668 TLI.isOperationLegal(Opcode, VT)) {
21669 bool CanFold = false;
21681 unsigned SVTNumElts = SVT.getVectorNumElements();
21682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21683 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21684 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21685 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21686 CanFold = SVOp->getMaskElt(i) < 0;
21689 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21690 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21691 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21692 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21697 // Only handle 128 wide vector from here on.
21698 if (!VT.is128BitVector())
21701 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21702 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21703 // consecutive, non-overlapping, and in the right order.
21704 SmallVector<SDValue, 16> Elts;
21705 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21706 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21708 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21712 if (isTargetShuffle(N->getOpcode())) {
21714 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21715 if (Shuffle.getNode())
21718 // Try recursively combining arbitrary sequences of x86 shuffle
21719 // instructions into higher-order shuffles. We do this after combining
21720 // specific PSHUF instruction sequences into their minimal form so that we
21721 // can evaluate how many specialized shuffle instructions are involved in
21722 // a particular chain.
21723 SmallVector<int, 1> NonceMask; // Just a placeholder.
21724 NonceMask.push_back(0);
21725 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21726 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21728 return SDValue(); // This routine will use CombineTo to replace N.
21734 /// PerformTruncateCombine - Converts truncate operation to
21735 /// a sequence of vector shuffle operations.
21736 /// It is possible when we truncate 256-bit vector to 128-bit vector
21737 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21738 TargetLowering::DAGCombinerInfo &DCI,
21739 const X86Subtarget *Subtarget) {
21743 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21744 /// specific shuffle of a load can be folded into a single element load.
21745 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21746 /// shuffles have been customed lowered so we need to handle those here.
21747 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21748 TargetLowering::DAGCombinerInfo &DCI) {
21749 if (DCI.isBeforeLegalizeOps())
21752 SDValue InVec = N->getOperand(0);
21753 SDValue EltNo = N->getOperand(1);
21755 if (!isa<ConstantSDNode>(EltNo))
21758 EVT VT = InVec.getValueType();
21760 if (InVec.getOpcode() == ISD::BITCAST) {
21761 // Don't duplicate a load with other uses.
21762 if (!InVec.hasOneUse())
21764 EVT BCVT = InVec.getOperand(0).getValueType();
21765 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21767 InVec = InVec.getOperand(0);
21770 if (!isTargetShuffle(InVec.getOpcode()))
21773 // Don't duplicate a load with other uses.
21774 if (!InVec.hasOneUse())
21777 SmallVector<int, 16> ShuffleMask;
21779 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21783 // Select the input vector, guarding against out of range extract vector.
21784 unsigned NumElems = VT.getVectorNumElements();
21785 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21786 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21787 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21788 : InVec.getOperand(1);
21790 // If inputs to shuffle are the same for both ops, then allow 2 uses
21791 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21793 if (LdNode.getOpcode() == ISD::BITCAST) {
21794 // Don't duplicate a load with other uses.
21795 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21798 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21799 LdNode = LdNode.getOperand(0);
21802 if (!ISD::isNormalLoad(LdNode.getNode()))
21805 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21807 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21810 EVT EltVT = N->getValueType(0);
21811 // If there's a bitcast before the shuffle, check if the load type and
21812 // alignment is valid.
21813 unsigned Align = LN0->getAlignment();
21814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21815 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21816 EltVT.getTypeForEVT(*DAG.getContext()));
21818 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21821 // All checks match so transform back to vector_shuffle so that DAG combiner
21822 // can finish the job
21825 // Create shuffle node taking into account the case that its a unary shuffle
21826 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21827 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21828 InVec.getOperand(0), Shuffle,
21830 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21831 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21835 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21836 /// generation and convert it from being a bunch of shuffles and extracts
21837 /// to a simple store and scalar loads to extract the elements.
21838 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21839 TargetLowering::DAGCombinerInfo &DCI) {
21840 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21841 if (NewOp.getNode())
21844 SDValue InputVector = N->getOperand(0);
21846 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21847 // from mmx to v2i32 has a single usage.
21848 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21849 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21850 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21851 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21852 N->getValueType(0),
21853 InputVector.getNode()->getOperand(0));
21855 // Only operate on vectors of 4 elements, where the alternative shuffling
21856 // gets to be more expensive.
21857 if (InputVector.getValueType() != MVT::v4i32)
21860 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21861 // single use which is a sign-extend or zero-extend, and all elements are
21863 SmallVector<SDNode *, 4> Uses;
21864 unsigned ExtractedElements = 0;
21865 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21866 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21867 if (UI.getUse().getResNo() != InputVector.getResNo())
21870 SDNode *Extract = *UI;
21871 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21874 if (Extract->getValueType(0) != MVT::i32)
21876 if (!Extract->hasOneUse())
21878 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21879 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21881 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21884 // Record which element was extracted.
21885 ExtractedElements |=
21886 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21888 Uses.push_back(Extract);
21891 // If not all the elements were used, this may not be worthwhile.
21892 if (ExtractedElements != 15)
21895 // Ok, we've now decided to do the transformation.
21896 SDLoc dl(InputVector);
21898 // Store the value to a temporary stack slot.
21899 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21900 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21901 MachinePointerInfo(), false, false, 0);
21903 // Replace each use (extract) with a load of the appropriate element.
21904 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21905 UE = Uses.end(); UI != UE; ++UI) {
21906 SDNode *Extract = *UI;
21908 // cOMpute the element's address.
21909 SDValue Idx = Extract->getOperand(1);
21911 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21912 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21914 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21916 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21917 StackPtr, OffsetVal);
21919 // Load the scalar.
21920 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21921 ScalarAddr, MachinePointerInfo(),
21922 false, false, false, 0);
21924 // Replace the exact with the load.
21925 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21928 // The replacement was made in place; don't return anything.
21932 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21933 static std::pair<unsigned, bool>
21934 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21935 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21936 if (!VT.isVector())
21937 return std::make_pair(0, false);
21939 bool NeedSplit = false;
21940 switch (VT.getSimpleVT().SimpleTy) {
21941 default: return std::make_pair(0, false);
21945 if (!Subtarget->hasAVX2())
21947 if (!Subtarget->hasAVX())
21948 return std::make_pair(0, false);
21953 if (!Subtarget->hasSSE2())
21954 return std::make_pair(0, false);
21957 // SSE2 has only a small subset of the operations.
21958 bool hasUnsigned = Subtarget->hasSSE41() ||
21959 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21960 bool hasSigned = Subtarget->hasSSE41() ||
21961 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21963 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21966 // Check for x CC y ? x : y.
21967 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21968 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21973 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21976 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21979 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21982 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21984 // Check for x CC y ? y : x -- a min/max with reversed arms.
21985 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21986 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21991 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21994 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21997 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22000 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22004 return std::make_pair(Opc, NeedSplit);
22008 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22009 const X86Subtarget *Subtarget) {
22011 SDValue Cond = N->getOperand(0);
22012 SDValue LHS = N->getOperand(1);
22013 SDValue RHS = N->getOperand(2);
22015 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22016 SDValue CondSrc = Cond->getOperand(0);
22017 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22018 Cond = CondSrc->getOperand(0);
22021 MVT VT = N->getSimpleValueType(0);
22022 MVT EltVT = VT.getVectorElementType();
22023 unsigned NumElems = VT.getVectorNumElements();
22024 // There is no blend with immediate in AVX-512.
22025 if (VT.is512BitVector())
22028 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22030 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22033 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22036 // A vselect where all conditions and data are constants can be optimized into
22037 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22038 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22039 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22042 unsigned MaskValue = 0;
22043 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22046 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22047 for (unsigned i = 0; i < NumElems; ++i) {
22048 // Be sure we emit undef where we can.
22049 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22050 ShuffleMask[i] = -1;
22052 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22055 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22058 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22060 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22061 TargetLowering::DAGCombinerInfo &DCI,
22062 const X86Subtarget *Subtarget) {
22064 SDValue Cond = N->getOperand(0);
22065 // Get the LHS/RHS of the select.
22066 SDValue LHS = N->getOperand(1);
22067 SDValue RHS = N->getOperand(2);
22068 EVT VT = LHS.getValueType();
22069 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22071 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22072 // instructions match the semantics of the common C idiom x<y?x:y but not
22073 // x<=y?x:y, because of how they handle negative zero (which can be
22074 // ignored in unsafe-math mode).
22075 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22076 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22077 (Subtarget->hasSSE2() ||
22078 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22079 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22081 unsigned Opcode = 0;
22082 // Check for x CC y ? x : y.
22083 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22084 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22088 // Converting this to a min would handle NaNs incorrectly, and swapping
22089 // the operands would cause it to handle comparisons between positive
22090 // and negative zero incorrectly.
22091 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22092 if (!DAG.getTarget().Options.UnsafeFPMath &&
22093 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22095 std::swap(LHS, RHS);
22097 Opcode = X86ISD::FMIN;
22100 // Converting this to a min would handle comparisons between positive
22101 // and negative zero incorrectly.
22102 if (!DAG.getTarget().Options.UnsafeFPMath &&
22103 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22105 Opcode = X86ISD::FMIN;
22108 // Converting this to a min would handle both negative zeros and NaNs
22109 // incorrectly, but we can swap the operands to fix both.
22110 std::swap(LHS, RHS);
22114 Opcode = X86ISD::FMIN;
22118 // Converting this to a max would handle comparisons between positive
22119 // and negative zero incorrectly.
22120 if (!DAG.getTarget().Options.UnsafeFPMath &&
22121 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22123 Opcode = X86ISD::FMAX;
22126 // Converting this to a max would handle NaNs incorrectly, and swapping
22127 // the operands would cause it to handle comparisons between positive
22128 // and negative zero incorrectly.
22129 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22130 if (!DAG.getTarget().Options.UnsafeFPMath &&
22131 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22133 std::swap(LHS, RHS);
22135 Opcode = X86ISD::FMAX;
22138 // Converting this to a max would handle both negative zeros and NaNs
22139 // incorrectly, but we can swap the operands to fix both.
22140 std::swap(LHS, RHS);
22144 Opcode = X86ISD::FMAX;
22147 // Check for x CC y ? y : x -- a min/max with reversed arms.
22148 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22149 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22153 // Converting this to a min would handle comparisons between positive
22154 // and negative zero incorrectly, and swapping the operands would
22155 // cause it to handle NaNs incorrectly.
22156 if (!DAG.getTarget().Options.UnsafeFPMath &&
22157 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22158 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22160 std::swap(LHS, RHS);
22162 Opcode = X86ISD::FMIN;
22165 // Converting this to a min would handle NaNs incorrectly.
22166 if (!DAG.getTarget().Options.UnsafeFPMath &&
22167 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22169 Opcode = X86ISD::FMIN;
22172 // Converting this to a min would handle both negative zeros and NaNs
22173 // incorrectly, but we can swap the operands to fix both.
22174 std::swap(LHS, RHS);
22178 Opcode = X86ISD::FMIN;
22182 // Converting this to a max would handle NaNs incorrectly.
22183 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22185 Opcode = X86ISD::FMAX;
22188 // Converting this to a max would handle comparisons between positive
22189 // and negative zero incorrectly, and swapping the operands would
22190 // cause it to handle NaNs incorrectly.
22191 if (!DAG.getTarget().Options.UnsafeFPMath &&
22192 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22193 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22195 std::swap(LHS, RHS);
22197 Opcode = X86ISD::FMAX;
22200 // Converting this to a max would handle both negative zeros and NaNs
22201 // incorrectly, but we can swap the operands to fix both.
22202 std::swap(LHS, RHS);
22206 Opcode = X86ISD::FMAX;
22212 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22215 EVT CondVT = Cond.getValueType();
22216 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22217 CondVT.getVectorElementType() == MVT::i1) {
22218 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22219 // lowering on KNL. In this case we convert it to
22220 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22221 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22222 // Since SKX these selects have a proper lowering.
22223 EVT OpVT = LHS.getValueType();
22224 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22225 (OpVT.getVectorElementType() == MVT::i8 ||
22226 OpVT.getVectorElementType() == MVT::i16) &&
22227 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22228 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22229 DCI.AddToWorklist(Cond.getNode());
22230 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22233 // If this is a select between two integer constants, try to do some
22235 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22236 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22237 // Don't do this for crazy integer types.
22238 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22239 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22240 // so that TrueC (the true value) is larger than FalseC.
22241 bool NeedsCondInvert = false;
22243 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22244 // Efficiently invertible.
22245 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22246 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22247 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22248 NeedsCondInvert = true;
22249 std::swap(TrueC, FalseC);
22252 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22253 if (FalseC->getAPIntValue() == 0 &&
22254 TrueC->getAPIntValue().isPowerOf2()) {
22255 if (NeedsCondInvert) // Invert the condition if needed.
22256 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22257 DAG.getConstant(1, Cond.getValueType()));
22259 // Zero extend the condition if needed.
22260 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22262 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22263 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22264 DAG.getConstant(ShAmt, MVT::i8));
22267 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22268 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22269 if (NeedsCondInvert) // Invert the condition if needed.
22270 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22271 DAG.getConstant(1, Cond.getValueType()));
22273 // Zero extend the condition if needed.
22274 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22275 FalseC->getValueType(0), Cond);
22276 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22277 SDValue(FalseC, 0));
22280 // Optimize cases that will turn into an LEA instruction. This requires
22281 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22282 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22283 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22284 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22286 bool isFastMultiplier = false;
22288 switch ((unsigned char)Diff) {
22290 case 1: // result = add base, cond
22291 case 2: // result = lea base( , cond*2)
22292 case 3: // result = lea base(cond, cond*2)
22293 case 4: // result = lea base( , cond*4)
22294 case 5: // result = lea base(cond, cond*4)
22295 case 8: // result = lea base( , cond*8)
22296 case 9: // result = lea base(cond, cond*8)
22297 isFastMultiplier = true;
22302 if (isFastMultiplier) {
22303 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22304 if (NeedsCondInvert) // Invert the condition if needed.
22305 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22306 DAG.getConstant(1, Cond.getValueType()));
22308 // Zero extend the condition if needed.
22309 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22311 // Scale the condition by the difference.
22313 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22314 DAG.getConstant(Diff, Cond.getValueType()));
22316 // Add the base if non-zero.
22317 if (FalseC->getAPIntValue() != 0)
22318 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22319 SDValue(FalseC, 0));
22326 // Canonicalize max and min:
22327 // (x > y) ? x : y -> (x >= y) ? x : y
22328 // (x < y) ? x : y -> (x <= y) ? x : y
22329 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22330 // the need for an extra compare
22331 // against zero. e.g.
22332 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22334 // testl %edi, %edi
22336 // cmovgl %edi, %eax
22340 // cmovsl %eax, %edi
22341 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22342 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22343 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22344 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22349 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22350 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22351 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22352 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22357 // Early exit check
22358 if (!TLI.isTypeLegal(VT))
22361 // Match VSELECTs into subs with unsigned saturation.
22362 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22363 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22364 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22365 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22366 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22368 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22369 // left side invert the predicate to simplify logic below.
22371 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22373 CC = ISD::getSetCCInverse(CC, true);
22374 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22378 if (Other.getNode() && Other->getNumOperands() == 2 &&
22379 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22380 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22381 SDValue CondRHS = Cond->getOperand(1);
22383 // Look for a general sub with unsigned saturation first.
22384 // x >= y ? x-y : 0 --> subus x, y
22385 // x > y ? x-y : 0 --> subus x, y
22386 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22387 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22388 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22390 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22391 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22392 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22393 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22394 // If the RHS is a constant we have to reverse the const
22395 // canonicalization.
22396 // x > C-1 ? x+-C : 0 --> subus x, C
22397 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22398 CondRHSConst->getAPIntValue() ==
22399 (-OpRHSConst->getAPIntValue() - 1))
22400 return DAG.getNode(
22401 X86ISD::SUBUS, DL, VT, OpLHS,
22402 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22404 // Another special case: If C was a sign bit, the sub has been
22405 // canonicalized into a xor.
22406 // FIXME: Would it be better to use computeKnownBits to determine
22407 // whether it's safe to decanonicalize the xor?
22408 // x s< 0 ? x^C : 0 --> subus x, C
22409 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22410 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22411 OpRHSConst->getAPIntValue().isSignBit())
22412 // Note that we have to rebuild the RHS constant here to ensure we
22413 // don't rely on particular values of undef lanes.
22414 return DAG.getNode(
22415 X86ISD::SUBUS, DL, VT, OpLHS,
22416 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22421 // Try to match a min/max vector operation.
22422 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22423 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22424 unsigned Opc = ret.first;
22425 bool NeedSplit = ret.second;
22427 if (Opc && NeedSplit) {
22428 unsigned NumElems = VT.getVectorNumElements();
22429 // Extract the LHS vectors
22430 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22431 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22433 // Extract the RHS vectors
22434 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22435 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22437 // Create min/max for each subvector
22438 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22439 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22441 // Merge the result
22442 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22444 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22447 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22448 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22449 // Check if SETCC has already been promoted
22450 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22451 // Check that condition value type matches vselect operand type
22454 assert(Cond.getValueType().isVector() &&
22455 "vector select expects a vector selector!");
22457 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22458 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22460 if (!TValIsAllOnes && !FValIsAllZeros) {
22461 // Try invert the condition if true value is not all 1s and false value
22463 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22464 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22466 if (TValIsAllZeros || FValIsAllOnes) {
22467 SDValue CC = Cond.getOperand(2);
22468 ISD::CondCode NewCC =
22469 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22470 Cond.getOperand(0).getValueType().isInteger());
22471 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22472 std::swap(LHS, RHS);
22473 TValIsAllOnes = FValIsAllOnes;
22474 FValIsAllZeros = TValIsAllZeros;
22478 if (TValIsAllOnes || FValIsAllZeros) {
22481 if (TValIsAllOnes && FValIsAllZeros)
22483 else if (TValIsAllOnes)
22484 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22485 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22486 else if (FValIsAllZeros)
22487 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22488 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22490 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22494 // Try to fold this VSELECT into a MOVSS/MOVSD
22495 if (N->getOpcode() == ISD::VSELECT &&
22496 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22497 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22498 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22499 bool CanFold = false;
22500 unsigned NumElems = Cond.getNumOperands();
22504 if (isZero(Cond.getOperand(0))) {
22507 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22508 // fold (vselect <0,-1> -> (movsd A, B)
22509 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22510 CanFold = isAllOnes(Cond.getOperand(i));
22511 } else if (isAllOnes(Cond.getOperand(0))) {
22515 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22516 // fold (vselect <-1,0> -> (movsd B, A)
22517 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22518 CanFold = isZero(Cond.getOperand(i));
22522 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22523 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22524 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22527 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22528 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22529 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22530 // (v2i64 (bitcast B)))))
22532 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22533 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22534 // (v2f64 (bitcast B)))))
22536 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22537 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22538 // (v2i64 (bitcast A)))))
22540 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22541 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22542 // (v2f64 (bitcast A)))))
22544 CanFold = (isZero(Cond.getOperand(0)) &&
22545 isZero(Cond.getOperand(1)) &&
22546 isAllOnes(Cond.getOperand(2)) &&
22547 isAllOnes(Cond.getOperand(3)));
22549 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22550 isAllOnes(Cond.getOperand(1)) &&
22551 isZero(Cond.getOperand(2)) &&
22552 isZero(Cond.getOperand(3))) {
22554 std::swap(LHS, RHS);
22558 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22559 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22560 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22561 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22563 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22569 // If we know that this node is legal then we know that it is going to be
22570 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22571 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22572 // to simplify previous instructions.
22573 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22574 !DCI.isBeforeLegalize() &&
22575 // We explicitly check against v8i16 and v16i16 because, although
22576 // they're marked as Custom, they might only be legal when Cond is a
22577 // build_vector of constants. This will be taken care in a later
22579 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22580 VT != MVT::v8i16)) {
22581 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22583 // Don't optimize vector selects that map to mask-registers.
22587 // Check all uses of that condition operand to check whether it will be
22588 // consumed by non-BLEND instructions, which may depend on all bits are set
22590 for (SDNode::use_iterator I = Cond->use_begin(),
22591 E = Cond->use_end(); I != E; ++I)
22592 if (I->getOpcode() != ISD::VSELECT)
22593 // TODO: Add other opcodes eventually lowered into BLEND.
22596 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22597 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22599 APInt KnownZero, KnownOne;
22600 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22601 DCI.isBeforeLegalizeOps());
22602 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22603 (TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22605 // Don't optimize vector of constants. Those are handled by
22606 // the generic code and all the bits must be properly set for
22607 // the generic optimizer.
22608 !ISD::isBuildVectorOfConstantSDNodes(TLO.New.getNode())))
22609 DCI.CommitTargetLoweringOpt(TLO);
22612 // We should generate an X86ISD::BLENDI from a vselect if its argument
22613 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22614 // constants. This specific pattern gets generated when we split a
22615 // selector for a 512 bit vector in a machine without AVX512 (but with
22616 // 256-bit vectors), during legalization:
22618 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22620 // Iff we find this pattern and the build_vectors are built from
22621 // constants, we translate the vselect into a shuffle_vector that we
22622 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22623 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22624 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22625 if (Shuffle.getNode())
22632 // Check whether a boolean test is testing a boolean value generated by
22633 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22636 // Simplify the following patterns:
22637 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22638 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22639 // to (Op EFLAGS Cond)
22641 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22642 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22643 // to (Op EFLAGS !Cond)
22645 // where Op could be BRCOND or CMOV.
22647 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22648 // Quit if not CMP and SUB with its value result used.
22649 if (Cmp.getOpcode() != X86ISD::CMP &&
22650 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22653 // Quit if not used as a boolean value.
22654 if (CC != X86::COND_E && CC != X86::COND_NE)
22657 // Check CMP operands. One of them should be 0 or 1 and the other should be
22658 // an SetCC or extended from it.
22659 SDValue Op1 = Cmp.getOperand(0);
22660 SDValue Op2 = Cmp.getOperand(1);
22663 const ConstantSDNode* C = nullptr;
22664 bool needOppositeCond = (CC == X86::COND_E);
22665 bool checkAgainstTrue = false; // Is it a comparison against 1?
22667 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22669 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22671 else // Quit if all operands are not constants.
22674 if (C->getZExtValue() == 1) {
22675 needOppositeCond = !needOppositeCond;
22676 checkAgainstTrue = true;
22677 } else if (C->getZExtValue() != 0)
22678 // Quit if the constant is neither 0 or 1.
22681 bool truncatedToBoolWithAnd = false;
22682 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22683 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22684 SetCC.getOpcode() == ISD::TRUNCATE ||
22685 SetCC.getOpcode() == ISD::AND) {
22686 if (SetCC.getOpcode() == ISD::AND) {
22688 ConstantSDNode *CS;
22689 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22690 CS->getZExtValue() == 1)
22692 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22693 CS->getZExtValue() == 1)
22697 SetCC = SetCC.getOperand(OpIdx);
22698 truncatedToBoolWithAnd = true;
22700 SetCC = SetCC.getOperand(0);
22703 switch (SetCC.getOpcode()) {
22704 case X86ISD::SETCC_CARRY:
22705 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22706 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22707 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22708 // truncated to i1 using 'and'.
22709 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22711 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22712 "Invalid use of SETCC_CARRY!");
22714 case X86ISD::SETCC:
22715 // Set the condition code or opposite one if necessary.
22716 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22717 if (needOppositeCond)
22718 CC = X86::GetOppositeBranchCondition(CC);
22719 return SetCC.getOperand(1);
22720 case X86ISD::CMOV: {
22721 // Check whether false/true value has canonical one, i.e. 0 or 1.
22722 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22723 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22724 // Quit if true value is not a constant.
22727 // Quit if false value is not a constant.
22729 SDValue Op = SetCC.getOperand(0);
22730 // Skip 'zext' or 'trunc' node.
22731 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22732 Op.getOpcode() == ISD::TRUNCATE)
22733 Op = Op.getOperand(0);
22734 // A special case for rdrand/rdseed, where 0 is set if false cond is
22736 if ((Op.getOpcode() != X86ISD::RDRAND &&
22737 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22740 // Quit if false value is not the constant 0 or 1.
22741 bool FValIsFalse = true;
22742 if (FVal && FVal->getZExtValue() != 0) {
22743 if (FVal->getZExtValue() != 1)
22745 // If FVal is 1, opposite cond is needed.
22746 needOppositeCond = !needOppositeCond;
22747 FValIsFalse = false;
22749 // Quit if TVal is not the constant opposite of FVal.
22750 if (FValIsFalse && TVal->getZExtValue() != 1)
22752 if (!FValIsFalse && TVal->getZExtValue() != 0)
22754 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22755 if (needOppositeCond)
22756 CC = X86::GetOppositeBranchCondition(CC);
22757 return SetCC.getOperand(3);
22764 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22765 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22766 TargetLowering::DAGCombinerInfo &DCI,
22767 const X86Subtarget *Subtarget) {
22770 // If the flag operand isn't dead, don't touch this CMOV.
22771 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22774 SDValue FalseOp = N->getOperand(0);
22775 SDValue TrueOp = N->getOperand(1);
22776 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22777 SDValue Cond = N->getOperand(3);
22779 if (CC == X86::COND_E || CC == X86::COND_NE) {
22780 switch (Cond.getOpcode()) {
22784 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22785 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22786 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22792 Flags = checkBoolTestSetCCCombine(Cond, CC);
22793 if (Flags.getNode() &&
22794 // Extra check as FCMOV only supports a subset of X86 cond.
22795 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22796 SDValue Ops[] = { FalseOp, TrueOp,
22797 DAG.getConstant(CC, MVT::i8), Flags };
22798 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22801 // If this is a select between two integer constants, try to do some
22802 // optimizations. Note that the operands are ordered the opposite of SELECT
22804 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22805 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22806 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22807 // larger than FalseC (the false value).
22808 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22809 CC = X86::GetOppositeBranchCondition(CC);
22810 std::swap(TrueC, FalseC);
22811 std::swap(TrueOp, FalseOp);
22814 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22815 // This is efficient for any integer data type (including i8/i16) and
22817 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22818 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22819 DAG.getConstant(CC, MVT::i8), Cond);
22821 // Zero extend the condition if needed.
22822 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22824 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22825 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22826 DAG.getConstant(ShAmt, MVT::i8));
22827 if (N->getNumValues() == 2) // Dead flag value?
22828 return DCI.CombineTo(N, Cond, SDValue());
22832 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22833 // for any integer data type, including i8/i16.
22834 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22835 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22836 DAG.getConstant(CC, MVT::i8), Cond);
22838 // Zero extend the condition if needed.
22839 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22840 FalseC->getValueType(0), Cond);
22841 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22842 SDValue(FalseC, 0));
22844 if (N->getNumValues() == 2) // Dead flag value?
22845 return DCI.CombineTo(N, Cond, SDValue());
22849 // Optimize cases that will turn into an LEA instruction. This requires
22850 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22851 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22852 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22853 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22855 bool isFastMultiplier = false;
22857 switch ((unsigned char)Diff) {
22859 case 1: // result = add base, cond
22860 case 2: // result = lea base( , cond*2)
22861 case 3: // result = lea base(cond, cond*2)
22862 case 4: // result = lea base( , cond*4)
22863 case 5: // result = lea base(cond, cond*4)
22864 case 8: // result = lea base( , cond*8)
22865 case 9: // result = lea base(cond, cond*8)
22866 isFastMultiplier = true;
22871 if (isFastMultiplier) {
22872 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22873 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22874 DAG.getConstant(CC, MVT::i8), Cond);
22875 // Zero extend the condition if needed.
22876 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22878 // Scale the condition by the difference.
22880 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22881 DAG.getConstant(Diff, Cond.getValueType()));
22883 // Add the base if non-zero.
22884 if (FalseC->getAPIntValue() != 0)
22885 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22886 SDValue(FalseC, 0));
22887 if (N->getNumValues() == 2) // Dead flag value?
22888 return DCI.CombineTo(N, Cond, SDValue());
22895 // Handle these cases:
22896 // (select (x != c), e, c) -> select (x != c), e, x),
22897 // (select (x == c), c, e) -> select (x == c), x, e)
22898 // where the c is an integer constant, and the "select" is the combination
22899 // of CMOV and CMP.
22901 // The rationale for this change is that the conditional-move from a constant
22902 // needs two instructions, however, conditional-move from a register needs
22903 // only one instruction.
22905 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22906 // some instruction-combining opportunities. This opt needs to be
22907 // postponed as late as possible.
22909 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22910 // the DCI.xxxx conditions are provided to postpone the optimization as
22911 // late as possible.
22913 ConstantSDNode *CmpAgainst = nullptr;
22914 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22915 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22916 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22918 if (CC == X86::COND_NE &&
22919 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22920 CC = X86::GetOppositeBranchCondition(CC);
22921 std::swap(TrueOp, FalseOp);
22924 if (CC == X86::COND_E &&
22925 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22926 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22927 DAG.getConstant(CC, MVT::i8), Cond };
22928 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22936 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22937 const X86Subtarget *Subtarget) {
22938 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22940 default: return SDValue();
22941 // SSE/AVX/AVX2 blend intrinsics.
22942 case Intrinsic::x86_avx2_pblendvb:
22943 case Intrinsic::x86_avx2_pblendw:
22944 case Intrinsic::x86_avx2_pblendd_128:
22945 case Intrinsic::x86_avx2_pblendd_256:
22946 // Don't try to simplify this intrinsic if we don't have AVX2.
22947 if (!Subtarget->hasAVX2())
22950 case Intrinsic::x86_avx_blend_pd_256:
22951 case Intrinsic::x86_avx_blend_ps_256:
22952 case Intrinsic::x86_avx_blendv_pd_256:
22953 case Intrinsic::x86_avx_blendv_ps_256:
22954 // Don't try to simplify this intrinsic if we don't have AVX.
22955 if (!Subtarget->hasAVX())
22958 case Intrinsic::x86_sse41_pblendw:
22959 case Intrinsic::x86_sse41_blendpd:
22960 case Intrinsic::x86_sse41_blendps:
22961 case Intrinsic::x86_sse41_blendvps:
22962 case Intrinsic::x86_sse41_blendvpd:
22963 case Intrinsic::x86_sse41_pblendvb: {
22964 SDValue Op0 = N->getOperand(1);
22965 SDValue Op1 = N->getOperand(2);
22966 SDValue Mask = N->getOperand(3);
22968 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22969 if (!Subtarget->hasSSE41())
22972 // fold (blend A, A, Mask) -> A
22975 // fold (blend A, B, allZeros) -> A
22976 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22978 // fold (blend A, B, allOnes) -> B
22979 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22982 // Simplify the case where the mask is a constant i32 value.
22983 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22984 if (C->isNullValue())
22986 if (C->isAllOnesValue())
22993 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22994 case Intrinsic::x86_sse2_psrai_w:
22995 case Intrinsic::x86_sse2_psrai_d:
22996 case Intrinsic::x86_avx2_psrai_w:
22997 case Intrinsic::x86_avx2_psrai_d:
22998 case Intrinsic::x86_sse2_psra_w:
22999 case Intrinsic::x86_sse2_psra_d:
23000 case Intrinsic::x86_avx2_psra_w:
23001 case Intrinsic::x86_avx2_psra_d: {
23002 SDValue Op0 = N->getOperand(1);
23003 SDValue Op1 = N->getOperand(2);
23004 EVT VT = Op0.getValueType();
23005 assert(VT.isVector() && "Expected a vector type!");
23007 if (isa<BuildVectorSDNode>(Op1))
23008 Op1 = Op1.getOperand(0);
23010 if (!isa<ConstantSDNode>(Op1))
23013 EVT SVT = VT.getVectorElementType();
23014 unsigned SVTBits = SVT.getSizeInBits();
23016 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23017 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23018 uint64_t ShAmt = C.getZExtValue();
23020 // Don't try to convert this shift into a ISD::SRA if the shift
23021 // count is bigger than or equal to the element size.
23022 if (ShAmt >= SVTBits)
23025 // Trivial case: if the shift count is zero, then fold this
23026 // into the first operand.
23030 // Replace this packed shift intrinsic with a target independent
23032 SDValue Splat = DAG.getConstant(C, VT);
23033 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23038 /// PerformMulCombine - Optimize a single multiply with constant into two
23039 /// in order to implement it with two cheaper instructions, e.g.
23040 /// LEA + SHL, LEA + LEA.
23041 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23042 TargetLowering::DAGCombinerInfo &DCI) {
23043 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23046 EVT VT = N->getValueType(0);
23047 if (VT != MVT::i64)
23050 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23053 uint64_t MulAmt = C->getZExtValue();
23054 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23057 uint64_t MulAmt1 = 0;
23058 uint64_t MulAmt2 = 0;
23059 if ((MulAmt % 9) == 0) {
23061 MulAmt2 = MulAmt / 9;
23062 } else if ((MulAmt % 5) == 0) {
23064 MulAmt2 = MulAmt / 5;
23065 } else if ((MulAmt % 3) == 0) {
23067 MulAmt2 = MulAmt / 3;
23070 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23073 if (isPowerOf2_64(MulAmt2) &&
23074 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23075 // If second multiplifer is pow2, issue it first. We want the multiply by
23076 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23078 std::swap(MulAmt1, MulAmt2);
23081 if (isPowerOf2_64(MulAmt1))
23082 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23083 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23085 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23086 DAG.getConstant(MulAmt1, VT));
23088 if (isPowerOf2_64(MulAmt2))
23089 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23090 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23092 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23093 DAG.getConstant(MulAmt2, VT));
23095 // Do not add new nodes to DAG combiner worklist.
23096 DCI.CombineTo(N, NewMul, false);
23101 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23102 SDValue N0 = N->getOperand(0);
23103 SDValue N1 = N->getOperand(1);
23104 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23105 EVT VT = N0.getValueType();
23107 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23108 // since the result of setcc_c is all zero's or all ones.
23109 if (VT.isInteger() && !VT.isVector() &&
23110 N1C && N0.getOpcode() == ISD::AND &&
23111 N0.getOperand(1).getOpcode() == ISD::Constant) {
23112 SDValue N00 = N0.getOperand(0);
23113 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23114 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23115 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23116 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23117 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23118 APInt ShAmt = N1C->getAPIntValue();
23119 Mask = Mask.shl(ShAmt);
23121 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23122 N00, DAG.getConstant(Mask, VT));
23126 // Hardware support for vector shifts is sparse which makes us scalarize the
23127 // vector operations in many cases. Also, on sandybridge ADD is faster than
23129 // (shl V, 1) -> add V,V
23130 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23131 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23132 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23133 // We shift all of the values by one. In many cases we do not have
23134 // hardware support for this operation. This is better expressed as an ADD
23136 if (N1SplatC->getZExtValue() == 1)
23137 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23143 /// \brief Returns a vector of 0s if the node in input is a vector logical
23144 /// shift by a constant amount which is known to be bigger than or equal
23145 /// to the vector element size in bits.
23146 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23147 const X86Subtarget *Subtarget) {
23148 EVT VT = N->getValueType(0);
23150 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23151 (!Subtarget->hasInt256() ||
23152 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23155 SDValue Amt = N->getOperand(1);
23157 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23158 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23159 APInt ShiftAmt = AmtSplat->getAPIntValue();
23160 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23162 // SSE2/AVX2 logical shifts always return a vector of 0s
23163 // if the shift amount is bigger than or equal to
23164 // the element size. The constant shift amount will be
23165 // encoded as a 8-bit immediate.
23166 if (ShiftAmt.trunc(8).uge(MaxAmount))
23167 return getZeroVector(VT, Subtarget, DAG, DL);
23173 /// PerformShiftCombine - Combine shifts.
23174 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23175 TargetLowering::DAGCombinerInfo &DCI,
23176 const X86Subtarget *Subtarget) {
23177 if (N->getOpcode() == ISD::SHL) {
23178 SDValue V = PerformSHLCombine(N, DAG);
23179 if (V.getNode()) return V;
23182 if (N->getOpcode() != ISD::SRA) {
23183 // Try to fold this logical shift into a zero vector.
23184 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23185 if (V.getNode()) return V;
23191 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23192 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23193 // and friends. Likewise for OR -> CMPNEQSS.
23194 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23195 TargetLowering::DAGCombinerInfo &DCI,
23196 const X86Subtarget *Subtarget) {
23199 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23200 // we're requiring SSE2 for both.
23201 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23202 SDValue N0 = N->getOperand(0);
23203 SDValue N1 = N->getOperand(1);
23204 SDValue CMP0 = N0->getOperand(1);
23205 SDValue CMP1 = N1->getOperand(1);
23208 // The SETCCs should both refer to the same CMP.
23209 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23212 SDValue CMP00 = CMP0->getOperand(0);
23213 SDValue CMP01 = CMP0->getOperand(1);
23214 EVT VT = CMP00.getValueType();
23216 if (VT == MVT::f32 || VT == MVT::f64) {
23217 bool ExpectingFlags = false;
23218 // Check for any users that want flags:
23219 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23220 !ExpectingFlags && UI != UE; ++UI)
23221 switch (UI->getOpcode()) {
23226 ExpectingFlags = true;
23228 case ISD::CopyToReg:
23229 case ISD::SIGN_EXTEND:
23230 case ISD::ZERO_EXTEND:
23231 case ISD::ANY_EXTEND:
23235 if (!ExpectingFlags) {
23236 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23237 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23239 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23240 X86::CondCode tmp = cc0;
23245 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23246 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23247 // FIXME: need symbolic constants for these magic numbers.
23248 // See X86ATTInstPrinter.cpp:printSSECC().
23249 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23250 if (Subtarget->hasAVX512()) {
23251 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23252 CMP01, DAG.getConstant(x86cc, MVT::i8));
23253 if (N->getValueType(0) != MVT::i1)
23254 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23258 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23259 CMP00.getValueType(), CMP00, CMP01,
23260 DAG.getConstant(x86cc, MVT::i8));
23262 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23263 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23265 if (is64BitFP && !Subtarget->is64Bit()) {
23266 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23267 // 64-bit integer, since that's not a legal type. Since
23268 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23269 // bits, but can do this little dance to extract the lowest 32 bits
23270 // and work with those going forward.
23271 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23273 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23275 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23276 Vector32, DAG.getIntPtrConstant(0));
23280 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23281 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23282 DAG.getConstant(1, IntVT));
23283 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23284 return OneBitOfTruth;
23292 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23293 /// so it can be folded inside ANDNP.
23294 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23295 EVT VT = N->getValueType(0);
23297 // Match direct AllOnes for 128 and 256-bit vectors
23298 if (ISD::isBuildVectorAllOnes(N))
23301 // Look through a bit convert.
23302 if (N->getOpcode() == ISD::BITCAST)
23303 N = N->getOperand(0).getNode();
23305 // Sometimes the operand may come from a insert_subvector building a 256-bit
23307 if (VT.is256BitVector() &&
23308 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23309 SDValue V1 = N->getOperand(0);
23310 SDValue V2 = N->getOperand(1);
23312 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23313 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23314 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23315 ISD::isBuildVectorAllOnes(V2.getNode()))
23322 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23323 // register. In most cases we actually compare or select YMM-sized registers
23324 // and mixing the two types creates horrible code. This method optimizes
23325 // some of the transition sequences.
23326 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23327 TargetLowering::DAGCombinerInfo &DCI,
23328 const X86Subtarget *Subtarget) {
23329 EVT VT = N->getValueType(0);
23330 if (!VT.is256BitVector())
23333 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23334 N->getOpcode() == ISD::ZERO_EXTEND ||
23335 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23337 SDValue Narrow = N->getOperand(0);
23338 EVT NarrowVT = Narrow->getValueType(0);
23339 if (!NarrowVT.is128BitVector())
23342 if (Narrow->getOpcode() != ISD::XOR &&
23343 Narrow->getOpcode() != ISD::AND &&
23344 Narrow->getOpcode() != ISD::OR)
23347 SDValue N0 = Narrow->getOperand(0);
23348 SDValue N1 = Narrow->getOperand(1);
23351 // The Left side has to be a trunc.
23352 if (N0.getOpcode() != ISD::TRUNCATE)
23355 // The type of the truncated inputs.
23356 EVT WideVT = N0->getOperand(0)->getValueType(0);
23360 // The right side has to be a 'trunc' or a constant vector.
23361 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23362 ConstantSDNode *RHSConstSplat = nullptr;
23363 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23364 RHSConstSplat = RHSBV->getConstantSplatNode();
23365 if (!RHSTrunc && !RHSConstSplat)
23368 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23370 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23373 // Set N0 and N1 to hold the inputs to the new wide operation.
23374 N0 = N0->getOperand(0);
23375 if (RHSConstSplat) {
23376 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23377 SDValue(RHSConstSplat, 0));
23378 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23379 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23380 } else if (RHSTrunc) {
23381 N1 = N1->getOperand(0);
23384 // Generate the wide operation.
23385 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23386 unsigned Opcode = N->getOpcode();
23388 case ISD::ANY_EXTEND:
23390 case ISD::ZERO_EXTEND: {
23391 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23392 APInt Mask = APInt::getAllOnesValue(InBits);
23393 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23394 return DAG.getNode(ISD::AND, DL, VT,
23395 Op, DAG.getConstant(Mask, VT));
23397 case ISD::SIGN_EXTEND:
23398 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23399 Op, DAG.getValueType(NarrowVT));
23401 llvm_unreachable("Unexpected opcode");
23405 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23406 TargetLowering::DAGCombinerInfo &DCI,
23407 const X86Subtarget *Subtarget) {
23408 EVT VT = N->getValueType(0);
23409 if (DCI.isBeforeLegalizeOps())
23412 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23416 // Create BEXTR instructions
23417 // BEXTR is ((X >> imm) & (2**size-1))
23418 if (VT == MVT::i32 || VT == MVT::i64) {
23419 SDValue N0 = N->getOperand(0);
23420 SDValue N1 = N->getOperand(1);
23423 // Check for BEXTR.
23424 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23425 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23426 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23427 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23428 if (MaskNode && ShiftNode) {
23429 uint64_t Mask = MaskNode->getZExtValue();
23430 uint64_t Shift = ShiftNode->getZExtValue();
23431 if (isMask_64(Mask)) {
23432 uint64_t MaskSize = CountPopulation_64(Mask);
23433 if (Shift + MaskSize <= VT.getSizeInBits())
23434 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23435 DAG.getConstant(Shift | (MaskSize << 8), VT));
23443 // Want to form ANDNP nodes:
23444 // 1) In the hopes of then easily combining them with OR and AND nodes
23445 // to form PBLEND/PSIGN.
23446 // 2) To match ANDN packed intrinsics
23447 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23450 SDValue N0 = N->getOperand(0);
23451 SDValue N1 = N->getOperand(1);
23454 // Check LHS for vnot
23455 if (N0.getOpcode() == ISD::XOR &&
23456 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23457 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23458 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23460 // Check RHS for vnot
23461 if (N1.getOpcode() == ISD::XOR &&
23462 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23463 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23464 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23469 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23470 TargetLowering::DAGCombinerInfo &DCI,
23471 const X86Subtarget *Subtarget) {
23472 if (DCI.isBeforeLegalizeOps())
23475 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23479 SDValue N0 = N->getOperand(0);
23480 SDValue N1 = N->getOperand(1);
23481 EVT VT = N->getValueType(0);
23483 // look for psign/blend
23484 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23485 if (!Subtarget->hasSSSE3() ||
23486 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23489 // Canonicalize pandn to RHS
23490 if (N0.getOpcode() == X86ISD::ANDNP)
23492 // or (and (m, y), (pandn m, x))
23493 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23494 SDValue Mask = N1.getOperand(0);
23495 SDValue X = N1.getOperand(1);
23497 if (N0.getOperand(0) == Mask)
23498 Y = N0.getOperand(1);
23499 if (N0.getOperand(1) == Mask)
23500 Y = N0.getOperand(0);
23502 // Check to see if the mask appeared in both the AND and ANDNP and
23506 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23507 // Look through mask bitcast.
23508 if (Mask.getOpcode() == ISD::BITCAST)
23509 Mask = Mask.getOperand(0);
23510 if (X.getOpcode() == ISD::BITCAST)
23511 X = X.getOperand(0);
23512 if (Y.getOpcode() == ISD::BITCAST)
23513 Y = Y.getOperand(0);
23515 EVT MaskVT = Mask.getValueType();
23517 // Validate that the Mask operand is a vector sra node.
23518 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23519 // there is no psrai.b
23520 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23521 unsigned SraAmt = ~0;
23522 if (Mask.getOpcode() == ISD::SRA) {
23523 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23524 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23525 SraAmt = AmtConst->getZExtValue();
23526 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23527 SDValue SraC = Mask.getOperand(1);
23528 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23530 if ((SraAmt + 1) != EltBits)
23535 // Now we know we at least have a plendvb with the mask val. See if
23536 // we can form a psignb/w/d.
23537 // psign = x.type == y.type == mask.type && y = sub(0, x);
23538 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23539 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23540 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23541 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23542 "Unsupported VT for PSIGN");
23543 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23544 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23546 // PBLENDVB only available on SSE 4.1
23547 if (!Subtarget->hasSSE41())
23550 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23552 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23553 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23554 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23555 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23556 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23560 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23563 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23564 MachineFunction &MF = DAG.getMachineFunction();
23565 bool OptForSize = MF.getFunction()->getAttributes().
23566 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23568 // SHLD/SHRD instructions have lower register pressure, but on some
23569 // platforms they have higher latency than the equivalent
23570 // series of shifts/or that would otherwise be generated.
23571 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23572 // have higher latencies and we are not optimizing for size.
23573 if (!OptForSize && Subtarget->isSHLDSlow())
23576 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23578 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23580 if (!N0.hasOneUse() || !N1.hasOneUse())
23583 SDValue ShAmt0 = N0.getOperand(1);
23584 if (ShAmt0.getValueType() != MVT::i8)
23586 SDValue ShAmt1 = N1.getOperand(1);
23587 if (ShAmt1.getValueType() != MVT::i8)
23589 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23590 ShAmt0 = ShAmt0.getOperand(0);
23591 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23592 ShAmt1 = ShAmt1.getOperand(0);
23595 unsigned Opc = X86ISD::SHLD;
23596 SDValue Op0 = N0.getOperand(0);
23597 SDValue Op1 = N1.getOperand(0);
23598 if (ShAmt0.getOpcode() == ISD::SUB) {
23599 Opc = X86ISD::SHRD;
23600 std::swap(Op0, Op1);
23601 std::swap(ShAmt0, ShAmt1);
23604 unsigned Bits = VT.getSizeInBits();
23605 if (ShAmt1.getOpcode() == ISD::SUB) {
23606 SDValue Sum = ShAmt1.getOperand(0);
23607 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23608 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23609 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23610 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23611 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23612 return DAG.getNode(Opc, DL, VT,
23614 DAG.getNode(ISD::TRUNCATE, DL,
23617 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23618 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23620 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23621 return DAG.getNode(Opc, DL, VT,
23622 N0.getOperand(0), N1.getOperand(0),
23623 DAG.getNode(ISD::TRUNCATE, DL,
23630 // Generate NEG and CMOV for integer abs.
23631 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23632 EVT VT = N->getValueType(0);
23634 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23635 // 8-bit integer abs to NEG and CMOV.
23636 if (VT.isInteger() && VT.getSizeInBits() == 8)
23639 SDValue N0 = N->getOperand(0);
23640 SDValue N1 = N->getOperand(1);
23643 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23644 // and change it to SUB and CMOV.
23645 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23646 N0.getOpcode() == ISD::ADD &&
23647 N0.getOperand(1) == N1 &&
23648 N1.getOpcode() == ISD::SRA &&
23649 N1.getOperand(0) == N0.getOperand(0))
23650 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23651 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23652 // Generate SUB & CMOV.
23653 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23654 DAG.getConstant(0, VT), N0.getOperand(0));
23656 SDValue Ops[] = { N0.getOperand(0), Neg,
23657 DAG.getConstant(X86::COND_GE, MVT::i8),
23658 SDValue(Neg.getNode(), 1) };
23659 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23664 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23665 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23666 TargetLowering::DAGCombinerInfo &DCI,
23667 const X86Subtarget *Subtarget) {
23668 if (DCI.isBeforeLegalizeOps())
23671 if (Subtarget->hasCMov()) {
23672 SDValue RV = performIntegerAbsCombine(N, DAG);
23680 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23681 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23682 TargetLowering::DAGCombinerInfo &DCI,
23683 const X86Subtarget *Subtarget) {
23684 LoadSDNode *Ld = cast<LoadSDNode>(N);
23685 EVT RegVT = Ld->getValueType(0);
23686 EVT MemVT = Ld->getMemoryVT();
23688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23690 // On Sandybridge unaligned 256bit loads are inefficient.
23691 ISD::LoadExtType Ext = Ld->getExtensionType();
23692 unsigned Alignment = Ld->getAlignment();
23693 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23694 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23695 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23696 unsigned NumElems = RegVT.getVectorNumElements();
23700 SDValue Ptr = Ld->getBasePtr();
23701 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23703 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23705 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23706 Ld->getPointerInfo(), Ld->isVolatile(),
23707 Ld->isNonTemporal(), Ld->isInvariant(),
23709 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23710 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23711 Ld->getPointerInfo(), Ld->isVolatile(),
23712 Ld->isNonTemporal(), Ld->isInvariant(),
23713 std::min(16U, Alignment));
23714 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23716 Load2.getValue(1));
23718 SDValue NewVec = DAG.getUNDEF(RegVT);
23719 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23720 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23721 return DCI.CombineTo(N, NewVec, TF, true);
23727 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23728 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23729 const X86Subtarget *Subtarget) {
23730 StoreSDNode *St = cast<StoreSDNode>(N);
23731 EVT VT = St->getValue().getValueType();
23732 EVT StVT = St->getMemoryVT();
23734 SDValue StoredVal = St->getOperand(1);
23735 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23737 // If we are saving a concatenation of two XMM registers, perform two stores.
23738 // On Sandy Bridge, 256-bit memory operations are executed by two
23739 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23740 // memory operation.
23741 unsigned Alignment = St->getAlignment();
23742 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23743 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23744 StVT == VT && !IsAligned) {
23745 unsigned NumElems = VT.getVectorNumElements();
23749 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23750 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23752 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23753 SDValue Ptr0 = St->getBasePtr();
23754 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23756 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23757 St->getPointerInfo(), St->isVolatile(),
23758 St->isNonTemporal(), Alignment);
23759 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23760 St->getPointerInfo(), St->isVolatile(),
23761 St->isNonTemporal(),
23762 std::min(16U, Alignment));
23763 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23766 // Optimize trunc store (of multiple scalars) to shuffle and store.
23767 // First, pack all of the elements in one place. Next, store to memory
23768 // in fewer chunks.
23769 if (St->isTruncatingStore() && VT.isVector()) {
23770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23771 unsigned NumElems = VT.getVectorNumElements();
23772 assert(StVT != VT && "Cannot truncate to the same type");
23773 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23774 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23776 // From, To sizes and ElemCount must be pow of two
23777 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23778 // We are going to use the original vector elt for storing.
23779 // Accumulated smaller vector elements must be a multiple of the store size.
23780 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23782 unsigned SizeRatio = FromSz / ToSz;
23784 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23786 // Create a type on which we perform the shuffle
23787 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23788 StVT.getScalarType(), NumElems*SizeRatio);
23790 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23792 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23793 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23794 for (unsigned i = 0; i != NumElems; ++i)
23795 ShuffleVec[i] = i * SizeRatio;
23797 // Can't shuffle using an illegal type.
23798 if (!TLI.isTypeLegal(WideVecVT))
23801 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23802 DAG.getUNDEF(WideVecVT),
23804 // At this point all of the data is stored at the bottom of the
23805 // register. We now need to save it to mem.
23807 // Find the largest store unit
23808 MVT StoreType = MVT::i8;
23809 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23810 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23811 MVT Tp = (MVT::SimpleValueType)tp;
23812 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23816 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23817 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23818 (64 <= NumElems * ToSz))
23819 StoreType = MVT::f64;
23821 // Bitcast the original vector into a vector of store-size units
23822 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23823 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23824 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23825 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23826 SmallVector<SDValue, 8> Chains;
23827 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23828 TLI.getPointerTy());
23829 SDValue Ptr = St->getBasePtr();
23831 // Perform one or more big stores into memory.
23832 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23833 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23834 StoreType, ShuffWide,
23835 DAG.getIntPtrConstant(i));
23836 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23837 St->getPointerInfo(), St->isVolatile(),
23838 St->isNonTemporal(), St->getAlignment());
23839 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23840 Chains.push_back(Ch);
23843 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23846 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23847 // the FP state in cases where an emms may be missing.
23848 // A preferable solution to the general problem is to figure out the right
23849 // places to insert EMMS. This qualifies as a quick hack.
23851 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23852 if (VT.getSizeInBits() != 64)
23855 const Function *F = DAG.getMachineFunction().getFunction();
23856 bool NoImplicitFloatOps = F->getAttributes().
23857 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23858 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23859 && Subtarget->hasSSE2();
23860 if ((VT.isVector() ||
23861 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23862 isa<LoadSDNode>(St->getValue()) &&
23863 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23864 St->getChain().hasOneUse() && !St->isVolatile()) {
23865 SDNode* LdVal = St->getValue().getNode();
23866 LoadSDNode *Ld = nullptr;
23867 int TokenFactorIndex = -1;
23868 SmallVector<SDValue, 8> Ops;
23869 SDNode* ChainVal = St->getChain().getNode();
23870 // Must be a store of a load. We currently handle two cases: the load
23871 // is a direct child, and it's under an intervening TokenFactor. It is
23872 // possible to dig deeper under nested TokenFactors.
23873 if (ChainVal == LdVal)
23874 Ld = cast<LoadSDNode>(St->getChain());
23875 else if (St->getValue().hasOneUse() &&
23876 ChainVal->getOpcode() == ISD::TokenFactor) {
23877 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23878 if (ChainVal->getOperand(i).getNode() == LdVal) {
23879 TokenFactorIndex = i;
23880 Ld = cast<LoadSDNode>(St->getValue());
23882 Ops.push_back(ChainVal->getOperand(i));
23886 if (!Ld || !ISD::isNormalLoad(Ld))
23889 // If this is not the MMX case, i.e. we are just turning i64 load/store
23890 // into f64 load/store, avoid the transformation if there are multiple
23891 // uses of the loaded value.
23892 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23897 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23898 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23900 if (Subtarget->is64Bit() || F64IsLegal) {
23901 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23902 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23903 Ld->getPointerInfo(), Ld->isVolatile(),
23904 Ld->isNonTemporal(), Ld->isInvariant(),
23905 Ld->getAlignment());
23906 SDValue NewChain = NewLd.getValue(1);
23907 if (TokenFactorIndex != -1) {
23908 Ops.push_back(NewChain);
23909 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23911 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23912 St->getPointerInfo(),
23913 St->isVolatile(), St->isNonTemporal(),
23914 St->getAlignment());
23917 // Otherwise, lower to two pairs of 32-bit loads / stores.
23918 SDValue LoAddr = Ld->getBasePtr();
23919 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23920 DAG.getConstant(4, MVT::i32));
23922 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23923 Ld->getPointerInfo(),
23924 Ld->isVolatile(), Ld->isNonTemporal(),
23925 Ld->isInvariant(), Ld->getAlignment());
23926 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23927 Ld->getPointerInfo().getWithOffset(4),
23928 Ld->isVolatile(), Ld->isNonTemporal(),
23930 MinAlign(Ld->getAlignment(), 4));
23932 SDValue NewChain = LoLd.getValue(1);
23933 if (TokenFactorIndex != -1) {
23934 Ops.push_back(LoLd);
23935 Ops.push_back(HiLd);
23936 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23939 LoAddr = St->getBasePtr();
23940 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23941 DAG.getConstant(4, MVT::i32));
23943 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23944 St->getPointerInfo(),
23945 St->isVolatile(), St->isNonTemporal(),
23946 St->getAlignment());
23947 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23948 St->getPointerInfo().getWithOffset(4),
23950 St->isNonTemporal(),
23951 MinAlign(St->getAlignment(), 4));
23952 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23957 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23958 /// and return the operands for the horizontal operation in LHS and RHS. A
23959 /// horizontal operation performs the binary operation on successive elements
23960 /// of its first operand, then on successive elements of its second operand,
23961 /// returning the resulting values in a vector. For example, if
23962 /// A = < float a0, float a1, float a2, float a3 >
23964 /// B = < float b0, float b1, float b2, float b3 >
23965 /// then the result of doing a horizontal operation on A and B is
23966 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23967 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23968 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23969 /// set to A, RHS to B, and the routine returns 'true'.
23970 /// Note that the binary operation should have the property that if one of the
23971 /// operands is UNDEF then the result is UNDEF.
23972 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23973 // Look for the following pattern: if
23974 // A = < float a0, float a1, float a2, float a3 >
23975 // B = < float b0, float b1, float b2, float b3 >
23977 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23978 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23979 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23980 // which is A horizontal-op B.
23982 // At least one of the operands should be a vector shuffle.
23983 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23984 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23987 MVT VT = LHS.getSimpleValueType();
23989 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23990 "Unsupported vector type for horizontal add/sub");
23992 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23993 // operate independently on 128-bit lanes.
23994 unsigned NumElts = VT.getVectorNumElements();
23995 unsigned NumLanes = VT.getSizeInBits()/128;
23996 unsigned NumLaneElts = NumElts / NumLanes;
23997 assert((NumLaneElts % 2 == 0) &&
23998 "Vector type should have an even number of elements in each lane");
23999 unsigned HalfLaneElts = NumLaneElts/2;
24001 // View LHS in the form
24002 // LHS = VECTOR_SHUFFLE A, B, LMask
24003 // If LHS is not a shuffle then pretend it is the shuffle
24004 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24005 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24008 SmallVector<int, 16> LMask(NumElts);
24009 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24010 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24011 A = LHS.getOperand(0);
24012 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24013 B = LHS.getOperand(1);
24014 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24015 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24017 if (LHS.getOpcode() != ISD::UNDEF)
24019 for (unsigned i = 0; i != NumElts; ++i)
24023 // Likewise, view RHS in the form
24024 // RHS = VECTOR_SHUFFLE C, D, RMask
24026 SmallVector<int, 16> RMask(NumElts);
24027 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24028 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24029 C = RHS.getOperand(0);
24030 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24031 D = RHS.getOperand(1);
24032 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24033 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24035 if (RHS.getOpcode() != ISD::UNDEF)
24037 for (unsigned i = 0; i != NumElts; ++i)
24041 // Check that the shuffles are both shuffling the same vectors.
24042 if (!(A == C && B == D) && !(A == D && B == C))
24045 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24046 if (!A.getNode() && !B.getNode())
24049 // If A and B occur in reverse order in RHS, then "swap" them (which means
24050 // rewriting the mask).
24052 CommuteVectorShuffleMask(RMask, NumElts);
24054 // At this point LHS and RHS are equivalent to
24055 // LHS = VECTOR_SHUFFLE A, B, LMask
24056 // RHS = VECTOR_SHUFFLE A, B, RMask
24057 // Check that the masks correspond to performing a horizontal operation.
24058 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24059 for (unsigned i = 0; i != NumLaneElts; ++i) {
24060 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24062 // Ignore any UNDEF components.
24063 if (LIdx < 0 || RIdx < 0 ||
24064 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24065 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24068 // Check that successive elements are being operated on. If not, this is
24069 // not a horizontal operation.
24070 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24071 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24072 if (!(LIdx == Index && RIdx == Index + 1) &&
24073 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24078 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24079 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24083 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24084 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24085 const X86Subtarget *Subtarget) {
24086 EVT VT = N->getValueType(0);
24087 SDValue LHS = N->getOperand(0);
24088 SDValue RHS = N->getOperand(1);
24090 // Try to synthesize horizontal adds from adds of shuffles.
24091 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24092 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24093 isHorizontalBinOp(LHS, RHS, true))
24094 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24098 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24099 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24100 const X86Subtarget *Subtarget) {
24101 EVT VT = N->getValueType(0);
24102 SDValue LHS = N->getOperand(0);
24103 SDValue RHS = N->getOperand(1);
24105 // Try to synthesize horizontal subs from subs of shuffles.
24106 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24107 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24108 isHorizontalBinOp(LHS, RHS, false))
24109 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24113 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24114 /// X86ISD::FXOR nodes.
24115 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24116 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24117 // F[X]OR(0.0, x) -> x
24118 // F[X]OR(x, 0.0) -> x
24119 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24120 if (C->getValueAPF().isPosZero())
24121 return N->getOperand(1);
24122 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24123 if (C->getValueAPF().isPosZero())
24124 return N->getOperand(0);
24128 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24129 /// X86ISD::FMAX nodes.
24130 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24131 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24133 // Only perform optimizations if UnsafeMath is used.
24134 if (!DAG.getTarget().Options.UnsafeFPMath)
24137 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24138 // into FMINC and FMAXC, which are Commutative operations.
24139 unsigned NewOp = 0;
24140 switch (N->getOpcode()) {
24141 default: llvm_unreachable("unknown opcode");
24142 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24143 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24146 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24147 N->getOperand(0), N->getOperand(1));
24150 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24151 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24152 // FAND(0.0, x) -> 0.0
24153 // FAND(x, 0.0) -> 0.0
24154 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24155 if (C->getValueAPF().isPosZero())
24156 return N->getOperand(0);
24157 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24158 if (C->getValueAPF().isPosZero())
24159 return N->getOperand(1);
24163 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24164 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24165 // FANDN(x, 0.0) -> 0.0
24166 // FANDN(0.0, x) -> x
24167 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24168 if (C->getValueAPF().isPosZero())
24169 return N->getOperand(1);
24170 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24171 if (C->getValueAPF().isPosZero())
24172 return N->getOperand(1);
24176 static SDValue PerformBTCombine(SDNode *N,
24178 TargetLowering::DAGCombinerInfo &DCI) {
24179 // BT ignores high bits in the bit index operand.
24180 SDValue Op1 = N->getOperand(1);
24181 if (Op1.hasOneUse()) {
24182 unsigned BitWidth = Op1.getValueSizeInBits();
24183 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24184 APInt KnownZero, KnownOne;
24185 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24186 !DCI.isBeforeLegalizeOps());
24187 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24188 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24189 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24190 DCI.CommitTargetLoweringOpt(TLO);
24195 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24196 SDValue Op = N->getOperand(0);
24197 if (Op.getOpcode() == ISD::BITCAST)
24198 Op = Op.getOperand(0);
24199 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24200 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24201 VT.getVectorElementType().getSizeInBits() ==
24202 OpVT.getVectorElementType().getSizeInBits()) {
24203 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24208 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24209 const X86Subtarget *Subtarget) {
24210 EVT VT = N->getValueType(0);
24211 if (!VT.isVector())
24214 SDValue N0 = N->getOperand(0);
24215 SDValue N1 = N->getOperand(1);
24216 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24219 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24220 // both SSE and AVX2 since there is no sign-extended shift right
24221 // operation on a vector with 64-bit elements.
24222 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24223 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24224 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24225 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24226 SDValue N00 = N0.getOperand(0);
24228 // EXTLOAD has a better solution on AVX2,
24229 // it may be replaced with X86ISD::VSEXT node.
24230 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24231 if (!ISD::isNormalLoad(N00.getNode()))
24234 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24235 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24237 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24243 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24244 TargetLowering::DAGCombinerInfo &DCI,
24245 const X86Subtarget *Subtarget) {
24246 if (!DCI.isBeforeLegalizeOps())
24249 if (!Subtarget->hasFp256())
24252 EVT VT = N->getValueType(0);
24253 if (VT.isVector() && VT.getSizeInBits() == 256) {
24254 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24262 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24263 const X86Subtarget* Subtarget) {
24265 EVT VT = N->getValueType(0);
24267 // Let legalize expand this if it isn't a legal type yet.
24268 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24271 EVT ScalarVT = VT.getScalarType();
24272 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24273 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24276 SDValue A = N->getOperand(0);
24277 SDValue B = N->getOperand(1);
24278 SDValue C = N->getOperand(2);
24280 bool NegA = (A.getOpcode() == ISD::FNEG);
24281 bool NegB = (B.getOpcode() == ISD::FNEG);
24282 bool NegC = (C.getOpcode() == ISD::FNEG);
24284 // Negative multiplication when NegA xor NegB
24285 bool NegMul = (NegA != NegB);
24287 A = A.getOperand(0);
24289 B = B.getOperand(0);
24291 C = C.getOperand(0);
24295 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24297 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24299 return DAG.getNode(Opcode, dl, VT, A, B, C);
24302 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24303 TargetLowering::DAGCombinerInfo &DCI,
24304 const X86Subtarget *Subtarget) {
24305 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24306 // (and (i32 x86isd::setcc_carry), 1)
24307 // This eliminates the zext. This transformation is necessary because
24308 // ISD::SETCC is always legalized to i8.
24310 SDValue N0 = N->getOperand(0);
24311 EVT VT = N->getValueType(0);
24313 if (N0.getOpcode() == ISD::AND &&
24315 N0.getOperand(0).hasOneUse()) {
24316 SDValue N00 = N0.getOperand(0);
24317 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24319 if (!C || C->getZExtValue() != 1)
24321 return DAG.getNode(ISD::AND, dl, VT,
24322 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24323 N00.getOperand(0), N00.getOperand(1)),
24324 DAG.getConstant(1, VT));
24328 if (N0.getOpcode() == ISD::TRUNCATE &&
24330 N0.getOperand(0).hasOneUse()) {
24331 SDValue N00 = N0.getOperand(0);
24332 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24333 return DAG.getNode(ISD::AND, dl, VT,
24334 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24335 N00.getOperand(0), N00.getOperand(1)),
24336 DAG.getConstant(1, VT));
24339 if (VT.is256BitVector()) {
24340 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24348 // Optimize x == -y --> x+y == 0
24349 // x != -y --> x+y != 0
24350 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24351 const X86Subtarget* Subtarget) {
24352 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24353 SDValue LHS = N->getOperand(0);
24354 SDValue RHS = N->getOperand(1);
24355 EVT VT = N->getValueType(0);
24358 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24359 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24360 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24361 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24362 LHS.getValueType(), RHS, LHS.getOperand(1));
24363 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24364 addV, DAG.getConstant(0, addV.getValueType()), CC);
24366 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24368 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24369 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24370 RHS.getValueType(), LHS, RHS.getOperand(1));
24371 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24372 addV, DAG.getConstant(0, addV.getValueType()), CC);
24375 if (VT.getScalarType() == MVT::i1) {
24376 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24377 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24378 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24379 if (!IsSEXT0 && !IsVZero0)
24381 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24382 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24383 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24385 if (!IsSEXT1 && !IsVZero1)
24388 if (IsSEXT0 && IsVZero1) {
24389 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24390 if (CC == ISD::SETEQ)
24391 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24392 return LHS.getOperand(0);
24394 if (IsSEXT1 && IsVZero0) {
24395 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24396 if (CC == ISD::SETEQ)
24397 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24398 return RHS.getOperand(0);
24405 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24406 const X86Subtarget *Subtarget) {
24408 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24409 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24410 "X86insertps is only defined for v4x32");
24412 SDValue Ld = N->getOperand(1);
24413 if (MayFoldLoad(Ld)) {
24414 // Extract the countS bits from the immediate so we can get the proper
24415 // address when narrowing the vector load to a specific element.
24416 // When the second source op is a memory address, interps doesn't use
24417 // countS and just gets an f32 from that address.
24418 unsigned DestIndex =
24419 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24420 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24424 // Create this as a scalar to vector to match the instruction pattern.
24425 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24426 // countS bits are ignored when loading from memory on insertps, which
24427 // means we don't need to explicitly set them to 0.
24428 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24429 LoadScalarToVector, N->getOperand(2));
24432 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24433 // as "sbb reg,reg", since it can be extended without zext and produces
24434 // an all-ones bit which is more useful than 0/1 in some cases.
24435 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24438 return DAG.getNode(ISD::AND, DL, VT,
24439 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24440 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24441 DAG.getConstant(1, VT));
24442 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24443 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24444 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24445 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24448 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24449 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24450 TargetLowering::DAGCombinerInfo &DCI,
24451 const X86Subtarget *Subtarget) {
24453 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24454 SDValue EFLAGS = N->getOperand(1);
24456 if (CC == X86::COND_A) {
24457 // Try to convert COND_A into COND_B in an attempt to facilitate
24458 // materializing "setb reg".
24460 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24461 // cannot take an immediate as its first operand.
24463 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24464 EFLAGS.getValueType().isInteger() &&
24465 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24466 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24467 EFLAGS.getNode()->getVTList(),
24468 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24469 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24470 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24474 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24475 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24477 if (CC == X86::COND_B)
24478 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24482 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24483 if (Flags.getNode()) {
24484 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24485 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24491 // Optimize branch condition evaluation.
24493 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24494 TargetLowering::DAGCombinerInfo &DCI,
24495 const X86Subtarget *Subtarget) {
24497 SDValue Chain = N->getOperand(0);
24498 SDValue Dest = N->getOperand(1);
24499 SDValue EFLAGS = N->getOperand(3);
24500 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24504 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24505 if (Flags.getNode()) {
24506 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24507 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24514 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24515 SelectionDAG &DAG) {
24516 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24517 // optimize away operation when it's from a constant.
24519 // The general transformation is:
24520 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24521 // AND(VECTOR_CMP(x,y), constant2)
24522 // constant2 = UNARYOP(constant)
24524 // Early exit if this isn't a vector operation, the operand of the
24525 // unary operation isn't a bitwise AND, or if the sizes of the operations
24526 // aren't the same.
24527 EVT VT = N->getValueType(0);
24528 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24529 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24530 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24533 // Now check that the other operand of the AND is a constant. We could
24534 // make the transformation for non-constant splats as well, but it's unclear
24535 // that would be a benefit as it would not eliminate any operations, just
24536 // perform one more step in scalar code before moving to the vector unit.
24537 if (BuildVectorSDNode *BV =
24538 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24539 // Bail out if the vector isn't a constant.
24540 if (!BV->isConstant())
24543 // Everything checks out. Build up the new and improved node.
24545 EVT IntVT = BV->getValueType(0);
24546 // Create a new constant of the appropriate type for the transformed
24548 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24549 // The AND node needs bitcasts to/from an integer vector type around it.
24550 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24551 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24552 N->getOperand(0)->getOperand(0), MaskConst);
24553 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24560 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24561 const X86TargetLowering *XTLI) {
24562 // First try to optimize away the conversion entirely when it's
24563 // conditionally from a constant. Vectors only.
24564 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24565 if (Res != SDValue())
24568 // Now move on to more general possibilities.
24569 SDValue Op0 = N->getOperand(0);
24570 EVT InVT = Op0->getValueType(0);
24572 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24573 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24575 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24576 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24577 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24580 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24581 // a 32-bit target where SSE doesn't support i64->FP operations.
24582 if (Op0.getOpcode() == ISD::LOAD) {
24583 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24584 EVT VT = Ld->getValueType(0);
24585 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24586 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24587 !XTLI->getSubtarget()->is64Bit() &&
24589 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24590 Ld->getChain(), Op0, DAG);
24591 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24598 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24599 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24600 X86TargetLowering::DAGCombinerInfo &DCI) {
24601 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24602 // the result is either zero or one (depending on the input carry bit).
24603 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24604 if (X86::isZeroNode(N->getOperand(0)) &&
24605 X86::isZeroNode(N->getOperand(1)) &&
24606 // We don't have a good way to replace an EFLAGS use, so only do this when
24608 SDValue(N, 1).use_empty()) {
24610 EVT VT = N->getValueType(0);
24611 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24612 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24613 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24614 DAG.getConstant(X86::COND_B,MVT::i8),
24616 DAG.getConstant(1, VT));
24617 return DCI.CombineTo(N, Res1, CarryOut);
24623 // fold (add Y, (sete X, 0)) -> adc 0, Y
24624 // (add Y, (setne X, 0)) -> sbb -1, Y
24625 // (sub (sete X, 0), Y) -> sbb 0, Y
24626 // (sub (setne X, 0), Y) -> adc -1, Y
24627 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24630 // Look through ZExts.
24631 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24632 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24635 SDValue SetCC = Ext.getOperand(0);
24636 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24639 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24640 if (CC != X86::COND_E && CC != X86::COND_NE)
24643 SDValue Cmp = SetCC.getOperand(1);
24644 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24645 !X86::isZeroNode(Cmp.getOperand(1)) ||
24646 !Cmp.getOperand(0).getValueType().isInteger())
24649 SDValue CmpOp0 = Cmp.getOperand(0);
24650 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24651 DAG.getConstant(1, CmpOp0.getValueType()));
24653 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24654 if (CC == X86::COND_NE)
24655 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24656 DL, OtherVal.getValueType(), OtherVal,
24657 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24658 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24659 DL, OtherVal.getValueType(), OtherVal,
24660 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24663 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24664 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24665 const X86Subtarget *Subtarget) {
24666 EVT VT = N->getValueType(0);
24667 SDValue Op0 = N->getOperand(0);
24668 SDValue Op1 = N->getOperand(1);
24670 // Try to synthesize horizontal adds from adds of shuffles.
24671 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24672 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24673 isHorizontalBinOp(Op0, Op1, true))
24674 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24676 return OptimizeConditionalInDecrement(N, DAG);
24679 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24680 const X86Subtarget *Subtarget) {
24681 SDValue Op0 = N->getOperand(0);
24682 SDValue Op1 = N->getOperand(1);
24684 // X86 can't encode an immediate LHS of a sub. See if we can push the
24685 // negation into a preceding instruction.
24686 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24687 // If the RHS of the sub is a XOR with one use and a constant, invert the
24688 // immediate. Then add one to the LHS of the sub so we can turn
24689 // X-Y -> X+~Y+1, saving one register.
24690 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24691 isa<ConstantSDNode>(Op1.getOperand(1))) {
24692 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24693 EVT VT = Op0.getValueType();
24694 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24696 DAG.getConstant(~XorC, VT));
24697 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24698 DAG.getConstant(C->getAPIntValue()+1, VT));
24702 // Try to synthesize horizontal adds from adds of shuffles.
24703 EVT VT = N->getValueType(0);
24704 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24705 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24706 isHorizontalBinOp(Op0, Op1, true))
24707 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24709 return OptimizeConditionalInDecrement(N, DAG);
24712 /// performVZEXTCombine - Performs build vector combines
24713 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24714 TargetLowering::DAGCombinerInfo &DCI,
24715 const X86Subtarget *Subtarget) {
24717 MVT VT = N->getSimpleValueType(0);
24718 SDValue Op = N->getOperand(0);
24719 MVT OpVT = Op.getSimpleValueType();
24720 MVT OpEltVT = OpVT.getVectorElementType();
24721 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24723 // (vzext (bitcast (vzext (x)) -> (vzext x)
24725 while (V.getOpcode() == ISD::BITCAST)
24726 V = V.getOperand(0);
24728 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24729 MVT InnerVT = V.getSimpleValueType();
24730 MVT InnerEltVT = InnerVT.getVectorElementType();
24732 // If the element sizes match exactly, we can just do one larger vzext. This
24733 // is always an exact type match as vzext operates on integer types.
24734 if (OpEltVT == InnerEltVT) {
24735 assert(OpVT == InnerVT && "Types must match for vzext!");
24736 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24739 // The only other way we can combine them is if only a single element of the
24740 // inner vzext is used in the input to the outer vzext.
24741 if (InnerEltVT.getSizeInBits() < InputBits)
24744 // In this case, the inner vzext is completely dead because we're going to
24745 // only look at bits inside of the low element. Just do the outer vzext on
24746 // a bitcast of the input to the inner.
24747 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24748 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24751 // Check if we can bypass extracting and re-inserting an element of an input
24752 // vector. Essentialy:
24753 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24754 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24755 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24756 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24757 SDValue ExtractedV = V.getOperand(0);
24758 SDValue OrigV = ExtractedV.getOperand(0);
24759 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24760 if (ExtractIdx->getZExtValue() == 0) {
24761 MVT OrigVT = OrigV.getSimpleValueType();
24762 // Extract a subvector if necessary...
24763 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24764 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24765 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24766 OrigVT.getVectorNumElements() / Ratio);
24767 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24768 DAG.getIntPtrConstant(0));
24770 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24771 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24778 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24779 DAGCombinerInfo &DCI) const {
24780 SelectionDAG &DAG = DCI.DAG;
24781 switch (N->getOpcode()) {
24783 case ISD::EXTRACT_VECTOR_ELT:
24784 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24786 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24787 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24788 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24789 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24790 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24791 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24794 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24795 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24796 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24797 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24798 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24799 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24800 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24801 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24802 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24804 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24806 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24807 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24808 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24809 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24810 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24811 case ISD::ANY_EXTEND:
24812 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24813 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24814 case ISD::SIGN_EXTEND_INREG:
24815 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24816 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24817 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24818 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24819 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24820 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24821 case X86ISD::SHUFP: // Handle all target specific shuffles
24822 case X86ISD::PALIGNR:
24823 case X86ISD::UNPCKH:
24824 case X86ISD::UNPCKL:
24825 case X86ISD::MOVHLPS:
24826 case X86ISD::MOVLHPS:
24827 case X86ISD::PSHUFB:
24828 case X86ISD::PSHUFD:
24829 case X86ISD::PSHUFHW:
24830 case X86ISD::PSHUFLW:
24831 case X86ISD::MOVSS:
24832 case X86ISD::MOVSD:
24833 case X86ISD::VPERMILPI:
24834 case X86ISD::VPERM2X128:
24835 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24836 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24837 case ISD::INTRINSIC_WO_CHAIN:
24838 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24839 case X86ISD::INSERTPS:
24840 return PerformINSERTPSCombine(N, DAG, Subtarget);
24841 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24847 /// isTypeDesirableForOp - Return true if the target has native support for
24848 /// the specified value type and it is 'desirable' to use the type for the
24849 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24850 /// instruction encodings are longer and some i16 instructions are slow.
24851 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24852 if (!isTypeLegal(VT))
24854 if (VT != MVT::i16)
24861 case ISD::SIGN_EXTEND:
24862 case ISD::ZERO_EXTEND:
24863 case ISD::ANY_EXTEND:
24876 /// IsDesirableToPromoteOp - This method query the target whether it is
24877 /// beneficial for dag combiner to promote the specified node. If true, it
24878 /// should return the desired promotion type by reference.
24879 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24880 EVT VT = Op.getValueType();
24881 if (VT != MVT::i16)
24884 bool Promote = false;
24885 bool Commute = false;
24886 switch (Op.getOpcode()) {
24889 LoadSDNode *LD = cast<LoadSDNode>(Op);
24890 // If the non-extending load has a single use and it's not live out, then it
24891 // might be folded.
24892 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24893 Op.hasOneUse()*/) {
24894 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24895 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24896 // The only case where we'd want to promote LOAD (rather then it being
24897 // promoted as an operand is when it's only use is liveout.
24898 if (UI->getOpcode() != ISD::CopyToReg)
24905 case ISD::SIGN_EXTEND:
24906 case ISD::ZERO_EXTEND:
24907 case ISD::ANY_EXTEND:
24912 SDValue N0 = Op.getOperand(0);
24913 // Look out for (store (shl (load), x)).
24914 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24927 SDValue N0 = Op.getOperand(0);
24928 SDValue N1 = Op.getOperand(1);
24929 if (!Commute && MayFoldLoad(N1))
24931 // Avoid disabling potential load folding opportunities.
24932 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24934 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24944 //===----------------------------------------------------------------------===//
24945 // X86 Inline Assembly Support
24946 //===----------------------------------------------------------------------===//
24949 // Helper to match a string separated by whitespace.
24950 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24951 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24953 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24954 StringRef piece(*args[i]);
24955 if (!s.startswith(piece)) // Check if the piece matches.
24958 s = s.substr(piece.size());
24959 StringRef::size_type pos = s.find_first_not_of(" \t");
24960 if (pos == 0) // We matched a prefix.
24968 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24971 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24973 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24974 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24975 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24976 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24978 if (AsmPieces.size() == 3)
24980 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24987 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24988 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24990 std::string AsmStr = IA->getAsmString();
24992 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24993 if (!Ty || Ty->getBitWidth() % 16 != 0)
24996 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24997 SmallVector<StringRef, 4> AsmPieces;
24998 SplitString(AsmStr, AsmPieces, ";\n");
25000 switch (AsmPieces.size()) {
25001 default: return false;
25003 // FIXME: this should verify that we are targeting a 486 or better. If not,
25004 // we will turn this bswap into something that will be lowered to logical
25005 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25006 // lower so don't worry about this.
25008 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25009 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25010 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25011 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25012 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25013 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25014 // No need to check constraints, nothing other than the equivalent of
25015 // "=r,0" would be valid here.
25016 return IntrinsicLowering::LowerToByteSwap(CI);
25019 // rorw $$8, ${0:w} --> llvm.bswap.i16
25020 if (CI->getType()->isIntegerTy(16) &&
25021 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25022 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25023 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25025 const std::string &ConstraintsStr = IA->getConstraintString();
25026 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25027 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25028 if (clobbersFlagRegisters(AsmPieces))
25029 return IntrinsicLowering::LowerToByteSwap(CI);
25033 if (CI->getType()->isIntegerTy(32) &&
25034 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25035 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25036 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25037 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25039 const std::string &ConstraintsStr = IA->getConstraintString();
25040 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25041 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25042 if (clobbersFlagRegisters(AsmPieces))
25043 return IntrinsicLowering::LowerToByteSwap(CI);
25046 if (CI->getType()->isIntegerTy(64)) {
25047 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25048 if (Constraints.size() >= 2 &&
25049 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25050 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25051 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25052 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25053 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25054 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25055 return IntrinsicLowering::LowerToByteSwap(CI);
25063 /// getConstraintType - Given a constraint letter, return the type of
25064 /// constraint it is for this target.
25065 X86TargetLowering::ConstraintType
25066 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25067 if (Constraint.size() == 1) {
25068 switch (Constraint[0]) {
25079 return C_RegisterClass;
25103 return TargetLowering::getConstraintType(Constraint);
25106 /// Examine constraint type and operand type and determine a weight value.
25107 /// This object must already have been set up with the operand type
25108 /// and the current alternative constraint selected.
25109 TargetLowering::ConstraintWeight
25110 X86TargetLowering::getSingleConstraintMatchWeight(
25111 AsmOperandInfo &info, const char *constraint) const {
25112 ConstraintWeight weight = CW_Invalid;
25113 Value *CallOperandVal = info.CallOperandVal;
25114 // If we don't have a value, we can't do a match,
25115 // but allow it at the lowest weight.
25116 if (!CallOperandVal)
25118 Type *type = CallOperandVal->getType();
25119 // Look at the constraint type.
25120 switch (*constraint) {
25122 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25133 if (CallOperandVal->getType()->isIntegerTy())
25134 weight = CW_SpecificReg;
25139 if (type->isFloatingPointTy())
25140 weight = CW_SpecificReg;
25143 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25144 weight = CW_SpecificReg;
25148 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25149 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25150 weight = CW_Register;
25153 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25154 if (C->getZExtValue() <= 31)
25155 weight = CW_Constant;
25159 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25160 if (C->getZExtValue() <= 63)
25161 weight = CW_Constant;
25165 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25166 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25167 weight = CW_Constant;
25171 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25172 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25173 weight = CW_Constant;
25177 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25178 if (C->getZExtValue() <= 3)
25179 weight = CW_Constant;
25183 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25184 if (C->getZExtValue() <= 0xff)
25185 weight = CW_Constant;
25190 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25191 weight = CW_Constant;
25195 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25196 if ((C->getSExtValue() >= -0x80000000LL) &&
25197 (C->getSExtValue() <= 0x7fffffffLL))
25198 weight = CW_Constant;
25202 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25203 if (C->getZExtValue() <= 0xffffffff)
25204 weight = CW_Constant;
25211 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25212 /// with another that has more specific requirements based on the type of the
25213 /// corresponding operand.
25214 const char *X86TargetLowering::
25215 LowerXConstraint(EVT ConstraintVT) const {
25216 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25217 // 'f' like normal targets.
25218 if (ConstraintVT.isFloatingPoint()) {
25219 if (Subtarget->hasSSE2())
25221 if (Subtarget->hasSSE1())
25225 return TargetLowering::LowerXConstraint(ConstraintVT);
25228 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25229 /// vector. If it is invalid, don't add anything to Ops.
25230 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25231 std::string &Constraint,
25232 std::vector<SDValue>&Ops,
25233 SelectionDAG &DAG) const {
25236 // Only support length 1 constraints for now.
25237 if (Constraint.length() > 1) return;
25239 char ConstraintLetter = Constraint[0];
25240 switch (ConstraintLetter) {
25243 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25244 if (C->getZExtValue() <= 31) {
25245 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25252 if (C->getZExtValue() <= 63) {
25253 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25259 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25260 if (isInt<8>(C->getSExtValue())) {
25261 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25268 if (C->getZExtValue() <= 255) {
25269 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25275 // 32-bit signed value
25276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25277 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25278 C->getSExtValue())) {
25279 // Widen to 64 bits here to get it sign extended.
25280 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25283 // FIXME gcc accepts some relocatable values here too, but only in certain
25284 // memory models; it's complicated.
25289 // 32-bit unsigned value
25290 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25291 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25292 C->getZExtValue())) {
25293 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25297 // FIXME gcc accepts some relocatable values here too, but only in certain
25298 // memory models; it's complicated.
25302 // Literal immediates are always ok.
25303 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25304 // Widen to 64 bits here to get it sign extended.
25305 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25309 // In any sort of PIC mode addresses need to be computed at runtime by
25310 // adding in a register or some sort of table lookup. These can't
25311 // be used as immediates.
25312 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25315 // If we are in non-pic codegen mode, we allow the address of a global (with
25316 // an optional displacement) to be used with 'i'.
25317 GlobalAddressSDNode *GA = nullptr;
25318 int64_t Offset = 0;
25320 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25322 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25323 Offset += GA->getOffset();
25325 } else if (Op.getOpcode() == ISD::ADD) {
25326 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25327 Offset += C->getZExtValue();
25328 Op = Op.getOperand(0);
25331 } else if (Op.getOpcode() == ISD::SUB) {
25332 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25333 Offset += -C->getZExtValue();
25334 Op = Op.getOperand(0);
25339 // Otherwise, this isn't something we can handle, reject it.
25343 const GlobalValue *GV = GA->getGlobal();
25344 // If we require an extra load to get this address, as in PIC mode, we
25345 // can't accept it.
25346 if (isGlobalStubReference(
25347 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25350 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25351 GA->getValueType(0), Offset);
25356 if (Result.getNode()) {
25357 Ops.push_back(Result);
25360 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25363 std::pair<unsigned, const TargetRegisterClass*>
25364 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25366 // First, see if this is a constraint that directly corresponds to an LLVM
25368 if (Constraint.size() == 1) {
25369 // GCC Constraint Letters
25370 switch (Constraint[0]) {
25372 // TODO: Slight differences here in allocation order and leaving
25373 // RIP in the class. Do they matter any more here than they do
25374 // in the normal allocation?
25375 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25376 if (Subtarget->is64Bit()) {
25377 if (VT == MVT::i32 || VT == MVT::f32)
25378 return std::make_pair(0U, &X86::GR32RegClass);
25379 if (VT == MVT::i16)
25380 return std::make_pair(0U, &X86::GR16RegClass);
25381 if (VT == MVT::i8 || VT == MVT::i1)
25382 return std::make_pair(0U, &X86::GR8RegClass);
25383 if (VT == MVT::i64 || VT == MVT::f64)
25384 return std::make_pair(0U, &X86::GR64RegClass);
25387 // 32-bit fallthrough
25388 case 'Q': // Q_REGS
25389 if (VT == MVT::i32 || VT == MVT::f32)
25390 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25391 if (VT == MVT::i16)
25392 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25393 if (VT == MVT::i8 || VT == MVT::i1)
25394 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25395 if (VT == MVT::i64)
25396 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25398 case 'r': // GENERAL_REGS
25399 case 'l': // INDEX_REGS
25400 if (VT == MVT::i8 || VT == MVT::i1)
25401 return std::make_pair(0U, &X86::GR8RegClass);
25402 if (VT == MVT::i16)
25403 return std::make_pair(0U, &X86::GR16RegClass);
25404 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25405 return std::make_pair(0U, &X86::GR32RegClass);
25406 return std::make_pair(0U, &X86::GR64RegClass);
25407 case 'R': // LEGACY_REGS
25408 if (VT == MVT::i8 || VT == MVT::i1)
25409 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25410 if (VT == MVT::i16)
25411 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25412 if (VT == MVT::i32 || !Subtarget->is64Bit())
25413 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25414 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25415 case 'f': // FP Stack registers.
25416 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25417 // value to the correct fpstack register class.
25418 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25419 return std::make_pair(0U, &X86::RFP32RegClass);
25420 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25421 return std::make_pair(0U, &X86::RFP64RegClass);
25422 return std::make_pair(0U, &X86::RFP80RegClass);
25423 case 'y': // MMX_REGS if MMX allowed.
25424 if (!Subtarget->hasMMX()) break;
25425 return std::make_pair(0U, &X86::VR64RegClass);
25426 case 'Y': // SSE_REGS if SSE2 allowed
25427 if (!Subtarget->hasSSE2()) break;
25429 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25430 if (!Subtarget->hasSSE1()) break;
25432 switch (VT.SimpleTy) {
25434 // Scalar SSE types.
25437 return std::make_pair(0U, &X86::FR32RegClass);
25440 return std::make_pair(0U, &X86::FR64RegClass);
25448 return std::make_pair(0U, &X86::VR128RegClass);
25456 return std::make_pair(0U, &X86::VR256RegClass);
25461 return std::make_pair(0U, &X86::VR512RegClass);
25467 // Use the default implementation in TargetLowering to convert the register
25468 // constraint into a member of a register class.
25469 std::pair<unsigned, const TargetRegisterClass*> Res;
25470 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25472 // Not found as a standard register?
25474 // Map st(0) -> st(7) -> ST0
25475 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25476 tolower(Constraint[1]) == 's' &&
25477 tolower(Constraint[2]) == 't' &&
25478 Constraint[3] == '(' &&
25479 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25480 Constraint[5] == ')' &&
25481 Constraint[6] == '}') {
25483 Res.first = X86::FP0+Constraint[4]-'0';
25484 Res.second = &X86::RFP80RegClass;
25488 // GCC allows "st(0)" to be called just plain "st".
25489 if (StringRef("{st}").equals_lower(Constraint)) {
25490 Res.first = X86::FP0;
25491 Res.second = &X86::RFP80RegClass;
25496 if (StringRef("{flags}").equals_lower(Constraint)) {
25497 Res.first = X86::EFLAGS;
25498 Res.second = &X86::CCRRegClass;
25502 // 'A' means EAX + EDX.
25503 if (Constraint == "A") {
25504 Res.first = X86::EAX;
25505 Res.second = &X86::GR32_ADRegClass;
25511 // Otherwise, check to see if this is a register class of the wrong value
25512 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25513 // turn into {ax},{dx}.
25514 if (Res.second->hasType(VT))
25515 return Res; // Correct type already, nothing to do.
25517 // All of the single-register GCC register classes map their values onto
25518 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25519 // really want an 8-bit or 32-bit register, map to the appropriate register
25520 // class and return the appropriate register.
25521 if (Res.second == &X86::GR16RegClass) {
25522 if (VT == MVT::i8 || VT == MVT::i1) {
25523 unsigned DestReg = 0;
25524 switch (Res.first) {
25526 case X86::AX: DestReg = X86::AL; break;
25527 case X86::DX: DestReg = X86::DL; break;
25528 case X86::CX: DestReg = X86::CL; break;
25529 case X86::BX: DestReg = X86::BL; break;
25532 Res.first = DestReg;
25533 Res.second = &X86::GR8RegClass;
25535 } else if (VT == MVT::i32 || VT == MVT::f32) {
25536 unsigned DestReg = 0;
25537 switch (Res.first) {
25539 case X86::AX: DestReg = X86::EAX; break;
25540 case X86::DX: DestReg = X86::EDX; break;
25541 case X86::CX: DestReg = X86::ECX; break;
25542 case X86::BX: DestReg = X86::EBX; break;
25543 case X86::SI: DestReg = X86::ESI; break;
25544 case X86::DI: DestReg = X86::EDI; break;
25545 case X86::BP: DestReg = X86::EBP; break;
25546 case X86::SP: DestReg = X86::ESP; break;
25549 Res.first = DestReg;
25550 Res.second = &X86::GR32RegClass;
25552 } else if (VT == MVT::i64 || VT == MVT::f64) {
25553 unsigned DestReg = 0;
25554 switch (Res.first) {
25556 case X86::AX: DestReg = X86::RAX; break;
25557 case X86::DX: DestReg = X86::RDX; break;
25558 case X86::CX: DestReg = X86::RCX; break;
25559 case X86::BX: DestReg = X86::RBX; break;
25560 case X86::SI: DestReg = X86::RSI; break;
25561 case X86::DI: DestReg = X86::RDI; break;
25562 case X86::BP: DestReg = X86::RBP; break;
25563 case X86::SP: DestReg = X86::RSP; break;
25566 Res.first = DestReg;
25567 Res.second = &X86::GR64RegClass;
25570 } else if (Res.second == &X86::FR32RegClass ||
25571 Res.second == &X86::FR64RegClass ||
25572 Res.second == &X86::VR128RegClass ||
25573 Res.second == &X86::VR256RegClass ||
25574 Res.second == &X86::FR32XRegClass ||
25575 Res.second == &X86::FR64XRegClass ||
25576 Res.second == &X86::VR128XRegClass ||
25577 Res.second == &X86::VR256XRegClass ||
25578 Res.second == &X86::VR512RegClass) {
25579 // Handle references to XMM physical registers that got mapped into the
25580 // wrong class. This can happen with constraints like {xmm0} where the
25581 // target independent register mapper will just pick the first match it can
25582 // find, ignoring the required type.
25584 if (VT == MVT::f32 || VT == MVT::i32)
25585 Res.second = &X86::FR32RegClass;
25586 else if (VT == MVT::f64 || VT == MVT::i64)
25587 Res.second = &X86::FR64RegClass;
25588 else if (X86::VR128RegClass.hasType(VT))
25589 Res.second = &X86::VR128RegClass;
25590 else if (X86::VR256RegClass.hasType(VT))
25591 Res.second = &X86::VR256RegClass;
25592 else if (X86::VR512RegClass.hasType(VT))
25593 Res.second = &X86::VR512RegClass;
25599 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25601 // Scaling factors are not free at all.
25602 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25603 // will take 2 allocations in the out of order engine instead of 1
25604 // for plain addressing mode, i.e. inst (reg1).
25606 // vaddps (%rsi,%drx), %ymm0, %ymm1
25607 // Requires two allocations (one for the load, one for the computation)
25609 // vaddps (%rsi), %ymm0, %ymm1
25610 // Requires just 1 allocation, i.e., freeing allocations for other operations
25611 // and having less micro operations to execute.
25613 // For some X86 architectures, this is even worse because for instance for
25614 // stores, the complex addressing mode forces the instruction to use the
25615 // "load" ports instead of the dedicated "store" port.
25616 // E.g., on Haswell:
25617 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25618 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25619 if (isLegalAddressingMode(AM, Ty))
25620 // Scale represents reg2 * scale, thus account for 1
25621 // as soon as we use a second register.
25622 return AM.Scale != 0;
25626 bool X86TargetLowering::isTargetFTOL() const {
25627 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();