1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
45 // SSE codegen depends on cmovs, and all
46 // SSE1+ processors support them.
47 [FeatureMMX, FeatureCMOV]>;
48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
58 "Enable SSE 4.1 instructions",
60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
61 "Enable SSE 4.2 instructions",
63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
64 "Enable 3DNow! instructions",
66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
67 "Enable 3DNow! Athlon instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71 // without disabling 64-bit mode.
72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
73 "Support 64-bit instructions",
75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
76 "64-bit with cmpxchg16b",
78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
82 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
83 "IsUAMemFast", "true",
84 "Fast unaligned memory access">;
85 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
86 "Support SSE 4a instructions",
89 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
90 "Enable AVX instructions",
92 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
93 "Enable AVX2 instructions",
95 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
96 "Enable AVX-512 instructions",
98 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
99 "Enable AVX-512 Exponential and Reciprocal Instructions",
101 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
102 "Enable AVX-512 Conflict Detection Instructions",
104 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
105 "Enable AVX-512 PreFetch Instructions",
108 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
109 "Enable packed carry-less multiplication instructions",
111 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
112 "Enable three-operand fused multiple-add",
114 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
115 "Enable four-operand fused multiple-add",
116 [FeatureAVX, FeatureSSE4A]>;
117 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
118 "Enable XOP instructions",
120 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
121 "HasVectorUAMem", "true",
122 "Allow unaligned memory operands on vector/SIMD instructions">;
123 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
124 "Enable AES instructions",
126 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
127 "Enable TBM instructions">;
128 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
129 "Support MOVBE instruction">;
130 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
131 "Support RDRAND instruction">;
132 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
133 "Support 16-bit floating point conversion instructions",
135 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
136 "Support FS/GS Base instructions">;
137 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
138 "Support LZCNT instruction">;
139 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
140 "Support BMI instructions">;
141 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
142 "Support BMI2 instructions">;
143 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
144 "Support RTM instructions">;
145 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
147 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
148 "Support ADX instructions">;
149 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
150 "Enable SHA instructions",
152 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
153 "Support PRFCHW instructions">;
154 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
155 "Support RDSEED instruction">;
156 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
157 "Use LEA for adjusting the stack pointer">;
158 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
159 "HasSlowDivide", "true",
160 "Use small divide for positive values less than 256">;
161 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
162 "PadShortFunctions", "true",
163 "Pad short functions">;
164 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
165 "CallRegIndirect", "true",
166 "Call register indirect">;
167 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
168 "LEA instruction needs inputs at AG stage">;
170 //===----------------------------------------------------------------------===//
171 // X86 processors supported.
172 //===----------------------------------------------------------------------===//
174 include "X86Schedule.td"
176 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
177 "Intel Atom processors">;
178 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
179 "Intel Silvermont processors">;
181 class Proc<string Name, list<SubtargetFeature> Features>
182 : ProcessorModel<Name, GenericModel, Features>;
184 def : Proc<"generic", []>;
185 def : Proc<"i386", []>;
186 def : Proc<"i486", []>;
187 def : Proc<"i586", []>;
188 def : Proc<"pentium", []>;
189 def : Proc<"pentium-mmx", [FeatureMMX]>;
190 def : Proc<"i686", []>;
191 def : Proc<"pentiumpro", [FeatureCMOV]>;
192 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
193 def : Proc<"pentium3", [FeatureSSE1]>;
194 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
195 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
196 def : Proc<"pentium4", [FeatureSSE2]>;
197 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
200 def : ProcessorModel<"yonah", SandyBridgeModel,
201 [FeatureSSE3, FeatureSlowBTMem]>;
204 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
205 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
207 // Intel Core 2 Solo/Duo.
208 def : ProcessorModel<"core2", SandyBridgeModel,
209 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
210 def : ProcessorModel<"penryn", SandyBridgeModel,
211 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
214 def : ProcessorModel<"atom", AtomModel,
215 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
216 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
218 FeatureCallRegIndirect,
220 FeaturePadShortFunctions]>;
223 def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
224 FeatureSSE42, FeatureCMPXCHG16B,
225 FeatureMOVBE, FeaturePOPCNT,
226 FeaturePCLMUL, FeatureAES,
227 FeatureCallRegIndirect,
229 FeatureSlowBTMem, FeatureFastUAMem]>;
230 // "Arrandale" along with corei3 and corei5
231 def : ProcessorModel<"corei7", SandyBridgeModel,
232 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
233 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
235 def : ProcessorModel<"nehalem", SandyBridgeModel,
236 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
237 FeatureFastUAMem, FeaturePOPCNT]>;
238 // Westmere is a similar machine to nehalem with some additional features.
239 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
240 def : ProcessorModel<"westmere", SandyBridgeModel,
241 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
242 FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
245 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
246 // rather than a superset.
247 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
248 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
249 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
251 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
252 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
253 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
254 FeatureF16C, FeatureFSGSBase]>;
257 def : ProcessorModel<"core-avx2", HaswellModel,
258 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
259 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
260 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
261 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
265 // FIXME: define KNL model
266 def : ProcessorModel<"knl", HaswellModel,
267 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
268 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
269 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
270 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
271 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
273 def : Proc<"k6", [FeatureMMX]>;
274 def : Proc<"k6-2", [Feature3DNow]>;
275 def : Proc<"k6-3", [Feature3DNow]>;
276 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
278 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
280 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
282 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
284 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
286 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
287 FeatureSlowBTMem, FeatureSlowSHLD]>;
288 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
289 FeatureSlowBTMem, FeatureSlowSHLD]>;
290 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
291 FeatureSlowBTMem, FeatureSlowSHLD]>;
292 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
293 FeatureSlowBTMem, FeatureSlowSHLD]>;
294 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
295 FeatureSlowBTMem, FeatureSlowSHLD]>;
296 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
297 FeatureSlowBTMem, FeatureSlowSHLD]>;
298 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
299 FeatureSlowBTMem, FeatureSlowSHLD]>;
300 def : Proc<"amdfam10", [FeatureSSE4A,
301 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
302 FeaturePOPCNT, FeatureSlowBTMem,
305 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
306 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
309 def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
310 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
311 FeatureBMI, FeatureF16C, FeatureMOVBE,
312 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
314 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
315 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
316 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
318 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
319 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
320 FeatureF16C, FeatureLZCNT,
321 FeaturePOPCNT, FeatureBMI, FeatureTBM,
322 FeatureFMA, FeatureSlowSHLD]>;
325 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
326 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
327 FeatureF16C, FeatureLZCNT,
328 FeaturePOPCNT, FeatureBMI, FeatureTBM,
329 FeatureFMA, FeatureFSGSBase]>;
332 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
333 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
334 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
335 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
336 FeatureTBM, FeatureFMA, FeatureFSGSBase]>;
338 def : Proc<"geode", [Feature3DNowA]>;
340 def : Proc<"winchip-c6", [FeatureMMX]>;
341 def : Proc<"winchip2", [Feature3DNow]>;
342 def : Proc<"c3", [Feature3DNow]>;
343 def : Proc<"c3-2", [FeatureSSE1]>;
345 // We also provide a generic 64-bit specific x86 processor model which tries to
346 // be good for modern chips without enabling instruction set encodings past the
347 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
348 // modern 64-bit x86 chip, and enables features that are generally beneficial.
350 // We currently use the Sandy Bridge model as the default scheduling model as
351 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
352 // covers a huge swath of x86 processors. If there are specific scheduling
353 // knobs which need to be tuned differently for AMD chips, we might consider
354 // forming a common base for them.
355 def : ProcessorModel<"x86-64", SandyBridgeModel,
356 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
359 //===----------------------------------------------------------------------===//
360 // Register File Description
361 //===----------------------------------------------------------------------===//
363 include "X86RegisterInfo.td"
365 //===----------------------------------------------------------------------===//
366 // Instruction Descriptions
367 //===----------------------------------------------------------------------===//
369 include "X86InstrInfo.td"
371 def X86InstrInfo : InstrInfo;
373 //===----------------------------------------------------------------------===//
374 // Calling Conventions
375 //===----------------------------------------------------------------------===//
377 include "X86CallingConv.td"
380 //===----------------------------------------------------------------------===//
382 //===----------------------------------------------------------------------===//
384 def ATTAsmParser : AsmParser {
385 string AsmParserClassName = "AsmParser";
388 def ATTAsmParserVariant : AsmParserVariant {
394 // Discard comments in assembly strings.
395 string CommentDelimiter = "#";
397 // Recognize hard coded registers.
398 string RegisterPrefix = "%";
401 def IntelAsmParserVariant : AsmParserVariant {
405 string Name = "intel";
407 // Discard comments in assembly strings.
408 string CommentDelimiter = ";";
410 // Recognize hard coded registers.
411 string RegisterPrefix = "";
414 //===----------------------------------------------------------------------===//
416 //===----------------------------------------------------------------------===//
418 // The X86 target supports two different syntaxes for emitting machine code.
419 // This is controlled by the -x86-asm-syntax={att|intel}
420 def ATTAsmWriter : AsmWriter {
421 string AsmWriterClassName = "ATTInstPrinter";
424 def IntelAsmWriter : AsmWriter {
425 string AsmWriterClassName = "IntelInstPrinter";
430 // Information about the instructions...
431 let InstructionSet = X86InstrInfo;
432 let AssemblyParsers = [ATTAsmParser];
433 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
434 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];