lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 172                                      "Use LEA for adjusting the stack pointer">;
 173 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 174                                      "HasSlowDivide32", "true",
 175                                      "Use 8-bit divide for positive values less than 256">;
 176 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 177                                      "HasSlowDivide64", "true",
 178                                      "Use 16-bit divide for positive values less than 65536">;
 179 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 180                                      "PadShortFunctions", "true",
 181                                      "Pad short functions">;
 182 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 183                                      "CallRegIndirect", "true",
 184                                      "Call register indirect">;
 185 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 186                                    "LEA instruction needs inputs at AG stage">;
 187 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 188                                    "LEA instruction with certain arguments is slow">;
 189 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 190                                    "INC and DEC instructions are slower than ADD and SUB">;
 191 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
 192                             "Use RSQRT* to optimize square root calculations">;
 193 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
 194                           "true", "Use RCP* to optimize division calculations">;
 195
 196 //===----------------------------------------------------------------------===//
 197 // X86 processors supported.
 198 //===----------------------------------------------------------------------===//
 199
 200 include "X86Schedule.td"
 201
 202 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 203                     "Intel Atom processors">;
 204 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 205                     "Intel Silvermont processors">;
 206
 207 class Proc<string Name, list<SubtargetFeature> Features>
 208  : ProcessorModel<Name, GenericModel, Features>;
 209
 210 def : Proc<"generic",         []>;
 211 def : Proc<"i386",            []>;
 212 def : Proc<"i486",            []>;
 213 def : Proc<"i586",            []>;
 214 def : Proc<"pentium",         []>;
 215 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 216 def : Proc<"i686",            []>;
 217 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 218 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 219 def : Proc<"pentium3",        [FeatureSSE1]>;
 220 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 221 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 222 def : Proc<"pentium4",        [FeatureSSE2]>;
 223 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 224
 225 // Intel Core Duo.
 226 def : ProcessorModel<"yonah", SandyBridgeModel,
 227                      [FeatureSSE3, FeatureSlowBTMem]>;
 228
 229 // NetBurst.
 230 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 231 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 232
 233 // Intel Core 2 Solo/Duo.
 234 def : ProcessorModel<"core2", SandyBridgeModel,
 235                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 236 def : ProcessorModel<"penryn", SandyBridgeModel,
 237                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 238
 239 // Atom CPUs.
 240 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 241                                    ProcIntelAtom,
 242                                    FeatureSSSE3,
 243                                    FeatureCMPXCHG16B,
 244                                    FeatureMOVBE,
 245                                    FeatureSlowBTMem,
 246                                    FeatureLeaForSP,
 247                                    FeatureSlowDivide32,
 248                                    FeatureSlowDivide64,
 249                                    FeatureCallRegIndirect,
 250                                    FeatureLEAUsesAG,
 251                                    FeaturePadShortFunctions
 252                                  ]>;
 253 def : BonnellProc<"bonnell">;
 254 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 255
 256 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 257                                       ProcIntelSLM,
 258                                       FeatureSSE42,
 259                                       FeatureCMPXCHG16B,
 260                                       FeatureMOVBE,
 261                                       FeaturePOPCNT,
 262                                       FeaturePCLMUL,
 263                                       FeatureAES,
 264                                       FeatureSlowDivide64,
 265                                       FeatureCallRegIndirect,
 266                                       FeaturePRFCHW,
 267                                       FeatureSlowLEA,
 268                                       FeatureSlowIncDec,
 269                                       FeatureSlowBTMem,
 270                                       FeatureFastUAMem
 271                                     ]>;
 272 def : SilvermontProc<"silvermont">;
 273 def : SilvermontProc<"slm">; // Legacy alias.
 274
 275 // "Arrandale" along with corei3 and corei5
 276 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 277                                    FeatureSSE42,
 278                                    FeatureCMPXCHG16B,
 279                                    FeatureSlowBTMem,
 280                                    FeatureFastUAMem,
 281                                    FeaturePOPCNT
 282                                  ]>;
 283 def : NehalemProc<"nehalem">;
 284 def : NehalemProc<"corei7">;
 285
 286 // Westmere is a similar machine to nehalem with some additional features.
 287 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 288 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 289                                     FeatureSSE42,
 290                                     FeatureCMPXCHG16B,
 291                                     FeatureSlowBTMem,
 292                                     FeatureFastUAMem,
 293                                     FeaturePOPCNT,
 294                                     FeatureAES,
 295                                     FeaturePCLMUL
 296                                   ]>;
 297 def : WestmereProc<"westmere">;
 298
 299 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 300 // rather than a superset.
 301 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 302                                        FeatureAVX,
 303                                        FeatureCMPXCHG16B,
 304                                        FeatureFastUAMem,
 305                                        FeatureSlowUAMem32,
 306                                        FeaturePOPCNT,
 307                                        FeatureAES,
 308                                        FeaturePCLMUL
 309                                      ]>;
 310 def : SandyBridgeProc<"sandybridge">;
 311 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 312
 313 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 314                                      FeatureAVX,
 315                                      FeatureCMPXCHG16B,
 316                                      FeatureFastUAMem,
 317                                      FeatureSlowUAMem32,
 318                                      FeaturePOPCNT,
 319                                      FeatureAES,
 320                                      FeaturePCLMUL,
 321                                      FeatureRDRAND,
 322                                      FeatureF16C,
 323                                      FeatureFSGSBase
 324                                    ]>;
 325 def : IvyBridgeProc<"ivybridge">;
 326 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 327
 328 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 329                                    FeatureAVX2,
 330                                    FeatureCMPXCHG16B,
 331                                    FeatureFastUAMem,
 332                                    FeaturePOPCNT,
 333                                    FeatureAES,
 334                                    FeaturePCLMUL,
 335                                    FeatureRDRAND,
 336                                    FeatureF16C,
 337                                    FeatureFSGSBase,
 338                                    FeatureMOVBE,
 339                                    FeatureLZCNT,
 340                                    FeatureBMI,
 341                                    FeatureBMI2,
 342                                    FeatureFMA,
 343                                    FeatureRTM,
 344                                    FeatureHLE,
 345                                    FeatureSlowIncDec
 346                                  ]>;
 347 def : HaswellProc<"haswell">;
 348 def : HaswellProc<"core-avx2">; // Legacy alias.
 349
 350 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 351                                      FeatureAVX2,
 352                                      FeatureCMPXCHG16B,
 353                                      FeatureFastUAMem,
 354                                      FeaturePOPCNT,
 355                                      FeatureAES,
 356                                      FeaturePCLMUL,
 357                                      FeatureRDRAND,
 358                                      FeatureF16C,
 359                                      FeatureFSGSBase,
 360                                      FeatureMOVBE,
 361                                      FeatureLZCNT,
 362                                      FeatureBMI,
 363                                      FeatureBMI2,
 364                                      FeatureFMA,
 365                                      FeatureRTM,
 366                                      FeatureHLE,
 367                                      FeatureADX,
 368                                      FeatureRDSEED,
 369                                      FeatureSlowIncDec
 370                                    ]>;
 371 def : BroadwellProc<"broadwell">;
 372
 373 // FIXME: define KNL model
 374 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 375                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 376                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 377                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 378                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 379                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 380                       FeatureSlowIncDec]>;
 381 def : KnightsLandingProc<"knl">;
 382
 383 // FIXME: define SKX model
 384 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 385                      [FeatureAVX512, FeatureCDI,
 386                       FeatureDQI, FeatureBWI, FeatureVLX,
 387                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 388                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 389                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 390                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 391                       FeatureSlowIncDec]>;
 392 def : SkylakeProc<"skylake">;
 393 def : SkylakeProc<"skx">; // Legacy alias.
 394
 395
 396 // AMD CPUs.
 397
 398 def : Proc<"k6",              [FeatureMMX]>;
 399 def : Proc<"k6-2",            [Feature3DNow]>;
 400 def : Proc<"k6-3",            [Feature3DNow]>;
 401 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 402                                FeatureSlowSHLD]>;
 403 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 404                                FeatureSlowSHLD]>;
 405 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 406                                FeatureSlowSHLD]>;
 407 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 408                                FeatureSlowSHLD]>;
 409 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 410                                FeatureSlowSHLD]>;
 411 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 412                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 413 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 414                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 415 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 416                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 417 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 418                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 419 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 420                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 421 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 422                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 423 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 424                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 425 def : Proc<"amdfam10",        [FeatureSSE4A,
 426                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 427                                FeaturePOPCNT, FeatureSlowBTMem,
 428                                FeatureSlowSHLD]>;
 429 def : Proc<"barcelona",       [FeatureSSE4A,
 430                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 431                                FeaturePOPCNT, FeatureSlowBTMem,
 432                                FeatureSlowSHLD]>;
 433 // Bobcat
 434 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 435                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 436                                FeatureSlowSHLD]>;
 437
 438 // Jaguar
 439 def : ProcessorModel<"btver2", BtVer2Model,
 440                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 441                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 442                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 443                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 444                       FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
 445
 446 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 447
 448 // Bulldozer
 449 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 450                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 451                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 452                                FeaturePOPCNT, FeatureSlowSHLD]>;
 453 // Piledriver
 454 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 455                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 456                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 457                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 458                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 459
 460 // Steamroller
 461 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 462                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 463                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 464                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 465                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 466                                FeatureFSGSBase]>;
 467
 468 // Excavator
 469 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 470                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 471                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 472                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 473                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 474                                FeatureFSGSBase]>;
 475
 476 def : Proc<"geode",           [Feature3DNowA]>;
 477
 478 def : Proc<"winchip-c6",      [FeatureMMX]>;
 479 def : Proc<"winchip2",        [Feature3DNow]>;
 480 def : Proc<"c3",              [Feature3DNow]>;
 481 def : Proc<"c3-2",            [FeatureSSE1]>;
 482
 483 // We also provide a generic 64-bit specific x86 processor model which tries to
 484 // be good for modern chips without enabling instruction set encodings past the
 485 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 486 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 487 //
 488 // We currently use the Sandy Bridge model as the default scheduling model as
 489 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 490 // covers a huge swath of x86 processors. If there are specific scheduling
 491 // knobs which need to be tuned differently for AMD chips, we might consider
 492 // forming a common base for them.
 493 def : ProcessorModel<"x86-64", SandyBridgeModel,
 494                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 495                       FeatureFastUAMem]>;
 496
 497 //===----------------------------------------------------------------------===//
 498 // Register File Description
 499 //===----------------------------------------------------------------------===//
 500
 501 include "X86RegisterInfo.td"
 502
 503 //===----------------------------------------------------------------------===//
 504 // Instruction Descriptions
 505 //===----------------------------------------------------------------------===//
 506
 507 include "X86InstrInfo.td"
 508
 509 def X86InstrInfo : InstrInfo;
 510
 511 //===----------------------------------------------------------------------===//
 512 // Calling Conventions
 513 //===----------------------------------------------------------------------===//
 514
 515 include "X86CallingConv.td"
 516
 517
 518 //===----------------------------------------------------------------------===//
 519 // Assembly Parser
 520 //===----------------------------------------------------------------------===//
 521
 522 def ATTAsmParser : AsmParser {
 523   string AsmParserClassName = "AsmParser";
 524 }
 525
 526 def ATTAsmParserVariant : AsmParserVariant {
 527   int Variant = 0;
 528
 529   // Variant name.
 530   string Name = "att";
 531
 532   // Discard comments in assembly strings.
 533   string CommentDelimiter = "#";
 534
 535   // Recognize hard coded registers.
 536   string RegisterPrefix = "%";
 537 }
 538
 539 def IntelAsmParserVariant : AsmParserVariant {
 540   int Variant = 1;
 541
 542   // Variant name.
 543   string Name = "intel";
 544
 545   // Discard comments in assembly strings.
 546   string CommentDelimiter = ";";
 547
 548   // Recognize hard coded registers.
 549   string RegisterPrefix = "";
 550 }
 551
 552 //===----------------------------------------------------------------------===//
 553 // Assembly Printers
 554 //===----------------------------------------------------------------------===//
 555
 556 // The X86 target supports two different syntaxes for emitting machine code.
 557 // This is controlled by the -x86-asm-syntax={att|intel}
 558 def ATTAsmWriter : AsmWriter {
 559   string AsmWriterClassName  = "ATTInstPrinter";
 560   int Variant = 0;
 561 }
 562 def IntelAsmWriter : AsmWriter {
 563   string AsmWriterClassName  = "IntelInstPrinter";
 564   int Variant = 1;
 565 }
 566
 567 def X86 : Target {
 568   // Information about the instructions...
 569   let InstructionSet = X86InstrInfo;
 570   let AssemblyParsers = [ATTAsmParser];
 571   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 572   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 573 }