[X86] Add XSAVE intrinsic family
[oota-llvm.git] / lib / Target / X86 / X86.td
1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
12 //
13 //===----------------------------------------------------------------------===//
14
15 // Get the target-independent interfaces which we are implementing...
16 //
17 include "llvm/Target/Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
21 //
22
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24                                   "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26                                   "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28                                   "16-bit mode (i8086)">;
29
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
33
34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
35                                       "Enable conditional move instructions">;
36
37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38                                        "Support POPCNT instruction">;
39
40 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
41                                        "Support xsave instructions">;
42
43 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
44                                        "Support xsaveopt instructions">;
45
46 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
47                                        "Support xsavec instructions">;
48
49 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
50                                        "Support xsaves instructions">;
51
52 // The MMX subtarget feature is separate from the rest of the SSE features
53 // because it's important (for odd compatibility reasons) to be able to
54 // turn it off explicitly while allowing SSE+ to be on.
55 def FeatureMMX     : SubtargetFeature<"mmx","HasMMX", "true",
56                                       "Enable MMX instructions">;
57
58 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
59                                       "Enable SSE instructions",
60                                       // SSE codegen depends on cmovs, and all
61                                       // SSE1+ processors support them.
62                                       [FeatureCMOV]>;
63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
64                                       "Enable SSE2 instructions",
65                                       [FeatureSSE1]>;
66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
67                                       "Enable SSE3 instructions",
68                                       [FeatureSSE2]>;
69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
70                                       "Enable SSSE3 instructions",
71                                       [FeatureSSE3]>;
72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
73                                       "Enable SSE 4.1 instructions",
74                                       [FeatureSSSE3]>;
75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
76                                       "Enable SSE 4.2 instructions",
77                                       [FeatureSSE41]>;
78 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
79                                       "Enable 3DNow! instructions",
80                                       [FeatureMMX]>;
81 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
82                                       "Enable 3DNow! Athlon instructions",
83                                       [Feature3DNow]>;
84 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
85 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
86 // without disabling 64-bit mode.
87 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
88                                       "Support 64-bit instructions",
89                                       [FeatureCMOV]>;
90 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
91                                       "64-bit with cmpxchg16b",
92                                       [Feature64Bit]>;
93 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
94                                        "Bit testing of memory is slow">;
95 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
96                                        "SHLD instruction is slow">;
97 // FIXME: This should not apply to CPUs that do not have SSE.
98 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
99                                 "IsUAMem16Slow", "true",
100                                 "Slow unaligned 16-byte memory access">;
101 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
102                                 "IsUAMem32Slow", "true",
103                                 "Slow unaligned 32-byte memory access">;
104 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
105                                       "Support SSE 4a instructions",
106                                       [FeatureSSE3]>;
107
108 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
109                                       "Enable AVX instructions",
110                                       [FeatureSSE42]>;
111 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
112                                       "Enable AVX2 instructions",
113                                       [FeatureAVX]>;
114 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
115                                       "Enable AVX-512 instructions",
116                                       [FeatureAVX2]>;
117 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
118                       "Enable AVX-512 Exponential and Reciprocal Instructions",
119                                       [FeatureAVX512]>;
120 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
121                       "Enable AVX-512 Conflict Detection Instructions",
122                                       [FeatureAVX512]>;
123 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
124                       "Enable AVX-512 PreFetch Instructions",
125                                       [FeatureAVX512]>;
126 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
127                       "Enable AVX-512 Doubleword and Quadword Instructions",
128                                       [FeatureAVX512]>;
129 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
130                       "Enable AVX-512 Byte and Word Instructions",
131                                       [FeatureAVX512]>;
132 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
133                       "Enable AVX-512 Vector Length eXtensions",
134                                       [FeatureAVX512]>;
135 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
136                          "Enable packed carry-less multiplication instructions",
137                                [FeatureSSE2]>;
138 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
139                                       "Enable three-operand fused multiple-add",
140                                       [FeatureAVX]>;
141 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
142                                       "Enable four-operand fused multiple-add",
143                                       [FeatureAVX, FeatureSSE4A]>;
144 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
145                                       "Enable XOP instructions",
146                                       [FeatureFMA4]>;
147 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
148                                           "HasSSEUnalignedMem", "true",
149                       "Allow unaligned memory operands with SSE instructions">;
150 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
151                                       "Enable AES instructions",
152                                       [FeatureSSE2]>;
153 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
154                                       "Enable TBM instructions">;
155 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
156                                       "Support MOVBE instruction">;
157 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
158                                       "Support RDRAND instruction">;
159 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
160                        "Support 16-bit floating point conversion instructions",
161                        [FeatureAVX]>;
162 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
163                                        "Support FS/GS Base instructions">;
164 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
165                                       "Support LZCNT instruction">;
166 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
167                                       "Support BMI instructions">;
168 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
169                                       "Support BMI2 instructions">;
170 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
171                                       "Support RTM instructions">;
172 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
173                                       "Support HLE">;
174 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
175                                       "Support ADX instructions">;
176 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
177                                       "Enable SHA instructions",
178                                       [FeatureSSE2]>;
179 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
180                                       "Support PRFCHW instructions">;
181 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
182                                       "Support RDSEED instruction">;
183 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
184                                       "Support MPX instructions">;
185 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
186                                      "Use LEA for adjusting the stack pointer">;
187 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
188                                      "HasSlowDivide32", "true",
189                                      "Use 8-bit divide for positive values less than 256">;
190 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
191                                      "HasSlowDivide64", "true",
192                                      "Use 16-bit divide for positive values less than 65536">;
193 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
194                                      "PadShortFunctions", "true",
195                                      "Pad short functions">;
196 // TODO: This feature ought to be renamed.
197 // What it really refers to are CPUs for which certain instructions
198 // (which ones besides the example below?) are microcoded.
199 // The best examples of this are the memory forms of CALL and PUSH
200 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
201 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
202                                      "CallRegIndirect", "true",
203                                      "Call register indirect">;
204 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
205                                    "LEA instruction needs inputs at AG stage">;
206 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
207                                    "LEA instruction with certain arguments is slow">;
208 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
209                                    "INC and DEC instructions are slower than ADD and SUB">;
210 def FeatureSoftFloat
211     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
212                        "Use software floating point features.">;
213
214 //===----------------------------------------------------------------------===//
215 // X86 processors supported.
216 //===----------------------------------------------------------------------===//
217
218 include "X86Schedule.td"
219
220 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
221                     "Intel Atom processors">;
222 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
223                     "Intel Silvermont processors">;
224
225 class Proc<string Name, list<SubtargetFeature> Features>
226  : ProcessorModel<Name, GenericModel, Features>;
227
228 def : Proc<"generic",         [FeatureSlowUAMem16]>;
229 def : Proc<"i386",            [FeatureSlowUAMem16]>;
230 def : Proc<"i486",            [FeatureSlowUAMem16]>;
231 def : Proc<"i586",            [FeatureSlowUAMem16]>;
232 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
233 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
234 def : Proc<"i686",            [FeatureSlowUAMem16]>;
235 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
236 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
237 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
238 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
239                                FeatureSlowBTMem]>;
240 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
241                                FeatureSlowBTMem]>;
242 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
243 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
244                                FeatureSlowBTMem]>;
245
246 // Intel Core Duo.
247 def : ProcessorModel<
248           "yonah", SandyBridgeModel,
249           [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
250
251 // NetBurst.
252 def : Proc<"prescott",
253            [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
254 def : Proc<"nocona", [
255   FeatureSlowUAMem16,
256   FeatureMMX,
257   FeatureSSE3,
258   FeatureCMPXCHG16B,
259   FeatureSlowBTMem
260 ]>;
261
262 // Intel Core 2 Solo/Duo.
263 def : ProcessorModel<"core2", SandyBridgeModel, [
264   FeatureSlowUAMem16,
265   FeatureMMX,
266   FeatureSSSE3,
267   FeatureCMPXCHG16B,
268   FeatureSlowBTMem
269 ]>;
270 def : ProcessorModel<"penryn", SandyBridgeModel, [
271   FeatureSlowUAMem16,
272   FeatureMMX,
273   FeatureSSE41,
274   FeatureCMPXCHG16B,
275   FeatureSlowBTMem
276 ]>;
277
278 // Atom CPUs.
279 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
280   ProcIntelAtom,
281   FeatureSlowUAMem16,
282   FeatureMMX,
283   FeatureSSSE3,
284   FeatureCMPXCHG16B,
285   FeatureMOVBE,
286   FeatureSlowBTMem,
287   FeatureLeaForSP,
288   FeatureSlowDivide32,
289   FeatureSlowDivide64,
290   FeatureCallRegIndirect,
291   FeatureLEAUsesAG,
292   FeaturePadShortFunctions
293 ]>;
294 def : BonnellProc<"bonnell">;
295 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
296
297 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
298   ProcIntelSLM,
299   FeatureMMX,
300   FeatureSSE42,
301   FeatureCMPXCHG16B,
302   FeatureMOVBE,
303   FeaturePOPCNT,
304   FeaturePCLMUL,
305   FeatureAES,
306   FeatureSlowDivide64,
307   FeatureCallRegIndirect,
308   FeaturePRFCHW,
309   FeatureSlowLEA,
310   FeatureSlowIncDec,
311   FeatureSlowBTMem
312 ]>;
313 def : SilvermontProc<"silvermont">;
314 def : SilvermontProc<"slm">; // Legacy alias.
315
316 // "Arrandale" along with corei3 and corei5
317 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
318   FeatureMMX,
319   FeatureSSE42,
320   FeatureCMPXCHG16B,
321   FeatureSlowBTMem,
322   FeaturePOPCNT
323 ]>;
324 def : NehalemProc<"nehalem">;
325 def : NehalemProc<"corei7">;
326
327 // Westmere is a similar machine to nehalem with some additional features.
328 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
329 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
330   FeatureMMX,
331   FeatureSSE42,
332   FeatureCMPXCHG16B,
333   FeatureSlowBTMem,
334   FeaturePOPCNT,
335   FeatureAES,
336   FeaturePCLMUL
337 ]>;
338 def : WestmereProc<"westmere">;
339
340 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
341 // rather than a superset.
342 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
343   FeatureMMX,
344   FeatureAVX,
345   FeatureCMPXCHG16B,
346   FeatureSlowBTMem,
347   FeatureSlowUAMem32,
348   FeaturePOPCNT,
349   FeatureAES,
350   FeaturePCLMUL
351 ]>;
352 def : SandyBridgeProc<"sandybridge">;
353 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
354
355 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
356   FeatureMMX,
357   FeatureAVX,
358   FeatureCMPXCHG16B,
359   FeatureSlowBTMem,
360   FeatureSlowUAMem32,
361   FeaturePOPCNT,
362   FeatureAES,
363   FeaturePCLMUL,
364   FeatureRDRAND,
365   FeatureF16C,
366   FeatureFSGSBase
367 ]>;
368 def : IvyBridgeProc<"ivybridge">;
369 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
370
371 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
372   FeatureMMX,
373   FeatureAVX2,
374   FeatureCMPXCHG16B,
375   FeatureSlowBTMem,
376   FeaturePOPCNT,
377   FeatureAES,
378   FeaturePCLMUL,
379   FeatureRDRAND,
380   FeatureF16C,
381   FeatureFSGSBase,
382   FeatureMOVBE,
383   FeatureLZCNT,
384   FeatureBMI,
385   FeatureBMI2,
386   FeatureFMA,
387   FeatureRTM,
388   FeatureHLE,
389   FeatureSlowIncDec
390 ]>;
391 def : HaswellProc<"haswell">;
392 def : HaswellProc<"core-avx2">; // Legacy alias.
393
394 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
395   FeatureMMX,
396   FeatureAVX2,
397   FeatureCMPXCHG16B,
398   FeatureSlowBTMem,
399   FeaturePOPCNT,
400   FeatureAES,
401   FeaturePCLMUL,
402   FeatureRDRAND,
403   FeatureF16C,
404   FeatureFSGSBase,
405   FeatureMOVBE,
406   FeatureLZCNT,
407   FeatureBMI,
408   FeatureBMI2,
409   FeatureFMA,
410   FeatureRTM,
411   FeatureHLE,
412   FeatureADX,
413   FeatureRDSEED,
414   FeatureSlowIncDec
415 ]>;
416 def : BroadwellProc<"broadwell">;
417
418 // FIXME: define KNL model
419 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
420   FeatureMMX,
421   FeatureAVX512,
422   FeatureERI,
423   FeatureCDI,
424   FeaturePFI,
425   FeatureCMPXCHG16B,
426   FeaturePOPCNT,
427   FeatureAES,
428   FeaturePCLMUL,
429   FeatureRDRAND,
430   FeatureF16C,
431   FeatureFSGSBase,
432   FeatureMOVBE,
433   FeatureLZCNT,
434   FeatureBMI,
435   FeatureBMI2,
436   FeatureFMA,
437   FeatureRTM,
438   FeatureHLE,
439   FeatureSlowIncDec,
440   FeatureMPX
441 ]>;
442 def : KnightsLandingProc<"knl">;
443
444 // FIXME: define SKX model
445 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
446   FeatureMMX,
447   FeatureAVX512,
448   FeatureCDI,
449   FeatureDQI,
450   FeatureBWI,
451   FeatureVLX,
452   FeatureCMPXCHG16B,
453   FeatureSlowBTMem,
454   FeaturePOPCNT,
455   FeatureAES,
456   FeaturePCLMUL,
457   FeatureRDRAND,
458   FeatureF16C,
459   FeatureFSGSBase,
460   FeatureMOVBE,
461   FeatureLZCNT,
462   FeatureBMI,
463   FeatureBMI2,
464   FeatureFMA,
465   FeatureRTM,
466   FeatureHLE,
467   FeatureADX,
468   FeatureRDSEED,
469   FeatureSlowIncDec,
470   FeatureMPX
471 ]>;
472 def : SkylakeProc<"skylake">;
473 def : SkylakeProc<"skx">; // Legacy alias.
474
475
476 // AMD CPUs.
477
478 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
479 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
480 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
481 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
482                                FeatureSlowBTMem, FeatureSlowSHLD]>;
483 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
484                                FeatureSlowBTMem, FeatureSlowSHLD]>;
485 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
486                                FeatureSlowBTMem, FeatureSlowSHLD]>;
487 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
488                                FeatureSlowBTMem, FeatureSlowSHLD]>;
489 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
490                                FeatureSlowBTMem, FeatureSlowSHLD]>;
491 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
492                                Feature64Bit, FeatureSlowBTMem,
493                                FeatureSlowSHLD]>;
494 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
495                                Feature64Bit, FeatureSlowBTMem,
496                                FeatureSlowSHLD]>;
497 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
498                                Feature64Bit, FeatureSlowBTMem,
499                                FeatureSlowSHLD]>;
500 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
501                                Feature64Bit, FeatureSlowBTMem,
502                                FeatureSlowSHLD]>;
503 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
504                                FeatureCMPXCHG16B, FeatureSlowBTMem,
505                                FeatureSlowSHLD]>;
506 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
507                                FeatureCMPXCHG16B, FeatureSlowBTMem,
508                                FeatureSlowSHLD]>;
509 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
510                                FeatureCMPXCHG16B, FeatureSlowBTMem,
511                                FeatureSlowSHLD]>;
512 def : Proc<"amdfam10",        [FeatureSSE4A,
513                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
514                                FeaturePOPCNT, FeatureSlowBTMem,
515                                FeatureSlowSHLD]>;
516 def : Proc<"barcelona",       [FeatureSSE4A,
517                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
518                                FeaturePOPCNT, FeatureSlowBTMem,
519                                FeatureSlowSHLD]>;
520
521 // Bobcat
522 def : Proc<"btver1", [
523   FeatureMMX,
524   FeatureSSSE3,
525   FeatureSSE4A,
526   FeatureCMPXCHG16B,
527   FeaturePRFCHW,
528   FeatureLZCNT,
529   FeaturePOPCNT,
530   FeatureSlowSHLD
531 ]>;
532
533 // Jaguar
534 def : ProcessorModel<"btver2", BtVer2Model, [
535   FeatureMMX,
536   FeatureAVX,
537   FeatureSSE4A,
538   FeatureCMPXCHG16B,
539   FeaturePRFCHW,
540   FeatureAES,
541   FeaturePCLMUL,
542   FeatureBMI,
543   FeatureF16C,
544   FeatureMOVBE,
545   FeatureLZCNT,
546   FeaturePOPCNT,
547   FeatureSlowSHLD
548 ]>;
549
550 // Bulldozer
551 def : Proc<"bdver1", [
552   FeatureXOP,
553   FeatureFMA4,
554   FeatureCMPXCHG16B,
555   FeatureAES,
556   FeaturePRFCHW,
557   FeaturePCLMUL,
558   FeatureMMX,
559   FeatureAVX,
560   FeatureSSE4A,
561   FeatureLZCNT,
562   FeaturePOPCNT,
563   FeatureSlowSHLD
564 ]>;
565 // Piledriver
566 def : Proc<"bdver2", [
567   FeatureXOP,
568   FeatureFMA4,
569   FeatureCMPXCHG16B,
570   FeatureAES,
571   FeaturePRFCHW,
572   FeaturePCLMUL,
573   FeatureMMX,
574   FeatureAVX,
575   FeatureSSE4A,
576   FeatureF16C,
577   FeatureLZCNT,
578   FeaturePOPCNT,
579   FeatureBMI,
580   FeatureTBM,
581   FeatureFMA,
582   FeatureSlowSHLD
583 ]>;
584
585 // Steamroller
586 def : Proc<"bdver3", [
587   FeatureXOP,
588   FeatureFMA4,
589   FeatureCMPXCHG16B,
590   FeatureAES,
591   FeaturePRFCHW,
592   FeaturePCLMUL,
593   FeatureMMX,
594   FeatureAVX,
595   FeatureSSE4A,
596   FeatureF16C,
597   FeatureLZCNT,
598   FeaturePOPCNT,
599   FeatureBMI,
600   FeatureTBM,
601   FeatureFMA,
602   FeatureSlowSHLD,
603   FeatureFSGSBase
604 ]>;
605
606 // Excavator
607 def : Proc<"bdver4", [
608   FeatureMMX,
609   FeatureAVX2,
610   FeatureXOP,
611   FeatureFMA4,
612   FeatureCMPXCHG16B,
613   FeatureAES,
614   FeaturePRFCHW,
615   FeaturePCLMUL,
616   FeatureF16C,
617   FeatureLZCNT,
618   FeaturePOPCNT,
619   FeatureBMI,
620   FeatureBMI2,
621   FeatureTBM,
622   FeatureFMA,
623   FeatureSSE4A,
624   FeatureFSGSBase
625 ]>;
626
627 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
628
629 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
630 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
631 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
632 def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
633
634 // We also provide a generic 64-bit specific x86 processor model which tries to
635 // be good for modern chips without enabling instruction set encodings past the
636 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
637 // modern 64-bit x86 chip, and enables features that are generally beneficial.
638 //
639 // We currently use the Sandy Bridge model as the default scheduling model as
640 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
641 // covers a huge swath of x86 processors. If there are specific scheduling
642 // knobs which need to be tuned differently for AMD chips, we might consider
643 // forming a common base for them.
644 def : ProcessorModel<
645           "x86-64", SandyBridgeModel,
646           [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
647
648 //===----------------------------------------------------------------------===//
649 // Register File Description
650 //===----------------------------------------------------------------------===//
651
652 include "X86RegisterInfo.td"
653
654 //===----------------------------------------------------------------------===//
655 // Instruction Descriptions
656 //===----------------------------------------------------------------------===//
657
658 include "X86InstrInfo.td"
659
660 def X86InstrInfo : InstrInfo;
661
662 //===----------------------------------------------------------------------===//
663 // Calling Conventions
664 //===----------------------------------------------------------------------===//
665
666 include "X86CallingConv.td"
667
668
669 //===----------------------------------------------------------------------===//
670 // Assembly Parser
671 //===----------------------------------------------------------------------===//
672
673 def ATTAsmParser : AsmParser {
674   string AsmParserClassName = "AsmParser";
675 }
676
677 def ATTAsmParserVariant : AsmParserVariant {
678   int Variant = 0;
679
680   // Variant name.
681   string Name = "att";
682
683   // Discard comments in assembly strings.
684   string CommentDelimiter = "#";
685
686   // Recognize hard coded registers.
687   string RegisterPrefix = "%";
688 }
689
690 def IntelAsmParserVariant : AsmParserVariant {
691   int Variant = 1;
692
693   // Variant name.
694   string Name = "intel";
695
696   // Discard comments in assembly strings.
697   string CommentDelimiter = ";";
698
699   // Recognize hard coded registers.
700   string RegisterPrefix = "";
701 }
702
703 //===----------------------------------------------------------------------===//
704 // Assembly Printers
705 //===----------------------------------------------------------------------===//
706
707 // The X86 target supports two different syntaxes for emitting machine code.
708 // This is controlled by the -x86-asm-syntax={att|intel}
709 def ATTAsmWriter : AsmWriter {
710   string AsmWriterClassName  = "ATTInstPrinter";
711   int Variant = 0;
712 }
713 def IntelAsmWriter : AsmWriter {
714   string AsmWriterClassName  = "IntelInstPrinter";
715   int Variant = 1;
716 }
717
718 def X86 : Target {
719   // Information about the instructions...
720   let InstructionSet = X86InstrInfo;
721   let AssemblyParsers = [ATTAsmParser];
722   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
723   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
724 }