lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // X86 Subtarget features
  28 //===----------------------------------------------------------------------===//
  29
  30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  31                                       "Enable conditional move instructions">;
  32
  33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  34                                        "Support POPCNT instruction">;
  35
  36
  37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  38                                       "Enable MMX instructions">;
  39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  40                                       "Enable SSE instructions",
  41                                       // SSE codegen depends on cmovs, and all
  42                                       // SSE1+ processors support them.
  43                                       [FeatureMMX, FeatureCMOV]>;
  44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  45                                       "Enable SSE2 instructions",
  46                                       [FeatureSSE1]>;
  47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  48                                       "Enable SSE3 instructions",
  49                                       [FeatureSSE2]>;
  50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  51                                       "Enable SSSE3 instructions",
  52                                       [FeatureSSE3]>;
  53 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  54                                       "Enable SSE 4.1 instructions",
  55                                       [FeatureSSSE3]>;
  56 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  57                                       "Enable SSE 4.2 instructions",
  58                                       [FeatureSSE41]>;
  59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  60                                       "Enable 3DNow! instructions",
  61                                       [FeatureMMX]>;
  62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  63                                       "Enable 3DNow! Athlon instructions",
  64                                       [Feature3DNow]>;
  65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  67 // without disabling 64-bit mode.
  68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  69                                       "Support 64-bit instructions",
  70                                       [FeatureCMOV]>;
  71 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  72                                       "64-bit with cmpxchg16b",
  73                                       [Feature64Bit]>;
  74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  75                                        "Bit testing of memory is slow">;
  76 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  77                                        "SHLD instruction is slow">;
  78 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  79                                         "IsUAMemFast", "true",
  80                                         "Fast unaligned memory access">;
  81 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  82                                       "Support SSE 4a instructions",
  83                                       [FeatureSSE3]>;
  84
  85 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  86                                       "Enable AVX instructions",
  87                                       [FeatureSSE42]>;
  88 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  89                                       "Enable AVX2 instructions",
  90                                       [FeatureAVX]>;
  91 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
  92                                       "Enable AVX-512 instructions",
  93                                       [FeatureAVX2]>;
  94 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
  95                       "Enable AVX-512 Exponential and Reciprocal Instructions",
  96                                       [FeatureAVX512]>;
  97 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
  98                       "Enable AVX-512 Conflict Detection Instructions",
  99                                       [FeatureAVX512]>;
 100 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 101                       "Enable AVX-512 PreFetch Instructions",
 102                                       [FeatureAVX512]>;
 103
 104 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 105                          "Enable packed carry-less multiplication instructions",
 106                                [FeatureSSE2]>;
 107 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 108                                       "Enable three-operand fused multiple-add",
 109                                       [FeatureAVX]>;
 110 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 111                                       "Enable four-operand fused multiple-add",
 112                                       [FeatureAVX, FeatureSSE4A]>;
 113 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 114                                       "Enable XOP instructions",
 115                                       [FeatureFMA4]>;
 116 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 117                                           "HasVectorUAMem", "true",
 118                  "Allow unaligned memory operands on vector/SIMD instructions">;
 119 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 120                                       "Enable AES instructions",
 121                                       [FeatureSSE2]>;
 122 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 123                                       "Enable TBM instructions">;
 124 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 125                                       "Support MOVBE instruction">;
 126 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 127                                       "Support RDRAND instruction">;
 128 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 129                        "Support 16-bit floating point conversion instructions",
 130                        [FeatureAVX]>;
 131 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 132                                        "Support FS/GS Base instructions">;
 133 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 134                                       "Support LZCNT instruction">;
 135 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 136                                       "Support BMI instructions">;
 137 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 138                                       "Support BMI2 instructions">;
 139 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 140                                       "Support RTM instructions">;
 141 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 142                                       "Support HLE">;
 143 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 144                                       "Support ADX instructions">;
 145 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 146                                       "Enable SHA instructions",
 147                                       [FeatureSSE2]>;
 148 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 149                                       "Support PRFCHW instructions">;
 150 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 151                                       "Support RDSEED instruction">;
 152 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 153                                      "Use LEA for adjusting the stack pointer">;
 154 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
 155                                      "HasSlowDivide", "true",
 156                                      "Use small divide for positive values less than 256">;
 157 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 158                                      "PadShortFunctions", "true",
 159                                      "Pad short functions">;
 160 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 161                                      "CallRegIndirect", "true",
 162                                      "Call register indirect">;
 163 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 164                                    "LEA instruction needs inputs at AG stage">;
 165
 166 //===----------------------------------------------------------------------===//
 167 // X86 processors supported.
 168 //===----------------------------------------------------------------------===//
 169
 170 include "X86Schedule.td"
 171
 172 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 173                     "Intel Atom processors">;
 174 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 175                     "Intel Silvermont processors">;
 176
 177 class Proc<string Name, list<SubtargetFeature> Features>
 178  : ProcessorModel<Name, GenericModel, Features>;
 179
 180 def : Proc<"generic",         []>;
 181 def : Proc<"i386",            []>;
 182 def : Proc<"i486",            []>;
 183 def : Proc<"i586",            []>;
 184 def : Proc<"pentium",         []>;
 185 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 186 def : Proc<"i686",            []>;
 187 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 188 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 189 def : Proc<"pentium3",        [FeatureSSE1]>;
 190 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 191 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 192 def : Proc<"pentium4",        [FeatureSSE2]>;
 193 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 194 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 195                                FeatureFastUAMem]>;
 196 // Intel Core Duo.
 197 def : ProcessorModel<"yonah", SandyBridgeModel,
 198                      [FeatureSSE3, FeatureSlowBTMem]>;
 199
 200 // NetBurst.
 201 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 202 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 203
 204 // Intel Core 2 Solo/Duo.
 205 def : ProcessorModel<"core2", SandyBridgeModel,
 206                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 207 def : ProcessorModel<"penryn", SandyBridgeModel,
 208                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 209
 210 // Atom.
 211 def : ProcessorModel<"atom", AtomModel,
 212                      [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
 213                       FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
 214                       FeatureSlowDivide,
 215                       FeatureCallRegIndirect,
 216                       FeatureLEAUsesAG,
 217                       FeaturePadShortFunctions]>;
 218
 219 // Atom Silvermont.
 220 def : ProcessorModel<"slm",  SLMModel, [ProcIntelSLM,
 221                                FeatureSSE42, FeatureCMPXCHG16B,
 222                                FeatureMOVBE, FeaturePOPCNT,
 223                                FeaturePCLMUL, FeatureAES,
 224                                FeatureCallRegIndirect,
 225                                FeaturePRFCHW,
 226                                FeatureSlowBTMem]>;
 227 // "Arrandale" along with corei3 and corei5
 228 def : ProcessorModel<"corei7", SandyBridgeModel,
 229                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 230                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
 231
 232 def : ProcessorModel<"nehalem", SandyBridgeModel,
 233                      [FeatureSSE42,  FeatureCMPXCHG16B, FeatureSlowBTMem,
 234                       FeatureFastUAMem, FeaturePOPCNT]>;
 235 // Westmere is a similar machine to nehalem with some additional features.
 236 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 237 def : ProcessorModel<"westmere", SandyBridgeModel,
 238                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 239                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
 240                       FeaturePCLMUL]>;
 241 // Sandy Bridge
 242 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 243 // rather than a superset.
 244 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
 245                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 246                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
 247 // Ivy Bridge
 248 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
 249                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 250                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 251                       FeatureF16C, FeatureFSGSBase]>;
 252
 253 // Haswell
 254 def : ProcessorModel<"core-avx2", HaswellModel,
 255                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
 256                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 257                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 258                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 259                       FeatureHLE]>;
 260
 261 // KNL
 262 // FIXME: define KNL model
 263 def : ProcessorModel<"knl", HaswellModel,
 264                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 265                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 266                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 267                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 268                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
 269
 270 def : Proc<"k6",              [FeatureMMX]>;
 271 def : Proc<"k6-2",            [Feature3DNow]>;
 272 def : Proc<"k6-3",            [Feature3DNow]>;
 273 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 274                                FeatureSlowSHLD]>;
 275 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 276                                FeatureSlowSHLD]>;
 277 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 278                                FeatureSlowSHLD]>;
 279 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 280                                FeatureSlowSHLD]>;
 281 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 282                                FeatureSlowSHLD]>;
 283 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 284                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 285 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 286                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 287 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 288                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 289 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 290                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 291 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 292                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 293 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 294                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 295 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 296                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 297 def : Proc<"amdfam10",        [FeatureSSE4A,
 298                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 299                                FeaturePOPCNT, FeatureSlowBTMem,
 300                                FeatureSlowSHLD]>;
 301 // Bobcat
 302 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 303                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 304                                FeatureSlowSHLD]>;
 305 // Jaguar
 306 def : Proc<"btver2",          [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 307                                FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 308                                FeatureBMI, FeatureF16C, FeatureMOVBE,
 309                                FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
 310 // Bulldozer
 311 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 312                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 313                                FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
 314 // Piledriver
 315 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 316                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 317                                FeatureF16C, FeatureLZCNT,
 318                                FeaturePOPCNT, FeatureBMI, FeatureTBM,
 319                                FeatureFMA, FeatureSlowSHLD]>;
 320
 321 // Steamroller
 322 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 323                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 324                                FeatureF16C, FeatureLZCNT,
 325                                FeaturePOPCNT, FeatureBMI,  FeatureTBM,
 326                                FeatureFMA, FeatureFSGSBase]>;
 327
 328 def : Proc<"geode",           [Feature3DNowA]>;
 329
 330 def : Proc<"winchip-c6",      [FeatureMMX]>;
 331 def : Proc<"winchip2",        [Feature3DNow]>;
 332 def : Proc<"c3",              [Feature3DNow]>;
 333 def : Proc<"c3-2",            [FeatureSSE1]>;
 334
 335 //===----------------------------------------------------------------------===//
 336 // Register File Description
 337 //===----------------------------------------------------------------------===//
 338
 339 include "X86RegisterInfo.td"
 340
 341 //===----------------------------------------------------------------------===//
 342 // Instruction Descriptions
 343 //===----------------------------------------------------------------------===//
 344
 345 include "X86InstrInfo.td"
 346
 347 def X86InstrInfo : InstrInfo;
 348
 349 //===----------------------------------------------------------------------===//
 350 // Calling Conventions
 351 //===----------------------------------------------------------------------===//
 352
 353 include "X86CallingConv.td"
 354
 355
 356 //===----------------------------------------------------------------------===//
 357 // Assembly Parser
 358 //===----------------------------------------------------------------------===//
 359
 360 def ATTAsmParser : AsmParser {
 361   string AsmParserClassName = "AsmParser";
 362 }
 363
 364 def ATTAsmParserVariant : AsmParserVariant {
 365   int Variant = 0;
 366
 367   // Variant name.
 368   string Name = "att";
 369
 370   // Discard comments in assembly strings.
 371   string CommentDelimiter = "#";
 372
 373   // Recognize hard coded registers.
 374   string RegisterPrefix = "%";
 375 }
 376
 377 def IntelAsmParserVariant : AsmParserVariant {
 378   int Variant = 1;
 379
 380   // Variant name.
 381   string Name = "intel";
 382
 383   // Discard comments in assembly strings.
 384   string CommentDelimiter = ";";
 385
 386   // Recognize hard coded registers.
 387   string RegisterPrefix = "";
 388 }
 389
 390 //===----------------------------------------------------------------------===//
 391 // Assembly Printers
 392 //===----------------------------------------------------------------------===//
 393
 394 // The X86 target supports two different syntaxes for emitting machine code.
 395 // This is controlled by the -x86-asm-syntax={att|intel}
 396 def ATTAsmWriter : AsmWriter {
 397   string AsmWriterClassName  = "ATTInstPrinter";
 398   int Variant = 0;
 399 }
 400 def IntelAsmWriter : AsmWriter {
 401   string AsmWriterClassName  = "IntelInstPrinter";
 402   int Variant = 1;
 403 }
 404
 405 def X86 : Target {
 406   // Information about the instructions...
 407   let InstructionSet = X86InstrInfo;
 408   let AssemblyParsers = [ATTAsmParser];
 409   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 410   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 411 }