lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  83                                         "IsUAMemFast", "true",
  84                                         "Fast unaligned memory access">;
  85 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  86                                       "Support SSE 4a instructions",
  87                                       [FeatureSSE3]>;
  88
  89 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  90                                       "Enable AVX instructions",
  91                                       [FeatureSSE42]>;
  92 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  93                                       "Enable AVX2 instructions",
  94                                       [FeatureAVX]>;
  95 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
  96                                       "Enable AVX-512 instructions",
  97                                       [FeatureAVX2]>;
  98 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
  99                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 100                                       [FeatureAVX512]>;
 101 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 102                       "Enable AVX-512 Conflict Detection Instructions",
 103                                       [FeatureAVX512]>;
 104 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 105                       "Enable AVX-512 PreFetch Instructions",
 106                                       [FeatureAVX512]>;
 107 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 108                       "Enable AVX-512 Doubleword and Quadword Instructions",
 109                                       [FeatureAVX512]>;
 110 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 111                       "Enable AVX-512 Byte and Word Instructions",
 112                                       [FeatureAVX512]>;
 113 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 114                       "Enable AVX-512 Vector Length eXtensions",
 115                                       [FeatureAVX512]>;
 116 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 117                          "Enable packed carry-less multiplication instructions",
 118                                [FeatureSSE2]>;
 119 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 120                                       "Enable three-operand fused multiple-add",
 121                                       [FeatureAVX]>;
 122 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 123                                       "Enable four-operand fused multiple-add",
 124                                       [FeatureAVX, FeatureSSE4A]>;
 125 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 126                                       "Enable XOP instructions",
 127                                       [FeatureFMA4]>;
 128 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 129                                           "HasVectorUAMem", "true",
 130                  "Allow unaligned memory operands on vector/SIMD instructions">;
 131 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 132                                       "Enable AES instructions",
 133                                       [FeatureSSE2]>;
 134 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 135                                       "Enable TBM instructions">;
 136 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 137                                       "Support MOVBE instruction">;
 138 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 139                                       "Support RDRAND instruction">;
 140 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 141                        "Support 16-bit floating point conversion instructions",
 142                        [FeatureAVX]>;
 143 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 144                                        "Support FS/GS Base instructions">;
 145 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 146                                       "Support LZCNT instruction">;
 147 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 148                                       "Support BMI instructions">;
 149 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 150                                       "Support BMI2 instructions">;
 151 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 152                                       "Support RTM instructions">;
 153 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 154                                       "Support HLE">;
 155 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 156                                       "Support ADX instructions">;
 157 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 158                                       "Enable SHA instructions",
 159                                       [FeatureSSE2]>;
 160 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 161                                       "Support SGX instructions">;
 162 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 163                                       "Support PRFCHW instructions">;
 164 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 165                                       "Support RDSEED instruction">;
 166 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 167                                      "Use LEA for adjusting the stack pointer">;
 168 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
 169                                      "HasSlowDivide", "true",
 170                                      "Use small divide for positive values less than 256">;
 171 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 172                                      "PadShortFunctions", "true",
 173                                      "Pad short functions">;
 174 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 175                                      "CallRegIndirect", "true",
 176                                      "Call register indirect">;
 177 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 178                                    "LEA instruction needs inputs at AG stage">;
 179 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 180                                    "LEA instruction with certain arguments is slow">;
 181 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 182                                    "INC and DEC instructions are slower than ADD and SUB">;
 183
 184 //===----------------------------------------------------------------------===//
 185 // X86 processors supported.
 186 //===----------------------------------------------------------------------===//
 187
 188 include "X86Schedule.td"
 189
 190 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 191                     "Intel Atom processors">;
 192 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 193                     "Intel Silvermont processors">;
 194
 195 class Proc<string Name, list<SubtargetFeature> Features>
 196  : ProcessorModel<Name, GenericModel, Features>;
 197
 198 def : Proc<"generic",         []>;
 199 def : Proc<"i386",            []>;
 200 def : Proc<"i486",            []>;
 201 def : Proc<"i586",            []>;
 202 def : Proc<"pentium",         []>;
 203 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 204 def : Proc<"i686",            []>;
 205 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 206 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 207 def : Proc<"pentium3",        [FeatureSSE1]>;
 208 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 209 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 210 def : Proc<"pentium4",        [FeatureSSE2]>;
 211 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 212
 213 // Intel Core Duo.
 214 def : ProcessorModel<"yonah", SandyBridgeModel,
 215                      [FeatureSSE3, FeatureSlowBTMem]>;
 216
 217 // NetBurst.
 218 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 219 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 220
 221 // Intel Core 2 Solo/Duo.
 222 def : ProcessorModel<"core2", SandyBridgeModel,
 223                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 224 def : ProcessorModel<"penryn", SandyBridgeModel,
 225                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 226
 227 // Atom.
 228 def : ProcessorModel<"atom", AtomModel,
 229                      [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
 230                       FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
 231                       FeatureSlowDivide,
 232                       FeatureCallRegIndirect,
 233                       FeatureLEAUsesAG,
 234                       FeaturePadShortFunctions]>;
 235
 236 // Atom Silvermont.
 237 def : ProcessorModel<"slm",  SLMModel, [ProcIntelSLM,
 238                                FeatureSSE42, FeatureCMPXCHG16B,
 239                                FeatureMOVBE, FeaturePOPCNT,
 240                                FeaturePCLMUL, FeatureAES,
 241                                FeatureCallRegIndirect,
 242                                FeaturePRFCHW,
 243                                FeatureSlowLEA, FeatureSlowIncDec,
 244                                FeatureSlowBTMem, FeatureFastUAMem]>;
 245 // "Arrandale" along with corei3 and corei5
 246 def : ProcessorModel<"corei7", SandyBridgeModel,
 247                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 248                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
 249
 250 def : ProcessorModel<"nehalem", SandyBridgeModel,
 251                      [FeatureSSE42,  FeatureCMPXCHG16B, FeatureSlowBTMem,
 252                       FeatureFastUAMem, FeaturePOPCNT]>;
 253 // Westmere is a similar machine to nehalem with some additional features.
 254 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 255 def : ProcessorModel<"westmere", SandyBridgeModel,
 256                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 257                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
 258                       FeaturePCLMUL]>;
 259 // Sandy Bridge
 260 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 261 // rather than a superset.
 262 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
 263                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 264                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
 265 // Ivy Bridge
 266 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
 267                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 268                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 269                       FeatureF16C, FeatureFSGSBase]>;
 270
 271 // Haswell
 272 def : ProcessorModel<"core-avx2", HaswellModel,
 273                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
 274                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 275                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 276                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 277                       FeatureHLE]>;
 278
 279 // KNL
 280 // FIXME: define KNL model
 281 def : ProcessorModel<"knl", HaswellModel,
 282                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 283                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 284                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 285                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 286                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 287                       FeatureSlowIncDec]>;
 288
 289 // SKX
 290 // FIXME: define SKX model
 291 def : ProcessorModel<"skx", HaswellModel,
 292                      [FeatureAVX512, FeatureCDI,
 293                       FeatureDQI, FeatureBWI, FeatureVLX,
 294                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 295                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 296                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 297                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 298                       FeatureSlowIncDec, FeatureSGX]>;
 299
 300 def : Proc<"k6",              [FeatureMMX]>;
 301 def : Proc<"k6-2",            [Feature3DNow]>;
 302 def : Proc<"k6-3",            [Feature3DNow]>;
 303 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 304                                FeatureSlowSHLD]>;
 305 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 306                                FeatureSlowSHLD]>;
 307 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 308                                FeatureSlowSHLD]>;
 309 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 310                                FeatureSlowSHLD]>;
 311 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 312                                FeatureSlowSHLD]>;
 313 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 314                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 315 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 316                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 317 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 318                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 319 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 320                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 321 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 322                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 323 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 324                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 325 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 326                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 327 def : Proc<"amdfam10",        [FeatureSSE4A,
 328                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 329                                FeaturePOPCNT, FeatureSlowBTMem,
 330                                FeatureSlowSHLD]>;
 331 // Bobcat
 332 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 333                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 334                                FeatureSlowSHLD]>;
 335 // Jaguar
 336 def : Proc<"btver2",          [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 337                                FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 338                                FeatureBMI, FeatureF16C, FeatureMOVBE,
 339                                FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
 340 // Bulldozer
 341 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 342                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 343                                FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
 344 // Piledriver
 345 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 346                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 347                                FeatureF16C, FeatureLZCNT,
 348                                FeaturePOPCNT, FeatureBMI, FeatureTBM,
 349                                FeatureFMA, FeatureSlowSHLD]>;
 350
 351 // Steamroller
 352 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 353                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 354                                FeatureF16C, FeatureLZCNT,
 355                                FeaturePOPCNT, FeatureBMI,  FeatureTBM,
 356                                FeatureFMA, FeatureFSGSBase]>;
 357
 358 // Excavator
 359 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 360                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 361                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 362                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 363                                FeatureTBM, FeatureFMA, FeatureFSGSBase]>;
 364
 365 def : Proc<"geode",           [Feature3DNowA]>;
 366
 367 def : Proc<"winchip-c6",      [FeatureMMX]>;
 368 def : Proc<"winchip2",        [Feature3DNow]>;
 369 def : Proc<"c3",              [Feature3DNow]>;
 370 def : Proc<"c3-2",            [FeatureSSE1]>;
 371
 372 // We also provide a generic 64-bit specific x86 processor model which tries to
 373 // be good for modern chips without enabling instruction set encodings past the
 374 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 375 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 376 //
 377 // We currently use the Sandy Bridge model as the default scheduling model as
 378 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 379 // covers a huge swath of x86 processors. If there are specific scheduling
 380 // knobs which need to be tuned differently for AMD chips, we might consider
 381 // forming a common base for them.
 382 def : ProcessorModel<"x86-64", SandyBridgeModel,
 383                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 384                       FeatureFastUAMem]>;
 385
 386 //===----------------------------------------------------------------------===//
 387 // Register File Description
 388 //===----------------------------------------------------------------------===//
 389
 390 include "X86RegisterInfo.td"
 391
 392 //===----------------------------------------------------------------------===//
 393 // Instruction Descriptions
 394 //===----------------------------------------------------------------------===//
 395
 396 include "X86InstrInfo.td"
 397
 398 def X86InstrInfo : InstrInfo;
 399
 400 //===----------------------------------------------------------------------===//
 401 // Calling Conventions
 402 //===----------------------------------------------------------------------===//
 403
 404 include "X86CallingConv.td"
 405
 406
 407 //===----------------------------------------------------------------------===//
 408 // Assembly Parser
 409 //===----------------------------------------------------------------------===//
 410
 411 def ATTAsmParser : AsmParser {
 412   string AsmParserClassName = "AsmParser";
 413 }
 414
 415 def ATTAsmParserVariant : AsmParserVariant {
 416   int Variant = 0;
 417
 418   // Variant name.
 419   string Name = "att";
 420
 421   // Discard comments in assembly strings.
 422   string CommentDelimiter = "#";
 423
 424   // Recognize hard coded registers.
 425   string RegisterPrefix = "%";
 426 }
 427
 428 def IntelAsmParserVariant : AsmParserVariant {
 429   int Variant = 1;
 430
 431   // Variant name.
 432   string Name = "intel";
 433
 434   // Discard comments in assembly strings.
 435   string CommentDelimiter = ";";
 436
 437   // Recognize hard coded registers.
 438   string RegisterPrefix = "";
 439 }
 440
 441 //===----------------------------------------------------------------------===//
 442 // Assembly Printers
 443 //===----------------------------------------------------------------------===//
 444
 445 // The X86 target supports two different syntaxes for emitting machine code.
 446 // This is controlled by the -x86-asm-syntax={att|intel}
 447 def ATTAsmWriter : AsmWriter {
 448   string AsmWriterClassName  = "ATTInstPrinter";
 449   int Variant = 0;
 450 }
 451 def IntelAsmWriter : AsmWriter {
 452   string AsmWriterClassName  = "IntelInstPrinter";
 453   int Variant = 1;
 454 }
 455
 456 def X86 : Target {
 457   // Information about the instructions...
 458   let InstructionSet = X86InstrInfo;
 459   let AssemblyParsers = [ATTAsmParser];
 460   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 461   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 462 }