lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  41                                       "Support fxsave/fxrestore instructions">;
  42
  43 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  44                                        "Support xsave instructions">;
  45
  46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  47                                        "Support xsaveopt instructions">;
  48
  49 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  50                                        "Support xsavec instructions">;
  51
  52 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  53                                        "Support xsaves instructions">;
  54
  55 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  56                                       "Enable SSE instructions",
  57                                       // SSE codegen depends on cmovs, and all
  58                                       // SSE1+ processors support them.
  59                                       [FeatureCMOV]>;
  60 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  61                                       "Enable SSE2 instructions",
  62                                       [FeatureSSE1]>;
  63 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  64                                       "Enable SSE3 instructions",
  65                                       [FeatureSSE2]>;
  66 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  67                                       "Enable SSSE3 instructions",
  68                                       [FeatureSSE3]>;
  69 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  70                                       "Enable SSE 4.1 instructions",
  71                                       [FeatureSSSE3]>;
  72 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  73                                       "Enable SSE 4.2 instructions",
  74                                       [FeatureSSE41]>;
  75 // The MMX subtarget feature is separate from the rest of the SSE features
  76 // because it's important (for odd compatibility reasons) to be able to
  77 // turn it off explicitly while allowing SSE+ to be on.
  78 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  79                                       "Enable MMX instructions">;
  80 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  81                                       "Enable 3DNow! instructions",
  82                                       [FeatureMMX]>;
  83 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  84                                       "Enable 3DNow! Athlon instructions",
  85                                       [Feature3DNow]>;
  86 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  87 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  88 // without disabling 64-bit mode.
  89 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  90                                       "Support 64-bit instructions",
  91                                       [FeatureCMOV]>;
  92 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  93                                       "64-bit with cmpxchg16b",
  94                                       [Feature64Bit]>;
  95 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  96                                        "Bit testing of memory is slow">;
  97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  98                                        "SHLD instruction is slow">;
  99 // FIXME: This should not apply to CPUs that do not have SSE.
 100 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 101                                 "IsUAMem16Slow", "true",
 102                                 "Slow unaligned 16-byte memory access">;
 103 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 104                                 "IsUAMem32Slow", "true",
 105                                 "Slow unaligned 32-byte memory access">;
 106 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 107                                       "Support SSE 4a instructions",
 108                                       [FeatureSSE3]>;
 109
 110 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 111                                       "Enable AVX instructions",
 112                                       [FeatureSSE42]>;
 113 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 114                                       "Enable AVX2 instructions",
 115                                       [FeatureAVX]>;
 116 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 117                                       "Enable AVX-512 instructions",
 118                                       [FeatureAVX2]>;
 119 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 120                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 121                                       [FeatureAVX512]>;
 122 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 123                       "Enable AVX-512 Conflict Detection Instructions",
 124                                       [FeatureAVX512]>;
 125 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 126                       "Enable AVX-512 PreFetch Instructions",
 127                                       [FeatureAVX512]>;
 128 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 129                       "Enable AVX-512 Doubleword and Quadword Instructions",
 130                                       [FeatureAVX512]>;
 131 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 132                       "Enable AVX-512 Byte and Word Instructions",
 133                                       [FeatureAVX512]>;
 134 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 135                       "Enable AVX-512 Vector Length eXtensions",
 136                                       [FeatureAVX512]>;
 137 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 138                       "Enable protection keys">;
 139 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 140                          "Enable packed carry-less multiplication instructions",
 141                                [FeatureSSE2]>;
 142 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 143                                       "Enable three-operand fused multiple-add",
 144                                       [FeatureAVX]>;
 145 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 146                                       "Enable four-operand fused multiple-add",
 147                                       [FeatureAVX, FeatureSSE4A]>;
 148 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 149                                       "Enable XOP instructions",
 150                                       [FeatureFMA4]>;
 151 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 152                                           "HasSSEUnalignedMem", "true",
 153                       "Allow unaligned memory operands with SSE instructions">;
 154 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 155                                       "Enable AES instructions",
 156                                       [FeatureSSE2]>;
 157 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 158                                       "Enable TBM instructions">;
 159 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 160                                       "Support MOVBE instruction">;
 161 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 162                                       "Support RDRAND instruction">;
 163 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 164                        "Support 16-bit floating point conversion instructions",
 165                        [FeatureAVX]>;
 166 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 167                                        "Support FS/GS Base instructions">;
 168 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 169                                       "Support LZCNT instruction">;
 170 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 171                                       "Support BMI instructions">;
 172 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 173                                       "Support BMI2 instructions">;
 174 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 175                                       "Support RTM instructions">;
 176 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 177                                       "Support HLE">;
 178 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 179                                       "Support ADX instructions">;
 180 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 181                                       "Enable SHA instructions",
 182                                       [FeatureSSE2]>;
 183 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 184                                       "Support PRFCHW instructions">;
 185 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 186                                       "Support RDSEED instruction">;
 187 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 188                                        "Support LAHF and SAHF instructions">;
 189 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 190                                       "Support MPX instructions">;
 191 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 192                                      "Use LEA for adjusting the stack pointer">;
 193 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 194                                      "HasSlowDivide32", "true",
 195                                      "Use 8-bit divide for positive values less than 256">;
 196 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 197                                      "HasSlowDivide64", "true",
 198                                      "Use 16-bit divide for positive values less than 65536">;
 199 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 200                                      "PadShortFunctions", "true",
 201                                      "Pad short functions">;
 202 // TODO: This feature ought to be renamed.
 203 // What it really refers to are CPUs for which certain instructions
 204 // (which ones besides the example below?) are microcoded.
 205 // The best examples of this are the memory forms of CALL and PUSH
 206 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 207 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 208                                      "CallRegIndirect", "true",
 209                                      "Call register indirect">;
 210 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 211                                    "LEA instruction needs inputs at AG stage">;
 212 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 213                                    "LEA instruction with certain arguments is slow">;
 214 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 215                                    "INC and DEC instructions are slower than ADD and SUB">;
 216 def FeatureSoftFloat
 217     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 218                        "Use software floating point features.">;
 219
 220 //===----------------------------------------------------------------------===//
 221 // X86 processors supported.
 222 //===----------------------------------------------------------------------===//
 223
 224 include "X86Schedule.td"
 225
 226 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 227                     "Intel Atom processors">;
 228 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 229                     "Intel Silvermont processors">;
 230
 231 class Proc<string Name, list<SubtargetFeature> Features>
 232  : ProcessorModel<Name, GenericModel, Features>;
 233
 234 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 235 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 236 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 237 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 238 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 239 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 240 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 241 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 242 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
 243                                FeatureFXSR]>;
 244 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 245                                FeatureFXSR]>;
 246 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 247                                FeatureFXSR, FeatureSlowBTMem]>;
 248 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 249                                FeatureFXSR, FeatureSlowBTMem]>;
 250 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 251                                FeatureFXSR]>;
 252 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 253                                FeatureFXSR, FeatureSlowBTMem]>;
 254
 255 // Intel Core Duo.
 256 def : ProcessorModel<"yonah", SandyBridgeModel,
 257                      [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 258                       FeatureSlowBTMem]>;
 259
 260 // NetBurst.
 261 def : Proc<"prescott",
 262            [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 263             FeatureSlowBTMem]>;
 264 def : Proc<"nocona", [
 265   FeatureSlowUAMem16,
 266   FeatureMMX,
 267   FeatureSSE3,
 268   FeatureFXSR,
 269   FeatureCMPXCHG16B,
 270   FeatureSlowBTMem
 271 ]>;
 272
 273 // Intel Core 2 Solo/Duo.
 274 def : ProcessorModel<"core2", SandyBridgeModel, [
 275   FeatureSlowUAMem16,
 276   FeatureMMX,
 277   FeatureSSSE3,
 278   FeatureFXSR,
 279   FeatureCMPXCHG16B,
 280   FeatureSlowBTMem,
 281   FeatureLAHFSAHF
 282 ]>;
 283 def : ProcessorModel<"penryn", SandyBridgeModel, [
 284   FeatureSlowUAMem16,
 285   FeatureMMX,
 286   FeatureSSE41,
 287   FeatureFXSR,
 288   FeatureCMPXCHG16B,
 289   FeatureSlowBTMem,
 290   FeatureLAHFSAHF
 291 ]>;
 292
 293 // Atom CPUs.
 294 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 295   ProcIntelAtom,
 296   FeatureSlowUAMem16,
 297   FeatureMMX,
 298   FeatureSSSE3,
 299   FeatureFXSR,
 300   FeatureCMPXCHG16B,
 301   FeatureMOVBE,
 302   FeatureSlowBTMem,
 303   FeatureLEAForSP,
 304   FeatureSlowDivide32,
 305   FeatureSlowDivide64,
 306   FeatureCallRegIndirect,
 307   FeatureLEAUsesAG,
 308   FeaturePadShortFunctions,
 309   FeatureLAHFSAHF
 310 ]>;
 311 def : BonnellProc<"bonnell">;
 312 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 313
 314 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 315   ProcIntelSLM,
 316   FeatureMMX,
 317   FeatureSSE42,
 318   FeatureFXSR,
 319   FeatureCMPXCHG16B,
 320   FeatureMOVBE,
 321   FeaturePOPCNT,
 322   FeaturePCLMUL,
 323   FeatureAES,
 324   FeatureSlowDivide64,
 325   FeatureCallRegIndirect,
 326   FeaturePRFCHW,
 327   FeatureSlowLEA,
 328   FeatureSlowIncDec,
 329   FeatureSlowBTMem,
 330   FeatureLAHFSAHF
 331 ]>;
 332 def : SilvermontProc<"silvermont">;
 333 def : SilvermontProc<"slm">; // Legacy alias.
 334
 335 // "Arrandale" along with corei3 and corei5
 336 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 337   FeatureMMX,
 338   FeatureSSE42,
 339   FeatureFXSR,
 340   FeatureCMPXCHG16B,
 341   FeatureSlowBTMem,
 342   FeaturePOPCNT,
 343   FeatureLAHFSAHF
 344 ]>;
 345 def : NehalemProc<"nehalem">;
 346 def : NehalemProc<"corei7">;
 347
 348 // Westmere is a similar machine to nehalem with some additional features.
 349 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 350 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 351   FeatureMMX,
 352   FeatureSSE42,
 353   FeatureFXSR,
 354   FeatureCMPXCHG16B,
 355   FeatureSlowBTMem,
 356   FeaturePOPCNT,
 357   FeatureAES,
 358   FeaturePCLMUL,
 359   FeatureLAHFSAHF
 360 ]>;
 361 def : WestmereProc<"westmere">;
 362
 363 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 364 // rather than a superset.
 365 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 366   FeatureMMX,
 367   FeatureAVX,
 368   FeatureFXSR,
 369   FeatureCMPXCHG16B,
 370   FeatureSlowBTMem,
 371   FeatureSlowUAMem32,
 372   FeaturePOPCNT,
 373   FeatureAES,
 374   FeaturePCLMUL,
 375   FeatureXSAVE,
 376   FeatureXSAVEOPT,
 377   FeatureLAHFSAHF
 378 ]>;
 379 def : SandyBridgeProc<"sandybridge">;
 380 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 381
 382 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 383   FeatureMMX,
 384   FeatureAVX,
 385   FeatureFXSR,
 386   FeatureCMPXCHG16B,
 387   FeatureSlowBTMem,
 388   FeatureSlowUAMem32,
 389   FeaturePOPCNT,
 390   FeatureAES,
 391   FeaturePCLMUL,
 392   FeatureXSAVE,
 393   FeatureXSAVEOPT,
 394   FeatureRDRAND,
 395   FeatureF16C,
 396   FeatureFSGSBase,
 397   FeatureLAHFSAHF
 398 ]>;
 399 def : IvyBridgeProc<"ivybridge">;
 400 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 401
 402 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 403   FeatureMMX,
 404   FeatureAVX2,
 405   FeatureFXSR,
 406   FeatureCMPXCHG16B,
 407   FeatureSlowBTMem,
 408   FeaturePOPCNT,
 409   FeatureAES,
 410   FeaturePCLMUL,
 411   FeatureRDRAND,
 412   FeatureXSAVE,
 413   FeatureXSAVEOPT,
 414   FeatureF16C,
 415   FeatureFSGSBase,
 416   FeatureMOVBE,
 417   FeatureLZCNT,
 418   FeatureBMI,
 419   FeatureBMI2,
 420   FeatureFMA,
 421   FeatureRTM,
 422   FeatureHLE,
 423   FeatureSlowIncDec,
 424   FeatureLAHFSAHF
 425 ]>;
 426 def : HaswellProc<"haswell">;
 427 def : HaswellProc<"core-avx2">; // Legacy alias.
 428
 429 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 430   FeatureMMX,
 431   FeatureAVX2,
 432   FeatureFXSR,
 433   FeatureCMPXCHG16B,
 434   FeatureSlowBTMem,
 435   FeaturePOPCNT,
 436   FeatureAES,
 437   FeaturePCLMUL,
 438   FeatureXSAVE,
 439   FeatureXSAVEOPT,
 440   FeatureRDRAND,
 441   FeatureF16C,
 442   FeatureFSGSBase,
 443   FeatureMOVBE,
 444   FeatureLZCNT,
 445   FeatureBMI,
 446   FeatureBMI2,
 447   FeatureFMA,
 448   FeatureRTM,
 449   FeatureHLE,
 450   FeatureADX,
 451   FeatureRDSEED,
 452   FeatureSlowIncDec,
 453   FeatureLAHFSAHF
 454 ]>;
 455 def : BroadwellProc<"broadwell">;
 456
 457 // FIXME: define KNL model
 458 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
 459   FeatureMMX,
 460   FeatureAVX512,
 461   FeatureFXSR,
 462   FeatureERI,
 463   FeatureCDI,
 464   FeaturePFI,
 465   FeatureCMPXCHG16B,
 466   FeaturePOPCNT,
 467   FeatureAES,
 468   FeaturePCLMUL,
 469   FeatureXSAVE,
 470   FeatureXSAVEOPT,
 471   FeatureRDRAND,
 472   FeatureF16C,
 473   FeatureFSGSBase,
 474   FeatureMOVBE,
 475   FeatureLZCNT,
 476   FeatureBMI,
 477   FeatureBMI2,
 478   FeatureFMA,
 479   FeatureRTM,
 480   FeatureHLE,
 481   FeatureSlowIncDec,
 482   FeatureMPX,
 483   FeatureLAHFSAHF
 484 ]>;
 485 def : KnightsLandingProc<"knl">;
 486
 487 // FIXME: define SKX model
 488 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
 489   FeatureMMX,
 490   FeatureAVX512,
 491   FeatureFXSR,
 492   FeatureCDI,
 493   FeatureDQI,
 494   FeatureBWI,
 495   FeatureVLX,
 496   FeaturePKU,
 497   FeatureCMPXCHG16B,
 498   FeatureSlowBTMem,
 499   FeaturePOPCNT,
 500   FeatureAES,
 501   FeaturePCLMUL,
 502   FeatureXSAVE,
 503   FeatureXSAVEOPT,
 504   FeatureRDRAND,
 505   FeatureF16C,
 506   FeatureFSGSBase,
 507   FeatureMOVBE,
 508   FeatureLZCNT,
 509   FeatureBMI,
 510   FeatureBMI2,
 511   FeatureFMA,
 512   FeatureRTM,
 513   FeatureHLE,
 514   FeatureADX,
 515   FeatureRDSEED,
 516   FeatureSlowIncDec,
 517   FeatureMPX,
 518   FeatureXSAVEC,
 519   FeatureXSAVES,
 520   FeatureLAHFSAHF
 521 ]>;
 522 def : SkylakeProc<"skylake">;
 523 def : SkylakeProc<"skx">; // Legacy alias.
 524
 525
 526 // AMD CPUs.
 527
 528 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 529 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 530 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 531 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 532                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 533 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 534                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 535 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 536                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 537 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 538                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 539 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 540                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 541 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 542                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 543                                FeatureSlowSHLD]>;
 544 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 545                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 546                                FeatureSlowSHLD]>;
 547 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 548                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 549                                FeatureSlowSHLD]>;
 550 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 551                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 552                                FeatureSlowSHLD]>;
 553 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 554                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 555                                FeatureSlowSHLD]>;
 556 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 557                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 558                                FeatureSlowSHLD]>;
 559 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 560                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 561                                FeatureSlowSHLD]>;
 562 def : Proc<"amdfam10",        [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 563                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 564                                FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
 565 def : Proc<"barcelona",       [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 566                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 567                                FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
 568
 569 // Bobcat
 570 def : Proc<"btver1", [
 571   FeatureMMX,
 572   FeatureSSSE3,
 573   FeatureSSE4A,
 574   FeatureFXSR,
 575   FeatureCMPXCHG16B,
 576   FeaturePRFCHW,
 577   FeatureLZCNT,
 578   FeaturePOPCNT,
 579   FeatureXSAVE,
 580   FeatureSlowSHLD,
 581   FeatureLAHFSAHF
 582 ]>;
 583
 584 // Jaguar
 585 def : ProcessorModel<"btver2", BtVer2Model, [
 586   FeatureMMX,
 587   FeatureAVX,
 588   FeatureFXSR,
 589   FeatureSSE4A,
 590   FeatureCMPXCHG16B,
 591   FeaturePRFCHW,
 592   FeatureAES,
 593   FeaturePCLMUL,
 594   FeatureBMI,
 595   FeatureF16C,
 596   FeatureMOVBE,
 597   FeatureLZCNT,
 598   FeaturePOPCNT,
 599   FeatureXSAVE,
 600   FeatureXSAVEOPT,
 601   FeatureSlowSHLD,
 602   FeatureLAHFSAHF
 603 ]>;
 604
 605 // Bulldozer
 606 def : Proc<"bdver1", [
 607   FeatureXOP,
 608   FeatureFMA4,
 609   FeatureCMPXCHG16B,
 610   FeatureAES,
 611   FeaturePRFCHW,
 612   FeaturePCLMUL,
 613   FeatureMMX,
 614   FeatureAVX,
 615   FeatureFXSR,
 616   FeatureSSE4A,
 617   FeatureLZCNT,
 618   FeaturePOPCNT,
 619   FeatureXSAVE,
 620   FeatureSlowSHLD,
 621   FeatureLAHFSAHF
 622 ]>;
 623 // Piledriver
 624 def : Proc<"bdver2", [
 625   FeatureXOP,
 626   FeatureFMA4,
 627   FeatureCMPXCHG16B,
 628   FeatureAES,
 629   FeaturePRFCHW,
 630   FeaturePCLMUL,
 631   FeatureMMX,
 632   FeatureAVX,
 633   FeatureFXSR,
 634   FeatureSSE4A,
 635   FeatureF16C,
 636   FeatureLZCNT,
 637   FeaturePOPCNT,
 638   FeatureXSAVE,
 639   FeatureBMI,
 640   FeatureTBM,
 641   FeatureFMA,
 642   FeatureSlowSHLD,
 643   FeatureLAHFSAHF
 644 ]>;
 645
 646 // Steamroller
 647 def : Proc<"bdver3", [
 648   FeatureXOP,
 649   FeatureFMA4,
 650   FeatureCMPXCHG16B,
 651   FeatureAES,
 652   FeaturePRFCHW,
 653   FeaturePCLMUL,
 654   FeatureMMX,
 655   FeatureAVX,
 656   FeatureFXSR,
 657   FeatureSSE4A,
 658   FeatureF16C,
 659   FeatureLZCNT,
 660   FeaturePOPCNT,
 661   FeatureXSAVE,
 662   FeatureBMI,
 663   FeatureTBM,
 664   FeatureFMA,
 665   FeatureXSAVEOPT,
 666   FeatureSlowSHLD,
 667   FeatureFSGSBase,
 668   FeatureLAHFSAHF
 669 ]>;
 670
 671 // Excavator
 672 def : Proc<"bdver4", [
 673   FeatureMMX,
 674   FeatureAVX2,
 675   FeatureFXSR,
 676   FeatureXOP,
 677   FeatureFMA4,
 678   FeatureCMPXCHG16B,
 679   FeatureAES,
 680   FeaturePRFCHW,
 681   FeaturePCLMUL,
 682   FeatureF16C,
 683   FeatureLZCNT,
 684   FeaturePOPCNT,
 685   FeatureXSAVE,
 686   FeatureBMI,
 687   FeatureBMI2,
 688   FeatureTBM,
 689   FeatureFMA,
 690   FeatureXSAVEOPT,
 691   FeatureFSGSBase,
 692   FeatureLAHFSAHF
 693 ]>;
 694
 695 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 696
 697 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 698 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 699 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 700 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
 701
 702 // We also provide a generic 64-bit specific x86 processor model which tries to
 703 // be good for modern chips without enabling instruction set encodings past the
 704 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 705 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 706 //
 707 // We currently use the Sandy Bridge model as the default scheduling model as
 708 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 709 // covers a huge swath of x86 processors. If there are specific scheduling
 710 // knobs which need to be tuned differently for AMD chips, we might consider
 711 // forming a common base for them.
 712 def : ProcessorModel<"x86-64", SandyBridgeModel,
 713                      [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
 714                       FeatureSlowBTMem ]>;
 715
 716 //===----------------------------------------------------------------------===//
 717 // Register File Description
 718 //===----------------------------------------------------------------------===//
 719
 720 include "X86RegisterInfo.td"
 721
 722 //===----------------------------------------------------------------------===//
 723 // Instruction Descriptions
 724 //===----------------------------------------------------------------------===//
 725
 726 include "X86InstrInfo.td"
 727
 728 def X86InstrInfo : InstrInfo;
 729
 730 //===----------------------------------------------------------------------===//
 731 // Calling Conventions
 732 //===----------------------------------------------------------------------===//
 733
 734 include "X86CallingConv.td"
 735
 736
 737 //===----------------------------------------------------------------------===//
 738 // Assembly Parser
 739 //===----------------------------------------------------------------------===//
 740
 741 def ATTAsmParserVariant : AsmParserVariant {
 742   int Variant = 0;
 743
 744   // Variant name.
 745   string Name = "att";
 746
 747   // Discard comments in assembly strings.
 748   string CommentDelimiter = "#";
 749
 750   // Recognize hard coded registers.
 751   string RegisterPrefix = "%";
 752 }
 753
 754 def IntelAsmParserVariant : AsmParserVariant {
 755   int Variant = 1;
 756
 757   // Variant name.
 758   string Name = "intel";
 759
 760   // Discard comments in assembly strings.
 761   string CommentDelimiter = ";";
 762
 763   // Recognize hard coded registers.
 764   string RegisterPrefix = "";
 765 }
 766
 767 //===----------------------------------------------------------------------===//
 768 // Assembly Printers
 769 //===----------------------------------------------------------------------===//
 770
 771 // The X86 target supports two different syntaxes for emitting machine code.
 772 // This is controlled by the -x86-asm-syntax={att|intel}
 773 def ATTAsmWriter : AsmWriter {
 774   string AsmWriterClassName  = "ATTInstPrinter";
 775   int Variant = 0;
 776 }
 777 def IntelAsmWriter : AsmWriter {
 778   string AsmWriterClassName  = "IntelInstPrinter";
 779   int Variant = 1;
 780 }
 781
 782 def X86 : Target {
 783   // Information about the instructions...
 784   let InstructionSet = X86InstrInfo;
 785   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 786   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 787 }