lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 172                                       "Support MPX instructions">;
 173 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 174                                      "Use LEA for adjusting the stack pointer">;
 175 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 176                                      "HasSlowDivide32", "true",
 177                                      "Use 8-bit divide for positive values less than 256">;
 178 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 179                                      "HasSlowDivide64", "true",
 180                                      "Use 16-bit divide for positive values less than 65536">;
 181 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 182                                      "PadShortFunctions", "true",
 183                                      "Pad short functions">;
 184 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 185                                      "CallRegIndirect", "true",
 186                                      "Call register indirect">;
 187 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 188                                    "LEA instruction needs inputs at AG stage">;
 189 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 190                                    "LEA instruction with certain arguments is slow">;
 191 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 192                                    "INC and DEC instructions are slower than ADD and SUB">;
 193 def FeatureSoftFloat
 194     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 195                        "Use software floating point features.">;
 196
 197 //===----------------------------------------------------------------------===//
 198 // X86 processors supported.
 199 //===----------------------------------------------------------------------===//
 200
 201 include "X86Schedule.td"
 202
 203 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 204                     "Intel Atom processors">;
 205 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 206                     "Intel Silvermont processors">;
 207
 208 class Proc<string Name, list<SubtargetFeature> Features>
 209  : ProcessorModel<Name, GenericModel, Features>;
 210
 211 def : Proc<"generic",         []>;
 212 def : Proc<"i386",            []>;
 213 def : Proc<"i486",            []>;
 214 def : Proc<"i586",            []>;
 215 def : Proc<"pentium",         []>;
 216 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 217 def : Proc<"i686",            []>;
 218 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 219 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 220 def : Proc<"pentium3",        [FeatureSSE1]>;
 221 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 222 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 223 def : Proc<"pentium4",        [FeatureSSE2]>;
 224 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 225
 226 // Intel Core Duo.
 227 def : ProcessorModel<"yonah", SandyBridgeModel,
 228                      [FeatureSSE3, FeatureSlowBTMem]>;
 229
 230 // NetBurst.
 231 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 232 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 233
 234 // Intel Core 2 Solo/Duo.
 235 def : ProcessorModel<"core2", SandyBridgeModel,
 236                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 237 def : ProcessorModel<"penryn", SandyBridgeModel,
 238                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 239
 240 // Atom CPUs.
 241 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 242                                    ProcIntelAtom,
 243                                    FeatureSSSE3,
 244                                    FeatureCMPXCHG16B,
 245                                    FeatureMOVBE,
 246                                    FeatureSlowBTMem,
 247                                    FeatureLeaForSP,
 248                                    FeatureSlowDivide32,
 249                                    FeatureSlowDivide64,
 250                                    FeatureCallRegIndirect,
 251                                    FeatureLEAUsesAG,
 252                                    FeaturePadShortFunctions
 253                                  ]>;
 254 def : BonnellProc<"bonnell">;
 255 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 256
 257 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 258                                       ProcIntelSLM,
 259                                       FeatureSSE42,
 260                                       FeatureCMPXCHG16B,
 261                                       FeatureMOVBE,
 262                                       FeaturePOPCNT,
 263                                       FeaturePCLMUL,
 264                                       FeatureAES,
 265                                       FeatureSlowDivide64,
 266                                       FeatureCallRegIndirect,
 267                                       FeaturePRFCHW,
 268                                       FeatureSlowLEA,
 269                                       FeatureSlowIncDec,
 270                                       FeatureSlowBTMem,
 271                                       FeatureFastUAMem
 272                                     ]>;
 273 def : SilvermontProc<"silvermont">;
 274 def : SilvermontProc<"slm">; // Legacy alias.
 275
 276 // "Arrandale" along with corei3 and corei5
 277 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 278                                    FeatureSSE42,
 279                                    FeatureCMPXCHG16B,
 280                                    FeatureSlowBTMem,
 281                                    FeatureFastUAMem,
 282                                    FeaturePOPCNT
 283                                  ]>;
 284 def : NehalemProc<"nehalem">;
 285 def : NehalemProc<"corei7">;
 286
 287 // Westmere is a similar machine to nehalem with some additional features.
 288 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 289 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 290                                     FeatureSSE42,
 291                                     FeatureCMPXCHG16B,
 292                                     FeatureSlowBTMem,
 293                                     FeatureFastUAMem,
 294                                     FeaturePOPCNT,
 295                                     FeatureAES,
 296                                     FeaturePCLMUL
 297                                   ]>;
 298 def : WestmereProc<"westmere">;
 299
 300 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 301 // rather than a superset.
 302 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 303                                        FeatureAVX,
 304                                        FeatureCMPXCHG16B,
 305                                        FeatureFastUAMem,
 306                                        FeatureSlowUAMem32,
 307                                        FeaturePOPCNT,
 308                                        FeatureAES,
 309                                        FeaturePCLMUL
 310                                      ]>;
 311 def : SandyBridgeProc<"sandybridge">;
 312 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 313
 314 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 315                                      FeatureAVX,
 316                                      FeatureCMPXCHG16B,
 317                                      FeatureFastUAMem,
 318                                      FeatureSlowUAMem32,
 319                                      FeaturePOPCNT,
 320                                      FeatureAES,
 321                                      FeaturePCLMUL,
 322                                      FeatureRDRAND,
 323                                      FeatureF16C,
 324                                      FeatureFSGSBase
 325                                    ]>;
 326 def : IvyBridgeProc<"ivybridge">;
 327 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 328
 329 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 330                                    FeatureAVX2,
 331                                    FeatureCMPXCHG16B,
 332                                    FeatureFastUAMem,
 333                                    FeaturePOPCNT,
 334                                    FeatureAES,
 335                                    FeaturePCLMUL,
 336                                    FeatureRDRAND,
 337                                    FeatureF16C,
 338                                    FeatureFSGSBase,
 339                                    FeatureMOVBE,
 340                                    FeatureLZCNT,
 341                                    FeatureBMI,
 342                                    FeatureBMI2,
 343                                    FeatureFMA,
 344                                    FeatureRTM,
 345                                    FeatureHLE,
 346                                    FeatureSlowIncDec
 347                                  ]>;
 348 def : HaswellProc<"haswell">;
 349 def : HaswellProc<"core-avx2">; // Legacy alias.
 350
 351 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 352                                      FeatureAVX2,
 353                                      FeatureCMPXCHG16B,
 354                                      FeatureFastUAMem,
 355                                      FeaturePOPCNT,
 356                                      FeatureAES,
 357                                      FeaturePCLMUL,
 358                                      FeatureRDRAND,
 359                                      FeatureF16C,
 360                                      FeatureFSGSBase,
 361                                      FeatureMOVBE,
 362                                      FeatureLZCNT,
 363                                      FeatureBMI,
 364                                      FeatureBMI2,
 365                                      FeatureFMA,
 366                                      FeatureRTM,
 367                                      FeatureHLE,
 368                                      FeatureADX,
 369                                      FeatureRDSEED,
 370                                      FeatureSlowIncDec
 371                                    ]>;
 372 def : BroadwellProc<"broadwell">;
 373
 374 // FIXME: define KNL model
 375 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 376                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 377                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 378                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 379                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 380                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 381                       FeatureSlowIncDec, FeatureMPX]>;
 382 def : KnightsLandingProc<"knl">;
 383
 384 // FIXME: define SKX model
 385 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 386                      [FeatureAVX512, FeatureCDI,
 387                       FeatureDQI, FeatureBWI, FeatureVLX,
 388                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 389                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 390                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 391                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 392                       FeatureSlowIncDec, FeatureMPX]>;
 393 def : SkylakeProc<"skylake">;
 394 def : SkylakeProc<"skx">; // Legacy alias.
 395
 396
 397 // AMD CPUs.
 398
 399 def : Proc<"k6",              [FeatureMMX]>;
 400 def : Proc<"k6-2",            [Feature3DNow]>;
 401 def : Proc<"k6-3",            [Feature3DNow]>;
 402 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 403                                FeatureSlowSHLD]>;
 404 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 405                                FeatureSlowSHLD]>;
 406 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 407                                FeatureSlowSHLD]>;
 408 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 409                                FeatureSlowSHLD]>;
 410 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 411                                FeatureSlowSHLD]>;
 412 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 413                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 414 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 415                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 416 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 417                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 418 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 419                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 420 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 421                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 422 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 423                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 424 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 425                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 426 def : Proc<"amdfam10",        [FeatureSSE4A,
 427                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 428                                FeaturePOPCNT, FeatureSlowBTMem,
 429                                FeatureSlowSHLD]>;
 430 def : Proc<"barcelona",       [FeatureSSE4A,
 431                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 432                                FeaturePOPCNT, FeatureSlowBTMem,
 433                                FeatureSlowSHLD]>;
 434 // Bobcat
 435 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 436                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 437                                FeatureSlowSHLD]>;
 438
 439 // Jaguar
 440 def : ProcessorModel<"btver2", BtVer2Model,
 441                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 442                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 443                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 444                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 445                       FeatureSlowSHLD]>;
 446
 447 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 448
 449 // Bulldozer
 450 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 451                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 452                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 453                                FeaturePOPCNT, FeatureSlowSHLD]>;
 454 // Piledriver
 455 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 456                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 457                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 458                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 459                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 460
 461 // Steamroller
 462 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 463                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 464                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 465                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 466                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 467                                FeatureFSGSBase]>;
 468
 469 // Excavator
 470 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 471                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 472                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 473                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 474                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 475                                FeatureFSGSBase]>;
 476
 477 def : Proc<"geode",           [Feature3DNowA]>;
 478
 479 def : Proc<"winchip-c6",      [FeatureMMX]>;
 480 def : Proc<"winchip2",        [Feature3DNow]>;
 481 def : Proc<"c3",              [Feature3DNow]>;
 482 def : Proc<"c3-2",            [FeatureSSE1]>;
 483
 484 // We also provide a generic 64-bit specific x86 processor model which tries to
 485 // be good for modern chips without enabling instruction set encodings past the
 486 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 487 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 488 //
 489 // We currently use the Sandy Bridge model as the default scheduling model as
 490 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 491 // covers a huge swath of x86 processors. If there are specific scheduling
 492 // knobs which need to be tuned differently for AMD chips, we might consider
 493 // forming a common base for them.
 494 def : ProcessorModel<"x86-64", SandyBridgeModel,
 495                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 496                       FeatureFastUAMem]>;
 497
 498 //===----------------------------------------------------------------------===//
 499 // Register File Description
 500 //===----------------------------------------------------------------------===//
 501
 502 include "X86RegisterInfo.td"
 503
 504 //===----------------------------------------------------------------------===//
 505 // Instruction Descriptions
 506 //===----------------------------------------------------------------------===//
 507
 508 include "X86InstrInfo.td"
 509
 510 def X86InstrInfo : InstrInfo;
 511
 512 //===----------------------------------------------------------------------===//
 513 // Calling Conventions
 514 //===----------------------------------------------------------------------===//
 515
 516 include "X86CallingConv.td"
 517
 518
 519 //===----------------------------------------------------------------------===//
 520 // Assembly Parser
 521 //===----------------------------------------------------------------------===//
 522
 523 def ATTAsmParser : AsmParser {
 524   string AsmParserClassName = "AsmParser";
 525 }
 526
 527 def ATTAsmParserVariant : AsmParserVariant {
 528   int Variant = 0;
 529
 530   // Variant name.
 531   string Name = "att";
 532
 533   // Discard comments in assembly strings.
 534   string CommentDelimiter = "#";
 535
 536   // Recognize hard coded registers.
 537   string RegisterPrefix = "%";
 538 }
 539
 540 def IntelAsmParserVariant : AsmParserVariant {
 541   int Variant = 1;
 542
 543   // Variant name.
 544   string Name = "intel";
 545
 546   // Discard comments in assembly strings.
 547   string CommentDelimiter = ";";
 548
 549   // Recognize hard coded registers.
 550   string RegisterPrefix = "";
 551 }
 552
 553 //===----------------------------------------------------------------------===//
 554 // Assembly Printers
 555 //===----------------------------------------------------------------------===//
 556
 557 // The X86 target supports two different syntaxes for emitting machine code.
 558 // This is controlled by the -x86-asm-syntax={att|intel}
 559 def ATTAsmWriter : AsmWriter {
 560   string AsmWriterClassName  = "ATTInstPrinter";
 561   int Variant = 0;
 562 }
 563 def IntelAsmWriter : AsmWriter {
 564   string AsmWriterClassName  = "IntelInstPrinter";
 565   int Variant = 1;
 566 }
 567
 568 def X86 : Target {
 569   // Information about the instructions...
 570   let InstructionSet = X86InstrInfo;
 571   let AssemblyParsers = [ATTAsmParser];
 572   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 573   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 574 }