lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  41                                       "Support fxsave/fxrestore instructions">;
  42
  43 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  44                                        "Support xsave instructions">;
  45
  46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  47                                        "Support xsaveopt instructions">;
  48
  49 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  50                                        "Support xsavec instructions">;
  51
  52 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  53                                        "Support xsaves instructions">;
  54
  55 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  56                                       "Enable SSE instructions",
  57                                       // SSE codegen depends on cmovs, and all
  58                                       // SSE1+ processors support them.
  59                                       [FeatureCMOV]>;
  60 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  61                                       "Enable SSE2 instructions",
  62                                       [FeatureSSE1]>;
  63 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  64                                       "Enable SSE3 instructions",
  65                                       [FeatureSSE2]>;
  66 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  67                                       "Enable SSSE3 instructions",
  68                                       [FeatureSSE3]>;
  69 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  70                                       "Enable SSE 4.1 instructions",
  71                                       [FeatureSSSE3]>;
  72 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  73                                       "Enable SSE 4.2 instructions",
  74                                       [FeatureSSE41]>;
  75 // The MMX subtarget feature is separate from the rest of the SSE features
  76 // because it's important (for odd compatibility reasons) to be able to
  77 // turn it off explicitly while allowing SSE+ to be on.
  78 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  79                                       "Enable MMX instructions">;
  80 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  81                                       "Enable 3DNow! instructions",
  82                                       [FeatureMMX]>;
  83 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  84                                       "Enable 3DNow! Athlon instructions",
  85                                       [Feature3DNow]>;
  86 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  87 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  88 // without disabling 64-bit mode.
  89 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  90                                       "Support 64-bit instructions",
  91                                       [FeatureCMOV]>;
  92 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  93                                       "64-bit with cmpxchg16b",
  94                                       [Feature64Bit]>;
  95 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  96                                        "Bit testing of memory is slow">;
  97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  98                                        "SHLD instruction is slow">;
  99 // FIXME: This should not apply to CPUs that do not have SSE.
 100 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 101                                 "IsUAMem16Slow", "true",
 102                                 "Slow unaligned 16-byte memory access">;
 103 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 104                                 "IsUAMem32Slow", "true",
 105                                 "Slow unaligned 32-byte memory access">;
 106 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 107                                       "Support SSE 4a instructions",
 108                                       [FeatureSSE3]>;
 109
 110 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 111                                       "Enable AVX instructions",
 112                                       [FeatureSSE42]>;
 113 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 114                                       "Enable AVX2 instructions",
 115                                       [FeatureAVX]>;
 116 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 117                                       "Enable AVX-512 instructions",
 118                                       [FeatureAVX2]>;
 119 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 120                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 121                                       [FeatureAVX512]>;
 122 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 123                       "Enable AVX-512 Conflict Detection Instructions",
 124                                       [FeatureAVX512]>;
 125 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 126                       "Enable AVX-512 PreFetch Instructions",
 127                                       [FeatureAVX512]>;
 128 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 129                       "Enable AVX-512 Doubleword and Quadword Instructions",
 130                                       [FeatureAVX512]>;
 131 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 132                       "Enable AVX-512 Byte and Word Instructions",
 133                                       [FeatureAVX512]>;
 134 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 135                       "Enable AVX-512 Vector Length eXtensions",
 136                                       [FeatureAVX512]>;
 137 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 138                          "Enable packed carry-less multiplication instructions",
 139                                [FeatureSSE2]>;
 140 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 141                                       "Enable three-operand fused multiple-add",
 142                                       [FeatureAVX]>;
 143 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 144                                       "Enable four-operand fused multiple-add",
 145                                       [FeatureAVX, FeatureSSE4A]>;
 146 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 147                                       "Enable XOP instructions",
 148                                       [FeatureFMA4]>;
 149 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 150                                           "HasSSEUnalignedMem", "true",
 151                       "Allow unaligned memory operands with SSE instructions">;
 152 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 153                                       "Enable AES instructions",
 154                                       [FeatureSSE2]>;
 155 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 156                                       "Enable TBM instructions">;
 157 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 158                                       "Support MOVBE instruction">;
 159 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 160                                       "Support RDRAND instruction">;
 161 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 162                        "Support 16-bit floating point conversion instructions",
 163                        [FeatureAVX]>;
 164 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 165                                        "Support FS/GS Base instructions">;
 166 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 167                                       "Support LZCNT instruction">;
 168 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 169                                       "Support BMI instructions">;
 170 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 171                                       "Support BMI2 instructions">;
 172 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 173                                       "Support RTM instructions">;
 174 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 175                                       "Support HLE">;
 176 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 177                                       "Support ADX instructions">;
 178 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 179                                       "Enable SHA instructions",
 180                                       [FeatureSSE2]>;
 181 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 182                                       "Support PRFCHW instructions">;
 183 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 184                                       "Support RDSEED instruction">;
 185 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 186                                        "Support LAHF and SAHF instructions">;
 187 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 188                                       "Support MPX instructions">;
 189 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 190                                      "Use LEA for adjusting the stack pointer">;
 191 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 192                                      "HasSlowDivide32", "true",
 193                                      "Use 8-bit divide for positive values less than 256">;
 194 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 195                                      "HasSlowDivide64", "true",
 196                                      "Use 16-bit divide for positive values less than 65536">;
 197 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 198                                      "PadShortFunctions", "true",
 199                                      "Pad short functions">;
 200 // TODO: This feature ought to be renamed.
 201 // What it really refers to are CPUs for which certain instructions
 202 // (which ones besides the example below?) are microcoded.
 203 // The best examples of this are the memory forms of CALL and PUSH
 204 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 205 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 206                                      "CallRegIndirect", "true",
 207                                      "Call register indirect">;
 208 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 209                                    "LEA instruction needs inputs at AG stage">;
 210 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 211                                    "LEA instruction with certain arguments is slow">;
 212 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 213                                    "INC and DEC instructions are slower than ADD and SUB">;
 214 def FeatureSoftFloat
 215     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 216                        "Use software floating point features.">;
 217
 218 //===----------------------------------------------------------------------===//
 219 // X86 processors supported.
 220 //===----------------------------------------------------------------------===//
 221
 222 include "X86Schedule.td"
 223
 224 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 225                     "Intel Atom processors">;
 226 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 227                     "Intel Silvermont processors">;
 228
 229 class Proc<string Name, list<SubtargetFeature> Features>
 230  : ProcessorModel<Name, GenericModel, Features>;
 231
 232 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 233 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 234 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 235 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 236 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 237 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 238 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 239 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 240 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
 241                                FeatureFXSR]>;
 242 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 243                                FeatureFXSR]>;
 244 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 245                                FeatureFXSR, FeatureSlowBTMem]>;
 246 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 247                                FeatureFXSR, FeatureSlowBTMem]>;
 248 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 249                                FeatureFXSR]>;
 250 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 251                                FeatureFXSR, FeatureSlowBTMem]>;
 252
 253 // Intel Core Duo.
 254 def : ProcessorModel<"yonah", SandyBridgeModel,
 255                      [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 256                       FeatureSlowBTMem]>;
 257
 258 // NetBurst.
 259 def : Proc<"prescott",
 260            [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 261             FeatureSlowBTMem]>;
 262 def : Proc<"nocona", [
 263   FeatureSlowUAMem16,
 264   FeatureMMX,
 265   FeatureSSE3,
 266   FeatureFXSR,
 267   FeatureCMPXCHG16B,
 268   FeatureSlowBTMem
 269 ]>;
 270
 271 // Intel Core 2 Solo/Duo.
 272 def : ProcessorModel<"core2", SandyBridgeModel, [
 273   FeatureSlowUAMem16,
 274   FeatureMMX,
 275   FeatureSSSE3,
 276   FeatureFXSR,
 277   FeatureCMPXCHG16B,
 278   FeatureSlowBTMem,
 279   FeatureLAHFSAHF
 280 ]>;
 281 def : ProcessorModel<"penryn", SandyBridgeModel, [
 282   FeatureSlowUAMem16,
 283   FeatureMMX,
 284   FeatureSSE41,
 285   FeatureFXSR,
 286   FeatureCMPXCHG16B,
 287   FeatureSlowBTMem,
 288   FeatureLAHFSAHF
 289 ]>;
 290
 291 // Atom CPUs.
 292 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 293   ProcIntelAtom,
 294   FeatureSlowUAMem16,
 295   FeatureMMX,
 296   FeatureSSSE3,
 297   FeatureFXSR,
 298   FeatureCMPXCHG16B,
 299   FeatureMOVBE,
 300   FeatureSlowBTMem,
 301   FeatureLEAForSP,
 302   FeatureSlowDivide32,
 303   FeatureSlowDivide64,
 304   FeatureCallRegIndirect,
 305   FeatureLEAUsesAG,
 306   FeaturePadShortFunctions,
 307   FeatureLAHFSAHF
 308 ]>;
 309 def : BonnellProc<"bonnell">;
 310 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 311
 312 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 313   ProcIntelSLM,
 314   FeatureMMX,
 315   FeatureSSE42,
 316   FeatureFXSR,
 317   FeatureCMPXCHG16B,
 318   FeatureMOVBE,
 319   FeaturePOPCNT,
 320   FeaturePCLMUL,
 321   FeatureAES,
 322   FeatureSlowDivide64,
 323   FeatureCallRegIndirect,
 324   FeaturePRFCHW,
 325   FeatureSlowLEA,
 326   FeatureSlowIncDec,
 327   FeatureSlowBTMem,
 328   FeatureLAHFSAHF
 329 ]>;
 330 def : SilvermontProc<"silvermont">;
 331 def : SilvermontProc<"slm">; // Legacy alias.
 332
 333 // "Arrandale" along with corei3 and corei5
 334 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 335   FeatureMMX,
 336   FeatureSSE42,
 337   FeatureFXSR,
 338   FeatureCMPXCHG16B,
 339   FeatureSlowBTMem,
 340   FeaturePOPCNT,
 341   FeatureLAHFSAHF
 342 ]>;
 343 def : NehalemProc<"nehalem">;
 344 def : NehalemProc<"corei7">;
 345
 346 // Westmere is a similar machine to nehalem with some additional features.
 347 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 348 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 349   FeatureMMX,
 350   FeatureSSE42,
 351   FeatureFXSR,
 352   FeatureCMPXCHG16B,
 353   FeatureSlowBTMem,
 354   FeaturePOPCNT,
 355   FeatureAES,
 356   FeaturePCLMUL,
 357   FeatureLAHFSAHF
 358 ]>;
 359 def : WestmereProc<"westmere">;
 360
 361 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 362 // rather than a superset.
 363 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 364   FeatureMMX,
 365   FeatureAVX,
 366   FeatureFXSR,
 367   FeatureCMPXCHG16B,
 368   FeatureSlowBTMem,
 369   FeatureSlowUAMem32,
 370   FeaturePOPCNT,
 371   FeatureAES,
 372   FeaturePCLMUL,
 373   FeatureXSAVE,
 374   FeatureXSAVEOPT,
 375   FeatureLAHFSAHF
 376 ]>;
 377 def : SandyBridgeProc<"sandybridge">;
 378 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 379
 380 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 381   FeatureMMX,
 382   FeatureAVX,
 383   FeatureFXSR,
 384   FeatureCMPXCHG16B,
 385   FeatureSlowBTMem,
 386   FeatureSlowUAMem32,
 387   FeaturePOPCNT,
 388   FeatureAES,
 389   FeaturePCLMUL,
 390   FeatureXSAVE,
 391   FeatureXSAVEOPT,
 392   FeatureRDRAND,
 393   FeatureF16C,
 394   FeatureFSGSBase,
 395   FeatureLAHFSAHF
 396 ]>;
 397 def : IvyBridgeProc<"ivybridge">;
 398 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 399
 400 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 401   FeatureMMX,
 402   FeatureAVX2,
 403   FeatureFXSR,
 404   FeatureCMPXCHG16B,
 405   FeatureSlowBTMem,
 406   FeaturePOPCNT,
 407   FeatureAES,
 408   FeaturePCLMUL,
 409   FeatureRDRAND,
 410   FeatureXSAVE,
 411   FeatureXSAVEOPT,
 412   FeatureF16C,
 413   FeatureFSGSBase,
 414   FeatureMOVBE,
 415   FeatureLZCNT,
 416   FeatureBMI,
 417   FeatureBMI2,
 418   FeatureFMA,
 419   FeatureRTM,
 420   FeatureHLE,
 421   FeatureSlowIncDec,
 422   FeatureLAHFSAHF
 423 ]>;
 424 def : HaswellProc<"haswell">;
 425 def : HaswellProc<"core-avx2">; // Legacy alias.
 426
 427 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 428   FeatureMMX,
 429   FeatureAVX2,
 430   FeatureFXSR,
 431   FeatureCMPXCHG16B,
 432   FeatureSlowBTMem,
 433   FeaturePOPCNT,
 434   FeatureAES,
 435   FeaturePCLMUL,
 436   FeatureXSAVE,
 437   FeatureXSAVEOPT,
 438   FeatureRDRAND,
 439   FeatureF16C,
 440   FeatureFSGSBase,
 441   FeatureMOVBE,
 442   FeatureLZCNT,
 443   FeatureBMI,
 444   FeatureBMI2,
 445   FeatureFMA,
 446   FeatureRTM,
 447   FeatureHLE,
 448   FeatureADX,
 449   FeatureRDSEED,
 450   FeatureSlowIncDec,
 451   FeatureLAHFSAHF
 452 ]>;
 453 def : BroadwellProc<"broadwell">;
 454
 455 // FIXME: define KNL model
 456 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
 457   FeatureMMX,
 458   FeatureAVX512,
 459   FeatureFXSR,
 460   FeatureERI,
 461   FeatureCDI,
 462   FeaturePFI,
 463   FeatureCMPXCHG16B,
 464   FeaturePOPCNT,
 465   FeatureAES,
 466   FeaturePCLMUL,
 467   FeatureXSAVE,
 468   FeatureXSAVEOPT,
 469   FeatureRDRAND,
 470   FeatureF16C,
 471   FeatureFSGSBase,
 472   FeatureMOVBE,
 473   FeatureLZCNT,
 474   FeatureBMI,
 475   FeatureBMI2,
 476   FeatureFMA,
 477   FeatureRTM,
 478   FeatureHLE,
 479   FeatureSlowIncDec,
 480   FeatureMPX,
 481   FeatureLAHFSAHF
 482 ]>;
 483 def : KnightsLandingProc<"knl">;
 484
 485 // FIXME: define SKX model
 486 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
 487   FeatureMMX,
 488   FeatureAVX512,
 489   FeatureFXSR,
 490   FeatureCDI,
 491   FeatureDQI,
 492   FeatureBWI,
 493   FeatureVLX,
 494   FeatureCMPXCHG16B,
 495   FeatureSlowBTMem,
 496   FeaturePOPCNT,
 497   FeatureAES,
 498   FeaturePCLMUL,
 499   FeatureXSAVE,
 500   FeatureXSAVEOPT,
 501   FeatureRDRAND,
 502   FeatureF16C,
 503   FeatureFSGSBase,
 504   FeatureMOVBE,
 505   FeatureLZCNT,
 506   FeatureBMI,
 507   FeatureBMI2,
 508   FeatureFMA,
 509   FeatureRTM,
 510   FeatureHLE,
 511   FeatureADX,
 512   FeatureRDSEED,
 513   FeatureSlowIncDec,
 514   FeatureMPX,
 515   FeatureXSAVEC,
 516   FeatureXSAVES,
 517   FeatureLAHFSAHF
 518 ]>;
 519 def : SkylakeProc<"skylake">;
 520 def : SkylakeProc<"skx">; // Legacy alias.
 521
 522
 523 // AMD CPUs.
 524
 525 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 526 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 527 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 528 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 529                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 530 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 531                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 532 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 533                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 534 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 535                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 536 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 537                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 538 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 539                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 540                                FeatureSlowSHLD]>;
 541 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 542                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 543                                FeatureSlowSHLD]>;
 544 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 545                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 546                                FeatureSlowSHLD]>;
 547 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 548                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 549                                FeatureSlowSHLD]>;
 550 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 551                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 552                                FeatureSlowSHLD]>;
 553 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 554                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 555                                FeatureSlowSHLD]>;
 556 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 557                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 558                                FeatureSlowSHLD]>;
 559 def : Proc<"amdfam10",        [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 560                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 561                                FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
 562 def : Proc<"barcelona",       [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 563                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 564                                FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
 565
 566 // Bobcat
 567 def : Proc<"btver1", [
 568   FeatureMMX,
 569   FeatureSSSE3,
 570   FeatureSSE4A,
 571   FeatureFXSR,
 572   FeatureCMPXCHG16B,
 573   FeaturePRFCHW,
 574   FeatureLZCNT,
 575   FeaturePOPCNT,
 576   FeatureXSAVE,
 577   FeatureSlowSHLD,
 578   FeatureLAHFSAHF
 579 ]>;
 580
 581 // Jaguar
 582 def : ProcessorModel<"btver2", BtVer2Model, [
 583   FeatureMMX,
 584   FeatureAVX,
 585   FeatureFXSR,
 586   FeatureSSE4A,
 587   FeatureCMPXCHG16B,
 588   FeaturePRFCHW,
 589   FeatureAES,
 590   FeaturePCLMUL,
 591   FeatureBMI,
 592   FeatureF16C,
 593   FeatureMOVBE,
 594   FeatureLZCNT,
 595   FeaturePOPCNT,
 596   FeatureXSAVE,
 597   FeatureXSAVEOPT,
 598   FeatureSlowSHLD,
 599   FeatureLAHFSAHF
 600 ]>;
 601
 602 // Bulldozer
 603 def : Proc<"bdver1", [
 604   FeatureXOP,
 605   FeatureFMA4,
 606   FeatureCMPXCHG16B,
 607   FeatureAES,
 608   FeaturePRFCHW,
 609   FeaturePCLMUL,
 610   FeatureMMX,
 611   FeatureAVX,
 612   FeatureFXSR,
 613   FeatureSSE4A,
 614   FeatureLZCNT,
 615   FeaturePOPCNT,
 616   FeatureXSAVE,
 617   FeatureSlowSHLD,
 618   FeatureLAHFSAHF
 619 ]>;
 620 // Piledriver
 621 def : Proc<"bdver2", [
 622   FeatureXOP,
 623   FeatureFMA4,
 624   FeatureCMPXCHG16B,
 625   FeatureAES,
 626   FeaturePRFCHW,
 627   FeaturePCLMUL,
 628   FeatureMMX,
 629   FeatureAVX,
 630   FeatureFXSR,
 631   FeatureSSE4A,
 632   FeatureF16C,
 633   FeatureLZCNT,
 634   FeaturePOPCNT,
 635   FeatureXSAVE,
 636   FeatureBMI,
 637   FeatureTBM,
 638   FeatureFMA,
 639   FeatureSlowSHLD,
 640   FeatureLAHFSAHF
 641 ]>;
 642
 643 // Steamroller
 644 def : Proc<"bdver3", [
 645   FeatureXOP,
 646   FeatureFMA4,
 647   FeatureCMPXCHG16B,
 648   FeatureAES,
 649   FeaturePRFCHW,
 650   FeaturePCLMUL,
 651   FeatureMMX,
 652   FeatureAVX,
 653   FeatureFXSR,
 654   FeatureSSE4A,
 655   FeatureF16C,
 656   FeatureLZCNT,
 657   FeaturePOPCNT,
 658   FeatureXSAVE,
 659   FeatureBMI,
 660   FeatureTBM,
 661   FeatureFMA,
 662   FeatureXSAVEOPT,
 663   FeatureSlowSHLD,
 664   FeatureFSGSBase,
 665   FeatureLAHFSAHF
 666 ]>;
 667
 668 // Excavator
 669 def : Proc<"bdver4", [
 670   FeatureMMX,
 671   FeatureAVX2,
 672   FeatureFXSR,
 673   FeatureXOP,
 674   FeatureFMA4,
 675   FeatureCMPXCHG16B,
 676   FeatureAES,
 677   FeaturePRFCHW,
 678   FeaturePCLMUL,
 679   FeatureF16C,
 680   FeatureLZCNT,
 681   FeaturePOPCNT,
 682   FeatureXSAVE,
 683   FeatureBMI,
 684   FeatureBMI2,
 685   FeatureTBM,
 686   FeatureFMA,
 687   FeatureXSAVEOPT,
 688   FeatureFSGSBase,
 689   FeatureLAHFSAHF
 690 ]>;
 691
 692 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 693
 694 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 695 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 696 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 697 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
 698
 699 // We also provide a generic 64-bit specific x86 processor model which tries to
 700 // be good for modern chips without enabling instruction set encodings past the
 701 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 702 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 703 //
 704 // We currently use the Sandy Bridge model as the default scheduling model as
 705 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 706 // covers a huge swath of x86 processors. If there are specific scheduling
 707 // knobs which need to be tuned differently for AMD chips, we might consider
 708 // forming a common base for them.
 709 def : ProcessorModel<"x86-64", SandyBridgeModel,
 710                      [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
 711                       FeatureSlowBTMem ]>;
 712
 713 //===----------------------------------------------------------------------===//
 714 // Register File Description
 715 //===----------------------------------------------------------------------===//
 716
 717 include "X86RegisterInfo.td"
 718
 719 //===----------------------------------------------------------------------===//
 720 // Instruction Descriptions
 721 //===----------------------------------------------------------------------===//
 722
 723 include "X86InstrInfo.td"
 724
 725 def X86InstrInfo : InstrInfo;
 726
 727 //===----------------------------------------------------------------------===//
 728 // Calling Conventions
 729 //===----------------------------------------------------------------------===//
 730
 731 include "X86CallingConv.td"
 732
 733
 734 //===----------------------------------------------------------------------===//
 735 // Assembly Parser
 736 //===----------------------------------------------------------------------===//
 737
 738 def ATTAsmParser : AsmParser {
 739   string AsmParserClassName = "AsmParser";
 740 }
 741
 742 def ATTAsmParserVariant : AsmParserVariant {
 743   int Variant = 0;
 744
 745   // Variant name.
 746   string Name = "att";
 747
 748   // Discard comments in assembly strings.
 749   string CommentDelimiter = "#";
 750
 751   // Recognize hard coded registers.
 752   string RegisterPrefix = "%";
 753 }
 754
 755 def IntelAsmParserVariant : AsmParserVariant {
 756   int Variant = 1;
 757
 758   // Variant name.
 759   string Name = "intel";
 760
 761   // Discard comments in assembly strings.
 762   string CommentDelimiter = ";";
 763
 764   // Recognize hard coded registers.
 765   string RegisterPrefix = "";
 766 }
 767
 768 //===----------------------------------------------------------------------===//
 769 // Assembly Printers
 770 //===----------------------------------------------------------------------===//
 771
 772 // The X86 target supports two different syntaxes for emitting machine code.
 773 // This is controlled by the -x86-asm-syntax={att|intel}
 774 def ATTAsmWriter : AsmWriter {
 775   string AsmWriterClassName  = "ATTInstPrinter";
 776   int Variant = 0;
 777 }
 778 def IntelAsmWriter : AsmWriter {
 779   string AsmWriterClassName  = "IntelInstPrinter";
 780   int Variant = 1;
 781 }
 782
 783 def X86 : Target {
 784   // Information about the instructions...
 785   let InstructionSet = X86InstrInfo;
 786   let AssemblyParsers = [ATTAsmParser];
 787   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 788   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 789 }