lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  41                                       "Support fxsave/fxrestore instructions">;
  42
  43 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  44                                        "Support xsave instructions">;
  45
  46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  47                                        "Support xsaveopt instructions">;
  48
  49 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  50                                        "Support xsavec instructions">;
  51
  52 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  53                                        "Support xsaves instructions">;
  54
  55 // The MMX subtarget feature is separate from the rest of the SSE features
  56 // because it's important (for odd compatibility reasons) to be able to
  57 // turn it off explicitly while allowing SSE+ to be on.
  58 def FeatureMMX     : SubtargetFeature<"mmx","HasMMX", "true",
  59                                       "Enable MMX instructions">;
  60
  61 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  62                                       "Enable SSE instructions",
  63                                       // SSE codegen depends on cmovs, and all
  64                                       // SSE1+ processors support them.
  65                                       [FeatureCMOV]>;
  66 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  67                                       "Enable SSE2 instructions",
  68                                       [FeatureSSE1]>;
  69 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  70                                       "Enable SSE3 instructions",
  71                                       [FeatureSSE2]>;
  72 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  73                                       "Enable SSSE3 instructions",
  74                                       [FeatureSSE3]>;
  75 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  76                                       "Enable SSE 4.1 instructions",
  77                                       [FeatureSSSE3]>;
  78 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  79                                       "Enable SSE 4.2 instructions",
  80                                       [FeatureSSE41]>;
  81 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  82                                       "Enable 3DNow! instructions",
  83                                       [FeatureMMX]>;
  84 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  85                                       "Enable 3DNow! Athlon instructions",
  86                                       [Feature3DNow]>;
  87 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  88 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  89 // without disabling 64-bit mode.
  90 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  91                                       "Support 64-bit instructions",
  92                                       [FeatureCMOV]>;
  93 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  94                                       "64-bit with cmpxchg16b",
  95                                       [Feature64Bit]>;
  96 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  97                                        "Bit testing of memory is slow">;
  98 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  99                                        "SHLD instruction is slow">;
 100 // FIXME: This should not apply to CPUs that do not have SSE.
 101 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 102                                 "IsUAMem16Slow", "true",
 103                                 "Slow unaligned 16-byte memory access">;
 104 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 105                                 "IsUAMem32Slow", "true",
 106                                 "Slow unaligned 32-byte memory access">;
 107 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 108                                       "Support SSE 4a instructions",
 109                                       [FeatureSSE3]>;
 110
 111 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 112                                       "Enable AVX instructions",
 113                                       [FeatureSSE42]>;
 114 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 115                                       "Enable AVX2 instructions",
 116                                       [FeatureAVX]>;
 117 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 118                                       "Enable AVX-512 instructions",
 119                                       [FeatureAVX2]>;
 120 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 121                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 122                                       [FeatureAVX512]>;
 123 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 124                       "Enable AVX-512 Conflict Detection Instructions",
 125                                       [FeatureAVX512]>;
 126 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 127                       "Enable AVX-512 PreFetch Instructions",
 128                                       [FeatureAVX512]>;
 129 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 130                       "Enable AVX-512 Doubleword and Quadword Instructions",
 131                                       [FeatureAVX512]>;
 132 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 133                       "Enable AVX-512 Byte and Word Instructions",
 134                                       [FeatureAVX512]>;
 135 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 136                       "Enable AVX-512 Vector Length eXtensions",
 137                                       [FeatureAVX512]>;
 138 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 139                          "Enable packed carry-less multiplication instructions",
 140                                [FeatureSSE2]>;
 141 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 142                                       "Enable three-operand fused multiple-add",
 143                                       [FeatureAVX]>;
 144 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 145                                       "Enable four-operand fused multiple-add",
 146                                       [FeatureAVX, FeatureSSE4A]>;
 147 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 148                                       "Enable XOP instructions",
 149                                       [FeatureFMA4]>;
 150 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 151                                           "HasSSEUnalignedMem", "true",
 152                       "Allow unaligned memory operands with SSE instructions">;
 153 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 154                                       "Enable AES instructions",
 155                                       [FeatureSSE2]>;
 156 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 157                                       "Enable TBM instructions">;
 158 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 159                                       "Support MOVBE instruction">;
 160 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 161                                       "Support RDRAND instruction">;
 162 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 163                        "Support 16-bit floating point conversion instructions",
 164                        [FeatureAVX]>;
 165 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 166                                        "Support FS/GS Base instructions">;
 167 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 168                                       "Support LZCNT instruction">;
 169 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 170                                       "Support BMI instructions">;
 171 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 172                                       "Support BMI2 instructions">;
 173 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 174                                       "Support RTM instructions">;
 175 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 176                                       "Support HLE">;
 177 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 178                                       "Support ADX instructions">;
 179 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 180                                       "Enable SHA instructions",
 181                                       [FeatureSSE2]>;
 182 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 183                                       "Support PRFCHW instructions">;
 184 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 185                                       "Support RDSEED instruction">;
 186 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 187                                       "Support MPX instructions">;
 188 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 189                                      "Use LEA for adjusting the stack pointer">;
 190 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 191                                      "HasSlowDivide32", "true",
 192                                      "Use 8-bit divide for positive values less than 256">;
 193 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 194                                      "HasSlowDivide64", "true",
 195                                      "Use 16-bit divide for positive values less than 65536">;
 196 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 197                                      "PadShortFunctions", "true",
 198                                      "Pad short functions">;
 199 // TODO: This feature ought to be renamed.
 200 // What it really refers to are CPUs for which certain instructions
 201 // (which ones besides the example below?) are microcoded.
 202 // The best examples of this are the memory forms of CALL and PUSH
 203 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 204 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 205                                      "CallRegIndirect", "true",
 206                                      "Call register indirect">;
 207 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 208                                    "LEA instruction needs inputs at AG stage">;
 209 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 210                                    "LEA instruction with certain arguments is slow">;
 211 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 212                                    "INC and DEC instructions are slower than ADD and SUB">;
 213 def FeatureSoftFloat
 214     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 215                        "Use software floating point features.">;
 216
 217 //===----------------------------------------------------------------------===//
 218 // X86 processors supported.
 219 //===----------------------------------------------------------------------===//
 220
 221 include "X86Schedule.td"
 222
 223 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 224                     "Intel Atom processors">;
 225 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 226                     "Intel Silvermont processors">;
 227
 228 class Proc<string Name, list<SubtargetFeature> Features>
 229  : ProcessorModel<Name, GenericModel, Features>;
 230
 231 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 232 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 233 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 234 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 235 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 236 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 237 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 238 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 239 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
 240                                FeatureFXSR]>;
 241 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 242                                FeatureFXSR]>;
 243 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 244                                FeatureFXSR, FeatureSlowBTMem]>;
 245 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 246                                FeatureFXSR, FeatureSlowBTMem]>;
 247 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 248                                FeatureFXSR]>;
 249 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 250                                FeatureFXSR, FeatureSlowBTMem]>;
 251
 252 // Intel Core Duo.
 253 def : ProcessorModel<"yonah", SandyBridgeModel,
 254                      [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 255                       FeatureSlowBTMem]>;
 256
 257 // NetBurst.
 258 def : Proc<"prescott",
 259            [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 260             FeatureSlowBTMem]>;
 261 def : Proc<"nocona", [
 262   FeatureSlowUAMem16,
 263   FeatureMMX,
 264   FeatureSSE3,
 265   FeatureFXSR,
 266   FeatureCMPXCHG16B,
 267   FeatureSlowBTMem
 268 ]>;
 269
 270 // Intel Core 2 Solo/Duo.
 271 def : ProcessorModel<"core2", SandyBridgeModel, [
 272   FeatureSlowUAMem16,
 273   FeatureMMX,
 274   FeatureSSSE3,
 275   FeatureFXSR,
 276   FeatureCMPXCHG16B,
 277   FeatureSlowBTMem
 278 ]>;
 279 def : ProcessorModel<"penryn", SandyBridgeModel, [
 280   FeatureSlowUAMem16,
 281   FeatureMMX,
 282   FeatureSSE41,
 283   FeatureFXSR,
 284   FeatureCMPXCHG16B,
 285   FeatureSlowBTMem
 286 ]>;
 287
 288 // Atom CPUs.
 289 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 290   ProcIntelAtom,
 291   FeatureSlowUAMem16,
 292   FeatureMMX,
 293   FeatureSSSE3,
 294   FeatureFXSR,
 295   FeatureCMPXCHG16B,
 296   FeatureMOVBE,
 297   FeatureSlowBTMem,
 298   FeatureLEAForSP,
 299   FeatureSlowDivide32,
 300   FeatureSlowDivide64,
 301   FeatureCallRegIndirect,
 302   FeatureLEAUsesAG,
 303   FeaturePadShortFunctions
 304 ]>;
 305 def : BonnellProc<"bonnell">;
 306 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 307
 308 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 309   ProcIntelSLM,
 310   FeatureMMX,
 311   FeatureSSE42,
 312   FeatureFXSR,
 313   FeatureCMPXCHG16B,
 314   FeatureMOVBE,
 315   FeaturePOPCNT,
 316   FeaturePCLMUL,
 317   FeatureAES,
 318   FeatureSlowDivide64,
 319   FeatureCallRegIndirect,
 320   FeaturePRFCHW,
 321   FeatureSlowLEA,
 322   FeatureSlowIncDec,
 323   FeatureSlowBTMem
 324 ]>;
 325 def : SilvermontProc<"silvermont">;
 326 def : SilvermontProc<"slm">; // Legacy alias.
 327
 328 // "Arrandale" along with corei3 and corei5
 329 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 330   FeatureMMX,
 331   FeatureSSE42,
 332   FeatureFXSR,
 333   FeatureCMPXCHG16B,
 334   FeatureSlowBTMem,
 335   FeaturePOPCNT
 336 ]>;
 337 def : NehalemProc<"nehalem">;
 338 def : NehalemProc<"corei7">;
 339
 340 // Westmere is a similar machine to nehalem with some additional features.
 341 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 342 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 343   FeatureMMX,
 344   FeatureSSE42,
 345   FeatureFXSR,
 346   FeatureCMPXCHG16B,
 347   FeatureSlowBTMem,
 348   FeaturePOPCNT,
 349   FeatureAES,
 350   FeaturePCLMUL
 351 ]>;
 352 def : WestmereProc<"westmere">;
 353
 354 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 355 // rather than a superset.
 356 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 357   FeatureMMX,
 358   FeatureAVX,
 359   FeatureFXSR,
 360   FeatureCMPXCHG16B,
 361   FeatureSlowBTMem,
 362   FeatureSlowUAMem32,
 363   FeaturePOPCNT,
 364   FeatureAES,
 365   FeaturePCLMUL,
 366   FeatureXSAVE,
 367   FeatureXSAVEOPT
 368 ]>;
 369 def : SandyBridgeProc<"sandybridge">;
 370 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 371
 372 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 373   FeatureMMX,
 374   FeatureAVX,
 375   FeatureFXSR,
 376   FeatureCMPXCHG16B,
 377   FeatureSlowBTMem,
 378   FeatureSlowUAMem32,
 379   FeaturePOPCNT,
 380   FeatureAES,
 381   FeaturePCLMUL,
 382   FeatureXSAVE,
 383   FeatureXSAVEOPT,
 384   FeatureRDRAND,
 385   FeatureF16C,
 386   FeatureFSGSBase
 387 ]>;
 388 def : IvyBridgeProc<"ivybridge">;
 389 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 390
 391 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 392   FeatureMMX,
 393   FeatureAVX2,
 394   FeatureFXSR,
 395   FeatureCMPXCHG16B,
 396   FeatureSlowBTMem,
 397   FeaturePOPCNT,
 398   FeatureAES,
 399   FeaturePCLMUL,
 400   FeatureRDRAND,
 401   FeatureXSAVE,
 402   FeatureXSAVEOPT,
 403   FeatureF16C,
 404   FeatureFSGSBase,
 405   FeatureMOVBE,
 406   FeatureLZCNT,
 407   FeatureBMI,
 408   FeatureBMI2,
 409   FeatureFMA,
 410   FeatureRTM,
 411   FeatureHLE,
 412   FeatureSlowIncDec
 413 ]>;
 414 def : HaswellProc<"haswell">;
 415 def : HaswellProc<"core-avx2">; // Legacy alias.
 416
 417 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 418   FeatureMMX,
 419   FeatureAVX2,
 420   FeatureFXSR,
 421   FeatureCMPXCHG16B,
 422   FeatureSlowBTMem,
 423   FeaturePOPCNT,
 424   FeatureAES,
 425   FeaturePCLMUL,
 426   FeatureXSAVE,
 427   FeatureXSAVEOPT,
 428   FeatureRDRAND,
 429   FeatureF16C,
 430   FeatureFSGSBase,
 431   FeatureMOVBE,
 432   FeatureLZCNT,
 433   FeatureBMI,
 434   FeatureBMI2,
 435   FeatureFMA,
 436   FeatureRTM,
 437   FeatureHLE,
 438   FeatureADX,
 439   FeatureRDSEED,
 440   FeatureSlowIncDec
 441 ]>;
 442 def : BroadwellProc<"broadwell">;
 443
 444 // FIXME: define KNL model
 445 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
 446   FeatureMMX,
 447   FeatureAVX512,
 448   FeatureFXSR,
 449   FeatureERI,
 450   FeatureCDI,
 451   FeaturePFI,
 452   FeatureCMPXCHG16B,
 453   FeaturePOPCNT,
 454   FeatureAES,
 455   FeaturePCLMUL,
 456   FeatureXSAVE,
 457   FeatureXSAVEOPT,
 458   FeatureRDRAND,
 459   FeatureF16C,
 460   FeatureFSGSBase,
 461   FeatureMOVBE,
 462   FeatureLZCNT,
 463   FeatureBMI,
 464   FeatureBMI2,
 465   FeatureFMA,
 466   FeatureRTM,
 467   FeatureHLE,
 468   FeatureSlowIncDec,
 469   FeatureMPX
 470 ]>;
 471 def : KnightsLandingProc<"knl">;
 472
 473 // FIXME: define SKX model
 474 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
 475   FeatureMMX,
 476   FeatureAVX512,
 477   FeatureFXSR,
 478   FeatureCDI,
 479   FeatureDQI,
 480   FeatureBWI,
 481   FeatureVLX,
 482   FeatureCMPXCHG16B,
 483   FeatureSlowBTMem,
 484   FeaturePOPCNT,
 485   FeatureAES,
 486   FeaturePCLMUL,
 487   FeatureXSAVE,
 488   FeatureXSAVEOPT,
 489   FeatureRDRAND,
 490   FeatureF16C,
 491   FeatureFSGSBase,
 492   FeatureMOVBE,
 493   FeatureLZCNT,
 494   FeatureBMI,
 495   FeatureBMI2,
 496   FeatureFMA,
 497   FeatureRTM,
 498   FeatureHLE,
 499   FeatureADX,
 500   FeatureRDSEED,
 501   FeatureSlowIncDec,
 502   FeatureMPX,
 503   FeatureXSAVEC,
 504   FeatureXSAVES
 505 ]>;
 506 def : SkylakeProc<"skylake">;
 507 def : SkylakeProc<"skx">; // Legacy alias.
 508
 509
 510 // AMD CPUs.
 511
 512 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 513 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 514 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 515 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 516                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 517 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 518                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 519 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 520                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 521 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 522                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 523 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 524                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 525 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 526                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 527                                FeatureSlowSHLD]>;
 528 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 529                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 530                                FeatureSlowSHLD]>;
 531 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 532                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 533                                FeatureSlowSHLD]>;
 534 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 535                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 536                                FeatureSlowSHLD]>;
 537 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 538                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 539                                FeatureSlowSHLD]>;
 540 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 541                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 542                                FeatureSlowSHLD]>;
 543 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 544                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 545                                FeatureSlowSHLD]>;
 546 def : Proc<"amdfam10",        [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 547                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 548                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 549 def : Proc<"barcelona",       [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 550                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 551                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 552
 553 // Bobcat
 554 def : Proc<"btver1", [
 555   FeatureMMX,
 556   FeatureSSSE3,
 557   FeatureSSE4A,
 558   FeatureFXSR,
 559   FeatureCMPXCHG16B,
 560   FeaturePRFCHW,
 561   FeatureLZCNT,
 562   FeaturePOPCNT,
 563   FeatureXSAVE,
 564   FeatureSlowSHLD
 565 ]>;
 566
 567 // Jaguar
 568 def : ProcessorModel<"btver2", BtVer2Model, [
 569   FeatureMMX,
 570   FeatureAVX,
 571   FeatureFXSR,
 572   FeatureSSE4A,
 573   FeatureCMPXCHG16B,
 574   FeaturePRFCHW,
 575   FeatureAES,
 576   FeaturePCLMUL,
 577   FeatureBMI,
 578   FeatureF16C,
 579   FeatureMOVBE,
 580   FeatureLZCNT,
 581   FeaturePOPCNT,
 582   FeatureXSAVE,
 583   FeatureXSAVEOPT,
 584   FeatureSlowSHLD
 585 ]>;
 586
 587 // Bulldozer
 588 def : Proc<"bdver1", [
 589   FeatureXOP,
 590   FeatureFMA4,
 591   FeatureCMPXCHG16B,
 592   FeatureAES,
 593   FeaturePRFCHW,
 594   FeaturePCLMUL,
 595   FeatureMMX,
 596   FeatureAVX,
 597   FeatureFXSR,
 598   FeatureSSE4A,
 599   FeatureLZCNT,
 600   FeaturePOPCNT,
 601   FeatureXSAVE,
 602   FeatureSlowSHLD
 603 ]>;
 604 // Piledriver
 605 def : Proc<"bdver2", [
 606   FeatureXOP,
 607   FeatureFMA4,
 608   FeatureCMPXCHG16B,
 609   FeatureAES,
 610   FeaturePRFCHW,
 611   FeaturePCLMUL,
 612   FeatureMMX,
 613   FeatureAVX,
 614   FeatureFXSR,
 615   FeatureSSE4A,
 616   FeatureF16C,
 617   FeatureLZCNT,
 618   FeaturePOPCNT,
 619   FeatureXSAVE,
 620   FeatureBMI,
 621   FeatureTBM,
 622   FeatureFMA,
 623   FeatureSlowSHLD
 624 ]>;
 625
 626 // Steamroller
 627 def : Proc<"bdver3", [
 628   FeatureXOP,
 629   FeatureFMA4,
 630   FeatureCMPXCHG16B,
 631   FeatureAES,
 632   FeaturePRFCHW,
 633   FeaturePCLMUL,
 634   FeatureMMX,
 635   FeatureAVX,
 636   FeatureFXSR,
 637   FeatureSSE4A,
 638   FeatureF16C,
 639   FeatureLZCNT,
 640   FeaturePOPCNT,
 641   FeatureXSAVE,
 642   FeatureBMI,
 643   FeatureTBM,
 644   FeatureFMA,
 645   FeatureXSAVEOPT,
 646   FeatureSlowSHLD,
 647   FeatureFSGSBase
 648 ]>;
 649
 650 // Excavator
 651 def : Proc<"bdver4", [
 652   FeatureMMX,
 653   FeatureAVX2,
 654   FeatureFXSR,
 655   FeatureXOP,
 656   FeatureFMA4,
 657   FeatureCMPXCHG16B,
 658   FeatureAES,
 659   FeaturePRFCHW,
 660   FeaturePCLMUL,
 661   FeatureF16C,
 662   FeatureLZCNT,
 663   FeaturePOPCNT,
 664   FeatureXSAVE,
 665   FeatureBMI,
 666   FeatureBMI2,
 667   FeatureTBM,
 668   FeatureFMA,
 669   FeatureXSAVEOPT,
 670   FeatureFSGSBase
 671 ]>;
 672
 673 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 674
 675 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 676 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 677 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 678 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
 679
 680 // We also provide a generic 64-bit specific x86 processor model which tries to
 681 // be good for modern chips without enabling instruction set encodings past the
 682 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 683 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 684 //
 685 // We currently use the Sandy Bridge model as the default scheduling model as
 686 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 687 // covers a huge swath of x86 processors. If there are specific scheduling
 688 // knobs which need to be tuned differently for AMD chips, we might consider
 689 // forming a common base for them.
 690 def : ProcessorModel<"x86-64", SandyBridgeModel,
 691                      [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
 692                       FeatureSlowBTMem ]>;
 693
 694 //===----------------------------------------------------------------------===//
 695 // Register File Description
 696 //===----------------------------------------------------------------------===//
 697
 698 include "X86RegisterInfo.td"
 699
 700 //===----------------------------------------------------------------------===//
 701 // Instruction Descriptions
 702 //===----------------------------------------------------------------------===//
 703
 704 include "X86InstrInfo.td"
 705
 706 def X86InstrInfo : InstrInfo;
 707
 708 //===----------------------------------------------------------------------===//
 709 // Calling Conventions
 710 //===----------------------------------------------------------------------===//
 711
 712 include "X86CallingConv.td"
 713
 714
 715 //===----------------------------------------------------------------------===//
 716 // Assembly Parser
 717 //===----------------------------------------------------------------------===//
 718
 719 def ATTAsmParser : AsmParser {
 720   string AsmParserClassName = "AsmParser";
 721 }
 722
 723 def ATTAsmParserVariant : AsmParserVariant {
 724   int Variant = 0;
 725
 726   // Variant name.
 727   string Name = "att";
 728
 729   // Discard comments in assembly strings.
 730   string CommentDelimiter = "#";
 731
 732   // Recognize hard coded registers.
 733   string RegisterPrefix = "%";
 734 }
 735
 736 def IntelAsmParserVariant : AsmParserVariant {
 737   int Variant = 1;
 738
 739   // Variant name.
 740   string Name = "intel";
 741
 742   // Discard comments in assembly strings.
 743   string CommentDelimiter = ";";
 744
 745   // Recognize hard coded registers.
 746   string RegisterPrefix = "";
 747 }
 748
 749 //===----------------------------------------------------------------------===//
 750 // Assembly Printers
 751 //===----------------------------------------------------------------------===//
 752
 753 // The X86 target supports two different syntaxes for emitting machine code.
 754 // This is controlled by the -x86-asm-syntax={att|intel}
 755 def ATTAsmWriter : AsmWriter {
 756   string AsmWriterClassName  = "ATTInstPrinter";
 757   int Variant = 0;
 758 }
 759 def IntelAsmWriter : AsmWriter {
 760   string AsmWriterClassName  = "IntelInstPrinter";
 761   int Variant = 1;
 762 }
 763
 764 def X86 : Target {
 765   // Information about the instructions...
 766   let InstructionSet = X86InstrInfo;
 767   let AssemblyParsers = [ATTAsmParser];
 768   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 769   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 770 }